Index: llvm/lib/Transforms/Utils/SimplifyCFG.cpp
===================================================================
--- llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+++ llvm/lib/Transforms/Utils/SimplifyCFG.cpp
@@ -1995,6 +1995,26 @@
   return nullptr;
 }
 
+/// Check if the cost of the necessary selects will be within the given
+/// budget.
+static bool selectCostsWithinBudget(BasicBlock *BB, BasicBlock *ThenBB,
+                                    BasicBlock *EndBB, int BudgetRemaining,
+                                    const TargetTransformInfo &TTI) {
+  TargetTransformInfo::TargetCostKind CostKind =
+    BB->getParent()->hasMinSize()
+    ? TargetTransformInfo::TCK_CodeSize
+    : TargetTransformInfo::TCK_SizeAndLatency;
+  for (PHINode &PN : EndBB->phis()) {
+    Value *OrigV = PN.getIncomingValueForBlock(BB);
+    Value *ThenV = PN.getIncomingValueForBlock(ThenBB);
+    if (OrigV != ThenV)
+      BudgetRemaining -=
+          TTI.getCmpSelInstrCost(Instruction::Select, PN.getType(), nullptr,
+                                 CostKind);
+  }
+  return BudgetRemaining >= 0;
+}
+
 /// Speculate a conditional basic block flattening the CFG.
 ///
 /// Note that this is a very risky transform currently. Speculating
@@ -2042,24 +2062,11 @@
   BasicBlock *BB = BI->getParent();
   BasicBlock *EndBB = ThenBB->getTerminator()->getSuccessor(0);
 
-  TargetTransformInfo::TargetCostKind CostKind =
-    BI->getFunction()->hasMinSize()
-    ? TargetTransformInfo::TCK_CodeSize
-    : TargetTransformInfo::TCK_SizeAndLatency;
   // Check how expensive it will be to insert the necessary selects.
   int BudgetRemaining =
-    PHINodeFoldingThreshold * TargetTransformInfo::TCC_Basic;
-  for (PHINode &PN : EndBB->phis()) {
-    unsigned OrigI = PN.getBasicBlockIndex(BB);
-    unsigned ThenI = PN.getBasicBlockIndex(ThenBB);
-    Value *OrigV = PN.getIncomingValue(OrigI);
-    Value *ThenV = PN.getIncomingValue(ThenI);
-    if (OrigV != ThenV)
-      BudgetRemaining -=
-          TTI.getCmpSelInstrCost(Instruction::Select, PN.getType(), nullptr,
-                                 CostKind);
-  }
-  if (BudgetRemaining < 0)
+      PHINodeFoldingThreshold * TargetTransformInfo::TCC_Basic;
+
+  if (!selectCostsWithinBudget(BB, ThenBB, EndBB, BudgetRemaining, TTI))
     return false;
 
   // If ThenBB is actually on the false edge of the conditional branch, remember
@@ -2522,6 +2529,10 @@
   if (IfBlock2)
     hoistAllInstructionsInto(DomBlock, InsertPt, IfBlock2);
 
+  // Check whether the cost of the required selects will surpass the budget.
+  if (!selectCostsWithinBudget(IfTrue, IfFalse, BB, BudgetRemaining, TTI))
+    return Changed;
+
   // Propagate fast-math-flags from phi nodes to replacement selects.
   IRBuilder<>::FastMathFlagGuard FMFGuard(Builder);
   while (PHINode *PN = dyn_cast<PHINode>(BB->begin())) {
Index: llvm/test/Transforms/PGOProfile/chr.ll
===================================================================
--- llvm/test/Transforms/PGOProfile/chr.ll
+++ llvm/test/Transforms/PGOProfile/chr.ll
@@ -472,10 +472,10 @@
 ; CHECK-NEXT:    [[TMP15:%.*]] = icmp eq i32 [[TMP14]], 0
 ; CHECK-NEXT:    [[SUM4_NONCHR_V:%.*]] = select i1 [[TMP15]], i32 44, i32 88
 ; CHECK-NEXT:    [[SUM4_NONCHR:%.*]] = add i32 [[SUM2_NONCHR]], [[SUM4_NONCHR_V]]
-; CHECK-NEXT:    [[SUM5_NONCHR:%.*]] = select i1 [[TMP13]], i32 [[SUM2_NONCHR]], i32 [[SUM4_NONCHR]], !prof !16
-; CHECK-NEXT:    br label [[BB3]]
+; CHECK-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[TMP13]], i32 [[SUM2_NONCHR]], i32 [[SUM4_NONCHR]], !prof !16
+; CHECK-NEXT:    ret i32 [[SPEC_SELECT]]
 ; CHECK:       bb3:
-; CHECK-NEXT:    [[SUM6:%.*]] = phi i32 [ [[TMP4]], [[BB0]] ], [ [[SUM0]], [[ENTRY_SPLIT_NONCHR]] ], [ [[SUM5_NONCHR]], [[BB0_NONCHR]] ]
+; CHECK-NEXT:    [[SUM6:%.*]] = phi i32 [ [[TMP4]], [[BB0]] ], [ [[SUM0]], [[ENTRY_SPLIT_NONCHR]] ]
 ; CHECK-NEXT:    ret i32 [[SUM6]]
 ;
 entry:
@@ -572,10 +572,10 @@
 ; CHECK-NEXT:    [[TMP18:%.*]] = icmp eq i32 [[TMP17]], 0
 ; CHECK-NEXT:    [[SUM4_NONCHR_V:%.*]] = select i1 [[TMP18]], i32 44, i32 88
 ; CHECK-NEXT:    [[SUM4_NONCHR:%.*]] = add i32 [[SUM2_NONCHR]], [[SUM4_NONCHR_V]]
-; CHECK-NEXT:    [[SUM5_NONCHR:%.*]] = select i1 [[TMP16]], i32 [[SUM2_NONCHR]], i32 [[SUM4_NONCHR]], !prof !16
-; CHECK-NEXT:    br label [[BB3]]
+; CHECK-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[TMP16]], i32 [[SUM2_NONCHR]], i32 [[SUM4_NONCHR]], !prof !16
+; CHECK-NEXT:    ret i32 [[SPEC_SELECT]]
 ; CHECK:       bb3:
-; CHECK-NEXT:    [[SUM6:%.*]] = phi i32 [ [[TMP7]], [[BB0]] ], [ [[SUM0]], [[ENTRY_SPLIT_NONCHR]] ], [ [[SUM5_NONCHR]], [[BB0_NONCHR]] ]
+; CHECK-NEXT:    [[SUM6:%.*]] = phi i32 [ [[TMP7]], [[BB0]] ], [ [[SUM0]], [[ENTRY_SPLIT_NONCHR]] ]
 ; CHECK-NEXT:    ret i32 [[SUM6]]
 ;
 entry:
@@ -669,10 +669,10 @@
 ; CHECK-NEXT:    [[V12_NONCHR:%.*]] = icmp eq i32 [[V11_NONCHR]], 0
 ; CHECK-NEXT:    [[SUM4_NONCHR_V:%.*]] = select i1 [[V12_NONCHR]], i32 44, i32 88
 ; CHECK-NEXT:    [[SUM4_NONCHR:%.*]] = add i32 [[SUM2_NONCHR]], [[SUM4_NONCHR_V]]
-; CHECK-NEXT:    [[SUM5_NONCHR:%.*]] = select i1 [[V10_NONCHR]], i32 [[SUM2_NONCHR]], i32 [[SUM4_NONCHR]], !prof !16
-; CHECK-NEXT:    br label [[BB3]]
+; CHECK-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[V10_NONCHR]], i32 [[SUM2_NONCHR]], i32 [[SUM4_NONCHR]], !prof !16
+; CHECK-NEXT:    ret i32 [[SPEC_SELECT]]
 ; CHECK:       bb3:
-; CHECK-NEXT:    [[SUM6:%.*]] = phi i32 [ [[V13]], [[BB0]] ], [ [[SUM0]], [[ENTRY_SPLIT_NONCHR]] ], [ [[SUM5_NONCHR]], [[BB0_NONCHR]] ]
+; CHECK-NEXT:    [[SUM6:%.*]] = phi i32 [ [[V13]], [[BB0]] ], [ [[SUM0]], [[ENTRY_SPLIT_NONCHR]] ]
 ; CHECK-NEXT:    ret i32 [[SUM6]]
 ;
 entry:
@@ -1755,10 +1755,10 @@
 ; CHECK-NEXT:    [[TMP10:%.*]] = icmp eq i32 [[TMP9]], 0
 ; CHECK-NEXT:    [[SUM4_NONCHR_V:%.*]] = select i1 [[TMP10]], i32 44, i32 88
 ; CHECK-NEXT:    [[SUM4_NONCHR:%.*]] = add i32 [[SUM2_NONCHR]], [[SUM4_NONCHR_V]]
-; CHECK-NEXT:    [[SUM5_NONCHR:%.*]] = select i1 [[TMP7]], i32 [[SUM2_NONCHR]], i32 [[SUM4_NONCHR]], !prof !16
-; CHECK-NEXT:    br label [[BB3]]
+; CHECK-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[TMP7]], i32 [[SUM2_NONCHR]], i32 [[SUM4_NONCHR]], !prof !16
+; CHECK-NEXT:    ret i32 [[SPEC_SELECT]]
 ; CHECK:       bb3:
-; CHECK-NEXT:    [[SUM6:%.*]] = phi i32 [ [[TMP4]], [[BB0]] ], [ [[SUM0]], [[ENTRY_SPLIT_NONCHR]] ], [ [[SUM5_NONCHR]], [[BB0_NONCHR]] ]
+; CHECK-NEXT:    [[SUM6:%.*]] = phi i32 [ [[TMP4]], [[BB0]] ], [ [[SUM0]], [[ENTRY_SPLIT_NONCHR]] ]
 ; CHECK-NEXT:    ret i32 [[SUM6]]
 ;
 entry:
Index: llvm/test/Transforms/SimplifyCFG/ARM/phi-eliminate.ll
===================================================================
--- llvm/test/Transforms/SimplifyCFG/ARM/phi-eliminate.ll
+++ llvm/test/Transforms/SimplifyCFG/ARM/phi-eliminate.ll
@@ -15,11 +15,17 @@
 ; CHECK-V8M-TWO-FOLD-4-NEXT:    [[IAJAK:%.*]] = add i32 [[IAJ]], [[K:%.*]]
 ; CHECK-V8M-TWO-FOLD-4-NEXT:    [[IXJ:%.*]] = xor i32 [[I]], [[J]]
 ; CHECK-V8M-TWO-FOLD-4-NEXT:    [[IXJXK:%.*]] = xor i32 [[IXJ]], [[K]]
-; CHECK-V8M-TWO-FOLD-4-NEXT:    [[WP:%.*]] = select i1 [[B:%.*]], i32 [[IAJAK]], i32 [[IXJXK]]
+; CHECK-V8M-TWO-FOLD-4-NEXT:    br i1 [[B:%.*]], label [[P:%.*]], label [[Q:%.*]]
+; CHECK-V8M-TWO-FOLD-4:       P:
+; CHECK-V8M-TWO-FOLD-4-NEXT:    br label [[N:%.*]]
+; CHECK-V8M-TWO-FOLD-4:       Q:
+; CHECK-V8M-TWO-FOLD-4-NEXT:    br label [[N]]
+; CHECK-V8M-TWO-FOLD-4:       N:
+; CHECK-V8M-TWO-FOLD-4-NEXT:    [[WP:%.*]] = phi i32 [ [[IAJAK]], [[P]] ], [ [[IXJXK]], [[Q]] ]
 ; CHECK-V8M-TWO-FOLD-4-NEXT:    [[WP2:%.*]] = add i32 [[WP]], [[WP]]
 ; CHECK-V8M-TWO-FOLD-4-NEXT:    br label [[M]]
 ; CHECK-V8M-TWO-FOLD-4:       M:
-; CHECK-V8M-TWO-FOLD-4-NEXT:    [[W:%.*]] = phi i32 [ [[WP2]], [[O]] ], [ 2, [[ENTRY:%.*]] ]
+; CHECK-V8M-TWO-FOLD-4-NEXT:    [[W:%.*]] = phi i32 [ [[WP2]], [[N]] ], [ 2, [[ENTRY:%.*]] ]
 ; CHECK-V8M-TWO-FOLD-4-NEXT:    [[R:%.*]] = add i32 [[W]], 1
 ; CHECK-V8M-TWO-FOLD-4-NEXT:    ret i32 [[R]]
 ;
@@ -31,11 +37,17 @@
 ; CHECK-V8A-TWO-FOLD-4-NEXT:    [[IAJAK:%.*]] = add i32 [[IAJ]], [[K:%.*]]
 ; CHECK-V8A-TWO-FOLD-4-NEXT:    [[IXJ:%.*]] = xor i32 [[I]], [[J]]
 ; CHECK-V8A-TWO-FOLD-4-NEXT:    [[IXJXK:%.*]] = xor i32 [[IXJ]], [[K]]
-; CHECK-V8A-TWO-FOLD-4-NEXT:    [[WP:%.*]] = select i1 [[B:%.*]], i32 [[IAJAK]], i32 [[IXJXK]]
+; CHECK-V8A-TWO-FOLD-4-NEXT:    br i1 [[B:%.*]], label [[P:%.*]], label [[Q:%.*]]
+; CHECK-V8A-TWO-FOLD-4:       P:
+; CHECK-V8A-TWO-FOLD-4-NEXT:    br label [[N:%.*]]
+; CHECK-V8A-TWO-FOLD-4:       Q:
+; CHECK-V8A-TWO-FOLD-4-NEXT:    br label [[N]]
+; CHECK-V8A-TWO-FOLD-4:       N:
+; CHECK-V8A-TWO-FOLD-4-NEXT:    [[WP:%.*]] = phi i32 [ [[IAJAK]], [[P]] ], [ [[IXJXK]], [[Q]] ]
 ; CHECK-V8A-TWO-FOLD-4-NEXT:    [[WP2:%.*]] = add i32 [[WP]], [[WP]]
 ; CHECK-V8A-TWO-FOLD-4-NEXT:    br label [[M]]
 ; CHECK-V8A-TWO-FOLD-4:       M:
-; CHECK-V8A-TWO-FOLD-4-NEXT:    [[W:%.*]] = phi i32 [ [[WP2]], [[O]] ], [ 2, [[ENTRY:%.*]] ]
+; CHECK-V8A-TWO-FOLD-4-NEXT:    [[W:%.*]] = phi i32 [ [[WP2]], [[N]] ], [ 2, [[ENTRY:%.*]] ]
 ; CHECK-V8A-TWO-FOLD-4-NEXT:    [[R:%.*]] = add i32 [[W]], 1
 ; CHECK-V8A-TWO-FOLD-4-NEXT:    ret i32 [[R]]
 ;
@@ -79,8 +91,8 @@
 ; CHECK-V8M-TWO-FOLD-6-NEXT:    [[IXJXK:%.*]] = xor i32 [[IXJ]], [[K]]
 ; CHECK-V8M-TWO-FOLD-6-NEXT:    [[WP:%.*]] = select i1 [[B:%.*]], i32 [[IAJAK]], i32 [[IXJXK]]
 ; CHECK-V8M-TWO-FOLD-6-NEXT:    [[WP2:%.*]] = add i32 [[WP]], [[WP]]
-; CHECK-V8M-TWO-FOLD-6-NEXT:    [[W:%.*]] = select i1 [[A:%.*]], i32 2, i32 [[WP2]]
-; CHECK-V8M-TWO-FOLD-6-NEXT:    [[R:%.*]] = add i32 [[W]], 1
+; CHECK-V8M-TWO-FOLD-6-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[A:%.*]], i32 2, i32 [[WP2]]
+; CHECK-V8M-TWO-FOLD-6-NEXT:    [[R:%.*]] = add i32 [[SPEC_SELECT]], 1
 ; CHECK-V8M-TWO-FOLD-6-NEXT:    ret i32 [[R]]
 ;
 ; CHECK-V8A-TWO-FOLD-6-LABEL: @test_i32(
@@ -91,8 +103,8 @@
 ; CHECK-V8A-TWO-FOLD-6-NEXT:    [[IXJXK:%.*]] = xor i32 [[IXJ]], [[K]]
 ; CHECK-V8A-TWO-FOLD-6-NEXT:    [[WP:%.*]] = select i1 [[B:%.*]], i32 [[IAJAK]], i32 [[IXJXK]]
 ; CHECK-V8A-TWO-FOLD-6-NEXT:    [[WP2:%.*]] = add i32 [[WP]], [[WP]]
-; CHECK-V8A-TWO-FOLD-6-NEXT:    [[W:%.*]] = select i1 [[A:%.*]], i32 2, i32 [[WP2]]
-; CHECK-V8A-TWO-FOLD-6-NEXT:    [[R:%.*]] = add i32 [[W]], 1
+; CHECK-V8A-TWO-FOLD-6-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[A:%.*]], i32 2, i32 [[WP2]]
+; CHECK-V8A-TWO-FOLD-6-NEXT:    [[R:%.*]] = add i32 [[SPEC_SELECT]], 1
 ; CHECK-V8A-TWO-FOLD-6-NEXT:    ret i32 [[R]]
 ;
 entry:
@@ -126,11 +138,17 @@
 ; CHECK-V8M-TWO-FOLD-4-NEXT:    [[IAJAK:%.*]] = add i32 [[IAJ]], [[K:%.*]]
 ; CHECK-V8M-TWO-FOLD-4-NEXT:    [[IXJ:%.*]] = xor i32 [[I]], [[J]]
 ; CHECK-V8M-TWO-FOLD-4-NEXT:    [[IXJXK:%.*]] = xor i32 [[IXJ]], [[K]]
-; CHECK-V8M-TWO-FOLD-4-NEXT:    [[WP:%.*]] = select i1 [[B:%.*]], i32 [[IAJAK]], i32 [[IXJXK]]
+; CHECK-V8M-TWO-FOLD-4-NEXT:    br i1 [[B:%.*]], label [[P:%.*]], label [[Q:%.*]]
+; CHECK-V8M-TWO-FOLD-4:       P:
+; CHECK-V8M-TWO-FOLD-4-NEXT:    br label [[N:%.*]]
+; CHECK-V8M-TWO-FOLD-4:       Q:
+; CHECK-V8M-TWO-FOLD-4-NEXT:    br label [[N]]
+; CHECK-V8M-TWO-FOLD-4:       N:
+; CHECK-V8M-TWO-FOLD-4-NEXT:    [[WP:%.*]] = phi i32 [ [[IAJAK]], [[P]] ], [ [[IXJXK]], [[Q]] ]
 ; CHECK-V8M-TWO-FOLD-4-NEXT:    [[WP2:%.*]] = add i32 [[WP]], [[WP]]
 ; CHECK-V8M-TWO-FOLD-4-NEXT:    br label [[M]]
 ; CHECK-V8M-TWO-FOLD-4:       M:
-; CHECK-V8M-TWO-FOLD-4-NEXT:    [[W:%.*]] = phi i32 [ [[WP2]], [[O]] ], [ 2, [[ENTRY:%.*]] ]
+; CHECK-V8M-TWO-FOLD-4-NEXT:    [[W:%.*]] = phi i32 [ [[WP2]], [[N]] ], [ 2, [[ENTRY:%.*]] ]
 ; CHECK-V8M-TWO-FOLD-4-NEXT:    [[R:%.*]] = add i32 [[W]], 1
 ; CHECK-V8M-TWO-FOLD-4-NEXT:    ret i32 [[R]]
 ;
@@ -142,11 +160,17 @@
 ; CHECK-V8A-TWO-FOLD-4-NEXT:    [[IAJAK:%.*]] = add i32 [[IAJ]], [[K:%.*]]
 ; CHECK-V8A-TWO-FOLD-4-NEXT:    [[IXJ:%.*]] = xor i32 [[I]], [[J]]
 ; CHECK-V8A-TWO-FOLD-4-NEXT:    [[IXJXK:%.*]] = xor i32 [[IXJ]], [[K]]
-; CHECK-V8A-TWO-FOLD-4-NEXT:    [[WP:%.*]] = select i1 [[B:%.*]], i32 [[IAJAK]], i32 [[IXJXK]]
+; CHECK-V8A-TWO-FOLD-4-NEXT:    br i1 [[B:%.*]], label [[P:%.*]], label [[Q:%.*]]
+; CHECK-V8A-TWO-FOLD-4:       P:
+; CHECK-V8A-TWO-FOLD-4-NEXT:    br label [[N:%.*]]
+; CHECK-V8A-TWO-FOLD-4:       Q:
+; CHECK-V8A-TWO-FOLD-4-NEXT:    br label [[N]]
+; CHECK-V8A-TWO-FOLD-4:       N:
+; CHECK-V8A-TWO-FOLD-4-NEXT:    [[WP:%.*]] = phi i32 [ [[IAJAK]], [[P]] ], [ [[IXJXK]], [[Q]] ]
 ; CHECK-V8A-TWO-FOLD-4-NEXT:    [[WP2:%.*]] = add i32 [[WP]], [[WP]]
 ; CHECK-V8A-TWO-FOLD-4-NEXT:    br label [[M]]
 ; CHECK-V8A-TWO-FOLD-4:       M:
-; CHECK-V8A-TWO-FOLD-4-NEXT:    [[W:%.*]] = phi i32 [ [[WP2]], [[O]] ], [ 2, [[ENTRY:%.*]] ]
+; CHECK-V8A-TWO-FOLD-4-NEXT:    [[W:%.*]] = phi i32 [ [[WP2]], [[N]] ], [ 2, [[ENTRY:%.*]] ]
 ; CHECK-V8A-TWO-FOLD-4-NEXT:    [[R:%.*]] = add i32 [[W]], 1
 ; CHECK-V8A-TWO-FOLD-4-NEXT:    ret i32 [[R]]
 ;
@@ -158,11 +182,17 @@
 ; CHECK-V8M-TWO-FOLD-5-NEXT:    [[IAJAK:%.*]] = add i32 [[IAJ]], [[K:%.*]]
 ; CHECK-V8M-TWO-FOLD-5-NEXT:    [[IXJ:%.*]] = xor i32 [[I]], [[J]]
 ; CHECK-V8M-TWO-FOLD-5-NEXT:    [[IXJXK:%.*]] = xor i32 [[IXJ]], [[K]]
-; CHECK-V8M-TWO-FOLD-5-NEXT:    [[WP:%.*]] = select i1 [[B:%.*]], i32 [[IAJAK]], i32 [[IXJXK]]
+; CHECK-V8M-TWO-FOLD-5-NEXT:    br i1 [[B:%.*]], label [[P:%.*]], label [[Q:%.*]]
+; CHECK-V8M-TWO-FOLD-5:       P:
+; CHECK-V8M-TWO-FOLD-5-NEXT:    br label [[N:%.*]]
+; CHECK-V8M-TWO-FOLD-5:       Q:
+; CHECK-V8M-TWO-FOLD-5-NEXT:    br label [[N]]
+; CHECK-V8M-TWO-FOLD-5:       N:
+; CHECK-V8M-TWO-FOLD-5-NEXT:    [[WP:%.*]] = phi i32 [ [[IAJAK]], [[P]] ], [ [[IXJXK]], [[Q]] ]
 ; CHECK-V8M-TWO-FOLD-5-NEXT:    [[WP2:%.*]] = add i32 [[WP]], [[WP]]
 ; CHECK-V8M-TWO-FOLD-5-NEXT:    br label [[M]]
 ; CHECK-V8M-TWO-FOLD-5:       M:
-; CHECK-V8M-TWO-FOLD-5-NEXT:    [[W:%.*]] = phi i32 [ [[WP2]], [[O]] ], [ 2, [[ENTRY:%.*]] ]
+; CHECK-V8M-TWO-FOLD-5-NEXT:    [[W:%.*]] = phi i32 [ [[WP2]], [[N]] ], [ 2, [[ENTRY:%.*]] ]
 ; CHECK-V8M-TWO-FOLD-5-NEXT:    [[R:%.*]] = add i32 [[W]], 1
 ; CHECK-V8M-TWO-FOLD-5-NEXT:    ret i32 [[R]]
 ;
@@ -190,8 +220,8 @@
 ; CHECK-V8M-TWO-FOLD-6-NEXT:    [[IXJXK:%.*]] = xor i32 [[IXJ]], [[K]]
 ; CHECK-V8M-TWO-FOLD-6-NEXT:    [[WP:%.*]] = select i1 [[B:%.*]], i32 [[IAJAK]], i32 [[IXJXK]]
 ; CHECK-V8M-TWO-FOLD-6-NEXT:    [[WP2:%.*]] = add i32 [[WP]], [[WP]]
-; CHECK-V8M-TWO-FOLD-6-NEXT:    [[W:%.*]] = select i1 [[A:%.*]], i32 2, i32 [[WP2]]
-; CHECK-V8M-TWO-FOLD-6-NEXT:    [[R:%.*]] = add i32 [[W]], 1
+; CHECK-V8M-TWO-FOLD-6-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[A:%.*]], i32 2, i32 [[WP2]]
+; CHECK-V8M-TWO-FOLD-6-NEXT:    [[R:%.*]] = add i32 [[SPEC_SELECT]], 1
 ; CHECK-V8M-TWO-FOLD-6-NEXT:    ret i32 [[R]]
 ;
 ; CHECK-V8A-TWO-FOLD-6-LABEL: @test_i32_minsize(
@@ -202,8 +232,8 @@
 ; CHECK-V8A-TWO-FOLD-6-NEXT:    [[IXJXK:%.*]] = xor i32 [[IXJ]], [[K]]
 ; CHECK-V8A-TWO-FOLD-6-NEXT:    [[WP:%.*]] = select i1 [[B:%.*]], i32 [[IAJAK]], i32 [[IXJXK]]
 ; CHECK-V8A-TWO-FOLD-6-NEXT:    [[WP2:%.*]] = add i32 [[WP]], [[WP]]
-; CHECK-V8A-TWO-FOLD-6-NEXT:    [[W:%.*]] = select i1 [[A:%.*]], i32 2, i32 [[WP2]]
-; CHECK-V8A-TWO-FOLD-6-NEXT:    [[R:%.*]] = add i32 [[W]], 1
+; CHECK-V8A-TWO-FOLD-6-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[A:%.*]], i32 2, i32 [[WP2]]
+; CHECK-V8A-TWO-FOLD-6-NEXT:    [[R:%.*]] = add i32 [[SPEC_SELECT]], 1
 ; CHECK-V8A-TWO-FOLD-6-NEXT:    ret i32 [[R]]
 ;
 entry:
@@ -237,11 +267,17 @@
 ; CHECK-V8M-TWO-FOLD-4-NEXT:    [[IAJAK:%.*]] = add i64 [[IAJ]], [[K:%.*]]
 ; CHECK-V8M-TWO-FOLD-4-NEXT:    [[IXJ:%.*]] = xor i64 [[I]], [[J]]
 ; CHECK-V8M-TWO-FOLD-4-NEXT:    [[IXJXK:%.*]] = xor i64 [[IXJ]], [[K]]
-; CHECK-V8M-TWO-FOLD-4-NEXT:    [[WP:%.*]] = select i1 [[B:%.*]], i64 [[IAJAK]], i64 [[IXJXK]]
+; CHECK-V8M-TWO-FOLD-4-NEXT:    br i1 [[B:%.*]], label [[P:%.*]], label [[Q:%.*]]
+; CHECK-V8M-TWO-FOLD-4:       P:
+; CHECK-V8M-TWO-FOLD-4-NEXT:    br label [[N:%.*]]
+; CHECK-V8M-TWO-FOLD-4:       Q:
+; CHECK-V8M-TWO-FOLD-4-NEXT:    br label [[N]]
+; CHECK-V8M-TWO-FOLD-4:       N:
+; CHECK-V8M-TWO-FOLD-4-NEXT:    [[WP:%.*]] = phi i64 [ [[IAJAK]], [[P]] ], [ [[IXJXK]], [[Q]] ]
 ; CHECK-V8M-TWO-FOLD-4-NEXT:    [[WP2:%.*]] = add i64 [[WP]], [[WP]]
 ; CHECK-V8M-TWO-FOLD-4-NEXT:    br label [[M]]
 ; CHECK-V8M-TWO-FOLD-4:       M:
-; CHECK-V8M-TWO-FOLD-4-NEXT:    [[W:%.*]] = phi i64 [ [[WP2]], [[O]] ], [ 2, [[ENTRY:%.*]] ]
+; CHECK-V8M-TWO-FOLD-4-NEXT:    [[W:%.*]] = phi i64 [ [[WP2]], [[N]] ], [ 2, [[ENTRY:%.*]] ]
 ; CHECK-V8M-TWO-FOLD-4-NEXT:    [[R:%.*]] = add i64 [[W]], 1
 ; CHECK-V8M-TWO-FOLD-4-NEXT:    ret i64 [[R]]
 ;
@@ -253,11 +289,17 @@
 ; CHECK-V8A-TWO-FOLD-4-NEXT:    [[IAJAK:%.*]] = add i64 [[IAJ]], [[K:%.*]]
 ; CHECK-V8A-TWO-FOLD-4-NEXT:    [[IXJ:%.*]] = xor i64 [[I]], [[J]]
 ; CHECK-V8A-TWO-FOLD-4-NEXT:    [[IXJXK:%.*]] = xor i64 [[IXJ]], [[K]]
-; CHECK-V8A-TWO-FOLD-4-NEXT:    [[WP:%.*]] = select i1 [[B:%.*]], i64 [[IAJAK]], i64 [[IXJXK]]
+; CHECK-V8A-TWO-FOLD-4-NEXT:    br i1 [[B:%.*]], label [[P:%.*]], label [[Q:%.*]]
+; CHECK-V8A-TWO-FOLD-4:       P:
+; CHECK-V8A-TWO-FOLD-4-NEXT:    br label [[N:%.*]]
+; CHECK-V8A-TWO-FOLD-4:       Q:
+; CHECK-V8A-TWO-FOLD-4-NEXT:    br label [[N]]
+; CHECK-V8A-TWO-FOLD-4:       N:
+; CHECK-V8A-TWO-FOLD-4-NEXT:    [[WP:%.*]] = phi i64 [ [[IAJAK]], [[P]] ], [ [[IXJXK]], [[Q]] ]
 ; CHECK-V8A-TWO-FOLD-4-NEXT:    [[WP2:%.*]] = add i64 [[WP]], [[WP]]
 ; CHECK-V8A-TWO-FOLD-4-NEXT:    br label [[M]]
 ; CHECK-V8A-TWO-FOLD-4:       M:
-; CHECK-V8A-TWO-FOLD-4-NEXT:    [[W:%.*]] = phi i64 [ [[WP2]], [[O]] ], [ 2, [[ENTRY:%.*]] ]
+; CHECK-V8A-TWO-FOLD-4-NEXT:    [[W:%.*]] = phi i64 [ [[WP2]], [[N]] ], [ 2, [[ENTRY:%.*]] ]
 ; CHECK-V8A-TWO-FOLD-4-NEXT:    [[R:%.*]] = add i64 [[W]], 1
 ; CHECK-V8A-TWO-FOLD-4-NEXT:    ret i64 [[R]]
 ;
@@ -301,8 +343,8 @@
 ; CHECK-V8M-TWO-FOLD-6-NEXT:    [[IXJXK:%.*]] = xor i64 [[IXJ]], [[K]]
 ; CHECK-V8M-TWO-FOLD-6-NEXT:    [[WP:%.*]] = select i1 [[B:%.*]], i64 [[IAJAK]], i64 [[IXJXK]]
 ; CHECK-V8M-TWO-FOLD-6-NEXT:    [[WP2:%.*]] = add i64 [[WP]], [[WP]]
-; CHECK-V8M-TWO-FOLD-6-NEXT:    [[W:%.*]] = select i1 [[A:%.*]], i64 2, i64 [[WP2]]
-; CHECK-V8M-TWO-FOLD-6-NEXT:    [[R:%.*]] = add i64 [[W]], 1
+; CHECK-V8M-TWO-FOLD-6-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[A:%.*]], i64 2, i64 [[WP2]]
+; CHECK-V8M-TWO-FOLD-6-NEXT:    [[R:%.*]] = add i64 [[SPEC_SELECT]], 1
 ; CHECK-V8M-TWO-FOLD-6-NEXT:    ret i64 [[R]]
 ;
 ; CHECK-V8A-TWO-FOLD-6-LABEL: @test_i64(
@@ -313,8 +355,8 @@
 ; CHECK-V8A-TWO-FOLD-6-NEXT:    [[IXJXK:%.*]] = xor i64 [[IXJ]], [[K]]
 ; CHECK-V8A-TWO-FOLD-6-NEXT:    [[WP:%.*]] = select i1 [[B:%.*]], i64 [[IAJAK]], i64 [[IXJXK]]
 ; CHECK-V8A-TWO-FOLD-6-NEXT:    [[WP2:%.*]] = add i64 [[WP]], [[WP]]
-; CHECK-V8A-TWO-FOLD-6-NEXT:    [[W:%.*]] = select i1 [[A:%.*]], i64 2, i64 [[WP2]]
-; CHECK-V8A-TWO-FOLD-6-NEXT:    [[R:%.*]] = add i64 [[W]], 1
+; CHECK-V8A-TWO-FOLD-6-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[A:%.*]], i64 2, i64 [[WP2]]
+; CHECK-V8A-TWO-FOLD-6-NEXT:    [[R:%.*]] = add i64 [[SPEC_SELECT]], 1
 ; CHECK-V8A-TWO-FOLD-6-NEXT:    ret i64 [[R]]
 ;
 entry:
@@ -348,11 +390,17 @@
 ; CHECK-V8M-TWO-FOLD-4-NEXT:    [[IAJAK:%.*]] = add i64 [[IAJ]], [[K:%.*]]
 ; CHECK-V8M-TWO-FOLD-4-NEXT:    [[IXJ:%.*]] = xor i64 [[I]], [[J]]
 ; CHECK-V8M-TWO-FOLD-4-NEXT:    [[IXJXK:%.*]] = xor i64 [[IXJ]], [[K]]
-; CHECK-V8M-TWO-FOLD-4-NEXT:    [[WP:%.*]] = select i1 [[B:%.*]], i64 [[IAJAK]], i64 [[IXJXK]]
+; CHECK-V8M-TWO-FOLD-4-NEXT:    br i1 [[B:%.*]], label [[P:%.*]], label [[Q:%.*]]
+; CHECK-V8M-TWO-FOLD-4:       P:
+; CHECK-V8M-TWO-FOLD-4-NEXT:    br label [[N:%.*]]
+; CHECK-V8M-TWO-FOLD-4:       Q:
+; CHECK-V8M-TWO-FOLD-4-NEXT:    br label [[N]]
+; CHECK-V8M-TWO-FOLD-4:       N:
+; CHECK-V8M-TWO-FOLD-4-NEXT:    [[WP:%.*]] = phi i64 [ [[IAJAK]], [[P]] ], [ [[IXJXK]], [[Q]] ]
 ; CHECK-V8M-TWO-FOLD-4-NEXT:    [[WP2:%.*]] = add i64 [[WP]], [[WP]]
 ; CHECK-V8M-TWO-FOLD-4-NEXT:    br label [[M]]
 ; CHECK-V8M-TWO-FOLD-4:       M:
-; CHECK-V8M-TWO-FOLD-4-NEXT:    [[W:%.*]] = phi i64 [ [[WP2]], [[O]] ], [ 2, [[ENTRY:%.*]] ]
+; CHECK-V8M-TWO-FOLD-4-NEXT:    [[W:%.*]] = phi i64 [ [[WP2]], [[N]] ], [ 2, [[ENTRY:%.*]] ]
 ; CHECK-V8M-TWO-FOLD-4-NEXT:    [[R:%.*]] = add i64 [[W]], 1
 ; CHECK-V8M-TWO-FOLD-4-NEXT:    ret i64 [[R]]
 ;
@@ -364,11 +412,17 @@
 ; CHECK-V8A-TWO-FOLD-4-NEXT:    [[IAJAK:%.*]] = add i64 [[IAJ]], [[K:%.*]]
 ; CHECK-V8A-TWO-FOLD-4-NEXT:    [[IXJ:%.*]] = xor i64 [[I]], [[J]]
 ; CHECK-V8A-TWO-FOLD-4-NEXT:    [[IXJXK:%.*]] = xor i64 [[IXJ]], [[K]]
-; CHECK-V8A-TWO-FOLD-4-NEXT:    [[WP:%.*]] = select i1 [[B:%.*]], i64 [[IAJAK]], i64 [[IXJXK]]
+; CHECK-V8A-TWO-FOLD-4-NEXT:    br i1 [[B:%.*]], label [[P:%.*]], label [[Q:%.*]]
+; CHECK-V8A-TWO-FOLD-4:       P:
+; CHECK-V8A-TWO-FOLD-4-NEXT:    br label [[N:%.*]]
+; CHECK-V8A-TWO-FOLD-4:       Q:
+; CHECK-V8A-TWO-FOLD-4-NEXT:    br label [[N]]
+; CHECK-V8A-TWO-FOLD-4:       N:
+; CHECK-V8A-TWO-FOLD-4-NEXT:    [[WP:%.*]] = phi i64 [ [[IAJAK]], [[P]] ], [ [[IXJXK]], [[Q]] ]
 ; CHECK-V8A-TWO-FOLD-4-NEXT:    [[WP2:%.*]] = add i64 [[WP]], [[WP]]
 ; CHECK-V8A-TWO-FOLD-4-NEXT:    br label [[M]]
 ; CHECK-V8A-TWO-FOLD-4:       M:
-; CHECK-V8A-TWO-FOLD-4-NEXT:    [[W:%.*]] = phi i64 [ [[WP2]], [[O]] ], [ 2, [[ENTRY:%.*]] ]
+; CHECK-V8A-TWO-FOLD-4-NEXT:    [[W:%.*]] = phi i64 [ [[WP2]], [[N]] ], [ 2, [[ENTRY:%.*]] ]
 ; CHECK-V8A-TWO-FOLD-4-NEXT:    [[R:%.*]] = add i64 [[W]], 1
 ; CHECK-V8A-TWO-FOLD-4-NEXT:    ret i64 [[R]]
 ;
@@ -380,11 +434,17 @@
 ; CHECK-V8M-TWO-FOLD-5-NEXT:    [[IAJAK:%.*]] = add i64 [[IAJ]], [[K:%.*]]
 ; CHECK-V8M-TWO-FOLD-5-NEXT:    [[IXJ:%.*]] = xor i64 [[I]], [[J]]
 ; CHECK-V8M-TWO-FOLD-5-NEXT:    [[IXJXK:%.*]] = xor i64 [[IXJ]], [[K]]
-; CHECK-V8M-TWO-FOLD-5-NEXT:    [[WP:%.*]] = select i1 [[B:%.*]], i64 [[IAJAK]], i64 [[IXJXK]]
+; CHECK-V8M-TWO-FOLD-5-NEXT:    br i1 [[B:%.*]], label [[P:%.*]], label [[Q:%.*]]
+; CHECK-V8M-TWO-FOLD-5:       P:
+; CHECK-V8M-TWO-FOLD-5-NEXT:    br label [[N:%.*]]
+; CHECK-V8M-TWO-FOLD-5:       Q:
+; CHECK-V8M-TWO-FOLD-5-NEXT:    br label [[N]]
+; CHECK-V8M-TWO-FOLD-5:       N:
+; CHECK-V8M-TWO-FOLD-5-NEXT:    [[WP:%.*]] = phi i64 [ [[IAJAK]], [[P]] ], [ [[IXJXK]], [[Q]] ]
 ; CHECK-V8M-TWO-FOLD-5-NEXT:    [[WP2:%.*]] = add i64 [[WP]], [[WP]]
 ; CHECK-V8M-TWO-FOLD-5-NEXT:    br label [[M]]
 ; CHECK-V8M-TWO-FOLD-5:       M:
-; CHECK-V8M-TWO-FOLD-5-NEXT:    [[W:%.*]] = phi i64 [ [[WP2]], [[O]] ], [ 2, [[ENTRY:%.*]] ]
+; CHECK-V8M-TWO-FOLD-5-NEXT:    [[W:%.*]] = phi i64 [ [[WP2]], [[N]] ], [ 2, [[ENTRY:%.*]] ]
 ; CHECK-V8M-TWO-FOLD-5-NEXT:    [[R:%.*]] = add i64 [[W]], 1
 ; CHECK-V8M-TWO-FOLD-5-NEXT:    ret i64 [[R]]
 ;
@@ -406,13 +466,23 @@
 ;
 ; CHECK-V8M-TWO-FOLD-6-LABEL: @test_i64_minsize(
 ; CHECK-V8M-TWO-FOLD-6-NEXT:  entry:
+; CHECK-V8M-TWO-FOLD-6-NEXT:    br i1 [[A:%.*]], label [[M:%.*]], label [[O:%.*]]
+; CHECK-V8M-TWO-FOLD-6:       O:
 ; CHECK-V8M-TWO-FOLD-6-NEXT:    [[IAJ:%.*]] = add i64 [[I:%.*]], [[J:%.*]]
 ; CHECK-V8M-TWO-FOLD-6-NEXT:    [[IAJAK:%.*]] = add i64 [[IAJ]], [[K:%.*]]
 ; CHECK-V8M-TWO-FOLD-6-NEXT:    [[IXJ:%.*]] = xor i64 [[I]], [[J]]
 ; CHECK-V8M-TWO-FOLD-6-NEXT:    [[IXJXK:%.*]] = xor i64 [[IXJ]], [[K]]
-; CHECK-V8M-TWO-FOLD-6-NEXT:    [[WP:%.*]] = select i1 [[B:%.*]], i64 [[IAJAK]], i64 [[IXJXK]]
+; CHECK-V8M-TWO-FOLD-6-NEXT:    br i1 [[B:%.*]], label [[P:%.*]], label [[Q:%.*]]
+; CHECK-V8M-TWO-FOLD-6:       P:
+; CHECK-V8M-TWO-FOLD-6-NEXT:    br label [[N:%.*]]
+; CHECK-V8M-TWO-FOLD-6:       Q:
+; CHECK-V8M-TWO-FOLD-6-NEXT:    br label [[N]]
+; CHECK-V8M-TWO-FOLD-6:       N:
+; CHECK-V8M-TWO-FOLD-6-NEXT:    [[WP:%.*]] = phi i64 [ [[IAJAK]], [[P]] ], [ [[IXJXK]], [[Q]] ]
 ; CHECK-V8M-TWO-FOLD-6-NEXT:    [[WP2:%.*]] = add i64 [[WP]], [[WP]]
-; CHECK-V8M-TWO-FOLD-6-NEXT:    [[W:%.*]] = select i1 [[A:%.*]], i64 2, i64 [[WP2]]
+; CHECK-V8M-TWO-FOLD-6-NEXT:    br label [[M]]
+; CHECK-V8M-TWO-FOLD-6:       M:
+; CHECK-V8M-TWO-FOLD-6-NEXT:    [[W:%.*]] = phi i64 [ [[WP2]], [[N]] ], [ 2, [[ENTRY:%.*]] ]
 ; CHECK-V8M-TWO-FOLD-6-NEXT:    [[R:%.*]] = add i64 [[W]], 1
 ; CHECK-V8M-TWO-FOLD-6-NEXT:    ret i64 [[R]]
 ;
@@ -424,8 +494,8 @@
 ; CHECK-V8A-TWO-FOLD-6-NEXT:    [[IXJXK:%.*]] = xor i64 [[IXJ]], [[K]]
 ; CHECK-V8A-TWO-FOLD-6-NEXT:    [[WP:%.*]] = select i1 [[B:%.*]], i64 [[IAJAK]], i64 [[IXJXK]]
 ; CHECK-V8A-TWO-FOLD-6-NEXT:    [[WP2:%.*]] = add i64 [[WP]], [[WP]]
-; CHECK-V8A-TWO-FOLD-6-NEXT:    [[W:%.*]] = select i1 [[A:%.*]], i64 2, i64 [[WP2]]
-; CHECK-V8A-TWO-FOLD-6-NEXT:    [[R:%.*]] = add i64 [[W]], 1
+; CHECK-V8A-TWO-FOLD-6-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[A:%.*]], i64 2, i64 [[WP2]]
+; CHECK-V8A-TWO-FOLD-6-NEXT:    [[R:%.*]] = add i64 [[SPEC_SELECT]], 1
 ; CHECK-V8A-TWO-FOLD-6-NEXT:    ret i64 [[R]]
 ;
 entry:
Index: llvm/test/Transforms/SimplifyCFG/ARM/speculate-math.ll
===================================================================
--- llvm/test/Transforms/SimplifyCFG/ARM/speculate-math.ll
+++ llvm/test/Transforms/SimplifyCFG/ARM/speculate-math.ll
@@ -17,21 +17,33 @@
 ; CHECK-MVE-NEXT:  entry:
 ; CHECK-MVE-NEXT:    [[CMP:%.*]] = fcmp ogt double [[A:%.*]], 0.000000e+00
 ; CHECK-MVE-NEXT:    [[DIV:%.*]] = fdiv double [[B:%.*]], [[A]]
-; CHECK-MVE-NEXT:    [[COND:%.*]] = select nsz i1 [[CMP]], double [[DIV]], double 0.000000e+00
+; CHECK-MVE-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_END:%.*]]
+; CHECK-MVE:       cond.true:
+; CHECK-MVE-NEXT:    br label [[COND_END]]
+; CHECK-MVE:       cond.end:
+; CHECK-MVE-NEXT:    [[COND:%.*]] = phi nsz double [ [[DIV]], [[COND_TRUE]] ], [ 0.000000e+00, [[ENTRY:%.*]] ]
 ; CHECK-MVE-NEXT:    ret double [[COND]]
 ;
 ; CHECK-V8M-MAIN-LABEL: @fdiv_test(
 ; CHECK-V8M-MAIN-NEXT:  entry:
 ; CHECK-V8M-MAIN-NEXT:    [[CMP:%.*]] = fcmp ogt double [[A:%.*]], 0.000000e+00
 ; CHECK-V8M-MAIN-NEXT:    [[DIV:%.*]] = fdiv double [[B:%.*]], [[A]]
-; CHECK-V8M-MAIN-NEXT:    [[COND:%.*]] = select nsz i1 [[CMP]], double [[DIV]], double 0.000000e+00
+; CHECK-V8M-MAIN-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_END:%.*]]
+; CHECK-V8M-MAIN:       cond.true:
+; CHECK-V8M-MAIN-NEXT:    br label [[COND_END]]
+; CHECK-V8M-MAIN:       cond.end:
+; CHECK-V8M-MAIN-NEXT:    [[COND:%.*]] = phi nsz double [ [[DIV]], [[COND_TRUE]] ], [ 0.000000e+00, [[ENTRY:%.*]] ]
 ; CHECK-V8M-MAIN-NEXT:    ret double [[COND]]
 ;
 ; CHECK-V8M-BASE-LABEL: @fdiv_test(
 ; CHECK-V8M-BASE-NEXT:  entry:
 ; CHECK-V8M-BASE-NEXT:    [[CMP:%.*]] = fcmp ogt double [[A:%.*]], 0.000000e+00
 ; CHECK-V8M-BASE-NEXT:    [[DIV:%.*]] = fdiv double [[B:%.*]], [[A]]
-; CHECK-V8M-BASE-NEXT:    [[COND:%.*]] = select nsz i1 [[CMP]], double [[DIV]], double 0.000000e+00
+; CHECK-V8M-BASE-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_END:%.*]]
+; CHECK-V8M-BASE:       cond.true:
+; CHECK-V8M-BASE-NEXT:    br label [[COND_END]]
+; CHECK-V8M-BASE:       cond.end:
+; CHECK-V8M-BASE-NEXT:    [[COND:%.*]] = phi nsz double [ [[DIV]], [[COND_TRUE]] ], [ 0.000000e+00, [[ENTRY:%.*]] ]
 ; CHECK-V8M-BASE-NEXT:    ret double [[COND]]
 ;
 entry:
@@ -51,7 +63,7 @@
 ; CHECK-MVE-LABEL: @sqrt_test(
 ; CHECK-MVE-NEXT:  entry:
 ; CHECK-MVE-NEXT:    [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
-; CHECK-MVE-NEXT:    [[TMP0:%.*]] = tail call float @llvm.sqrt.f32(float [[A]]) #3
+; CHECK-MVE-NEXT:    [[TMP0:%.*]] = tail call float @llvm.sqrt.f32(float [[A]]) [[ATTR3:#.*]]
 ; CHECK-MVE-NEXT:    [[COND_I:%.*]] = select afn i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
 ; CHECK-MVE-NEXT:    store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
 ; CHECK-MVE-NEXT:    ret void
@@ -59,7 +71,7 @@
 ; CHECK-V8M-MAIN-LABEL: @sqrt_test(
 ; CHECK-V8M-MAIN-NEXT:  entry:
 ; CHECK-V8M-MAIN-NEXT:    [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
-; CHECK-V8M-MAIN-NEXT:    [[TMP0:%.*]] = tail call float @llvm.sqrt.f32(float [[A]]) #2
+; CHECK-V8M-MAIN-NEXT:    [[TMP0:%.*]] = tail call float @llvm.sqrt.f32(float [[A]]) [[ATTR2:#.*]]
 ; CHECK-V8M-MAIN-NEXT:    [[COND_I:%.*]] = select afn i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
 ; CHECK-V8M-MAIN-NEXT:    store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
 ; CHECK-V8M-MAIN-NEXT:    ret void
@@ -67,7 +79,7 @@
 ; CHECK-V8M-BASE-LABEL: @sqrt_test(
 ; CHECK-V8M-BASE-NEXT:  entry:
 ; CHECK-V8M-BASE-NEXT:    [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
-; CHECK-V8M-BASE-NEXT:    [[TMP0:%.*]] = tail call float @llvm.sqrt.f32(float [[A]]) #2
+; CHECK-V8M-BASE-NEXT:    [[TMP0:%.*]] = tail call float @llvm.sqrt.f32(float [[A]]) [[ATTR2:#.*]]
 ; CHECK-V8M-BASE-NEXT:    [[COND_I:%.*]] = select afn i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
 ; CHECK-V8M-BASE-NEXT:    store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
 ; CHECK-V8M-BASE-NEXT:    ret void
@@ -90,7 +102,7 @@
 ; CHECK-MVE-LABEL: @fabs_test(
 ; CHECK-MVE-NEXT:  entry:
 ; CHECK-MVE-NEXT:    [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
-; CHECK-MVE-NEXT:    [[TMP0:%.*]] = tail call float @llvm.fabs.f32(float [[A]]) #3
+; CHECK-MVE-NEXT:    [[TMP0:%.*]] = tail call float @llvm.fabs.f32(float [[A]]) [[ATTR3]]
 ; CHECK-MVE-NEXT:    [[COND_I:%.*]] = select reassoc i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
 ; CHECK-MVE-NEXT:    store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
 ; CHECK-MVE-NEXT:    ret void
@@ -98,7 +110,7 @@
 ; CHECK-V8M-MAIN-LABEL: @fabs_test(
 ; CHECK-V8M-MAIN-NEXT:  entry:
 ; CHECK-V8M-MAIN-NEXT:    [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
-; CHECK-V8M-MAIN-NEXT:    [[TMP0:%.*]] = tail call float @llvm.fabs.f32(float [[A]]) #2
+; CHECK-V8M-MAIN-NEXT:    [[TMP0:%.*]] = tail call float @llvm.fabs.f32(float [[A]]) [[ATTR2]]
 ; CHECK-V8M-MAIN-NEXT:    [[COND_I:%.*]] = select reassoc i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
 ; CHECK-V8M-MAIN-NEXT:    store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
 ; CHECK-V8M-MAIN-NEXT:    ret void
@@ -106,7 +118,7 @@
 ; CHECK-V8M-BASE-LABEL: @fabs_test(
 ; CHECK-V8M-BASE-NEXT:  entry:
 ; CHECK-V8M-BASE-NEXT:    [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
-; CHECK-V8M-BASE-NEXT:    [[TMP0:%.*]] = tail call float @llvm.fabs.f32(float [[A]]) #2
+; CHECK-V8M-BASE-NEXT:    [[TMP0:%.*]] = tail call float @llvm.fabs.f32(float [[A]]) [[ATTR2]]
 ; CHECK-V8M-BASE-NEXT:    [[COND_I:%.*]] = select reassoc i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
 ; CHECK-V8M-BASE-NEXT:    store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
 ; CHECK-V8M-BASE-NEXT:    ret void
@@ -129,7 +141,7 @@
 ; CHECK-MVE-LABEL: @fma_test(
 ; CHECK-MVE-NEXT:  entry:
 ; CHECK-MVE-NEXT:    [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
-; CHECK-MVE-NEXT:    [[TMP0:%.*]] = tail call float @llvm.fma.f32(float [[A]], float [[B:%.*]], float [[C:%.*]]) #3
+; CHECK-MVE-NEXT:    [[TMP0:%.*]] = tail call float @llvm.fma.f32(float [[A]], float [[B:%.*]], float [[C:%.*]]) [[ATTR3]]
 ; CHECK-MVE-NEXT:    [[COND_I:%.*]] = select reassoc nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
 ; CHECK-MVE-NEXT:    store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
 ; CHECK-MVE-NEXT:    ret void
@@ -137,7 +149,7 @@
 ; CHECK-V8M-MAIN-LABEL: @fma_test(
 ; CHECK-V8M-MAIN-NEXT:  entry:
 ; CHECK-V8M-MAIN-NEXT:    [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
-; CHECK-V8M-MAIN-NEXT:    [[TMP0:%.*]] = tail call float @llvm.fma.f32(float [[A]], float [[B:%.*]], float [[C:%.*]]) #2
+; CHECK-V8M-MAIN-NEXT:    [[TMP0:%.*]] = tail call float @llvm.fma.f32(float [[A]], float [[B:%.*]], float [[C:%.*]]) [[ATTR2]]
 ; CHECK-V8M-MAIN-NEXT:    [[COND_I:%.*]] = select reassoc nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
 ; CHECK-V8M-MAIN-NEXT:    store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
 ; CHECK-V8M-MAIN-NEXT:    ret void
@@ -145,7 +157,7 @@
 ; CHECK-V8M-BASE-LABEL: @fma_test(
 ; CHECK-V8M-BASE-NEXT:  entry:
 ; CHECK-V8M-BASE-NEXT:    [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
-; CHECK-V8M-BASE-NEXT:    [[TMP0:%.*]] = tail call float @llvm.fma.f32(float [[A]], float [[B:%.*]], float [[C:%.*]]) #2
+; CHECK-V8M-BASE-NEXT:    [[TMP0:%.*]] = tail call float @llvm.fma.f32(float [[A]], float [[B:%.*]], float [[C:%.*]]) [[ATTR2]]
 ; CHECK-V8M-BASE-NEXT:    [[COND_I:%.*]] = select reassoc nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
 ; CHECK-V8M-BASE-NEXT:    store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
 ; CHECK-V8M-BASE-NEXT:    ret void
@@ -168,7 +180,7 @@
 ; CHECK-MVE-LABEL: @fmuladd_test(
 ; CHECK-MVE-NEXT:  entry:
 ; CHECK-MVE-NEXT:    [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
-; CHECK-MVE-NEXT:    [[TMP0:%.*]] = tail call float @llvm.fmuladd.f32(float [[A]], float [[B:%.*]], float [[C:%.*]]) #3
+; CHECK-MVE-NEXT:    [[TMP0:%.*]] = tail call float @llvm.fmuladd.f32(float [[A]], float [[B:%.*]], float [[C:%.*]]) [[ATTR3]]
 ; CHECK-MVE-NEXT:    [[COND_I:%.*]] = select ninf i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
 ; CHECK-MVE-NEXT:    store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
 ; CHECK-MVE-NEXT:    ret void
@@ -176,7 +188,7 @@
 ; CHECK-V8M-MAIN-LABEL: @fmuladd_test(
 ; CHECK-V8M-MAIN-NEXT:  entry:
 ; CHECK-V8M-MAIN-NEXT:    [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
-; CHECK-V8M-MAIN-NEXT:    [[TMP0:%.*]] = tail call float @llvm.fmuladd.f32(float [[A]], float [[B:%.*]], float [[C:%.*]]) #2
+; CHECK-V8M-MAIN-NEXT:    [[TMP0:%.*]] = tail call float @llvm.fmuladd.f32(float [[A]], float [[B:%.*]], float [[C:%.*]]) [[ATTR2]]
 ; CHECK-V8M-MAIN-NEXT:    [[COND_I:%.*]] = select ninf i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
 ; CHECK-V8M-MAIN-NEXT:    store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
 ; CHECK-V8M-MAIN-NEXT:    ret void
@@ -184,7 +196,7 @@
 ; CHECK-V8M-BASE-LABEL: @fmuladd_test(
 ; CHECK-V8M-BASE-NEXT:  entry:
 ; CHECK-V8M-BASE-NEXT:    [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
-; CHECK-V8M-BASE-NEXT:    [[TMP0:%.*]] = tail call float @llvm.fmuladd.f32(float [[A]], float [[B:%.*]], float [[C:%.*]]) #2
+; CHECK-V8M-BASE-NEXT:    [[TMP0:%.*]] = tail call float @llvm.fmuladd.f32(float [[A]], float [[B:%.*]], float [[C:%.*]]) [[ATTR2]]
 ; CHECK-V8M-BASE-NEXT:    [[COND_I:%.*]] = select ninf i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
 ; CHECK-V8M-BASE-NEXT:    store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
 ; CHECK-V8M-BASE-NEXT:    ret void
@@ -207,7 +219,7 @@
 ; CHECK-MVE-LABEL: @minnum_test(
 ; CHECK-MVE-NEXT:  entry:
 ; CHECK-MVE-NEXT:    [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
-; CHECK-MVE-NEXT:    [[TMP0:%.*]] = tail call float @llvm.minnum.f32(float [[A]], float [[B:%.*]]) #3
+; CHECK-MVE-NEXT:    [[TMP0:%.*]] = tail call float @llvm.minnum.f32(float [[A]], float [[B:%.*]]) [[ATTR3]]
 ; CHECK-MVE-NEXT:    [[COND_I:%.*]] = select i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
 ; CHECK-MVE-NEXT:    store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
 ; CHECK-MVE-NEXT:    ret void
@@ -215,7 +227,7 @@
 ; CHECK-V8M-MAIN-LABEL: @minnum_test(
 ; CHECK-V8M-MAIN-NEXT:  entry:
 ; CHECK-V8M-MAIN-NEXT:    [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
-; CHECK-V8M-MAIN-NEXT:    [[TMP0:%.*]] = tail call float @llvm.minnum.f32(float [[A]], float [[B:%.*]]) #2
+; CHECK-V8M-MAIN-NEXT:    [[TMP0:%.*]] = tail call float @llvm.minnum.f32(float [[A]], float [[B:%.*]]) [[ATTR2]]
 ; CHECK-V8M-MAIN-NEXT:    [[COND_I:%.*]] = select i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
 ; CHECK-V8M-MAIN-NEXT:    store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
 ; CHECK-V8M-MAIN-NEXT:    ret void
@@ -223,7 +235,7 @@
 ; CHECK-V8M-BASE-LABEL: @minnum_test(
 ; CHECK-V8M-BASE-NEXT:  entry:
 ; CHECK-V8M-BASE-NEXT:    [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
-; CHECK-V8M-BASE-NEXT:    [[TMP0:%.*]] = tail call float @llvm.minnum.f32(float [[A]], float [[B:%.*]]) #2
+; CHECK-V8M-BASE-NEXT:    [[TMP0:%.*]] = tail call float @llvm.minnum.f32(float [[A]], float [[B:%.*]]) [[ATTR2]]
 ; CHECK-V8M-BASE-NEXT:    [[COND_I:%.*]] = select i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
 ; CHECK-V8M-BASE-NEXT:    store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
 ; CHECK-V8M-BASE-NEXT:    ret void
@@ -246,7 +258,7 @@
 ; CHECK-MVE-LABEL: @maxnum_test(
 ; CHECK-MVE-NEXT:  entry:
 ; CHECK-MVE-NEXT:    [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
-; CHECK-MVE-NEXT:    [[TMP0:%.*]] = tail call float @llvm.maxnum.f32(float [[A]], float [[B:%.*]]) #3
+; CHECK-MVE-NEXT:    [[TMP0:%.*]] = tail call float @llvm.maxnum.f32(float [[A]], float [[B:%.*]]) [[ATTR3]]
 ; CHECK-MVE-NEXT:    [[COND_I:%.*]] = select ninf nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
 ; CHECK-MVE-NEXT:    store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
 ; CHECK-MVE-NEXT:    ret void
@@ -254,7 +266,7 @@
 ; CHECK-V8M-MAIN-LABEL: @maxnum_test(
 ; CHECK-V8M-MAIN-NEXT:  entry:
 ; CHECK-V8M-MAIN-NEXT:    [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
-; CHECK-V8M-MAIN-NEXT:    [[TMP0:%.*]] = tail call float @llvm.maxnum.f32(float [[A]], float [[B:%.*]]) #2
+; CHECK-V8M-MAIN-NEXT:    [[TMP0:%.*]] = tail call float @llvm.maxnum.f32(float [[A]], float [[B:%.*]]) [[ATTR2]]
 ; CHECK-V8M-MAIN-NEXT:    [[COND_I:%.*]] = select ninf nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
 ; CHECK-V8M-MAIN-NEXT:    store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
 ; CHECK-V8M-MAIN-NEXT:    ret void
@@ -262,7 +274,7 @@
 ; CHECK-V8M-BASE-LABEL: @maxnum_test(
 ; CHECK-V8M-BASE-NEXT:  entry:
 ; CHECK-V8M-BASE-NEXT:    [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
-; CHECK-V8M-BASE-NEXT:    [[TMP0:%.*]] = tail call float @llvm.maxnum.f32(float [[A]], float [[B:%.*]]) #2
+; CHECK-V8M-BASE-NEXT:    [[TMP0:%.*]] = tail call float @llvm.maxnum.f32(float [[A]], float [[B:%.*]]) [[ATTR2]]
 ; CHECK-V8M-BASE-NEXT:    [[COND_I:%.*]] = select ninf nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
 ; CHECK-V8M-BASE-NEXT:    store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
 ; CHECK-V8M-BASE-NEXT:    ret void
@@ -285,7 +297,7 @@
 ; CHECK-MVE-LABEL: @minimum_test(
 ; CHECK-MVE-NEXT:  entry:
 ; CHECK-MVE-NEXT:    [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
-; CHECK-MVE-NEXT:    [[TMP0:%.*]] = tail call float @llvm.minimum.f32(float [[A]], float [[B:%.*]]) #3
+; CHECK-MVE-NEXT:    [[TMP0:%.*]] = tail call float @llvm.minimum.f32(float [[A]], float [[B:%.*]]) [[ATTR3]]
 ; CHECK-MVE-NEXT:    [[COND_I:%.*]] = select reassoc i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
 ; CHECK-MVE-NEXT:    store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
 ; CHECK-MVE-NEXT:    ret void
@@ -293,7 +305,7 @@
 ; CHECK-V8M-MAIN-LABEL: @minimum_test(
 ; CHECK-V8M-MAIN-NEXT:  entry:
 ; CHECK-V8M-MAIN-NEXT:    [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
-; CHECK-V8M-MAIN-NEXT:    [[TMP0:%.*]] = tail call float @llvm.minimum.f32(float [[A]], float [[B:%.*]]) #2
+; CHECK-V8M-MAIN-NEXT:    [[TMP0:%.*]] = tail call float @llvm.minimum.f32(float [[A]], float [[B:%.*]]) [[ATTR2]]
 ; CHECK-V8M-MAIN-NEXT:    [[COND_I:%.*]] = select reassoc i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
 ; CHECK-V8M-MAIN-NEXT:    store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
 ; CHECK-V8M-MAIN-NEXT:    ret void
@@ -301,7 +313,7 @@
 ; CHECK-V8M-BASE-LABEL: @minimum_test(
 ; CHECK-V8M-BASE-NEXT:  entry:
 ; CHECK-V8M-BASE-NEXT:    [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
-; CHECK-V8M-BASE-NEXT:    [[TMP0:%.*]] = tail call float @llvm.minimum.f32(float [[A]], float [[B:%.*]]) #2
+; CHECK-V8M-BASE-NEXT:    [[TMP0:%.*]] = tail call float @llvm.minimum.f32(float [[A]], float [[B:%.*]]) [[ATTR2]]
 ; CHECK-V8M-BASE-NEXT:    [[COND_I:%.*]] = select reassoc i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
 ; CHECK-V8M-BASE-NEXT:    store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
 ; CHECK-V8M-BASE-NEXT:    ret void
@@ -324,7 +336,7 @@
 ; CHECK-MVE-LABEL: @maximum_test(
 ; CHECK-MVE-NEXT:  entry:
 ; CHECK-MVE-NEXT:    [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
-; CHECK-MVE-NEXT:    [[TMP0:%.*]] = tail call float @llvm.maximum.f32(float [[A]], float [[B:%.*]]) #3
+; CHECK-MVE-NEXT:    [[TMP0:%.*]] = tail call float @llvm.maximum.f32(float [[A]], float [[B:%.*]]) [[ATTR3]]
 ; CHECK-MVE-NEXT:    [[COND_I:%.*]] = select nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
 ; CHECK-MVE-NEXT:    store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
 ; CHECK-MVE-NEXT:    ret void
@@ -332,7 +344,7 @@
 ; CHECK-V8M-MAIN-LABEL: @maximum_test(
 ; CHECK-V8M-MAIN-NEXT:  entry:
 ; CHECK-V8M-MAIN-NEXT:    [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
-; CHECK-V8M-MAIN-NEXT:    [[TMP0:%.*]] = tail call float @llvm.maximum.f32(float [[A]], float [[B:%.*]]) #2
+; CHECK-V8M-MAIN-NEXT:    [[TMP0:%.*]] = tail call float @llvm.maximum.f32(float [[A]], float [[B:%.*]]) [[ATTR2]]
 ; CHECK-V8M-MAIN-NEXT:    [[COND_I:%.*]] = select nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
 ; CHECK-V8M-MAIN-NEXT:    store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
 ; CHECK-V8M-MAIN-NEXT:    ret void
@@ -340,7 +352,7 @@
 ; CHECK-V8M-BASE-LABEL: @maximum_test(
 ; CHECK-V8M-BASE-NEXT:  entry:
 ; CHECK-V8M-BASE-NEXT:    [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
-; CHECK-V8M-BASE-NEXT:    [[TMP0:%.*]] = tail call float @llvm.maximum.f32(float [[A]], float [[B:%.*]]) #2
+; CHECK-V8M-BASE-NEXT:    [[TMP0:%.*]] = tail call float @llvm.maximum.f32(float [[A]], float [[B:%.*]]) [[ATTR2]]
 ; CHECK-V8M-BASE-NEXT:    [[COND_I:%.*]] = select nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
 ; CHECK-V8M-BASE-NEXT:    store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
 ; CHECK-V8M-BASE-NEXT:    ret void
Index: llvm/test/Transforms/SimplifyCFG/PhiEliminate3.ll
===================================================================
--- llvm/test/Transforms/SimplifyCFG/PhiEliminate3.ll
+++ llvm/test/Transforms/SimplifyCFG/PhiEliminate3.ll
@@ -2,26 +2,106 @@
 ; RUN: opt < %s -simplifycfg -S -phi-node-folding-threshold=1 | FileCheck %s --check-prefix=ALL --check-prefix=CHECK-ONE
 ; RUN: opt < %s -simplifycfg -S -phi-node-folding-threshold=2 | FileCheck %s --check-prefix=ALL --check-prefix=CHECK-TWO
 ; RUN: opt < %s -simplifycfg -S -phi-node-folding-threshold=7 | FileCheck %s --check-prefix=ALL --check-prefix=CHECK-SEVEN
+; RUN: opt < %s -simplifycfg -S -two-entry-phi-node-folding-threshold=5 | FileCheck %s --check-prefix=ALL --check-prefix=CHECK-TWO-FOLD-5
+; RUN: opt < %s -simplifycfg -S -two-entry-phi-node-folding-threshold=6 | FileCheck %s --check-prefix=ALL --check-prefix=CHECK-TWO-FOLD-6
 
 ; Test merging of blocks containing complex expressions,
 ; with various folding thresholds
 
 define i32 @test(i1 %a, i1 %b, i32 %i, i32 %j, i32 %k) {
-; ALL-LABEL: @test(
-; ALL-NEXT:  entry:
-; ALL-NEXT:    br i1 [[A:%.*]], label [[M:%.*]], label [[O:%.*]]
-; ALL:       O:
-; ALL-NEXT:    [[IAJ:%.*]] = add i32 [[I:%.*]], [[J:%.*]]
-; ALL-NEXT:    [[IAJAK:%.*]] = add i32 [[IAJ]], [[K:%.*]]
-; ALL-NEXT:    [[IXJ:%.*]] = xor i32 [[I]], [[J]]
-; ALL-NEXT:    [[IXJXK:%.*]] = xor i32 [[IXJ]], [[K]]
-; ALL-NEXT:    [[WP:%.*]] = select i1 [[B:%.*]], i32 [[IAJAK]], i32 [[IXJXK]]
-; ALL-NEXT:    [[WP2:%.*]] = add i32 [[WP]], [[WP]]
-; ALL-NEXT:    br label [[M]]
-; ALL:       M:
-; ALL-NEXT:    [[W:%.*]] = phi i32 [ [[WP2]], [[O]] ], [ 2, [[ENTRY:%.*]] ]
-; ALL-NEXT:    [[R:%.*]] = add i32 [[W]], 1
-; ALL-NEXT:    ret i32 [[R]]
+; CHECK-ONE-LABEL: @test(
+; CHECK-ONE-NEXT:  entry:
+; CHECK-ONE-NEXT:    br i1 [[A:%.*]], label [[M:%.*]], label [[O:%.*]]
+; CHECK-ONE:       O:
+; CHECK-ONE-NEXT:    [[IAJ:%.*]] = add i32 [[I:%.*]], [[J:%.*]]
+; CHECK-ONE-NEXT:    [[IAJAK:%.*]] = add i32 [[IAJ]], [[K:%.*]]
+; CHECK-ONE-NEXT:    [[IXJ:%.*]] = xor i32 [[I]], [[J]]
+; CHECK-ONE-NEXT:    [[IXJXK:%.*]] = xor i32 [[IXJ]], [[K]]
+; CHECK-ONE-NEXT:    br i1 [[B:%.*]], label [[P:%.*]], label [[Q:%.*]]
+; CHECK-ONE:       P:
+; CHECK-ONE-NEXT:    br label [[N:%.*]]
+; CHECK-ONE:       Q:
+; CHECK-ONE-NEXT:    br label [[N]]
+; CHECK-ONE:       N:
+; CHECK-ONE-NEXT:    [[WP:%.*]] = phi i32 [ [[IAJAK]], [[P]] ], [ [[IXJXK]], [[Q]] ]
+; CHECK-ONE-NEXT:    [[WP2:%.*]] = add i32 [[WP]], [[WP]]
+; CHECK-ONE-NEXT:    br label [[M]]
+; CHECK-ONE:       M:
+; CHECK-ONE-NEXT:    [[W:%.*]] = phi i32 [ [[WP2]], [[N]] ], [ 2, [[ENTRY:%.*]] ]
+; CHECK-ONE-NEXT:    [[R:%.*]] = add i32 [[W]], 1
+; CHECK-ONE-NEXT:    ret i32 [[R]]
+;
+; CHECK-TWO-LABEL: @test(
+; CHECK-TWO-NEXT:  entry:
+; CHECK-TWO-NEXT:    br i1 [[A:%.*]], label [[M:%.*]], label [[O:%.*]]
+; CHECK-TWO:       O:
+; CHECK-TWO-NEXT:    [[IAJ:%.*]] = add i32 [[I:%.*]], [[J:%.*]]
+; CHECK-TWO-NEXT:    [[IAJAK:%.*]] = add i32 [[IAJ]], [[K:%.*]]
+; CHECK-TWO-NEXT:    [[IXJ:%.*]] = xor i32 [[I]], [[J]]
+; CHECK-TWO-NEXT:    [[IXJXK:%.*]] = xor i32 [[IXJ]], [[K]]
+; CHECK-TWO-NEXT:    br i1 [[B:%.*]], label [[P:%.*]], label [[Q:%.*]]
+; CHECK-TWO:       P:
+; CHECK-TWO-NEXT:    br label [[N:%.*]]
+; CHECK-TWO:       Q:
+; CHECK-TWO-NEXT:    br label [[N]]
+; CHECK-TWO:       N:
+; CHECK-TWO-NEXT:    [[WP:%.*]] = phi i32 [ [[IAJAK]], [[P]] ], [ [[IXJXK]], [[Q]] ]
+; CHECK-TWO-NEXT:    [[WP2:%.*]] = add i32 [[WP]], [[WP]]
+; CHECK-TWO-NEXT:    br label [[M]]
+; CHECK-TWO:       M:
+; CHECK-TWO-NEXT:    [[W:%.*]] = phi i32 [ [[WP2]], [[N]] ], [ 2, [[ENTRY:%.*]] ]
+; CHECK-TWO-NEXT:    [[R:%.*]] = add i32 [[W]], 1
+; CHECK-TWO-NEXT:    ret i32 [[R]]
+;
+; CHECK-SEVEN-LABEL: @test(
+; CHECK-SEVEN-NEXT:  entry:
+; CHECK-SEVEN-NEXT:    br i1 [[A:%.*]], label [[M:%.*]], label [[O:%.*]]
+; CHECK-SEVEN:       O:
+; CHECK-SEVEN-NEXT:    [[IAJ:%.*]] = add i32 [[I:%.*]], [[J:%.*]]
+; CHECK-SEVEN-NEXT:    [[IAJAK:%.*]] = add i32 [[IAJ]], [[K:%.*]]
+; CHECK-SEVEN-NEXT:    [[IXJ:%.*]] = xor i32 [[I]], [[J]]
+; CHECK-SEVEN-NEXT:    [[IXJXK:%.*]] = xor i32 [[IXJ]], [[K]]
+; CHECK-SEVEN-NEXT:    br i1 [[B:%.*]], label [[P:%.*]], label [[Q:%.*]]
+; CHECK-SEVEN:       P:
+; CHECK-SEVEN-NEXT:    br label [[N:%.*]]
+; CHECK-SEVEN:       Q:
+; CHECK-SEVEN-NEXT:    br label [[N]]
+; CHECK-SEVEN:       N:
+; CHECK-SEVEN-NEXT:    [[WP:%.*]] = phi i32 [ [[IAJAK]], [[P]] ], [ [[IXJXK]], [[Q]] ]
+; CHECK-SEVEN-NEXT:    [[WP2:%.*]] = add i32 [[WP]], [[WP]]
+; CHECK-SEVEN-NEXT:    br label [[M]]
+; CHECK-SEVEN:       M:
+; CHECK-SEVEN-NEXT:    [[W:%.*]] = phi i32 [ [[WP2]], [[N]] ], [ 2, [[ENTRY:%.*]] ]
+; CHECK-SEVEN-NEXT:    [[R:%.*]] = add i32 [[W]], 1
+; CHECK-SEVEN-NEXT:    ret i32 [[R]]
+;
+; CHECK-TWO-FOLD-5-LABEL: @test(
+; CHECK-TWO-FOLD-5-NEXT:  entry:
+; CHECK-TWO-FOLD-5-NEXT:    br i1 [[A:%.*]], label [[M:%.*]], label [[O:%.*]]
+; CHECK-TWO-FOLD-5:       O:
+; CHECK-TWO-FOLD-5-NEXT:    [[IAJ:%.*]] = add i32 [[I:%.*]], [[J:%.*]]
+; CHECK-TWO-FOLD-5-NEXT:    [[IAJAK:%.*]] = add i32 [[IAJ]], [[K:%.*]]
+; CHECK-TWO-FOLD-5-NEXT:    [[IXJ:%.*]] = xor i32 [[I]], [[J]]
+; CHECK-TWO-FOLD-5-NEXT:    [[IXJXK:%.*]] = xor i32 [[IXJ]], [[K]]
+; CHECK-TWO-FOLD-5-NEXT:    [[WP:%.*]] = select i1 [[B:%.*]], i32 [[IAJAK]], i32 [[IXJXK]]
+; CHECK-TWO-FOLD-5-NEXT:    [[WP2:%.*]] = add i32 [[WP]], [[WP]]
+; CHECK-TWO-FOLD-5-NEXT:    br label [[M]]
+; CHECK-TWO-FOLD-5:       M:
+; CHECK-TWO-FOLD-5-NEXT:    [[W:%.*]] = phi i32 [ [[WP2]], [[O]] ], [ 2, [[ENTRY:%.*]] ]
+; CHECK-TWO-FOLD-5-NEXT:    [[R:%.*]] = add i32 [[W]], 1
+; CHECK-TWO-FOLD-5-NEXT:    ret i32 [[R]]
+;
+; CHECK-TWO-FOLD-6-LABEL: @test(
+; CHECK-TWO-FOLD-6-NEXT:  entry:
+; CHECK-TWO-FOLD-6-NEXT:    [[IAJ:%.*]] = add i32 [[I:%.*]], [[J:%.*]]
+; CHECK-TWO-FOLD-6-NEXT:    [[IAJAK:%.*]] = add i32 [[IAJ]], [[K:%.*]]
+; CHECK-TWO-FOLD-6-NEXT:    [[IXJ:%.*]] = xor i32 [[I]], [[J]]
+; CHECK-TWO-FOLD-6-NEXT:    [[IXJXK:%.*]] = xor i32 [[IXJ]], [[K]]
+; CHECK-TWO-FOLD-6-NEXT:    [[WP:%.*]] = select i1 [[B:%.*]], i32 [[IAJAK]], i32 [[IXJXK]]
+; CHECK-TWO-FOLD-6-NEXT:    [[WP2:%.*]] = add i32 [[WP]], [[WP]]
+; CHECK-TWO-FOLD-6-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[A:%.*]], i32 2, i32 [[WP2]]
+; CHECK-TWO-FOLD-6-NEXT:    [[R:%.*]] = add i32 [[SPEC_SELECT]], 1
+; CHECK-TWO-FOLD-6-NEXT:    ret i32 [[R]]
 ;
 entry:
   br i1 %a, label %M, label %O
Index: llvm/test/Transforms/SimplifyCFG/speculate-math.ll
===================================================================
--- llvm/test/Transforms/SimplifyCFG/speculate-math.ll
+++ llvm/test/Transforms/SimplifyCFG/speculate-math.ll
@@ -16,7 +16,11 @@
 ; ALL-NEXT:  entry:
 ; ALL-NEXT:    [[CMP:%.*]] = fcmp ogt double [[A:%.*]], 0.000000e+00
 ; ALL-NEXT:    [[DIV:%.*]] = fdiv double [[B:%.*]], [[A]]
-; ALL-NEXT:    [[COND:%.*]] = select nsz i1 [[CMP]], double [[DIV]], double 0.000000e+00
+; ALL-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_END:%.*]]
+; ALL:       cond.true:
+; ALL-NEXT:    br label [[COND_END]]
+; ALL:       cond.end:
+; ALL-NEXT:    [[COND:%.*]] = phi nsz double [ [[DIV]], [[COND_TRUE]] ], [ 0.000000e+00, [[ENTRY:%.*]] ]
 ; ALL-NEXT:    ret double [[COND]]
 ;
 entry:
@@ -36,7 +40,7 @@
 ; ALL-LABEL: @sqrt_test(
 ; ALL-NEXT:  entry:
 ; ALL-NEXT:    [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
-; ALL-NEXT:    [[TMP0:%.*]] = tail call float @llvm.sqrt.f32(float [[A]]) #2
+; ALL-NEXT:    [[TMP0:%.*]] = tail call float @llvm.sqrt.f32(float [[A]]) [[ATTR2:#.*]]
 ; ALL-NEXT:    [[COND_I:%.*]] = select afn i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
 ; ALL-NEXT:    store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
 ; ALL-NEXT:    ret void
@@ -59,7 +63,7 @@
 ; ALL-LABEL: @fabs_test(
 ; ALL-NEXT:  entry:
 ; ALL-NEXT:    [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
-; ALL-NEXT:    [[TMP0:%.*]] = tail call float @llvm.fabs.f32(float [[A]]) #2
+; ALL-NEXT:    [[TMP0:%.*]] = tail call float @llvm.fabs.f32(float [[A]]) [[ATTR2]]
 ; ALL-NEXT:    [[COND_I:%.*]] = select reassoc i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
 ; ALL-NEXT:    store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
 ; ALL-NEXT:    ret void
@@ -82,7 +86,7 @@
 ; ALL-LABEL: @fma_test(
 ; ALL-NEXT:  entry:
 ; ALL-NEXT:    [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
-; ALL-NEXT:    [[TMP0:%.*]] = tail call float @llvm.fma.f32(float [[A]], float [[B:%.*]], float [[C:%.*]]) #2
+; ALL-NEXT:    [[TMP0:%.*]] = tail call float @llvm.fma.f32(float [[A]], float [[B:%.*]], float [[C:%.*]]) [[ATTR2]]
 ; ALL-NEXT:    [[COND_I:%.*]] = select reassoc nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
 ; ALL-NEXT:    store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
 ; ALL-NEXT:    ret void
@@ -105,7 +109,7 @@
 ; ALL-LABEL: @fmuladd_test(
 ; ALL-NEXT:  entry:
 ; ALL-NEXT:    [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
-; ALL-NEXT:    [[TMP0:%.*]] = tail call float @llvm.fmuladd.f32(float [[A]], float [[B:%.*]], float [[C:%.*]]) #2
+; ALL-NEXT:    [[TMP0:%.*]] = tail call float @llvm.fmuladd.f32(float [[A]], float [[B:%.*]], float [[C:%.*]]) [[ATTR2]]
 ; ALL-NEXT:    [[COND_I:%.*]] = select ninf i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
 ; ALL-NEXT:    store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
 ; ALL-NEXT:    ret void
@@ -128,7 +132,7 @@
 ; ALL-LABEL: @minnum_test(
 ; ALL-NEXT:  entry:
 ; ALL-NEXT:    [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
-; ALL-NEXT:    [[TMP0:%.*]] = tail call float @llvm.minnum.f32(float [[A]], float [[B:%.*]]) #2
+; ALL-NEXT:    [[TMP0:%.*]] = tail call float @llvm.minnum.f32(float [[A]], float [[B:%.*]]) [[ATTR2]]
 ; ALL-NEXT:    [[COND_I:%.*]] = select i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
 ; ALL-NEXT:    store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
 ; ALL-NEXT:    ret void
@@ -151,7 +155,7 @@
 ; ALL-LABEL: @maxnum_test(
 ; ALL-NEXT:  entry:
 ; ALL-NEXT:    [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
-; ALL-NEXT:    [[TMP0:%.*]] = tail call float @llvm.maxnum.f32(float [[A]], float [[B:%.*]]) #2
+; ALL-NEXT:    [[TMP0:%.*]] = tail call float @llvm.maxnum.f32(float [[A]], float [[B:%.*]]) [[ATTR2]]
 ; ALL-NEXT:    [[COND_I:%.*]] = select ninf nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
 ; ALL-NEXT:    store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
 ; ALL-NEXT:    ret void
@@ -174,7 +178,7 @@
 ; ALL-LABEL: @minimum_test(
 ; ALL-NEXT:  entry:
 ; ALL-NEXT:    [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
-; ALL-NEXT:    [[TMP0:%.*]] = tail call float @llvm.minimum.f32(float [[A]], float [[B:%.*]]) #2
+; ALL-NEXT:    [[TMP0:%.*]] = tail call float @llvm.minimum.f32(float [[A]], float [[B:%.*]]) [[ATTR2]]
 ; ALL-NEXT:    [[COND_I:%.*]] = select reassoc i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
 ; ALL-NEXT:    store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
 ; ALL-NEXT:    ret void
@@ -197,7 +201,7 @@
 ; ALL-LABEL: @maximum_test(
 ; ALL-NEXT:  entry:
 ; ALL-NEXT:    [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
-; ALL-NEXT:    [[TMP0:%.*]] = tail call float @llvm.maximum.f32(float [[A]], float [[B:%.*]]) #2
+; ALL-NEXT:    [[TMP0:%.*]] = tail call float @llvm.maximum.f32(float [[A]], float [[B:%.*]]) [[ATTR2]]
 ; ALL-NEXT:    [[COND_I:%.*]] = select nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
 ; ALL-NEXT:    store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
 ; ALL-NEXT:    ret void