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[AMDGPU] Correct DWARF register defintions
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Authored by t-tye on Aug 19 2020, 6:15 PM.

Details

Summary
  • Rename AMDGPU SCC DWARF register to STATUS since the scalar condition code is a bit within the STATUS register.
  • Correct bit size of the VCC_64 register to 64 which is the size in wave64 mode.

Diff Detail

Event Timeline

t-tye created this revision.Aug 19 2020, 6:15 PM
Herald added a project: Restricted Project. · View Herald TranscriptAug 19 2020, 6:15 PM
t-tye requested review of this revision.Aug 19 2020, 6:15 PM
scott.linder accepted this revision.Aug 19 2020, 6:18 PM
This revision is now accepted and ready to land.Aug 19 2020, 6:18 PM
This revision was landed with ongoing or failed builds.Aug 19 2020, 6:19 PM
This revision was automatically updated to reflect the committed changes.