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Differential D86042

[AMDGPU] Use correct defaults for xnack and sramecc
AbandonedPublic

Authored by kerbowa on Aug 16 2020, 2:21 PM.

Details

Reviewers
kzhuravl
t-tye
yaxunl
rampitec
scott.linder
arsenm
Summary

Depends on D85882.

Diff Detail

Event Timeline

kerbowa created this revision.Aug 16 2020, 2:21 PM
Herald added a project: Restricted Project. · View Herald TranscriptAug 16 2020, 2:21 PM
Herald added subscribers: llvm-commits, asbirlea, jfb and 6 others. · View Herald Transcript
kerbowa requested review of this revision.Aug 16 2020, 2:21 PM
Herald added a subscriber: wdng. · View Herald TranscriptAug 16 2020, 2:21 PM
Harbormaster completed remote builds in B68557: Diff 285903.Aug 16 2020, 2:22 PM
asbirlea removed a subscriber: asbirlea.Aug 17 2020, 9:23 AM
kerbowa abandoned this revision.Oct 19 2020, 9:35 AM
Herald added a subscriber: wenlei. · View Herald TranscriptOct 19 2020, 9:35 AM

Large Diff

This large diff affects 142 files. Files without inline comments have been collapsed. Expand All Files

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Diff 285903

llvm/lib/Target/AMDGPU/AMDGPU.td

llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h

llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp

llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement-stack-lower.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomic-cmpxchg-local.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomic-cmpxchg-region.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-add-global.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-fadd-local.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-fadd-region.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-xchg-local.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-xchg-region.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.v2s16.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-sendmsg.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sat.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s32.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values-build-vector.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.dec.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.csub.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ubfe.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-default.mir

llvm/test/CodeGen/AMDGPU/add.v2i16.ll

llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll

llvm/test/CodeGen/AMDGPU/amdhsa-trap-num-sgprs.ll

llvm/test/CodeGen/AMDGPU/and.ll

llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll

llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll

llvm/test/CodeGen/AMDGPU/bitreverse.ll

llvm/test/CodeGen/AMDGPU/break-smem-soft-clauses.mir

llvm/test/CodeGen/AMDGPU/break-vmem-soft-clauses.mir

llvm/test/CodeGen/AMDGPU/buffer-intrinsics-mmo-offsets.ll

llvm/test/CodeGen/AMDGPU/cc-update.ll

llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll

llvm/test/CodeGen/AMDGPU/cluster-flat-loads-postra.mir

llvm/test/CodeGen/AMDGPU/cluster_stores.ll

llvm/test/CodeGen/AMDGPU/code-object-v3.ll

llvm/test/CodeGen/AMDGPU/collapse-endcf-broken.mir

llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll

llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll

llvm/test/CodeGen/AMDGPU/ctlz.ll

llvm/test/CodeGen/AMDGPU/ctpop16.ll

llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll

llvm/test/CodeGen/AMDGPU/directive-amdgcn-target.ll

llvm/test/CodeGen/AMDGPU/elf-header-flags-mach.ll

llvm/test/CodeGen/AMDGPU/elf-header-flags-sram-ecc.ll

llvm/test/CodeGen/AMDGPU/fabs.ll

llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll

llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.private.ll

llvm/test/CodeGen/AMDGPU/flat-scratch-reg.ll

llvm/test/CodeGen/AMDGPU/fneg-fabs.ll

llvm/test/CodeGen/AMDGPU/fold-operands-remove-m0-redef.mir

llvm/test/CodeGen/AMDGPU/fold-reload-into-exec.mir

llvm/test/CodeGen/AMDGPU/frem.ll

llvm/test/CodeGen/AMDGPU/fshl.ll

llvm/test/CodeGen/AMDGPU/fshr.ll

llvm/test/CodeGen/AMDGPU/function-returns.ll

llvm/test/CodeGen/AMDGPU/global-saddr.ll

llvm/test/CodeGen/AMDGPU/hazard-hidden-bundle.mir

llvm/test/CodeGen/AMDGPU/hazard-in-bundle.mir

llvm/test/CodeGen/AMDGPU/hsa-metadata-kernel-code-props-v3.ll

llvm/test/CodeGen/AMDGPU/hsa-metadata-kernel-code-props.ll

llvm/test/CodeGen/AMDGPU/idiv-licm.ll

llvm/test/CodeGen/AMDGPU/idot2.ll

llvm/test/CodeGen/AMDGPU/idot4s.ll

llvm/test/CodeGen/AMDGPU/idot4u.ll

llvm/test/CodeGen/AMDGPU/idot8s.ll

llvm/test/CodeGen/AMDGPU/idot8u.ll

llvm/test/CodeGen/AMDGPU/image-load-d16-tfe.ll

llvm/test/CodeGen/AMDGPU/imm.ll

llvm/test/CodeGen/AMDGPU/imm16.ll

llvm/test/CodeGen/AMDGPU/immv216.ll

llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll

llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll

llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.nsa.ll

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ubfe.ll

llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll

llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll

llvm/test/CodeGen/AMDGPU/load-hi16.ll

llvm/test/CodeGen/AMDGPU/load-lo16.ll

llvm/test/CodeGen/AMDGPU/loop_header_nopred.mir

llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll

llvm/test/CodeGen/AMDGPU/max.i16.ll

llvm/test/CodeGen/AMDGPU/memory-legalizer-atomic-rmw.ll

llvm/test/CodeGen/AMDGPU/min.ll

llvm/test/CodeGen/AMDGPU/nsa-reassign.ll

llvm/test/CodeGen/AMDGPU/nsa-vmem-hazard.mir

llvm/test/CodeGen/AMDGPU/offset-split-flat.ll

llvm/test/CodeGen/AMDGPU/offset-split-global.ll

llvm/test/CodeGen/AMDGPU/or.ll

llvm/test/CodeGen/AMDGPU/postra-bundle-memops.mir

llvm/test/CodeGen/AMDGPU/reassoc-scalar.ll

llvm/test/CodeGen/AMDGPU/s_addk_i32.ll

llvm/test/CodeGen/AMDGPU/s_mulk_i32.ll

llvm/test/CodeGen/AMDGPU/saddo.ll

llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll

llvm/test/CodeGen/AMDGPU/select.f16.ll

llvm/test/CodeGen/AMDGPU/setcc-limit-load-shrink.ll

llvm/test/CodeGen/AMDGPU/shl.v2i16.ll

llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll

llvm/test/CodeGen/AMDGPU/si-lower-control-flow.mir

llvm/test/CodeGen/AMDGPU/sign_extend.ll

llvm/test/CodeGen/AMDGPU/smed3.ll

llvm/test/CodeGen/AMDGPU/smrd.ll

llvm/test/CodeGen/AMDGPU/spill-special-sgpr.mir

llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr.ll

llvm/test/CodeGen/AMDGPU/spill192.mir

llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll

llvm/test/CodeGen/AMDGPU/sub.v2i16.ll

llvm/test/CodeGen/AMDGPU/trunc-combine.ll

llvm/test/CodeGen/AMDGPU/umed3.ll

llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll

llvm/test/CodeGen/AMDGPU/vgpr-descriptor-waterfall-loop-idom-update.ll

llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll

llvm/test/CodeGen/AMDGPU/virtregrewrite-undef-identity-copy.mir

llvm/test/CodeGen/AMDGPU/waitcnt-overflow.mir

llvm/test/CodeGen/AMDGPU/waitcnt-vmem-waw.mir

llvm/test/CodeGen/AMDGPU/wwm-reserved.ll

llvm/test/CodeGen/AMDGPU/xnack-subtarget-feature-any.ll

llvm/test/CodeGen/AMDGPU/xor.ll

llvm/test/CodeGen/AMDGPU/zero_extend.ll

llvm/test/MC/AMDGPU/xnack-mask.s