[ARM] Enabled VMLAV and Add instructions to use VMLAVA

[MeeraN]

Summary

Used InstCombine to enable VMLAV and Add instructions to generate VMLAVA instead with regression tests.

[dmgreen]

llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp

216

Can you quickly run clang-format on the patch too

219

I think here you don't need the cast<Value>, if user is already an Instruction.

[spatel]

llvm/test/Transforms/InstCombine/ARM/vmldava.ll

3

This is not the right test file for this patch?

[MeeraN]

Changed tests to show original IR (vmlav and add instructions) being transformed to use vmlava, run using opt -instcombine -S -mtriple=arm -o - %s instead.

[dmgreen]

This seems good to me.

The part I am a little unsure about is that it is converting add(vmlav) into a new vmlava, but we are starting at the vmlav to do it. So need to set the insertion point and use replaceAllUsesWith/eraseInstFromFunction. I couldn't find anything else that worked like that in instcombine, but maybe just missed it. It seems to work just fine like this, but it might be cause potential problems with the way instcombine iterates? It hasn't caused any problems we have seen though.

I think this is good, but give it a day or two before committing in case anyone knows that this will be a problem.

[spatel]

In D85825#2215592, @dmgreen wrote:

The part I am a little unsure about is that it is converting add(vmlav) into a new vmlava, but we are starting at the vmlav to do it. So need to set the insertion point and use replaceAllUsesWith/eraseInstFromFunction. I couldn't find anything else that worked like that in instcombine, but maybe just missed it. It seems to work just fine like this, but it might be cause potential problems with the way instcombine iterates? It hasn't caused any problems we have seen though.

Yes, this is not the typical code construct for instcombine. But given that we've (finally!) moved the target-specific combines out of the generic code files, I think this is the only way to match this kind of pattern.
There are similar constructs for generic patterns with phi ops and load/store, so this should be good too.

[MeeraN]

Closed by revision https://reviews.llvm.org/rG545de56f87f5

llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp

 bool ARMTTIImpl::shouldFavorPostInc() const {
   if (ST->hasMVEIntegerOps())
     return true;
   return false;
 }
 
 Optional<Instruction *>
 ARMTTIImpl::instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const {
+  using namespace PatternMatch;
   Intrinsic::ID IID = II.getIntrinsicID();
   switch (IID) {
   default:
     break;
   case Intrinsic::arm_neon_vld1: {
     Align MemAlign =
         getKnownAlignment(II.getArgOperand(0), IC.getDataLayout(), &II,
                           &IC.getAssumptionCache(), &IC.getDominatorTree());
case Intrinsic::arm_mve_vadc_predicated: {
 
     KnownBits CarryKnown(32);
     if (IC.SimplifyDemandedBits(&II, CarryOp, APInt::getOneBitSet(32, 29),
                                 CarryKnown)) {
       return &II;
     }
     break;
   }
+  case Intrinsic::arm_mve_vmldava: {
+    Instruction *I = cast<Instruction>(&II);
+    if (I->hasOneUse()) {
+      auto *User = cast<Instruction>(*I->user_begin());
+      Value *OpZ;
+      if (match(User, m_c_Add(m_Specific(I), m_Value(OpZ))) &&
+          match(I->getOperand(3), m_Zero())) {
+        Value *OpX = I->getOperand(4);
+        Value *OpY = I->getOperand(5);
+        Type *OpTy = OpX->getType();
+
+        IC.Builder.SetInsertPoint(User);
+        Value *V =
+            IC.Builder.CreateIntrinsic(Intrinsic::arm_mve_vmldava, {OpTy},
+                                       {I->getOperand(0), I->getOperand(1),
+                                        I->getOperand(2), OpZ, OpX, OpY});
+
+        IC.replaceInstUsesWith(*User, V);
+        return IC.eraseInstFromFunction(*User);
+      }
+    }
+    return None;
+  }
   }
   return None;
 }
 
 int ARMTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty,
                               TTI::TargetCostKind CostKind) {
   assert(Ty->isIntegerTy());
 

llvm/test/Transforms/InstCombine/ARM/vmldava.ll

+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -instcombine -S -mtriple=arm -o - %s | FileCheck %s
+
+target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
+
+define arm_aapcs_vfpcc i32 @test_vmladavaq_s32(i32 %z, <4 x i32> %x, <4 x i32> %y) {
+; CHECK-LABEL: @test_vmladavaq_s32(
+; CHECK-NEXT:  entry: 
+; CHECK-NEXT:  %0 = call i32 @llvm.arm.mve.vmldava.v4i32(i32 0, i32 0, i32 0, i32 %z, <4 x i32> %x, <4 x i32> %y)
+; CHECK-NEXT:  ret i32 %0
+entry:
+  %0 = tail call i32 @llvm.arm.mve.vmldava.v4i32(i32 0, i32 0, i32 0, i32 0, <4 x i32> %x, <4 x i32> %y)
+  %1 = add nsw i32 %0, %z
+  ret i32 %1
+}
+
+define arm_aapcs_vfpcc i32 @test_vmladavaq_s16(i32 %z, <8 x i16> %x, <8 x i16> %y) {
+; CHECK-LABEL: @test_vmladavaq_s16(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:  %0 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 0, i32 0, i32 0, i32 %z, <8 x i16> %x, <8 x i16> %y)
+; CHECK-NEXT:  ret i32 %0
+entry:
+  %0 = tail call i32 @llvm.arm.mve.vmldava.v8i16(i32 0, i32 0, i32 0, i32 0, <8 x i16> %x, <8 x i16> %y)
+  %1 = add nsw i32 %0, %z
+  ret i32 %1
+}
+
+define arm_aapcs_vfpcc i32 @test_vmladavaq_s8(i32 %z, <16 x i8> %x, <16 x i8> %y) {
+; CHECK-LABEL: @test_vmladavaq_s8(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:  %0 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 0, i32 0, i32 0, i32 %z, <16 x i8> %x, <16 x i8> %y)
+; CHECK-NEXT:  ret i32 %0
+entry:
+  %0 = tail call i32 @llvm.arm.mve.vmldava.v16i8(i32 0, i32 0, i32 0, i32 0, <16 x i8> %x, <16 x i8> %y)
+  %1 = add nsw i32 %0, %z
+  ret i32 %1
+}
+
+define arm_aapcs_vfpcc i32 @test_vmladavaq_u32(i32 %z, <4 x i32> %x, <4 x i32> %y) {
+; CHECK-LABEL: @test_vmladavaq_u32(
+; CHECK-NEXT:  entry: 
+; CHECK-NEXT:  %0 = call i32 @llvm.arm.mve.vmldava.v4i32(i32 1, i32 0, i32 0, i32 %z, <4 x i32> %x, <4 x i32> %y)
+; CHECK-NEXT:  ret i32 %0
+entry:
+  %0 = tail call i32 @llvm.arm.mve.vmldava.v4i32(i32 1, i32 0, i32 0, i32 0, <4 x i32> %x, <4 x i32> %y)
+  %1 = add nsw i32 %0, %z
+  ret i32 %1
+}
+
+define arm_aapcs_vfpcc i32 @test_vmladavaq_u16(i32 %z, <8 x i16> %x, <8 x i16> %y) {
+; CHECK-LABEL: @test_vmladavaq_u16(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:  %0 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 1, i32 0, i32 0, i32 %z, <8 x i16> %x, <8 x i16> %y)
+; CHECK-NEXT:  ret i32 %0
+entry:
+  %0 = tail call i32 @llvm.arm.mve.vmldava.v8i16(i32 1, i32 0, i32 0, i32 0, <8 x i16> %x, <8 x i16> %y)
+  %1 = add nsw i32 %0, %z
+  ret i32 %1
+}
+
+define arm_aapcs_vfpcc i32 @test_vmladavaq_u8(i32 %z, <16 x i8> %x, <16 x i8> %y) {
+; CHECK-LABEL: @test_vmladavaq_u8(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:  %0 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 1, i32 0, i32 0, i32 %z, <16 x i8> %x, <16 x i8> %y)
+; CHECK-NEXT:  ret i32 %0
+entry:
+  %0 = tail call i32 @llvm.arm.mve.vmldava.v16i8(i32 1, i32 0, i32 0, i32 0, <16 x i8> %x, <16 x i8> %y)
+  %1 = add nsw i32 %0, %z
+  ret i32 %1
+}
+
+define arm_aapcs_vfpcc i32 @test_vmlsdavaq_s32(i32 %z, <4 x i32> %x, <4 x i32> %y) {
+; CHECK-LABEL: @test_vmlsdavaq_s32(
+; CHECK-NEXT:  entry: 
+; CHECK-NEXT:  %0 = call i32 @llvm.arm.mve.vmldava.v4i32(i32 0, i32 1, i32 0, i32 %z, <4 x i32> %x, <4 x i32> %y)
+; CHECK-NEXT:  ret i32 %0
+entry:
+  %0 = tail call i32 @llvm.arm.mve.vmldava.v4i32(i32 0, i32 1, i32 0, i32 0, <4 x i32> %x, <4 x i32> %y)
+  %1 = add nsw i32 %0, %z
+  ret i32 %1
+}
+
+define arm_aapcs_vfpcc i32 @test_vmlsdavaq_s16(i32 %z, <8 x i16> %x, <8 x i16> %y) {
+; CHECK-LABEL: @test_vmlsdavaq_s16(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:  %0 = call i32 @llvm.arm.mve.vmldava.v8i16(i32 0, i32 1, i32 0, i32 %z, <8 x i16> %x, <8 x i16> %y)
+; CHECK-NEXT:  ret i32 %0
+entry:
+  %0 = tail call i32 @llvm.arm.mve.vmldava.v8i16(i32 0, i32 1, i32 0, i32 0, <8 x i16> %x, <8 x i16> %y)
+  %1 = add nsw i32 %0, %z
+  ret i32 %1
+}
+
+define arm_aapcs_vfpcc i32 @test_vmlsdavaq_s8(i32 %z, <16 x i8> %x, <16 x i8> %y) {
+; CHECK-LABEL: @test_vmlsdavaq_s8(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:  %0 = call i32 @llvm.arm.mve.vmldava.v16i8(i32 0, i32 1, i32 0, i32 %z, <16 x i8> %x, <16 x i8> %y)
+; CHECK-NEXT:  ret i32 %0
+entry:
+  %0 = tail call i32 @llvm.arm.mve.vmldava.v16i8(i32 0, i32 1, i32 0, i32 0, <16 x i8> %x, <16 x i8> %y)
+  %1 = add nsw i32 %0, %z
+  ret i32 %1
+}
+
+declare i32 @llvm.arm.mve.vmldava.v4i32(i32, i32, i32, i32, <4 x i32>, <4 x i32>)
+declare i32 @llvm.arm.mve.vmldava.v8i16(i32, i32, i32, i32, <8 x i16>, <8 x i16>)
+declare i32 @llvm.arm.mve.vmldava.v16i8(i32, i32, i32, i32, <16 x i8>, <16 x i8>)