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[SVE] Lower fixed length integer extend operations.
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Authored by paulwalker-arm on Aug 10 2020, 5:19 AM.

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paulwalker-arm created this revision.Aug 10 2020, 5:19 AM
paulwalker-arm requested review of this revision.Aug 10 2020, 5:19 AM

Slightly more complicated than expected, hence why I broke out D85546. I needed to custom lower ANY_EXTEND and SIGNED_EXTEND_INREG for the test named sext_v4i8_v4i64.

paulwalker-arm planned changes to this revision.Aug 10 2020, 7:55 AM

Sorry I pushed too soon, I've yet to add the zext tests.

Added zext tests.

efriedma added inline comments.Aug 10 2020, 12:39 PM
llvm/test/CodeGen/AArch64/sve-fixed-length-int-extends.ll
99

Maybe worth adding a couple CHECK lines for sext_v16i8_v16i32 if the fixed vector width is 256, to make sure we do something sane if we need to legalize the result type?

Added VBITS_EQ_256 check lines for sext_v16i8_v16i32 and zext_v16i8_v16i32.

This revision is now accepted and ready to land.Aug 11 2020, 4:37 PM
This revision was landed with ongoing or failed builds.Aug 13 2020, 3:56 AM
This revision was automatically updated to reflect the committed changes.