Index: llvm/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h =================================================================== --- llvm/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h +++ llvm/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h @@ -251,7 +251,8 @@ MCSection * getSectionForFunctionDescriptor(const Function *F, const TargetMachine &TM) const override; - MCSection *getSectionForTOCEntry(const MCSymbol *Sym) const override; + MCSection *getSectionForTOCEntry(const MCSymbol *Sym, + const TargetMachine &TM) const override; /// For external functions, this will always return a function descriptor /// csect. Index: llvm/include/llvm/Target/TargetLoweringObjectFile.h =================================================================== --- llvm/include/llvm/Target/TargetLoweringObjectFile.h +++ llvm/include/llvm/Target/TargetLoweringObjectFile.h @@ -226,7 +226,8 @@ /// On targets that support TOC entries, return a section for the entry given /// the symbol it refers to. /// TODO: Implement this interface for existing ELF targets. - virtual MCSection *getSectionForTOCEntry(const MCSymbol *S) const { + virtual MCSection *getSectionForTOCEntry(const MCSymbol *S, + const TargetMachine &TM) const { return nullptr; } Index: llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp =================================================================== --- llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp +++ llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp @@ -2195,8 +2195,11 @@ } MCSection *TargetLoweringObjectFileXCOFF::getSectionForTOCEntry( - const MCSymbol *Sym) const { + const MCSymbol *Sym, const TargetMachine &TM) const { + // Use TE storage-mapping class when large code model is enabled so that + // the chance of needing -bbigtoc is decreased. return getContext().getXCOFFSection( - cast(Sym)->getSymbolTableName(), XCOFF::XMC_TC, + cast(Sym)->getSymbolTableName(), + TM.getCodeModel() == CodeModel::Large ? XCOFF::XMC_TE : XCOFF::XMC_TC, XCOFF::XTY_SD, XCOFF::C_HIDEXT, SectionKind::getData()); } Index: llvm/lib/MC/MCSectionXCOFF.cpp =================================================================== --- llvm/lib/MC/MCSectionXCOFF.cpp +++ llvm/lib/MC/MCSectionXCOFF.cpp @@ -45,6 +45,7 @@ printCsectDirective(OS); break; case XCOFF::XMC_TC: + case XCOFF::XMC_TE: break; case XCOFF::XMC_TC0: OS << "\t.toc\n"; Index: llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp =================================================================== --- llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp +++ llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp @@ -20,8 +20,8 @@ #include "llvm/ADT/StringRef.h" #include "llvm/ADT/Triple.h" #include "llvm/BinaryFormat/ELF.h" -#include "llvm/MC/MCAssembler.h" #include "llvm/MC/MCAsmBackend.h" +#include "llvm/MC/MCAssembler.h" #include "llvm/MC/MCCodeEmitter.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCDwarf.h" @@ -30,6 +30,7 @@ #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCObjectWriter.h" #include "llvm/MC/MCRegisterInfo.h" +#include "llvm/MC/MCSectionXCOFF.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCSymbol.h" @@ -122,8 +123,8 @@ void emitTCEntry(const MCSymbol &S) override { if (const MCSymbolXCOFF *XSym = dyn_cast(&S)) { MCSymbolXCOFF *TCSym = - cast(Streamer.getContext().getOrCreateSymbol( - XSym->getSymbolTableName() + "[TC]")); + cast(Streamer.getCurrentSectionOnly()) + ->getQualNameSymbol(); OS << "\t.tc " << TCSym->getName() << "," << XSym->getName() << '\n'; if (TCSym->hasRename()) Index: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp =================================================================== --- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp +++ llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp @@ -1817,7 +1817,7 @@ for (auto &I : TOC) { // Setup the csect for the current TC entry. MCSectionXCOFF *TCEntry = cast( - getObjFileLowering().getSectionForTOCEntry(I.first)); + getObjFileLowering().getSectionForTOCEntry(I.first, TM)); OutStreamer->SwitchSection(TCEntry); OutStreamer->emitLabel(I.second); Index: llvm/test/CodeGen/PowerPC/aix-lower-block-address.ll =================================================================== --- llvm/test/CodeGen/PowerPC/aix-lower-block-address.ll +++ llvm/test/CodeGen/PowerPC/aix-lower-block-address.ll @@ -15,16 +15,16 @@ ; RUN: --check-prefix=64LARGE-MIR %s ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \ -; RUN: -code-model=small < %s | FileCheck --check-prefixes=32SMALL-ASM,CHECK %s +; RUN: -code-model=small < %s | FileCheck --check-prefixes=32SMALL-ASM,SMALL-ASM %s ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \ -; RUN: -code-model=large < %s | FileCheck --check-prefixes=32LARGE-ASM,CHECK %s +; RUN: -code-model=large < %s | FileCheck --check-prefixes=32LARGE-ASM,LARGE-ASM %s ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \ -; RUN: -code-model=small < %s | FileCheck --check-prefixes=64SMALL-ASM,CHECK %s +; RUN: -code-model=small < %s | FileCheck --check-prefixes=64SMALL-ASM,SMALL-ASM %s ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \ -; RUN: -code-model=large < %s | FileCheck --check-prefixes=64LARGE-ASM,CHECK %s +; RUN: -code-model=large < %s | FileCheck --check-prefixes=64LARGE-ASM,LARGE-ASM %s define void @foo() { entry: @@ -68,5 +68,8 @@ ; 64LARGE-ASM: addis [[REG1:[0-9]+]], L..C0@u(2) ; 64LARGE-ASM: ld [[REG2:[0-9]+]], L..C0@l([[REG1]]) -; CHECK: .toc -; CHECK: .tc L..tmp0[TC],L..tmp0 +; SMALL-ASM: .toc +; SMALL-ASM: .tc L..tmp0[TC],L..tmp0 + +; LARGE-ASM: .toc +; LARGE-ASM: .tc L..tmp0[TE],L..tmp0 Index: llvm/test/CodeGen/PowerPC/aix-lower-constant-pool-index.ll =================================================================== --- llvm/test/CodeGen/PowerPC/aix-lower-constant-pool-index.ll +++ llvm/test/CodeGen/PowerPC/aix-lower-constant-pool-index.ll @@ -15,16 +15,16 @@ ; RUN: --check-prefix=64LARGE-MIR %s ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \ -; RUN: -code-model=small < %s | FileCheck --check-prefixes=32SMALL-ASM,CHECK %s +; RUN: -code-model=small < %s | FileCheck --check-prefixes=32SMALL-ASM,SMALL-ASM %s ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \ -; RUN: -code-model=large < %s | FileCheck --check-prefixes=32LARGE-ASM,CHECK %s +; RUN: -code-model=large < %s | FileCheck --check-prefixes=32LARGE-ASM,LARGE-ASM %s ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \ -; RUN: -code-model=small < %s | FileCheck --check-prefixes=64SMALL-ASM,CHECK %s +; RUN: -code-model=small < %s | FileCheck --check-prefixes=64SMALL-ASM,SMALL-ASM %s ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \ -; RUN: -code-model=large < %s | FileCheck --check-prefixes=64LARGE-ASM,CHECK %s +; RUN: -code-model=large < %s | FileCheck --check-prefixes=64LARGE-ASM,LARGE-ASM %s define float @test_float() { entry: @@ -83,5 +83,8 @@ ; 64LARGE-ASM: lfs 1, 0([[REG2]]) ; 64LARGE-ASM: blr -; CHECK: .toc -; CHECK: .tc L..CPI0_0[TC],L..CPI0_0 +; SMALL-ASM: .toc +; SMALL-ASM: .tc L..CPI0_0[TC],L..CPI0_0 + +; LARGE-ASM: .toc +; LARGE-ASM: .tc L..CPI0_0[TE],L..CPI0_0 Index: llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll =================================================================== --- llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll +++ llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll @@ -15,16 +15,16 @@ ; RUN: --check-prefix=64LARGE-MIR %s ; RUN: llc -mtriple powerpc-ibm-aix-xcoff -code-model=small < %s | FileCheck \ -; RUN: --check-prefixes=32SMALL-ASM,CHECK %s +; RUN: --check-prefixes=32SMALL-ASM,SMALL-ASM %s ; RUN: llc -mtriple powerpc-ibm-aix-xcoff -code-model=large < %s | FileCheck \ -; RUN: --check-prefixes=32LARGE-ASM,CHECK %s +; RUN: --check-prefixes=32LARGE-ASM,LARGE-ASM %s ; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -code-model=small < %s | FileCheck \ -; RUN: --check-prefixes=64SMALL-ASM,CHECK %s +; RUN: --check-prefixes=64SMALL-ASM,SMALL-ASM %s ; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -code-model=large < %s | FileCheck \ -; RUN: --check-prefixes=64LARGE-ASM,CHECK %s +; RUN: --check-prefixes=64LARGE-ASM,LARGE-ASM %s define i32 @jump_table(i32 %a) { entry: @@ -184,5 +184,8 @@ ; 64LARGE-ASM: .vbyte 4, L..BB0_4-L..JTI0_0 ; 64LARGE-ASM: .vbyte 4, L..BB0_5-L..JTI0_0 -; CHECK: .toc -; CHECK: .tc L..JTI0_0[TC],L..JTI0_0 +; SMALL-ASM: .toc +; SMALL-ASM: .tc L..JTI0_0[TC],L..JTI0_0 + +; LARGE-ASM: .toc +; LARGE-ASM: .tc L..JTI0_0[TE],L..JTI0_0 Index: llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix-asm.ll =================================================================== --- llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix-asm.ll +++ llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix-asm.ll @@ -1,8 +1,8 @@ ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \ -; RUN: -code-model=small < %s | FileCheck %s --check-prefixes=CHECK,SMALL +; RUN: -code-model=small < %s | FileCheck %s --check-prefix=SMALL ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \ -; RUN: -code-model=large < %s | FileCheck %s --check-prefixes=CHECK,LARGE +; RUN: -code-model=large < %s | FileCheck %s --check-prefix=LARGE @a = common global i32 0 @@ -41,5 +41,8 @@ ; LARGE: stw [[REG3:[0-9]+]], 0([[REG2]]) ; LARGE: blr -; CHECK: .tc a[TC],a -; CHECK: .tc b[TC],b +; SMALL: .tc a[TC],a +; SMALL: .tc b[TC],b + +; LARGE: .tc a[TE],a +; LARGE: .tc b[TE],b Index: llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix-asm.ll =================================================================== --- llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix-asm.ll +++ llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix-asm.ll @@ -1,8 +1,8 @@ ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \ -; RUN: -code-model=small < %s | FileCheck %s --check-prefixes=CHECK,SMALL +; RUN: -code-model=small < %s | FileCheck %s --check-prefix=SMALL ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \ -; RUN: -code-model=large < %s | FileCheck %s --check-prefixes=CHECK,LARGE +; RUN: -code-model=large < %s | FileCheck %s --check-prefix=LARGE @a = common global i32 0 @@ -41,5 +41,8 @@ ; LARGE: stw [[REG3:[0-9]+]], 0([[REG2]]) ; LARGE: blr -; CHECK: .tc a[TC],a -; CHECK: .tc b[TC],b +; SMALL: .tc a[TC],a +; SMALL: .tc b[TC],b + +; LARGE: .tc a[TE],a +; LARGE: .tc b[TE],b