diff --git a/llvm/lib/Target/PowerPC/PPCBoolRetToInt.cpp b/llvm/lib/Target/PowerPC/PPCBoolRetToInt.cpp --- a/llvm/lib/Target/PowerPC/PPCBoolRetToInt.cpp +++ b/llvm/lib/Target/PowerPC/PPCBoolRetToInt.cpp @@ -90,6 +90,9 @@ // Translate a i1 value to an equivalent i32/i64 value: Value *translate(Value *V) { + assert(V->getType() == Type::getInt1Ty(V->getContext()) && + "Expect an i1 value"); + Type *IntTy = ST->isPPC64() ? Type::getInt64Ty(V->getContext()) : Type::getInt32Ty(V->getContext()); @@ -227,8 +230,9 @@ // CallInst. Potentially, bitwise operations (AND, OR, XOR, NOT) and sign // extension could also be handled in the future. for (Value *V : Defs) - if (!isa(V) && !isa(V) && - !isa(V) && !isa(V)) + if ((!isa(V) && !isa(V) && !isa(V) && + !isa(V)) || + isa(V)) return false; for (Value *V : Defs) diff --git a/llvm/test/CodeGen/PowerPC/pr46923.ll b/llvm/test/CodeGen/PowerPC/pr46923.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/pr46923.ll @@ -0,0 +1,31 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \ +; RUN: -ppc-asm-full-reg-names < %s | FileCheck %s + +@bar = external constant i64, align 8 + +define i1 @foo() { +; CHECK-LABEL: foo: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: crxor 4*cr5+lt, 4*cr5+lt, 4*cr5+lt +; CHECK-NEXT: li r3, 0 +; CHECK-NEXT: li r4, 1 +; CHECK-NEXT: isel r3, r4, r3, 4*cr5+lt +; CHECK-NEXT: blr +entry: + br label %next + +next: + br i1 undef, label %true, label %false + +true: + br label %end + +false: + br label %end + +end: + %a = phi i1 [ icmp ugt (i64 0, i64 ptrtoint (i64* @bar to i64)), %true ], + [ icmp ugt (i64 0, i64 2), %false ] + ret i1 %a +}