[PowerPC] Handle SUBFIC in reg+reg -> reg+imm transformation

[nemanjai]

Summary

We initially missed the subtract-immediate in this transformation. This patch just adds that.

[foad]

Looks great to me, but probably needs a PowerPC expert to look at it too.

[lkail]

LGTM.

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

case PPC::ADDI8: {
     if (isInt<16>(Addend + SExtImm)) {
       ReplaceWithLI = true;
       Is64BitLI = Opc == PPC::ADDI8;
       NewImm = Addend + SExtImm;
       break;
     }
     return false;
   }
+  case PPC::SUBFIC:
+  case PPC::SUBFIC8: {
+    // Only transform this if the CARRY implicit operand is dead.
+    if (MI.getNumOperands() > 3 && !MI.getOperand(3).isDead())
+      return false;
+    int64_t Minuend = MI.getOperand(2).getImm();
+    if (isInt<16>(Minuend - SExtImm)) {
+      ReplaceWithLI = true;
+      Is64BitLI = Opc == PPC::SUBFIC8;
+      NewImm = Minuend - SExtImm;
+      break;
+    }
+    return false;
+  }
   case PPC::RLDICL:
   case PPC::RLDICL_rec:
   case PPC::RLDICL_32:
   case PPC::RLDICL_32_64: {
     // Use APInt's rotate function.
     int64_t SH = MI.getOperand(2).getImm();
     int64_t MB = MI.getOperand(3).getImm();
     APInt InVal((Opc == PPC::RLDICL || Opc == PPC::RLDICL_rec) ? 64 : 32,

llvm/test/CodeGen/PowerPC/pr44183.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:     -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
 %struct.m.2.5.8.11 = type { %struct.l.0.3.6.9, [7 x i8], %struct.a.1.4.7.10 }
 %struct.l.0.3.6.9 = type { i8 }
 %struct.a.1.4.7.10 = type { [27 x i8], [0 x i32], [4 x i8] }
 define void @_ZN1m1nEv(%struct.m.2.5.8.11* %this) local_unnamed_addr nounwind align 2 {
 ; CHECK-LABEL: _ZN1m1nEv:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mflr r0
-; CHECK-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r0, 16(r1)
-; CHECK-NEXT:    stdu r1, -64(r1)
+; CHECK-NEXT:    stdu r1, -48(r1)
 ; CHECK-NEXT:    mr r30, r3
-; CHECK-NEXT:    li r3, 4
 ; CHECK-NEXT:    ld r4, 16(r30)
 ; CHECK-NEXT:    ld r5, 8(r30)
-; CHECK-NEXT:    subfic r29, r3, 64
-; CHECK-NEXT:    rldicl r3, r5, 60, 4
-; CHECK-NEXT:    sld r4, r4, r29
-; CHECK-NEXT:    lwz r5, 36(r30)
-; CHECK-NEXT:    or r3, r4, r3
-; CHECK-NEXT:    rlwinm r3, r3, 31, 0, 0
-; CHECK-NEXT:    clrlwi r4, r5, 31
+; CHECK-NEXT:    lwz r6, 36(r30)
+; CHECK-NEXT:    rldicl r5, r5, 60, 4
+; CHECK-NEXT:    sldi r4, r4, 60
+; CHECK-NEXT:    or r4, r4, r5
+; CHECK-NEXT:    rlwinm r3, r4, 31, 0, 0
+; CHECK-NEXT:    clrlwi r4, r6, 31
 ; CHECK-NEXT:    or r4, r4, r3
 ; CHECK-NEXT:    bl _ZN1llsE1d
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    ld r3, 16(r30)
 ; CHECK-NEXT:    ld r4, 8(r30)
 ; CHECK-NEXT:    rldicl r4, r4, 60, 4
-; CHECK-NEXT:    sld r3, r3, r29
+; CHECK-NEXT:    sldi r3, r3, 60
 ; CHECK-NEXT:    or r3, r3, r4
 ; CHECK-NEXT:    sldi r3, r3, 31
 ; CHECK-NEXT:    clrldi r4, r3, 32
 ; CHECK-NEXT:    bl _ZN1llsE1d
 ; CHECK-NEXT:    nop
-; CHECK-NEXT:    addi r1, r1, 64
+; CHECK-NEXT:    addi r1, r1, 48
 ; CHECK-NEXT:    ld r0, 16(r1)
 ; CHECK-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
-; CHECK-NEXT:    ld r29, -24(r1) # 8-byte Folded Reload
 ; CHECK-NEXT:    mtlr r0
 ; CHECK-NEXT:    blr
 entry:
   %bc = getelementptr inbounds %struct.m.2.5.8.11, %struct.m.2.5.8.11* %this, i64 0, i32 2
   %0 = bitcast %struct.a.1.4.7.10* %bc to i216*
   %bf.load = load i216, i216* %0, align 8
   %bf.lshr = lshr i216 %bf.load, 4
   %shl.i23 = shl i216 %bf.lshr, 31