Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp =================================================================== --- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -288,11 +288,21 @@ SEW_1024, }; - enum class VLMUL { LMUL_1 = 0, LMUL_2, LMUL_4, LMUL_8 }; + enum class VLMUL { + LMUL_1 = 0, + LMUL_2, + LMUL_4, + LMUL_8, + LMUL_F8 = 5, + LMUL_F4, + LMUL_F2 + }; struct VTypeOp { VSEW Sew; VLMUL Lmul; + bool TailAgnostic; + bool MaskedoffAgnostic; unsigned Encoding; }; @@ -746,6 +756,8 @@ static StringRef getSEWStr(VSEW Sew) { switch (Sew) { + default: + llvm_unreachable("Unknown SEW."); case VSEW::SEW_8: return "e8"; case VSEW::SEW_16: @@ -763,11 +775,12 @@ case VSEW::SEW_1024: return "e1024"; } - return ""; } static StringRef getLMULStr(VLMUL Lmul) { switch (Lmul) { + default: + llvm_unreachable("Unknown LMUL."); case VLMUL::LMUL_1: return "m1"; case VLMUL::LMUL_2: @@ -776,8 +789,13 @@ return "m4"; case VLMUL::LMUL_8: return "m8"; + case VLMUL::LMUL_F2: + return "mf2"; + case VLMUL::LMUL_F4: + return "mf4"; + case VLMUL::LMUL_F8: + return "mf8"; } - return ""; } StringRef getVType(SmallString<32> &Buf) const { @@ -852,15 +870,31 @@ return Op; } - static std::unique_ptr createVType(APInt Sew, APInt Lmul, - SMLoc S, bool IsRV64) { + static std::unique_ptr + createVType(APInt Sew, APInt Lmul, bool Fractional, bool TailAgnostic, + bool MaskedoffAgnostic, SMLoc S, bool IsRV64) { auto Op = std::make_unique(KindTy::VType); Sew.ashrInPlace(3); unsigned SewLog2 = Sew.logBase2(); unsigned LmulLog2 = Lmul.logBase2(); Op->VType.Sew = static_cast(SewLog2); - Op->VType.Lmul = static_cast(LmulLog2); - Op->VType.Encoding = (SewLog2 << 2) | LmulLog2; + if (Fractional) { + unsigned Flmul = 8 - LmulLog2; + Op->VType.Lmul = static_cast(Flmul); + Op->VType.Encoding = + ((Flmul & 0x4) << 3) | ((SewLog2 & 0x7) << 2) | (Flmul & 0x3); + } else { + Op->VType.Lmul = static_cast(LmulLog2); + Op->VType.Encoding = (SewLog2 << 2) | LmulLog2; + } + if (TailAgnostic) { + Op->VType.Encoding |= 0x40; + } + if (MaskedoffAgnostic) { + Op->VType.Encoding |= 0x80; + } + Op->VType.TailAgnostic = TailAgnostic; + Op->VType.MaskedoffAgnostic = MaskedoffAgnostic; Op->StartLoc = S; Op->IsRV64 = IsRV64; return Op; @@ -1181,8 +1215,10 @@ } case Match_InvalidVTypeI: { SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc(); - return Error(ErrorLoc, - "operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8]"); + return Error( + ErrorLoc, + "operand must be " + "e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]"); } case Match_InvalidVMaskRegister: { SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc(); @@ -1549,7 +1585,7 @@ if (getLexer().getKind() != AsmToken::Identifier) return MatchOperand_NoMatch; - // Parse "e8,m1" + // Parse "e8,m1,t[a|u],m[a|u]" StringRef Name = getLexer().getTok().getIdentifier(); if (!Name.consume_front("e")) return MatchOperand_NoMatch; @@ -1559,13 +1595,6 @@ return MatchOperand_NoMatch; getLexer().Lex(); - if (getLexer().getKind() == AsmToken::EndOfStatement) { - Operands.push_back( - RISCVOperand::createVType(Sew, APInt(16, 1), S, isRV64())); - - return MatchOperand_Success; - } - if (!getLexer().is(AsmToken::Comma)) return MatchOperand_NoMatch; getLexer().Lex(); @@ -1573,15 +1602,51 @@ Name = getLexer().getTok().getIdentifier(); if (!Name.consume_front("m")) return MatchOperand_NoMatch; + // "m" or "mf" + bool Fractional = false; + if (Name.consume_front("f")) { + Fractional = true; + } APInt Lmul(16, Name, 10); if (Lmul != 1 && Lmul != 2 && Lmul != 4 && Lmul != 8) return MatchOperand_NoMatch; getLexer().Lex(); + if (!getLexer().is(AsmToken::Comma)) + return MatchOperand_NoMatch; + getLexer().Lex(); + + Name = getLexer().getTok().getIdentifier(); + // ta or tu + bool TailAgnostic; + if (Name.consume_front("ta")) + TailAgnostic = true; + else if (Name.consume_front("tu")) + TailAgnostic = false; + else + return MatchOperand_NoMatch; + getLexer().Lex(); + + if (!getLexer().is(AsmToken::Comma)) + return MatchOperand_NoMatch; + getLexer().Lex(); + + Name = getLexer().getTok().getIdentifier(); + // ma or mu + bool MaskedoffAgnostic; + if (Name.consume_front("ma")) + MaskedoffAgnostic = true; + else if (Name.consume_front("mu")) + MaskedoffAgnostic = false; + else + return MatchOperand_NoMatch; + getLexer().Lex(); + if (getLexer().getKind() != AsmToken::EndOfStatement) return MatchOperand_NoMatch; - Operands.push_back(RISCVOperand::createVType(Sew, Lmul, S, isRV64())); + Operands.push_back(RISCVOperand::createVType( + Sew, Lmul, Fractional, TailAgnostic, MaskedoffAgnostic, S, isRV64())); return MatchOperand_Success; } @@ -2281,71 +2346,41 @@ return false; unsigned DestReg = Inst.getOperand(0).getReg(); + unsigned CheckReg; // Operands[1] will be the first operand, DestReg. SMLoc Loc = Operands[1]->getStartLoc(); - if ((TargetFlags == RISCV::WidenV) || (TargetFlags == RISCV::WidenW) || - (TargetFlags == RISCV::SlideUp) || (TargetFlags == RISCV::Vrgather) || - (TargetFlags == RISCV::Vcompress)) { - if (TargetFlags != RISCV::WidenW) { - unsigned Src2Reg = Inst.getOperand(1).getReg(); - if (DestReg == Src2Reg) - return Error(Loc, "The destination vector register group cannot overlap" - " the source vector register group."); - if (TargetFlags == RISCV::WidenV) { - // Assume DestReg LMUL is 2 at least for widening/narrowing operations. - if (DestReg + 1 == Src2Reg) - return Error(Loc, - "The destination vector register group cannot overlap" - " the source vector register group."); - } - } - if (Inst.getOperand(2).isReg()) { - unsigned Src1Reg = Inst.getOperand(2).getReg(); - if (DestReg == Src1Reg) - return Error(Loc, "The destination vector register group cannot overlap" - " the source vector register group."); - if (TargetFlags == RISCV::WidenV || TargetFlags == RISCV::WidenW) { - // Assume DestReg LMUL is 2 at least for widening/narrowing operations. - if (DestReg + 1 == Src1Reg) - return Error(Loc, - "The destination vector register group cannot overlap" - " the source vector register group."); - } - } - if (Inst.getNumOperands() == 4) { - unsigned MaskReg = Inst.getOperand(3).getReg(); - - if (DestReg == MaskReg) - return Error(Loc, "The destination vector register group cannot overlap" - " the mask register."); - } - } else if (TargetFlags == RISCV::Narrow) { - unsigned Src2Reg = Inst.getOperand(1).getReg(); - if (DestReg == Src2Reg) + if (TargetFlags & RISCV::VS2Constraint) { + CheckReg = Inst.getOperand(1).getReg(); + if (DestReg == CheckReg) return Error(Loc, "The destination vector register group cannot overlap" " the source vector register group."); - // Assume Src2Reg LMUL is 2 at least for widening/narrowing operations. - if (DestReg == Src2Reg + 1) + } + if ((TargetFlags & RISCV::VS1Constraint) && (Inst.getOperand(2).isReg())) { + CheckReg = Inst.getOperand(2).getReg(); + if (DestReg == CheckReg) return Error(Loc, "The destination vector register group cannot overlap" " the source vector register group."); - } else if (TargetFlags == RISCV::WidenCvt || TargetFlags == RISCV::Iota) { - unsigned Src2Reg = Inst.getOperand(1).getReg(); - if (DestReg == Src2Reg) + } + if ((TargetFlags & RISCV::VMConstraint) && (DestReg == RISCV::V0)) { + // vadc, vsbc are special cases. These instructions have no mask register. + // The destination register could not be V0. + unsigned Opcode = Inst.getOpcode(); + if (Opcode == RISCV::VADC_VVM || Opcode == RISCV::VADC_VXM || + Opcode == RISCV::VADC_VIM || Opcode == RISCV::VSBC_VVM || + Opcode == RISCV::VSBC_VXM) + return Error(Loc, "The destination vector register group cannot be V0."); + + // Regardless masked or unmasked version, the number of operands is the + // same. For example, "viota.m v0, v2" is "viota.m v0, v2, NoRegister" + // actually. We need to check the last operand to ensure whether it is + // masked or not. + if ((TargetFlags & RISCV::OneInput) && (Inst.getNumOperands() == 3)) + CheckReg = Inst.getOperand(2).getReg(); + else if (Inst.getNumOperands() == 4) + CheckReg = Inst.getOperand(3).getReg(); + if (DestReg == CheckReg) return Error(Loc, "The destination vector register group cannot overlap" - " the source vector register group."); - if (TargetFlags == RISCV::WidenCvt) { - // Assume DestReg LMUL is 2 at least for widening/narrowing operations. - if (DestReg + 1 == Src2Reg) - return Error(Loc, "The destination vector register group cannot overlap" - " the source vector register group."); - } - if (Inst.getNumOperands() == 3) { - unsigned MaskReg = Inst.getOperand(2).getReg(); - - if (DestReg == MaskReg) - return Error(Loc, "The destination vector register group cannot overlap" - " the mask register."); - } + " the mask register."); } return false; } Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp =================================================================== --- llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp +++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp @@ -155,10 +155,28 @@ unsigned Imm = MI->getOperand(OpNo).getImm(); unsigned Sew = (Imm >> 2) & 0x7; unsigned Lmul = Imm & 0x3; + bool Fractional = (Imm >> 5) & 0x1; - Lmul = 0x1 << Lmul; Sew = 0x1 << (Sew + 3); - O << "e" << Sew << ",m" << Lmul; + O << "e" << Sew; + if (Fractional) { + Lmul = 4 - Lmul; + Lmul = 0x1 << Lmul; + O << ",mf" << Lmul; + } else { + Lmul = 0x1 << Lmul; + O << ",m" << Lmul; + } + bool TailAgnostic = Imm & 0x40; + bool MaskedoffAgnostic = Imm & 0x80; + if (TailAgnostic) + O << ",ta"; + else + O << ",tu"; + if (MaskedoffAgnostic) + O << ",ma"; + else + O << ",mu"; } void RISCVInstPrinter::printVMaskReg(const MCInst *MI, unsigned OpNo, Index: llvm/lib/Target/RISCV/RISCV.td =================================================================== --- llvm/lib/Target/RISCV/RISCV.td +++ llvm/lib/Target/RISCV/RISCV.td @@ -147,6 +147,13 @@ AssemblerPredicate<(all_of(not FeatureNoRVCHints)), "RVC Hint Instructions">; +def FeatureStdExtZvlsseg + : SubtargetFeature<"experimental-zvlsseg", "HasStdExtZvlsseg", "true", + "'Zvlsseg' (Vector segment load/store instructions)">; +def HasStdExtZvlsseg : Predicate<"Subtarget->hasStdExtZvlsseg()">, + AssemblerPredicate<(all_of FeatureStdExtZvlsseg), + "'Zvlsseg' (Vector segment load/store instructions)">; + def FeatureStdExtV : SubtargetFeature<"experimental-v", "HasStdExtV", "true", "'V' (Vector Instructions)", Index: llvm/lib/Target/RISCV/RISCVInstrFormats.td =================================================================== --- llvm/lib/Target/RISCV/RISCVInstrFormats.td +++ llvm/lib/Target/RISCV/RISCVInstrFormats.td @@ -52,15 +52,37 @@ class RISCVVConstraint val> { bits<4> Value = val; } -def NoConstraint : RISCVVConstraint<0>; -def WidenV : RISCVVConstraint<1>; -def WidenW : RISCVVConstraint<2>; -def WidenCvt : RISCVVConstraint<3>; -def Narrow : RISCVVConstraint<4>; -def Iota : RISCVVConstraint<5>; -def SlideUp : RISCVVConstraint<6>; -def Vrgather : RISCVVConstraint<7>; -def Vcompress : RISCVVConstraint<8>; +def NoConstraint : RISCVVConstraint<0b0000>; +def VS2Constraint : RISCVVConstraint<0b0001>; +def VS1Constraint : RISCVVConstraint<0b0010>; +def VMConstraint : RISCVVConstraint<0b0100>; +def OneInput : RISCVVConstraint<0b1000>; + +def WidenV : RISCVVConstraint; +def WidenW : RISCVVConstraint; +def WidenCvt : RISCVVConstraint; +def Narrow : RISCVVConstraint; +def NarrowCvt : RISCVVConstraint; +def Vmadc : RISCVVConstraint; +def Iota : RISCVVConstraint; +def SlideUp : RISCVVConstraint; +def Vrgather : RISCVVConstraint; +def Vcompress : RISCVVConstraint; // The following opcode names match those given in Table 19.1 in the // RISC-V User-level ISA specification ("RISC-V base opcode map"). Index: llvm/lib/Target/RISCV/RISCVInstrFormatsV.td =================================================================== --- llvm/lib/Target/RISCV/RISCVInstrFormatsV.td +++ llvm/lib/Target/RISCV/RISCVInstrFormatsV.td @@ -21,20 +21,17 @@ def OPFVF : RISCVVFormat<0b101>; def OPMVX : RISCVVFormat<0b110>; -class RISCVMOP val> { - bits<3> Value = val; +class RISCVMOP val> { + bits<2> Value = val; } -def MOPLDUnitStrideU : RISCVMOP<0b000>; -def MOPLDStridedU : RISCVMOP<0b010>; -def MOPLDIndexedU : RISCVMOP<0b011>; -def MOPLDUnitStrideS : RISCVMOP<0b100>; -def MOPLDStridedS : RISCVMOP<0b110>; -def MOPLDIndexedS : RISCVMOP<0b111>; - -def MOPSTUnitStride : RISCVMOP<0b000>; -def MOPSTStrided : RISCVMOP<0b010>; -def MOPSTIndexedOrder: RISCVMOP<0b011>; -def MOPSTIndexedUnOrd: RISCVMOP<0b111>; +def MOPLDUnitStride : RISCVMOP<0b00>; +def MOPLDStrided : RISCVMOP<0b10>; +def MOPLDIndexed : RISCVMOP<0b11>; + +def MOPSTUnitStride : RISCVMOP<0b00>; +def MOPSTIndexedUnord : RISCVMOP<0b01>; +def MOPSTStrided : RISCVMOP<0b10>; +def MOPSTIndexedOrder : RISCVMOP<0b11>; class RISCVLSUMOP val> { bits<5> Value = val; @@ -45,13 +42,17 @@ def SUMOPUnitStride : RISCVLSUMOP<0b00000>; def SUMOPUnitStrideWholeReg : RISCVLSUMOP<0b01000>; -class RISCVWidth val> { - bits<3> Value = val; +class RISCVWidth val> { + bits<4> Value = val; } -def LSWidthVByte : RISCVWidth<0b000>; -def LSWidthVHalf : RISCVWidth<0b101>; -def LSWidthVWord : RISCVWidth<0b110>; -def LSWidthVSEW : RISCVWidth<0b111>; +def LSWidth8 : RISCVWidth<0b0000>; +def LSWidth16 : RISCVWidth<0b0101>; +def LSWidth32 : RISCVWidth<0b0110>; +def LSWidth64 : RISCVWidth<0b0111>; +def LSWidth128 : RISCVWidth<0b1000>; +def LSWidth256 : RISCVWidth<0b1101>; +def LSWidth512 : RISCVWidth<0b1110>; +def LSWidth1024 : RISCVWidth<0b1111>; class RVInstSetVLi : RVInst { @@ -103,6 +104,7 @@ let Opcode = OPC_OP_V.Value; let Uses = [VTYPE, VL]; + let RVVConstraint = VMConstraint; } class RVInstVX funct6, RISCVVFormat opv, dag outs, dag ins, @@ -122,6 +124,7 @@ let Opcode = OPC_OP_V.Value; let Uses = [VTYPE, VL]; + let RVVConstraint = VMConstraint; } class RVInstV2 funct6, bits<5> vs2, RISCVVFormat opv, dag outs, dag ins, @@ -140,6 +143,7 @@ let Opcode = OPC_OP_V.Value; let Uses = [VTYPE, VL]; + let RVVConstraint = VMConstraint; } class RVInstIVI funct6, dag outs, dag ins, string opcodestr, @@ -159,6 +163,7 @@ let Opcode = OPC_OP_V.Value; let Uses = [VTYPE, VL]; + let RVVConstraint = VMConstraint; } class RVInstV funct6, bits<5> vs1, RISCVVFormat opv, dag outs, @@ -177,10 +182,11 @@ let Opcode = OPC_OP_V.Value; let Uses = [VTYPE, VL]; + let RVVConstraint = VMConstraint; } -class RVInstVLU nf, RISCVMOP mop, RISCVLSUMOP lumop, - RISCVWidth width, dag outs, dag ins, string opcodestr, +class RVInstVLU nf, bit mew, RISCVLSUMOP lumop, + bits<3> width, dag outs, dag ins, string opcodestr, string argstr> : RVInst { bits<5> rs1; @@ -188,18 +194,20 @@ bit vm; let Inst{31-29} = nf; - let Inst{28-26} = mop.Value; + let Inst{28} = mew; + let Inst{27-26} = MOPLDUnitStride.Value; let Inst{25} = vm; let Inst{24-20} = lumop.Value; let Inst{19-15} = rs1; - let Inst{14-12} = width.Value; + let Inst{14-12} = width; let Inst{11-7} = vd; let Opcode = OPC_LOAD_FP.Value; let Uses = [VTYPE, VL]; + let RVVConstraint = VMConstraint; } -class RVInstVLS nf, RISCVMOP mop, RISCVWidth width, +class RVInstVLS nf, bit mew, bits<3> width, dag outs, dag ins, string opcodestr, string argstr> : RVInst { bits<5> rs2; @@ -208,18 +216,20 @@ bit vm; let Inst{31-29} = nf; - let Inst{28-26} = mop.Value; + let Inst{28} = mew; + let Inst{27-26} = MOPLDStrided.Value; let Inst{25} = vm; let Inst{24-20} = rs2; let Inst{19-15} = rs1; - let Inst{14-12} = width.Value; + let Inst{14-12} = width; let Inst{11-7} = vd; let Opcode = OPC_LOAD_FP.Value; let Uses = [VTYPE, VL]; + let RVVConstraint = VMConstraint; } -class RVInstVLX nf, RISCVMOP mop, RISCVWidth width, +class RVInstVLX nf, bit mew, bits<3> width, dag outs, dag ins, string opcodestr, string argstr> : RVInst { bits<5> vs2; @@ -228,19 +238,21 @@ bit vm; let Inst{31-29} = nf; - let Inst{28-26} = mop.Value; + let Inst{28} = mew; + let Inst{27-26} = MOPLDIndexed.Value; let Inst{25} = vm; let Inst{24-20} = vs2; let Inst{19-15} = rs1; - let Inst{14-12} = width.Value; + let Inst{14-12} = width; let Inst{11-7} = vd; let Opcode = OPC_LOAD_FP.Value; let Uses = [VTYPE, VL]; + let RVVConstraint = VMConstraint; } -class RVInstVSU nf, RISCVMOP mop, RISCVLSUMOP sumop, - RISCVWidth width, dag outs, dag ins, string opcodestr, +class RVInstVSU nf, bit mew, RISCVLSUMOP sumop, + bits<3> width, dag outs, dag ins, string opcodestr, string argstr> : RVInst { bits<5> rs1; @@ -248,18 +260,19 @@ bit vm; let Inst{31-29} = nf; - let Inst{28-26} = mop.Value; + let Inst{28} = mew; + let Inst{27-26} = MOPSTUnitStride.Value; let Inst{25} = vm; let Inst{24-20} = sumop.Value; let Inst{19-15} = rs1; - let Inst{14-12} = width.Value; + let Inst{14-12} = width; let Inst{11-7} = vs3; let Opcode = OPC_STORE_FP.Value; let Uses = [VTYPE, VL]; } -class RVInstVSS nf, RISCVMOP mop, RISCVWidth width, +class RVInstVSS nf, bit mew, bits<3> width, dag outs, dag ins, string opcodestr, string argstr> : RVInst { bits<5> rs2; @@ -268,18 +281,19 @@ bit vm; let Inst{31-29} = nf; - let Inst{28-26} = mop.Value; + let Inst{28} = mew; + let Inst{27-26} = MOPSTStrided.Value; let Inst{25} = vm; let Inst{24-20} = rs2; let Inst{19-15} = rs1; - let Inst{14-12} = width.Value; + let Inst{14-12} = width; let Inst{11-7} = vs3; let Opcode = OPC_STORE_FP.Value; let Uses = [VTYPE, VL]; } -class RVInstVSX nf, RISCVMOP mop, RISCVWidth width, +class RVInstVSX nf, bit mew, RISCVMOP mop, bits<3> width, dag outs, dag ins, string opcodestr, string argstr> : RVInst { bits<5> vs2; @@ -288,11 +302,12 @@ bit vm; let Inst{31-29} = nf; - let Inst{28-26} = mop.Value; + let Inst{28} = mew; + let Inst{27-26} = mop.Value; let Inst{25} = vm; let Inst{24-20} = vs2; let Inst{19-15} = rs1; - let Inst{14-12} = width.Value; + let Inst{14-12} = width; let Inst{11-7} = vs3; let Opcode = OPC_STORE_FP.Value; Index: llvm/lib/Target/RISCV/RISCVInstrInfo.h =================================================================== --- llvm/lib/Target/RISCV/RISCVInstrInfo.h +++ llvm/lib/Target/RISCV/RISCVInstrInfo.h @@ -138,14 +138,53 @@ // Match with the definitions in RISCVInstrFormatsV.td enum RVVConstraintType { NoConstraint = 0, - WidenV = 1, - WidenW = 2, - WidenCvt = 3, - Narrow = 4, - Iota = 5, - SlideUp = 6, - Vrgather = 7, - Vcompress = 8, + VS2Constraint = 0b0001, + VS1Constraint = 0b0010, + VMConstraint = 0b0100, + OneInput = 0b1000, + + // Illegal instructions: + // + // * The destination vector register group for a masked vector instruction + // cannot overlap the source mask register (v0), unless the destination vector + // register is being written with a mask value (e.g., comparisons) or the + // scalar result of a reduction. + // + // * Widening: The destination vector register group cannot overlap a source + // vector register group of a different EEW + // + // * Narrowing: The destination vector register group cannot overlap the + // first source vector register group + // + // * For vadc and vsbc, an illegal instruction exception is raised if the + // destination vector register is v0. + // + // * For vmadc and vmsbc, an illegal instruction exception is raised if the + // destination vector register overlaps a source vector register group. + // + // * viota: An illegal instruction exception is raised if the destination + // vector register group overlaps the source vector mask register. If the + // instruction is masked, an illegal instruction exception is issued if the + // destination vector register group overlaps v0. + // + // * v[f]slide[1]up: The destination vector register group for vslideup cannot + // overlap the source vector register group. + // + // * vrgather: The destination vector register group cannot overlap with the + // source vector register groups. + // + // * vcompress: The destination vector register group cannot overlap the + // source vector register group or the source mask register + WidenV = VS2Constraint | VS1Constraint | VMConstraint, + WidenW = VS1Constraint | VMConstraint, + WidenCvt = VS2Constraint | VMConstraint | OneInput, + Narrow = VS2Constraint | VMConstraint, + NarrowCvt = VS2Constraint | VMConstraint | OneInput, + Vmadc = VS2Constraint | VS1Constraint, + Iota = VS2Constraint | VMConstraint | OneInput, + SlideUp = VS2Constraint | VMConstraint, + Vrgather = VS2Constraint | VS1Constraint | VMConstraint, + Vcompress = VS2Constraint | VS1Constraint, ConstraintOffset = 5, ConstraintMask = 0b1111 Index: llvm/lib/Target/RISCV/RISCVInstrInfoV.td =================================================================== --- llvm/lib/Target/RISCV/RISCVInstrInfoV.td +++ llvm/lib/Target/RISCV/RISCVInstrInfoV.td @@ -7,7 +7,7 @@ //===----------------------------------------------------------------------===// /// /// This file describes the RISC-V instructions from the standard 'V' Vector -/// extension, version 0.8. +/// extension, version 0.9. /// This version is still experimental as the 'V' extension hasn't been /// ratified yet. /// @@ -96,61 +96,105 @@ let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in { // load vd, (rs1), vm -class VUnitStrideLoad - : RVInstVLU<0b000, mop, lumop, width, (outs VRegOp:$vd), +class VUnitStrideLoad + : RVInstVLU<0b000, width.Value{3}, lumop, width.Value{2-0}, + (outs VRegOp:$vd), (ins GPR:$rs1, VMaskOp:$vm), opcodestr, "$vd, (${rs1})$vm">; // load vd, (rs1), rs2, vm -class VStridedLoad - : RVInstVLS<0b000, mop, width, (outs VRegOp:$vd), +class VStridedLoad + : RVInstVLS<0b000, width.Value{3}, width.Value{2-0}, + (outs VRegOp:$vd), (ins GPR:$rs1, GPR:$rs2, VMaskOp:$vm), opcodestr, "$vd, (${rs1}), $rs2$vm">; // load vd, (rs1), vs2, vm -class VIndexedLoad - : RVInstVLX<0b000, mop, width, (outs VRegOp:$vd), +class VIndexedLoad + : RVInstVLX<0b000, width.Value{3}, width.Value{2-0}, + (outs VRegOp:$vd), (ins GPR:$rs1, VRegOp:$vs2, VMaskOp:$vm), opcodestr, "$vd, (${rs1}), $vs2$vm">; // vlr.v vd, (rs1) class VWholeLoad nf, string opcodestr> - : RVInstVLU { let vm = 1; let Uses = []; } + +// segment load vd, (rs1), vm +class VUnitStrideSegmentLoad nf, RISCVLSUMOP lumop, + RISCVWidth width, string opcodestr> + : RVInstVLU; + +// segment load vd, (rs1), rs2, vm +class VStridedSegmentLoad nf, RISCVWidth width, string opcodestr> + : RVInstVLS; + + +// segment load vd, (rs1), vs2, vm +class VIndexedSegmentLoad nf, RISCVWidth width, string opcodestr> + : RVInstVLX; } // hasSideEffects = 0, mayLoad = 1, mayStore = 0 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in { // store vd, vs3, (rs1), vm -class VUnitStrideStore - : RVInstVSU<0b000, mop, sumop, width, (outs), - (ins VRegOp:$vs3, GPR:$rs1, VMaskOp:$vm), opcodestr, + : RVInstVSU<0b000, width.Value{3}, sumop, width.Value{2-0}, + (outs), (ins VRegOp:$vs3, GPR:$rs1, VMaskOp:$vm), opcodestr, "$vs3, (${rs1})$vm">; // store vd, vs3, (rs1), rs2, vm -class VStridedStore - : RVInstVSS<0b000, mop, width, (outs), +class VStridedStore + : RVInstVSS<0b000, width.Value{3}, width.Value{2-0}, (outs), (ins VRegOp:$vs3, GPR:$rs1, GPR:$rs2, VMaskOp:$vm), opcodestr, "$vs3, (${rs1}), $rs2$vm">; // store vd, vs3, (rs1), vs2, vm class VIndexedStore - : RVInstVSX<0b000, mop, width, (outs), + : RVInstVSX<0b000, width.Value{3}, mop, width.Value{2-0}, (outs), (ins VRegOp:$vs3, GPR:$rs1, VRegOp:$vs2, VMaskOp:$vm), opcodestr, "$vs3, (${rs1}), $vs2$vm">; // vsr.v vd, (rs1) class VWholeStore nf, string opcodestr> - : RVInstVSU { let vm = 1; let Uses = []; } + +// segment store vd, vs3, (rs1), vm +class VUnitStrideSegmentStore nf, RISCVLSUMOP sumop, + RISCVWidth width, string opcodestr> + : RVInstVSU; + +// segment store vd, vs3, (rs1), rs2, vm +class VStridedSegmentStore nf, RISCVWidth width, string opcodestr> + : RVInstVSS; + +// segment store vd, vs3, (rs1), vs2, vm +class VIndexedSegmentStore nf, RISCVMOP mop, RISCVWidth width, string opcodestr> + : RVInstVSX; } // hasSideEffects = 0, mayLoad = 0, mayStore = 1 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { @@ -372,68 +416,79 @@ } // hasSideEffects = 1, mayLoad = 0, mayStore = 0 // Vector Unit-Stride Instructions -def VLB_V : VUnitStrideLoad; -def VLH_V : VUnitStrideLoad; -def VLW_V : VUnitStrideLoad; - -def VLBU_V : VUnitStrideLoad; -def VLHU_V : VUnitStrideLoad; -def VLWU_V : VUnitStrideLoad; - -def VLE_V : VUnitStrideLoad; - -def VLBFF_V : VUnitStrideLoad; -def VLHFF_V : VUnitStrideLoad; -def VLWFF_V : VUnitStrideLoad; - -def VLBUFF_V : VUnitStrideLoad; -def VLHUFF_V : VUnitStrideLoad; -def VLWUFF_V : VUnitStrideLoad; - -def VLEFF_V : VUnitStrideLoad; - -def VSB_V : VUnitStrideStore; -def VSH_V : VUnitStrideStore; -def VSW_V : VUnitStrideStore; - -def VSE_V : VUnitStrideStore; +def VLE8_V : VUnitStrideLoad; +def VLE16_V : VUnitStrideLoad; +def VLE32_V : VUnitStrideLoad; +def VLE64_V : VUnitStrideLoad; +def VLE128_V : VUnitStrideLoad; +def VLE256_V : VUnitStrideLoad; +def VLE512_V : VUnitStrideLoad; +def VLE1024_V : VUnitStrideLoad; + +def VLE8FF_V : VUnitStrideLoad; +def VLE16FF_V : VUnitStrideLoad; +def VLE32FF_V : VUnitStrideLoad; +def VLE64FF_V : VUnitStrideLoad; +def VLE128FF_V : VUnitStrideLoad; +def VLE256FF_V : VUnitStrideLoad; +def VLE512FF_V : VUnitStrideLoad; +def VLE1024FF_V : VUnitStrideLoad; + +def VSE8_V : VUnitStrideStore; +def VSE16_V : VUnitStrideStore; +def VSE32_V : VUnitStrideStore; +def VSE64_V : VUnitStrideStore; +def VSE128_V : VUnitStrideStore; +def VSE256_V : VUnitStrideStore; +def VSE512_V : VUnitStrideStore; +def VSE1024_V : VUnitStrideStore; // Vector Strided Instructions -def VLSB_V : VStridedLoad; -def VLSH_V : VStridedLoad; -def VLSW_V : VStridedLoad; - -def VLSBU_V : VStridedLoad; -def VLSHU_V : VStridedLoad; -def VLSWU_V : VStridedLoad; - -def VLSE_V : VStridedLoad; - -def VSSB_V : VStridedStore; -def VSSH_V : VStridedStore; -def VSSW_V : VStridedStore; -def VSSE_V : VStridedStore; +def VLSE8_V : VStridedLoad; +def VLSE16_V : VStridedLoad; +def VLSE32_V : VStridedLoad; +def VLSE64_V : VStridedLoad; +def VLSE128_V : VStridedLoad; +def VLSE256_V : VStridedLoad; +def VLSE512_V : VStridedLoad; +def VLSE1024_V : VStridedLoad; + +def VSSE8_V : VStridedStore; +def VSSE16_V : VStridedStore; +def VSSE32_V : VStridedStore; +def VSSE64_V : VStridedStore; +def VSSE128_V : VStridedStore; +def VSSE256_V : VStridedStore; +def VSSE512_V : VStridedStore; +def VSSE1024_V : VStridedStore; // Vector Indexed Instructions -def VLXB_V : VIndexedLoad; -def VLXH_V : VIndexedLoad; -def VLXW_V : VIndexedLoad; - -def VLXBU_V : VIndexedLoad; -def VLXHU_V : VIndexedLoad; -def VLXWU_V : VIndexedLoad; - -def VLXE_V : VIndexedLoad; - -def VSXB_V : VIndexedStore; -def VSXH_V : VIndexedStore; -def VSXW_V : VIndexedStore; -def VSXE_V : VIndexedStore; - -def VSUXB_V : VIndexedStore; -def VSUXH_V : VIndexedStore; -def VSUXW_V : VIndexedStore; -def VSUXE_V : VIndexedStore; +def VLXEI8_V : VIndexedLoad; +def VLXEI16_V : VIndexedLoad; +def VLXEI32_V : VIndexedLoad; +def VLXEI64_V : VIndexedLoad; +def VLXEI128_V : VIndexedLoad; +def VLXEI256_V : VIndexedLoad; +def VLXEI512_V : VIndexedLoad; +def VLXEI1024_V : VIndexedLoad; + +def VSXEI8_V : VIndexedStore; +def VSXEI16_V : VIndexedStore; +def VSXEI32_V : VIndexedStore; +def VSXEI64_V : VIndexedStore; +def VSXEI128_V : VIndexedStore; +def VSXEI256_V : VIndexedStore; +def VSXEI512_V : VIndexedStore; +def VSXEI1024_V : VIndexedStore; + +def VSUXEI8_V : VIndexedStore; +def VSUXEI16_V : VIndexedStore; +def VSUXEI32_V : VIndexedStore; +def VSUXEI64_V : VIndexedStore; +def VSUXEI128_V : VIndexedStore; +def VSUXEI256_V : VIndexedStore; +def VSUXEI512_V : VIndexedStore; +def VSUXEI1024_V : VIndexedStore; def VL1R_V : VWholeLoad<0, "vl1r.v">; def VS1R_V : VWholeStore<0, "vs1r.v">; @@ -472,13 +527,25 @@ def : InstAlias<"vwcvtu.x.x.v $vd, $vs$vm", (VWADDU_VX VRegOp:$vd, VRegOp:$vs, X0, VMaskOp:$vm)>; +// Vector Integer Extension +defm VZEXT_VF8 : VALU_MV_VS2<"vzext.vf8", 0b010010, 0b00010>; +defm VSEXT_VF8 : VALU_MV_VS2<"vsext.vf8", 0b010010, 0b00011>; +defm VZEXT_VF4 : VALU_MV_VS2<"vzext.vf4", 0b010010, 0b00100>; +defm VSEXT_VF4 : VALU_MV_VS2<"vsext.vf4", 0b010010, 0b00101>; +defm VZEXT_VF2 : VALU_MV_VS2<"vzext.vf2", 0b010010, 0b00110>; +defm VSEXT_VF2 : VALU_MV_VS2<"vsext.vf2", 0b010010, 0b00111>; + // Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions defm VADC_V : VALUm_IV_V_X_I<"vadc", 0b010000>; +let Constraints = "@earlyclobber $vd", RVVConstraint = Vmadc in { defm VMADC_V : VALUm_IV_V_X_I<"vmadc", 0b010001>; defm VMADC_V : VALUNoVm_IV_V_X_I<"vmadc", 0b010001>; +} // Constraints = "@earlyclobber $vd", RVVConstraint = Vmadc defm VSBC_V : VALUm_IV_V_X<"vsbc", 0b010010>; +let Constraints = "@earlyclobber $vd", RVVConstraint = Vmadc in { defm VMSBC_V : VALUm_IV_V_X<"vmsbc", 0b010011>; defm VMSBC_V : VALUNoVm_IV_V_X<"vmsbc", 0b010011>; +} // Constraints = "@earlyclobber $vd", RVVConstraint = Vmadc // Vector Bitwise Logical Instructions defm VAND_V : VALU_IV_V_X_I<"vand", 0b001001>; @@ -664,7 +731,7 @@ } // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV // Vector Floating-Point Square-Root Instruction -defm VFSQRT_V : VALU_FV_VS2<"vfsqrt.v", 0b100011, 0b00000>; +defm VFSQRT_V : VALU_FV_VS2<"vfsqrt.v", 0b010011, 0b00000>; // Vector Floating-Point MIN/MAX Instructions defm VFMIN_V : VALU_FV_V_F<"vfmin", 0b000100>; @@ -689,7 +756,7 @@ (VMFLE_VV VRegOp:$vd, VRegOp:$vb, VRegOp:$va, VMaskOp:$vm), 0>; // Vector Floating-Point Classify Instruction -defm VFCLASS_V : VALU_FV_VS2<"vfclass.v", 0b100011, 0b10000>; +defm VFCLASS_V : VALU_FV_VS2<"vfclass.v", 0b010011, 0b10000>; let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { // Vector Floating-Point Merge Instruction @@ -708,29 +775,35 @@ } // hasSideEffects = 0, mayLoad = 0, mayStore = 0 // Single-Width Floating-Point/Integer Type-Convert Instructions -defm VFCVT_XU_F_V : VALU_FV_VS2<"vfcvt.xu.f.v", 0b100010, 0b00000>; -defm VFCVT_X_F_V : VALU_FV_VS2<"vfcvt.x.f.v", 0b100010, 0b00001>; -defm VFCVT_F_XU_V : VALU_FV_VS2<"vfcvt.f.xu.v", 0b100010, 0b00010>; -defm VFCVT_F_X_V : VALU_FV_VS2<"vfcvt.f.x.v", 0b100010, 0b00011>; +defm VFCVT_XU_F_V : VALU_FV_VS2<"vfcvt.xu.f.v", 0b010010, 0b00000>; +defm VFCVT_X_F_V : VALU_FV_VS2<"vfcvt.x.f.v", 0b010010, 0b00001>; +defm VFCVT_RTZ_XU_F_V : VALU_FV_VS2<"vfcvt.rtz.xu.f.v", 0b010010, 0b00110>; +defm VFCVT_RTZ_X_F_V : VALU_FV_VS2<"vfcvt.rtz.x.f.v", 0b010010, 0b00111>; +defm VFCVT_F_XU_V : VALU_FV_VS2<"vfcvt.f.xu.v", 0b010010, 0b00010>; +defm VFCVT_F_X_V : VALU_FV_VS2<"vfcvt.f.x.v", 0b010010, 0b00011>; // Widening Floating-Point/Integer Type-Convert Instructions let Constraints = "@earlyclobber $vd", RVVConstraint = WidenCvt in { -defm VFWCVT_XU_F_V : VALU_FV_VS2<"vfwcvt.xu.f.v", 0b100010, 0b01000>; -defm VFWCVT_X_F_V : VALU_FV_VS2<"vfwcvt.x.f.v", 0b100010, 0b01001>; -defm VFWCVT_F_XU_V : VALU_FV_VS2<"vfwcvt.f.xu.v", 0b100010, 0b01010>; -defm VFWCVT_F_X_V : VALU_FV_VS2<"vfwcvt.f.x.v", 0b100010, 0b01011>; -defm VFWCVT_F_F_V : VALU_FV_VS2<"vfwcvt.f.f.v", 0b100010, 0b01100>; +defm VFWCVT_XU_F_V : VALU_FV_VS2<"vfwcvt.xu.f.v", 0b010010, 0b01000>; +defm VFWCVT_X_F_V : VALU_FV_VS2<"vfwcvt.x.f.v", 0b010010, 0b01001>; +defm VFWCVT_RTZ_XU_F_V : VALU_FV_VS2<"vfwcvt.rtz.xu.f.v", 0b010010, 0b01110>; +defm VFWCVT_RTZ_X_F_V : VALU_FV_VS2<"vfwcvt.rtz.x.f.v", 0b010010, 0b01111>; +defm VFWCVT_F_XU_V : VALU_FV_VS2<"vfwcvt.f.xu.v", 0b010010, 0b01010>; +defm VFWCVT_F_X_V : VALU_FV_VS2<"vfwcvt.f.x.v", 0b010010, 0b01011>; +defm VFWCVT_F_F_V : VALU_FV_VS2<"vfwcvt.f.f.v", 0b010010, 0b01100>; } // Constraints = "@earlyclobber $vd", RVVConstraint = WidenCvt // Narrowing Floating-Point/Integer Type-Convert Instructions -let Constraints = "@earlyclobber $vd", RVVConstraint = Narrow in { -defm VFNCVT_XU_F_W : VALU_FV_VS2<"vfncvt.xu.f.w", 0b100010, 0b10000>; -defm VFNCVT_X_F_W : VALU_FV_VS2<"vfncvt.x.f.w", 0b100010, 0b10001>; -defm VFNCVT_F_XU_W : VALU_FV_VS2<"vfncvt.f.xu.w", 0b100010, 0b10010>; -defm VFNCVT_F_X_W : VALU_FV_VS2<"vfncvt.f.x.w", 0b100010, 0b10011>; -defm VFNCVT_F_F_W : VALU_FV_VS2<"vfncvt.f.f.w", 0b100010, 0b10100>; -defm VFNCVT_ROD_F_F_W : VALU_FV_VS2<"vfncvt.rod.f.f.w", 0b100010, 0b10101>; -} // Constraints = "@earlyclobber $vd", RVVConstraint = Narrow +let Constraints = "@earlyclobber $vd", RVVConstraint = NarrowCvt in { +defm VFNCVT_XU_F_W : VALU_FV_VS2<"vfncvt.xu.f.w", 0b010010, 0b10000>; +defm VFNCVT_X_F_W : VALU_FV_VS2<"vfncvt.x.f.w", 0b010010, 0b10001>; +defm VFNCVT_RTZ_XU_F_W : VALU_FV_VS2<"vfncvt.rtz.xu.f.w", 0b010010, 0b10110>; +defm VFNCVT_RTZ_X_F_W : VALU_FV_VS2<"vfncvt.rtz.x.f.w", 0b010010, 0b10111>; +defm VFNCVT_F_XU_W : VALU_FV_VS2<"vfncvt.f.xu.w", 0b010010, 0b10010>; +defm VFNCVT_F_X_W : VALU_FV_VS2<"vfncvt.f.x.w", 0b010010, 0b10011>; +defm VFNCVT_F_F_W : VALU_FV_VS2<"vfncvt.f.f.w", 0b010010, 0b10100>; +defm VFNCVT_ROD_F_F_W : VALU_FV_VS2<"vfncvt.rod.f.f.w", 0b010010, 0b10101>; +} // Constraints = "@earlyclobber $vd", RVVConstraint = NarrowCvt // Vector Single-Width Integer Reduction Instructions defm VREDSUM : VALU_MV_V<"vredsum", 0b000000>; @@ -778,7 +851,7 @@ defm VMORNOT_M : VALU_MV_Mask<"vmornot", 0b011100, "m">; defm VMXNOR_M : VALU_MV_Mask<"vmxnor", 0b011111, "m">; -def : InstAlias<"vmcpy.m $vd, $vs", +def : InstAlias<"vmmv.m $vd, $vs", (VMAND_MM VRegOp:$vd, VRegOp:$vs, VRegOp:$vs)>; def : InstAlias<"vmclr.m $vd", (VMXOR_MM VRegOp:$vd, VRegOp:$vd, VRegOp:$vd)>; @@ -847,8 +920,10 @@ let Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp in { defm VSLIDE1UP_V : VALU_MV_X<"vslide1up", 0b001110>; +defm VFSLIDE1UP_V : VALU_FV_F<"vfslide1up", 0b001110>; } // Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp defm VSLIDE1DOWN_V : VALU_MV_X<"vslide1down", 0b001111>; +defm VFSLIDE1DOWN_V : VALU_FV_F<"vfslide1down", 0b001111>; // Vector Register Gather Instruction let Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather in { @@ -871,3 +946,72 @@ } } // hasSideEffects = 0, mayLoad = 0, mayStore = 0 } // Predicates = [HasStdExtV] + +let Predicates = [HasStdExtV, HasStdExtZvlsseg] in { + foreach nf=2-8 in { + def VLSEG#nf#E8_V : VUnitStrideSegmentLoad; + def VLSEG#nf#E16_V : VUnitStrideSegmentLoad; + def VLSEG#nf#E32_V : VUnitStrideSegmentLoad; + def VLSEG#nf#E64_V : VUnitStrideSegmentLoad; + def VLSEG#nf#E128_V : VUnitStrideSegmentLoad; + def VLSEG#nf#E256_V : VUnitStrideSegmentLoad; + def VLSEG#nf#E512_V : VUnitStrideSegmentLoad; + def VLSEG#nf#E1024_V : VUnitStrideSegmentLoad; + + def VLSEG#nf#E8FF_V : VUnitStrideSegmentLoad; + def VLSEG#nf#E16FF_V : VUnitStrideSegmentLoad; + def VLSEG#nf#E32FF_V : VUnitStrideSegmentLoad; + def VLSEG#nf#E64FF_V : VUnitStrideSegmentLoad; + def VLSEG#nf#E128FF_V : VUnitStrideSegmentLoad; + def VLSEG#nf#E256FF_V : VUnitStrideSegmentLoad; + def VLSEG#nf#E512FF_V : VUnitStrideSegmentLoad; + def VLSEG#nf#E1024FF_V : VUnitStrideSegmentLoad; + + def VSSEG#nf#E8_V : VUnitStrideSegmentStore; + def VSSEG#nf#E16_V : VUnitStrideSegmentStore; + def VSSEG#nf#E32_V : VUnitStrideSegmentStore; + def VSSEG#nf#E64_V : VUnitStrideSegmentStore; + def VSSEG#nf#E128_V : VUnitStrideSegmentStore; + def VSSEG#nf#E256_V : VUnitStrideSegmentStore; + def VSSEG#nf#E512_V : VUnitStrideSegmentStore; + def VSSEG#nf#E1024_V : VUnitStrideSegmentStore; + + // Vector Strided Instructions + def VLSSEG#nf#E8_V : VStridedSegmentLoad; + def VLSSEG#nf#E16_V : VStridedSegmentLoad; + def VLSSEG#nf#E32_V : VStridedSegmentLoad; + def VLSSEG#nf#E64_V : VStridedSegmentLoad; + def VLSSEG#nf#E128_V : VStridedSegmentLoad; + def VLSSEG#nf#E256_V : VStridedSegmentLoad; + def VLSSEG#nf#E512_V : VStridedSegmentLoad; + def VLSSEG#nf#E1024_V : VStridedSegmentLoad; + + def VSSSEG#nf#E8_V : VStridedSegmentStore; + def VSSSEG#nf#E16_V : VStridedSegmentStore; + def VSSSEG#nf#E32_V : VStridedSegmentStore; + def VSSSEG#nf#E64_V : VStridedSegmentStore; + def VSSSEG#nf#E128_V : VStridedSegmentStore; + def VSSSEG#nf#E256_V : VStridedSegmentStore; + def VSSSEG#nf#E512_V : VStridedSegmentStore; + def VSSSEG#nf#E1024_V : VStridedSegmentStore; + + // Vector Indexed Instructions + def VLXSEG#nf#EI8_V : VIndexedSegmentLoad; + def VLXSEG#nf#EI16_V : VIndexedSegmentLoad; + def VLXSEG#nf#EI32_V : VIndexedSegmentLoad; + def VLXSEG#nf#EI64_V : VIndexedSegmentLoad; + def VLXSEG#nf#EI128_V : VIndexedSegmentLoad; + def VLXSEG#nf#EI256_V : VIndexedSegmentLoad; + def VLXSEG#nf#EI512_V : VIndexedSegmentLoad; + def VLXSEG#nf#EI1024_V : VIndexedSegmentLoad; + + def VSXSEG#nf#EI8_V : VIndexedSegmentStore; + def VSXSEG#nf#EI16_V : VIndexedSegmentStore; + def VSXSEG#nf#EI32_V : VIndexedSegmentStore; + def VSXSEG#nf#EI64_V : VIndexedSegmentStore; + def VSXSEG#nf#EI128_V : VIndexedSegmentStore; + def VSXSEG#nf#EI256_V : VIndexedSegmentStore; + def VSXSEG#nf#EI512_V : VIndexedSegmentStore; + def VSXSEG#nf#EI1024_V : VIndexedSegmentStore; + } +} // Predicates = [HasStdExtV, HasStdExtZvlsseg] Index: llvm/lib/Target/RISCV/RISCVSchedRocket32.td =================================================================== --- llvm/lib/Target/RISCV/RISCVSchedRocket32.td +++ llvm/lib/Target/RISCV/RISCVSchedRocket32.td @@ -17,7 +17,7 @@ let LoadLatency = 3; let MispredictPenalty = 3; let CompleteModel = 1; - let UnsupportedFeatures = [HasStdExtV]; + let UnsupportedFeatures = [HasStdExtV, HasStdExtZvlsseg]; } //===----------------------------------------------------------------------===// Index: llvm/lib/Target/RISCV/RISCVSchedRocket64.td =================================================================== --- llvm/lib/Target/RISCV/RISCVSchedRocket64.td +++ llvm/lib/Target/RISCV/RISCVSchedRocket64.td @@ -16,7 +16,7 @@ let IssueWidth = 1; // 1 micro-ops are dispatched per cycle. let LoadLatency = 3; let MispredictPenalty = 3; - let UnsupportedFeatures = [HasStdExtV]; + let UnsupportedFeatures = [HasStdExtV, HasStdExtZvlsseg]; } //===----------------------------------------------------------------------===// Index: llvm/lib/Target/RISCV/RISCVSubtarget.h =================================================================== --- llvm/lib/Target/RISCV/RISCVSubtarget.h +++ llvm/lib/Target/RISCV/RISCVSubtarget.h @@ -51,6 +51,7 @@ bool HasStdExtZbt = false; bool HasStdExtZbproposedc = false; bool HasStdExtV = false; + bool HasStdExtZvlsseg = false; bool HasRV64 = false; bool IsRV32E = false; bool EnableLinkerRelax = false; @@ -112,6 +113,7 @@ bool hasStdExtZbt() const { return HasStdExtZbt; } bool hasStdExtZbproposedc() const { return HasStdExtZbproposedc; } bool hasStdExtV() const { return HasStdExtV; } + bool hasStdExtZvlsseg() const { return HasStdExtZvlsseg; } bool is64Bit() const { return HasRV64; } bool isRV32E() const { return IsRV32E; } bool enableLinkerRelax() const { return EnableLinkerRelax; } Index: llvm/test/MC/RISCV/rvv/convert.s =================================================================== --- llvm/test/MC/RISCV/rvv/convert.s +++ llvm/test/MC/RISCV/rvv/convert.s @@ -10,180 +10,252 @@ vfcvt.xu.f.v v8, v4, v0.t # CHECK-INST: vfcvt.xu.f.v v8, v4, v0.t -# CHECK-ENCODING: [0x57,0x14,0x40,0x88] +# CHECK-ENCODING: [0x57,0x14,0x40,0x48] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 57 14 40 88 +# CHECK-UNKNOWN: 57 14 40 48 vfcvt.xu.f.v v8, v4 # CHECK-INST: vfcvt.xu.f.v v8, v4 -# CHECK-ENCODING: [0x57,0x14,0x40,0x8a] +# CHECK-ENCODING: [0x57,0x14,0x40,0x4a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 57 14 40 8a +# CHECK-UNKNOWN: 57 14 40 4a vfcvt.x.f.v v8, v4, v0.t # CHECK-INST: vfcvt.x.f.v v8, v4, v0.t -# CHECK-ENCODING: [0x57,0x94,0x40,0x88] +# CHECK-ENCODING: [0x57,0x94,0x40,0x48] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 57 94 40 88 +# CHECK-UNKNOWN: 57 94 40 48 vfcvt.x.f.v v8, v4 # CHECK-INST: vfcvt.x.f.v v8, v4 -# CHECK-ENCODING: [0x57,0x94,0x40,0x8a] +# CHECK-ENCODING: [0x57,0x94,0x40,0x4a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 57 94 40 8a +# CHECK-UNKNOWN: 57 94 40 4a vfcvt.f.xu.v v8, v4, v0.t # CHECK-INST: vfcvt.f.xu.v v8, v4, v0.t -# CHECK-ENCODING: [0x57,0x14,0x41,0x88] +# CHECK-ENCODING: [0x57,0x14,0x41,0x48] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 57 14 41 88 +# CHECK-UNKNOWN: 57 14 41 48 vfcvt.f.xu.v v8, v4 # CHECK-INST: vfcvt.f.xu.v v8, v4 -# CHECK-ENCODING: [0x57,0x14,0x41,0x8a] +# CHECK-ENCODING: [0x57,0x14,0x41,0x4a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 57 14 41 8a +# CHECK-UNKNOWN: 57 14 41 4a vfcvt.f.x.v v8, v4, v0.t # CHECK-INST: vfcvt.f.x.v v8, v4, v0.t -# CHECK-ENCODING: [0x57,0x94,0x41,0x88] +# CHECK-ENCODING: [0x57,0x94,0x41,0x48] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 57 94 41 88 +# CHECK-UNKNOWN: 57 94 41 48 vfcvt.f.x.v v8, v4 # CHECK-INST: vfcvt.f.x.v v8, v4 -# CHECK-ENCODING: [0x57,0x94,0x41,0x8a] +# CHECK-ENCODING: [0x57,0x94,0x41,0x4a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 57 94 41 8a +# CHECK-UNKNOWN: 57 94 41 4a + +vfcvt.rtz.xu.f.v v8, v4, v0.t +# CHECK-INST: vfcvt.rtz.xu.f.v v8, v4, v0.t +# CHECK-ENCODING: [0x57,0x14,0x43,0x48] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 43 48 + +vfcvt.rtz.xu.f.v v8, v4 +# CHECK-INST: vfcvt.rtz.xu.f.v v8, v4 +# CHECK-ENCODING: [0x57,0x14,0x43,0x4a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 43 4a + +vfcvt.rtz.x.f.v v8, v4, v0.t +# CHECK-INST: vfcvt.rtz.x.f.v v8, v4, v0.t +# CHECK-ENCODING: [0x57,0x94,0x43,0x48] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 94 43 48 + +vfcvt.rtz.x.f.v v8, v4 +# CHECK-INST: vfcvt.rtz.x.f.v v8, v4 +# CHECK-ENCODING: [0x57,0x94,0x43,0x4a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 94 43 4a vfwcvt.xu.f.v v8, v4, v0.t # CHECK-INST: vfwcvt.xu.f.v v8, v4, v0.t -# CHECK-ENCODING: [0x57,0x14,0x44,0x88] +# CHECK-ENCODING: [0x57,0x14,0x44,0x48] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 57 14 44 88 +# CHECK-UNKNOWN: 57 14 44 48 vfwcvt.xu.f.v v8, v4 # CHECK-INST: vfwcvt.xu.f.v v8, v4 -# CHECK-ENCODING: [0x57,0x14,0x44,0x8a] +# CHECK-ENCODING: [0x57,0x14,0x44,0x4a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 57 14 44 8a +# CHECK-UNKNOWN: 57 14 44 4a vfwcvt.x.f.v v8, v4, v0.t # CHECK-INST: vfwcvt.x.f.v v8, v4, v0.t -# CHECK-ENCODING: [0x57,0x94,0x44,0x88] +# CHECK-ENCODING: [0x57,0x94,0x44,0x48] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 57 94 44 88 +# CHECK-UNKNOWN: 57 94 44 48 vfwcvt.x.f.v v8, v4 # CHECK-INST: vfwcvt.x.f.v v8, v4 -# CHECK-ENCODING: [0x57,0x94,0x44,0x8a] +# CHECK-ENCODING: [0x57,0x94,0x44,0x4a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 57 94 44 8a +# CHECK-UNKNOWN: 57 94 44 4a vfwcvt.f.xu.v v8, v4, v0.t # CHECK-INST: vfwcvt.f.xu.v v8, v4, v0.t -# CHECK-ENCODING: [0x57,0x14,0x45,0x88] +# CHECK-ENCODING: [0x57,0x14,0x45,0x48] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 57 14 45 88 +# CHECK-UNKNOWN: 57 14 45 48 vfwcvt.f.xu.v v8, v4 # CHECK-INST: vfwcvt.f.xu.v v8, v4 -# CHECK-ENCODING: [0x57,0x14,0x45,0x8a] +# CHECK-ENCODING: [0x57,0x14,0x45,0x4a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 57 14 45 8a +# CHECK-UNKNOWN: 57 14 45 4a vfwcvt.f.x.v v8, v4, v0.t # CHECK-INST: vfwcvt.f.x.v v8, v4, v0.t -# CHECK-ENCODING: [0x57,0x94,0x45,0x88] +# CHECK-ENCODING: [0x57,0x94,0x45,0x48] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 57 94 45 88 +# CHECK-UNKNOWN: 57 94 45 48 vfwcvt.f.x.v v8, v4 # CHECK-INST: vfwcvt.f.x.v v8, v4 -# CHECK-ENCODING: [0x57,0x94,0x45,0x8a] +# CHECK-ENCODING: [0x57,0x94,0x45,0x4a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 57 94 45 8a +# CHECK-UNKNOWN: 57 94 45 4a vfwcvt.f.f.v v8, v4, v0.t # CHECK-INST: vfwcvt.f.f.v v8, v4, v0.t -# CHECK-ENCODING: [0x57,0x14,0x46,0x88] +# CHECK-ENCODING: [0x57,0x14,0x46,0x48] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 57 14 46 88 +# CHECK-UNKNOWN: 57 14 46 48 vfwcvt.f.f.v v8, v4 # CHECK-INST: vfwcvt.f.f.v v8, v4 -# CHECK-ENCODING: [0x57,0x14,0x46,0x8a] +# CHECK-ENCODING: [0x57,0x14,0x46,0x4a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 46 4a + +vfwcvt.rtz.xu.f.v v8, v4, v0.t +# CHECK-INST: vfwcvt.rtz.xu.f.v v8, v4, v0.t +# CHECK-ENCODING: [0x57,0x14,0x47,0x48] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 47 48 + +vfwcvt.rtz.xu.f.v v8, v4 +# CHECK-INST: vfwcvt.rtz.xu.f.v v8, v4 +# CHECK-ENCODING: [0x57,0x14,0x47,0x4a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 57 14 46 8a +# CHECK-UNKNOWN: 57 14 47 4a + +vfwcvt.rtz.x.f.v v8, v4, v0.t +# CHECK-INST: vfwcvt.rtz.x.f.v v8, v4, v0.t +# CHECK-ENCODING: [0x57,0x94,0x47,0x48] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 94 47 48 + +vfwcvt.rtz.x.f.v v8, v4 +# CHECK-INST: vfwcvt.rtz.x.f.v v8, v4 +# CHECK-ENCODING: [0x57,0x94,0x47,0x4a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 94 47 4a vfncvt.xu.f.w v8, v4, v0.t # CHECK-INST: vfncvt.xu.f.w v8, v4, v0.t -# CHECK-ENCODING: [0x57,0x14,0x48,0x88] +# CHECK-ENCODING: [0x57,0x14,0x48,0x48] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 57 14 48 88 +# CHECK-UNKNOWN: 57 14 48 48 vfncvt.xu.f.w v8, v4 # CHECK-INST: vfncvt.xu.f.w v8, v4 -# CHECK-ENCODING: [0x57,0x14,0x48,0x8a] +# CHECK-ENCODING: [0x57,0x14,0x48,0x4a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 57 14 48 8a +# CHECK-UNKNOWN: 57 14 48 4a vfncvt.x.f.w v8, v4, v0.t # CHECK-INST: vfncvt.x.f.w v8, v4, v0.t -# CHECK-ENCODING: [0x57,0x94,0x48,0x88] +# CHECK-ENCODING: [0x57,0x94,0x48,0x48] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 57 94 48 88 +# CHECK-UNKNOWN: 57 94 48 48 vfncvt.x.f.w v8, v4 # CHECK-INST: vfncvt.x.f.w v8, v4 -# CHECK-ENCODING: [0x57,0x94,0x48,0x8a] +# CHECK-ENCODING: [0x57,0x94,0x48,0x4a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 57 94 48 8a +# CHECK-UNKNOWN: 57 94 48 4a vfncvt.f.xu.w v8, v4, v0.t # CHECK-INST: vfncvt.f.xu.w v8, v4, v0.t -# CHECK-ENCODING: [0x57,0x14,0x49,0x88] +# CHECK-ENCODING: [0x57,0x14,0x49,0x48] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 57 14 49 88 +# CHECK-UNKNOWN: 57 14 49 48 vfncvt.f.xu.w v8, v4 # CHECK-INST: vfncvt.f.xu.w v8, v4 -# CHECK-ENCODING: [0x57,0x14,0x49,0x8a] +# CHECK-ENCODING: [0x57,0x14,0x49,0x4a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 57 14 49 8a +# CHECK-UNKNOWN: 57 14 49 4a vfncvt.f.x.w v8, v4, v0.t # CHECK-INST: vfncvt.f.x.w v8, v4, v0.t -# CHECK-ENCODING: [0x57,0x94,0x49,0x88] +# CHECK-ENCODING: [0x57,0x94,0x49,0x48] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 57 94 49 88 +# CHECK-UNKNOWN: 57 94 49 48 vfncvt.f.x.w v8, v4 # CHECK-INST: vfncvt.f.x.w v8, v4 -# CHECK-ENCODING: [0x57,0x94,0x49,0x8a] +# CHECK-ENCODING: [0x57,0x94,0x49,0x4a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 57 94 49 8a +# CHECK-UNKNOWN: 57 94 49 4a vfncvt.f.f.w v8, v4, v0.t # CHECK-INST: vfncvt.f.f.w v8, v4, v0.t -# CHECK-ENCODING: [0x57,0x14,0x4a,0x88] +# CHECK-ENCODING: [0x57,0x14,0x4a,0x48] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 57 14 4a 88 +# CHECK-UNKNOWN: 57 14 4a 48 vfncvt.f.f.w v8, v4 # CHECK-INST: vfncvt.f.f.w v8, v4 -# CHECK-ENCODING: [0x57,0x14,0x4a,0x8a] +# CHECK-ENCODING: [0x57,0x14,0x4a,0x4a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 57 14 4a 8a +# CHECK-UNKNOWN: 57 14 4a 4a vfncvt.rod.f.f.w v8, v4, v0.t # CHECK-INST: vfncvt.rod.f.f.w v8, v4, v0.t -# CHECK-ENCODING: [0x57,0x94,0x4a,0x88] +# CHECK-ENCODING: [0x57,0x94,0x4a,0x48] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 57 94 4a 88 +# CHECK-UNKNOWN: 57 94 4a 48 vfncvt.rod.f.f.w v8, v4 # CHECK-INST: vfncvt.rod.f.f.w v8, v4 -# CHECK-ENCODING: [0x57,0x94,0x4a,0x8a] +# CHECK-ENCODING: [0x57,0x94,0x4a,0x4a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 94 4a 4a + +vfncvt.rtz.xu.f.w v8, v4, v0.t +# CHECK-INST: vfncvt.rtz.xu.f.w v8, v4, v0.t +# CHECK-ENCODING: [0x57,0x14,0x4b,0x48] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4b 48 + +vfncvt.rtz.xu.f.w v8, v4 +# CHECK-INST: vfncvt.rtz.xu.f.w v8, v4 +# CHECK-ENCODING: [0x57,0x14,0x4b,0x4a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 14 4b 4a + +vfncvt.rtz.x.f.w v8, v4, v0.t +# CHECK-INST: vfncvt.rtz.x.f.w v8, v4, v0.t +# CHECK-ENCODING: [0x57,0x94,0x4b,0x48] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 94 4b 48 + +vfncvt.rtz.x.f.w v8, v4 +# CHECK-INST: vfncvt.rtz.x.f.w v8, v4 +# CHECK-ENCODING: [0x57,0x94,0x4b,0x4a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 57 94 4a 8a +# CHECK-UNKNOWN: 57 94 4b 4a Index: llvm/test/MC/RISCV/rvv/ext.s =================================================================== --- /dev/null +++ llvm/test/MC/RISCV/rvv/ext.s @@ -0,0 +1,81 @@ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d --mattr=+experimental-v - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +vzext.vf2 v8, v4, v0.t +# CHECK-INST: vzext.vf2 v8, v4, v0.t +# CHECK-ENCODING: [0x57,0x24,0x43,0x48] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 43 48 + +vzext.vf2 v8, v4 +# CHECK-INST: vzext.vf2 v8, v4 +# CHECK-ENCODING: [0x57,0x24,0x43,0x4a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 43 4a + +vsext.vf2 v8, v4, v0.t +# CHECK-INST: vsext.vf2 v8, v4, v0.t +# CHECK-ENCODING: [0x57,0xa4,0x43,0x48] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 a4 43 48 + +vsext.vf2 v8, v4 +# CHECK-INST: vsext.vf2 v8, v4 +# CHECK-ENCODING: [0x57,0xa4,0x43,0x4a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 a4 43 4a + +vzext.vf4 v8, v4, v0.t +# CHECK-INST: vzext.vf4 v8, v4, v0.t +# CHECK-ENCODING: [0x57,0x24,0x42,0x48] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 42 48 + +vzext.vf4 v8, v4 +# CHECK-INST: vzext.vf4 v8, v4 +# CHECK-ENCODING: [0x57,0x24,0x42,0x4a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 42 4a + +vsext.vf4 v8, v4, v0.t +# CHECK-INST: vsext.vf4 v8, v4, v0.t +# CHECK-ENCODING: [0x57,0xa4,0x42,0x48] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 a4 42 48 + +vsext.vf4 v8, v4 +# CHECK-INST: vsext.vf4 v8, v4 +# CHECK-ENCODING: [0x57,0xa4,0x42,0x4a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 a4 42 4a + +vzext.vf8 v8, v4, v0.t +# CHECK-INST: vzext.vf8 v8, v4, v0.t +# CHECK-ENCODING: [0x57,0x24,0x41,0x48] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 41 48 + +vzext.vf8 v8, v4 +# CHECK-INST: vzext.vf8 v8, v4 +# CHECK-ENCODING: [0x57,0x24,0x41,0x4a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 24 41 4a + +vsext.vf8 v8, v4, v0.t +# CHECK-INST: vsext.vf8 v8, v4, v0.t +# CHECK-ENCODING: [0x57,0xa4,0x41,0x48] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 a4 41 48 + +vsext.vf8 v8, v4 +# CHECK-INST: vsext.vf8 v8, v4 +# CHECK-ENCODING: [0x57,0xa4,0x41,0x4a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 a4 41 4a Index: llvm/test/MC/RISCV/rvv/fothers.s =================================================================== --- llvm/test/MC/RISCV/rvv/fothers.s +++ llvm/test/MC/RISCV/rvv/fothers.s @@ -10,30 +10,54 @@ vfsqrt.v v8, v4, v0.t # CHECK-INST: vfsqrt.v v8, v4, v0.t -# CHECK-ENCODING: [0x57,0x14,0x40,0x8c] +# CHECK-ENCODING: [0x57,0x14,0x40,0x4c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 57 14 40 8c +# CHECK-UNKNOWN: 57 14 40 4c vfsqrt.v v8, v4 # CHECK-INST: vfsqrt.v v8, v4 -# CHECK-ENCODING: [0x57,0x14,0x40,0x8e] +# CHECK-ENCODING: [0x57,0x14,0x40,0x4e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 57 14 40 8e +# CHECK-UNKNOWN: 57 14 40 4e vfclass.v v8, v4, v0.t # CHECK-INST: vfclass.v v8, v4, v0.t -# CHECK-ENCODING: [0x57,0x14,0x48,0x8c] +# CHECK-ENCODING: [0x57,0x14,0x48,0x4c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 57 14 48 8c +# CHECK-UNKNOWN: 57 14 48 4c vfclass.v v8, v4 # CHECK-INST: vfclass.v v8, v4 -# CHECK-ENCODING: [0x57,0x14,0x48,0x8e] +# CHECK-ENCODING: [0x57,0x14,0x48,0x4e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 57 14 48 8e +# CHECK-UNKNOWN: 57 14 48 4e vfmerge.vfm v8, v4, fa0, v0 # CHECK-INST: vfmerge.vfm v8, v4, fa0, v0 # CHECK-ENCODING: [0x57,0x54,0x45,0x5c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 57 54 45 5c + +vfslide1up.vf v8, v4, fa0, v0.t +# CHECK-INST: vfslide1up.vf v8, v4, fa0, v0.t +# CHECK-ENCODING: [0x57,0x54,0x45,0x38] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 38 + +vfslide1up.vf v8, v4, fa0 +# CHECK-INST: vfslide1up.vf v8, v4, fa0 +# CHECK-ENCODING: [0x57,0x54,0x45,0x3a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 3a + +vfslide1down.vf v8, v4, fa0, v0.t +# CHECK-INST: vfslide1down.vf v8, v4, fa0, v0.t +# CHECK-ENCODING: [0x57,0x54,0x45,0x3c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 3c + +vfslide1down.vf v8, v4, fa0 +# CHECK-INST: vfslide1down.vf v8, v4, fa0 +# CHECK-ENCODING: [0x57,0x54,0x45,0x3e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 54 45 3e Index: llvm/test/MC/RISCV/rvv/invalid.s =================================================================== --- llvm/test/MC/RISCV/rvv/invalid.s +++ llvm/test/MC/RISCV/rvv/invalid.s @@ -2,22 +2,34 @@ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR vsetvli a2, a0, e31 -# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8] +# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu] vsetvli a2, a0, e32,m3 -# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8] +# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu] vsetvli a2, a0, m1,e32 -# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8] +# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu] vsetvli a2, a0, e32,m16 -# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8] +# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu] vsetvli a2, a0, e2048,m8 -# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8] +# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu] vsetvli a2, a0, e1,m8 -# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8] +# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu] + +vsetvli a2, a0, e8,m1,tx +# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu] + +vsetvli a2, a0, e8,m1,ta,mx +# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu] + +vsetvli a2, a0, e8,m1,ma +# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu] + +vsetvli a2, a0, e8,m1,mu +# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu] vadd.vv v1, v3, v2, v4.t # CHECK-ERROR: operand must be v0.t @@ -47,10 +59,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vfwcvt.xu.f.v v2, v2 -vfwcvt.xu.f.v v2, v3 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vfwcvt.xu.f.v v2, v3 - vfwcvt.x.f.v v0, v2, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vfwcvt.x.f.v v0, v2, v0.t @@ -59,10 +67,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vfwcvt.x.f.v v2, v2 -vfwcvt.x.f.v v2, v3 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vfwcvt.x.f.v v2, v3 - vfwcvt.f.xu.v v0, v2, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vfwcvt.f.xu.v v0, v2, v0.t @@ -71,10 +75,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vfwcvt.f.xu.v v2, v2 -vfwcvt.f.xu.v v2, v3 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vfwcvt.f.xu.v v2, v3 - vfwcvt.f.x.v v0, v2, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vfwcvt.f.x.v v0, v2, v0.t @@ -83,10 +83,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vfwcvt.f.x.v v2, v2 -vfwcvt.f.x.v v2, v3 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vfwcvt.f.x.v v2, v3 - vfwcvt.f.f.v v0, v2, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vfwcvt.f.f.v v0, v2, v0.t @@ -95,10 +91,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vfwcvt.f.f.v v2, v2 -vfwcvt.f.f.v v2, v3 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vfwcvt.f.f.v v2, v3 - vslideup.vx v0, v2, a0, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vslideup.vx v0, v2, a0, v0.t @@ -127,10 +119,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vnsrl.wv v2, v2, v4 -vnsrl.wv v3, v2, v4 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vnsrl.wv v3, v2, v4 - vnsrl.wx v2, v2, a0 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vnsrl.wx v2, v2, a0 @@ -143,10 +131,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vnsra.wv v2, v2, v4 -vnsra.wv v3, v2, v4 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vnsra.wv v3, v2, v4 - vnsra.wx v2, v2, a0 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vnsra.wx v2, v2, a0 @@ -159,10 +143,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vnclipu.wv v2, v2, v4 -vnclipu.wv v3, v2, v4 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vnclipu.wv v3, v2, v4 - vnclipu.wx v2, v2, a0 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vnclipu.wx v2, v2, a0 @@ -175,10 +155,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vnclip.wv v2, v2, v4 -vnclip.wv v3, v2, v4 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vnclip.wv v3, v2, v4 - vnclip.wx v2, v2, a0 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vnclip.wx v2, v2, a0 @@ -191,50 +167,26 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vfncvt.xu.f.w v2, v2 -vfncvt.xu.f.w v3, v2 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vfncvt.xu.f.w v3, v2 - vfncvt.x.f.w v2, v2 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vfncvt.x.f.w v2, v2 -vfncvt.x.f.w v3, v2 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vfncvt.x.f.w v3, v2 - vfncvt.f.xu.w v2, v2 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vfncvt.f.xu.w v2, v2 -vfncvt.f.xu.w v3, v2 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vfncvt.f.xu.w v3, v2 - vfncvt.f.x.w v2, v2 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vfncvt.f.x.w v2, v2 -vfncvt.f.x.w v3, v2 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vfncvt.f.x.w v3, v2 - vfncvt.f.f.w v2, v2 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vfncvt.f.f.w v2, v2 -vfncvt.f.f.w v3, v2 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vfncvt.f.f.w v3, v2 - vfncvt.rod.f.f.w v2, v2 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vfncvt.rod.f.f.w v2, v2 -vfncvt.rod.f.f.w v3, v2 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vfncvt.rod.f.f.w v3, v2 - vrgather.vv v0, v2, v4, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vrgather.vv v0, v2, v4, v0.t @@ -267,10 +219,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vwaddu.vv v2, v2, v4 -vwaddu.vv v2, v3, v4 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vwaddu.vv v2, v3, v4 - vwsubu.vv v0, v2, v4, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vwsubu.vv v0, v2, v4, v0.t @@ -279,10 +227,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vwsubu.vv v2, v2, v4 -vwsubu.vv v2, v3, v4 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vwsubu.vv v2, v3, v4 - vwadd.vv v0, v2, v4, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vwadd.vv v0, v2, v4, v0.t @@ -291,10 +235,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vwadd.vv v2, v2, v4 -vwadd.vv v2, v3, v4 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vwadd.vv v2, v3, v4 - vwsub.vv v0, v2, v4, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vwsub.vv v0, v2, v4, v0.t @@ -303,10 +243,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vwsub.vv v2, v2, v4 -vwsub.vv v2, v3, v4 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vwsub.vv v2, v3, v4 - vwmul.vv v0, v2, v4, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vwmul.vv v0, v2, v4, v0.t @@ -315,10 +251,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vwmul.vv v2, v2, v4 -vwmul.vv v2, v3, v4 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vwmul.vv v2, v3, v4 - vwmulu.vv v0, v2, v4, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vwmulu.vv v0, v2, v4, v0.t @@ -327,10 +259,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vwmulu.vv v2, v2, v4 -vwmulu.vv v2, v3, v4 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vwmulu.vv v2, v3, v4 - vwmulsu.vv v0, v2, v4, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vwmulsu.vv v0, v2, v4, v0.t @@ -339,10 +267,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vwmulsu.vv v2, v2, v4 -vwmulsu.vv v2, v3, v4 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vwmulsu.vv v2, v3, v4 - vwmaccu.vv v0, v4, v2, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vwmaccu.vv v0, v4, v2, v0.t @@ -351,10 +275,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vwmaccu.vv v2, v4, v2 -vwmaccu.vv v2, v4, v3 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vwmaccu.vv v2, v4, v3 - vwmacc.vv v0, v4, v2, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vwmacc.vv v0, v4, v2, v0.t @@ -363,10 +283,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vwmacc.vv v2, v4, v2 -vwmacc.vv v2, v4, v3 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vwmacc.vv v2, v4, v3 - vwmaccsu.vv v0, v4, v2, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vwmaccsu.vv v0, v4, v2, v0.t @@ -375,10 +291,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vwmaccsu.vv v2, v4, v2 -vwmaccsu.vv v2, v4, v3 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vwmaccsu.vv v2, v4, v3 - vfwadd.vv v0, v2, v4, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vfwadd.vv v0, v2, v4, v0.t @@ -387,10 +299,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vfwadd.vv v2, v2, v4 -vfwadd.vv v2, v3, v4 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vfwadd.vv v2, v3, v4 - vfwsub.vv v0, v2, v4, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vfwsub.vv v0, v2, v4, v0.t @@ -399,10 +307,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vfwsub.vv v2, v2, v4 -vfwsub.vv v2, v3, v4 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vfwsub.vv v2, v3, v4 - vfwmul.vv v0, v2, v4, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vfwmul.vv v0, v2, v4, v0.t @@ -411,10 +315,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vfwmul.vv v2, v2, v4 -vfwmul.vv v2, v3, v4 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vfwmul.vv v2, v3, v4 - vfwmacc.vv v0, v4, v2, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vfwmacc.vv v0, v4, v2, v0.t @@ -423,10 +323,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vfwmacc.vv v2, v4, v2 -vfwmacc.vv v2, v4, v3 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vfwmacc.vv v2, v4, v3 - vfwnmacc.vv v0, v4, v2, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vfwnmacc.vv v0, v4, v2, v0.t @@ -435,10 +331,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vfwnmacc.vv v2, v4, v2 -vfwnmacc.vv v2, v4, v3 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vfwnmacc.vv v2, v4, v3 - vfwmsac.vv v0, v4, v2, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vfwmsac.vv v0, v4, v2, v0.t @@ -447,10 +339,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vfwmsac.vv v2, v4, v2 -vfwmsac.vv v2, v4, v3 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vfwmsac.vv v2, v4, v3 - vfwnmsac.vv v0, v4, v2, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vfwnmsac.vv v0, v4, v2, v0.t @@ -459,10 +347,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vfwnmsac.vv v2, v4, v2 -vfwnmsac.vv v2, v4, v3 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vfwnmsac.vv v2, v4, v3 - vwaddu.vx v0, v2, a0, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vwaddu.vx v0, v2, a0, v0.t @@ -471,10 +355,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vwaddu.vx v2, v2, a0 -vwaddu.vx v2, v3, a0 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vwaddu.vx v2, v3, a0 - vwsubu.vx v0, v2, a0, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vwsubu.vx v0, v2, a0, v0.t @@ -483,10 +363,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vwsubu.vx v2, v2, a0 -vwsubu.vx v2, v3, a0 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vwsubu.vx v2, v3, a0 - vwadd.vx v0, v2, a0, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vwadd.vx v0, v2, a0, v0.t @@ -495,10 +371,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vwadd.vx v2, v2, a0 -vwadd.vx v2, v3, a0 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vwadd.vx v2, v3, a0 - vwsub.vx v0, v2, a0, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vwsub.vx v0, v2, a0, v0.t @@ -507,10 +379,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vwsub.vx v2, v2, a0 -vwsub.vx v2, v3, a0 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vwsub.vx v2, v3, a0 - vwmul.vx v0, v2, a0, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vwmul.vx v0, v2, a0, v0.t @@ -519,10 +387,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vwmul.vx v2, v2, a0 -vwmul.vx v2, v3, a0 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vwmul.vx v2, v3, a0 - vwmulu.vx v0, v2, a0, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vwmulu.vx v0, v2, a0, v0.t @@ -531,10 +395,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vwmulu.vx v2, v2, a0 -vwmulu.vx v2, v3, a0 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vwmulu.vx v2, v3, a0 - vwmulsu.vx v0, v2, a0, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vwmulsu.vx v0, v2, a0, v0.t @@ -543,10 +403,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vwmulsu.vx v2, v2, a0 -vwmulsu.vx v2, v3, a0 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vwmulsu.vx v2, v3, a0 - vwmaccu.vx v0, a0, v2, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vwmaccu.vx v0, a0, v2, v0.t @@ -555,10 +411,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vwmaccu.vx v2, a0, v2 -vwmaccu.vx v2, a0, v3 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vwmaccu.vx v2, a0, v3 - vwmacc.vx v0, a0, v2, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vwmacc.vx v0, a0, v2, v0.t @@ -567,10 +419,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vwmacc.vx v2, a0, v2 -vwmacc.vx v2, a0, v3 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vwmacc.vx v2, a0, v3 - vwmaccsu.vx v0, a0, v2, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vwmaccsu.vx v0, a0, v2, v0.t @@ -579,10 +427,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vwmaccsu.vx v2, a0, v2 -vwmaccsu.vx v2, a0, v3 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vwmaccsu.vx v2, a0, v3 - vwmaccus.vx v0, a0, v2, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vwmaccus.vx v0, a0, v2, v0.t @@ -591,10 +435,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vwmaccus.vx v2, a0, v2 -vwmaccus.vx v2, a0, v3 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vwmaccus.vx v2, a0, v3 - vfwadd.vf v0, v2, fa0, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vfwadd.vf v0, v2, fa0, v0.t @@ -603,10 +443,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vfwadd.vf v2, v2, fa0 -vfwadd.vf v2, v3, fa0 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vfwadd.vf v2, v3, fa0 - vfwsub.vf v0, v2, fa0, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vfwsub.vf v0, v2, fa0, v0.t @@ -615,10 +451,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vfwsub.vf v2, v2, fa0 -vfwsub.vf v2, v3, fa0 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vfwsub.vf v2, v3, fa0 - vfwmul.vf v0, v2, fa0, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vfwmul.vf v0, v2, fa0, v0.t @@ -627,10 +459,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vfwmul.vf v2, v2, fa0 -vfwmul.vf v2, v3, fa0 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vfwmul.vf v2, v3, fa0 - vfwmacc.vf v0, fa0, v2, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vfwmacc.vf v0, fa0, v2, v0.t @@ -639,10 +467,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vfwmacc.vf v2, fa0, v2 -vfwmacc.vf v2, fa0, v3 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vfwmacc.vf v2, fa0, v3 - vfwnmacc.vf v0, fa0, v2, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vfwnmacc.vf v0, fa0, v2, v0.t @@ -651,10 +475,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vfwnmacc.vf v2, fa0, v2 -vfwnmacc.vf v2, fa0, v3 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vfwnmacc.vf v2, fa0, v3 - vfwmsac.vf v0, fa0, v2, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vfwmsac.vf v0, fa0, v2, v0.t @@ -663,10 +483,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vfwmsac.vf v2, fa0, v2 -vfwmsac.vf v2, fa0, v3 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vfwmsac.vf v2, fa0, v3 - vfwnmsac.vf v0, fa0, v2, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vfwnmsac.vf v0, fa0, v2, v0.t @@ -675,10 +491,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vfwnmsac.vf v2, fa0, v2 -vfwnmsac.vf v2, fa0, v3 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vfwnmsac.vf v2, fa0, v3 - vcompress.vm v2, v2, v4 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vcompress.vm v2, v2, v4 @@ -691,10 +503,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vwaddu.wv v2, v4, v2 -vwaddu.wv v2, v4, v3 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vwaddu.wv v2, v4, v3 - vwsubu.wv v0, v2, v4, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vwsubu.wv v0, v2, v4, v0.t @@ -703,10 +511,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vwsubu.wv v2, v4, v2 -vwsubu.wv v2, v4, v3 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vwsubu.wv v2, v4, v3 - vwadd.wv v0, v2, v4, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vwadd.wv v0, v2, v4, v0.t @@ -715,10 +519,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vwadd.wv v2, v4, v2 -vwadd.wv v2, v4, v3 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vwadd.wv v2, v4, v3 - vwsub.wv v0, v2, v4, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vwsub.wv v0, v2, v4, v0.t @@ -727,10 +527,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vwsub.wv v2, v4, v2 -vwsub.wv v2, v4, v3 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vwsub.wv v2, v4, v3 - vfwadd.wv v0, v2, v4, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vfwadd.wv v0, v2, v4, v0.t @@ -739,10 +535,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vfwadd.wv v2, v4, v2 -vfwadd.wv v2, v4, v3 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vfwadd.wv v2, v4, v3 - vfwsub.wv v0, v2, v4, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vfwsub.wv v0, v2, v4, v0.t @@ -751,10 +543,6 @@ # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. # CHECK-ERROR-LABEL: vfwsub.wv v2, v4, v2 -vfwsub.wv v2, v4, v3 -# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. -# CHECK-ERROR-LABEL: vfwsub.wv v2, v4, v3 - vwaddu.wx v0, v2, a0, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vwaddu.wx v0, v2, a0, v0.t @@ -778,3 +566,27 @@ vfwsub.wf v0, v2, fa0, v0.t # CHECK-ERROR: The destination vector register group cannot overlap the mask register. # CHECK-ERROR-LABEL: vfwsub.wf v0, v2, fa0, v0.t + +vadc.vvm v0, v2, v4, v0 +# CHECK-ERROR: The destination vector register group cannot be V0. +# CHECK-ERROR-LABEL: vadc.vvm v0, v2, v4, v0 + +vmadc.vvm v2, v2, v4, v0 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vmadc.vvm v2, v2, v4, v0 + +vmadc.vvm v4, v2, v4, v0 +# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group. +# CHECK-ERROR-LABEL: vmadc.vvm v4, v2, v4, v0 + +vadd.vv v0, v2, v4, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vadd.vv v0, v2, v4, v0.t + +vadd.vx v0, v2, a0, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vadd.vx v0, v2, a0, v0.t + +vadd.vi v0, v2, 1, v0.t +# CHECK-ERROR: The destination vector register group cannot overlap the mask register. +# CHECK-ERROR-LABEL: vadd.vi v0, v2, 1, v0.t Index: llvm/test/MC/RISCV/rvv/load.s =================================================================== --- llvm/test/MC/RISCV/rvv/load.s +++ llvm/test/MC/RISCV/rvv/load.s @@ -8,332 +8,392 @@ # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN -vlb.v v8, (a0), v0.t -# CHECK-INST: vlb.v v8, (a0), v0.t -# CHECK-ENCODING: [0x07,0x04,0x05,0x10] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 07 04 05 10 - -vlb.v v8, (a0) -# CHECK-INST: vlb.v v8, (a0) -# CHECK-ENCODING: [0x07,0x04,0x05,0x12] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 07 04 05 12 - -vlh.v v8, (a0), v0.t -# CHECK-INST: vlh.v v8, (a0), v0.t -# CHECK-ENCODING: [0x07,0x54,0x05,0x10] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 07 54 05 10 - -vlh.v v8, (a0) -# CHECK-INST: vlh.v v8, (a0) -# CHECK-ENCODING: [0x07,0x54,0x05,0x12] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 07 54 05 12 - -vlw.v v8, (a0), v0.t -# CHECK-INST: vlw.v v8, (a0), v0.t -# CHECK-ENCODING: [0x07,0x64,0x05,0x10] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 07 64 05 10 - -vlw.v v8, (a0) -# CHECK-INST: vlw.v v8, (a0) -# CHECK-ENCODING: [0x07,0x64,0x05,0x12] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 07 64 05 12 - -vlbu.v v8, (a0), v0.t -# CHECK-INST: vlbu.v v8, (a0), v0.t +vle8.v v8, (a0), v0.t +# CHECK-INST: vle8.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0x00] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 07 04 05 00 -vlbu.v v8, (a0) -# CHECK-INST: vlbu.v v8, (a0) +vle8.v v8, (a0) +# CHECK-INST: vle8.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0x02] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 07 04 05 02 -vlhu.v v8, (a0), v0.t -# CHECK-INST: vlhu.v v8, (a0), v0.t +vle16.v v8, (a0), v0.t +# CHECK-INST: vle16.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0x00] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 07 54 05 00 -vlhu.v v8, (a0) -# CHECK-INST: vlhu.v v8, (a0) +vle16.v v8, (a0) +# CHECK-INST: vle16.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0x02] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 07 54 05 02 -vlwu.v v8, (a0), v0.t -# CHECK-INST: vlwu.v v8, (a0), v0.t +vle32.v v8, (a0), v0.t +# CHECK-INST: vle32.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0x00] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 07 64 05 00 -vlwu.v v8, (a0) -# CHECK-INST: vlwu.v v8, (a0) +vle32.v v8, (a0) +# CHECK-INST: vle32.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0x02] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 07 64 05 02 -vlbff.v v8, (a0), v0.t -# CHECK-INST: vlbff.v v8, (a0), v0.t -# CHECK-ENCODING: [0x07,0x04,0x05,0x11] +vle64.v v8, (a0), v0.t +# CHECK-INST: vle64.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x74,0x05,0x00] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 07 04 05 11 +# CHECK-UNKNOWN: 07 74 05 00 -vlbff.v v8, (a0) -# CHECK-INST: vlbff.v v8, (a0) -# CHECK-ENCODING: [0x07,0x04,0x05,0x13] +vle64.v v8, (a0) +# CHECK-INST: vle64.v v8, (a0) +# CHECK-ENCODING: [0x07,0x74,0x05,0x02] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 07 04 05 13 +# CHECK-UNKNOWN: 07 74 05 02 -vlhff.v v8, (a0), v0.t -# CHECK-INST: vlhff.v v8, (a0), v0.t -# CHECK-ENCODING: [0x07,0x54,0x05,0x11] +vle128.v v8, (a0), v0.t +# CHECK-INST: vle128.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x04,0x05,0x10] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 07 54 05 11 +# CHECK-UNKNOWN: 07 04 05 10 -vlhff.v v8, (a0) -# CHECK-INST: vlhff.v v8, (a0) -# CHECK-ENCODING: [0x07,0x54,0x05,0x13] +vle128.v v8, (a0) +# CHECK-INST: vle128.v v8, (a0) +# CHECK-ENCODING: [0x07,0x04,0x05,0x12] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 07 54 05 13 +# CHECK-UNKNOWN: 07 04 05 12 -vlwff.v v8, (a0), v0.t -# CHECK-INST: vlwff.v v8, (a0), v0.t -# CHECK-ENCODING: [0x07,0x64,0x05,0x11] +vle256.v v8, (a0), v0.t +# CHECK-INST: vle256.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x54,0x05,0x10] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 07 64 05 11 +# CHECK-UNKNOWN: 07 54 05 10 -vlwff.v v8, (a0) -# CHECK-INST: vlwff.v v8, (a0) -# CHECK-ENCODING: [0x07,0x64,0x05,0x13] +vle256.v v8, (a0) +# CHECK-INST: vle256.v v8, (a0) +# CHECK-ENCODING: [0x07,0x54,0x05,0x12] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 07 64 05 13 +# CHECK-UNKNOWN: 07 54 05 12 -vlbuff.v v8, (a0), v0.t -# CHECK-INST: vlbuff.v v8, (a0), v0.t +vle512.v v8, (a0), v0.t +# CHECK-INST: vle512.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x64,0x05,0x10] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 64 05 10 + +vle512.v v8, (a0) +# CHECK-INST: vle512.v v8, (a0) +# CHECK-ENCODING: [0x07,0x64,0x05,0x12] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 64 05 12 + +vle1024.v v8, (a0), v0.t +# CHECK-INST: vle1024.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x74,0x05,0x10] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 74 05 10 + +vle1024.v v8, (a0) +# CHECK-INST: vle1024.v v8, (a0) +# CHECK-ENCODING: [0x07,0x74,0x05,0x12] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 74 05 12 + +vle8ff.v v8, (a0), v0.t +# CHECK-INST: vle8ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0x01] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 07 04 05 01 -vlbuff.v v8, (a0) -# CHECK-INST: vlbuff.v v8, (a0) +vle8ff.v v8, (a0) +# CHECK-INST: vle8ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0x03] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 07 04 05 03 -vlhuff.v v8, (a0), v0.t -# CHECK-INST: vlhuff.v v8, (a0), v0.t +vle16ff.v v8, (a0), v0.t +# CHECK-INST: vle16ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0x01] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 07 54 05 01 -vlhuff.v v8, (a0) -# CHECK-INST: vlhuff.v v8, (a0) +vle16ff.v v8, (a0) +# CHECK-INST: vle16ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0x03] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 07 54 05 03 -vlwuff.v v8, (a0), v0.t -# CHECK-INST: vlwuff.v v8, (a0), v0.t +vle32ff.v v8, (a0), v0.t +# CHECK-INST: vle32ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0x01] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 07 64 05 01 -vlwuff.v v8, (a0) -# CHECK-INST: vlwuff.v v8, (a0) +vle32ff.v v8, (a0) +# CHECK-INST: vle32ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0x03] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 07 64 05 03 -vleff.v v8, (a0), v0.t -# CHECK-INST: vleff.v v8, (a0), v0.t +vle64ff.v v8, (a0), v0.t +# CHECK-INST: vle64ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0x01] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 07 74 05 01 -vleff.v v8, (a0) -# CHECK-INST: vleff.v v8, (a0) +vle64ff.v v8, (a0) +# CHECK-INST: vle64ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0x03] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 07 74 05 03 -vlsb.v v8, (a0), a1, v0.t -# CHECK-INST: vlsb.v v8, (a0), a1, v0.t -# CHECK-ENCODING: [0x07,0x04,0xb5,0x18] +vle128ff.v v8, (a0), v0.t +# CHECK-INST: vle128ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x04,0x05,0x11] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 07 04 b5 18 +# CHECK-UNKNOWN: 07 04 05 11 -vlsb.v v8, (a0), a1 -# CHECK-INST: vlsb.v v8, (a0), a1 -# CHECK-ENCODING: [0x07,0x04,0xb5,0x1a] +vle128ff.v v8, (a0) +# CHECK-INST: vle128ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x04,0x05,0x13] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 07 04 b5 1a +# CHECK-UNKNOWN: 07 04 05 13 -vlsh.v v8, (a0), a1, v0.t -# CHECK-INST: vlsh.v v8, (a0), a1, v0.t -# CHECK-ENCODING: [0x07,0x54,0xb5,0x18] +vle256ff.v v8, (a0), v0.t +# CHECK-INST: vle256ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x54,0x05,0x11] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 07 54 b5 18 +# CHECK-UNKNOWN: 07 54 05 11 -vlsh.v v8, (a0), a1 -# CHECK-INST: vlsh.v v8, (a0), a1 -# CHECK-ENCODING: [0x07,0x54,0xb5,0x1a] +vle256ff.v v8, (a0) +# CHECK-INST: vle256ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x54,0x05,0x13] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 07 54 b5 1a +# CHECK-UNKNOWN: 07 54 05 13 -vlsw.v v8, (a0), a1, v0.t -# CHECK-INST: vlsw.v v8, (a0), a1, v0.t -# CHECK-ENCODING: [0x07,0x64,0xb5,0x18] +vle512ff.v v8, (a0), v0.t +# CHECK-INST: vle512ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x64,0x05,0x11] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 07 64 b5 18 +# CHECK-UNKNOWN: 07 64 05 11 -vlsw.v v8, (a0), a1 -# CHECK-INST: vlsw.v v8, (a0), a1 -# CHECK-ENCODING: [0x07,0x64,0xb5,0x1a] +vle512ff.v v8, (a0) +# CHECK-INST: vle512ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x64,0x05,0x13] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 07 64 b5 1a +# CHECK-UNKNOWN: 07 64 05 13 + +vle1024ff.v v8, (a0), v0.t +# CHECK-INST: vle1024ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x74,0x05,0x11] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 74 05 11 + +vle1024ff.v v8, (a0) +# CHECK-INST: vle1024ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x74,0x05,0x13] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 74 05 13 -vlsbu.v v8, (a0), a1, v0.t -# CHECK-INST: vlsbu.v v8, (a0), a1, v0.t +vlse8.v v8, (a0), a1, v0.t +# CHECK-INST: vlse8.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x04,0xb5,0x08] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 07 04 b5 08 -vlsbu.v v8, (a0), a1 -# CHECK-INST: vlsbu.v v8, (a0), a1 +vlse8.v v8, (a0), a1 +# CHECK-INST: vlse8.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x04,0xb5,0x0a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 07 04 b5 0a -vlshu.v v8, (a0), a1, v0.t -# CHECK-INST: vlshu.v v8, (a0), a1, v0.t +vlse16.v v8, (a0), a1, v0.t +# CHECK-INST: vlse16.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x54,0xb5,0x08] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 07 54 b5 08 -vlshu.v v8, (a0), a1 -# CHECK-INST: vlshu.v v8, (a0), a1 +vlse16.v v8, (a0), a1 +# CHECK-INST: vlse16.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x54,0xb5,0x0a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 07 54 b5 0a -vlswu.v v8, (a0), a1, v0.t -# CHECK-INST: vlswu.v v8, (a0), a1, v0.t +vlse32.v v8, (a0), a1, v0.t +# CHECK-INST: vlse32.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x64,0xb5,0x08] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 07 64 b5 08 -vlswu.v v8, (a0), a1 -# CHECK-INST: vlswu.v v8, (a0), a1 +vlse32.v v8, (a0), a1 +# CHECK-INST: vlse32.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x64,0xb5,0x0a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 07 64 b5 0a -vlse.v v8, (a0), a1, v0.t -# CHECK-INST: vlse.v v8, (a0), a1, v0.t +vlse64.v v8, (a0), a1, v0.t +# CHECK-INST: vlse64.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x74,0xb5,0x08] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 07 74 b5 08 -vlse.v v8, (a0), a1 -# CHECK-INST: vlse.v v8, (a0), a1 +vlse64.v v8, (a0), a1 +# CHECK-INST: vlse64.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x74,0xb5,0x0a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 07 74 b5 0a -vlxb.v v8, (a0), v4, v0.t -# CHECK-INST: vlxb.v v8, (a0), v4, v0.t -# CHECK-ENCODING: [0x07,0x04,0x45,0x1c] +vlse128.v v8, (a0), a1, v0.t +# CHECK-INST: vlse128.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x04,0xb5,0x18] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 07 04 45 1c +# CHECK-UNKNOWN: 07 04 b5 18 -vlxb.v v8, (a0), v4 -# CHECK-INST: vlxb.v v8, (a0), v4 -# CHECK-ENCODING: [0x07,0x04,0x45,0x1e] +vlse128.v v8, (a0), a1 +# CHECK-INST: vlse128.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x04,0xb5,0x1a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 07 04 45 1e +# CHECK-UNKNOWN: 07 04 b5 1a -vlxh.v v8, (a0), v4, v0.t -# CHECK-INST: vlxh.v v8, (a0), v4, v0.t -# CHECK-ENCODING: [0x07,0x54,0x45,0x1c] +vlse256.v v8, (a0), a1, v0.t +# CHECK-INST: vlse256.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x54,0xb5,0x18] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 07 54 45 1c +# CHECK-UNKNOWN: 07 54 b5 18 -vlxh.v v8, (a0), v4 -# CHECK-INST: vlxh.v v8, (a0), v4 -# CHECK-ENCODING: [0x07,0x54,0x45,0x1e] +vlse256.v v8, (a0), a1 +# CHECK-INST: vlse256.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x54,0xb5,0x1a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 07 54 45 1e +# CHECK-UNKNOWN: 07 54 b5 1a -vlxw.v v8, (a0), v4, v0.t -# CHECK-INST: vlxw.v v8, (a0), v4, v0.t -# CHECK-ENCODING: [0x07,0x64,0x45,0x1c] +vlse512.v v8, (a0), a1, v0.t +# CHECK-INST: vlse512.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x64,0xb5,0x18] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 07 64 45 1c +# CHECK-UNKNOWN: 07 64 b5 18 -vlxw.v v8, (a0), v4 -# CHECK-INST: vlxw.v v8, (a0), v4 -# CHECK-ENCODING: [0x07,0x64,0x45,0x1e] +vlse512.v v8, (a0), a1 +# CHECK-INST: vlse512.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x64,0xb5,0x1a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 07 64 45 1e +# CHECK-UNKNOWN: 07 64 b5 1a + +vlse1024.v v8, (a0), a1, v0.t +# CHECK-INST: vlse1024.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x74,0xb5,0x18] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 74 b5 18 -vlxbu.v v8, (a0), v4, v0.t -# CHECK-INST: vlxbu.v v8, (a0), v4, v0.t +vlse1024.v v8, (a0), a1 +# CHECK-INST: vlse1024.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x74,0xb5,0x1a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 74 b5 1a + +vlxei8.v v8, (a0), v4, v0.t +# CHECK-INST: vlxei8.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0x0c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 07 04 45 0c -vlxbu.v v8, (a0), v4 -# CHECK-INST: vlxbu.v v8, (a0), v4 +vlxei8.v v8, (a0), v4 +# CHECK-INST: vlxei8.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0x0e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 07 04 45 0e -vlxhu.v v8, (a0), v4, v0.t -# CHECK-INST: vlxhu.v v8, (a0), v4, v0.t +vlxei16.v v8, (a0), v4, v0.t +# CHECK-INST: vlxei16.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0x0c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 07 54 45 0c -vlxhu.v v8, (a0), v4 -# CHECK-INST: vlxhu.v v8, (a0), v4 +vlxei16.v v8, (a0), v4 +# CHECK-INST: vlxei16.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0x0e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 07 54 45 0e -vlxwu.v v8, (a0), v4, v0.t -# CHECK-INST: vlxwu.v v8, (a0), v4, v0.t +vlxei32.v v8, (a0), v4, v0.t +# CHECK-INST: vlxei32.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0x0c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 07 64 45 0c -vlxwu.v v8, (a0), v4 -# CHECK-INST: vlxwu.v v8, (a0), v4 +vlxei32.v v8, (a0), v4 +# CHECK-INST: vlxei32.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0x0e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 07 64 45 0e -vlxe.v v8, (a0), v4, v0.t -# CHECK-INST: vlxe.v v8, (a0), v4, v0.t +vlxei64.v v8, (a0), v4, v0.t +# CHECK-INST: vlxei64.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x74,0x45,0x0c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 07 74 45 0c -vlxe.v v8, (a0), v4 -# CHECK-INST: vlxe.v v8, (a0), v4 +vlxei64.v v8, (a0), v4 +# CHECK-INST: vlxei64.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x74,0x45,0x0e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 07 74 45 0e +vlxei128.v v8, (a0), v4, v0.t +# CHECK-INST: vlxei128.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x04,0x45,0x1c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 04 45 1c + +vlxei128.v v8, (a0), v4 +# CHECK-INST: vlxei128.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x04,0x45,0x1e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 04 45 1e + +vlxei256.v v8, (a0), v4, v0.t +# CHECK-INST: vlxei256.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x54,0x45,0x1c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 54 45 1c + +vlxei256.v v8, (a0), v4 +# CHECK-INST: vlxei256.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x54,0x45,0x1e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 54 45 1e + +vlxei512.v v8, (a0), v4, v0.t +# CHECK-INST: vlxei512.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x64,0x45,0x1c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 64 45 1c + +vlxei512.v v8, (a0), v4 +# CHECK-INST: vlxei512.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x64,0x45,0x1e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 64 45 1e + +vlxei1024.v v8, (a0), v4, v0.t +# CHECK-INST: vlxei1024.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x74,0x45,0x1c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 74 45 1c + +vlxei1024.v v8, (a0), v4 +# CHECK-INST: vlxei1024.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x74,0x45,0x1e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 07 74 45 1e + vl1r.v v8, (a0) # CHECK-INST: vl1r.v v8, (a0) -# CHECK-ENCODING: [0x07,0x74,0x85,0x02] +# CHECK-ENCODING: [0x07,0x04,0x85,0x02] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 07 74 85 02 +# CHECK-UNKNOWN: 07 04 85 02 Index: llvm/test/MC/RISCV/rvv/mask.s =================================================================== --- llvm/test/MC/RISCV/rvv/mask.s +++ llvm/test/MC/RISCV/rvv/mask.s @@ -140,8 +140,8 @@ # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 57 a4 08 52 -vmcpy.m v8, v4 -# CHECK-INST: vmcpy.m v8, v4 +vmmv.m v8, v4 +# CHECK-INST: vmmv.m v8, v4 # CHECK-ENCODING: [0x57,0x24,0x42,0x66] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 57 24 42 66 Index: llvm/test/MC/RISCV/rvv/snippet.s =================================================================== --- llvm/test/MC/RISCV/rvv/snippet.s +++ llvm/test/MC/RISCV/rvv/snippet.s @@ -5,28 +5,28 @@ # RUN: | FileCheck %s --check-prefix=CHECK-INST loop: - vsetvli a3, a0, e16,m4 # vtype = 16-bit integer vectors -# CHECK-INST: d7 76 65 00 vsetvli a3, a0, e16,m4 - vlh.v v4, (a1) # Get 16b vector -# CHECK-INST: 07 d2 05 12 vlh.v v4, (a1) - slli t1, a3, 1 # Multiply length by two bytes/element + vsetvli a3, a0, e16,m4,ta,ma # vtype = 16-bit integer vectors +# CHECK-INST: d7 76 65 0c vsetvli a3, a0, e16,m4,ta,ma + vle16.v v4, (a1) # Get 16b vector +# CHECK-INST: 07 d2 05 02 vle16.v v4, (a1) + slli t1, a3, 1 # Multiply length by two bytes/element # CHECK-INST: 13 93 16 00 slli t1, a3, 1 - add a1, a1, t1 # Bump pointer + add a1, a1, t1 # Bump pointer # CHECK-INST: b3 85 65 00 add a1, a1, t1 - vwmul.vx v8, v4, x10 # 32b in + vwmul.vx v8, v4, x10 # 32b in # CHECK-INST: 57 64 45 ee vwmul.vx v8, v4, a0 - vsetvli x0, a0, e32,m8 # Operate on 32b values -# CHECK-INST: 57 70 b5 00 vsetvli zero, a0, e32,m8 + vsetvli x0, a0, e32,m8,ta,ma # Operate on 32b values +# CHECK-INST: 57 70 b5 0c vsetvli zero, a0, e32,m8,ta,ma vsrl.vi v8, v8, 3 # CHECK-INST: 57 b4 81 a2 vsrl.vi v8, v8, 3 - vsw.v v8, (a2) # Store vector of 32b -# CHECK-INST: 27 64 06 02 vsw.v v8, (a2) - slli t1, a3, 2 # Multiply length by four bytes/element + vse32.v v8, (a2) # Store vector of 32b +# CHECK-INST: 27 64 06 02 vse32.v v8, (a2) + slli t1, a3, 2 # Multiply length by four bytes/element # CHECK-INST: 13 93 26 00 slli t1, a3, 2 - add a2, a2, t1 # Bump pointer + add a2, a2, t1 # Bump pointer # CHECK-INST: 33 06 66 00 add a2, a2, t1 - sub a0, a0, a3 # Decrement count + sub a0, a0, a3 # Decrement count # CHECK-INST: 33 05 d5 40 sub a0, a0, a3 - bnez a0, loop # Any more? + bnez a0, loop # Any more? # CHECK-INST: e3 1a 05 fc bnez a0, -44 Index: llvm/test/MC/RISCV/rvv/store.s =================================================================== --- llvm/test/MC/RISCV/rvv/store.s +++ llvm/test/MC/RISCV/rvv/store.s @@ -8,200 +8,296 @@ # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN -vsb.v v24, (a0), v0.t -# CHECK-INST: vsb.v v24, (a0), v0.t +vse8.v v24, (a0), v0.t +# CHECK-INST: vse8.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x0c,0x05,0x00] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 27 0c 05 00 -vsb.v v24, (a0) -# CHECK-INST: vsb.v v24, (a0) +vse8.v v24, (a0) +# CHECK-INST: vse8.v v24, (a0) # CHECK-ENCODING: [0x27,0x0c,0x05,0x02] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 27 0c 05 02 -vsh.v v24, (a0), v0.t -# CHECK-INST: vsh.v v24, (a0), v0.t +vse16.v v24, (a0), v0.t +# CHECK-INST: vse16.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x5c,0x05,0x00] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 27 5c 05 00 -vsh.v v24, (a0) -# CHECK-INST: vsh.v v24, (a0) +vse16.v v24, (a0) +# CHECK-INST: vse16.v v24, (a0) # CHECK-ENCODING: [0x27,0x5c,0x05,0x02] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 27 5c 05 02 -vsw.v v24, (a0), v0.t -# CHECK-INST: vsw.v v24, (a0), v0.t +vse32.v v24, (a0), v0.t +# CHECK-INST: vse32.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x6c,0x05,0x00] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 27 6c 05 00 -vsw.v v24, (a0) -# CHECK-INST: vsw.v v24, (a0) +vse32.v v24, (a0) +# CHECK-INST: vse32.v v24, (a0) # CHECK-ENCODING: [0x27,0x6c,0x05,0x02] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 27 6c 05 02 -vse.v v24, (a0), v0.t -# CHECK-INST: vse.v v24, (a0), v0.t +vse64.v v24, (a0), v0.t +# CHECK-INST: vse64.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x7c,0x05,0x00] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 27 7c 05 00 -vse.v v24, (a0) -# CHECK-INST: vse.v v24, (a0) +vse64.v v24, (a0) +# CHECK-INST: vse64.v v24, (a0) # CHECK-ENCODING: [0x27,0x7c,0x05,0x02] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 27 7c 05 02 -vssb.v v24, (a0), a1, v0.t -# CHECK-INST: vssb.v v24, (a0), a1, v0.t +vse128.v v24, (a0), v0.t +# CHECK-INST: vse128.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x0c,0x05,0x10] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 27 0c 05 10 + +vse128.v v24, (a0) +# CHECK-INST: vse128.v v24, (a0) +# CHECK-ENCODING: [0x27,0x0c,0x05,0x12] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 27 0c 05 12 + +vse256.v v24, (a0), v0.t +# CHECK-INST: vse256.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x5c,0x05,0x10] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 27 5c 05 10 + +vse256.v v24, (a0) +# CHECK-INST: vse256.v v24, (a0) +# CHECK-ENCODING: [0x27,0x5c,0x05,0x12] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 27 5c 05 12 + +vse512.v v24, (a0), v0.t +# CHECK-INST: vse512.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x6c,0x05,0x10] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 27 6c 05 10 + +vse512.v v24, (a0) +# CHECK-INST: vse512.v v24, (a0) +# CHECK-ENCODING: [0x27,0x6c,0x05,0x12] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 27 6c 05 12 + +vse1024.v v24, (a0), v0.t +# CHECK-INST: vse1024.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x7c,0x05,0x10] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 27 7c 05 10 + +vse1024.v v24, (a0) +# CHECK-INST: vse1024.v v24, (a0) +# CHECK-ENCODING: [0x27,0x7c,0x05,0x12] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 27 7c 05 12 + +vsse8.v v24, (a0), a1, v0.t +# CHECK-INST: vsse8.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x0c,0xb5,0x08] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 27 0c b5 08 -vssb.v v24, (a0), a1 -# CHECK-INST: vssb.v v24, (a0), a1 +vsse8.v v24, (a0), a1 +# CHECK-INST: vsse8.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x0c,0xb5,0x0a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 27 0c b5 0a -vssh.v v24, (a0), a1, v0.t -# CHECK-INST: vssh.v v24, (a0), a1, v0.t +vsse16.v v24, (a0), a1, v0.t +# CHECK-INST: vsse16.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x5c,0xb5,0x08] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 27 5c b5 08 -vssh.v v24, (a0), a1 -# CHECK-INST: vssh.v v24, (a0), a1 +vsse16.v v24, (a0), a1 +# CHECK-INST: vsse16.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x5c,0xb5,0x0a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 27 5c b5 0a -vssw.v v24, (a0), a1, v0.t -# CHECK-INST: vssw.v v24, (a0), a1, v0.t +vsse32.v v24, (a0), a1, v0.t +# CHECK-INST: vsse32.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x6c,0xb5,0x08] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 27 6c b5 08 -vssw.v v24, (a0), a1 -# CHECK-INST: vssw.v v24, (a0), a1 +vsse32.v v24, (a0), a1 +# CHECK-INST: vsse32.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x6c,0xb5,0x0a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 27 6c b5 0a -vsse.v v24, (a0), a1, v0.t -# CHECK-INST: vsse.v v24, (a0), a1, v0.t +vsse64.v v24, (a0), a1, v0.t +# CHECK-INST: vsse64.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x7c,0xb5,0x08] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 27 7c b5 08 -vsse.v v24, (a0), a1 -# CHECK-INST: vsse.v v24, (a0), a1 +vsse64.v v24, (a0), a1 +# CHECK-INST: vsse64.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x7c,0xb5,0x0a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 27 7c b5 0a -vsxb.v v24, (a0), v4, v0.t -# CHECK-INST: vsxb.v v24, (a0), v4, v0.t +vsse128.v v24, (a0), a1, v0.t +# CHECK-INST: vsse128.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x0c,0xb5,0x18] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 27 0c b5 18 + +vsse128.v v24, (a0), a1 +# CHECK-INST: vsse128.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x0c,0xb5,0x1a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 27 0c b5 1a + +vsse256.v v24, (a0), a1, v0.t +# CHECK-INST: vsse256.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x5c,0xb5,0x18] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 27 5c b5 18 + +vsse256.v v24, (a0), a1 +# CHECK-INST: vsse256.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x5c,0xb5,0x1a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 27 5c b5 1a + +vsse512.v v24, (a0), a1, v0.t +# CHECK-INST: vsse512.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x6c,0xb5,0x18] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 27 6c b5 18 + +vsse512.v v24, (a0), a1 +# CHECK-INST: vsse512.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x6c,0xb5,0x1a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 27 6c b5 1a + +vsse1024.v v24, (a0), a1, v0.t +# CHECK-INST: vsse1024.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x7c,0xb5,0x18] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 27 7c b5 18 + +vsse1024.v v24, (a0), a1 +# CHECK-INST: vsse1024.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x7c,0xb5,0x1a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 27 7c b5 1a + +vsxei8.v v24, (a0), v4, v0.t +# CHECK-INST: vsxei8.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x0c,0x45,0x0c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 27 0c 45 0c -vsxb.v v24, (a0), v4 -# CHECK-INST: vsxb.v v24, (a0), v4 +vsxei8.v v24, (a0), v4 +# CHECK-INST: vsxei8.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x0c,0x45,0x0e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 27 0c 45 0e -vsxh.v v24, (a0), v4, v0.t -# CHECK-INST: vsxh.v v24, (a0), v4, v0.t +vsxei16.v v24, (a0), v4, v0.t +# CHECK-INST: vsxei16.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x5c,0x45,0x0c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 27 5c 45 0c -vsxh.v v24, (a0), v4 -# CHECK-INST: vsxh.v v24, (a0), v4 +vsxei16.v v24, (a0), v4 +# CHECK-INST: vsxei16.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x5c,0x45,0x0e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 27 5c 45 0e -vsxw.v v24, (a0), v4, v0.t -# CHECK-INST: vsxw.v v24, (a0), v4, v0.t +vsxei32.v v24, (a0), v4, v0.t +# CHECK-INST: vsxei32.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x6c,0x45,0x0c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 27 6c 45 0c -vsxw.v v24, (a0), v4 -# CHECK-INST: vsxw.v v24, (a0), v4 +vsxei32.v v24, (a0), v4 +# CHECK-INST: vsxei32.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x6c,0x45,0x0e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 27 6c 45 0e -vsxe.v v24, (a0), v4, v0.t -# CHECK-INST: vsxe.v v24, (a0), v4, v0.t +vsxei64.v v24, (a0), v4, v0.t +# CHECK-INST: vsxei64.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x7c,0x45,0x0c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 27 7c 45 0c -vsxe.v v24, (a0), v4 -# CHECK-INST: vsxe.v v24, (a0), v4 +vsxei64.v v24, (a0), v4 +# CHECK-INST: vsxei64.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x7c,0x45,0x0e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 27 7c 45 0e -vsuxb.v v24, (a0), v4, v0.t -# CHECK-INST: vsuxb.v v24, (a0), v4, v0.t +vsxei128.v v24, (a0), v4, v0.t +# CHECK-INST: vsxei128.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x0c,0x45,0x1c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 27 0c 45 1c -vsuxb.v v24, (a0), v4 -# CHECK-INST: vsuxb.v v24, (a0), v4 +vsxei128.v v24, (a0), v4 +# CHECK-INST: vsxei128.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x0c,0x45,0x1e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 27 0c 45 1e -vsuxh.v v24, (a0), v4, v0.t -# CHECK-INST: vsuxh.v v24, (a0), v4, v0.t +vsxei256.v v24, (a0), v4, v0.t +# CHECK-INST: vsxei256.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x5c,0x45,0x1c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 27 5c 45 1c -vsuxh.v v24, (a0), v4 -# CHECK-INST: vsuxh.v v24, (a0), v4 +vsxei256.v v24, (a0), v4 +# CHECK-INST: vsxei256.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x5c,0x45,0x1e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 27 5c 45 1e -vsuxw.v v24, (a0), v4, v0.t -# CHECK-INST: vsuxw.v v24, (a0), v4, v0.t +vsxei512.v v24, (a0), v4, v0.t +# CHECK-INST: vsxei512.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x6c,0x45,0x1c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 27 6c 45 1c -vsuxw.v v24, (a0), v4 -# CHECK-INST: vsuxw.v v24, (a0), v4 +vsxei512.v v24, (a0), v4 +# CHECK-INST: vsxei512.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x6c,0x45,0x1e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 27 6c 45 1e -vsuxe.v v24, (a0), v4, v0.t -# CHECK-INST: vsuxe.v v24, (a0), v4, v0.t +vsxei1024.v v24, (a0), v4, v0.t +# CHECK-INST: vsxei1024.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x7c,0x45,0x1c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 27 7c 45 1c -vsuxe.v v24, (a0), v4 -# CHECK-INST: vsuxe.v v24, (a0), v4 +vsxei1024.v v24, (a0), v4 +# CHECK-INST: vsxei1024.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x7c,0x45,0x1e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) # CHECK-UNKNOWN: 27 7c 45 1e vs1r.v v24, (a0) # CHECK-INST: vs1r.v v24, (a0) -# CHECK-ENCODING: [0x27,0x7c,0x85,0x02] +# CHECK-ENCODING: [0x27,0x0c,0x85,0x02] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 27 7c 85 02 +# CHECK-UNKNOWN: 27 0c 85 02 Index: llvm/test/MC/RISCV/rvv/vsetvl.s =================================================================== --- llvm/test/MC/RISCV/rvv/vsetvl.s +++ llvm/test/MC/RISCV/rvv/vsetvl.s @@ -8,11 +8,71 @@ # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \ # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN -vsetvli a2, a0, e32,m4 -# CHECK-INST: vsetvli a2, a0, e32,m4 -# CHECK-ENCODING: [0x57,0x76,0xa5,0x00] +vsetvli a2, a0, e32,m1,ta,ma +# CHECK-INST: vsetvli a2, a0, e32,m1,ta,ma +# CHECK-ENCODING: [0x57,0x76,0x85,0x0c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 57 76 a5 00 +# CHECK-UNKNOWN: 57 76 85 0c + +vsetvli a2, a0, e32,m2,ta,ma +# CHECK-INST: vsetvli a2, a0, e32,m2,ta,ma +# CHECK-ENCODING: [0x57,0x76,0x95,0x0c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 76 95 0c + +vsetvli a2, a0, e32,m4,ta,ma +# CHECK-INST: vsetvli a2, a0, e32,m4,ta,ma +# CHECK-ENCODING: [0x57,0x76,0xa5,0x0c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 76 a5 0c + +vsetvli a2, a0, e32,m8,ta,ma +# CHECK-INST: vsetvli a2, a0, e32,m8,ta,ma +# CHECK-ENCODING: [0x57,0x76,0xb5,0x0c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 76 b5 0c + +vsetvli a2, a0, e32,mf2,ta,ma +# CHECK-INST: vsetvli a2, a0, e32,mf2,ta,ma +# CHECK-ENCODING: [0x57,0x76,0xb5,0x0e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 76 b5 0e + +vsetvli a2, a0, e32,mf4,ta,ma +# CHECK-INST: vsetvli a2, a0, e32,mf4,ta,ma +# CHECK-ENCODING: [0x57,0x76,0xa5,0x0e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 76 a5 0e + +vsetvli a2, a0, e32,mf8,ta,ma +# CHECK-INST: vsetvli a2, a0, e32,mf8,ta,ma +# CHECK-ENCODING: [0x57,0x76,0x95,0x0e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 76 95 0e + +vsetvli a2, a0, e32,m1,ta,ma +# CHECK-INST: vsetvli a2, a0, e32,m1,ta,ma +# CHECK-ENCODING: [0x57,0x76,0x85,0x0c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 76 85 0c + +vsetvli a2, a0, e32,m1,tu,ma +# CHECK-INST: vsetvli a2, a0, e32,m1,tu,ma +# CHECK-ENCODING: [0x57,0x76,0x85,0x08] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 76 85 08 + +vsetvli a2, a0, e32,m1,ta,mu +# CHECK-INST: vsetvli a2, a0, e32,m1,ta,mu +# CHECK-ENCODING: [0x57,0x76,0x85,0x04] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 76 85 04 + +vsetvli a2, a0, e32,m1,tu,mu +# CHECK-INST: vsetvli a2, a0, e32,m1 +# CHECK-ENCODING: [0x57,0x76,0x85,0x00] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) +# CHECK-UNKNOWN: 57 76 85 00 vsetvl a2, a0, a1 # CHECK-INST: vsetvl a2, a0, a1 Index: llvm/test/MC/RISCV/rvv/zvlsseg.s =================================================================== --- /dev/null +++ llvm/test/MC/RISCV/rvv/zvlsseg.s @@ -0,0 +1,4713 @@ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v,experimental-zvlsseg %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v,experimental-zvlsseg %s \ +# RUN: | llvm-objdump -d --mattr=+experimental-v,experimental-zvlsseg - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v,experimental-zvlsseg %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +vlseg2e8.v v8, (a0) +# CHECK-INST: vlseg2e8.v v8, (a0) +# CHECK-ENCODING: [0x07,0x04,0x05,0x22] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 22 + +vlseg2e16.v v8, (a0) +# CHECK-INST: vlseg2e16.v v8, (a0) +# CHECK-ENCODING: [0x07,0x54,0x05,0x22] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 22 + +vlseg2e32.v v8, (a0) +# CHECK-INST: vlseg2e32.v v8, (a0) +# CHECK-ENCODING: [0x07,0x64,0x05,0x22] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 22 + +vlseg2e64.v v8, (a0) +# CHECK-INST: vlseg2e64.v v8, (a0) +# CHECK-ENCODING: [0x07,0x74,0x05,0x22] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 22 + +vlseg2e128.v v8, (a0) +# CHECK-INST: vlseg2e128.v v8, (a0) +# CHECK-ENCODING: [0x07,0x04,0x05,0x32] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 32 + +vlseg2e256.v v8, (a0) +# CHECK-INST: vlseg2e256.v v8, (a0) +# CHECK-ENCODING: [0x07,0x54,0x05,0x32] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 32 + +vlseg2e512.v v8, (a0) +# CHECK-INST: vlseg2e512.v v8, (a0) +# CHECK-ENCODING: [0x07,0x64,0x05,0x32] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 32 + +vlseg2e1024.v v8, (a0) +# CHECK-INST: vlseg2e1024.v v8, (a0) +# CHECK-ENCODING: [0x07,0x74,0x05,0x32] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 32 + +vlseg2e8.v v8, (a0), v0.t +# CHECK-INST: vlseg2e8.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x04,0x05,0x20] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 20 + +vlseg2e16.v v8, (a0), v0.t +# CHECK-INST: vlseg2e16.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x54,0x05,0x20] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 20 + +vlseg2e32.v v8, (a0), v0.t +# CHECK-INST: vlseg2e32.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x64,0x05,0x20] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 20 + +vlseg2e64.v v8, (a0), v0.t +# CHECK-INST: vlseg2e64.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x74,0x05,0x20] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 20 + +vlseg2e128.v v8, (a0), v0.t +# CHECK-INST: vlseg2e128.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x04,0x05,0x30] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 30 + +vlseg2e256.v v8, (a0), v0.t +# CHECK-INST: vlseg2e256.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x54,0x05,0x30] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 30 + +vlseg2e512.v v8, (a0), v0.t +# CHECK-INST: vlseg2e512.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x64,0x05,0x30] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 30 + +vlseg2e1024.v v8, (a0), v0.t +# CHECK-INST: vlseg2e1024.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x74,0x05,0x30] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 30 + +vlseg3e8.v v8, (a0) +# CHECK-INST: vlseg3e8.v v8, (a0) +# CHECK-ENCODING: [0x07,0x04,0x05,0x42] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 42 + +vlseg3e16.v v8, (a0) +# CHECK-INST: vlseg3e16.v v8, (a0) +# CHECK-ENCODING: [0x07,0x54,0x05,0x42] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 42 + +vlseg3e32.v v8, (a0) +# CHECK-INST: vlseg3e32.v v8, (a0) +# CHECK-ENCODING: [0x07,0x64,0x05,0x42] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 42 + +vlseg3e64.v v8, (a0) +# CHECK-INST: vlseg3e64.v v8, (a0) +# CHECK-ENCODING: [0x07,0x74,0x05,0x42] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 42 + +vlseg3e128.v v8, (a0) +# CHECK-INST: vlseg3e128.v v8, (a0) +# CHECK-ENCODING: [0x07,0x04,0x05,0x52] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 52 + +vlseg3e256.v v8, (a0) +# CHECK-INST: vlseg3e256.v v8, (a0) +# CHECK-ENCODING: [0x07,0x54,0x05,0x52] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 52 + +vlseg3e512.v v8, (a0) +# CHECK-INST: vlseg3e512.v v8, (a0) +# CHECK-ENCODING: [0x07,0x64,0x05,0x52] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 52 + +vlseg3e1024.v v8, (a0) +# CHECK-INST: vlseg3e1024.v v8, (a0) +# CHECK-ENCODING: [0x07,0x74,0x05,0x52] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 52 + +vlseg3e8.v v8, (a0), v0.t +# CHECK-INST: vlseg3e8.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x04,0x05,0x40] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 40 + +vlseg3e16.v v8, (a0), v0.t +# CHECK-INST: vlseg3e16.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x54,0x05,0x40] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 40 + +vlseg3e32.v v8, (a0), v0.t +# CHECK-INST: vlseg3e32.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x64,0x05,0x40] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 40 + +vlseg3e64.v v8, (a0), v0.t +# CHECK-INST: vlseg3e64.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x74,0x05,0x40] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 40 + +vlseg3e128.v v8, (a0), v0.t +# CHECK-INST: vlseg3e128.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x04,0x05,0x50] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 50 + +vlseg3e256.v v8, (a0), v0.t +# CHECK-INST: vlseg3e256.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x54,0x05,0x50] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 50 + +vlseg3e512.v v8, (a0), v0.t +# CHECK-INST: vlseg3e512.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x64,0x05,0x50] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 50 + +vlseg3e1024.v v8, (a0), v0.t +# CHECK-INST: vlseg3e1024.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x74,0x05,0x50] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 50 + +vlseg4e8.v v8, (a0) +# CHECK-INST: vlseg4e8.v v8, (a0) +# CHECK-ENCODING: [0x07,0x04,0x05,0x62] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 62 + +vlseg4e16.v v8, (a0) +# CHECK-INST: vlseg4e16.v v8, (a0) +# CHECK-ENCODING: [0x07,0x54,0x05,0x62] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 62 + +vlseg4e32.v v8, (a0) +# CHECK-INST: vlseg4e32.v v8, (a0) +# CHECK-ENCODING: [0x07,0x64,0x05,0x62] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 62 + +vlseg4e64.v v8, (a0) +# CHECK-INST: vlseg4e64.v v8, (a0) +# CHECK-ENCODING: [0x07,0x74,0x05,0x62] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 62 + +vlseg4e128.v v8, (a0) +# CHECK-INST: vlseg4e128.v v8, (a0) +# CHECK-ENCODING: [0x07,0x04,0x05,0x72] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 72 + +vlseg4e256.v v8, (a0) +# CHECK-INST: vlseg4e256.v v8, (a0) +# CHECK-ENCODING: [0x07,0x54,0x05,0x72] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 72 + +vlseg4e512.v v8, (a0) +# CHECK-INST: vlseg4e512.v v8, (a0) +# CHECK-ENCODING: [0x07,0x64,0x05,0x72] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 72 + +vlseg4e1024.v v8, (a0) +# CHECK-INST: vlseg4e1024.v v8, (a0) +# CHECK-ENCODING: [0x07,0x74,0x05,0x72] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 72 + +vlseg4e8.v v8, (a0), v0.t +# CHECK-INST: vlseg4e8.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x04,0x05,0x60] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 60 + +vlseg4e16.v v8, (a0), v0.t +# CHECK-INST: vlseg4e16.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x54,0x05,0x60] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 60 + +vlseg4e32.v v8, (a0), v0.t +# CHECK-INST: vlseg4e32.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x64,0x05,0x60] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 60 + +vlseg4e64.v v8, (a0), v0.t +# CHECK-INST: vlseg4e64.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x74,0x05,0x60] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 60 + +vlseg4e128.v v8, (a0), v0.t +# CHECK-INST: vlseg4e128.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x04,0x05,0x70] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 70 + +vlseg4e256.v v8, (a0), v0.t +# CHECK-INST: vlseg4e256.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x54,0x05,0x70] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 70 + +vlseg4e512.v v8, (a0), v0.t +# CHECK-INST: vlseg4e512.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x64,0x05,0x70] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 70 + +vlseg4e1024.v v8, (a0), v0.t +# CHECK-INST: vlseg4e1024.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x74,0x05,0x70] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 70 + +vlseg5e8.v v8, (a0) +# CHECK-INST: vlseg5e8.v v8, (a0) +# CHECK-ENCODING: [0x07,0x04,0x05,0x82] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 82 + +vlseg5e16.v v8, (a0) +# CHECK-INST: vlseg5e16.v v8, (a0) +# CHECK-ENCODING: [0x07,0x54,0x05,0x82] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 82 + +vlseg5e32.v v8, (a0) +# CHECK-INST: vlseg5e32.v v8, (a0) +# CHECK-ENCODING: [0x07,0x64,0x05,0x82] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 82 + +vlseg5e64.v v8, (a0) +# CHECK-INST: vlseg5e64.v v8, (a0) +# CHECK-ENCODING: [0x07,0x74,0x05,0x82] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 82 + +vlseg5e128.v v8, (a0) +# CHECK-INST: vlseg5e128.v v8, (a0) +# CHECK-ENCODING: [0x07,0x04,0x05,0x92] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 92 + +vlseg5e256.v v8, (a0) +# CHECK-INST: vlseg5e256.v v8, (a0) +# CHECK-ENCODING: [0x07,0x54,0x05,0x92] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 92 + +vlseg5e512.v v8, (a0) +# CHECK-INST: vlseg5e512.v v8, (a0) +# CHECK-ENCODING: [0x07,0x64,0x05,0x92] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 92 + +vlseg5e1024.v v8, (a0) +# CHECK-INST: vlseg5e1024.v v8, (a0) +# CHECK-ENCODING: [0x07,0x74,0x05,0x92] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 92 + +vlseg5e8.v v8, (a0), v0.t +# CHECK-INST: vlseg5e8.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x04,0x05,0x80] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 80 + +vlseg5e16.v v8, (a0), v0.t +# CHECK-INST: vlseg5e16.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x54,0x05,0x80] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 80 + +vlseg5e32.v v8, (a0), v0.t +# CHECK-INST: vlseg5e32.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x64,0x05,0x80] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 80 + +vlseg5e64.v v8, (a0), v0.t +# CHECK-INST: vlseg5e64.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x74,0x05,0x80] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 80 + +vlseg5e128.v v8, (a0), v0.t +# CHECK-INST: vlseg5e128.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x04,0x05,0x90] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 90 + +vlseg5e256.v v8, (a0), v0.t +# CHECK-INST: vlseg5e256.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x54,0x05,0x90] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 90 + +vlseg5e512.v v8, (a0), v0.t +# CHECK-INST: vlseg5e512.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x64,0x05,0x90] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 90 + +vlseg5e1024.v v8, (a0), v0.t +# CHECK-INST: vlseg5e1024.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x74,0x05,0x90] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 90 + +vlseg6e8.v v8, (a0) +# CHECK-INST: vlseg6e8.v v8, (a0) +# CHECK-ENCODING: [0x07,0x04,0x05,0xa2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 a2 + +vlseg6e16.v v8, (a0) +# CHECK-INST: vlseg6e16.v v8, (a0) +# CHECK-ENCODING: [0x07,0x54,0x05,0xa2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 a2 + +vlseg6e32.v v8, (a0) +# CHECK-INST: vlseg6e32.v v8, (a0) +# CHECK-ENCODING: [0x07,0x64,0x05,0xa2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 a2 + +vlseg6e64.v v8, (a0) +# CHECK-INST: vlseg6e64.v v8, (a0) +# CHECK-ENCODING: [0x07,0x74,0x05,0xa2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 a2 + +vlseg6e128.v v8, (a0) +# CHECK-INST: vlseg6e128.v v8, (a0) +# CHECK-ENCODING: [0x07,0x04,0x05,0xb2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 b2 + +vlseg6e256.v v8, (a0) +# CHECK-INST: vlseg6e256.v v8, (a0) +# CHECK-ENCODING: [0x07,0x54,0x05,0xb2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 b2 + +vlseg6e512.v v8, (a0) +# CHECK-INST: vlseg6e512.v v8, (a0) +# CHECK-ENCODING: [0x07,0x64,0x05,0xb2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 b2 + +vlseg6e1024.v v8, (a0) +# CHECK-INST: vlseg6e1024.v v8, (a0) +# CHECK-ENCODING: [0x07,0x74,0x05,0xb2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 b2 + +vlseg6e8.v v8, (a0), v0.t +# CHECK-INST: vlseg6e8.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x04,0x05,0xa0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 a0 + +vlseg6e16.v v8, (a0), v0.t +# CHECK-INST: vlseg6e16.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x54,0x05,0xa0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 a0 + +vlseg6e32.v v8, (a0), v0.t +# CHECK-INST: vlseg6e32.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x64,0x05,0xa0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 a0 + +vlseg6e64.v v8, (a0), v0.t +# CHECK-INST: vlseg6e64.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x74,0x05,0xa0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 a0 + +vlseg6e128.v v8, (a0), v0.t +# CHECK-INST: vlseg6e128.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x04,0x05,0xb0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 b0 + +vlseg6e256.v v8, (a0), v0.t +# CHECK-INST: vlseg6e256.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x54,0x05,0xb0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 b0 + +vlseg6e512.v v8, (a0), v0.t +# CHECK-INST: vlseg6e512.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x64,0x05,0xb0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 b0 + +vlseg6e1024.v v8, (a0), v0.t +# CHECK-INST: vlseg6e1024.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x74,0x05,0xb0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 b0 + +vlseg7e8.v v8, (a0) +# CHECK-INST: vlseg7e8.v v8, (a0) +# CHECK-ENCODING: [0x07,0x04,0x05,0xc2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 c2 + +vlseg7e16.v v8, (a0) +# CHECK-INST: vlseg7e16.v v8, (a0) +# CHECK-ENCODING: [0x07,0x54,0x05,0xc2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 c2 + +vlseg7e32.v v8, (a0) +# CHECK-INST: vlseg7e32.v v8, (a0) +# CHECK-ENCODING: [0x07,0x64,0x05,0xc2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 c2 + +vlseg7e64.v v8, (a0) +# CHECK-INST: vlseg7e64.v v8, (a0) +# CHECK-ENCODING: [0x07,0x74,0x05,0xc2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 c2 + +vlseg7e128.v v8, (a0) +# CHECK-INST: vlseg7e128.v v8, (a0) +# CHECK-ENCODING: [0x07,0x04,0x05,0xd2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 d2 + +vlseg7e256.v v8, (a0) +# CHECK-INST: vlseg7e256.v v8, (a0) +# CHECK-ENCODING: [0x07,0x54,0x05,0xd2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 d2 + +vlseg7e512.v v8, (a0) +# CHECK-INST: vlseg7e512.v v8, (a0) +# CHECK-ENCODING: [0x07,0x64,0x05,0xd2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 d2 + +vlseg7e1024.v v8, (a0) +# CHECK-INST: vlseg7e1024.v v8, (a0) +# CHECK-ENCODING: [0x07,0x74,0x05,0xd2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 d2 + +vlseg7e8.v v8, (a0), v0.t +# CHECK-INST: vlseg7e8.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x04,0x05,0xc0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 c0 + +vlseg7e16.v v8, (a0), v0.t +# CHECK-INST: vlseg7e16.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x54,0x05,0xc0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 c0 + +vlseg7e32.v v8, (a0), v0.t +# CHECK-INST: vlseg7e32.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x64,0x05,0xc0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 c0 + +vlseg7e64.v v8, (a0), v0.t +# CHECK-INST: vlseg7e64.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x74,0x05,0xc0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 c0 + +vlseg7e128.v v8, (a0), v0.t +# CHECK-INST: vlseg7e128.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x04,0x05,0xd0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 d0 + +vlseg7e256.v v8, (a0), v0.t +# CHECK-INST: vlseg7e256.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x54,0x05,0xd0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 d0 + +vlseg7e512.v v8, (a0), v0.t +# CHECK-INST: vlseg7e512.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x64,0x05,0xd0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 d0 + +vlseg7e1024.v v8, (a0), v0.t +# CHECK-INST: vlseg7e1024.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x74,0x05,0xd0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 d0 + +vlseg8e8.v v8, (a0) +# CHECK-INST: vlseg8e8.v v8, (a0) +# CHECK-ENCODING: [0x07,0x04,0x05,0xe2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 e2 + +vlseg8e16.v v8, (a0) +# CHECK-INST: vlseg8e16.v v8, (a0) +# CHECK-ENCODING: [0x07,0x54,0x05,0xe2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 e2 + +vlseg8e32.v v8, (a0) +# CHECK-INST: vlseg8e32.v v8, (a0) +# CHECK-ENCODING: [0x07,0x64,0x05,0xe2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 e2 + +vlseg8e64.v v8, (a0) +# CHECK-INST: vlseg8e64.v v8, (a0) +# CHECK-ENCODING: [0x07,0x74,0x05,0xe2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 e2 + +vlseg8e128.v v8, (a0) +# CHECK-INST: vlseg8e128.v v8, (a0) +# CHECK-ENCODING: [0x07,0x04,0x05,0xf2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 f2 + +vlseg8e256.v v8, (a0) +# CHECK-INST: vlseg8e256.v v8, (a0) +# CHECK-ENCODING: [0x07,0x54,0x05,0xf2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 f2 + +vlseg8e512.v v8, (a0) +# CHECK-INST: vlseg8e512.v v8, (a0) +# CHECK-ENCODING: [0x07,0x64,0x05,0xf2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 f2 + +vlseg8e1024.v v8, (a0) +# CHECK-INST: vlseg8e1024.v v8, (a0) +# CHECK-ENCODING: [0x07,0x74,0x05,0xf2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 f2 + +vlseg8e8.v v8, (a0), v0.t +# CHECK-INST: vlseg8e8.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x04,0x05,0xe0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 e0 + +vlseg8e16.v v8, (a0), v0.t +# CHECK-INST: vlseg8e16.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x54,0x05,0xe0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 e0 + +vlseg8e32.v v8, (a0), v0.t +# CHECK-INST: vlseg8e32.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x64,0x05,0xe0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 e0 + +vlseg8e64.v v8, (a0), v0.t +# CHECK-INST: vlseg8e64.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x74,0x05,0xe0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 e0 + +vlseg8e128.v v8, (a0), v0.t +# CHECK-INST: vlseg8e128.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x04,0x05,0xf0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 f0 + +vlseg8e256.v v8, (a0), v0.t +# CHECK-INST: vlseg8e256.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x54,0x05,0xf0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 f0 + +vlseg8e512.v v8, (a0), v0.t +# CHECK-INST: vlseg8e512.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x64,0x05,0xf0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 f0 + +vlseg8e1024.v v8, (a0), v0.t +# CHECK-INST: vlseg8e1024.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x74,0x05,0xf0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 f0 + +vlsseg2e8.v v8, (a0), a1 +# CHECK-INST: vlsseg2e8.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x04,0xb5,0x2a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 b5 2a + +vlsseg2e16.v v8, (a0), a1 +# CHECK-INST: vlsseg2e16.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x54,0xb5,0x2a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 b5 2a + +vlsseg2e32.v v8, (a0), a1 +# CHECK-INST: vlsseg2e32.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x64,0xb5,0x2a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 b5 2a + +vlsseg2e64.v v8, (a0), a1 +# CHECK-INST: vlsseg2e64.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x74,0xb5,0x2a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 b5 2a + +vlsseg2e128.v v8, (a0), a1 +# CHECK-INST: vlsseg2e128.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x04,0xb5,0x3a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 b5 3a + +vlsseg2e256.v v8, (a0), a1 +# CHECK-INST: vlsseg2e256.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x54,0xb5,0x3a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 b5 3a + +vlsseg2e512.v v8, (a0), a1 +# CHECK-INST: vlsseg2e512.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x64,0xb5,0x3a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 b5 3a + +vlsseg2e1024.v v8, (a0), a1 +# CHECK-INST: vlsseg2e1024.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x74,0xb5,0x3a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 b5 3a + +vlsseg2e8.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg2e8.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x04,0xb5,0x28] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 b5 28 + +vlsseg2e16.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg2e16.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x54,0xb5,0x28] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 b5 28 + +vlsseg2e32.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg2e32.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x64,0xb5,0x28] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 b5 28 + +vlsseg2e64.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg2e64.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x74,0xb5,0x28] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 b5 28 + +vlsseg2e128.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg2e128.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x04,0xb5,0x38] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 b5 38 + +vlsseg2e256.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg2e256.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x54,0xb5,0x38] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 b5 38 + +vlsseg2e512.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg2e512.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x64,0xb5,0x38] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 b5 38 + +vlsseg2e1024.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg2e1024.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x74,0xb5,0x38] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 b5 38 + +vlsseg3e8.v v8, (a0), a1 +# CHECK-INST: vlsseg3e8.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x04,0xb5,0x4a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 b5 4a + +vlsseg3e16.v v8, (a0), a1 +# CHECK-INST: vlsseg3e16.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x54,0xb5,0x4a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 b5 4a + +vlsseg3e32.v v8, (a0), a1 +# CHECK-INST: vlsseg3e32.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x64,0xb5,0x4a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 b5 4a + +vlsseg3e64.v v8, (a0), a1 +# CHECK-INST: vlsseg3e64.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x74,0xb5,0x4a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 b5 4a + +vlsseg3e128.v v8, (a0), a1 +# CHECK-INST: vlsseg3e128.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x04,0xb5,0x5a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 b5 5a + +vlsseg3e256.v v8, (a0), a1 +# CHECK-INST: vlsseg3e256.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x54,0xb5,0x5a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 b5 5a + +vlsseg3e512.v v8, (a0), a1 +# CHECK-INST: vlsseg3e512.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x64,0xb5,0x5a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 b5 5a + +vlsseg3e1024.v v8, (a0), a1 +# CHECK-INST: vlsseg3e1024.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x74,0xb5,0x5a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 b5 5a + +vlsseg3e8.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg3e8.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x04,0xb5,0x48] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 b5 48 + +vlsseg3e16.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg3e16.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x54,0xb5,0x48] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 b5 48 + +vlsseg3e32.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg3e32.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x64,0xb5,0x48] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 b5 48 + +vlsseg3e64.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg3e64.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x74,0xb5,0x48] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 b5 48 + +vlsseg3e128.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg3e128.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x04,0xb5,0x58] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 b5 58 + +vlsseg3e256.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg3e256.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x54,0xb5,0x58] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 b5 58 + +vlsseg3e512.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg3e512.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x64,0xb5,0x58] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 b5 58 + +vlsseg3e1024.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg3e1024.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x74,0xb5,0x58] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 b5 58 + +vlsseg4e8.v v8, (a0), a1 +# CHECK-INST: vlsseg4e8.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x04,0xb5,0x6a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 b5 6a + +vlsseg4e16.v v8, (a0), a1 +# CHECK-INST: vlsseg4e16.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x54,0xb5,0x6a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 b5 6a + +vlsseg4e32.v v8, (a0), a1 +# CHECK-INST: vlsseg4e32.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x64,0xb5,0x6a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 b5 6a + +vlsseg4e64.v v8, (a0), a1 +# CHECK-INST: vlsseg4e64.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x74,0xb5,0x6a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 b5 6a + +vlsseg4e128.v v8, (a0), a1 +# CHECK-INST: vlsseg4e128.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x04,0xb5,0x7a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 b5 7a + +vlsseg4e256.v v8, (a0), a1 +# CHECK-INST: vlsseg4e256.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x54,0xb5,0x7a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 b5 7a + +vlsseg4e512.v v8, (a0), a1 +# CHECK-INST: vlsseg4e512.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x64,0xb5,0x7a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 b5 7a + +vlsseg4e1024.v v8, (a0), a1 +# CHECK-INST: vlsseg4e1024.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x74,0xb5,0x7a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 b5 7a + +vlsseg4e8.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg4e8.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x04,0xb5,0x68] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 b5 68 + +vlsseg4e16.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg4e16.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x54,0xb5,0x68] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 b5 68 + +vlsseg4e32.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg4e32.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x64,0xb5,0x68] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 b5 68 + +vlsseg4e64.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg4e64.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x74,0xb5,0x68] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 b5 68 + +vlsseg4e128.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg4e128.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x04,0xb5,0x78] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 b5 78 + +vlsseg4e256.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg4e256.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x54,0xb5,0x78] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 b5 78 + +vlsseg4e512.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg4e512.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x64,0xb5,0x78] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 b5 78 + +vlsseg4e1024.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg4e1024.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x74,0xb5,0x78] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 b5 78 + +vlsseg5e8.v v8, (a0), a1 +# CHECK-INST: vlsseg5e8.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x04,0xb5,0x8a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 b5 8a + +vlsseg5e16.v v8, (a0), a1 +# CHECK-INST: vlsseg5e16.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x54,0xb5,0x8a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 b5 8a + +vlsseg5e32.v v8, (a0), a1 +# CHECK-INST: vlsseg5e32.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x64,0xb5,0x8a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 b5 8a + +vlsseg5e64.v v8, (a0), a1 +# CHECK-INST: vlsseg5e64.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x74,0xb5,0x8a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 b5 8a + +vlsseg5e128.v v8, (a0), a1 +# CHECK-INST: vlsseg5e128.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x04,0xb5,0x9a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 b5 9a + +vlsseg5e256.v v8, (a0), a1 +# CHECK-INST: vlsseg5e256.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x54,0xb5,0x9a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 b5 9a + +vlsseg5e512.v v8, (a0), a1 +# CHECK-INST: vlsseg5e512.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x64,0xb5,0x9a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 b5 9a + +vlsseg5e1024.v v8, (a0), a1 +# CHECK-INST: vlsseg5e1024.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x74,0xb5,0x9a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 b5 9a + +vlsseg5e8.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg5e8.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x04,0xb5,0x88] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 b5 88 + +vlsseg5e16.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg5e16.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x54,0xb5,0x88] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 b5 88 + +vlsseg5e32.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg5e32.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x64,0xb5,0x88] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 b5 88 + +vlsseg5e64.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg5e64.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x74,0xb5,0x88] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 b5 88 + +vlsseg5e128.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg5e128.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x04,0xb5,0x98] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 b5 98 + +vlsseg5e256.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg5e256.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x54,0xb5,0x98] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 b5 98 + +vlsseg5e512.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg5e512.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x64,0xb5,0x98] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 b5 98 + +vlsseg5e1024.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg5e1024.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x74,0xb5,0x98] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 b5 98 + +vlsseg6e8.v v8, (a0), a1 +# CHECK-INST: vlsseg6e8.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x04,0xb5,0xaa] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 b5 aa + +vlsseg6e16.v v8, (a0), a1 +# CHECK-INST: vlsseg6e16.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x54,0xb5,0xaa] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 b5 aa + +vlsseg6e32.v v8, (a0), a1 +# CHECK-INST: vlsseg6e32.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x64,0xb5,0xaa] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 b5 aa + +vlsseg6e64.v v8, (a0), a1 +# CHECK-INST: vlsseg6e64.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x74,0xb5,0xaa] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 b5 aa + +vlsseg6e128.v v8, (a0), a1 +# CHECK-INST: vlsseg6e128.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x04,0xb5,0xba] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 b5 ba + +vlsseg6e256.v v8, (a0), a1 +# CHECK-INST: vlsseg6e256.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x54,0xb5,0xba] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 b5 ba + +vlsseg6e512.v v8, (a0), a1 +# CHECK-INST: vlsseg6e512.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x64,0xb5,0xba] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 b5 ba + +vlsseg6e1024.v v8, (a0), a1 +# CHECK-INST: vlsseg6e1024.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x74,0xb5,0xba] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 b5 ba + +vlsseg6e8.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg6e8.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x04,0xb5,0xa8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 b5 a8 + +vlsseg6e16.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg6e16.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x54,0xb5,0xa8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 b5 a8 + +vlsseg6e32.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg6e32.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x64,0xb5,0xa8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 b5 a8 + +vlsseg6e64.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg6e64.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x74,0xb5,0xa8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 b5 a8 + +vlsseg6e128.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg6e128.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x04,0xb5,0xb8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 b5 b8 + +vlsseg6e256.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg6e256.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x54,0xb5,0xb8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 b5 b8 + +vlsseg6e512.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg6e512.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x64,0xb5,0xb8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 b5 b8 + +vlsseg6e1024.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg6e1024.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x74,0xb5,0xb8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 b5 b8 + +vlsseg7e8.v v8, (a0), a1 +# CHECK-INST: vlsseg7e8.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x04,0xb5,0xca] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 b5 ca + +vlsseg7e16.v v8, (a0), a1 +# CHECK-INST: vlsseg7e16.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x54,0xb5,0xca] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 b5 ca + +vlsseg7e32.v v8, (a0), a1 +# CHECK-INST: vlsseg7e32.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x64,0xb5,0xca] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 b5 ca + +vlsseg7e64.v v8, (a0), a1 +# CHECK-INST: vlsseg7e64.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x74,0xb5,0xca] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 b5 ca + +vlsseg7e128.v v8, (a0), a1 +# CHECK-INST: vlsseg7e128.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x04,0xb5,0xda] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 b5 da + +vlsseg7e256.v v8, (a0), a1 +# CHECK-INST: vlsseg7e256.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x54,0xb5,0xda] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 b5 da + +vlsseg7e512.v v8, (a0), a1 +# CHECK-INST: vlsseg7e512.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x64,0xb5,0xda] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 b5 da + +vlsseg7e1024.v v8, (a0), a1 +# CHECK-INST: vlsseg7e1024.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x74,0xb5,0xda] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 b5 da + +vlsseg7e8.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg7e8.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x04,0xb5,0xc8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 b5 c8 + +vlsseg7e16.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg7e16.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x54,0xb5,0xc8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 b5 c8 + +vlsseg7e32.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg7e32.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x64,0xb5,0xc8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 b5 c8 + +vlsseg7e64.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg7e64.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x74,0xb5,0xc8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 b5 c8 + +vlsseg7e128.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg7e128.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x04,0xb5,0xd8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 b5 d8 + +vlsseg7e256.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg7e256.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x54,0xb5,0xd8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 b5 d8 + +vlsseg7e512.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg7e512.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x64,0xb5,0xd8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 b5 d8 + +vlsseg7e1024.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg7e1024.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x74,0xb5,0xd8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 b5 d8 + +vlsseg8e8.v v8, (a0), a1 +# CHECK-INST: vlsseg8e8.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x04,0xb5,0xea] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 b5 ea + +vlsseg8e16.v v8, (a0), a1 +# CHECK-INST: vlsseg8e16.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x54,0xb5,0xea] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 b5 ea + +vlsseg8e32.v v8, (a0), a1 +# CHECK-INST: vlsseg8e32.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x64,0xb5,0xea] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 b5 ea + +vlsseg8e64.v v8, (a0), a1 +# CHECK-INST: vlsseg8e64.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x74,0xb5,0xea] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 b5 ea + +vlsseg8e128.v v8, (a0), a1 +# CHECK-INST: vlsseg8e128.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x04,0xb5,0xfa] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 b5 fa + +vlsseg8e256.v v8, (a0), a1 +# CHECK-INST: vlsseg8e256.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x54,0xb5,0xfa] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 b5 fa + +vlsseg8e512.v v8, (a0), a1 +# CHECK-INST: vlsseg8e512.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x64,0xb5,0xfa] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 b5 fa + +vlsseg8e1024.v v8, (a0), a1 +# CHECK-INST: vlsseg8e1024.v v8, (a0), a1 +# CHECK-ENCODING: [0x07,0x74,0xb5,0xfa] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 b5 fa + +vlsseg8e8.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg8e8.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x04,0xb5,0xe8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 b5 e8 + +vlsseg8e16.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg8e16.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x54,0xb5,0xe8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 b5 e8 + +vlsseg8e32.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg8e32.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x64,0xb5,0xe8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 b5 e8 + +vlsseg8e64.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg8e64.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x74,0xb5,0xe8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 b5 e8 + +vlsseg8e128.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg8e128.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x04,0xb5,0xf8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 b5 f8 + +vlsseg8e256.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg8e256.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x54,0xb5,0xf8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 b5 f8 + +vlsseg8e512.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg8e512.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x64,0xb5,0xf8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 b5 f8 + +vlsseg8e1024.v v8, (a0), a1, v0.t +# CHECK-INST: vlsseg8e1024.v v8, (a0), a1, v0.t +# CHECK-ENCODING: [0x07,0x74,0xb5,0xf8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 b5 f8 + +vlxseg2ei8.v v8, (a0), v4 +# CHECK-INST: vlxseg2ei8.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x04,0x45,0x2e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 45 2e + +vlxseg2ei16.v v8, (a0), v4 +# CHECK-INST: vlxseg2ei16.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x54,0x45,0x2e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 45 2e + +vlxseg2ei32.v v8, (a0), v4 +# CHECK-INST: vlxseg2ei32.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x64,0x45,0x2e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 45 2e + +vlxseg2ei64.v v8, (a0), v4 +# CHECK-INST: vlxseg2ei64.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x74,0x45,0x2e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 45 2e + +vlxseg2ei128.v v8, (a0), v4 +# CHECK-INST: vlxseg2ei128.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x04,0x45,0x3e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 45 3e + +vlxseg2ei256.v v8, (a0), v4 +# CHECK-INST: vlxseg2ei256.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x54,0x45,0x3e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 45 3e + +vlxseg2ei512.v v8, (a0), v4 +# CHECK-INST: vlxseg2ei512.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x64,0x45,0x3e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 45 3e + +vlxseg2ei1024.v v8, (a0), v4 +# CHECK-INST: vlxseg2ei1024.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x74,0x45,0x3e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 45 3e + +vlxseg2ei8.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg2ei8.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x04,0x45,0x2c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 45 2c + +vlxseg2ei16.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg2ei16.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x54,0x45,0x2c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 45 2c + +vlxseg2ei32.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg2ei32.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x64,0x45,0x2c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 45 2c + +vlxseg2ei64.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg2ei64.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x74,0x45,0x2c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 45 2c + +vlxseg2ei128.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg2ei128.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x04,0x45,0x3c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 45 3c + +vlxseg2ei256.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg2ei256.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x54,0x45,0x3c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 45 3c + +vlxseg2ei512.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg2ei512.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x64,0x45,0x3c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 45 3c + +vlxseg2ei1024.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg2ei1024.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x74,0x45,0x3c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 45 3c + +vlxseg3ei8.v v8, (a0), v4 +# CHECK-INST: vlxseg3ei8.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x04,0x45,0x4e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 45 4e + +vlxseg3ei16.v v8, (a0), v4 +# CHECK-INST: vlxseg3ei16.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x54,0x45,0x4e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 45 4e + +vlxseg3ei32.v v8, (a0), v4 +# CHECK-INST: vlxseg3ei32.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x64,0x45,0x4e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 45 4e + +vlxseg3ei64.v v8, (a0), v4 +# CHECK-INST: vlxseg3ei64.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x74,0x45,0x4e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 45 4e + +vlxseg3ei128.v v8, (a0), v4 +# CHECK-INST: vlxseg3ei128.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x04,0x45,0x5e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 45 5e + +vlxseg3ei256.v v8, (a0), v4 +# CHECK-INST: vlxseg3ei256.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x54,0x45,0x5e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 45 5e + +vlxseg3ei512.v v8, (a0), v4 +# CHECK-INST: vlxseg3ei512.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x64,0x45,0x5e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 45 5e + +vlxseg3ei1024.v v8, (a0), v4 +# CHECK-INST: vlxseg3ei1024.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x74,0x45,0x5e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 45 5e + +vlxseg3ei8.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg3ei8.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x04,0x45,0x4c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 45 4c + +vlxseg3ei16.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg3ei16.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x54,0x45,0x4c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 45 4c + +vlxseg3ei32.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg3ei32.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x64,0x45,0x4c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 45 4c + +vlxseg3ei64.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg3ei64.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x74,0x45,0x4c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 45 4c + +vlxseg3ei128.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg3ei128.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x04,0x45,0x5c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 45 5c + +vlxseg3ei256.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg3ei256.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x54,0x45,0x5c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 45 5c + +vlxseg3ei512.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg3ei512.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x64,0x45,0x5c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 45 5c + +vlxseg3ei1024.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg3ei1024.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x74,0x45,0x5c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 45 5c + +vlxseg4ei8.v v8, (a0), v4 +# CHECK-INST: vlxseg4ei8.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x04,0x45,0x6e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 45 6e + +vlxseg4ei16.v v8, (a0), v4 +# CHECK-INST: vlxseg4ei16.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x54,0x45,0x6e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 45 6e + +vlxseg4ei32.v v8, (a0), v4 +# CHECK-INST: vlxseg4ei32.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x64,0x45,0x6e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 45 6e + +vlxseg4ei64.v v8, (a0), v4 +# CHECK-INST: vlxseg4ei64.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x74,0x45,0x6e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 45 6e + +vlxseg4ei128.v v8, (a0), v4 +# CHECK-INST: vlxseg4ei128.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x04,0x45,0x7e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 45 7e + +vlxseg4ei256.v v8, (a0), v4 +# CHECK-INST: vlxseg4ei256.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x54,0x45,0x7e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 45 7e + +vlxseg4ei512.v v8, (a0), v4 +# CHECK-INST: vlxseg4ei512.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x64,0x45,0x7e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 45 7e + +vlxseg4ei1024.v v8, (a0), v4 +# CHECK-INST: vlxseg4ei1024.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x74,0x45,0x7e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 45 7e + +vlxseg4ei8.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg4ei8.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x04,0x45,0x6c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 45 6c + +vlxseg4ei16.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg4ei16.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x54,0x45,0x6c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 45 6c + +vlxseg4ei32.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg4ei32.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x64,0x45,0x6c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 45 6c + +vlxseg4ei64.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg4ei64.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x74,0x45,0x6c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 45 6c + +vlxseg4ei128.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg4ei128.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x04,0x45,0x7c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 45 7c + +vlxseg4ei256.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg4ei256.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x54,0x45,0x7c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 45 7c + +vlxseg4ei512.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg4ei512.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x64,0x45,0x7c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 45 7c + +vlxseg4ei1024.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg4ei1024.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x74,0x45,0x7c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 45 7c + +vlxseg5ei8.v v8, (a0), v4 +# CHECK-INST: vlxseg5ei8.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x04,0x45,0x8e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 45 8e + +vlxseg5ei16.v v8, (a0), v4 +# CHECK-INST: vlxseg5ei16.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x54,0x45,0x8e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 45 8e + +vlxseg5ei32.v v8, (a0), v4 +# CHECK-INST: vlxseg5ei32.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x64,0x45,0x8e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 45 8e + +vlxseg5ei64.v v8, (a0), v4 +# CHECK-INST: vlxseg5ei64.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x74,0x45,0x8e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 45 8e + +vlxseg5ei128.v v8, (a0), v4 +# CHECK-INST: vlxseg5ei128.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x04,0x45,0x9e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 45 9e + +vlxseg5ei256.v v8, (a0), v4 +# CHECK-INST: vlxseg5ei256.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x54,0x45,0x9e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 45 9e + +vlxseg5ei512.v v8, (a0), v4 +# CHECK-INST: vlxseg5ei512.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x64,0x45,0x9e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 45 9e + +vlxseg5ei1024.v v8, (a0), v4 +# CHECK-INST: vlxseg5ei1024.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x74,0x45,0x9e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 45 9e + +vlxseg5ei8.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg5ei8.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x04,0x45,0x8c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 45 8c + +vlxseg5ei16.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg5ei16.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x54,0x45,0x8c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 45 8c + +vlxseg5ei32.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg5ei32.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x64,0x45,0x8c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 45 8c + +vlxseg5ei64.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg5ei64.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x74,0x45,0x8c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 45 8c + +vlxseg5ei128.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg5ei128.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x04,0x45,0x9c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 45 9c + +vlxseg5ei256.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg5ei256.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x54,0x45,0x9c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 45 9c + +vlxseg5ei512.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg5ei512.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x64,0x45,0x9c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 45 9c + +vlxseg5ei1024.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg5ei1024.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x74,0x45,0x9c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 45 9c + +vlxseg6ei8.v v8, (a0), v4 +# CHECK-INST: vlxseg6ei8.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x04,0x45,0xae] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 45 ae + +vlxseg6ei16.v v8, (a0), v4 +# CHECK-INST: vlxseg6ei16.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x54,0x45,0xae] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 45 ae + +vlxseg6ei32.v v8, (a0), v4 +# CHECK-INST: vlxseg6ei32.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x64,0x45,0xae] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 45 ae + +vlxseg6ei64.v v8, (a0), v4 +# CHECK-INST: vlxseg6ei64.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x74,0x45,0xae] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 45 ae + +vlxseg6ei128.v v8, (a0), v4 +# CHECK-INST: vlxseg6ei128.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x04,0x45,0xbe] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 45 be + +vlxseg6ei256.v v8, (a0), v4 +# CHECK-INST: vlxseg6ei256.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x54,0x45,0xbe] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 45 be + +vlxseg6ei512.v v8, (a0), v4 +# CHECK-INST: vlxseg6ei512.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x64,0x45,0xbe] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 45 be + +vlxseg6ei1024.v v8, (a0), v4 +# CHECK-INST: vlxseg6ei1024.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x74,0x45,0xbe] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 45 be + +vlxseg6ei8.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg6ei8.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x04,0x45,0xac] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 45 ac + +vlxseg6ei16.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg6ei16.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x54,0x45,0xac] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 45 ac + +vlxseg6ei32.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg6ei32.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x64,0x45,0xac] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 45 ac + +vlxseg6ei64.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg6ei64.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x74,0x45,0xac] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 45 ac + +vlxseg6ei128.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg6ei128.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x04,0x45,0xbc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 45 bc + +vlxseg6ei256.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg6ei256.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x54,0x45,0xbc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 45 bc + +vlxseg6ei512.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg6ei512.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x64,0x45,0xbc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 45 bc + +vlxseg6ei1024.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg6ei1024.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x74,0x45,0xbc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 45 bc + +vlxseg7ei8.v v8, (a0), v4 +# CHECK-INST: vlxseg7ei8.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x04,0x45,0xce] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 45 ce + +vlxseg7ei16.v v8, (a0), v4 +# CHECK-INST: vlxseg7ei16.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x54,0x45,0xce] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 45 ce + +vlxseg7ei32.v v8, (a0), v4 +# CHECK-INST: vlxseg7ei32.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x64,0x45,0xce] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 45 ce + +vlxseg7ei64.v v8, (a0), v4 +# CHECK-INST: vlxseg7ei64.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x74,0x45,0xce] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 45 ce + +vlxseg7ei128.v v8, (a0), v4 +# CHECK-INST: vlxseg7ei128.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x04,0x45,0xde] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 45 de + +vlxseg7ei256.v v8, (a0), v4 +# CHECK-INST: vlxseg7ei256.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x54,0x45,0xde] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 45 de + +vlxseg7ei512.v v8, (a0), v4 +# CHECK-INST: vlxseg7ei512.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x64,0x45,0xde] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 45 de + +vlxseg7ei1024.v v8, (a0), v4 +# CHECK-INST: vlxseg7ei1024.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x74,0x45,0xde] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 45 de + +vlxseg7ei8.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg7ei8.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x04,0x45,0xcc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 45 cc + +vlxseg7ei16.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg7ei16.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x54,0x45,0xcc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 45 cc + +vlxseg7ei32.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg7ei32.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x64,0x45,0xcc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 45 cc + +vlxseg7ei64.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg7ei64.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x74,0x45,0xcc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 45 cc + +vlxseg7ei128.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg7ei128.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x04,0x45,0xdc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 45 dc + +vlxseg7ei256.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg7ei256.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x54,0x45,0xdc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 45 dc + +vlxseg7ei512.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg7ei512.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x64,0x45,0xdc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 45 dc + +vlxseg7ei1024.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg7ei1024.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x74,0x45,0xdc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 45 dc + +vlxseg8ei8.v v8, (a0), v4 +# CHECK-INST: vlxseg8ei8.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x04,0x45,0xee] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 45 ee + +vlxseg8ei16.v v8, (a0), v4 +# CHECK-INST: vlxseg8ei16.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x54,0x45,0xee] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 45 ee + +vlxseg8ei32.v v8, (a0), v4 +# CHECK-INST: vlxseg8ei32.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x64,0x45,0xee] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 45 ee + +vlxseg8ei64.v v8, (a0), v4 +# CHECK-INST: vlxseg8ei64.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x74,0x45,0xee] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 45 ee + +vlxseg8ei128.v v8, (a0), v4 +# CHECK-INST: vlxseg8ei128.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x04,0x45,0xfe] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 45 fe + +vlxseg8ei256.v v8, (a0), v4 +# CHECK-INST: vlxseg8ei256.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x54,0x45,0xfe] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 45 fe + +vlxseg8ei512.v v8, (a0), v4 +# CHECK-INST: vlxseg8ei512.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x64,0x45,0xfe] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 45 fe + +vlxseg8ei1024.v v8, (a0), v4 +# CHECK-INST: vlxseg8ei1024.v v8, (a0), v4 +# CHECK-ENCODING: [0x07,0x74,0x45,0xfe] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 45 fe + +vlxseg8ei8.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg8ei8.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x04,0x45,0xec] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 45 ec + +vlxseg8ei16.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg8ei16.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x54,0x45,0xec] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 45 ec + +vlxseg8ei32.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg8ei32.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x64,0x45,0xec] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 45 ec + +vlxseg8ei64.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg8ei64.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x74,0x45,0xec] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 45 ec + +vlxseg8ei128.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg8ei128.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x04,0x45,0xfc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 45 fc + +vlxseg8ei256.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg8ei256.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x54,0x45,0xfc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 45 fc + +vlxseg8ei512.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg8ei512.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x64,0x45,0xfc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 45 fc + +vlxseg8ei1024.v v8, (a0), v4, v0.t +# CHECK-INST: vlxseg8ei1024.v v8, (a0), v4, v0.t +# CHECK-ENCODING: [0x07,0x74,0x45,0xfc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 45 fc + +vlseg2e8ff.v v8, (a0) +# CHECK-INST: vlseg2e8ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x04,0x05,0x23] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 23 + +vlseg2e16ff.v v8, (a0) +# CHECK-INST: vlseg2e16ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x54,0x05,0x23] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 23 + +vlseg2e32ff.v v8, (a0) +# CHECK-INST: vlseg2e32ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x64,0x05,0x23] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 23 + +vlseg2e64ff.v v8, (a0) +# CHECK-INST: vlseg2e64ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x74,0x05,0x23] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 23 + +vlseg2e128ff.v v8, (a0) +# CHECK-INST: vlseg2e128ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x04,0x05,0x33] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 33 + +vlseg2e256ff.v v8, (a0) +# CHECK-INST: vlseg2e256ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x54,0x05,0x33] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 33 + +vlseg2e512ff.v v8, (a0) +# CHECK-INST: vlseg2e512ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x64,0x05,0x33] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 33 + +vlseg2e1024ff.v v8, (a0) +# CHECK-INST: vlseg2e1024ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x74,0x05,0x33] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 33 + +vlseg2e8ff.v v8, (a0), v0.t +# CHECK-INST: vlseg2e8ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x04,0x05,0x21] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 21 + +vlseg2e16ff.v v8, (a0), v0.t +# CHECK-INST: vlseg2e16ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x54,0x05,0x21] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 21 + +vlseg2e32ff.v v8, (a0), v0.t +# CHECK-INST: vlseg2e32ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x64,0x05,0x21] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 21 + +vlseg2e64ff.v v8, (a0), v0.t +# CHECK-INST: vlseg2e64ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x74,0x05,0x21] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 21 + +vlseg2e128ff.v v8, (a0), v0.t +# CHECK-INST: vlseg2e128ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x04,0x05,0x31] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 31 + +vlseg2e256ff.v v8, (a0), v0.t +# CHECK-INST: vlseg2e256ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x54,0x05,0x31] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 31 + +vlseg2e512ff.v v8, (a0), v0.t +# CHECK-INST: vlseg2e512ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x64,0x05,0x31] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 31 + +vlseg2e1024ff.v v8, (a0), v0.t +# CHECK-INST: vlseg2e1024ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x74,0x05,0x31] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 31 + +vlseg3e8ff.v v8, (a0) +# CHECK-INST: vlseg3e8ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x04,0x05,0x43] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 43 + +vlseg3e16ff.v v8, (a0) +# CHECK-INST: vlseg3e16ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x54,0x05,0x43] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 43 + +vlseg3e32ff.v v8, (a0) +# CHECK-INST: vlseg3e32ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x64,0x05,0x43] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 43 + +vlseg3e64ff.v v8, (a0) +# CHECK-INST: vlseg3e64ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x74,0x05,0x43] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 43 + +vlseg3e128ff.v v8, (a0) +# CHECK-INST: vlseg3e128ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x04,0x05,0x53] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 53 + +vlseg3e256ff.v v8, (a0) +# CHECK-INST: vlseg3e256ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x54,0x05,0x53] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 53 + +vlseg3e512ff.v v8, (a0) +# CHECK-INST: vlseg3e512ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x64,0x05,0x53] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 53 + +vlseg3e1024ff.v v8, (a0) +# CHECK-INST: vlseg3e1024ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x74,0x05,0x53] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 53 + +vlseg3e8ff.v v8, (a0), v0.t +# CHECK-INST: vlseg3e8ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x04,0x05,0x41] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 41 + +vlseg3e16ff.v v8, (a0), v0.t +# CHECK-INST: vlseg3e16ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x54,0x05,0x41] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 41 + +vlseg3e32ff.v v8, (a0), v0.t +# CHECK-INST: vlseg3e32ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x64,0x05,0x41] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 41 + +vlseg3e64ff.v v8, (a0), v0.t +# CHECK-INST: vlseg3e64ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x74,0x05,0x41] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 41 + +vlseg3e128ff.v v8, (a0), v0.t +# CHECK-INST: vlseg3e128ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x04,0x05,0x51] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 51 + +vlseg3e256ff.v v8, (a0), v0.t +# CHECK-INST: vlseg3e256ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x54,0x05,0x51] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 51 + +vlseg3e512ff.v v8, (a0), v0.t +# CHECK-INST: vlseg3e512ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x64,0x05,0x51] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 51 + +vlseg3e1024ff.v v8, (a0), v0.t +# CHECK-INST: vlseg3e1024ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x74,0x05,0x51] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 51 + +vlseg4e8ff.v v8, (a0) +# CHECK-INST: vlseg4e8ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x04,0x05,0x63] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 63 + +vlseg4e16ff.v v8, (a0) +# CHECK-INST: vlseg4e16ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x54,0x05,0x63] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 63 + +vlseg4e32ff.v v8, (a0) +# CHECK-INST: vlseg4e32ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x64,0x05,0x63] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 63 + +vlseg4e64ff.v v8, (a0) +# CHECK-INST: vlseg4e64ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x74,0x05,0x63] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 63 + +vlseg4e128ff.v v8, (a0) +# CHECK-INST: vlseg4e128ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x04,0x05,0x73] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 73 + +vlseg4e256ff.v v8, (a0) +# CHECK-INST: vlseg4e256ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x54,0x05,0x73] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 73 + +vlseg4e512ff.v v8, (a0) +# CHECK-INST: vlseg4e512ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x64,0x05,0x73] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 73 + +vlseg4e1024ff.v v8, (a0) +# CHECK-INST: vlseg4e1024ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x74,0x05,0x73] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 73 + +vlseg4e8ff.v v8, (a0), v0.t +# CHECK-INST: vlseg4e8ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x04,0x05,0x61] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 61 + +vlseg4e16ff.v v8, (a0), v0.t +# CHECK-INST: vlseg4e16ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x54,0x05,0x61] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 61 + +vlseg4e32ff.v v8, (a0), v0.t +# CHECK-INST: vlseg4e32ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x64,0x05,0x61] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 61 + +vlseg4e64ff.v v8, (a0), v0.t +# CHECK-INST: vlseg4e64ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x74,0x05,0x61] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 61 + +vlseg4e128ff.v v8, (a0), v0.t +# CHECK-INST: vlseg4e128ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x04,0x05,0x71] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 71 + +vlseg4e256ff.v v8, (a0), v0.t +# CHECK-INST: vlseg4e256ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x54,0x05,0x71] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 71 + +vlseg4e512ff.v v8, (a0), v0.t +# CHECK-INST: vlseg4e512ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x64,0x05,0x71] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 71 + +vlseg4e1024ff.v v8, (a0), v0.t +# CHECK-INST: vlseg4e1024ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x74,0x05,0x71] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 71 + +vlseg5e8ff.v v8, (a0) +# CHECK-INST: vlseg5e8ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x04,0x05,0x83] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 83 + +vlseg5e16ff.v v8, (a0) +# CHECK-INST: vlseg5e16ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x54,0x05,0x83] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 83 + +vlseg5e32ff.v v8, (a0) +# CHECK-INST: vlseg5e32ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x64,0x05,0x83] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 83 + +vlseg5e64ff.v v8, (a0) +# CHECK-INST: vlseg5e64ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x74,0x05,0x83] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 83 + +vlseg5e128ff.v v8, (a0) +# CHECK-INST: vlseg5e128ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x04,0x05,0x93] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 93 + +vlseg5e256ff.v v8, (a0) +# CHECK-INST: vlseg5e256ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x54,0x05,0x93] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 93 + +vlseg5e512ff.v v8, (a0) +# CHECK-INST: vlseg5e512ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x64,0x05,0x93] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 93 + +vlseg5e1024ff.v v8, (a0) +# CHECK-INST: vlseg5e1024ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x74,0x05,0x93] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 93 + +vlseg5e8ff.v v8, (a0), v0.t +# CHECK-INST: vlseg5e8ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x04,0x05,0x81] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 81 + +vlseg5e16ff.v v8, (a0), v0.t +# CHECK-INST: vlseg5e16ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x54,0x05,0x81] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 81 + +vlseg5e32ff.v v8, (a0), v0.t +# CHECK-INST: vlseg5e32ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x64,0x05,0x81] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 81 + +vlseg5e64ff.v v8, (a0), v0.t +# CHECK-INST: vlseg5e64ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x74,0x05,0x81] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 81 + +vlseg5e128ff.v v8, (a0), v0.t +# CHECK-INST: vlseg5e128ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x04,0x05,0x91] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 91 + +vlseg5e256ff.v v8, (a0), v0.t +# CHECK-INST: vlseg5e256ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x54,0x05,0x91] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 91 + +vlseg5e512ff.v v8, (a0), v0.t +# CHECK-INST: vlseg5e512ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x64,0x05,0x91] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 91 + +vlseg5e1024ff.v v8, (a0), v0.t +# CHECK-INST: vlseg5e1024ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x74,0x05,0x91] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 91 + +vlseg6e8ff.v v8, (a0) +# CHECK-INST: vlseg6e8ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x04,0x05,0xa3] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 a3 + +vlseg6e16ff.v v8, (a0) +# CHECK-INST: vlseg6e16ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x54,0x05,0xa3] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 a3 + +vlseg6e32ff.v v8, (a0) +# CHECK-INST: vlseg6e32ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x64,0x05,0xa3] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 a3 + +vlseg6e64ff.v v8, (a0) +# CHECK-INST: vlseg6e64ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x74,0x05,0xa3] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 a3 + +vlseg6e128ff.v v8, (a0) +# CHECK-INST: vlseg6e128ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x04,0x05,0xb3] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 b3 + +vlseg6e256ff.v v8, (a0) +# CHECK-INST: vlseg6e256ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x54,0x05,0xb3] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 b3 + +vlseg6e512ff.v v8, (a0) +# CHECK-INST: vlseg6e512ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x64,0x05,0xb3] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 b3 + +vlseg6e1024ff.v v8, (a0) +# CHECK-INST: vlseg6e1024ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x74,0x05,0xb3] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 b3 + +vlseg6e8ff.v v8, (a0), v0.t +# CHECK-INST: vlseg6e8ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x04,0x05,0xa1] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 a1 + +vlseg6e16ff.v v8, (a0), v0.t +# CHECK-INST: vlseg6e16ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x54,0x05,0xa1] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 a1 + +vlseg6e32ff.v v8, (a0), v0.t +# CHECK-INST: vlseg6e32ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x64,0x05,0xa1] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 a1 + +vlseg6e64ff.v v8, (a0), v0.t +# CHECK-INST: vlseg6e64ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x74,0x05,0xa1] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 a1 + +vlseg6e128ff.v v8, (a0), v0.t +# CHECK-INST: vlseg6e128ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x04,0x05,0xb1] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 b1 + +vlseg6e256ff.v v8, (a0), v0.t +# CHECK-INST: vlseg6e256ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x54,0x05,0xb1] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 b1 + +vlseg6e512ff.v v8, (a0), v0.t +# CHECK-INST: vlseg6e512ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x64,0x05,0xb1] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 b1 + +vlseg6e1024ff.v v8, (a0), v0.t +# CHECK-INST: vlseg6e1024ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x74,0x05,0xb1] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 b1 + +vlseg7e8ff.v v8, (a0) +# CHECK-INST: vlseg7e8ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x04,0x05,0xc3] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 c3 + +vlseg7e16ff.v v8, (a0) +# CHECK-INST: vlseg7e16ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x54,0x05,0xc3] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 c3 + +vlseg7e32ff.v v8, (a0) +# CHECK-INST: vlseg7e32ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x64,0x05,0xc3] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 c3 + +vlseg7e64ff.v v8, (a0) +# CHECK-INST: vlseg7e64ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x74,0x05,0xc3] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 c3 + +vlseg7e128ff.v v8, (a0) +# CHECK-INST: vlseg7e128ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x04,0x05,0xd3] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 d3 + +vlseg7e256ff.v v8, (a0) +# CHECK-INST: vlseg7e256ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x54,0x05,0xd3] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 d3 + +vlseg7e512ff.v v8, (a0) +# CHECK-INST: vlseg7e512ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x64,0x05,0xd3] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 d3 + +vlseg7e1024ff.v v8, (a0) +# CHECK-INST: vlseg7e1024ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x74,0x05,0xd3] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 d3 + +vlseg7e8ff.v v8, (a0), v0.t +# CHECK-INST: vlseg7e8ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x04,0x05,0xc1] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 c1 + +vlseg7e16ff.v v8, (a0), v0.t +# CHECK-INST: vlseg7e16ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x54,0x05,0xc1] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 c1 + +vlseg7e32ff.v v8, (a0), v0.t +# CHECK-INST: vlseg7e32ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x64,0x05,0xc1] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 c1 + +vlseg7e64ff.v v8, (a0), v0.t +# CHECK-INST: vlseg7e64ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x74,0x05,0xc1] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 c1 + +vlseg7e128ff.v v8, (a0), v0.t +# CHECK-INST: vlseg7e128ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x04,0x05,0xd1] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 d1 + +vlseg7e256ff.v v8, (a0), v0.t +# CHECK-INST: vlseg7e256ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x54,0x05,0xd1] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 d1 + +vlseg7e512ff.v v8, (a0), v0.t +# CHECK-INST: vlseg7e512ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x64,0x05,0xd1] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 d1 + +vlseg7e1024ff.v v8, (a0), v0.t +# CHECK-INST: vlseg7e1024ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x74,0x05,0xd1] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 d1 + +vlseg8e8ff.v v8, (a0) +# CHECK-INST: vlseg8e8ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x04,0x05,0xe3] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 e3 + +vlseg8e16ff.v v8, (a0) +# CHECK-INST: vlseg8e16ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x54,0x05,0xe3] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 e3 + +vlseg8e32ff.v v8, (a0) +# CHECK-INST: vlseg8e32ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x64,0x05,0xe3] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 e3 + +vlseg8e64ff.v v8, (a0) +# CHECK-INST: vlseg8e64ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x74,0x05,0xe3] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 e3 + +vlseg8e128ff.v v8, (a0) +# CHECK-INST: vlseg8e128ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x04,0x05,0xf3] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 f3 + +vlseg8e256ff.v v8, (a0) +# CHECK-INST: vlseg8e256ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x54,0x05,0xf3] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 f3 + +vlseg8e512ff.v v8, (a0) +# CHECK-INST: vlseg8e512ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x64,0x05,0xf3] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 f3 + +vlseg8e1024ff.v v8, (a0) +# CHECK-INST: vlseg8e1024ff.v v8, (a0) +# CHECK-ENCODING: [0x07,0x74,0x05,0xf3] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 f3 + +vlseg8e8ff.v v8, (a0), v0.t +# CHECK-INST: vlseg8e8ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x04,0x05,0xe1] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 e1 + +vlseg8e16ff.v v8, (a0), v0.t +# CHECK-INST: vlseg8e16ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x54,0x05,0xe1] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 e1 + +vlseg8e32ff.v v8, (a0), v0.t +# CHECK-INST: vlseg8e32ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x64,0x05,0xe1] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 e1 + +vlseg8e64ff.v v8, (a0), v0.t +# CHECK-INST: vlseg8e64ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x74,0x05,0xe1] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 e1 + +vlseg8e128ff.v v8, (a0), v0.t +# CHECK-INST: vlseg8e128ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x04,0x05,0xf1] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 04 05 f1 + +vlseg8e256ff.v v8, (a0), v0.t +# CHECK-INST: vlseg8e256ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x54,0x05,0xf1] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 54 05 f1 + +vlseg8e512ff.v v8, (a0), v0.t +# CHECK-INST: vlseg8e512ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x64,0x05,0xf1] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 64 05 f1 + +vlseg8e1024ff.v v8, (a0), v0.t +# CHECK-INST: vlseg8e1024ff.v v8, (a0), v0.t +# CHECK-ENCODING: [0x07,0x74,0x05,0xf1] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 07 74 05 f1 + +vsseg2e8.v v24, (a0) +# CHECK-INST: vsseg2e8.v v24, (a0) +# CHECK-ENCODING: [0x27,0x0c,0x05,0x22] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 05 22 + +vsseg2e16.v v24, (a0) +# CHECK-INST: vsseg2e16.v v24, (a0) +# CHECK-ENCODING: [0x27,0x5c,0x05,0x22] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 05 22 + +vsseg2e32.v v24, (a0) +# CHECK-INST: vsseg2e32.v v24, (a0) +# CHECK-ENCODING: [0x27,0x6c,0x05,0x22] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 05 22 + +vsseg2e64.v v24, (a0) +# CHECK-INST: vsseg2e64.v v24, (a0) +# CHECK-ENCODING: [0x27,0x7c,0x05,0x22] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 05 22 + +vsseg2e128.v v24, (a0) +# CHECK-INST: vsseg2e128.v v24, (a0) +# CHECK-ENCODING: [0x27,0x0c,0x05,0x32] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 05 32 + +vsseg2e256.v v24, (a0) +# CHECK-INST: vsseg2e256.v v24, (a0) +# CHECK-ENCODING: [0x27,0x5c,0x05,0x32] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 05 32 + +vsseg2e512.v v24, (a0) +# CHECK-INST: vsseg2e512.v v24, (a0) +# CHECK-ENCODING: [0x27,0x6c,0x05,0x32] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 05 32 + +vsseg2e1024.v v24, (a0) +# CHECK-INST: vsseg2e1024.v v24, (a0) +# CHECK-ENCODING: [0x27,0x7c,0x05,0x32] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 05 32 + +vsseg2e8.v v24, (a0), v0.t +# CHECK-INST: vsseg2e8.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x0c,0x05,0x20] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 05 20 + +vsseg2e16.v v24, (a0), v0.t +# CHECK-INST: vsseg2e16.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x5c,0x05,0x20] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 05 20 + +vsseg2e32.v v24, (a0), v0.t +# CHECK-INST: vsseg2e32.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x6c,0x05,0x20] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 05 20 + +vsseg2e64.v v24, (a0), v0.t +# CHECK-INST: vsseg2e64.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x7c,0x05,0x20] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 05 20 + +vsseg2e128.v v24, (a0), v0.t +# CHECK-INST: vsseg2e128.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x0c,0x05,0x30] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 05 30 + +vsseg2e256.v v24, (a0), v0.t +# CHECK-INST: vsseg2e256.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x5c,0x05,0x30] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 05 30 + +vsseg2e512.v v24, (a0), v0.t +# CHECK-INST: vsseg2e512.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x6c,0x05,0x30] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 05 30 + +vsseg2e1024.v v24, (a0), v0.t +# CHECK-INST: vsseg2e1024.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x7c,0x05,0x30] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 05 30 + +vsseg3e8.v v24, (a0) +# CHECK-INST: vsseg3e8.v v24, (a0) +# CHECK-ENCODING: [0x27,0x0c,0x05,0x42] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 05 42 + +vsseg3e16.v v24, (a0) +# CHECK-INST: vsseg3e16.v v24, (a0) +# CHECK-ENCODING: [0x27,0x5c,0x05,0x42] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 05 42 + +vsseg3e32.v v24, (a0) +# CHECK-INST: vsseg3e32.v v24, (a0) +# CHECK-ENCODING: [0x27,0x6c,0x05,0x42] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 05 42 + +vsseg3e64.v v24, (a0) +# CHECK-INST: vsseg3e64.v v24, (a0) +# CHECK-ENCODING: [0x27,0x7c,0x05,0x42] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 05 42 + +vsseg3e128.v v24, (a0) +# CHECK-INST: vsseg3e128.v v24, (a0) +# CHECK-ENCODING: [0x27,0x0c,0x05,0x52] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 05 52 + +vsseg3e256.v v24, (a0) +# CHECK-INST: vsseg3e256.v v24, (a0) +# CHECK-ENCODING: [0x27,0x5c,0x05,0x52] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 05 52 + +vsseg3e512.v v24, (a0) +# CHECK-INST: vsseg3e512.v v24, (a0) +# CHECK-ENCODING: [0x27,0x6c,0x05,0x52] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 05 52 + +vsseg3e1024.v v24, (a0) +# CHECK-INST: vsseg3e1024.v v24, (a0) +# CHECK-ENCODING: [0x27,0x7c,0x05,0x52] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 05 52 + +vsseg3e8.v v24, (a0), v0.t +# CHECK-INST: vsseg3e8.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x0c,0x05,0x40] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 05 40 + +vsseg3e16.v v24, (a0), v0.t +# CHECK-INST: vsseg3e16.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x5c,0x05,0x40] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 05 40 + +vsseg3e32.v v24, (a0), v0.t +# CHECK-INST: vsseg3e32.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x6c,0x05,0x40] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 05 40 + +vsseg3e64.v v24, (a0), v0.t +# CHECK-INST: vsseg3e64.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x7c,0x05,0x40] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 05 40 + +vsseg3e128.v v24, (a0), v0.t +# CHECK-INST: vsseg3e128.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x0c,0x05,0x50] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 05 50 + +vsseg3e256.v v24, (a0), v0.t +# CHECK-INST: vsseg3e256.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x5c,0x05,0x50] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 05 50 + +vsseg3e512.v v24, (a0), v0.t +# CHECK-INST: vsseg3e512.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x6c,0x05,0x50] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 05 50 + +vsseg3e1024.v v24, (a0), v0.t +# CHECK-INST: vsseg3e1024.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x7c,0x05,0x50] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 05 50 + +vsseg4e8.v v24, (a0) +# CHECK-INST: vsseg4e8.v v24, (a0) +# CHECK-ENCODING: [0x27,0x0c,0x05,0x62] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 05 62 + +vsseg4e16.v v24, (a0) +# CHECK-INST: vsseg4e16.v v24, (a0) +# CHECK-ENCODING: [0x27,0x5c,0x05,0x62] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 05 62 + +vsseg4e32.v v24, (a0) +# CHECK-INST: vsseg4e32.v v24, (a0) +# CHECK-ENCODING: [0x27,0x6c,0x05,0x62] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 05 62 + +vsseg4e64.v v24, (a0) +# CHECK-INST: vsseg4e64.v v24, (a0) +# CHECK-ENCODING: [0x27,0x7c,0x05,0x62] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 05 62 + +vsseg4e128.v v24, (a0) +# CHECK-INST: vsseg4e128.v v24, (a0) +# CHECK-ENCODING: [0x27,0x0c,0x05,0x72] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 05 72 + +vsseg4e256.v v24, (a0) +# CHECK-INST: vsseg4e256.v v24, (a0) +# CHECK-ENCODING: [0x27,0x5c,0x05,0x72] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 05 72 + +vsseg4e512.v v24, (a0) +# CHECK-INST: vsseg4e512.v v24, (a0) +# CHECK-ENCODING: [0x27,0x6c,0x05,0x72] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 05 72 + +vsseg4e1024.v v24, (a0) +# CHECK-INST: vsseg4e1024.v v24, (a0) +# CHECK-ENCODING: [0x27,0x7c,0x05,0x72] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 05 72 + +vsseg4e8.v v24, (a0), v0.t +# CHECK-INST: vsseg4e8.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x0c,0x05,0x60] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 05 60 + +vsseg4e16.v v24, (a0), v0.t +# CHECK-INST: vsseg4e16.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x5c,0x05,0x60] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 05 60 + +vsseg4e32.v v24, (a0), v0.t +# CHECK-INST: vsseg4e32.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x6c,0x05,0x60] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 05 60 + +vsseg4e64.v v24, (a0), v0.t +# CHECK-INST: vsseg4e64.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x7c,0x05,0x60] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 05 60 + +vsseg4e128.v v24, (a0), v0.t +# CHECK-INST: vsseg4e128.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x0c,0x05,0x70] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 05 70 + +vsseg4e256.v v24, (a0), v0.t +# CHECK-INST: vsseg4e256.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x5c,0x05,0x70] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 05 70 + +vsseg4e512.v v24, (a0), v0.t +# CHECK-INST: vsseg4e512.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x6c,0x05,0x70] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 05 70 + +vsseg4e1024.v v24, (a0), v0.t +# CHECK-INST: vsseg4e1024.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x7c,0x05,0x70] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 05 70 + +vsseg5e8.v v24, (a0) +# CHECK-INST: vsseg5e8.v v24, (a0) +# CHECK-ENCODING: [0x27,0x0c,0x05,0x82] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 05 82 + +vsseg5e16.v v24, (a0) +# CHECK-INST: vsseg5e16.v v24, (a0) +# CHECK-ENCODING: [0x27,0x5c,0x05,0x82] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 05 82 + +vsseg5e32.v v24, (a0) +# CHECK-INST: vsseg5e32.v v24, (a0) +# CHECK-ENCODING: [0x27,0x6c,0x05,0x82] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 05 82 + +vsseg5e64.v v24, (a0) +# CHECK-INST: vsseg5e64.v v24, (a0) +# CHECK-ENCODING: [0x27,0x7c,0x05,0x82] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 05 82 + +vsseg5e128.v v24, (a0) +# CHECK-INST: vsseg5e128.v v24, (a0) +# CHECK-ENCODING: [0x27,0x0c,0x05,0x92] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 05 92 + +vsseg5e256.v v24, (a0) +# CHECK-INST: vsseg5e256.v v24, (a0) +# CHECK-ENCODING: [0x27,0x5c,0x05,0x92] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 05 92 + +vsseg5e512.v v24, (a0) +# CHECK-INST: vsseg5e512.v v24, (a0) +# CHECK-ENCODING: [0x27,0x6c,0x05,0x92] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 05 92 + +vsseg5e1024.v v24, (a0) +# CHECK-INST: vsseg5e1024.v v24, (a0) +# CHECK-ENCODING: [0x27,0x7c,0x05,0x92] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 05 92 + +vsseg5e8.v v24, (a0), v0.t +# CHECK-INST: vsseg5e8.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x0c,0x05,0x80] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 05 80 + +vsseg5e16.v v24, (a0), v0.t +# CHECK-INST: vsseg5e16.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x5c,0x05,0x80] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 05 80 + +vsseg5e32.v v24, (a0), v0.t +# CHECK-INST: vsseg5e32.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x6c,0x05,0x80] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 05 80 + +vsseg5e64.v v24, (a0), v0.t +# CHECK-INST: vsseg5e64.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x7c,0x05,0x80] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 05 80 + +vsseg5e128.v v24, (a0), v0.t +# CHECK-INST: vsseg5e128.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x0c,0x05,0x90] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 05 90 + +vsseg5e256.v v24, (a0), v0.t +# CHECK-INST: vsseg5e256.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x5c,0x05,0x90] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 05 90 + +vsseg5e512.v v24, (a0), v0.t +# CHECK-INST: vsseg5e512.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x6c,0x05,0x90] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 05 90 + +vsseg5e1024.v v24, (a0), v0.t +# CHECK-INST: vsseg5e1024.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x7c,0x05,0x90] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 05 90 + +vsseg6e8.v v24, (a0) +# CHECK-INST: vsseg6e8.v v24, (a0) +# CHECK-ENCODING: [0x27,0x0c,0x05,0xa2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 05 a2 + +vsseg6e16.v v24, (a0) +# CHECK-INST: vsseg6e16.v v24, (a0) +# CHECK-ENCODING: [0x27,0x5c,0x05,0xa2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 05 a2 + +vsseg6e32.v v24, (a0) +# CHECK-INST: vsseg6e32.v v24, (a0) +# CHECK-ENCODING: [0x27,0x6c,0x05,0xa2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 05 a2 + +vsseg6e64.v v24, (a0) +# CHECK-INST: vsseg6e64.v v24, (a0) +# CHECK-ENCODING: [0x27,0x7c,0x05,0xa2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 05 a2 + +vsseg6e128.v v24, (a0) +# CHECK-INST: vsseg6e128.v v24, (a0) +# CHECK-ENCODING: [0x27,0x0c,0x05,0xb2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 05 b2 + +vsseg6e256.v v24, (a0) +# CHECK-INST: vsseg6e256.v v24, (a0) +# CHECK-ENCODING: [0x27,0x5c,0x05,0xb2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 05 b2 + +vsseg6e512.v v24, (a0) +# CHECK-INST: vsseg6e512.v v24, (a0) +# CHECK-ENCODING: [0x27,0x6c,0x05,0xb2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 05 b2 + +vsseg6e1024.v v24, (a0) +# CHECK-INST: vsseg6e1024.v v24, (a0) +# CHECK-ENCODING: [0x27,0x7c,0x05,0xb2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 05 b2 + +vsseg6e8.v v24, (a0), v0.t +# CHECK-INST: vsseg6e8.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x0c,0x05,0xa0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 05 a0 + +vsseg6e16.v v24, (a0), v0.t +# CHECK-INST: vsseg6e16.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x5c,0x05,0xa0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 05 a0 + +vsseg6e32.v v24, (a0), v0.t +# CHECK-INST: vsseg6e32.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x6c,0x05,0xa0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 05 a0 + +vsseg6e64.v v24, (a0), v0.t +# CHECK-INST: vsseg6e64.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x7c,0x05,0xa0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 05 a0 + +vsseg6e128.v v24, (a0), v0.t +# CHECK-INST: vsseg6e128.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x0c,0x05,0xb0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 05 b0 + +vsseg6e256.v v24, (a0), v0.t +# CHECK-INST: vsseg6e256.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x5c,0x05,0xb0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 05 b0 + +vsseg6e512.v v24, (a0), v0.t +# CHECK-INST: vsseg6e512.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x6c,0x05,0xb0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 05 b0 + +vsseg6e1024.v v24, (a0), v0.t +# CHECK-INST: vsseg6e1024.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x7c,0x05,0xb0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 05 b0 + +vsseg7e8.v v24, (a0) +# CHECK-INST: vsseg7e8.v v24, (a0) +# CHECK-ENCODING: [0x27,0x0c,0x05,0xc2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 05 c2 + +vsseg7e16.v v24, (a0) +# CHECK-INST: vsseg7e16.v v24, (a0) +# CHECK-ENCODING: [0x27,0x5c,0x05,0xc2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 05 c2 + +vsseg7e32.v v24, (a0) +# CHECK-INST: vsseg7e32.v v24, (a0) +# CHECK-ENCODING: [0x27,0x6c,0x05,0xc2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 05 c2 + +vsseg7e64.v v24, (a0) +# CHECK-INST: vsseg7e64.v v24, (a0) +# CHECK-ENCODING: [0x27,0x7c,0x05,0xc2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 05 c2 + +vsseg7e128.v v24, (a0) +# CHECK-INST: vsseg7e128.v v24, (a0) +# CHECK-ENCODING: [0x27,0x0c,0x05,0xd2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 05 d2 + +vsseg7e256.v v24, (a0) +# CHECK-INST: vsseg7e256.v v24, (a0) +# CHECK-ENCODING: [0x27,0x5c,0x05,0xd2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 05 d2 + +vsseg7e512.v v24, (a0) +# CHECK-INST: vsseg7e512.v v24, (a0) +# CHECK-ENCODING: [0x27,0x6c,0x05,0xd2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 05 d2 + +vsseg7e1024.v v24, (a0) +# CHECK-INST: vsseg7e1024.v v24, (a0) +# CHECK-ENCODING: [0x27,0x7c,0x05,0xd2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 05 d2 + +vsseg7e8.v v24, (a0), v0.t +# CHECK-INST: vsseg7e8.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x0c,0x05,0xc0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 05 c0 + +vsseg7e16.v v24, (a0), v0.t +# CHECK-INST: vsseg7e16.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x5c,0x05,0xc0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 05 c0 + +vsseg7e32.v v24, (a0), v0.t +# CHECK-INST: vsseg7e32.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x6c,0x05,0xc0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 05 c0 + +vsseg7e64.v v24, (a0), v0.t +# CHECK-INST: vsseg7e64.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x7c,0x05,0xc0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 05 c0 + +vsseg7e128.v v24, (a0), v0.t +# CHECK-INST: vsseg7e128.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x0c,0x05,0xd0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 05 d0 + +vsseg7e256.v v24, (a0), v0.t +# CHECK-INST: vsseg7e256.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x5c,0x05,0xd0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 05 d0 + +vsseg7e512.v v24, (a0), v0.t +# CHECK-INST: vsseg7e512.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x6c,0x05,0xd0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 05 d0 + +vsseg7e1024.v v24, (a0), v0.t +# CHECK-INST: vsseg7e1024.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x7c,0x05,0xd0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 05 d0 + +vsseg8e8.v v24, (a0) +# CHECK-INST: vsseg8e8.v v24, (a0) +# CHECK-ENCODING: [0x27,0x0c,0x05,0xe2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 05 e2 + +vsseg8e16.v v24, (a0) +# CHECK-INST: vsseg8e16.v v24, (a0) +# CHECK-ENCODING: [0x27,0x5c,0x05,0xe2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 05 e2 + +vsseg8e32.v v24, (a0) +# CHECK-INST: vsseg8e32.v v24, (a0) +# CHECK-ENCODING: [0x27,0x6c,0x05,0xe2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 05 e2 + +vsseg8e64.v v24, (a0) +# CHECK-INST: vsseg8e64.v v24, (a0) +# CHECK-ENCODING: [0x27,0x7c,0x05,0xe2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 05 e2 + +vsseg8e128.v v24, (a0) +# CHECK-INST: vsseg8e128.v v24, (a0) +# CHECK-ENCODING: [0x27,0x0c,0x05,0xf2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 05 f2 + +vsseg8e256.v v24, (a0) +# CHECK-INST: vsseg8e256.v v24, (a0) +# CHECK-ENCODING: [0x27,0x5c,0x05,0xf2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 05 f2 + +vsseg8e512.v v24, (a0) +# CHECK-INST: vsseg8e512.v v24, (a0) +# CHECK-ENCODING: [0x27,0x6c,0x05,0xf2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 05 f2 + +vsseg8e1024.v v24, (a0) +# CHECK-INST: vsseg8e1024.v v24, (a0) +# CHECK-ENCODING: [0x27,0x7c,0x05,0xf2] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 05 f2 + +vsseg8e8.v v24, (a0), v0.t +# CHECK-INST: vsseg8e8.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x0c,0x05,0xe0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 05 e0 + +vsseg8e16.v v24, (a0), v0.t +# CHECK-INST: vsseg8e16.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x5c,0x05,0xe0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 05 e0 + +vsseg8e32.v v24, (a0), v0.t +# CHECK-INST: vsseg8e32.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x6c,0x05,0xe0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 05 e0 + +vsseg8e64.v v24, (a0), v0.t +# CHECK-INST: vsseg8e64.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x7c,0x05,0xe0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 05 e0 + +vsseg8e128.v v24, (a0), v0.t +# CHECK-INST: vsseg8e128.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x0c,0x05,0xf0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 05 f0 + +vsseg8e256.v v24, (a0), v0.t +# CHECK-INST: vsseg8e256.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x5c,0x05,0xf0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 05 f0 + +vsseg8e512.v v24, (a0), v0.t +# CHECK-INST: vsseg8e512.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x6c,0x05,0xf0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 05 f0 + +vsseg8e1024.v v24, (a0), v0.t +# CHECK-INST: vsseg8e1024.v v24, (a0), v0.t +# CHECK-ENCODING: [0x27,0x7c,0x05,0xf0] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 05 f0 + +vssseg2e8.v v24, (a0), a1 +# CHECK-INST: vssseg2e8.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x0c,0xb5,0x2a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c b5 2a + +vssseg2e16.v v24, (a0), a1 +# CHECK-INST: vssseg2e16.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x5c,0xb5,0x2a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c b5 2a + +vssseg2e32.v v24, (a0), a1 +# CHECK-INST: vssseg2e32.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x6c,0xb5,0x2a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c b5 2a + +vssseg2e64.v v24, (a0), a1 +# CHECK-INST: vssseg2e64.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x7c,0xb5,0x2a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c b5 2a + +vssseg2e128.v v24, (a0), a1 +# CHECK-INST: vssseg2e128.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x0c,0xb5,0x3a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c b5 3a + +vssseg2e256.v v24, (a0), a1 +# CHECK-INST: vssseg2e256.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x5c,0xb5,0x3a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c b5 3a + +vssseg2e512.v v24, (a0), a1 +# CHECK-INST: vssseg2e512.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x6c,0xb5,0x3a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c b5 3a + +vssseg2e1024.v v24, (a0), a1 +# CHECK-INST: vssseg2e1024.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x7c,0xb5,0x3a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c b5 3a + +vssseg2e8.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg2e8.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x0c,0xb5,0x28] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c b5 28 + +vssseg2e16.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg2e16.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x5c,0xb5,0x28] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c b5 28 + +vssseg2e32.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg2e32.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x6c,0xb5,0x28] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c b5 28 + +vssseg2e64.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg2e64.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x7c,0xb5,0x28] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c b5 28 + +vssseg2e128.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg2e128.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x0c,0xb5,0x38] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c b5 38 + +vssseg2e256.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg2e256.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x5c,0xb5,0x38] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c b5 38 + +vssseg2e512.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg2e512.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x6c,0xb5,0x38] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c b5 38 + +vssseg2e1024.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg2e1024.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x7c,0xb5,0x38] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c b5 38 + +vssseg3e8.v v24, (a0), a1 +# CHECK-INST: vssseg3e8.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x0c,0xb5,0x4a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c b5 4a + +vssseg3e16.v v24, (a0), a1 +# CHECK-INST: vssseg3e16.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x5c,0xb5,0x4a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c b5 4a + +vssseg3e32.v v24, (a0), a1 +# CHECK-INST: vssseg3e32.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x6c,0xb5,0x4a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c b5 4a + +vssseg3e64.v v24, (a0), a1 +# CHECK-INST: vssseg3e64.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x7c,0xb5,0x4a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c b5 4a + +vssseg3e128.v v24, (a0), a1 +# CHECK-INST: vssseg3e128.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x0c,0xb5,0x5a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c b5 5a + +vssseg3e256.v v24, (a0), a1 +# CHECK-INST: vssseg3e256.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x5c,0xb5,0x5a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c b5 5a + +vssseg3e512.v v24, (a0), a1 +# CHECK-INST: vssseg3e512.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x6c,0xb5,0x5a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c b5 5a + +vssseg3e1024.v v24, (a0), a1 +# CHECK-INST: vssseg3e1024.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x7c,0xb5,0x5a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c b5 5a + +vssseg3e8.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg3e8.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x0c,0xb5,0x48] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c b5 48 + +vssseg3e16.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg3e16.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x5c,0xb5,0x48] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c b5 48 + +vssseg3e32.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg3e32.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x6c,0xb5,0x48] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c b5 48 + +vssseg3e64.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg3e64.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x7c,0xb5,0x48] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c b5 48 + +vssseg3e128.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg3e128.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x0c,0xb5,0x58] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c b5 58 + +vssseg3e256.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg3e256.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x5c,0xb5,0x58] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c b5 58 + +vssseg3e512.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg3e512.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x6c,0xb5,0x58] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c b5 58 + +vssseg3e1024.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg3e1024.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x7c,0xb5,0x58] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c b5 58 + +vssseg4e8.v v24, (a0), a1 +# CHECK-INST: vssseg4e8.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x0c,0xb5,0x6a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c b5 6a + +vssseg4e16.v v24, (a0), a1 +# CHECK-INST: vssseg4e16.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x5c,0xb5,0x6a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c b5 6a + +vssseg4e32.v v24, (a0), a1 +# CHECK-INST: vssseg4e32.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x6c,0xb5,0x6a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c b5 6a + +vssseg4e64.v v24, (a0), a1 +# CHECK-INST: vssseg4e64.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x7c,0xb5,0x6a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c b5 6a + +vssseg4e128.v v24, (a0), a1 +# CHECK-INST: vssseg4e128.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x0c,0xb5,0x7a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c b5 7a + +vssseg4e256.v v24, (a0), a1 +# CHECK-INST: vssseg4e256.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x5c,0xb5,0x7a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c b5 7a + +vssseg4e512.v v24, (a0), a1 +# CHECK-INST: vssseg4e512.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x6c,0xb5,0x7a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c b5 7a + +vssseg4e1024.v v24, (a0), a1 +# CHECK-INST: vssseg4e1024.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x7c,0xb5,0x7a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c b5 7a + +vssseg4e8.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg4e8.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x0c,0xb5,0x68] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c b5 68 + +vssseg4e16.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg4e16.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x5c,0xb5,0x68] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c b5 68 + +vssseg4e32.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg4e32.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x6c,0xb5,0x68] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c b5 68 + +vssseg4e64.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg4e64.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x7c,0xb5,0x68] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c b5 68 + +vssseg4e128.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg4e128.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x0c,0xb5,0x78] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c b5 78 + +vssseg4e256.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg4e256.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x5c,0xb5,0x78] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c b5 78 + +vssseg4e512.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg4e512.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x6c,0xb5,0x78] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c b5 78 + +vssseg4e1024.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg4e1024.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x7c,0xb5,0x78] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c b5 78 + +vssseg5e8.v v24, (a0), a1 +# CHECK-INST: vssseg5e8.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x0c,0xb5,0x8a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c b5 8a + +vssseg5e16.v v24, (a0), a1 +# CHECK-INST: vssseg5e16.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x5c,0xb5,0x8a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c b5 8a + +vssseg5e32.v v24, (a0), a1 +# CHECK-INST: vssseg5e32.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x6c,0xb5,0x8a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c b5 8a + +vssseg5e64.v v24, (a0), a1 +# CHECK-INST: vssseg5e64.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x7c,0xb5,0x8a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c b5 8a + +vssseg5e128.v v24, (a0), a1 +# CHECK-INST: vssseg5e128.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x0c,0xb5,0x9a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c b5 9a + +vssseg5e256.v v24, (a0), a1 +# CHECK-INST: vssseg5e256.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x5c,0xb5,0x9a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c b5 9a + +vssseg5e512.v v24, (a0), a1 +# CHECK-INST: vssseg5e512.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x6c,0xb5,0x9a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c b5 9a + +vssseg5e1024.v v24, (a0), a1 +# CHECK-INST: vssseg5e1024.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x7c,0xb5,0x9a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c b5 9a + +vssseg5e8.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg5e8.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x0c,0xb5,0x88] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c b5 88 + +vssseg5e16.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg5e16.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x5c,0xb5,0x88] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c b5 88 + +vssseg5e32.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg5e32.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x6c,0xb5,0x88] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c b5 88 + +vssseg5e64.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg5e64.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x7c,0xb5,0x88] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c b5 88 + +vssseg5e128.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg5e128.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x0c,0xb5,0x98] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c b5 98 + +vssseg5e256.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg5e256.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x5c,0xb5,0x98] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c b5 98 + +vssseg5e512.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg5e512.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x6c,0xb5,0x98] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c b5 98 + +vssseg5e1024.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg5e1024.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x7c,0xb5,0x98] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c b5 98 + +vssseg6e8.v v24, (a0), a1 +# CHECK-INST: vssseg6e8.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x0c,0xb5,0xaa] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c b5 aa + +vssseg6e16.v v24, (a0), a1 +# CHECK-INST: vssseg6e16.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x5c,0xb5,0xaa] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c b5 aa + +vssseg6e32.v v24, (a0), a1 +# CHECK-INST: vssseg6e32.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x6c,0xb5,0xaa] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c b5 aa + +vssseg6e64.v v24, (a0), a1 +# CHECK-INST: vssseg6e64.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x7c,0xb5,0xaa] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c b5 aa + +vssseg6e128.v v24, (a0), a1 +# CHECK-INST: vssseg6e128.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x0c,0xb5,0xba] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c b5 ba + +vssseg6e256.v v24, (a0), a1 +# CHECK-INST: vssseg6e256.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x5c,0xb5,0xba] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c b5 ba + +vssseg6e512.v v24, (a0), a1 +# CHECK-INST: vssseg6e512.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x6c,0xb5,0xba] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c b5 ba + +vssseg6e1024.v v24, (a0), a1 +# CHECK-INST: vssseg6e1024.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x7c,0xb5,0xba] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c b5 ba + +vssseg6e8.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg6e8.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x0c,0xb5,0xa8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c b5 a8 + +vssseg6e16.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg6e16.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x5c,0xb5,0xa8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c b5 a8 + +vssseg6e32.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg6e32.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x6c,0xb5,0xa8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c b5 a8 + +vssseg6e64.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg6e64.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x7c,0xb5,0xa8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c b5 a8 + +vssseg6e128.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg6e128.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x0c,0xb5,0xb8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c b5 b8 + +vssseg6e256.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg6e256.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x5c,0xb5,0xb8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c b5 b8 + +vssseg6e512.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg6e512.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x6c,0xb5,0xb8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c b5 b8 + +vssseg6e1024.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg6e1024.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x7c,0xb5,0xb8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c b5 b8 + +vssseg7e8.v v24, (a0), a1 +# CHECK-INST: vssseg7e8.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x0c,0xb5,0xca] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c b5 ca + +vssseg7e16.v v24, (a0), a1 +# CHECK-INST: vssseg7e16.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x5c,0xb5,0xca] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c b5 ca + +vssseg7e32.v v24, (a0), a1 +# CHECK-INST: vssseg7e32.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x6c,0xb5,0xca] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c b5 ca + +vssseg7e64.v v24, (a0), a1 +# CHECK-INST: vssseg7e64.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x7c,0xb5,0xca] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c b5 ca + +vssseg7e128.v v24, (a0), a1 +# CHECK-INST: vssseg7e128.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x0c,0xb5,0xda] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c b5 da + +vssseg7e256.v v24, (a0), a1 +# CHECK-INST: vssseg7e256.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x5c,0xb5,0xda] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c b5 da + +vssseg7e512.v v24, (a0), a1 +# CHECK-INST: vssseg7e512.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x6c,0xb5,0xda] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c b5 da + +vssseg7e1024.v v24, (a0), a1 +# CHECK-INST: vssseg7e1024.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x7c,0xb5,0xda] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c b5 da + +vssseg7e8.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg7e8.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x0c,0xb5,0xc8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c b5 c8 + +vssseg7e16.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg7e16.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x5c,0xb5,0xc8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c b5 c8 + +vssseg7e32.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg7e32.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x6c,0xb5,0xc8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c b5 c8 + +vssseg7e64.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg7e64.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x7c,0xb5,0xc8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c b5 c8 + +vssseg7e128.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg7e128.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x0c,0xb5,0xd8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c b5 d8 + +vssseg7e256.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg7e256.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x5c,0xb5,0xd8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c b5 d8 + +vssseg7e512.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg7e512.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x6c,0xb5,0xd8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c b5 d8 + +vssseg7e1024.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg7e1024.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x7c,0xb5,0xd8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c b5 d8 + +vssseg8e8.v v24, (a0), a1 +# CHECK-INST: vssseg8e8.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x0c,0xb5,0xea] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c b5 ea + +vssseg8e16.v v24, (a0), a1 +# CHECK-INST: vssseg8e16.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x5c,0xb5,0xea] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c b5 ea + +vssseg8e32.v v24, (a0), a1 +# CHECK-INST: vssseg8e32.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x6c,0xb5,0xea] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c b5 ea + +vssseg8e64.v v24, (a0), a1 +# CHECK-INST: vssseg8e64.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x7c,0xb5,0xea] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c b5 ea + +vssseg8e128.v v24, (a0), a1 +# CHECK-INST: vssseg8e128.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x0c,0xb5,0xfa] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c b5 fa + +vssseg8e256.v v24, (a0), a1 +# CHECK-INST: vssseg8e256.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x5c,0xb5,0xfa] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c b5 fa + +vssseg8e512.v v24, (a0), a1 +# CHECK-INST: vssseg8e512.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x6c,0xb5,0xfa] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c b5 fa + +vssseg8e1024.v v24, (a0), a1 +# CHECK-INST: vssseg8e1024.v v24, (a0), a1 +# CHECK-ENCODING: [0x27,0x7c,0xb5,0xfa] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c b5 fa + +vssseg8e8.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg8e8.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x0c,0xb5,0xe8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c b5 e8 + +vssseg8e16.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg8e16.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x5c,0xb5,0xe8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c b5 e8 + +vssseg8e32.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg8e32.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x6c,0xb5,0xe8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c b5 e8 + +vssseg8e64.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg8e64.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x7c,0xb5,0xe8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c b5 e8 + +vssseg8e128.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg8e128.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x0c,0xb5,0xf8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c b5 f8 + +vssseg8e256.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg8e256.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x5c,0xb5,0xf8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c b5 f8 + +vssseg8e512.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg8e512.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x6c,0xb5,0xf8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c b5 f8 + +vssseg8e1024.v v24, (a0), a1, v0.t +# CHECK-INST: vssseg8e1024.v v24, (a0), a1, v0.t +# CHECK-ENCODING: [0x27,0x7c,0xb5,0xf8] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c b5 f8 + +vsxseg2ei8.v v24, (a0), v4 +# CHECK-INST: vsxseg2ei8.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x0c,0x45,0x2e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 45 2e + +vsxseg2ei16.v v24, (a0), v4 +# CHECK-INST: vsxseg2ei16.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x5c,0x45,0x2e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 45 2e + +vsxseg2ei32.v v24, (a0), v4 +# CHECK-INST: vsxseg2ei32.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x6c,0x45,0x2e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 45 2e + +vsxseg2ei64.v v24, (a0), v4 +# CHECK-INST: vsxseg2ei64.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x7c,0x45,0x2e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 45 2e + +vsxseg2ei128.v v24, (a0), v4 +# CHECK-INST: vsxseg2ei128.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x0c,0x45,0x3e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 45 3e + +vsxseg2ei256.v v24, (a0), v4 +# CHECK-INST: vsxseg2ei256.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x5c,0x45,0x3e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 45 3e + +vsxseg2ei512.v v24, (a0), v4 +# CHECK-INST: vsxseg2ei512.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x6c,0x45,0x3e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 45 3e + +vsxseg2ei1024.v v24, (a0), v4 +# CHECK-INST: vsxseg2ei1024.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x7c,0x45,0x3e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 45 3e + +vsxseg2ei8.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg2ei8.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x0c,0x45,0x2c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 45 2c + +vsxseg2ei16.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg2ei16.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x5c,0x45,0x2c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 45 2c + +vsxseg2ei32.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg2ei32.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x6c,0x45,0x2c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 45 2c + +vsxseg2ei64.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg2ei64.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x7c,0x45,0x2c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 45 2c + +vsxseg2ei128.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg2ei128.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x0c,0x45,0x3c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 45 3c + +vsxseg2ei256.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg2ei256.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x5c,0x45,0x3c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 45 3c + +vsxseg2ei512.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg2ei512.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x6c,0x45,0x3c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 45 3c + +vsxseg2ei1024.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg2ei1024.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x7c,0x45,0x3c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 45 3c + +vsxseg3ei8.v v24, (a0), v4 +# CHECK-INST: vsxseg3ei8.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x0c,0x45,0x4e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 45 4e + +vsxseg3ei16.v v24, (a0), v4 +# CHECK-INST: vsxseg3ei16.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x5c,0x45,0x4e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 45 4e + +vsxseg3ei32.v v24, (a0), v4 +# CHECK-INST: vsxseg3ei32.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x6c,0x45,0x4e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 45 4e + +vsxseg3ei64.v v24, (a0), v4 +# CHECK-INST: vsxseg3ei64.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x7c,0x45,0x4e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 45 4e + +vsxseg3ei128.v v24, (a0), v4 +# CHECK-INST: vsxseg3ei128.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x0c,0x45,0x5e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 45 5e + +vsxseg3ei256.v v24, (a0), v4 +# CHECK-INST: vsxseg3ei256.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x5c,0x45,0x5e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 45 5e + +vsxseg3ei512.v v24, (a0), v4 +# CHECK-INST: vsxseg3ei512.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x6c,0x45,0x5e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 45 5e + +vsxseg3ei1024.v v24, (a0), v4 +# CHECK-INST: vsxseg3ei1024.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x7c,0x45,0x5e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 45 5e + +vsxseg3ei8.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg3ei8.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x0c,0x45,0x4c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 45 4c + +vsxseg3ei16.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg3ei16.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x5c,0x45,0x4c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 45 4c + +vsxseg3ei32.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg3ei32.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x6c,0x45,0x4c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 45 4c + +vsxseg3ei64.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg3ei64.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x7c,0x45,0x4c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 45 4c + +vsxseg3ei128.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg3ei128.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x0c,0x45,0x5c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 45 5c + +vsxseg3ei256.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg3ei256.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x5c,0x45,0x5c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 45 5c + +vsxseg3ei512.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg3ei512.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x6c,0x45,0x5c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 45 5c + +vsxseg3ei1024.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg3ei1024.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x7c,0x45,0x5c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 45 5c + +vsxseg4ei8.v v24, (a0), v4 +# CHECK-INST: vsxseg4ei8.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x0c,0x45,0x6e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 45 6e + +vsxseg4ei16.v v24, (a0), v4 +# CHECK-INST: vsxseg4ei16.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x5c,0x45,0x6e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 45 6e + +vsxseg4ei32.v v24, (a0), v4 +# CHECK-INST: vsxseg4ei32.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x6c,0x45,0x6e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 45 6e + +vsxseg4ei64.v v24, (a0), v4 +# CHECK-INST: vsxseg4ei64.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x7c,0x45,0x6e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 45 6e + +vsxseg4ei128.v v24, (a0), v4 +# CHECK-INST: vsxseg4ei128.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x0c,0x45,0x7e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 45 7e + +vsxseg4ei256.v v24, (a0), v4 +# CHECK-INST: vsxseg4ei256.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x5c,0x45,0x7e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 45 7e + +vsxseg4ei512.v v24, (a0), v4 +# CHECK-INST: vsxseg4ei512.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x6c,0x45,0x7e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 45 7e + +vsxseg4ei1024.v v24, (a0), v4 +# CHECK-INST: vsxseg4ei1024.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x7c,0x45,0x7e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 45 7e + +vsxseg4ei8.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg4ei8.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x0c,0x45,0x6c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 45 6c + +vsxseg4ei16.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg4ei16.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x5c,0x45,0x6c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 45 6c + +vsxseg4ei32.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg4ei32.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x6c,0x45,0x6c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 45 6c + +vsxseg4ei64.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg4ei64.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x7c,0x45,0x6c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 45 6c + +vsxseg4ei128.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg4ei128.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x0c,0x45,0x7c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 45 7c + +vsxseg4ei256.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg4ei256.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x5c,0x45,0x7c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 45 7c + +vsxseg4ei512.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg4ei512.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x6c,0x45,0x7c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 45 7c + +vsxseg4ei1024.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg4ei1024.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x7c,0x45,0x7c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 45 7c + +vsxseg5ei8.v v24, (a0), v4 +# CHECK-INST: vsxseg5ei8.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x0c,0x45,0x8e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 45 8e + +vsxseg5ei16.v v24, (a0), v4 +# CHECK-INST: vsxseg5ei16.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x5c,0x45,0x8e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 45 8e + +vsxseg5ei32.v v24, (a0), v4 +# CHECK-INST: vsxseg5ei32.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x6c,0x45,0x8e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 45 8e + +vsxseg5ei64.v v24, (a0), v4 +# CHECK-INST: vsxseg5ei64.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x7c,0x45,0x8e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 45 8e + +vsxseg5ei128.v v24, (a0), v4 +# CHECK-INST: vsxseg5ei128.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x0c,0x45,0x9e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 45 9e + +vsxseg5ei256.v v24, (a0), v4 +# CHECK-INST: vsxseg5ei256.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x5c,0x45,0x9e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 45 9e + +vsxseg5ei512.v v24, (a0), v4 +# CHECK-INST: vsxseg5ei512.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x6c,0x45,0x9e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 45 9e + +vsxseg5ei1024.v v24, (a0), v4 +# CHECK-INST: vsxseg5ei1024.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x7c,0x45,0x9e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 45 9e + +vsxseg5ei8.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg5ei8.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x0c,0x45,0x8c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 45 8c + +vsxseg5ei16.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg5ei16.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x5c,0x45,0x8c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 45 8c + +vsxseg5ei32.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg5ei32.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x6c,0x45,0x8c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 45 8c + +vsxseg5ei64.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg5ei64.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x7c,0x45,0x8c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 45 8c + +vsxseg5ei128.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg5ei128.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x0c,0x45,0x9c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 45 9c + +vsxseg5ei256.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg5ei256.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x5c,0x45,0x9c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 45 9c + +vsxseg5ei512.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg5ei512.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x6c,0x45,0x9c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 45 9c + +vsxseg5ei1024.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg5ei1024.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x7c,0x45,0x9c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 45 9c + +vsxseg6ei8.v v24, (a0), v4 +# CHECK-INST: vsxseg6ei8.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x0c,0x45,0xae] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 45 ae + +vsxseg6ei16.v v24, (a0), v4 +# CHECK-INST: vsxseg6ei16.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x5c,0x45,0xae] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 45 ae + +vsxseg6ei32.v v24, (a0), v4 +# CHECK-INST: vsxseg6ei32.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x6c,0x45,0xae] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 45 ae + +vsxseg6ei64.v v24, (a0), v4 +# CHECK-INST: vsxseg6ei64.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x7c,0x45,0xae] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 45 ae + +vsxseg6ei128.v v24, (a0), v4 +# CHECK-INST: vsxseg6ei128.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x0c,0x45,0xbe] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 45 be + +vsxseg6ei256.v v24, (a0), v4 +# CHECK-INST: vsxseg6ei256.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x5c,0x45,0xbe] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 45 be + +vsxseg6ei512.v v24, (a0), v4 +# CHECK-INST: vsxseg6ei512.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x6c,0x45,0xbe] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 45 be + +vsxseg6ei1024.v v24, (a0), v4 +# CHECK-INST: vsxseg6ei1024.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x7c,0x45,0xbe] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 45 be + +vsxseg6ei8.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg6ei8.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x0c,0x45,0xac] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 45 ac + +vsxseg6ei16.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg6ei16.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x5c,0x45,0xac] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 45 ac + +vsxseg6ei32.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg6ei32.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x6c,0x45,0xac] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 45 ac + +vsxseg6ei64.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg6ei64.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x7c,0x45,0xac] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 45 ac + +vsxseg6ei128.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg6ei128.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x0c,0x45,0xbc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 45 bc + +vsxseg6ei256.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg6ei256.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x5c,0x45,0xbc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 45 bc + +vsxseg6ei512.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg6ei512.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x6c,0x45,0xbc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 45 bc + +vsxseg6ei1024.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg6ei1024.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x7c,0x45,0xbc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 45 bc + +vsxseg7ei8.v v24, (a0), v4 +# CHECK-INST: vsxseg7ei8.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x0c,0x45,0xce] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 45 ce + +vsxseg7ei16.v v24, (a0), v4 +# CHECK-INST: vsxseg7ei16.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x5c,0x45,0xce] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 45 ce + +vsxseg7ei32.v v24, (a0), v4 +# CHECK-INST: vsxseg7ei32.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x6c,0x45,0xce] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 45 ce + +vsxseg7ei64.v v24, (a0), v4 +# CHECK-INST: vsxseg7ei64.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x7c,0x45,0xce] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 45 ce + +vsxseg7ei128.v v24, (a0), v4 +# CHECK-INST: vsxseg7ei128.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x0c,0x45,0xde] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 45 de + +vsxseg7ei256.v v24, (a0), v4 +# CHECK-INST: vsxseg7ei256.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x5c,0x45,0xde] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 45 de + +vsxseg7ei512.v v24, (a0), v4 +# CHECK-INST: vsxseg7ei512.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x6c,0x45,0xde] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 45 de + +vsxseg7ei1024.v v24, (a0), v4 +# CHECK-INST: vsxseg7ei1024.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x7c,0x45,0xde] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 45 de + +vsxseg7ei8.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg7ei8.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x0c,0x45,0xcc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 45 cc + +vsxseg7ei16.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg7ei16.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x5c,0x45,0xcc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 45 cc + +vsxseg7ei32.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg7ei32.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x6c,0x45,0xcc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 45 cc + +vsxseg7ei64.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg7ei64.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x7c,0x45,0xcc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 45 cc + +vsxseg7ei128.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg7ei128.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x0c,0x45,0xdc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 45 dc + +vsxseg7ei256.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg7ei256.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x5c,0x45,0xdc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 45 dc + +vsxseg7ei512.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg7ei512.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x6c,0x45,0xdc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 45 dc + +vsxseg7ei1024.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg7ei1024.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x7c,0x45,0xdc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 45 dc + +vsxseg8ei8.v v24, (a0), v4 +# CHECK-INST: vsxseg8ei8.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x0c,0x45,0xee] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 45 ee + +vsxseg8ei16.v v24, (a0), v4 +# CHECK-INST: vsxseg8ei16.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x5c,0x45,0xee] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 45 ee + +vsxseg8ei32.v v24, (a0), v4 +# CHECK-INST: vsxseg8ei32.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x6c,0x45,0xee] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 45 ee + +vsxseg8ei64.v v24, (a0), v4 +# CHECK-INST: vsxseg8ei64.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x7c,0x45,0xee] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 45 ee + +vsxseg8ei128.v v24, (a0), v4 +# CHECK-INST: vsxseg8ei128.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x0c,0x45,0xfe] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 45 fe + +vsxseg8ei256.v v24, (a0), v4 +# CHECK-INST: vsxseg8ei256.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x5c,0x45,0xfe] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 45 fe + +vsxseg8ei512.v v24, (a0), v4 +# CHECK-INST: vsxseg8ei512.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x6c,0x45,0xfe] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 45 fe + +vsxseg8ei1024.v v24, (a0), v4 +# CHECK-INST: vsxseg8ei1024.v v24, (a0), v4 +# CHECK-ENCODING: [0x27,0x7c,0x45,0xfe] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 45 fe + +vsxseg8ei8.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg8ei8.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x0c,0x45,0xec] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 45 ec + +vsxseg8ei16.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg8ei16.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x5c,0x45,0xec] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 45 ec + +vsxseg8ei32.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg8ei32.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x6c,0x45,0xec] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 45 ec + +vsxseg8ei64.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg8ei64.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x7c,0x45,0xec] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 45 ec + +vsxseg8ei128.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg8ei128.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x0c,0x45,0xfc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 0c 45 fc + +vsxseg8ei256.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg8ei256.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x5c,0x45,0xfc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 5c 45 fc + +vsxseg8ei512.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg8ei512.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x6c,0x45,0xfc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 6c 45 fc + +vsxseg8ei1024.v v24, (a0), v4, v0.t +# CHECK-INST: vsxseg8ei1024.v v24, (a0), v4, v0.t +# CHECK-ENCODING: [0x27,0x7c,0x45,0xfc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions) +# CHECK-UNKNOWN: 27 7c 45 fc \ No newline at end of file