Index: llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
@@ -1424,10 +1424,22 @@
         .copyImplicitOps(*MBBI);
     MBB.erase(MBBI);
   } else {
-    BuildMI(
-        MBB, MBBI, DL,
-        TII->get(ShouldSignWithAKey(MF) ? AArch64::AUTIASP : AArch64::AUTIBSP))
-        .setMIFlag(MachineInstr::FrameDestroy);
+    MachineInstrBuilder B =
+        BuildMI(MBB, MBBI, DL,
+                TII->get(ShouldSignWithAKey(MF) ? AArch64::AUTIASP
+                                                : AArch64::AUTIBSP))
+            .setMIFlag(MachineInstr::FrameDestroy);
+    // Similarly to way we handle LR use in RET_ReallyLR (see comment in
+    // AArch64ExpandPseudeInstrs.cpp), rely on callee-saved register handling to
+    // ensure LR is restored before we emit the AUTIxSP, but set the undef flag
+    // here to appease the MachineVerifier liveness checks.
+    for (MachineOperand &MO : B.getInstr()->operands()) {
+      if (!MO.isReg() || MO.isDef())
+        continue;
+      if (MO.getReg() != AArch64::LR)
+        continue;
+      MO.setIsUndef();
+    }
   }
 }
 
Index: llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -6536,10 +6536,22 @@
           .copyImplicitOps(*MBBAUT);
       MBB.erase(MBBAUT);
     } else {
-      BuildMI(MBB, MBBAUT, DL,
-              TII->get(ShouldSignReturnAddrWithAKey ? AArch64::AUTIASP
-                                                    : AArch64::AUTIBSP))
-          .setMIFlag(MachineInstr::FrameDestroy);
+      MachineInstrBuilder B =
+          BuildMI(MBB, MBBAUT, DL,
+                  TII->get(ShouldSignReturnAddrWithAKey ? AArch64::AUTIASP
+                                                        : AArch64::AUTIBSP))
+              .setMIFlag(MachineInstr::FrameDestroy);
+      // Similarly to way we handle LR use in RET_ReallyLR (see comment in
+      // AArch64ExpandPseudeInstrs.cpp), rely on callee-saved register handling
+      // to ensure LR is restored before we emit the AUTIxSP, but set the undef
+      // flag here to appease the MachineVerifier liveness checks.
+      for (MachineOperand &MO : B.getInstr()->operands()) {
+        if (!MO.isReg() || MO.isDef())
+          continue;
+        if (MO.getReg() != AArch64::LR)
+          continue;
+        MO.setIsUndef();
+      }
     }
   }
 }
Index: llvm/test/CodeGen/AArch64/builtin-return-address-autisap.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/builtin-return-address-autisap.ll
@@ -0,0 +1,16 @@
+;; RUN: llc  -mtriple aarch64 %s -o - | FileCheck %s
+define i8* @f() #0 {
+entry:
+  %0 = tail call i8* @llvm.returnaddress(i32 0)
+  ret i8* %0
+}
+
+declare i8* @llvm.returnaddress(i32 immarg) #1
+
+attributes #0 = { nounwind readnone  "sign-return-address"="all" "sign-return-address-key"="a_key" }
+attributes #1 = { nounwind readnone }
+
+;; CHECK-LABEL: f:
+;; CHECK:      mov x0, x30
+;; CHECK-NEXT: hint #29
+;; CHECK-NEXT: ret
Index: llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-sp-mod.mir
===================================================================
--- llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-sp-mod.mir
+++ llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-sp-mod.mir
@@ -80,7 +80,7 @@
     STRXui renamable $x9, renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile store 8 into @v)
     STRXui killed renamable $x9, killed renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile store 8 into @v)
     $sp = frame-destroy ADDXri $sp, 16, 0
-    frame-destroy AUTIASP implicit-def $lr, implicit killed $lr, implicit $sp
+    frame-destroy AUTIASP implicit-def $lr, implicit undef $lr, implicit $sp
     RET undef $lr
 
 # CHECK-LABEL:    name:            legal0
@@ -90,7 +90,7 @@
 # CHECK:                frame-setup PACIASP implicit-def $lr, implicit killed $lr, implicit $sp
 # CHECK-NEXT:           frame-setup CFI_INSTRUCTION negate_ra_sign_state
 # CHECK:                BL @[[OUTLINED_FUNC:OUTLINED_FUNCTION_[0-9]+]]
-# CHECK:                frame-destroy AUTIASP implicit-def $lr, implicit killed $lr, implicit $sp
+# CHECK:                frame-destroy AUTIASP implicit-def $lr, implicit undef $lr, implicit $sp
 # CHECK-NEXT:           RET undef $lr
 
 ...
@@ -113,7 +113,7 @@
     STRXui renamable $x9, renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile store 8 into @v)
     STRXui killed renamable $x9, killed renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile store 8 into @v)
     $sp = frame-destroy ADDXri $sp, 16, 0
-    frame-destroy AUTIASP implicit-def $lr, implicit killed $lr, implicit $sp
+    frame-destroy AUTIASP implicit-def $lr, implicit undef $lr, implicit $sp
     RET undef $lr
 
 # CHECK-LABEL:    name:            legal1
@@ -123,7 +123,7 @@
 # CHECK:                frame-setup PACIASP implicit-def $lr, implicit killed $lr, implicit $sp
 # CHECK-NEXT:           frame-setup CFI_INSTRUCTION negate_ra_sign_state
 # CHECK:                BL @[[OUTLINED_FUNC]]
-# CHECK:                frame-destroy AUTIASP implicit-def $lr, implicit killed $lr, implicit $sp
+# CHECK:                frame-destroy AUTIASP implicit-def $lr, implicit undef $lr, implicit $sp
 # CHECK-NEXT:           RET undef $lr
 
 ...
@@ -146,7 +146,7 @@
     STRXui renamable $x9, renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile store 8 into @v)
     STRXui killed renamable $x9, killed renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile store 8 into @v)
     $sp = frame-destroy ADDXri $sp, 12, 0
-    frame-destroy AUTIASP implicit-def $lr, implicit killed $lr, implicit $sp
+    frame-destroy AUTIASP implicit-def $lr, implicit undef $lr, implicit $sp
     RET undef $lr
 
 ...
@@ -169,7 +169,7 @@
     STRXui renamable $x9, renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile store 8 into @v)
     STRXui killed renamable $x9, killed renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @v :: (volatile store 8 into @v)
     $sp = frame-destroy ADDXri $sp, 12, 0
-    frame-destroy AUTIASP implicit-def $lr, implicit killed $lr, implicit $sp
+    frame-destroy AUTIASP implicit-def $lr, implicit undef $lr, implicit $sp
     RET undef $lr
 
 # CHECK-LABEL:    name:            illegal0
@@ -179,7 +179,7 @@
 # CHECK:                frame-setup PACIASP implicit-def $lr, implicit killed $lr, implicit $sp
 # CHECK-NEXT:           frame-setup CFI_INSTRUCTION negate_ra_sign_state
 # CHECK-NOT:            BL @OUTLINED_FUNCTION_{{.*}}
-# CHECK:                frame-destroy AUTIASP implicit-def $lr, implicit killed $lr, implicit $sp
+# CHECK:                frame-destroy AUTIASP implicit-def $lr, implicit undef $lr, implicit $sp
 # CHECK-NEXT:           RET undef $lr
 
 # CHECK-LABEL:    name:            illegal1
@@ -189,7 +189,7 @@
 # CHECK:                frame-setup PACIASP implicit-def $lr, implicit killed $lr, implicit $sp
 # CHECK-NEXT:           frame-setup CFI_INSTRUCTION negate_ra_sign_state
 # CHECK-NOT:            BL @OUTLINED_FUNCTION_{{.*}}
-# CHECK:                frame-destroy AUTIASP implicit-def $lr, implicit killed $lr, implicit $sp
+# CHECK:                frame-destroy AUTIASP implicit-def $lr, implicit undef $lr, implicit $sp
 # CHECK-NEXT:           RET undef $lr
 
 # Outlined function that contains only legal sp modifications
@@ -202,5 +202,5 @@
 # CHECK-NEXT:         frame-setup CFI_INSTRUCTION negate_ra_sign_state
 # CHECK-NEXT:         $sp = frame-setup SUBXri $sp, 16, 0
 # CHECK:              $sp = frame-destroy ADDXri $sp, 16, 0
-# CHECK-NEXT:         frame-destroy AUTIASP implicit-def $lr, implicit $lr, implicit $sp
+# CHECK-NEXT:         frame-destroy AUTIASP implicit-def $lr, implicit undef $lr, implicit $sp
 # CHECK-NEXT:         RET $lr
Index: llvm/test/CodeGen/MIR/AArch64/return-address-signing.mir
===================================================================
--- llvm/test/CodeGen/MIR/AArch64/return-address-signing.mir
+++ llvm/test/CodeGen/MIR/AArch64/return-address-signing.mir
@@ -22,7 +22,7 @@
   maxCallFrameSize: 0
 #CHECK:    frame-setup PACIASP implicit-def $lr, implicit $lr, implicit $sp
 #CHECK:    frame-setup CFI_INSTRUCTION negate_ra_sign_state
-#CHECK:    frame-destroy AUTIASP implicit-def $lr, implicit $lr, implicit $sp
+#CHECK:    frame-destroy AUTIASP implicit-def $lr, implicit undef $lr, implicit $sp
 body:             |
   bb.0.entry:
     $w0 = MOVi32imm 2
@@ -39,7 +39,7 @@
 #CHECK:    frame-setup EMITBKEY
 #CHECK:    frame-setup PACIBSP implicit-def $lr, implicit $lr, implicit $sp
 #CHECK:    frame-setup CFI_INSTRUCTION negate_ra_sign_state
-#CHECK:    frame-destroy AUTIBSP implicit-def $lr, implicit $lr, implicit $sp
+#CHECK:    frame-destroy AUTIBSP implicit-def $lr, implicit undef $lr, implicit $sp
 body:             |
   bb.0.entry:
     $w0 = MOVi32imm 2