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Differential D84111

[X86] Enable PostRA scheduler in the SNB scheduler model the default for Linux and Windows w/clang
Changes PlannedPublic

Authored by craig.topper on Jul 18 2020, 3:44 PM.

Details

Reviewers
spatel
RKSimon
echristo
andreadb
Summary

This patch enables the PostRA scheduler in the SNB scheduler model.
This model is used by default for 32-bit and 64-bit Linux and
Windows.

We were previously using PostRA by default on 32-bit until I
changed 'pentium4' to use the SNB scheduler earlier this week.

I haven't done any perf measurements with this yet. Anything
specific people would like to see?

Diff Detail

Event Timeline

craig.topper created this revision.Jul 18 2020, 3:44 PM
Herald added a project: Restricted Project. · View Herald TranscriptJul 18 2020, 3:44 PM
Herald added subscribers: mstorsjo, jfb, hiraditya, qcolombet. · View Herald Transcript
Harbormaster completed remote builds in B64822: Diff 279031.Jul 18 2020, 4:18 PM
RKSimon added a comment.Jul 21 2020, 2:10 PM

I haven't done any perf measurements with this yet. Anything specific people would like to see?

Nothing specific - test-suite should give us a reasonable overview. It would be useful to see build times as well as execution times though, thats often the reason for not enabling postra-scheduling

craig.topper planned changes to this revision.Aug 21 2020, 12:40 PM

Probably going to hold off on this until after I finish mtune.

Revision Contents

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Diff 279031

llvm/lib/Target/X86/X86SchedSandyBridge.td

Show All 17 Lines
def SandyBridgeModel : SchedMachineModel { def SandyBridgeModel : SchedMachineModel {
// All x86 instructions are modeled as a single micro-op, and SB can decode 4 // All x86 instructions are modeled as a single micro-op, and SB can decode 4
// instructions per cycle. // instructions per cycle.
// FIXME: Identify instructions that aren't a single fused micro-op. // FIXME: Identify instructions that aren't a single fused micro-op.
let IssueWidth = 4; let IssueWidth = 4;
let MicroOpBufferSize = 168; // Based on the reorder buffer. let MicroOpBufferSize = 168; // Based on the reorder buffer.
let LoadLatency = 5; let LoadLatency = 5;
let MispredictPenalty = 16; let MispredictPenalty = 16;
let PostRAScheduler = 1;
// Based on the LSD (loop-stream detector) queue size. // Based on the LSD (loop-stream detector) queue size.
let LoopMicroOpBufferSize = 28; let LoopMicroOpBufferSize = 28;
// This flag is set to allow the scheduler to assign // This flag is set to allow the scheduler to assign
// a default model to unrecognized opcodes. // a default model to unrecognized opcodes.
let CompleteModel = 0; let CompleteModel = 0;
} }
▲ Show 20 Lines • Show All 1,193 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/2007-05-15-maskmovq.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-apple-darwin8 -mcpu=yonah | FileCheck %s ; RUN: llc < %s -mtriple=i686-apple-darwin8 -mcpu=yonah | FileCheck %s
define void @test(<1 x i64> %c64, <1 x i64> %mask1, i8* %P) { define void @test(<1 x i64> %c64, <1 x i64> %mask1, i8* %P) {
; CHECK-LABEL: test: ; CHECK-LABEL: test:
; CHECK: ## %bb.0: ## %entry ; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: pushl %edi ; CHECK-NEXT: pushl %edi
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: subl $16, %esp ; CHECK-NEXT: subl $16, %esp
; CHECK-NEXT: .cfi_def_cfa_offset 24 ; CHECK-NEXT: .cfi_def_cfa_offset 24
; CHECK-NEXT: .cfi_offset %edi, -8 ; CHECK-NEXT: .cfi_offset %edi, -8
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: movl %ecx, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl %eax, (%esp)
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edi
; CHECK-NEXT: movl %ecx, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: movl %eax, (%esp)
; CHECK-NEXT: movl %edx, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl %ecx, {{[0-9]+}}(%esp) ; CHECK-NEXT: movl %ecx, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edi
; CHECK-NEXT: movq (%esp), %mm0 ; CHECK-NEXT: movq (%esp), %mm0
; CHECK-NEXT: movq {{[0-9]+}}(%esp), %mm1 ; CHECK-NEXT: movq {{[0-9]+}}(%esp), %mm1
; CHECK-NEXT: maskmovq %mm0, %mm1 ; CHECK-NEXT: maskmovq %mm0, %mm1
; CHECK-NEXT: addl $16, %esp ; CHECK-NEXT: addl $16, %esp
; CHECK-NEXT: popl %edi ; CHECK-NEXT: popl %edi
; CHECK-NEXT: retl ; CHECK-NEXT: retl
entry: entry:
%tmp4 = bitcast <1 x i64> %mask1 to x86_mmx ; <x86_mmx> [#uses=1] %tmp4 = bitcast <1 x i64> %mask1 to x86_mmx ; <x86_mmx> [#uses=1]
%tmp6 = bitcast <1 x i64> %c64 to x86_mmx ; <x86_mmx> [#uses=1] %tmp6 = bitcast <1 x i64> %c64 to x86_mmx ; <x86_mmx> [#uses=1]
tail call void @llvm.x86.mmx.maskmovq( x86_mmx %tmp4, x86_mmx %tmp6, i8* %P ) tail call void @llvm.x86.mmx.maskmovq( x86_mmx %tmp4, x86_mmx %tmp6, i8* %P )
ret void ret void
} }
declare void @llvm.x86.mmx.maskmovq(x86_mmx, x86_mmx, i8*) declare void @llvm.x86.mmx.maskmovq(x86_mmx, x86_mmx, i8*)

llvm/test/CodeGen/X86/2008-09-11-CoalescerBug2.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- ; RUN: llc < %s -mtriple=i686--
; RUN: llc -pre-RA-sched=source < %s -mtriple=i686-unknown-linux -mcpu=corei7 | FileCheck %s --check-prefix=SOURCE-SCHED ; RUN: llc -pre-RA-sched=source < %s -mtriple=i686-unknown-linux -mcpu=corei7 | FileCheck %s --check-prefix=SOURCE-SCHED
; PR2748 ; PR2748
@g_73 = external global i32 @g_73 = external global i32
@g_5 = external global i32 @g_5 = external global i32
define i32 @func_44(i16 signext %p_46) nounwind { define i32 @func_44(i16 signext %p_46) nounwind {
; SOURCE-SCHED-LABEL: func_44: ; SOURCE-SCHED-LABEL: func_44:
; SOURCE-SCHED: # %bb.0: # %entry ; SOURCE-SCHED: # %bb.0: # %entry
; SOURCE-SCHED-NEXT: subl $12, %esp ; SOURCE-SCHED-NEXT: subl $12, %esp
; SOURCE-SCHED-NEXT: movl g_5, %eax ; SOURCE-SCHED-NEXT: movl g_5, %eax
; SOURCE-SCHED-NEXT: sarl %eax
; SOURCE-SCHED-NEXT: xorl %ecx, %ecx ; SOURCE-SCHED-NEXT: xorl %ecx, %ecx
; SOURCE-SCHED-NEXT: movb g_73, %dl
; SOURCE-SCHED-NEXT: sarl %eax
; SOURCE-SCHED-NEXT: cmpl $1, %eax ; SOURCE-SCHED-NEXT: cmpl $1, %eax
; SOURCE-SCHED-NEXT: setg %cl ; SOURCE-SCHED-NEXT: setg %cl
; SOURCE-SCHED-NEXT: movb g_73, %dl
; SOURCE-SCHED-NEXT: xorl %eax, %eax ; SOURCE-SCHED-NEXT: xorl %eax, %eax
; SOURCE-SCHED-NEXT: subb {{[0-9]+}}(%esp), %al ; SOURCE-SCHED-NEXT: subb {{[0-9]+}}(%esp), %al
; SOURCE-SCHED-NEXT: testb %dl, %dl ; SOURCE-SCHED-NEXT: testb %dl, %dl
; SOURCE-SCHED-NEXT: jne .LBB0_2 ; SOURCE-SCHED-NEXT: jne .LBB0_2
; SOURCE-SCHED-NEXT: # %bb.1: # %bb11 ; SOURCE-SCHED-NEXT: # %bb.1: # %bb11
; SOURCE-SCHED-NEXT: movzbl %al, %eax ; SOURCE-SCHED-NEXT: movzbl %al, %eax
; SOURCE-SCHED-NEXT: divb %dl ; SOURCE-SCHED-NEXT: divb %dl
; SOURCE-SCHED-NEXT: movzbl %ah, %eax ; SOURCE-SCHED-NEXT: movzbl %ah, %eax
Show All 37 Lines

llvm/test/CodeGen/X86/2009-03-23-MultiUseSched.ll

Show All 16 Lines
; CHECK-NEXT: movq {{.*}}(%rip), %r8 ; CHECK-NEXT: movq {{.*}}(%rip), %r8
; CHECK-NEXT: movq {{.*}}(%rip), %r10 ; CHECK-NEXT: movq {{.*}}(%rip), %r10
; CHECK-NEXT: movq {{.*}}(%rip), %r9 ; CHECK-NEXT: movq {{.*}}(%rip), %r9
; CHECK-NEXT: movq {{.*}}(%rip), %r12 ; CHECK-NEXT: movq {{.*}}(%rip), %r12
; CHECK-NEXT: movq {{.*}}(%rip), %r15 ; CHECK-NEXT: movq {{.*}}(%rip), %r15
; CHECK-NEXT: movq {{.*}}(%rip), %r14 ; CHECK-NEXT: movq {{.*}}(%rip), %r14
; CHECK-NEXT: movq {{.*}}(%rip), %r11 ; CHECK-NEXT: movq {{.*}}(%rip), %r11
; CHECK-NEXT: movq {{.*}}(%rip), %rdx ; CHECK-NEXT: movq {{.*}}(%rip), %rdx
; CHECK-NEXT: addq %r15, %rdx
; CHECK-NEXT: movq {{.*}}(%rip), %rsi ; CHECK-NEXT: movq {{.*}}(%rip), %rsi
; CHECK-NEXT: bswapq %rsi ; CHECK-NEXT: movq {{.*}}(%rip), %rdi
; CHECK-NEXT: leaq (%r11,%r14), %rbx ; CHECK-NEXT: leaq (%r11,%r14), %rbx
; CHECK-NEXT: addq %r15, %rdx
; CHECK-NEXT: bswapq %rsi
; CHECK-NEXT: bswapq %rdi
; CHECK-NEXT: addq %r15, %rbx ; CHECK-NEXT: addq %r15, %rbx
; CHECK-NEXT: addq %rdx, %rbx ; CHECK-NEXT: addq %rdx, %rbx
; CHECK-NEXT: addq %r11, %rdi
; CHECK-NEXT: movq {{.*}}(%rip), %r11
; CHECK-NEXT: movq {{.*}}(%rip), %rcx
; CHECK-NEXT: addq %rsi, %rbx ; CHECK-NEXT: addq %rsi, %rbx
; CHECK-NEXT: leaq (%r9,%r10), %rsi ; CHECK-NEXT: leaq (%r9,%r10), %rsi
; CHECK-NEXT: leaq (%rsi,%r8), %rdx ; CHECK-NEXT: leaq (%rsi,%r8), %rdx
; CHECK-NEXT: addq %rsi, %rdx
; CHECK-NEXT: movq {{.*}}(%rip), %rdi
; CHECK-NEXT: addq %rbx, %r12 ; CHECK-NEXT: addq %rbx, %r12
; CHECK-NEXT: addq %r8, %rdx ; CHECK-NEXT: addq %rsi, %rdx
; CHECK-NEXT: bswapq %rdi
; CHECK-NEXT: addq %rbx, %rdx
; CHECK-NEXT: leaq (%r15,%r14), %rsi ; CHECK-NEXT: leaq (%r15,%r14), %rsi
; CHECK-NEXT: addq %r8, %rdx
; CHECK-NEXT: addq %r12, %rsi ; CHECK-NEXT: addq %r12, %rsi
; CHECK-NEXT: addq %r11, %rdi ; CHECK-NEXT: addq %rbx, %rdx
; CHECK-NEXT: addq %rsi, %rdi
; CHECK-NEXT: leaq (%r10,%r8), %rbx ; CHECK-NEXT: leaq (%r10,%r8), %rbx
; CHECK-NEXT: addq %rsi, %rdi
; CHECK-NEXT: bswapq %r11
; CHECK-NEXT: bswapq %rcx
; CHECK-NEXT: leaq (%rdx,%rbx), %rsi ; CHECK-NEXT: leaq (%rdx,%rbx), %rsi
; CHECK-NEXT: addq %rbx, %rsi
; CHECK-NEXT: movq {{.*}}(%rip), %rbx
; CHECK-NEXT: addq %r12, %rdi ; CHECK-NEXT: addq %r12, %rdi
; CHECK-NEXT: leaq (%rdx,%r8), %rax
; CHECK-NEXT: addq %rbx, %rsi
; CHECK-NEXT: addq %rdi, %r9 ; CHECK-NEXT: addq %rdi, %r9
; CHECK-NEXT: addq %r14, %r11
; CHECK-NEXT: addq %r15, %rcx
; CHECK-NEXT: addq %rdx, %rsi ; CHECK-NEXT: addq %rdx, %rsi
; CHECK-NEXT: addq %rdi, %rsi ; CHECK-NEXT: addq %rdi, %rsi
; CHECK-NEXT: bswapq %rbx
; CHECK-NEXT: leaq (%r12,%r15), %rdi ; CHECK-NEXT: leaq (%r12,%r15), %rdi
; CHECK-NEXT: addq %r9, %rdi ; CHECK-NEXT: addq %r9, %rdi
; CHECK-NEXT: addq %r14, %rbx ; CHECK-NEXT: leaq (%rsi,%rdx), %rbx
; CHECK-NEXT: addq %rdi, %rbx ; CHECK-NEXT: addq %rdi, %r11
; CHECK-NEXT: leaq (%rdx,%r8), %rax
; CHECK-NEXT: leaq (%rsi,%rax), %rdi ; CHECK-NEXT: leaq (%rsi,%rax), %rdi
; CHECK-NEXT: addq %rax, %rdi ; CHECK-NEXT: addq %rax, %rdi
; CHECK-NEXT: movq {{.*}}(%rip), %rcx ; CHECK-NEXT: addq %r9, %r11
; CHECK-NEXT: addq %r9, %rbx
; CHECK-NEXT: addq %rbx, %r10
; CHECK-NEXT: addq %rsi, %rdi
; CHECK-NEXT: bswapq %rcx
; CHECK-NEXT: addq %rbx, %rdi
; CHECK-NEXT: leaq (%r9,%r12), %rax ; CHECK-NEXT: leaq (%r9,%r12), %rax
; CHECK-NEXT: addq %rsi, %rdi
; CHECK-NEXT: addq %r11, %r10
; CHECK-NEXT: addq %r11, %rdi
; CHECK-NEXT: addq %r10, %rax ; CHECK-NEXT: addq %r10, %rax
; CHECK-NEXT: addq %r15, %rcx
; CHECK-NEXT: addq %rax, %rcx
; CHECK-NEXT: leaq (%rsi,%rdx), %rbx
; CHECK-NEXT: leaq (%rdi,%rbx), %r11 ; CHECK-NEXT: leaq (%rdi,%rbx), %r11
; CHECK-NEXT: addq %rax, %rcx
; CHECK-NEXT: leaq (%rdi,%rsi), %rax
; CHECK-NEXT: addq %rbx, %r11 ; CHECK-NEXT: addq %rbx, %r11
; CHECK-NEXT: movq {{.*}}(%rip), %rbx ; CHECK-NEXT: movq {{.*}}(%rip), %rbx
; CHECK-NEXT: addq %r10, %rcx ; CHECK-NEXT: addq %r10, %rcx
; CHECK-NEXT: addq %rcx, %r8
; CHECK-NEXT: addq %rdi, %r11 ; CHECK-NEXT: addq %rdi, %r11
; CHECK-NEXT: addq %rcx, %r8
; CHECK-NEXT: addq %rcx, %r11 ; CHECK-NEXT: addq %rcx, %r11
; CHECK-NEXT: bswapq %rbx
; CHECK-NEXT: leaq (%r10,%r9), %rcx ; CHECK-NEXT: leaq (%r10,%r9), %rcx
; CHECK-NEXT: addq %r8, %rcx
; CHECK-NEXT: addq %r12, %rbx
; CHECK-NEXT: addq %rcx, %rbx
; CHECK-NEXT: leaq (%rdi,%rsi), %rax
; CHECK-NEXT: leaq (%r11,%rax), %r14 ; CHECK-NEXT: leaq (%r11,%rax), %r14
; CHECK-NEXT: addq %r8, %rcx
; CHECK-NEXT: addq %rax, %r14 ; CHECK-NEXT: addq %rax, %r14
; CHECK-NEXT: movq {{.*}}(%rip), %rax ; CHECK-NEXT: movq {{.*}}(%rip), %rax
; CHECK-NEXT: addq %r8, %rbx ; CHECK-NEXT: movq {{.*}}(%rip), %r15
; CHECK-NEXT: addq %rbx, %rdx ; CHECK-NEXT: bswapq %rbx
; CHECK-NEXT: addq %r11, %r14 ; CHECK-NEXT: addq %r11, %r14
; CHECK-NEXT: addq %r12, %rbx
; CHECK-NEXT: addq %rcx, %rbx
; CHECK-NEXT: addq %r8, %rbx
; CHECK-NEXT: bswapq %rax ; CHECK-NEXT: bswapq %rax
; CHECK-NEXT: bswapq %r15
; CHECK-NEXT: addq %rbx, %rdx
; CHECK-NEXT: addq %rbx, %r14 ; CHECK-NEXT: addq %rbx, %r14
; CHECK-NEXT: leaq (%r8,%r10), %rbx ; CHECK-NEXT: leaq (%r8,%r10), %rbx
; CHECK-NEXT: addq %rdx, %rbx ; CHECK-NEXT: addq %rdx, %rbx
; CHECK-NEXT: addq %r9, %rax ; CHECK-NEXT: addq %r9, %rax
; CHECK-NEXT: addq %r10, %r15
; CHECK-NEXT: addq %rbx, %rax ; CHECK-NEXT: addq %rbx, %rax
; CHECK-NEXT: leaq (%r11,%rdi), %rbx ; CHECK-NEXT: leaq (%r11,%rdi), %rbx
; CHECK-NEXT: leaq (%r14,%rbx), %r9 ; CHECK-NEXT: leaq (%r14,%rbx), %r9
; CHECK-NEXT: addq %rbx, %r9
; CHECK-NEXT: movq {{.*}}(%rip), %rbx
; CHECK-NEXT: addq %rdx, %rax ; CHECK-NEXT: addq %rdx, %rax
; CHECK-NEXT: addq %rbx, %r9
; CHECK-NEXT: addq %rax, %rsi ; CHECK-NEXT: addq %rax, %rsi
; CHECK-NEXT: addq %r14, %r9 ; CHECK-NEXT: addq %r14, %r9
; CHECK-NEXT: leaq (%rsi,%rdx), %rbx
; CHECK-NEXT: addq %rax, %r9 ; CHECK-NEXT: addq %rax, %r9
; CHECK-NEXT: bswapq %rbx
; CHECK-NEXT: leaq (%rdx,%r8), %rax ; CHECK-NEXT: leaq (%rdx,%r8), %rax
; CHECK-NEXT: addq %rsi, %rax ; CHECK-NEXT: addq %rsi, %rax
; CHECK-NEXT: addq %r10, %rbx ; CHECK-NEXT: addq %rax, %r15
; CHECK-NEXT: addq %rax, %rbx
; CHECK-NEXT: leaq (%r14,%r11), %rax ; CHECK-NEXT: leaq (%r14,%r11), %rax
; CHECK-NEXT: leaq (%r9,%rax), %r10 ; CHECK-NEXT: leaq (%r9,%rax), %r10
; CHECK-NEXT: addq %rsi, %r15
; CHECK-NEXT: addq %rax, %r10 ; CHECK-NEXT: addq %rax, %r10
; CHECK-NEXT: movq {{.*}}(%rip), %rax ; CHECK-NEXT: movq {{.*}}(%rip), %rax
; CHECK-NEXT: addq %rsi, %rbx ; CHECK-NEXT: movq {{.*}}(%rip), %rcx
; CHECK-NEXT: addq %rbx, %rdi ; CHECK-NEXT: addq %r15, %rdi
; CHECK-NEXT: addq %r9, %r10 ; CHECK-NEXT: addq %r9, %r10
; CHECK-NEXT: bswapq %rax
; CHECK-NEXT: addq %rbx, %r10
; CHECK-NEXT: leaq (%rsi,%rdx), %rbx
; CHECK-NEXT: addq %rdi, %rbx ; CHECK-NEXT: addq %rdi, %rbx
; CHECK-NEXT: addq %r15, %r10
; CHECK-NEXT: bswapq %rax
; CHECK-NEXT: bswapq %rcx
; CHECK-NEXT: addq %r8, %rax ; CHECK-NEXT: addq %r8, %rax
; CHECK-NEXT: addq %rdx, %rcx
; CHECK-NEXT: addq %rbx, %rax ; CHECK-NEXT: addq %rbx, %rax
; CHECK-NEXT: leaq (%r9,%r14), %rbx ; CHECK-NEXT: leaq (%r9,%r14), %rbx
; CHECK-NEXT: leaq (%r10,%rbx), %r8 ; CHECK-NEXT: leaq (%r10,%rbx), %r8
; CHECK-NEXT: addq %rbx, %r8
; CHECK-NEXT: movq {{.*}}(%rip), %rbx
; CHECK-NEXT: addq %rdi, %rax ; CHECK-NEXT: addq %rdi, %rax
; CHECK-NEXT: addq %rbx, %r8
; CHECK-NEXT: addq %rax, %r11 ; CHECK-NEXT: addq %rax, %r11
; CHECK-NEXT: addq %r10, %r8 ; CHECK-NEXT: addq %r10, %r8
; CHECK-NEXT: leaq (%r11,%rdi), %rbx
; CHECK-NEXT: addq %rax, %r8 ; CHECK-NEXT: addq %rax, %r8
; CHECK-NEXT: bswapq %rbx
; CHECK-NEXT: leaq (%rdi,%rsi), %rax ; CHECK-NEXT: leaq (%rdi,%rsi), %rax
; CHECK-NEXT: addq %r11, %rax ; CHECK-NEXT: addq %r11, %rax
; CHECK-NEXT: addq %rdx, %rbx ; CHECK-NEXT: addq %rax, %rcx
; CHECK-NEXT: addq %rax, %rbx
; CHECK-NEXT: leaq (%r10,%r9), %rax ; CHECK-NEXT: leaq (%r10,%r9), %rax
; CHECK-NEXT: leaq (%r8,%rax), %r15 ; CHECK-NEXT: leaq (%r8,%rax), %r15
; CHECK-NEXT: addq %r11, %rcx
; CHECK-NEXT: addq %rax, %r15 ; CHECK-NEXT: addq %rax, %r15
; CHECK-NEXT: movq {{.*}}(%rip), %rax ; CHECK-NEXT: movq {{.*}}(%rip), %rax
; CHECK-NEXT: addq %r11, %rbx ; CHECK-NEXT: movq {{.*}}(%rip), %rdx
; CHECK-NEXT: addq %rbx, %r14 ; CHECK-NEXT: addq %rcx, %r14
; CHECK-NEXT: addq %r8, %r15 ; CHECK-NEXT: addq %r8, %r15
; CHECK-NEXT: bswapq %rax
; CHECK-NEXT: addq %rbx, %r15
; CHECK-NEXT: leaq (%r11,%rdi), %rbx
; CHECK-NEXT: addq %r14, %rbx ; CHECK-NEXT: addq %r14, %rbx
; CHECK-NEXT: addq %rcx, %r15
; CHECK-NEXT: movq {{.*}}(%rip), %rcx
; CHECK-NEXT: bswapq %rax
; CHECK-NEXT: bswapq %rdx
; CHECK-NEXT: addq %rsi, %rax ; CHECK-NEXT: addq %rsi, %rax
; CHECK-NEXT: addq %rdi, %rdx
; CHECK-NEXT: bswapq %rcx
; CHECK-NEXT: addq %rbx, %rax ; CHECK-NEXT: addq %rbx, %rax
; CHECK-NEXT: leaq (%r8,%r10), %rbx ; CHECK-NEXT: leaq (%r8,%r10), %rbx
; CHECK-NEXT: leaq (%r15,%rbx), %rsi ; CHECK-NEXT: leaq (%r15,%rbx), %rsi
; CHECK-NEXT: addq %rbx, %rsi
; CHECK-NEXT: movq {{.*}}(%rip), %rbx
; CHECK-NEXT: addq %r14, %rax ; CHECK-NEXT: addq %r14, %rax
; CHECK-NEXT: addq %r11, %rcx
; CHECK-NEXT: addq %rbx, %rsi
; CHECK-NEXT: addq %rax, %r9 ; CHECK-NEXT: addq %rax, %r9
; CHECK-NEXT: addq %r15, %rsi ; CHECK-NEXT: addq %r15, %rsi
; CHECK-NEXT: addq %rax, %rsi ; CHECK-NEXT: addq %rax, %rsi
; CHECK-NEXT: bswapq %rbx
; CHECK-NEXT: leaq (%r14,%r11), %rax ; CHECK-NEXT: leaq (%r14,%r11), %rax
; CHECK-NEXT: addq %r9, %rax ; CHECK-NEXT: addq %r9, %rax
; CHECK-NEXT: addq %rdi, %rbx ; CHECK-NEXT: leaq (%rsi,%r15), %rbx
; CHECK-NEXT: addq %rax, %rbx ; CHECK-NEXT: addq %rax, %rdx
; CHECK-NEXT: leaq (%r15,%r8), %rax ; CHECK-NEXT: leaq (%r15,%r8), %rax
; CHECK-NEXT: leaq (%rsi,%rax), %r12 ; CHECK-NEXT: leaq (%rsi,%rax), %r12
; CHECK-NEXT: addq %r9, %rdx
; CHECK-NEXT: addq %rax, %r12 ; CHECK-NEXT: addq %rax, %r12
; CHECK-NEXT: movq {{.*}}(%rip), %rcx ; CHECK-NEXT: addq %rdx, %r10
; CHECK-NEXT: addq %r9, %rbx
; CHECK-NEXT: addq %rbx, %r10
; CHECK-NEXT: addq %rsi, %r12
; CHECK-NEXT: bswapq %rcx
; CHECK-NEXT: addq %rbx, %r12
; CHECK-NEXT: leaq (%r9,%r14), %rax ; CHECK-NEXT: leaq (%r9,%r14), %rax
; CHECK-NEXT: addq %rsi, %r12
; CHECK-NEXT: addq %r10, %rax ; CHECK-NEXT: addq %r10, %rax
; CHECK-NEXT: addq %r11, %rcx ; CHECK-NEXT: addq %rdx, %r12
; CHECK-NEXT: addq %rax, %rcx ; CHECK-NEXT: addq %rax, %rcx
; CHECK-NEXT: leaq (%rsi,%r15), %rbx
; CHECK-NEXT: leaq (%r12,%rbx), %rax ; CHECK-NEXT: leaq (%r12,%rbx), %rax
; CHECK-NEXT: addq %r10, %rcx
; CHECK-NEXT: leaq (%r12,%rsi), %rdx
; CHECK-NEXT: addq %rbx, %rax ; CHECK-NEXT: addq %rbx, %rax
; CHECK-NEXT: movq {{.*}}(%rip), %rbx ; CHECK-NEXT: movq {{.*}}(%rip), %rbx
; CHECK-NEXT: addq %r10, %rcx ; CHECK-NEXT: movq {{.*}}(%rip), %rdi
; CHECK-NEXT: addq %rcx, %r8 ; CHECK-NEXT: addq %rcx, %r8
; CHECK-NEXT: addq %r12, %rax ; CHECK-NEXT: addq %r12, %rax
; CHECK-NEXT: addq %rcx, %rax ; CHECK-NEXT: addq %rcx, %rax
; CHECK-NEXT: bswapq %rbx
; CHECK-NEXT: leaq (%r10,%r9), %rcx ; CHECK-NEXT: leaq (%r10,%r9), %rcx
; CHECK-NEXT: addq %r8, %rcx ; CHECK-NEXT: addq %r8, %rcx
; CHECK-NEXT: bswapq %rbx
; CHECK-NEXT: bswapq %rdi
; CHECK-NEXT: addq %r14, %rbx ; CHECK-NEXT: addq %r14, %rbx
; CHECK-NEXT: addq %r9, %rdi
; CHECK-NEXT: leaq (%rax,%r12), %r9
; CHECK-NEXT: addq %rcx, %rbx ; CHECK-NEXT: addq %rcx, %rbx
; CHECK-NEXT: leaq (%r12,%rsi), %rdx
; CHECK-NEXT: leaq (%rax,%rdx), %rcx ; CHECK-NEXT: leaq (%rax,%rdx), %rcx
; CHECK-NEXT: addq %rdx, %rcx ; CHECK-NEXT: addq %rdx, %rcx
; CHECK-NEXT: movq {{.*}}(%rip), %rdx
; CHECK-NEXT: addq %r8, %rbx ; CHECK-NEXT: addq %r8, %rbx
; CHECK-NEXT: addq %rbx, %r15
; CHECK-NEXT: addq %rax, %rcx ; CHECK-NEXT: addq %rax, %rcx
; CHECK-NEXT: bswapq %rdx ; CHECK-NEXT: addq %rbx, %r15
; CHECK-NEXT: addq %rbx, %rcx ; CHECK-NEXT: addq %rbx, %rcx
; CHECK-NEXT: leaq (%r8,%r10), %rbx ; CHECK-NEXT: leaq (%r8,%r10), %rbx
; CHECK-NEXT: leaq (%rcx,%r9), %r11
; CHECK-NEXT: addq %r15, %rbx ; CHECK-NEXT: addq %r15, %rbx
; CHECK-NEXT: addq %r9, %rdx ; CHECK-NEXT: addq %r9, %r11
; CHECK-NEXT: addq %rbx, %rdx ; CHECK-NEXT: movq {{.*}}(%rip), %r9
; CHECK-NEXT: leaq (%rax,%r12), %r9
; CHECK-NEXT: leaq (%rcx,%r9), %rbx
; CHECK-NEXT: addq %r9, %rbx
; CHECK-NEXT: addq %r15, %rdx
; CHECK-NEXT: addq %rdx, %rsi
; CHECK-NEXT: addq %rcx, %rbx
; CHECK-NEXT: addq %rdx, %rbx
; CHECK-NEXT: movq {{.*}}(%rip), %rdx
; CHECK-NEXT: bswapq %rdx
; CHECK-NEXT: addq %r10, %rdx
; CHECK-NEXT: leaq (%r15,%r8), %rdi
; CHECK-NEXT: addq %rsi, %rdi
; CHECK-NEXT: addq %rdi, %rdx
; CHECK-NEXT: addq %rax, %rcx
; CHECK-NEXT: leaq (%rbx,%rcx), %rdi
; CHECK-NEXT: addq %rcx, %rdi
; CHECK-NEXT: addq %rbx, %rdi ; CHECK-NEXT: addq %rbx, %rdi
; CHECK-NEXT: addq %rsi, %rdx ; CHECK-NEXT: addq %rcx, %r11
; CHECK-NEXT: addq %rdx, %r12 ; CHECK-NEXT: addq %rax, %rcx
; CHECK-NEXT: addq %rdx, %rdi
; CHECK-NEXT: addq %r15, %rsi
; CHECK-NEXT: movq {{.*}}(%rip), %rax ; CHECK-NEXT: movq {{.*}}(%rip), %rax
; CHECK-NEXT: addq %r15, %rdi
; CHECK-NEXT: addq %rdi, %rsi
; CHECK-NEXT: addq %rdi, %r11
; CHECK-NEXT: leaq (%r15,%r8), %rdi
; CHECK-NEXT: addq %rsi, %rdi
; CHECK-NEXT: bswapq %r9
; CHECK-NEXT: bswapq %rax ; CHECK-NEXT: bswapq %rax
; CHECK-NEXT: addq %r10, %r9
; CHECK-NEXT: addq %rdi, %r9
; CHECK-NEXT: leaq (%r11,%rcx), %rdi
; CHECK-NEXT: movq %rax, {{.*}}(%rip) ; CHECK-NEXT: movq %rax, {{.*}}(%rip)
; CHECK-NEXT: addq %r8, %rax ; CHECK-NEXT: addq %r8, %rax
; CHECK-NEXT: addq %rsi, %r9
; CHECK-NEXT: addq %r15, %rsi
; CHECK-NEXT: addq %rcx, %rdi
; CHECK-NEXT: addq %r9, %r12
; CHECK-NEXT: addq %r11, %rdi
; CHECK-NEXT: addq %r12, %rsi ; CHECK-NEXT: addq %r12, %rsi
; CHECK-NEXT: addq %r9, %rdi
; CHECK-NEXT: addq %rsi, %rax ; CHECK-NEXT: addq %rsi, %rax
; CHECK-NEXT: addq %r12, %rax ; CHECK-NEXT: addq %r12, %rax
; CHECK-NEXT: addq %rdi, %rax ; CHECK-NEXT: addq %rdi, %rax
; CHECK-NEXT: popq %rbx ; CHECK-NEXT: popq %rbx
; CHECK-NEXT: popq %r12 ; CHECK-NEXT: popq %r12
; CHECK-NEXT: popq %r14 ; CHECK-NEXT: popq %r14
; CHECK-NEXT: popq %r15 ; CHECK-NEXT: popq %r15
; CHECK-NEXT: retq ; CHECK-NEXT: retq
▲ Show 20 Lines • Show All 231 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll

; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=corei7 | FileCheck %s ; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=corei7 | FileCheck %s
; rdar://r7512579 ; rdar://r7512579
; PHI defs in the atomic loop should be used by the add / adc ; PHI defs in the atomic loop should be used by the add / adc
; instructions. They should not be dead. ; instructions. They should not be dead.
define void @t(i64* nocapture %p) nounwind ssp { define void @t(i64* nocapture %p) nounwind ssp {
entry: entry:
; CHECK-LABEL: t: ; CHECK-LABEL: t:
; CHECK: movl ([[REG:%[a-z]+]]), %eax ; CHECK: movl ([[REG:%[a-z]+]]), %eax
; CHECK: movl 4([[REG]]), %edx ; CHECK: movl 4([[REG]]), %edx
; CHECK: LBB0_1: ; CHECK: LBB0_1:
; CHECK: movl %eax, %ebx ; CHECK: movl %eax, %ebx
; CHECK: addl $1, %ebx
; CHECK: movl %edx, %ecx ; CHECK: movl %edx, %ecx
; CHECK: addl $1, %ebx
; CHECK: adcl $0, %ecx ; CHECK: adcl $0, %ecx
; CHECK: lock cmpxchg8b ([[REG]]) ; CHECK: lock cmpxchg8b ([[REG]])
; CHECK-NEXT: jne ; CHECK-NEXT: jne
%0 = atomicrmw add i64* %p, i64 1 seq_cst %0 = atomicrmw add i64* %p, i64 1 seq_cst
ret void ret void
} }

llvm/test/CodeGen/X86/2011-05-09-loaduse.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- -mcpu=corei7 | FileCheck %s --check-prefixes=CHECK,X86 ; RUN: llc < %s -mtriple=i686-- -mcpu=corei7 | FileCheck %s --check-prefixes=CHECK,X86
; RUN: llc < %s -mtriple=x86_64-- -mcpu=corei7 | FileCheck %s --check-prefixes=CHECK,X64 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=corei7 | FileCheck %s --check-prefixes=CHECK,X64
define float @test(<4 x float>* %A) nounwind { define float @test(<4 x float>* %A) nounwind {
; X86-LABEL: test: ; X86-LABEL: test:
; X86: # %bb.0: # %entry ; X86: # %bb.0: # %entry
; X86-NEXT: pushl %eax ; X86-NEXT: pushl %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movaps (%eax), %xmm0
; X86-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1,2,3]
; X86-NEXT: xorps %xmm1, %xmm1 ; X86-NEXT: xorps %xmm1, %xmm1
; X86-NEXT: movaps (%eax), %xmm0
; X86-NEXT: movaps %xmm1, (%eax) ; X86-NEXT: movaps %xmm1, (%eax)
; X86-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1,2,3]
; X86-NEXT: movss %xmm0, (%esp) ; X86-NEXT: movss %xmm0, (%esp)
; X86-NEXT: flds (%esp) ; X86-NEXT: flds (%esp)
; X86-NEXT: popl %eax ; X86-NEXT: popl %eax
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: test: ; X64-LABEL: test:
; X64: # %bb.0: # %entry ; X64: # %bb.0: # %entry
; X64-NEXT: movaps (%rdi), %xmm0 ; X64-NEXT: movaps (%rdi), %xmm0
; X64-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1,2,3]
; X64-NEXT: xorps %xmm1, %xmm1 ; X64-NEXT: xorps %xmm1, %xmm1
; X64-NEXT: movaps %xmm1, (%rdi) ; X64-NEXT: movaps %xmm1, (%rdi)
; X64-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1,2,3]
; X64-NEXT: retq ; X64-NEXT: retq
entry: entry:
%T = load <4 x float>, <4 x float>* %A %T = load <4 x float>, <4 x float>* %A
%R = extractelement <4 x float> %T, i32 3 %R = extractelement <4 x float> %T, i32 3
store <4 x float><float 0.0, float 0.0, float 0.0, float 0.0>, <4 x float>* %A store <4 x float><float 0.0, float 0.0, float 0.0, float 0.0>, <4 x float>* %A
ret float %R ret float %R
} }

llvm/test/CodeGen/X86/2011-10-19-LegelizeLoad.ll

Show All 14 Lines
; Based on /gcc-4_2-testsuite/src/gcc.c-torture/execute/pr23135.c ; Based on /gcc-4_2-testsuite/src/gcc.c-torture/execute/pr23135.c
define i32 @main() nounwind uwtable { define i32 @main() nounwind uwtable {
; CHECK-LABEL: main: ; CHECK-LABEL: main:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movq {{.*}}(%rip), %rsi ; CHECK-NEXT: movq {{.*}}(%rip), %rsi
; CHECK-NEXT: movq {{.*}}(%rip), %rax ; CHECK-NEXT: movq {{.*}}(%rip), %rax
; CHECK-NEXT: movq %rsi, %rdx ; CHECK-NEXT: movq %rsi, %rdx
; CHECK-NEXT: shrq $8, %rdx
; CHECK-NEXT: movsbl %al, %ecx ; CHECK-NEXT: movsbl %al, %ecx
; CHECK-NEXT: shrq $8, %rax ; CHECK-NEXT: shrq $8, %rax
; CHECK-NEXT: shrq $8, %rdx
; CHECK-NEXT: cbtw ; CHECK-NEXT: cbtw
; CHECK-NEXT: idivb %dl ; CHECK-NEXT: idivb %dl
; CHECK-NEXT: movl %eax, %edx ; CHECK-NEXT: movl %eax, %edx
; CHECK-NEXT: movl %ecx, %eax ; CHECK-NEXT: movl %ecx, %eax
; CHECK-NEXT: idivb %sil ; CHECK-NEXT: idivb %sil
; CHECK-NEXT: movzbl %dl, %ecx ; CHECK-NEXT: movzbl %dl, %ecx
; CHECK-NEXT: movzbl %al, %eax ; CHECK-NEXT: movzbl %al, %eax
; CHECK-NEXT: movd %eax, %xmm0 ; CHECK-NEXT: movd %eax, %xmm0
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: pinsrb $1, %ecx, %xmm0 ; CHECK-NEXT: pinsrb $1, %ecx, %xmm0
; CHECK-NEXT: pextrw $0, %xmm0, {{.*}}(%rip) ; CHECK-NEXT: pextrw $0, %xmm0, {{.*}}(%rip)
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
entry: entry:
%0 = load <2 x i8>, <2 x i8>* @i, align 8 %0 = load <2 x i8>, <2 x i8>* @i, align 8
%1 = load <2 x i8>, <2 x i8>* @j, align 8 %1 = load <2 x i8>, <2 x i8>* @j, align 8
%div = sdiv <2 x i8> %1, %0 %div = sdiv <2 x i8> %1, %0
store <2 x i8> %div, <2 x i8>* getelementptr inbounds (%union.anon, %union.anon* @res, i32 0, i32 0), align 8 store <2 x i8> %div, <2 x i8>* getelementptr inbounds (%union.anon, %union.anon* @res, i32 0, i32 0), align 8
ret i32 0 ret i32 0
} }

llvm/test/CodeGen/X86/2011-10-19-widen_vselect.ll

Show All 18 Linesentry:
%0 = select <2 x i1> undef, <2 x float> %a, <2 x float> %b %0 = select <2 x i1> undef, <2 x float> %a, <2 x float> %b
store <2 x float> %0, <2 x float>* undef store <2 x float> %0, <2 x float>* undef
ret void ret void
} }
define void @complex_inreg_work(<2 x float> %a, <2 x float> %b, <2 x float> %c) { define void @complex_inreg_work(<2 x float> %a, <2 x float> %b, <2 x float> %c) {
; X32-LABEL: complex_inreg_work: ; X32-LABEL: complex_inreg_work:
; X32: # %bb.0: # %entry ; X32: # %bb.0: # %entry
; X32-NEXT: movaps %xmm0, %xmm3
; X32-NEXT: cmpordps %xmm2, %xmm2 ; X32-NEXT: cmpordps %xmm2, %xmm2
; X32-NEXT: movaps %xmm0, %xmm3
; X32-NEXT: movaps %xmm2, %xmm0 ; X32-NEXT: movaps %xmm2, %xmm0
; X32-NEXT: blendvps %xmm0, %xmm3, %xmm1 ; X32-NEXT: blendvps %xmm0, %xmm3, %xmm1
; X32-NEXT: movlps %xmm1, (%eax) ; X32-NEXT: movlps %xmm1, (%eax)
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: complex_inreg_work: ; X64-LABEL: complex_inreg_work:
; X64: # %bb.0: # %entry ; X64: # %bb.0: # %entry
; X64-NEXT: movaps %xmm0, %xmm3
; X64-NEXT: cmpordps %xmm2, %xmm2 ; X64-NEXT: cmpordps %xmm2, %xmm2
; X64-NEXT: movaps %xmm0, %xmm3
; X64-NEXT: movaps %xmm2, %xmm0 ; X64-NEXT: movaps %xmm2, %xmm0
; X64-NEXT: blendvps %xmm0, %xmm3, %xmm1 ; X64-NEXT: blendvps %xmm0, %xmm3, %xmm1
; X64-NEXT: movlps %xmm1, (%rax) ; X64-NEXT: movlps %xmm1, (%rax)
; X64-NEXT: retq ; X64-NEXT: retq
entry: entry:
%0 = fcmp oeq <2 x float> %c, %c %0 = fcmp oeq <2 x float> %c, %c
%1 = select <2 x i1> %0, <2 x float> %a, <2 x float> %b %1 = select <2 x i1> %0, <2 x float> %a, <2 x float> %b
store <2 x float> %1, <2 x float>* undef store <2 x float> %1, <2 x float>* undef
Show All 19 Lines
} }
define void @full_test() { define void @full_test() {
; X32-LABEL: full_test: ; X32-LABEL: full_test:
; X32: # %bb.0: # %entry ; X32: # %bb.0: # %entry
; X32-NEXT: subl $60, %esp ; X32-NEXT: subl $60, %esp
; X32-NEXT: .cfi_def_cfa_offset 64 ; X32-NEXT: .cfi_def_cfa_offset 64
; X32-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero ; X32-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
; X32-NEXT: movaps {{.*#+}} xmm3 = <1.0E+0,1.0E+0,u,u>
; X32-NEXT: cvttps2dq %xmm2, %xmm0 ; X32-NEXT: cvttps2dq %xmm2, %xmm0
; X32-NEXT: cvtdq2ps %xmm0, %xmm1 ; X32-NEXT: cvtdq2ps %xmm0, %xmm1
; X32-NEXT: xorps %xmm0, %xmm0 ; X32-NEXT: xorps %xmm0, %xmm0
; X32-NEXT: cmpltps %xmm2, %xmm0 ; X32-NEXT: cmpltps %xmm2, %xmm0
; X32-NEXT: movaps {{.*#+}} xmm3 = <1.0E+0,1.0E+0,u,u>
; X32-NEXT: addps %xmm1, %xmm3 ; X32-NEXT: addps %xmm1, %xmm3
; X32-NEXT: movaps %xmm1, %xmm4 ; X32-NEXT: movaps %xmm1, %xmm4
; X32-NEXT: blendvps %xmm0, %xmm3, %xmm4
; X32-NEXT: cmpeqps %xmm2, %xmm1 ; X32-NEXT: cmpeqps %xmm2, %xmm1
; X32-NEXT: blendvps %xmm0, %xmm3, %xmm4
; X32-NEXT: movaps %xmm1, %xmm0 ; X32-NEXT: movaps %xmm1, %xmm0
; X32-NEXT: blendvps %xmm0, %xmm2, %xmm4 ; X32-NEXT: blendvps %xmm0, %xmm2, %xmm4
; X32-NEXT: movlps %xmm4, {{[0-9]+}}(%esp) ; X32-NEXT: movlps %xmm4, {{[0-9]+}}(%esp)
; X32-NEXT: movlps %xmm4, {{[0-9]+}}(%esp) ; X32-NEXT: movlps %xmm4, {{[0-9]+}}(%esp)
; X32-NEXT: addl $60, %esp ; X32-NEXT: addl $60, %esp
; X32-NEXT: .cfi_def_cfa_offset 4 ; X32-NEXT: .cfi_def_cfa_offset 4
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: full_test: ; X64-LABEL: full_test:
; X64: # %bb.0: # %entry ; X64: # %bb.0: # %entry
; X64-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero ; X64-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
; X64-NEXT: movaps {{.*#+}} xmm3 = <1.0E+0,1.0E+0,u,u>
; X64-NEXT: cvttps2dq %xmm2, %xmm0 ; X64-NEXT: cvttps2dq %xmm2, %xmm0
; X64-NEXT: cvtdq2ps %xmm0, %xmm1 ; X64-NEXT: cvtdq2ps %xmm0, %xmm1
; X64-NEXT: xorps %xmm0, %xmm0 ; X64-NEXT: xorps %xmm0, %xmm0
; X64-NEXT: cmpltps %xmm2, %xmm0 ; X64-NEXT: cmpltps %xmm2, %xmm0
; X64-NEXT: movaps {{.*#+}} xmm3 = <1.0E+0,1.0E+0,u,u>
; X64-NEXT: addps %xmm1, %xmm3 ; X64-NEXT: addps %xmm1, %xmm3
; X64-NEXT: movaps %xmm1, %xmm4 ; X64-NEXT: movaps %xmm1, %xmm4
; X64-NEXT: blendvps %xmm0, %xmm3, %xmm4
; X64-NEXT: cmpeqps %xmm2, %xmm1 ; X64-NEXT: cmpeqps %xmm2, %xmm1
; X64-NEXT: blendvps %xmm0, %xmm3, %xmm4
; X64-NEXT: movaps %xmm1, %xmm0 ; X64-NEXT: movaps %xmm1, %xmm0
; X64-NEXT: blendvps %xmm0, %xmm2, %xmm4 ; X64-NEXT: blendvps %xmm0, %xmm2, %xmm4
; X64-NEXT: movlps %xmm4, -{{[0-9]+}}(%rsp) ; X64-NEXT: movlps %xmm4, -{{[0-9]+}}(%rsp)
; X64-NEXT: movlps %xmm4, -{{[0-9]+}}(%rsp) ; X64-NEXT: movlps %xmm4, -{{[0-9]+}}(%rsp)
; X64-NEXT: retq ; X64-NEXT: retq
entry: entry:
%Cy300 = alloca <4 x float> %Cy300 = alloca <4 x float>
%Cy11a = alloca <2 x float> %Cy11a = alloca <2 x float>
Show All 18 Lines

llvm/test/CodeGen/X86/2011-10-21-widen-cmp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 | FileCheck %s
; Check that a <4 x float> compare is generated and that we are ; Check that a <4 x float> compare is generated and that we are
; not stuck in an endless loop. ; not stuck in an endless loop.
define void @cmp_2_floats(<2 x float> %a, <2 x float> %b, <2 x float> %c) { define void @cmp_2_floats(<2 x float> %a, <2 x float> %b, <2 x float> %c) {
; CHECK-LABEL: cmp_2_floats: ; CHECK-LABEL: cmp_2_floats:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movaps %xmm0, %xmm3
; CHECK-NEXT: cmpordps %xmm2, %xmm2 ; CHECK-NEXT: cmpordps %xmm2, %xmm2
; CHECK-NEXT: movaps %xmm0, %xmm3
; CHECK-NEXT: movaps %xmm2, %xmm0 ; CHECK-NEXT: movaps %xmm2, %xmm0
; CHECK-NEXT: blendvps %xmm0, %xmm3, %xmm1 ; CHECK-NEXT: blendvps %xmm0, %xmm3, %xmm1
; CHECK-NEXT: movlps %xmm1, (%rax) ; CHECK-NEXT: movlps %xmm1, (%rax)
; CHECK-NEXT: retq ; CHECK-NEXT: retq
entry: entry:
%0 = fcmp oeq <2 x float> %c, %c %0 = fcmp oeq <2 x float> %c, %c
%1 = select <2 x i1> %0, <2 x float> %a, <2 x float> %b %1 = select <2 x i1> %0, <2 x float> %a, <2 x float> %b
store <2 x float> %1, <2 x float>* undef store <2 x float> %1, <2 x float>* undef
ret void ret void
} }
define void @cmp_2_doubles(<2 x double> %a, <2 x double> %b, <2 x double> %c) { define void @cmp_2_doubles(<2 x double> %a, <2 x double> %b, <2 x double> %c) {
; CHECK-LABEL: cmp_2_doubles: ; CHECK-LABEL: cmp_2_doubles:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movapd %xmm0, %xmm3
; CHECK-NEXT: cmpordpd %xmm2, %xmm2 ; CHECK-NEXT: cmpordpd %xmm2, %xmm2
; CHECK-NEXT: movapd %xmm0, %xmm3
; CHECK-NEXT: movapd %xmm2, %xmm0 ; CHECK-NEXT: movapd %xmm2, %xmm0
; CHECK-NEXT: blendvpd %xmm0, %xmm3, %xmm1 ; CHECK-NEXT: blendvpd %xmm0, %xmm3, %xmm1
; CHECK-NEXT: movapd %xmm1, (%rax) ; CHECK-NEXT: movapd %xmm1, (%rax)
; CHECK-NEXT: retq ; CHECK-NEXT: retq
entry: entry:
%0 = fcmp oeq <2 x double> %c, %c %0 = fcmp oeq <2 x double> %c, %c
%1 = select <2 x i1> %0, <2 x double> %a, <2 x double> %b %1 = select <2 x i1> %0, <2 x double> %a, <2 x double> %b
store <2 x double> %1, <2 x double>* undef store <2 x double> %1, <2 x double>* undef
Show All 17 Lines

llvm/test/CodeGen/X86/2011-12-28-vselecti8.ll

Show All 13 Lines
; ;
; Make sure that the sign_extend_inreg is simplified and that we ; Make sure that the sign_extend_inreg is simplified and that we
; don't generate psll, psraw and pblendvb from the vselect. ; don't generate psll, psraw and pblendvb from the vselect.
define void @foo8(float* nocapture %RET) nounwind { define void @foo8(float* nocapture %RET) nounwind {
; CHECK-LABEL: foo8: ; CHECK-LABEL: foo8:
; CHECK: ## %bb.0: ## %allocas ; CHECK: ## %bb.0: ## %allocas
; CHECK-NEXT: pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero ; CHECK-NEXT: pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
; CHECK-NEXT: cvtdq2ps %xmm0, %xmm0
; CHECK-NEXT: movaps {{.*#+}} xmm1 = [1.0E+2,2.0E+0,1.0E+2,4.0E+0] ; CHECK-NEXT: movaps {{.*#+}} xmm1 = [1.0E+2,2.0E+0,1.0E+2,4.0E+0]
; CHECK-NEXT: movups %xmm1, (%rdi) ; CHECK-NEXT: movups %xmm1, (%rdi)
; CHECK-NEXT: cvtdq2ps %xmm0, %xmm0
; CHECK-NEXT: movups %xmm0, 16(%rdi) ; CHECK-NEXT: movups %xmm0, 16(%rdi)
; CHECK-NEXT: retq ; CHECK-NEXT: retq
allocas: allocas:
%resultvec.i = select <8 x i1> <i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true>, <8 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, <8 x i8> <i8 100, i8 100, i8 100, i8 100, i8 100, i8 100, i8 100, i8 100> %resultvec.i = select <8 x i1> <i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true>, <8 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, <8 x i8> <i8 100, i8 100, i8 100, i8 100, i8 100, i8 100, i8 100, i8 100>
%uint2float = uitofp <8 x i8> %resultvec.i to <8 x float> %uint2float = uitofp <8 x i8> %resultvec.i to <8 x float>
%ptr = bitcast float * %RET to <8 x float> * %ptr = bitcast float * %RET to <8 x float> *
store <8 x float> %uint2float, <8 x float>* %ptr, align 4 store <8 x float> %uint2float, <8 x float>* %ptr, align 4
ret void ret void
} }

llvm/test/CodeGen/X86/2012-11-28-merge-store-alias.ll

; RUN: llc < %s -mcpu=corei7 -mtriple=x86_64-pc-win64 | FileCheck %s ; RUN: llc < %s -mcpu=corei7 -mtriple=x86_64-pc-win64 | FileCheck %s
; CHECK: merge_stores_can ; CHECK: merge_stores_can
; CHECK: callq foo ; CHECK: callq foo
; CHECK: xorps %xmm0, %xmm0 ; CHECK: xorps %xmm0, %xmm0
; CHECK-NEXT: movups %xmm0 ; CHECK-NEXT: movups %xmm0
; CHECK-NEXT: movl 36(%rsp), %ebp ; CHECK: movl 36(%rsp), %ebp
; CHECK: callq foo ; CHECK: callq foo
; CHECK: ret ; CHECK: ret
declare i32 @foo([10 x i32]* ) declare i32 @foo([10 x i32]* )
define i32 @merge_stores_can() nounwind ssp { define i32 @merge_stores_can() nounwind ssp {
%object1 = alloca [10 x i32] %object1 = alloca [10 x i32]
%ret0 = call i32 @foo([10 x i32]* %object1) nounwind %ret0 = call i32 @foo([10 x i32]* %object1) nounwind
Show All 38 Lines

llvm/test/CodeGen/X86/GlobalISel/add-vec.ll

Show First 20 Lines • Show All 49 Lines • ▼ Show 20 Lines
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpaddb %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpaddb %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX1-LABEL: test_add_v32i8: ; AVX1-LABEL: test_add_v32i8:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
; AVX1-NEXT: vpaddb %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vpaddb %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vpaddb %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpaddb %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
%ret = add <32 x i8> %arg1, %arg2 %ret = add <32 x i8> %arg1, %arg2
ret <32 x i8> %ret ret <32 x i8> %ret
} }
define <16 x i16> @test_add_v16i16(<16 x i16> %arg1, <16 x i16> %arg2) { define <16 x i16> @test_add_v16i16(<16 x i16> %arg1, <16 x i16> %arg2) {
; SKX-LABEL: test_add_v16i16: ; SKX-LABEL: test_add_v16i16:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vpaddw %ymm1, %ymm0, %ymm0 ; SKX-NEXT: vpaddw %ymm1, %ymm0, %ymm0
; SKX-NEXT: retq ; SKX-NEXT: retq
; ;
; AVX2-LABEL: test_add_v16i16: ; AVX2-LABEL: test_add_v16i16:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpaddw %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpaddw %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX1-LABEL: test_add_v16i16: ; AVX1-LABEL: test_add_v16i16:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
; AVX1-NEXT: vpaddw %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vpaddw %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vpaddw %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpaddw %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
%ret = add <16 x i16> %arg1, %arg2 %ret = add <16 x i16> %arg1, %arg2
ret <16 x i16> %ret ret <16 x i16> %ret
} }
define <8 x i32> @test_add_v8i32(<8 x i32> %arg1, <8 x i32> %arg2) { define <8 x i32> @test_add_v8i32(<8 x i32> %arg1, <8 x i32> %arg2) {
; SKX-LABEL: test_add_v8i32: ; SKX-LABEL: test_add_v8i32:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vpaddd %ymm1, %ymm0, %ymm0 ; SKX-NEXT: vpaddd %ymm1, %ymm0, %ymm0
; SKX-NEXT: retq ; SKX-NEXT: retq
; ;
; AVX2-LABEL: test_add_v8i32: ; AVX2-LABEL: test_add_v8i32:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpaddd %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpaddd %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX1-LABEL: test_add_v8i32: ; AVX1-LABEL: test_add_v8i32:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
; AVX1-NEXT: vpaddd %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpaddd %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
%ret = add <8 x i32> %arg1, %arg2 %ret = add <8 x i32> %arg1, %arg2
ret <8 x i32> %ret ret <8 x i32> %ret
} }
define <4 x i64> @test_add_v4i64(<4 x i64> %arg1, <4 x i64> %arg2) { define <4 x i64> @test_add_v4i64(<4 x i64> %arg1, <4 x i64> %arg2) {
; SKX-LABEL: test_add_v4i64: ; SKX-LABEL: test_add_v4i64:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vpaddq %ymm1, %ymm0, %ymm0 ; SKX-NEXT: vpaddq %ymm1, %ymm0, %ymm0
; SKX-NEXT: retq ; SKX-NEXT: retq
; ;
; AVX2-LABEL: test_add_v4i64: ; AVX2-LABEL: test_add_v4i64:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpaddq %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpaddq %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX1-LABEL: test_add_v4i64: ; AVX1-LABEL: test_add_v4i64:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
; AVX1-NEXT: vpaddq %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vpaddq %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vpaddq %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vpaddq %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
%ret = add <4 x i64> %arg1, %arg2 %ret = add <4 x i64> %arg1, %arg2
ret <4 x i64> %ret ret <4 x i64> %ret
} }
define <64 x i8> @test_add_v64i8(<64 x i8> %arg1, <64 x i8> %arg2) { define <64 x i8> @test_add_v64i8(<64 x i8> %arg1, <64 x i8> %arg2) {
; SKX-LABEL: test_add_v64i8: ; SKX-LABEL: test_add_v64i8:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vpaddb %zmm1, %zmm0, %zmm0 ; SKX-NEXT: vpaddb %zmm1, %zmm0, %zmm0
; SKX-NEXT: retq ; SKX-NEXT: retq
; ;
; AVX2-LABEL: test_add_v64i8: ; AVX2-LABEL: test_add_v64i8:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpaddb %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpaddb %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpaddb %ymm3, %ymm1, %ymm1 ; AVX2-NEXT: vpaddb %ymm3, %ymm1, %ymm1
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX1-LABEL: test_add_v64i8: ; AVX1-LABEL: test_add_v64i8:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm4 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm4
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm5 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm5
; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm6 ; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm6
; AVX1-NEXT: vpaddb %xmm6, %xmm4, %xmm4 ; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm7
; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm6
; AVX1-NEXT: vpaddb %xmm6, %xmm5, %xmm5
; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0 ; AVX1-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpaddb %xmm3, %xmm1, %xmm1 ; AVX1-NEXT: vpaddb %xmm3, %xmm1, %xmm1
; AVX1-NEXT: vpaddb %xmm6, %xmm4, %xmm4
; AVX1-NEXT: vpaddb %xmm7, %xmm5, %xmm5
; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0
; AVX1-NEXT: vinsertf128 $1, %xmm5, %ymm1, %ymm1 ; AVX1-NEXT: vinsertf128 $1, %xmm5, %ymm1, %ymm1
; AVX1-NEXT: retq ; AVX1-NEXT: retq
%ret = add <64 x i8> %arg1, %arg2 %ret = add <64 x i8> %arg1, %arg2
ret <64 x i8> %ret ret <64 x i8> %ret
} }
define <32 x i16> @test_add_v32i16(<32 x i16> %arg1, <32 x i16> %arg2) { define <32 x i16> @test_add_v32i16(<32 x i16> %arg1, <32 x i16> %arg2) {
; SKX-LABEL: test_add_v32i16: ; SKX-LABEL: test_add_v32i16:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vpaddw %zmm1, %zmm0, %zmm0 ; SKX-NEXT: vpaddw %zmm1, %zmm0, %zmm0
; SKX-NEXT: retq ; SKX-NEXT: retq
; ;
; AVX2-LABEL: test_add_v32i16: ; AVX2-LABEL: test_add_v32i16:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpaddw %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpaddw %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpaddw %ymm3, %ymm1, %ymm1 ; AVX2-NEXT: vpaddw %ymm3, %ymm1, %ymm1
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX1-LABEL: test_add_v32i16: ; AVX1-LABEL: test_add_v32i16:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm4 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm4
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm5 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm5
; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm6 ; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm6
; AVX1-NEXT: vpaddw %xmm6, %xmm4, %xmm4 ; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm7
; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm6
; AVX1-NEXT: vpaddw %xmm6, %xmm5, %xmm5
; AVX1-NEXT: vpaddw %xmm2, %xmm0, %xmm0 ; AVX1-NEXT: vpaddw %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpaddw %xmm3, %xmm1, %xmm1 ; AVX1-NEXT: vpaddw %xmm3, %xmm1, %xmm1
; AVX1-NEXT: vpaddw %xmm6, %xmm4, %xmm4
; AVX1-NEXT: vpaddw %xmm7, %xmm5, %xmm5
; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0
; AVX1-NEXT: vinsertf128 $1, %xmm5, %ymm1, %ymm1 ; AVX1-NEXT: vinsertf128 $1, %xmm5, %ymm1, %ymm1
; AVX1-NEXT: retq ; AVX1-NEXT: retq
%ret = add <32 x i16> %arg1, %arg2 %ret = add <32 x i16> %arg1, %arg2
ret <32 x i16> %ret ret <32 x i16> %ret
} }
define <16 x i32> @test_add_v16i32(<16 x i32> %arg1, <16 x i32> %arg2) { define <16 x i32> @test_add_v16i32(<16 x i32> %arg1, <16 x i32> %arg2) {
; SKX-LABEL: test_add_v16i32: ; SKX-LABEL: test_add_v16i32:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vpaddd %zmm1, %zmm0, %zmm0 ; SKX-NEXT: vpaddd %zmm1, %zmm0, %zmm0
; SKX-NEXT: retq ; SKX-NEXT: retq
; ;
; AVX2-LABEL: test_add_v16i32: ; AVX2-LABEL: test_add_v16i32:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpaddd %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpaddd %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpaddd %ymm3, %ymm1, %ymm1 ; AVX2-NEXT: vpaddd %ymm3, %ymm1, %ymm1
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX1-LABEL: test_add_v16i32: ; AVX1-LABEL: test_add_v16i32:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm4 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm4
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm5 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm5
; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm6 ; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm6
; AVX1-NEXT: vpaddd %xmm6, %xmm4, %xmm4 ; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm7
; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm6
; AVX1-NEXT: vpaddd %xmm6, %xmm5, %xmm5
; AVX1-NEXT: vpaddd %xmm2, %xmm0, %xmm0 ; AVX1-NEXT: vpaddd %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpaddd %xmm3, %xmm1, %xmm1 ; AVX1-NEXT: vpaddd %xmm3, %xmm1, %xmm1
; AVX1-NEXT: vpaddd %xmm6, %xmm4, %xmm4
; AVX1-NEXT: vpaddd %xmm7, %xmm5, %xmm5
; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0
; AVX1-NEXT: vinsertf128 $1, %xmm5, %ymm1, %ymm1 ; AVX1-NEXT: vinsertf128 $1, %xmm5, %ymm1, %ymm1
; AVX1-NEXT: retq ; AVX1-NEXT: retq
%ret = add <16 x i32> %arg1, %arg2 %ret = add <16 x i32> %arg1, %arg2
ret <16 x i32> %ret ret <16 x i32> %ret
} }
define <8 x i64> @test_add_v8i64(<8 x i64> %arg1, <8 x i64> %arg2) { define <8 x i64> @test_add_v8i64(<8 x i64> %arg1, <8 x i64> %arg2) {
; SKX-LABEL: test_add_v8i64: ; SKX-LABEL: test_add_v8i64:
; SKX: # %bb.0: ; SKX: # %bb.0:
; SKX-NEXT: vpaddq %zmm1, %zmm0, %zmm0 ; SKX-NEXT: vpaddq %zmm1, %zmm0, %zmm0
; SKX-NEXT: retq ; SKX-NEXT: retq
; ;
; AVX2-LABEL: test_add_v8i64: ; AVX2-LABEL: test_add_v8i64:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpaddq %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpaddq %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpaddq %ymm3, %ymm1, %ymm1 ; AVX2-NEXT: vpaddq %ymm3, %ymm1, %ymm1
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX1-LABEL: test_add_v8i64: ; AVX1-LABEL: test_add_v8i64:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm4 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm4
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm5 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm5
; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm6 ; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm6
; AVX1-NEXT: vpaddq %xmm6, %xmm4, %xmm4 ; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm7
; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm6
; AVX1-NEXT: vpaddq %xmm6, %xmm5, %xmm5
; AVX1-NEXT: vpaddq %xmm2, %xmm0, %xmm0 ; AVX1-NEXT: vpaddq %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vpaddq %xmm3, %xmm1, %xmm1 ; AVX1-NEXT: vpaddq %xmm3, %xmm1, %xmm1
; AVX1-NEXT: vpaddq %xmm6, %xmm4, %xmm4
; AVX1-NEXT: vpaddq %xmm7, %xmm5, %xmm5
; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0
; AVX1-NEXT: vinsertf128 $1, %xmm5, %ymm1, %ymm1 ; AVX1-NEXT: vinsertf128 $1, %xmm5, %ymm1, %ymm1
; AVX1-NEXT: retq ; AVX1-NEXT: retq
%ret = add <8 x i64> %arg1, %arg2 %ret = add <8 x i64> %arg1, %arg2
ret <8 x i64> %ret ret <8 x i64> %ret
} }

llvm/test/CodeGen/X86/atom-sched.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -O2 -mcpu=atom -mtriple=i686-- -relocation-model=static | FileCheck -check-prefix=atom %s ; RUN: llc < %s -O2 -mcpu=atom -mtriple=i686-- -relocation-model=static | FileCheck -check-prefix=atom %s
; RUN: llc < %s -O2 -mcpu=slm -mtriple=i686-- -relocation-model=static | FileCheck -check-prefix=slm %s ; RUN: llc < %s -O2 -mcpu=slm -mtriple=i686-- -relocation-model=static | FileCheck -check-prefix=slm %s
; RUN: llc < %s -O2 -mcpu=goldmont -mtriple=i686-- -relocation-model=static | FileCheck -check-prefix=slm %s ; RUN: llc < %s -O2 -mcpu=goldmont -mtriple=i686-- -relocation-model=static | FileCheck -check-prefix=slm %s
; RUN: llc < %s -O2 -mcpu=core2 -mtriple=i686-- -relocation-model=static | FileCheck %s ; RUN: llc < %s -O2 -mcpu=core2 -mtriple=i686-- -relocation-model=static | FileCheck %s
; ;
@a = common global i32 0, align 4 @a = common global i32 0, align 4
@b = common global i32 0, align 4 @b = common global i32 0, align 4
@c = common global i32 0, align 4 @c = common global i32 0, align 4
@d = common global i32 0, align 4 @d = common global i32 0, align 4
@e = common global i32 0, align 4 @e = common global i32 0, align 4
@f = common global i32 0, align 4 @f = common global i32 0, align 4
define void @func() nounwind uwtable { define void @func() nounwind uwtable {
; atom: imull ; atom-LABEL: func:
; atom-NOT: movl ; atom: # %bb.0: # %entry
; atom: imull ; atom-NEXT: movl b, %eax
; slm: imull ; atom-NEXT: movl e, %ecx
; slm-NOT: movl ; atom-NEXT: imull c, %eax
; slm: imull ; atom-NEXT: imull f, %ecx
; CHECK: imull ; atom-NEXT: movl %eax, a
; CHECK: movl ; atom-NEXT: movl %ecx, d
; CHECK: imull ; atom-NEXT: retl
;
; slm-LABEL: func:
; slm: # %bb.0: # %entry
; slm-NEXT: movl b, %eax
; slm-NEXT: movl e, %ecx
; slm-NEXT: imull c, %eax
; slm-NEXT: imull f, %ecx
; slm-NEXT: movl %eax, a
; slm-NEXT: movl %ecx, d
; slm-NEXT: retl
;
; CHECK-LABEL: func:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl b, %eax
; CHECK-NEXT: movl e, %ecx
; CHECK-NEXT: imull c, %eax
; CHECK-NEXT: imull f, %ecx
; CHECK-NEXT: movl %eax, a
; CHECK-NEXT: movl %ecx, d
; CHECK-NEXT: retl
entry: entry:
%0 = load i32, i32* @b, align 4 %0 = load i32, i32* @b, align 4
%1 = load i32, i32* @c, align 4 %1 = load i32, i32* @c, align 4
%mul = mul nsw i32 %0, %1 %mul = mul nsw i32 %0, %1
store i32 %mul, i32* @a, align 4 store i32 %mul, i32* @a, align 4
%2 = load i32, i32* @e, align 4 %2 = load i32, i32* @e, align 4
%3 = load i32, i32* @f, align 4 %3 = load i32, i32* @f, align 4
%mul1 = mul nsw i32 %2, %3 %mul1 = mul nsw i32 %2, %3
store i32 %mul1, i32* @d, align 4 store i32 %mul1, i32* @d, align 4
ret void ret void
} }

llvm/test/CodeGen/X86/atomic-load-store-wide.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mcpu=corei7 -mtriple=i686-- -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=SSE42 ; RUN: llc < %s -mcpu=corei7 -mtriple=i686-- -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=SSE42
; RUN: llc < %s -mtriple=i686-- -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=NOSSE ; RUN: llc < %s -mtriple=i686-- -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=NOSSE
; 64-bit load/store on x86-32 ; 64-bit load/store on x86-32
; FIXME: The generated code can be substantially improved. ; FIXME: The generated code can be substantially improved.
define void @test1(i64* %ptr, i64 %val1) { define void @test1(i64* %ptr, i64 %val1) {
; SSE42-LABEL: test1: ; SSE42-LABEL: test1:
; SSE42: # %bb.0: ; SSE42: # %bb.0:
; SSE42-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE42-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; SSE42-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; SSE42-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE42-NEXT: movlps %xmm0, (%eax) ; SSE42-NEXT: movlps %xmm0, (%eax)
; SSE42-NEXT: lock orl $0, (%esp) ; SSE42-NEXT: lock orl $0, (%esp)
; SSE42-NEXT: retl ; SSE42-NEXT: retl
; ;
; NOSSE-LABEL: test1: ; NOSSE-LABEL: test1:
; NOSSE: # %bb.0: ; NOSSE: # %bb.0:
; NOSSE-NEXT: pushl %ebp ; NOSSE-NEXT: pushl %ebp
; NOSSE-NEXT: .cfi_def_cfa_offset 8 ; NOSSE-NEXT: .cfi_def_cfa_offset 8
Show All 18 Lines; NOSSE-NEXT: retl
ret void ret void
} }
define i64 @test2(i64* %ptr) { define i64 @test2(i64* %ptr) {
; SSE42-LABEL: test2: ; SSE42-LABEL: test2:
; SSE42: # %bb.0: ; SSE42: # %bb.0:
; SSE42-NEXT: movl {{[0-9]+}}(%esp), %eax ; SSE42-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE42-NEXT: movq {{.*#+}} xmm0 = mem[0],zero ; SSE42-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
; SSE42-NEXT: movd %xmm0, %eax
; SSE42-NEXT: pextrd $1, %xmm0, %edx ; SSE42-NEXT: pextrd $1, %xmm0, %edx
; SSE42-NEXT: movd %xmm0, %eax
; SSE42-NEXT: retl ; SSE42-NEXT: retl
; ;
; NOSSE-LABEL: test2: ; NOSSE-LABEL: test2:
; NOSSE: # %bb.0: ; NOSSE: # %bb.0:
; NOSSE-NEXT: pushl %ebp ; NOSSE-NEXT: pushl %ebp
; NOSSE-NEXT: .cfi_def_cfa_offset 8 ; NOSSE-NEXT: .cfi_def_cfa_offset 8
; NOSSE-NEXT: .cfi_offset %ebp, -8 ; NOSSE-NEXT: .cfi_offset %ebp, -8
; NOSSE-NEXT: movl %esp, %ebp ; NOSSE-NEXT: movl %esp, %ebp
Show All 38 Lines; CHECK-NEXT: retl
ret i64 %val ret i64 %val
} }
define i64 @test4(i64* %ptr) { define i64 @test4(i64* %ptr) {
; SSE42-LABEL: test4: ; SSE42-LABEL: test4:
; SSE42: # %bb.0: ; SSE42: # %bb.0:
; SSE42-NEXT: movl {{[0-9]+}}(%esp), %eax ; SSE42-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE42-NEXT: movq {{.*#+}} xmm0 = mem[0],zero ; SSE42-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
; SSE42-NEXT: movd %xmm0, %eax
; SSE42-NEXT: pextrd $1, %xmm0, %edx ; SSE42-NEXT: pextrd $1, %xmm0, %edx
; SSE42-NEXT: movd %xmm0, %eax
; SSE42-NEXT: retl ; SSE42-NEXT: retl
; ;
; NOSSE-LABEL: test4: ; NOSSE-LABEL: test4:
; NOSSE: # %bb.0: ; NOSSE: # %bb.0:
; NOSSE-NEXT: pushl %ebp ; NOSSE-NEXT: pushl %ebp
; NOSSE-NEXT: .cfi_def_cfa_offset 8 ; NOSSE-NEXT: .cfi_def_cfa_offset 8
; NOSSE-NEXT: .cfi_offset %ebp, -8 ; NOSSE-NEXT: .cfi_offset %ebp, -8
; NOSSE-NEXT: movl %esp, %ebp ; NOSSE-NEXT: movl %esp, %ebp
Show All 15 Lines

llvm/test/CodeGen/X86/avoid-sfb-overlaps.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-linux -mcpu=x86-64 -verify-machineinstrs | FileCheck %s -check-prefix=CHECK ; RUN: llc < %s -mtriple=x86_64-linux -mcpu=x86-64 -verify-machineinstrs | FileCheck %s -check-prefix=CHECK
; RUN: llc < %s -mtriple=x86_64-linux -mcpu=x86-64 --x86-disable-avoid-SFB -verify-machineinstrs | FileCheck %s --check-prefix=DISABLED ; RUN: llc < %s -mtriple=x86_64-linux -mcpu=x86-64 --x86-disable-avoid-SFB -verify-machineinstrs | FileCheck %s --check-prefix=DISABLED
; RUN: llc < %s -mtriple=x86_64-linux -mcpu=core-avx2 -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-AVX2 ; RUN: llc < %s -mtriple=x86_64-linux -mcpu=core-avx2 -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-AVX2
; RUN: llc < %s -mtriple=x86_64-linux -mcpu=skx -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-AVX512 ; RUN: llc < %s -mtriple=x86_64-linux -mcpu=skx -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-AVX512
; ModuleID = '../testSFB/testOverlapBlocks.c' ; ModuleID = '../testSFB/testOverlapBlocks.c'
source_filename = "../testSFB/testOverlapBlocks.c" source_filename = "../testSFB/testOverlapBlocks.c"
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
; Function Attrs: nounwind uwtable ; Function Attrs: nounwind uwtable
define dso_local void @test_overlap_1(i8* nocapture %A, i32 %x) local_unnamed_addr #0 { define dso_local void @test_overlap_1(i8* nocapture %A, i32 %x) local_unnamed_addr #0 {
; CHECK-LABEL: test_overlap_1: ; CHECK-LABEL: test_overlap_1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl $7, -8(%rdi) ; CHECK-NEXT: movl $7, -8(%rdi)
; CHECK-NEXT: movslq %esi, %rcx
; CHECK-NEXT: movq -16(%rdi), %rax ; CHECK-NEXT: movq -16(%rdi), %rax
; CHECK-NEXT: movq %rax, (%rdi) ; CHECK-NEXT: movq %rax, (%rdi)
; CHECK-NEXT: movl -8(%rdi), %eax ; CHECK-NEXT: movl -8(%rdi), %eax
; CHECK-NEXT: movl %eax, 8(%rdi) ; CHECK-NEXT: movl %eax, 8(%rdi)
; CHECK-NEXT: movl -4(%rdi), %eax ; CHECK-NEXT: movl -4(%rdi), %eax
; CHECK-NEXT: movl %eax, 12(%rdi) ; CHECK-NEXT: movl %eax, 12(%rdi)
; CHECK-NEXT: movslq %esi, %rax ; CHECK-NEXT: movq %rcx, -9(%rdi)
; CHECK-NEXT: movq %rax, -9(%rdi) ; CHECK-NEXT: movq %rcx, -16(%rdi)
; CHECK-NEXT: movq %rax, -16(%rdi)
; CHECK-NEXT: movb $0, -1(%rdi) ; CHECK-NEXT: movb $0, -1(%rdi)
; CHECK-NEXT: movq -16(%rdi), %rax ; CHECK-NEXT: movq -16(%rdi), %rax
; CHECK-NEXT: movq %rax, 16(%rdi) ; CHECK-NEXT: movq %rax, 16(%rdi)
; CHECK-NEXT: movl -8(%rdi), %eax ; CHECK-NEXT: movl -8(%rdi), %eax
; CHECK-NEXT: movl %eax, 24(%rdi) ; CHECK-NEXT: movl %eax, 24(%rdi)
; CHECK-NEXT: movzwl -4(%rdi), %eax ; CHECK-NEXT: movzwl -4(%rdi), %eax
; CHECK-NEXT: movw %ax, 28(%rdi) ; CHECK-NEXT: movw %ax, 28(%rdi)
; CHECK-NEXT: movb -2(%rdi), %al ; CHECK-NEXT: movb -2(%rdi), %al
; CHECK-NEXT: movb %al, 30(%rdi) ; CHECK-NEXT: movb %al, 30(%rdi)
; CHECK-NEXT: movb -1(%rdi), %al ; CHECK-NEXT: movb -1(%rdi), %al
; CHECK-NEXT: movb %al, 31(%rdi) ; CHECK-NEXT: movb %al, 31(%rdi)
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; DISABLED-LABEL: test_overlap_1: ; DISABLED-LABEL: test_overlap_1:
; DISABLED: # %bb.0: # %entry ; DISABLED: # %bb.0: # %entry
; DISABLED-NEXT: movl $7, -8(%rdi) ; DISABLED-NEXT: movl $7, -8(%rdi)
; DISABLED-NEXT: movslq %esi, %rax
; DISABLED-NEXT: movups -16(%rdi), %xmm0 ; DISABLED-NEXT: movups -16(%rdi), %xmm0
; DISABLED-NEXT: movups %xmm0, (%rdi) ; DISABLED-NEXT: movups %xmm0, (%rdi)
; DISABLED-NEXT: movslq %esi, %rax
; DISABLED-NEXT: movq %rax, -9(%rdi) ; DISABLED-NEXT: movq %rax, -9(%rdi)
; DISABLED-NEXT: movq %rax, -16(%rdi) ; DISABLED-NEXT: movq %rax, -16(%rdi)
; DISABLED-NEXT: movb $0, -1(%rdi) ; DISABLED-NEXT: movb $0, -1(%rdi)
; DISABLED-NEXT: movups -16(%rdi), %xmm0 ; DISABLED-NEXT: movups -16(%rdi), %xmm0
; DISABLED-NEXT: movups %xmm0, 16(%rdi) ; DISABLED-NEXT: movups %xmm0, 16(%rdi)
; DISABLED-NEXT: retq ; DISABLED-NEXT: retq
; ;
; CHECK-AVX2-LABEL: test_overlap_1: ; CHECK-AVX2-LABEL: test_overlap_1:
▲ Show 20 Lines • Show All 151 Lines • ▼ Show 20 Linesentry:
ret void ret void
} }
; Function Attrs: nounwind uwtable ; Function Attrs: nounwind uwtable
define dso_local void @test_overlap_3(i8* nocapture %A, i32 %x) local_unnamed_addr #0 { define dso_local void @test_overlap_3(i8* nocapture %A, i32 %x) local_unnamed_addr #0 {
; CHECK-LABEL: test_overlap_3: ; CHECK-LABEL: test_overlap_3:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl $7, -10(%rdi) ; CHECK-NEXT: movl $7, -10(%rdi)
; CHECK-NEXT: movslq %esi, %rcx
; CHECK-NEXT: movl -16(%rdi), %eax ; CHECK-NEXT: movl -16(%rdi), %eax
; CHECK-NEXT: movl %eax, (%rdi) ; CHECK-NEXT: movl %eax, (%rdi)
; CHECK-NEXT: movzwl -12(%rdi), %eax ; CHECK-NEXT: movzwl -12(%rdi), %eax
; CHECK-NEXT: movw %ax, 4(%rdi) ; CHECK-NEXT: movw %ax, 4(%rdi)
; CHECK-NEXT: movl -10(%rdi), %eax ; CHECK-NEXT: movl -10(%rdi), %eax
; CHECK-NEXT: movl %eax, 6(%rdi) ; CHECK-NEXT: movl %eax, 6(%rdi)
; CHECK-NEXT: movl -6(%rdi), %eax ; CHECK-NEXT: movl -6(%rdi), %eax
; CHECK-NEXT: movl %eax, 10(%rdi) ; CHECK-NEXT: movl %eax, 10(%rdi)
; CHECK-NEXT: movzwl -2(%rdi), %eax ; CHECK-NEXT: movzwl -2(%rdi), %eax
; CHECK-NEXT: movw %ax, 14(%rdi) ; CHECK-NEXT: movw %ax, 14(%rdi)
; CHECK-NEXT: movslq %esi, %rax ; CHECK-NEXT: movq %rcx, -9(%rdi)
; CHECK-NEXT: movq %rax, -9(%rdi) ; CHECK-NEXT: movq %rcx, -16(%rdi)
; CHECK-NEXT: movq %rax, -16(%rdi)
; CHECK-NEXT: movb $0, -1(%rdi) ; CHECK-NEXT: movb $0, -1(%rdi)
; CHECK-NEXT: movq -16(%rdi), %rax ; CHECK-NEXT: movq -16(%rdi), %rax
; CHECK-NEXT: movq %rax, 16(%rdi) ; CHECK-NEXT: movq %rax, 16(%rdi)
; CHECK-NEXT: movzwl -8(%rdi), %eax ; CHECK-NEXT: movzwl -8(%rdi), %eax
; CHECK-NEXT: movw %ax, 24(%rdi) ; CHECK-NEXT: movw %ax, 24(%rdi)
; CHECK-NEXT: movl -6(%rdi), %eax ; CHECK-NEXT: movl -6(%rdi), %eax
; CHECK-NEXT: movl %eax, 26(%rdi) ; CHECK-NEXT: movl %eax, 26(%rdi)
; CHECK-NEXT: movb -2(%rdi), %al ; CHECK-NEXT: movb -2(%rdi), %al
; CHECK-NEXT: movb %al, 30(%rdi) ; CHECK-NEXT: movb %al, 30(%rdi)
; CHECK-NEXT: movb -1(%rdi), %al ; CHECK-NEXT: movb -1(%rdi), %al
; CHECK-NEXT: movb %al, 31(%rdi) ; CHECK-NEXT: movb %al, 31(%rdi)
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; DISABLED-LABEL: test_overlap_3: ; DISABLED-LABEL: test_overlap_3:
; DISABLED: # %bb.0: # %entry ; DISABLED: # %bb.0: # %entry
; DISABLED-NEXT: movl $7, -10(%rdi) ; DISABLED-NEXT: movl $7, -10(%rdi)
; DISABLED-NEXT: movslq %esi, %rax
; DISABLED-NEXT: movups -16(%rdi), %xmm0 ; DISABLED-NEXT: movups -16(%rdi), %xmm0
; DISABLED-NEXT: movups %xmm0, (%rdi) ; DISABLED-NEXT: movups %xmm0, (%rdi)
; DISABLED-NEXT: movslq %esi, %rax
; DISABLED-NEXT: movq %rax, -9(%rdi) ; DISABLED-NEXT: movq %rax, -9(%rdi)
; DISABLED-NEXT: movq %rax, -16(%rdi) ; DISABLED-NEXT: movq %rax, -16(%rdi)
; DISABLED-NEXT: movb $0, -1(%rdi) ; DISABLED-NEXT: movb $0, -1(%rdi)
; DISABLED-NEXT: movups -16(%rdi), %xmm0 ; DISABLED-NEXT: movups -16(%rdi), %xmm0
; DISABLED-NEXT: movups %xmm0, 16(%rdi) ; DISABLED-NEXT: movups %xmm0, 16(%rdi)
; DISABLED-NEXT: retq ; DISABLED-NEXT: retq
; ;
; CHECK-AVX2-LABEL: test_overlap_3: ; CHECK-AVX2-LABEL: test_overlap_3:
▲ Show 20 Lines • Show All 72 Lines • ▼ Show 20 Linesentry:
ret void ret void
} }
; Function Attrs: nounwind uwtable ; Function Attrs: nounwind uwtable
define dso_local void @test_overlap_4(i8* nocapture %A, i32 %x) local_unnamed_addr #0 { define dso_local void @test_overlap_4(i8* nocapture %A, i32 %x) local_unnamed_addr #0 {
; CHECK-LABEL: test_overlap_4: ; CHECK-LABEL: test_overlap_4:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movups -16(%rdi), %xmm0 ; CHECK-NEXT: movups -16(%rdi), %xmm0
; CHECK-NEXT: movups %xmm0, (%rdi)
; CHECK-NEXT: movslq %esi, %rax ; CHECK-NEXT: movslq %esi, %rax
; CHECK-NEXT: movups %xmm0, (%rdi)
; CHECK-NEXT: movq %rax, -8(%rdi) ; CHECK-NEXT: movq %rax, -8(%rdi)
; CHECK-NEXT: movl %eax, -16(%rdi) ; CHECK-NEXT: movl %eax, -16(%rdi)
; CHECK-NEXT: movl $0, -11(%rdi) ; CHECK-NEXT: movl $0, -11(%rdi)
; CHECK-NEXT: movl -16(%rdi), %eax ; CHECK-NEXT: movl -16(%rdi), %eax
; CHECK-NEXT: movl %eax, 16(%rdi) ; CHECK-NEXT: movl %eax, 16(%rdi)
; CHECK-NEXT: movb -12(%rdi), %al ; CHECK-NEXT: movb -12(%rdi), %al
; CHECK-NEXT: movb %al, 20(%rdi) ; CHECK-NEXT: movb %al, 20(%rdi)
; CHECK-NEXT: movl -11(%rdi), %eax ; CHECK-NEXT: movl -11(%rdi), %eax
; CHECK-NEXT: movl %eax, 21(%rdi) ; CHECK-NEXT: movl %eax, 21(%rdi)
; CHECK-NEXT: movl -7(%rdi), %eax ; CHECK-NEXT: movl -7(%rdi), %eax
; CHECK-NEXT: movl %eax, 25(%rdi) ; CHECK-NEXT: movl %eax, 25(%rdi)
; CHECK-NEXT: movzwl -3(%rdi), %eax ; CHECK-NEXT: movzwl -3(%rdi), %eax
; CHECK-NEXT: movw %ax, 29(%rdi) ; CHECK-NEXT: movw %ax, 29(%rdi)
; CHECK-NEXT: movb -1(%rdi), %al ; CHECK-NEXT: movb -1(%rdi), %al
; CHECK-NEXT: movb %al, 31(%rdi) ; CHECK-NEXT: movb %al, 31(%rdi)
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; DISABLED-LABEL: test_overlap_4: ; DISABLED-LABEL: test_overlap_4:
; DISABLED: # %bb.0: # %entry ; DISABLED: # %bb.0: # %entry
; DISABLED-NEXT: movups -16(%rdi), %xmm0 ; DISABLED-NEXT: movups -16(%rdi), %xmm0
; DISABLED-NEXT: movups %xmm0, (%rdi)
; DISABLED-NEXT: movslq %esi, %rax ; DISABLED-NEXT: movslq %esi, %rax
; DISABLED-NEXT: movups %xmm0, (%rdi)
; DISABLED-NEXT: movq %rax, -8(%rdi) ; DISABLED-NEXT: movq %rax, -8(%rdi)
; DISABLED-NEXT: movl %eax, -16(%rdi) ; DISABLED-NEXT: movl %eax, -16(%rdi)
; DISABLED-NEXT: movl $0, -11(%rdi) ; DISABLED-NEXT: movl $0, -11(%rdi)
; DISABLED-NEXT: movups -16(%rdi), %xmm0 ; DISABLED-NEXT: movups -16(%rdi), %xmm0
; DISABLED-NEXT: movups %xmm0, 16(%rdi) ; DISABLED-NEXT: movups %xmm0, 16(%rdi)
; DISABLED-NEXT: retq ; DISABLED-NEXT: retq
; ;
; CHECK-AVX2-LABEL: test_overlap_4: ; CHECK-AVX2-LABEL: test_overlap_4:
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Linesentry:
ret void ret void
} }
; Function Attrs: nounwind uwtable ; Function Attrs: nounwind uwtable
define dso_local void @test_overlap_5(i8* nocapture %A, i32 %x) local_unnamed_addr #0 { define dso_local void @test_overlap_5(i8* nocapture %A, i32 %x) local_unnamed_addr #0 {
; CHECK-LABEL: test_overlap_5: ; CHECK-LABEL: test_overlap_5:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movups -16(%rdi), %xmm0 ; CHECK-NEXT: movups -16(%rdi), %xmm0
; CHECK-NEXT: movups %xmm0, (%rdi)
; CHECK-NEXT: movslq %esi, %rax ; CHECK-NEXT: movslq %esi, %rax
; CHECK-NEXT: movups %xmm0, (%rdi)
; CHECK-NEXT: movq %rax, -16(%rdi) ; CHECK-NEXT: movq %rax, -16(%rdi)
; CHECK-NEXT: movb %al, -14(%rdi) ; CHECK-NEXT: movb %al, -14(%rdi)
; CHECK-NEXT: movb $0, -11(%rdi) ; CHECK-NEXT: movb $0, -11(%rdi)
; CHECK-NEXT: movzwl -16(%rdi), %eax ; CHECK-NEXT: movzwl -16(%rdi), %eax
; CHECK-NEXT: movw %ax, 16(%rdi) ; CHECK-NEXT: movw %ax, 16(%rdi)
; CHECK-NEXT: movb -14(%rdi), %al ; CHECK-NEXT: movb -14(%rdi), %al
; CHECK-NEXT: movb %al, 18(%rdi) ; CHECK-NEXT: movb %al, 18(%rdi)
; CHECK-NEXT: movzwl -13(%rdi), %eax ; CHECK-NEXT: movzwl -13(%rdi), %eax
; CHECK-NEXT: movw %ax, 19(%rdi) ; CHECK-NEXT: movw %ax, 19(%rdi)
; CHECK-NEXT: movb -11(%rdi), %al ; CHECK-NEXT: movb -11(%rdi), %al
; CHECK-NEXT: movb %al, 21(%rdi) ; CHECK-NEXT: movb %al, 21(%rdi)
; CHECK-NEXT: movq -10(%rdi), %rax ; CHECK-NEXT: movq -10(%rdi), %rax
; CHECK-NEXT: movq %rax, 22(%rdi) ; CHECK-NEXT: movq %rax, 22(%rdi)
; CHECK-NEXT: movzwl -2(%rdi), %eax ; CHECK-NEXT: movzwl -2(%rdi), %eax
; CHECK-NEXT: movw %ax, 30(%rdi) ; CHECK-NEXT: movw %ax, 30(%rdi)
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; DISABLED-LABEL: test_overlap_5: ; DISABLED-LABEL: test_overlap_5:
; DISABLED: # %bb.0: # %entry ; DISABLED: # %bb.0: # %entry
; DISABLED-NEXT: movups -16(%rdi), %xmm0 ; DISABLED-NEXT: movups -16(%rdi), %xmm0
; DISABLED-NEXT: movups %xmm0, (%rdi)
; DISABLED-NEXT: movslq %esi, %rax ; DISABLED-NEXT: movslq %esi, %rax
; DISABLED-NEXT: movups %xmm0, (%rdi)
; DISABLED-NEXT: movq %rax, -16(%rdi) ; DISABLED-NEXT: movq %rax, -16(%rdi)
; DISABLED-NEXT: movb %al, -14(%rdi) ; DISABLED-NEXT: movb %al, -14(%rdi)
; DISABLED-NEXT: movb $0, -11(%rdi) ; DISABLED-NEXT: movb $0, -11(%rdi)
; DISABLED-NEXT: movups -16(%rdi), %xmm0 ; DISABLED-NEXT: movups -16(%rdi), %xmm0
; DISABLED-NEXT: movups %xmm0, 16(%rdi) ; DISABLED-NEXT: movups %xmm0, 16(%rdi)
; DISABLED-NEXT: retq ; DISABLED-NEXT: retq
; ;
; CHECK-AVX2-LABEL: test_overlap_5: ; CHECK-AVX2-LABEL: test_overlap_5:
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llvm/test/CodeGen/X86/avoid-sfb.ll

Show All 13 Lines
; CHECK-LABEL: test_conditional_block: ; CHECK-LABEL: test_conditional_block:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpl $18, %edx ; CHECK-NEXT: cmpl $18, %edx
; CHECK-NEXT: jl .LBB0_2 ; CHECK-NEXT: jl .LBB0_2
; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: movl %edx, 4(%rdi) ; CHECK-NEXT: movl %edx, 4(%rdi)
; CHECK-NEXT: .LBB0_2: # %if.end ; CHECK-NEXT: .LBB0_2: # %if.end
; CHECK-NEXT: movups (%r8), %xmm0 ; CHECK-NEXT: movups (%r8), %xmm0
; CHECK-NEXT: movups %xmm0, (%rcx)
; CHECK-NEXT: movl (%rdi), %eax ; CHECK-NEXT: movl (%rdi), %eax
; CHECK-NEXT: movl 4(%rdi), %edx
; CHECK-NEXT: movl %eax, (%rsi) ; CHECK-NEXT: movl %eax, (%rsi)
; CHECK-NEXT: movl 4(%rdi), %eax ; CHECK-NEXT: movl %edx, 4(%rsi)
; CHECK-NEXT: movl %eax, 4(%rsi) ; CHECK-NEXT: movups %xmm0, (%rcx)
; CHECK-NEXT: movq 8(%rdi), %rax ; CHECK-NEXT: movq 8(%rdi), %rcx
; CHECK-NEXT: movq %rax, 8(%rsi) ; CHECK-NEXT: movq %rcx, 8(%rsi)
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; DISABLED-LABEL: test_conditional_block: ; DISABLED-LABEL: test_conditional_block:
; DISABLED: # %bb.0: # %entry ; DISABLED: # %bb.0: # %entry
; DISABLED-NEXT: cmpl $18, %edx ; DISABLED-NEXT: cmpl $18, %edx
; DISABLED-NEXT: jl .LBB0_2 ; DISABLED-NEXT: jl .LBB0_2
; DISABLED-NEXT: # %bb.1: # %if.then ; DISABLED-NEXT: # %bb.1: # %if.then
; DISABLED-NEXT: movl %edx, 4(%rdi) ; DISABLED-NEXT: movl %edx, 4(%rdi)
; DISABLED-NEXT: .LBB0_2: # %if.end ; DISABLED-NEXT: .LBB0_2: # %if.end
; DISABLED-NEXT: movups (%r8), %xmm0 ; DISABLED-NEXT: movups (%r8), %xmm0
; DISABLED-NEXT: movups (%rdi), %xmm1
; DISABLED-NEXT: movups %xmm0, (%rcx) ; DISABLED-NEXT: movups %xmm0, (%rcx)
; DISABLED-NEXT: movups (%rdi), %xmm0 ; DISABLED-NEXT: movups %xmm1, (%rsi)
; DISABLED-NEXT: movups %xmm0, (%rsi)
; DISABLED-NEXT: retq ; DISABLED-NEXT: retq
; ;
; CHECK-AVX2-LABEL: test_conditional_block: ; CHECK-AVX2-LABEL: test_conditional_block:
; CHECK-AVX2: # %bb.0: # %entry ; CHECK-AVX2: # %bb.0: # %entry
; CHECK-AVX2-NEXT: cmpl $18, %edx ; CHECK-AVX2-NEXT: cmpl $18, %edx
; CHECK-AVX2-NEXT: jl .LBB0_2 ; CHECK-AVX2-NEXT: jl .LBB0_2
; CHECK-AVX2-NEXT: # %bb.1: # %if.then ; CHECK-AVX2-NEXT: # %bb.1: # %if.then
; CHECK-AVX2-NEXT: movl %edx, 4(%rdi) ; CHECK-AVX2-NEXT: movl %edx, 4(%rdi)
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} }
%struct.S6 = type { [4 x i32], i32, i32, i32, i32 } %struct.S6 = type { [4 x i32], i32, i32, i32, i32 }
; Function Attrs: nounwind uwtable ; Function Attrs: nounwind uwtable
define void @test_stack(%struct.S6* noalias nocapture sret %agg.result, %struct.S6* byval nocapture readnone align 8 %s1, %struct.S6* byval nocapture align 8 %s2, i32 %x) local_unnamed_addr #0 { define void @test_stack(%struct.S6* noalias nocapture sret %agg.result, %struct.S6* byval nocapture readnone align 8 %s1, %struct.S6* byval nocapture align 8 %s2, i32 %x) local_unnamed_addr #0 {
; CHECK-LABEL: test_stack: ; CHECK-LABEL: test_stack:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: movl %esi, {{[0-9]+}}(%rsp) ; CHECK-NEXT: movl %esi, {{[0-9]+}}(%rsp)
; CHECK-NEXT: movaps {{[0-9]+}}(%rsp), %xmm0 ; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: movups %xmm0, (%rdi)
; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rcx
; CHECK-NEXT: movq %rcx, 16(%rdi)
; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %ecx
; CHECK-NEXT: movl %ecx, 24(%rdi)
; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %ecx
; CHECK-NEXT: movl %ecx, 28(%rdi)
; CHECK-NEXT: movaps {{[0-9]+}}(%rsp), %xmm0 ; CHECK-NEXT: movaps {{[0-9]+}}(%rsp), %xmm0
; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rcx ; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rcx
; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %edx ; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %edx
; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %r8d
; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %esi ; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %esi
; CHECK-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp) ; CHECK-NEXT: movl %edx, 24(%rdi)
; CHECK-NEXT: movq %rcx, {{[0-9]+}}(%rsp) ; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %edx
; CHECK-NEXT: movl %edx, {{[0-9]+}}(%rsp) ; CHECK-NEXT: movq %rcx, 16(%rdi)
; CHECK-NEXT: movl %r8d, 28(%rdi)
; CHECK-NEXT: movl %esi, {{[0-9]+}}(%rsp) ; CHECK-NEXT: movl %esi, {{[0-9]+}}(%rsp)
; CHECK-NEXT: movups %xmm0, (%rdi)
; CHECK-NEXT: movaps {{[0-9]+}}(%rsp), %xmm0
; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rdi
; CHECK-NEXT: movl %edx, {{[0-9]+}}(%rsp)
; CHECK-NEXT: movq %rdi, {{[0-9]+}}(%rsp)
; CHECK-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; DISABLED-LABEL: test_stack: ; DISABLED-LABEL: test_stack:
; DISABLED: # %bb.0: # %entry ; DISABLED: # %bb.0: # %entry
; DISABLED-NEXT: movq %rdi, %rax
; DISABLED-NEXT: movl %esi, {{[0-9]+}}(%rsp) ; DISABLED-NEXT: movl %esi, {{[0-9]+}}(%rsp)
; DISABLED-NEXT: movq %rdi, %rax
; DISABLED-NEXT: movaps {{[0-9]+}}(%rsp), %xmm1
; DISABLED-NEXT: movaps {{[0-9]+}}(%rsp), %xmm0 ; DISABLED-NEXT: movaps {{[0-9]+}}(%rsp), %xmm0
; DISABLED-NEXT: movups %xmm0, (%rdi) ; DISABLED-NEXT: movaps {{[0-9]+}}(%rsp), %xmm2
; DISABLED-NEXT: movaps {{[0-9]+}}(%rsp), %xmm0 ; DISABLED-NEXT: movups %xmm1, 16(%rdi)
; DISABLED-NEXT: movups %xmm0, 16(%rdi)
; DISABLED-NEXT: movaps {{[0-9]+}}(%rsp), %xmm0
; DISABLED-NEXT: movaps {{[0-9]+}}(%rsp), %xmm1 ; DISABLED-NEXT: movaps {{[0-9]+}}(%rsp), %xmm1
; DISABLED-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp) ; DISABLED-NEXT: movups %xmm0, (%rdi)
; DISABLED-NEXT: movaps %xmm2, {{[0-9]+}}(%rsp)
; DISABLED-NEXT: movaps %xmm1, {{[0-9]+}}(%rsp) ; DISABLED-NEXT: movaps %xmm1, {{[0-9]+}}(%rsp)
; DISABLED-NEXT: retq ; DISABLED-NEXT: retq
; ;
; CHECK-AVX2-LABEL: test_stack: ; CHECK-AVX2-LABEL: test_stack:
; CHECK-AVX2: # %bb.0: # %entry ; CHECK-AVX2: # %bb.0: # %entry
; CHECK-AVX2-NEXT: movq %rdi, %rax ; CHECK-AVX2-NEXT: movq %rdi, %rax
; CHECK-AVX2-NEXT: movl %esi, {{[0-9]+}}(%rsp) ; CHECK-AVX2-NEXT: movl %esi, {{[0-9]+}}(%rsp)
; CHECK-AVX2-NEXT: vmovups {{[0-9]+}}(%rsp), %xmm0 ; CHECK-AVX2-NEXT: vmovups {{[0-9]+}}(%rsp), %xmm0
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; CHECK-NEXT: movl %edx, %ebp ; CHECK-NEXT: movl %edx, %ebp
; CHECK-NEXT: movq %rsi, %r12 ; CHECK-NEXT: movq %rsi, %r12
; CHECK-NEXT: movq %rdi, %rbx ; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl %r9d, 12(%rdi) ; CHECK-NEXT: movl %r9d, 12(%rdi)
; CHECK-NEXT: callq bar ; CHECK-NEXT: callq bar
; CHECK-NEXT: cmpl $18, %ebp ; CHECK-NEXT: cmpl $18, %ebp
; CHECK-NEXT: jl .LBB9_2 ; CHECK-NEXT: jl .LBB9_2
; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: movl %ebp, 4(%rbx)
; CHECK-NEXT: movq %rbx, %rdi ; CHECK-NEXT: movq %rbx, %rdi
; CHECK-NEXT: movl %ebp, 4(%rbx)
; CHECK-NEXT: callq bar ; CHECK-NEXT: callq bar
; CHECK-NEXT: .LBB9_2: # %if.end ; CHECK-NEXT: .LBB9_2: # %if.end
; CHECK-NEXT: movups (%r15), %xmm0 ; CHECK-NEXT: movups (%r15), %xmm0
; CHECK-NEXT: movups %xmm0, (%r14) ; CHECK-NEXT: movups %xmm0, (%r14)
; CHECK-NEXT: movups (%rbx), %xmm0 ; CHECK-NEXT: movups (%rbx), %xmm0
; CHECK-NEXT: movups %xmm0, (%r12) ; CHECK-NEXT: movups %xmm0, (%r12)
; CHECK-NEXT: popq %rbx ; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 40 ; CHECK-NEXT: .cfi_def_cfa_offset 40
Show All 29 Lines
; DISABLED-NEXT: movl %edx, %ebp ; DISABLED-NEXT: movl %edx, %ebp
; DISABLED-NEXT: movq %rsi, %r12 ; DISABLED-NEXT: movq %rsi, %r12
; DISABLED-NEXT: movq %rdi, %rbx ; DISABLED-NEXT: movq %rdi, %rbx
; DISABLED-NEXT: movl %r9d, 12(%rdi) ; DISABLED-NEXT: movl %r9d, 12(%rdi)
; DISABLED-NEXT: callq bar ; DISABLED-NEXT: callq bar
; DISABLED-NEXT: cmpl $18, %ebp ; DISABLED-NEXT: cmpl $18, %ebp
; DISABLED-NEXT: jl .LBB9_2 ; DISABLED-NEXT: jl .LBB9_2
; DISABLED-NEXT: # %bb.1: # %if.then ; DISABLED-NEXT: # %bb.1: # %if.then
; DISABLED-NEXT: movl %ebp, 4(%rbx)
; DISABLED-NEXT: movq %rbx, %rdi ; DISABLED-NEXT: movq %rbx, %rdi
; DISABLED-NEXT: movl %ebp, 4(%rbx)
; DISABLED-NEXT: callq bar ; DISABLED-NEXT: callq bar
; DISABLED-NEXT: .LBB9_2: # %if.end ; DISABLED-NEXT: .LBB9_2: # %if.end
; DISABLED-NEXT: movups (%r15), %xmm0 ; DISABLED-NEXT: movups (%r15), %xmm0
; DISABLED-NEXT: movups %xmm0, (%r14) ; DISABLED-NEXT: movups %xmm0, (%r14)
; DISABLED-NEXT: movups (%rbx), %xmm0 ; DISABLED-NEXT: movups (%rbx), %xmm0
; DISABLED-NEXT: movups %xmm0, (%r12) ; DISABLED-NEXT: movups %xmm0, (%r12)
; DISABLED-NEXT: popq %rbx ; DISABLED-NEXT: popq %rbx
; DISABLED-NEXT: .cfi_def_cfa_offset 40 ; DISABLED-NEXT: .cfi_def_cfa_offset 40
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; CHECK-NEXT: movq %r8, %r12 ; CHECK-NEXT: movq %r8, %r12
; CHECK-NEXT: movq %rcx, %r15 ; CHECK-NEXT: movq %rcx, %r15
; CHECK-NEXT: movq %rsi, %r14 ; CHECK-NEXT: movq %rsi, %r14
; CHECK-NEXT: movq %rdi, %rbx ; CHECK-NEXT: movq %rdi, %rbx
; CHECK-NEXT: movl %r9d, 12(%rdi) ; CHECK-NEXT: movl %r9d, 12(%rdi)
; CHECK-NEXT: cmpl $18, %edx ; CHECK-NEXT: cmpl $18, %edx
; CHECK-NEXT: jl .LBB10_2 ; CHECK-NEXT: jl .LBB10_2
; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: movl %edx, 4(%rbx)
; CHECK-NEXT: movq %rbx, %rdi ; CHECK-NEXT: movq %rbx, %rdi
; CHECK-NEXT: movl %edx, 4(%rbx)
; CHECK-NEXT: callq bar ; CHECK-NEXT: callq bar
; CHECK-NEXT: .LBB10_2: # %if.end ; CHECK-NEXT: .LBB10_2: # %if.end
; CHECK-NEXT: movups (%r12), %xmm0 ; CHECK-NEXT: movups (%r12), %xmm0
; CHECK-NEXT: movups %xmm0, (%r15) ; CHECK-NEXT: movups %xmm0, (%r15)
; CHECK-NEXT: movq (%rbx), %rax ; CHECK-NEXT: movq (%rbx), %rax
; CHECK-NEXT: movq %rax, (%r14) ; CHECK-NEXT: movq %rax, (%r14)
; CHECK-NEXT: movl 8(%rbx), %eax ; CHECK-NEXT: movl 8(%rbx), %eax
; CHECK-NEXT: movl %eax, 8(%r14) ; CHECK-NEXT: movl %eax, 8(%r14)
Show All 30 Lines
; DISABLED-NEXT: movq %r8, %r15 ; DISABLED-NEXT: movq %r8, %r15
; DISABLED-NEXT: movq %rcx, %r14 ; DISABLED-NEXT: movq %rcx, %r14
; DISABLED-NEXT: movq %rsi, %r12 ; DISABLED-NEXT: movq %rsi, %r12
; DISABLED-NEXT: movq %rdi, %rbx ; DISABLED-NEXT: movq %rdi, %rbx
; DISABLED-NEXT: movl %r9d, 12(%rdi) ; DISABLED-NEXT: movl %r9d, 12(%rdi)
; DISABLED-NEXT: cmpl $18, %edx ; DISABLED-NEXT: cmpl $18, %edx
; DISABLED-NEXT: jl .LBB10_2 ; DISABLED-NEXT: jl .LBB10_2
; DISABLED-NEXT: # %bb.1: # %if.then ; DISABLED-NEXT: # %bb.1: # %if.then
; DISABLED-NEXT: movl %edx, 4(%rbx)
; DISABLED-NEXT: movq %rbx, %rdi ; DISABLED-NEXT: movq %rbx, %rdi
; DISABLED-NEXT: movl %edx, 4(%rbx)
; DISABLED-NEXT: callq bar ; DISABLED-NEXT: callq bar
; DISABLED-NEXT: .LBB10_2: # %if.end ; DISABLED-NEXT: .LBB10_2: # %if.end
; DISABLED-NEXT: movups (%r15), %xmm0 ; DISABLED-NEXT: movups (%r15), %xmm0
; DISABLED-NEXT: movups %xmm0, (%r14) ; DISABLED-NEXT: movups %xmm0, (%r14)
; DISABLED-NEXT: movups (%rbx), %xmm0 ; DISABLED-NEXT: movups (%rbx), %xmm0
; DISABLED-NEXT: movups %xmm0, (%r12) ; DISABLED-NEXT: movups %xmm0, (%r12)
; DISABLED-NEXT: addq $8, %rsp ; DISABLED-NEXT: addq $8, %rsp
; DISABLED-NEXT: .cfi_def_cfa_offset 40 ; DISABLED-NEXT: .cfi_def_cfa_offset 40
▲ Show 20 Lines • Show All 138 Lines • ▼ Show 20 Lines
; CHECK-NEXT: jl .LBB11_2 ; CHECK-NEXT: jl .LBB11_2
; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: movl $1065353216, 4(%rdi) # imm = 0x3F800000 ; CHECK-NEXT: movl $1065353216, 4(%rdi) # imm = 0x3F800000
; CHECK-NEXT: .LBB11_2: # %if.end ; CHECK-NEXT: .LBB11_2: # %if.end
; CHECK-NEXT: movups (%r8), %xmm0 ; CHECK-NEXT: movups (%r8), %xmm0
; CHECK-NEXT: movups 16(%r8), %xmm1 ; CHECK-NEXT: movups 16(%r8), %xmm1
; CHECK-NEXT: movups %xmm1, 16(%rcx) ; CHECK-NEXT: movups %xmm1, 16(%rcx)
; CHECK-NEXT: movups %xmm0, (%rcx) ; CHECK-NEXT: movups %xmm0, (%rcx)
; CHECK-NEXT: movups 16(%rdi), %xmm0
; CHECK-NEXT: movl (%rdi), %eax ; CHECK-NEXT: movl (%rdi), %eax
; CHECK-NEXT: movl 4(%rdi), %ecx ; CHECK-NEXT: movl 4(%rdi), %ecx
; CHECK-NEXT: movq 8(%rdi), %rdx ; CHECK-NEXT: movq 8(%rdi), %rdx
; CHECK-NEXT: movups 16(%rdi), %xmm0
; CHECK-NEXT: movups %xmm0, 16(%rsi)
; CHECK-NEXT: movl %eax, (%rsi) ; CHECK-NEXT: movl %eax, (%rsi)
; CHECK-NEXT: movl %ecx, 4(%rsi) ; CHECK-NEXT: movl %ecx, 4(%rsi)
; CHECK-NEXT: movq %rdx, 8(%rsi) ; CHECK-NEXT: movq %rdx, 8(%rsi)
; CHECK-NEXT: movups %xmm0, 16(%rsi)
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; DISABLED-LABEL: test_conditional_block_float: ; DISABLED-LABEL: test_conditional_block_float:
; DISABLED: # %bb.0: # %entry ; DISABLED: # %bb.0: # %entry
; DISABLED-NEXT: cmpl $18, %edx ; DISABLED-NEXT: cmpl $18, %edx
; DISABLED-NEXT: jl .LBB11_2 ; DISABLED-NEXT: jl .LBB11_2
; DISABLED-NEXT: # %bb.1: # %if.then ; DISABLED-NEXT: # %bb.1: # %if.then
; DISABLED-NEXT: movl $1065353216, 4(%rdi) # imm = 0x3F800000 ; DISABLED-NEXT: movl $1065353216, 4(%rdi) # imm = 0x3F800000
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; CHECK-NEXT: jl .LBB12_2 ; CHECK-NEXT: jl .LBB12_2
; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: movq $1, 8(%rdi) ; CHECK-NEXT: movq $1, 8(%rdi)
; CHECK-NEXT: .LBB12_2: # %if.end ; CHECK-NEXT: .LBB12_2: # %if.end
; CHECK-NEXT: movups (%r8), %xmm0 ; CHECK-NEXT: movups (%r8), %xmm0
; CHECK-NEXT: movups 16(%r8), %xmm1 ; CHECK-NEXT: movups 16(%r8), %xmm1
; CHECK-NEXT: movups %xmm1, 16(%rcx) ; CHECK-NEXT: movups %xmm1, 16(%rcx)
; CHECK-NEXT: movups %xmm0, (%rcx) ; CHECK-NEXT: movups %xmm0, (%rcx)
; CHECK-NEXT: movups 16(%rdi), %xmm0
; CHECK-NEXT: movq (%rdi), %rax ; CHECK-NEXT: movq (%rdi), %rax
; CHECK-NEXT: movq 8(%rdi), %rcx ; CHECK-NEXT: movq 8(%rdi), %rcx
; CHECK-NEXT: movups 16(%rdi), %xmm0
; CHECK-NEXT: movups %xmm0, 16(%rsi)
; CHECK-NEXT: movq %rax, (%rsi) ; CHECK-NEXT: movq %rax, (%rsi)
; CHECK-NEXT: movq %rcx, 8(%rsi) ; CHECK-NEXT: movq %rcx, 8(%rsi)
; CHECK-NEXT: movups %xmm0, 16(%rsi)
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; DISABLED-LABEL: test_conditional_block_ymm: ; DISABLED-LABEL: test_conditional_block_ymm:
; DISABLED: # %bb.0: # %entry ; DISABLED: # %bb.0: # %entry
; DISABLED-NEXT: cmpl $18, %edx ; DISABLED-NEXT: cmpl $18, %edx
; DISABLED-NEXT: jl .LBB12_2 ; DISABLED-NEXT: jl .LBB12_2
; DISABLED-NEXT: # %bb.1: # %if.then ; DISABLED-NEXT: # %bb.1: # %if.then
; DISABLED-NEXT: movq $1, 8(%rdi) ; DISABLED-NEXT: movq $1, 8(%rdi)
▲ Show 20 Lines • Show All 154 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/avx-arith.ll

Show First 20 Lines • Show All 185 Lines • ▼ Show 20 Lines
} }
declare float @sqrtf(float) readnone declare float @sqrtf(float) readnone
define <4 x i64> @vpaddq(<4 x i64> %i, <4 x i64> %j) nounwind readnone { define <4 x i64> @vpaddq(<4 x i64> %i, <4 x i64> %j) nounwind readnone {
; CHECK-LABEL: vpaddq: ; CHECK-LABEL: vpaddq:
; CHECK: ## %bb.0: ; CHECK: ## %bb.0:
; CHECK-NEXT: vextractf128 $1, %ymm1, %xmm2
; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm3 ; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm3
; CHECK-NEXT: vpaddq %xmm2, %xmm3, %xmm2 ; CHECK-NEXT: vextractf128 $1, %ymm1, %xmm2
; CHECK-NEXT: vpaddq %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vpaddq %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpaddq %xmm2, %xmm3, %xmm2
; CHECK-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; CHECK-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%x = add <4 x i64> %i, %j %x = add <4 x i64> %i, %j
ret <4 x i64> %x ret <4 x i64> %x
} }
define <8 x i32> @vpaddd(<8 x i32> %i, <8 x i32> %j) nounwind readnone { define <8 x i32> @vpaddd(<8 x i32> %i, <8 x i32> %j) nounwind readnone {
; CHECK-LABEL: vpaddd: ; CHECK-LABEL: vpaddd:
; CHECK: ## %bb.0: ; CHECK: ## %bb.0:
; CHECK-NEXT: vextractf128 $1, %ymm1, %xmm2
; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm3 ; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm3
; CHECK-NEXT: vpaddd %xmm2, %xmm3, %xmm2 ; CHECK-NEXT: vextractf128 $1, %ymm1, %xmm2
; CHECK-NEXT: vpaddd %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vpaddd %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpaddd %xmm2, %xmm3, %xmm2
; CHECK-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; CHECK-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%x = add <8 x i32> %i, %j %x = add <8 x i32> %i, %j
ret <8 x i32> %x ret <8 x i32> %x
} }
define <16 x i16> @vpaddw(<16 x i16> %i, <16 x i16> %j) nounwind readnone { define <16 x i16> @vpaddw(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
; CHECK-LABEL: vpaddw: ; CHECK-LABEL: vpaddw:
; CHECK: ## %bb.0: ; CHECK: ## %bb.0:
; CHECK-NEXT: vextractf128 $1, %ymm1, %xmm2
; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm3 ; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm3
; CHECK-NEXT: vpaddw %xmm2, %xmm3, %xmm2 ; CHECK-NEXT: vextractf128 $1, %ymm1, %xmm2
; CHECK-NEXT: vpaddw %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vpaddw %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpaddw %xmm2, %xmm3, %xmm2
; CHECK-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; CHECK-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%x = add <16 x i16> %i, %j %x = add <16 x i16> %i, %j
ret <16 x i16> %x ret <16 x i16> %x
} }
define <32 x i8> @vpaddb(<32 x i8> %i, <32 x i8> %j) nounwind readnone { define <32 x i8> @vpaddb(<32 x i8> %i, <32 x i8> %j) nounwind readnone {
; CHECK-LABEL: vpaddb: ; CHECK-LABEL: vpaddb:
; CHECK: ## %bb.0: ; CHECK: ## %bb.0:
; CHECK-NEXT: vextractf128 $1, %ymm1, %xmm2
; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm3 ; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm3
; CHECK-NEXT: vpaddb %xmm2, %xmm3, %xmm2 ; CHECK-NEXT: vextractf128 $1, %ymm1, %xmm2
; CHECK-NEXT: vpaddb %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vpaddb %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpaddb %xmm2, %xmm3, %xmm2
; CHECK-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; CHECK-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%x = add <32 x i8> %i, %j %x = add <32 x i8> %i, %j
ret <32 x i8> %x ret <32 x i8> %x
} }
define <4 x i64> @vpsubq(<4 x i64> %i, <4 x i64> %j) nounwind readnone { define <4 x i64> @vpsubq(<4 x i64> %i, <4 x i64> %j) nounwind readnone {
; CHECK-LABEL: vpsubq: ; CHECK-LABEL: vpsubq:
; CHECK: ## %bb.0: ; CHECK: ## %bb.0:
; CHECK-NEXT: vextractf128 $1, %ymm1, %xmm2
; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm3 ; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm3
; CHECK-NEXT: vpsubq %xmm2, %xmm3, %xmm2 ; CHECK-NEXT: vextractf128 $1, %ymm1, %xmm2
; CHECK-NEXT: vpsubq %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vpsubq %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpsubq %xmm2, %xmm3, %xmm2
; CHECK-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; CHECK-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%x = sub <4 x i64> %i, %j %x = sub <4 x i64> %i, %j
ret <4 x i64> %x ret <4 x i64> %x
} }
define <8 x i32> @vpsubd(<8 x i32> %i, <8 x i32> %j) nounwind readnone { define <8 x i32> @vpsubd(<8 x i32> %i, <8 x i32> %j) nounwind readnone {
; CHECK-LABEL: vpsubd: ; CHECK-LABEL: vpsubd:
; CHECK: ## %bb.0: ; CHECK: ## %bb.0:
; CHECK-NEXT: vextractf128 $1, %ymm1, %xmm2
; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm3 ; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm3
; CHECK-NEXT: vpsubd %xmm2, %xmm3, %xmm2 ; CHECK-NEXT: vextractf128 $1, %ymm1, %xmm2
; CHECK-NEXT: vpsubd %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vpsubd %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpsubd %xmm2, %xmm3, %xmm2
; CHECK-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; CHECK-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%x = sub <8 x i32> %i, %j %x = sub <8 x i32> %i, %j
ret <8 x i32> %x ret <8 x i32> %x
} }
define <16 x i16> @vpsubw(<16 x i16> %i, <16 x i16> %j) nounwind readnone { define <16 x i16> @vpsubw(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
; CHECK-LABEL: vpsubw: ; CHECK-LABEL: vpsubw:
; CHECK: ## %bb.0: ; CHECK: ## %bb.0:
; CHECK-NEXT: vextractf128 $1, %ymm1, %xmm2
; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm3 ; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm3
; CHECK-NEXT: vpsubw %xmm2, %xmm3, %xmm2 ; CHECK-NEXT: vextractf128 $1, %ymm1, %xmm2
; CHECK-NEXT: vpsubw %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vpsubw %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpsubw %xmm2, %xmm3, %xmm2
; CHECK-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; CHECK-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%x = sub <16 x i16> %i, %j %x = sub <16 x i16> %i, %j
ret <16 x i16> %x ret <16 x i16> %x
} }
define <32 x i8> @vpsubb(<32 x i8> %i, <32 x i8> %j) nounwind readnone { define <32 x i8> @vpsubb(<32 x i8> %i, <32 x i8> %j) nounwind readnone {
; CHECK-LABEL: vpsubb: ; CHECK-LABEL: vpsubb:
; CHECK: ## %bb.0: ; CHECK: ## %bb.0:
; CHECK-NEXT: vextractf128 $1, %ymm1, %xmm2
; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm3 ; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm3
; CHECK-NEXT: vpsubb %xmm2, %xmm3, %xmm2 ; CHECK-NEXT: vextractf128 $1, %ymm1, %xmm2
; CHECK-NEXT: vpsubb %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vpsubb %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpsubb %xmm2, %xmm3, %xmm2
; CHECK-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; CHECK-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%x = sub <32 x i8> %i, %j %x = sub <32 x i8> %i, %j
ret <32 x i8> %x ret <32 x i8> %x
} }
define <8 x i32> @vpmulld(<8 x i32> %i, <8 x i32> %j) nounwind readnone { define <8 x i32> @vpmulld(<8 x i32> %i, <8 x i32> %j) nounwind readnone {
; CHECK-LABEL: vpmulld: ; CHECK-LABEL: vpmulld:
; CHECK: ## %bb.0: ; CHECK: ## %bb.0:
; CHECK-NEXT: vextractf128 $1, %ymm1, %xmm2
; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm3 ; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm3
; CHECK-NEXT: vpmulld %xmm2, %xmm3, %xmm2 ; CHECK-NEXT: vextractf128 $1, %ymm1, %xmm2
; CHECK-NEXT: vpmulld %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vpmulld %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpmulld %xmm2, %xmm3, %xmm2
; CHECK-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; CHECK-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%x = mul <8 x i32> %i, %j %x = mul <8 x i32> %i, %j
ret <8 x i32> %x ret <8 x i32> %x
} }
define <16 x i16> @vpmullw(<16 x i16> %i, <16 x i16> %j) nounwind readnone { define <16 x i16> @vpmullw(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
; CHECK-LABEL: vpmullw: ; CHECK-LABEL: vpmullw:
; CHECK: ## %bb.0: ; CHECK: ## %bb.0:
; CHECK-NEXT: vextractf128 $1, %ymm1, %xmm2
; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm3 ; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm3
; CHECK-NEXT: vpmullw %xmm2, %xmm3, %xmm2 ; CHECK-NEXT: vextractf128 $1, %ymm1, %xmm2
; CHECK-NEXT: vpmullw %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vpmullw %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpmullw %xmm2, %xmm3, %xmm2
; CHECK-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; CHECK-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%x = mul <16 x i16> %i, %j %x = mul <16 x i16> %i, %j
ret <16 x i16> %x ret <16 x i16> %x
} }
define <4 x i64> @mul_v4i64(<4 x i64> %i, <4 x i64> %j) nounwind readnone { define <4 x i64> @mul_v4i64(<4 x i64> %i, <4 x i64> %j) nounwind readnone {
; CHECK-LABEL: mul_v4i64: ; CHECK-LABEL: mul_v4i64:
; CHECK: ## %bb.0: ; CHECK: ## %bb.0:
; CHECK-NEXT: vextractf128 $1, %ymm1, %xmm2 ; CHECK-NEXT: vextractf128 $1, %ymm1, %xmm2
; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm3 ; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm3
; CHECK-NEXT: vpsrlq $32, %xmm3, %xmm4 ; CHECK-NEXT: vpsrlq $32, %xmm3, %xmm4
; CHECK-NEXT: vpmuludq %xmm2, %xmm4, %xmm4
; CHECK-NEXT: vpsrlq $32, %xmm2, %xmm5 ; CHECK-NEXT: vpsrlq $32, %xmm2, %xmm5
; CHECK-NEXT: vpmuludq %xmm2, %xmm4, %xmm4
; CHECK-NEXT: vpmuludq %xmm5, %xmm3, %xmm5 ; CHECK-NEXT: vpmuludq %xmm5, %xmm3, %xmm5
; CHECK-NEXT: vpaddq %xmm4, %xmm5, %xmm4
; CHECK-NEXT: vpsllq $32, %xmm4, %xmm4
; CHECK-NEXT: vpmuludq %xmm2, %xmm3, %xmm2 ; CHECK-NEXT: vpmuludq %xmm2, %xmm3, %xmm2
; CHECK-NEXT: vpaddq %xmm4, %xmm2, %xmm2
; CHECK-NEXT: vpsrlq $32, %xmm0, %xmm3 ; CHECK-NEXT: vpsrlq $32, %xmm0, %xmm3
; CHECK-NEXT: vpmuludq %xmm1, %xmm3, %xmm3 ; CHECK-NEXT: vpmuludq %xmm1, %xmm3, %xmm3
; CHECK-NEXT: vpaddq %xmm4, %xmm5, %xmm4
; CHECK-NEXT: vpsllq $32, %xmm4, %xmm4
; CHECK-NEXT: vpaddq %xmm4, %xmm2, %xmm2
; CHECK-NEXT: vpsrlq $32, %xmm1, %xmm4 ; CHECK-NEXT: vpsrlq $32, %xmm1, %xmm4
; CHECK-NEXT: vpmuludq %xmm4, %xmm0, %xmm4 ; CHECK-NEXT: vpmuludq %xmm4, %xmm0, %xmm4
; CHECK-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpaddq %xmm3, %xmm4, %xmm3 ; CHECK-NEXT: vpaddq %xmm3, %xmm4, %xmm3
; CHECK-NEXT: vpsllq $32, %xmm3, %xmm3 ; CHECK-NEXT: vpsllq $32, %xmm3, %xmm3
; CHECK-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpaddq %xmm3, %xmm0, %xmm0 ; CHECK-NEXT: vpaddq %xmm3, %xmm0, %xmm0
; CHECK-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; CHECK-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%x = mul <4 x i64> %i, %j %x = mul <4 x i64> %i, %j
ret <4 x i64> %x ret <4 x i64> %x
} }
declare <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float>) nounwind readnone declare <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float>) nounwind readnone
Show All 25 Lines

llvm/test/CodeGen/X86/avx-win64-args.ll

; RUN: llc < %s -mcpu=corei7-avx -mattr=+avx | FileCheck %s ; RUN: llc < %s -mcpu=corei7-avx -mattr=+avx | FileCheck %s
target triple = "x86_64-pc-win32" target triple = "x86_64-pc-win32"
declare <8 x float> @foo(<8 x float>, i32) declare <8 x float> @foo(<8 x float>, i32)
define <8 x float> @test1(<8 x float> %x, <8 x float> %y) nounwind uwtable readnone ssp { define <8 x float> @test1(<8 x float> %x, <8 x float> %y) nounwind uwtable readnone ssp {
entry: entry:
; CHECK: test1 ; CHECK: test1
; CHECK: leaq {{.*}}, %rcx
; CHECK: movl {{.*}}, %edx ; CHECK: movl {{.*}}, %edx
; CHECK: leaq {{.*}}, %rcx
; CHECK: call ; CHECK: call
; CHECK: ret ; CHECK: ret
%x1 = fadd <8 x float> %x, %y %x1 = fadd <8 x float> %x, %y
%call = call <8 x float> @foo(<8 x float> %x1, i32 1) nounwind %call = call <8 x float> @foo(<8 x float> %x1, i32 1) nounwind
%y1 = fsub <8 x float> %call, %y %y1 = fsub <8 x float> %call, %y
ret <8 x float> %y1 ret <8 x float> %y1
} }

llvm/test/CodeGen/X86/avx.ll

Show First 20 Lines • Show All 50 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%1 = load <4 x float>, <4 x float>* %pb, align 16 %1 = load <4 x float>, <4 x float>* %pb, align 16
%2 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %1, i32 96) %2 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %1, i32 96)
ret <4 x float> %2 ret <4 x float> %2
} }
define <4 x float> @insertps_from_vector_load_offset_2(<4 x float> %a, <4 x float>* nocapture readonly %pb, i64 %index) { define <4 x float> @insertps_from_vector_load_offset_2(<4 x float> %a, <4 x float>* nocapture readonly %pb, i64 %index) {
; CHECK-LABEL: insertps_from_vector_load_offset_2: ; CHECK-LABEL: insertps_from_vector_load_offset_2:
; On X32, account for the argument's move to registers ; On X32, account for the argument's move to registers
; X32: movl 4(%esp), %eax
; X32: movl 8(%esp), %ecx ; X32: movl 8(%esp), %ecx
; X32: movl 4(%esp), %eax
; CHECK-NOT: mov ; CHECK-NOT: mov
;; Try to match a bit more of the instr, since we need the load's offset. ;; Try to match a bit more of the instr, since we need the load's offset.
; CHECK: vinsertps $0, 12(%{{...}},%{{...}}), {{.*#+}} xmm0 = mem[0],xmm0[1,2,3] ; CHECK: vinsertps $0, 12(%{{...}},%{{...}}), {{.*#+}} xmm0 = mem[0],xmm0[1,2,3]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = getelementptr inbounds <4 x float>, <4 x float>* %pb, i64 %index %1 = getelementptr inbounds <4 x float>, <4 x float>* %pb, i64 %index
%2 = load <4 x float>, <4 x float>* %1, align 16 %2 = load <4 x float>, <4 x float>* %1, align 16
%3 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %2, i32 192) %3 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %2, i32 192)
ret <4 x float> %3 ret <4 x float> %3
Show All 39 Lines
; CHECK-LABEL: insertps_from_broadcast_multiple_use: ; CHECK-LABEL: insertps_from_broadcast_multiple_use:
; On X32, account for the arguments' move to registers ; On X32, account for the arguments' move to registers
; X32: movl 8(%esp), %eax ; X32: movl 8(%esp), %eax
; X32: movl 4(%esp), %ecx ; X32: movl 4(%esp), %ecx
; CHECK: vbroadcastss ; CHECK: vbroadcastss
; CHECK-NOT: mov ; CHECK-NOT: mov
; CHECK: insertps $48 ; CHECK: insertps $48
; CHECK: insertps $48 ; CHECK: insertps $48
; CHECK: vaddps
; CHECK: insertps $48 ; CHECK: insertps $48
; CHECK: vaddps
; CHECK: insertps $48 ; CHECK: insertps $48
; CHECK: vaddps ; CHECK: vaddps
; CHECK: vaddps ; CHECK: vaddps
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = getelementptr inbounds float, float* %fb, i64 %index %1 = getelementptr inbounds float, float* %fb, i64 %index
%2 = load float, float* %1, align 4 %2 = load float, float* %1, align 4
%3 = insertelement <4 x float> undef, float %2, i32 0 %3 = insertelement <4 x float> undef, float %2, i32 0
%4 = insertelement <4 x float> %3, float %2, i32 1 %4 = insertelement <4 x float> %3, float %2, i32 1
Show All 11 Lines

llvm/test/CodeGen/X86/avx1-logical-load-folding.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -O3 -disable-peephole -mtriple=i686-apple-macosx10.9.0 -mcpu=corei7-avx -mattr=+avx | FileCheck %s --check-prefix=X86 ; RUN: llc < %s -O3 -disable-peephole -mtriple=i686-apple-macosx10.9.0 -mcpu=corei7-avx -mattr=+avx | FileCheck %s --check-prefix=X86
; RUN: llc < %s -O3 -disable-peephole -mtriple=x86_64-apple-macosx10.9.0 -mcpu=corei7-avx -mattr=+avx | FileCheck %s --check-prefix=X64 ; RUN: llc < %s -O3 -disable-peephole -mtriple=x86_64-apple-macosx10.9.0 -mcpu=corei7-avx -mattr=+avx | FileCheck %s --check-prefix=X64
; Function Attrs: nounwind ssp uwtable ; Function Attrs: nounwind ssp uwtable
define void @test1(float* %A, float* %C) #0 { define void @test1(float* %A, float* %C) #0 {
; X86-LABEL: test1: ; X86-LABEL: test1:
; X86: ## %bb.0: ; X86: ## %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X86-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-NEXT: vandps LCPI0_0, %xmm0, %xmm0 ; X86-NEXT: vandps LCPI0_0, %xmm0, %xmm0
; X86-NEXT: vmovss %xmm0, (%eax) ; X86-NEXT: vmovss %xmm0, (%eax)
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: test1: ; X64-LABEL: test1:
; X64: ## %bb.0: ; X64: ## %bb.0:
; X64-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X64-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
Show All 9 Lines; X64-NEXT: retq
store float %tmp6, float* %C store float %tmp6, float* %C
ret void ret void
} }
; Function Attrs: nounwind ssp uwtable ; Function Attrs: nounwind ssp uwtable
define void @test2(float* %A, float* %C) #0 { define void @test2(float* %A, float* %C) #0 {
; X86-LABEL: test2: ; X86-LABEL: test2:
; X86: ## %bb.0: ; X86: ## %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: vmovaps (%ecx), %xmm0 ; X86-NEXT: vmovaps (%ecx), %xmm0
; X86-NEXT: vorps LCPI1_0, %xmm0, %xmm0 ; X86-NEXT: vorps LCPI1_0, %xmm0, %xmm0
; X86-NEXT: vmovss %xmm0, (%eax) ; X86-NEXT: vmovss %xmm0, (%eax)
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: test2: ; X64-LABEL: test2:
; X64: ## %bb.0: ; X64: ## %bb.0:
; X64-NEXT: vmovaps (%rdi), %xmm0 ; X64-NEXT: vmovaps (%rdi), %xmm0
Show All 9 Lines; X64-NEXT: retq
store float %tmp6, float* %C store float %tmp6, float* %C
ret void ret void
} }
; Function Attrs: nounwind ssp uwtable ; Function Attrs: nounwind ssp uwtable
define void @test3(float* %A, float* %C) #0 { define void @test3(float* %A, float* %C) #0 {
; X86-LABEL: test3: ; X86-LABEL: test3:
; X86: ## %bb.0: ; X86: ## %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: vmovaps (%ecx), %xmm0 ; X86-NEXT: vmovaps (%ecx), %xmm0
; X86-NEXT: vxorps LCPI2_0, %xmm0, %xmm0 ; X86-NEXT: vxorps LCPI2_0, %xmm0, %xmm0
; X86-NEXT: vmovss %xmm0, (%eax) ; X86-NEXT: vmovss %xmm0, (%eax)
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: test3: ; X64-LABEL: test3:
; X64: ## %bb.0: ; X64: ## %bb.0:
; X64-NEXT: vmovaps (%rdi), %xmm0 ; X64-NEXT: vmovaps (%rdi), %xmm0
; X64-NEXT: vxorps {{.*}}(%rip), %xmm0, %xmm0 ; X64-NEXT: vxorps {{.*}}(%rip), %xmm0, %xmm0
; X64-NEXT: vmovss %xmm0, (%rsi) ; X64-NEXT: vmovss %xmm0, (%rsi)
; X64-NEXT: retq ; X64-NEXT: retq
%tmp1 = bitcast float* %A to <8 x float>* %tmp1 = bitcast float* %A to <8 x float>*
%tmp2 = load <8 x float>, <8 x float>* %tmp1, align 32 %tmp2 = load <8 x float>, <8 x float>* %tmp1, align 32
%tmp3 = bitcast <8 x float> %tmp2 to <8 x i32> %tmp3 = bitcast <8 x float> %tmp2 to <8 x i32>
%tmp4 = xor <8 x i32> %tmp3, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647> %tmp4 = xor <8 x i32> %tmp3, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
%tmp5 = bitcast <8 x i32> %tmp4 to <8 x float> %tmp5 = bitcast <8 x i32> %tmp4 to <8 x float>
%tmp6 = extractelement <8 x float> %tmp5, i32 0 %tmp6 = extractelement <8 x float> %tmp5, i32 0
store float %tmp6, float* %C store float %tmp6, float* %C
ret void ret void
} }
define void @test4(float* %A, float* %C) #0 { define void @test4(float* %A, float* %C) #0 {
; X86-LABEL: test4: ; X86-LABEL: test4:
; X86: ## %bb.0: ; X86: ## %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: vmovaps (%ecx), %xmm0 ; X86-NEXT: vmovaps (%ecx), %xmm0
; X86-NEXT: vandnps LCPI3_0, %xmm0, %xmm0 ; X86-NEXT: vandnps LCPI3_0, %xmm0, %xmm0
; X86-NEXT: vmovss %xmm0, (%eax) ; X86-NEXT: vmovss %xmm0, (%eax)
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: test4: ; X64-LABEL: test4:
; X64: ## %bb.0: ; X64: ## %bb.0:
; X64-NEXT: vmovaps (%rdi), %xmm0 ; X64-NEXT: vmovaps (%rdi), %xmm0
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llvm/test/CodeGen/X86/break-false-dep.ll

; RUN: llc < %s -mtriple=x86_64-linux -mattr=+sse2 -mcpu=nehalem | FileCheck %s --check-prefix=SSE ; RUN: llc < %s -mtriple=x86_64-linux -mattr=+sse2 -mcpu=nehalem | FileCheck %s --check-prefix=SSE
; RUN: llc < %s -mtriple=x86_64-win32 -mattr=+sse2 -mcpu=nehalem | FileCheck %s --check-prefix=SSE ; RUN: llc < %s -mtriple=x86_64-win32 -mattr=+sse2 -mcpu=nehalem | FileCheck %s --check-prefix=SSE
; RUN: llc < %s -mtriple=x86_64-win32 -mattr=+avx -mcpu=corei7-avx | FileCheck %s --check-prefix=AVX ; RUN: llc < %s -mtriple=x86_64-win32 -mattr=+avx -mcpu=corei7-avx | FileCheck %s --check-prefixes=AVX,AVX1
; RUN: llc < %s -mtriple=x86_64-win32 -mattr=+avx512vl -mcpu=skx | FileCheck %s --check-prefix=AVX ; RUN: llc < %s -mtriple=x86_64-win32 -mattr=+avx512vl -mcpu=skx | FileCheck %s --check-prefixes=AVX,AVX512
define double @t1(float* nocapture %x) nounwind readonly ssp { define double @t1(float* nocapture %x) nounwind readonly ssp {
entry: entry:
; SSE-LABEL: t1: ; SSE-LABEL: t1:
; SSE: movss ([[A0:%rdi|%rcx]]), %xmm0 ; SSE: movss ([[A0:%rdi|%rcx]]), %xmm0
; SSE: cvtss2sd %xmm0, %xmm0 ; SSE: cvtss2sd %xmm0, %xmm0
%0 = load float, float* %x, align 4 %0 = load float, float* %x, align 4
▲ Show 20 Lines • Show All 172 Lines • ▼ Show 20 Linesfor.inc14: ; preds = %for.body3
br i1 %exitcond26, label %for.end16, label %for.cond1.preheader br i1 %exitcond26, label %for.end16, label %for.cond1.preheader
for.end16: ; preds = %for.inc14 for.end16: ; preds = %for.inc14
ret void ret void
;SSE-LABEL:@loopdep3 ;SSE-LABEL:@loopdep3
;SSE: xorps [[XMM0:%xmm[0-9]+]], [[XMM0]] ;SSE: xorps [[XMM0:%xmm[0-9]+]], [[XMM0]]
;SSE-NEXT: cvtsi2sdl {{.*}}, [[XMM0]] ;SSE-NEXT: cvtsi2sdl {{.*}}, [[XMM0]]
;SSE-NEXT: mulsd {{.*}}, [[XMM0]] ;SSE: mulsd {{.*}}, [[XMM0]]
;SSE-NEXT: mulsd {{.*}}, [[XMM0]] ;SSE-NEXT: mulsd {{.*}}, [[XMM0]]
;SSE-NEXT: mulsd {{.*}}, [[XMM0]] ;SSE-NEXT: mulsd {{.*}}, [[XMM0]]
;SSE-NEXT: movsd [[XMM0]], ;SSE-NEXT: movsd [[XMM0]],
;AVX-LABEL:@loopdep3 ;AVX-LABEL:@loopdep3
;AVX: vxorps [[XMM0:%xmm[0-9]+]], [[XMM0]] ;AVX: vxorps [[XMM0:%xmm[0-9]+]], [[XMM0]]
;AVX-NEXT: vcvtsi2sdl {{.*}}, [[XMM0]], {{%xmm[0-9]+}} ;AVX-NEXT: vcvtsi2sdl {{.*}}, [[XMM0]], {{%xmm[0-9]+}}
;AVX-NEXT: vmulsd {{.*}}, [[XMM0]], [[XMM0]] ;AVX: vmulsd {{.*}}, [[XMM0]], [[XMM0]]
;AVX-NEXT: vmulsd {{.*}}, [[XMM0]], [[XMM0]] ;AVX-NEXT: vmulsd {{.*}}, [[XMM0]], [[XMM0]]
;AVX-NEXT: vmulsd {{.*}}, [[XMM0]], [[XMM0]] ;AVX-NEXT: vmulsd {{.*}}, [[XMM0]], [[XMM0]]
;AVX-NEXT: vmovsd [[XMM0]], ;AVX-NEXT: vmovsd [[XMM0]],
} }
define double @inlineasmdep(i64 %arg) { define double @inlineasmdep(i64 %arg) {
top: top:
tail call void asm sideeffect "", "~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{dirflag},~{fpsr},~{flags}"() tail call void asm sideeffect "", "~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{dirflag},~{fpsr},~{flags}"()
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tail call void asm sideeffect "", "~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{dirflag},~{fpsr},~{flags}"() tail call void asm sideeffect "", "~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{dirflag},~{fpsr},~{flags}"()
tail call void asm sideeffect "", "~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{dirflag},~{fpsr},~{flags}"() tail call void asm sideeffect "", "~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{dirflag},~{fpsr},~{flags}"()
tail call void asm sideeffect "", "~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{dirflag},~{fpsr},~{flags}"() tail call void asm sideeffect "", "~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{dirflag},~{fpsr},~{flags}"()
tail call void asm sideeffect "", "~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{dirflag},~{fpsr},~{flags}"() tail call void asm sideeffect "", "~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{dirflag},~{fpsr},~{flags}"()
tail call void asm sideeffect "", "~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{dirflag},~{fpsr},~{flags}"() tail call void asm sideeffect "", "~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{dirflag},~{fpsr},~{flags}"()
tail call void asm sideeffect "", "~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{dirflag},~{fpsr},~{flags}"() tail call void asm sideeffect "", "~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{dirflag},~{fpsr},~{flags}"()
%tmp1 = sitofp i64 %arg to double %tmp1 = sitofp i64 %arg to double
ret double %tmp1 ret double %tmp1
;AVX-LABEL:@clearence ;AVX1-LABEL:@clearence
;AVX: vxorps [[XMM6:%xmm6]], [[XMM6]], [[XMM6]] ;AVX1: vxorps [[XMM0:%xmm0]], [[XMM0]], [[XMM0]]
;AVX-NEXT: vcvtsi2sd {{.*}}, [[XMM6]], {{%xmm[0-9]+}} ;AVX1-NEXT: vcvtsi2sd {{.*}}, [[XMM0]], {{%xmm[0-9]+}}
;AVX512-LABEL:@clearence
;AVX512: vxorps [[XMM6:%xmm6]], [[XMM6]], [[XMM6]]
;AVX512-NEXT: vcvtsi2sd {{.*}}, [[XMM6]], {{%xmm[0-9]+}}
} }
; Make sure we are making a smart choice regarding undef registers in order to ; Make sure we are making a smart choice regarding undef registers in order to
; avoid a cyclic dependence on a write to the same register in a previous ; avoid a cyclic dependence on a write to the same register in a previous
; iteration, especially when we cannot zero out the undef register because it ; iteration, especially when we cannot zero out the undef register because it
; is alive. ; is alive.
define i64 @loopclearence(i64* nocapture %x, double* nocapture %y) nounwind { define i64 @loopclearence(i64* nocapture %x, double* nocapture %y) nounwind {
entry: entry:
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llvm/test/CodeGen/X86/bypass-slow-division-tune.ll

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; ATOM-NEXT: # kill: def $eax killed $eax killed $rax ; ATOM-NEXT: # kill: def $eax killed $eax killed $rax
; ATOM-NEXT: xorl %edx, %edx ; ATOM-NEXT: xorl %edx, %edx
; ATOM-NEXT: divl %esi ; ATOM-NEXT: divl %esi
; ATOM-NEXT: # kill: def $eax killed $eax def $rax ; ATOM-NEXT: # kill: def $eax killed $eax def $rax
; ATOM-NEXT: retq ; ATOM-NEXT: retq
; ;
; X64-LABEL: div64: ; X64-LABEL: div64:
; X64: # %bb.0: # %entry ; X64: # %bb.0: # %entry
; X64-NEXT: movq %rdi, %rax
; X64-NEXT: movq %rdi, %rcx ; X64-NEXT: movq %rdi, %rcx
; X64-NEXT: movq %rdi, %rax
; X64-NEXT: orq %rsi, %rcx ; X64-NEXT: orq %rsi, %rcx
; X64-NEXT: shrq $32, %rcx ; X64-NEXT: shrq $32, %rcx
; X64-NEXT: je .LBB1_1 ; X64-NEXT: je .LBB1_1
; X64-NEXT: # %bb.2: ; X64-NEXT: # %bb.2:
; X64-NEXT: cqto ; X64-NEXT: cqto
; X64-NEXT: idivq %rsi ; X64-NEXT: idivq %rsi
; X64-NEXT: retq ; X64-NEXT: retq
; X64-NEXT: .LBB1_1: ; X64-NEXT: .LBB1_1:
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; ATOM-NEXT: # kill: def $eax killed $eax killed $rax ; ATOM-NEXT: # kill: def $eax killed $eax killed $rax
; ATOM-NEXT: xorl %edx, %edx ; ATOM-NEXT: xorl %edx, %edx
; ATOM-NEXT: divl %esi ; ATOM-NEXT: divl %esi
; ATOM-NEXT: # kill: def $eax killed $eax def $rax ; ATOM-NEXT: # kill: def $eax killed $eax def $rax
; ATOM-NEXT: retq ; ATOM-NEXT: retq
; ;
; X64-LABEL: div64_hugews: ; X64-LABEL: div64_hugews:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: movq %rdi, %rax
; X64-NEXT: movq %rdi, %rcx ; X64-NEXT: movq %rdi, %rcx
; X64-NEXT: movq %rdi, %rax
; X64-NEXT: orq %rsi, %rcx ; X64-NEXT: orq %rsi, %rcx
; X64-NEXT: shrq $32, %rcx ; X64-NEXT: shrq $32, %rcx
; X64-NEXT: je .LBB4_1 ; X64-NEXT: je .LBB4_1
; X64-NEXT: # %bb.2: ; X64-NEXT: # %bb.2:
; X64-NEXT: cqto ; X64-NEXT: cqto
; X64-NEXT: idivq %rsi ; X64-NEXT: idivq %rsi
; X64-NEXT: retq ; X64-NEXT: retq
; X64-NEXT: .LBB4_1: ; X64-NEXT: .LBB4_1:
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llvm/test/CodeGen/X86/byval7.ll

Show All 9 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushl %ebp ; CHECK-NEXT: pushl %ebp
; CHECK-NEXT: movl %esp, %ebp ; CHECK-NEXT: movl %esp, %ebp
; CHECK-NEXT: pushl %edi ; CHECK-NEXT: pushl %edi
; CHECK-NEXT: pushl %esi ; CHECK-NEXT: pushl %esi
; CHECK-NEXT: andl $-16, %esp ; CHECK-NEXT: andl $-16, %esp
; CHECK-NEXT: subl $304, %esp # imm = 0x130 ; CHECK-NEXT: subl $304, %esp # imm = 0x130
; CHECK-NEXT: movaps {{.*#+}} xmm0 = [3,2,1,0] ; CHECK-NEXT: movaps {{.*#+}} xmm0 = [3,2,1,0]
; CHECK-NEXT: movaps %xmm0, {{[0-9]+}}(%esp)
; CHECK-NEXT: leal {{[0-9]+}}(%esp), %edi ; CHECK-NEXT: leal {{[0-9]+}}(%esp), %edi
; CHECK-NEXT: leal {{[0-9]+}}(%esp), %esi ; CHECK-NEXT: leal {{[0-9]+}}(%esp), %esi
; CHECK-NEXT: movl $36, %ecx ; CHECK-NEXT: movl $36, %ecx
; CHECK-NEXT: movaps %xmm0, {{[0-9]+}}(%esp)
; CHECK-NEXT: rep;movsl (%esi), %es:(%edi) ; CHECK-NEXT: rep;movsl (%esi), %es:(%edi)
; CHECK-NEXT: movl $1, (%esp) ; CHECK-NEXT: movl $1, (%esp)
; CHECK-NEXT: calll t ; CHECK-NEXT: calll t
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: leal -8(%ebp), %esp ; CHECK-NEXT: leal -8(%ebp), %esp
; CHECK-NEXT: popl %esi ; CHECK-NEXT: popl %esi
; CHECK-NEXT: popl %edi ; CHECK-NEXT: popl %edi
; CHECK-NEXT: popl %ebp ; CHECK-NEXT: popl %ebp
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llvm/test/CodeGen/X86/catchpad-regmask.ll

Show First 20 Lines • Show All 71 Lines • ▼ Show 20 Lines
; CHECK: movslq {{.*}}, %[[idx:[^ ]*]] ; CHECK: movslq {{.*}}, %[[idx:[^ ]*]]
; CHECK: leaq array(%rip), %[[base:[^ ]*]] ; CHECK: leaq array(%rip), %[[base:[^ ]*]]
; CHECK: movl $333, (%[[base]],%[[idx]],4) ; CHECK: movl $333, (%[[base]],%[[idx]],4)
; CHECK: popq %rbp ; CHECK: popq %rbp
; CHECK: retq ; CHECK: retq
; CHECK: "?catch${{[0-9]+}}@?0?global_array@4HA": ; CHECK: "?catch${{[0-9]+}}@?0?global_array@4HA":
; CHECK: pushq %rbp ; CHECK: pushq %rbp
; CHECK: movslq {{.*}}, %[[idx:[^ ]*]]
; CHECK: leaq array(%rip), %[[base:[^ ]*]] ; CHECK: leaq array(%rip), %[[base:[^ ]*]]
; CHECK: movslq {{.*}}, %[[idx:[^ ]*]]
; CHECK: movl $222, (%[[base]],%[[idx]],4) ; CHECK: movl $222, (%[[base]],%[[idx]],4)
; CHECK: popq %rbp ; CHECK: popq %rbp
; CHECK: retq # CATCHRET ; CHECK: retq # CATCHRET
declare void @_CxxThrowException(i8*, %eh.ThrowInfo*) declare void @_CxxThrowException(i8*, %eh.ThrowInfo*)
declare i32 @__CxxFrameHandler3(...) declare i32 @__CxxFrameHandler3(...)
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llvm/test/CodeGen/X86/cfguard-x86-64-vectorcall.ll

; RUN: llc < %s -mtriple=x86_64-pc-windows-msvc | FileCheck %s -check-prefix=X64 ; RUN: llc < %s -mtriple=x86_64-pc-windows-msvc | FileCheck %s -check-prefix=X64
; Control Flow Guard is currently only available on Windows ; Control Flow Guard is currently only available on Windows
; Test that Control Flow Guard checks are correctly added for x86_64 vector calls. ; Test that Control Flow Guard checks are correctly added for x86_64 vector calls.
define void @func_cf_vector_x64(void (%struct.HVA)* %0, %struct.HVA* %1) #0 { define void @func_cf_vector_x64(void (%struct.HVA)* %0, %struct.HVA* %1) #0 {
entry: entry:
%2 = alloca %struct.HVA, align 8 %2 = alloca %struct.HVA, align 8
%3 = bitcast %struct.HVA* %2 to i8* %3 = bitcast %struct.HVA* %2 to i8*
%4 = bitcast %struct.HVA* %1 to i8* %4 = bitcast %struct.HVA* %1 to i8*
call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 %3, i8* align 8 %4, i64 32, i1 false) call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 %3, i8* align 8 %4, i64 32, i1 false)
%5 = load %struct.HVA, %struct.HVA* %2, align 8 %5 = load %struct.HVA, %struct.HVA* %2, align 8
call x86_vectorcallcc void %0(%struct.HVA inreg %5) call x86_vectorcallcc void %0(%struct.HVA inreg %5)
ret void ret void
; X64-LABEL: func_cf_vector_x64 ; X64-LABEL: func_cf_vector_x64
; X64: movq %rcx, %rax
; X64: movups (%rdx), %xmm0 ; X64: movups (%rdx), %xmm0
; X64: movups 16(%rdx), %xmm1 ; X64: movups 16(%rdx), %xmm1
; X64: movq %rcx, %rax
; X64: movaps %xmm0, 32(%rsp) ; X64: movaps %xmm0, 32(%rsp)
; X64: movaps %xmm1, 48(%rsp) ; X64: movaps %xmm1, 48(%rsp)
; X64: movsd 32(%rsp), %xmm0 # xmm0 = mem[0],zero ; X64: movsd 32(%rsp), %xmm0 # xmm0 = mem[0],zero
; X64: movsd 40(%rsp), %xmm1 # xmm1 = mem[0],zero ; X64: movsd 40(%rsp), %xmm1 # xmm1 = mem[0],zero
; X64: movsd 48(%rsp), %xmm2 # xmm2 = mem[0],zero ; X64: movsd 48(%rsp), %xmm2 # xmm2 = mem[0],zero
; X64: movsd 56(%rsp), %xmm3 # xmm3 = mem[0],zero ; X64: movsd 56(%rsp), %xmm3 # xmm3 = mem[0],zero
; X64: callq *__guard_dispatch_icall_fptr(%rip) ; X64: callq *__guard_dispatch_icall_fptr(%rip)
; X64-NOT: callq ; X64-NOT: callq
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llvm/test/CodeGen/X86/cfguard-x86-vectorcall.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --no_x86_scrub_rip ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --no_x86_scrub_rip
; RUN: llc < %s -mtriple=i686-pc-windows-msvc | FileCheck %s -check-prefix=X32 ; RUN: llc < %s -mtriple=i686-pc-windows-msvc | FileCheck %s -check-prefix=X32
; Control Flow Guard is currently only available on Windows ; Control Flow Guard is currently only available on Windows
; Test that Control Flow Guard checks are correctly added for x86 vector calls. ; Test that Control Flow Guard checks are correctly added for x86 vector calls.
define void @func_cf_vector_x86(void (%struct.HVA)* %0, %struct.HVA* %1) #0 { define void @func_cf_vector_x86(void (%struct.HVA)* %0, %struct.HVA* %1) #0 {
; X32-LABEL: func_cf_vector_x86: ; X32-LABEL: func_cf_vector_x86:
; X32: # %bb.0: # %entry ; X32: # %bb.0: # %entry
; X32-NEXT: pushl %ebp ; X32-NEXT: pushl %ebp
; X32-NEXT: movl %esp, %ebp ; X32-NEXT: movl %esp, %ebp
; X32-NEXT: andl $-16, %esp ; X32-NEXT: andl $-16, %esp
; X32-NEXT: subl $48, %esp ; X32-NEXT: subl $48, %esp
; X32-NEXT: movl 8(%ebp), %ecx
; X32-NEXT: movl 12(%ebp), %eax ; X32-NEXT: movl 12(%ebp), %eax
; X32-NEXT: movl 8(%ebp), %ecx
; X32-NEXT: movups (%eax), %xmm0 ; X32-NEXT: movups (%eax), %xmm0
; X32-NEXT: movups 16(%eax), %xmm1 ; X32-NEXT: movups 16(%eax), %xmm1
; X32-NEXT: movaps %xmm0, (%esp) ; X32-NEXT: movaps %xmm0, (%esp)
; X32-NEXT: movaps %xmm1, 16(%esp) ; X32-NEXT: movaps %xmm1, 16(%esp)
; X32-NEXT: movsd (%esp), %xmm4 ; X32-NEXT: movsd (%esp), %xmm4
; X32-NEXT: movsd 8(%esp), %xmm5 ; X32-NEXT: movsd 8(%esp), %xmm5
; X32-NEXT: movsd 16(%esp), %xmm6 ; X32-NEXT: movsd 16(%esp), %xmm6
; X32-NEXT: movsd 24(%esp), %xmm7 ; X32-NEXT: movsd 24(%esp), %xmm7
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llvm/test/CodeGen/X86/cmov-fp.ll

Show First 20 Lines • Show All 1,051 Lines • ▼ Show 20 Lines; NOCMOV-NEXT: retl
%sel = select i1 %cmp, float 99.0, float %x %sel = select i1 %cmp, float 99.0, float %x
ret float %sel ret float %sel
} }
define x86_fp80 @test17(i32 %a, i32 %b, x86_fp80 %x) nounwind { define x86_fp80 @test17(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; SSE-LABEL: test17: ; SSE-LABEL: test17:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: fldt {{[0-9]+}}(%esp) ; SSE-NEXT: fldt {{[0-9]+}}(%esp)
; SSE-NEXT: flds {{\.LCPI.*}}
; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: flds {{\.LCPI.*}}
; SSE-NEXT: fxch %st(1) ; SSE-NEXT: fxch %st(1)
; SSE-NEXT: fcmovnbe %st(1), %st ; SSE-NEXT: fcmovnbe %st(1), %st
; SSE-NEXT: fstp %st(1) ; SSE-NEXT: fstp %st(1)
; SSE-NEXT: retl ; SSE-NEXT: retl
; ;
; NOSSE2-LABEL: test17: ; NOSSE2-LABEL: test17:
; NOSSE2: # %bb.0: ; NOSSE2: # %bb.0:
; NOSSE2-NEXT: fldt {{[0-9]+}}(%esp) ; NOSSE2-NEXT: fldt {{[0-9]+}}(%esp)
Show All 34 Lines; NOCMOV-NEXT: retl
%sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
ret x86_fp80 %sel ret x86_fp80 %sel
} }
define x86_fp80 @test18(i32 %a, i32 %b, x86_fp80 %x) nounwind { define x86_fp80 @test18(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; SSE-LABEL: test18: ; SSE-LABEL: test18:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: fldt {{[0-9]+}}(%esp) ; SSE-NEXT: fldt {{[0-9]+}}(%esp)
; SSE-NEXT: flds {{\.LCPI.*}}
; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: flds {{\.LCPI.*}}
; SSE-NEXT: fxch %st(1) ; SSE-NEXT: fxch %st(1)
; SSE-NEXT: fcmovnb %st(1), %st ; SSE-NEXT: fcmovnb %st(1), %st
; SSE-NEXT: fstp %st(1) ; SSE-NEXT: fstp %st(1)
; SSE-NEXT: retl ; SSE-NEXT: retl
; ;
; NOSSE2-LABEL: test18: ; NOSSE2-LABEL: test18:
; NOSSE2: # %bb.0: ; NOSSE2: # %bb.0:
; NOSSE2-NEXT: fldt {{[0-9]+}}(%esp) ; NOSSE2-NEXT: fldt {{[0-9]+}}(%esp)
Show All 34 Lines; NOCMOV-NEXT: retl
%sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
ret x86_fp80 %sel ret x86_fp80 %sel
} }
define x86_fp80 @test19(i32 %a, i32 %b, x86_fp80 %x) nounwind { define x86_fp80 @test19(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; SSE-LABEL: test19: ; SSE-LABEL: test19:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: fldt {{[0-9]+}}(%esp) ; SSE-NEXT: fldt {{[0-9]+}}(%esp)
; SSE-NEXT: flds {{\.LCPI.*}}
; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: flds {{\.LCPI.*}}
; SSE-NEXT: fxch %st(1) ; SSE-NEXT: fxch %st(1)
; SSE-NEXT: fcmovb %st(1), %st ; SSE-NEXT: fcmovb %st(1), %st
; SSE-NEXT: fstp %st(1) ; SSE-NEXT: fstp %st(1)
; SSE-NEXT: retl ; SSE-NEXT: retl
; ;
; NOSSE2-LABEL: test19: ; NOSSE2-LABEL: test19:
; NOSSE2: # %bb.0: ; NOSSE2: # %bb.0:
; NOSSE2-NEXT: fldt {{[0-9]+}}(%esp) ; NOSSE2-NEXT: fldt {{[0-9]+}}(%esp)
Show All 34 Lines; NOCMOV-NEXT: retl
%sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
ret x86_fp80 %sel ret x86_fp80 %sel
} }
define x86_fp80 @test20(i32 %a, i32 %b, x86_fp80 %x) nounwind { define x86_fp80 @test20(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; SSE-LABEL: test20: ; SSE-LABEL: test20:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: fldt {{[0-9]+}}(%esp) ; SSE-NEXT: fldt {{[0-9]+}}(%esp)
; SSE-NEXT: flds {{\.LCPI.*}}
; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: flds {{\.LCPI.*}}
; SSE-NEXT: fxch %st(1) ; SSE-NEXT: fxch %st(1)
; SSE-NEXT: fcmovbe %st(1), %st ; SSE-NEXT: fcmovbe %st(1), %st
; SSE-NEXT: fstp %st(1) ; SSE-NEXT: fstp %st(1)
; SSE-NEXT: retl ; SSE-NEXT: retl
; ;
; NOSSE2-LABEL: test20: ; NOSSE2-LABEL: test20:
; NOSSE2: # %bb.0: ; NOSSE2: # %bb.0:
; NOSSE2-NEXT: fldt {{[0-9]+}}(%esp) ; NOSSE2-NEXT: fldt {{[0-9]+}}(%esp)
Show All 34 Lines; NOCMOV-NEXT: retl
%sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
ret x86_fp80 %sel ret x86_fp80 %sel
} }
define x86_fp80 @test21(i32 %a, i32 %b, x86_fp80 %x) nounwind { define x86_fp80 @test21(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; SSE-LABEL: test21: ; SSE-LABEL: test21:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: fldt {{[0-9]+}}(%esp) ; SSE-NEXT: fldt {{[0-9]+}}(%esp)
; SSE-NEXT: flds {{\.LCPI.*}}
; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: fxch %st(1)
; SSE-NEXT: setg %al ; SSE-NEXT: setg %al
; SSE-NEXT: testb %al, %al ; SSE-NEXT: testb %al, %al
; SSE-NEXT: flds {{\.LCPI.*}}
; SSE-NEXT: fxch %st(1)
; SSE-NEXT: fcmovne %st(1), %st ; SSE-NEXT: fcmovne %st(1), %st
; SSE-NEXT: fstp %st(1) ; SSE-NEXT: fstp %st(1)
; SSE-NEXT: retl ; SSE-NEXT: retl
; ;
; NOSSE2-LABEL: test21: ; NOSSE2-LABEL: test21:
; NOSSE2: # %bb.0: ; NOSSE2: # %bb.0:
; NOSSE2-NEXT: fldt {{[0-9]+}}(%esp) ; NOSSE2-NEXT: fldt {{[0-9]+}}(%esp)
; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
Show All 38 Lines; We don't emit a branch for fp80, why?
%sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
ret x86_fp80 %sel ret x86_fp80 %sel
} }
define x86_fp80 @test22(i32 %a, i32 %b, x86_fp80 %x) nounwind { define x86_fp80 @test22(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; SSE-LABEL: test22: ; SSE-LABEL: test22:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: fldt {{[0-9]+}}(%esp) ; SSE-NEXT: fldt {{[0-9]+}}(%esp)
; SSE-NEXT: flds {{\.LCPI.*}}
; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: fxch %st(1)
; SSE-NEXT: setge %al ; SSE-NEXT: setge %al
; SSE-NEXT: testb %al, %al ; SSE-NEXT: testb %al, %al
; SSE-NEXT: flds {{\.LCPI.*}}
; SSE-NEXT: fxch %st(1)
; SSE-NEXT: fcmovne %st(1), %st ; SSE-NEXT: fcmovne %st(1), %st
; SSE-NEXT: fstp %st(1) ; SSE-NEXT: fstp %st(1)
; SSE-NEXT: retl ; SSE-NEXT: retl
; ;
; NOSSE2-LABEL: test22: ; NOSSE2-LABEL: test22:
; NOSSE2: # %bb.0: ; NOSSE2: # %bb.0:
; NOSSE2-NEXT: fldt {{[0-9]+}}(%esp) ; NOSSE2-NEXT: fldt {{[0-9]+}}(%esp)
; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
Show All 37 Lines; NOCMOV-NEXT: retl
%sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
ret x86_fp80 %sel ret x86_fp80 %sel
} }
define x86_fp80 @test23(i32 %a, i32 %b, x86_fp80 %x) nounwind { define x86_fp80 @test23(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; SSE-LABEL: test23: ; SSE-LABEL: test23:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: fldt {{[0-9]+}}(%esp) ; SSE-NEXT: fldt {{[0-9]+}}(%esp)
; SSE-NEXT: flds {{\.LCPI.*}}
; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: fxch %st(1)
; SSE-NEXT: setl %al ; SSE-NEXT: setl %al
; SSE-NEXT: testb %al, %al ; SSE-NEXT: testb %al, %al
; SSE-NEXT: flds {{\.LCPI.*}}
; SSE-NEXT: fxch %st(1)
; SSE-NEXT: fcmovne %st(1), %st ; SSE-NEXT: fcmovne %st(1), %st
; SSE-NEXT: fstp %st(1) ; SSE-NEXT: fstp %st(1)
; SSE-NEXT: retl ; SSE-NEXT: retl
; ;
; NOSSE2-LABEL: test23: ; NOSSE2-LABEL: test23:
; NOSSE2: # %bb.0: ; NOSSE2: # %bb.0:
; NOSSE2-NEXT: fldt {{[0-9]+}}(%esp) ; NOSSE2-NEXT: fldt {{[0-9]+}}(%esp)
; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
Show All 37 Lines; NOCMOV-NEXT: retl
%sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
ret x86_fp80 %sel ret x86_fp80 %sel
} }
define x86_fp80 @test24(i32 %a, i32 %b, x86_fp80 %x) nounwind { define x86_fp80 @test24(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; SSE-LABEL: test24: ; SSE-LABEL: test24:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: fldt {{[0-9]+}}(%esp) ; SSE-NEXT: fldt {{[0-9]+}}(%esp)
; SSE-NEXT: flds {{\.LCPI.*}}
; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: fxch %st(1)
; SSE-NEXT: setle %al ; SSE-NEXT: setle %al
; SSE-NEXT: testb %al, %al ; SSE-NEXT: testb %al, %al
; SSE-NEXT: flds {{\.LCPI.*}}
; SSE-NEXT: fxch %st(1)
; SSE-NEXT: fcmovne %st(1), %st ; SSE-NEXT: fcmovne %st(1), %st
; SSE-NEXT: fstp %st(1) ; SSE-NEXT: fstp %st(1)
; SSE-NEXT: retl ; SSE-NEXT: retl
; ;
; NOSSE2-LABEL: test24: ; NOSSE2-LABEL: test24:
; NOSSE2: # %bb.0: ; NOSSE2: # %bb.0:
; NOSSE2-NEXT: fldt {{[0-9]+}}(%esp) ; NOSSE2-NEXT: fldt {{[0-9]+}}(%esp)
; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
Show All 40 Lines

llvm/test/CodeGen/X86/cmpxchg-clobber-flags.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=i386-linux-gnu -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=32-ALL,32-GOOD-RA ; RUN: llc -mtriple=i386-linux-gnu -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=32-ALL,32-GOOD-RA
; RUN: llc -mtriple=i386-linux-gnu -verify-machineinstrs -pre-RA-sched=fast %s -o - | FileCheck %s --check-prefixes=32-ALL,32-FAST-RA ; RUN: llc -mtriple=i386-linux-gnu -verify-machineinstrs -pre-RA-sched=fast %s -o - | FileCheck %s --check-prefixes=32-ALL,32-FAST-RA
; RUN: llc -mtriple=x86_64-linux-gnu -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=64-ALL,64-GOOD-RA ; RUN: llc -mtriple=x86_64-linux-gnu -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=64-ALL,64-GOOD-RA
; RUN: llc -mtriple=x86_64-linux-gnu -verify-machineinstrs -pre-RA-sched=fast %s -o - | FileCheck %s --check-prefixes=64-ALL,64-FAST-RA ; RUN: llc -mtriple=x86_64-linux-gnu -verify-machineinstrs -pre-RA-sched=fast %s -o - | FileCheck %s --check-prefixes=64-ALL,64-FAST-RA
; RUN: llc -mtriple=x86_64-linux-gnu -verify-machineinstrs -mattr=+sahf %s -o - | FileCheck %s --check-prefixes=64-ALL,64-GOOD-RA-SAHF ; RUN: llc -mtriple=x86_64-linux-gnu -verify-machineinstrs -mattr=+sahf %s -o - | FileCheck %s --check-prefixes=64-ALL,64-GOOD-RA-SAHF,64-GOOD-RA-SAHF-GENERIC
; RUN: llc -mtriple=x86_64-linux-gnu -verify-machineinstrs -mattr=+sahf -pre-RA-sched=fast %s -o - | FileCheck %s --check-prefixes=64-ALL,64-FAST-RA-SAHF ; RUN: llc -mtriple=x86_64-linux-gnu -verify-machineinstrs -mattr=+sahf -pre-RA-sched=fast %s -o - | FileCheck %s --check-prefixes=64-ALL,64-FAST-RA-SAHF
; RUN: llc -mtriple=x86_64-linux-gnu -verify-machineinstrs -mcpu=corei7 %s -o - | FileCheck %s --check-prefixes=64-ALL,64-GOOD-RA-SAHF ; RUN: llc -mtriple=x86_64-linux-gnu -verify-machineinstrs -mcpu=corei7 %s -o - | FileCheck %s --check-prefixes=64-ALL,64-GOOD-RA-SAHF,64-GOOD-RA-SAHF-COREI7
declare i32 @foo() declare i32 @foo()
declare i32 @bar(i64) declare i32 @bar(i64)
; In the following case when using fast scheduling we get a long chain of ; In the following case when using fast scheduling we get a long chain of
; EFLAGS save/restore due to a sequence of: ; EFLAGS save/restore due to a sequence of:
; cmpxchg8b (implicit-def eflags) ; cmpxchg8b (implicit-def eflags)
; eax = copy eflags ; eax = copy eflags
▲ Show 20 Lines • Show All 229 Lines • ▼ Show 20 Lines
; 32-FAST-RA-NEXT: movl %eax, %esi ; 32-FAST-RA-NEXT: movl %eax, %esi
; 32-FAST-RA-NEXT: .LBB2_2: # %entry ; 32-FAST-RA-NEXT: .LBB2_2: # %entry
; 32-FAST-RA-NEXT: movl %esi, %eax ; 32-FAST-RA-NEXT: movl %esi, %eax
; 32-FAST-RA-NEXT: addl $4, %esp ; 32-FAST-RA-NEXT: addl $4, %esp
; 32-FAST-RA-NEXT: popl %esi ; 32-FAST-RA-NEXT: popl %esi
; 32-FAST-RA-NEXT: popl %ebx ; 32-FAST-RA-NEXT: popl %ebx
; 32-FAST-RA-NEXT: retl ; 32-FAST-RA-NEXT: retl
; ;
; 64-ALL-LABEL: test_feed_cmov: ; 64-GOOD-RA-LABEL: test_feed_cmov:
; 64-ALL: # %bb.0: # %entry ; 64-GOOD-RA: # %bb.0: # %entry
; 64-ALL-NEXT: pushq %rbp ; 64-GOOD-RA-NEXT: pushq %rbp
; 64-ALL-NEXT: pushq %rbx ; 64-GOOD-RA-NEXT: pushq %rbx
; 64-ALL-NEXT: pushq %rax ; 64-GOOD-RA-NEXT: pushq %rax
; 64-ALL-NEXT: movl %edx, %ebx ; 64-GOOD-RA-NEXT: movl %edx, %ebx
; 64-ALL-NEXT: movl %esi, %eax ; 64-GOOD-RA-NEXT: movl %esi, %eax
; 64-ALL-NEXT: lock cmpxchgl %edx, (%rdi) ; 64-GOOD-RA-NEXT: lock cmpxchgl %edx, (%rdi)
; 64-ALL-NEXT: sete %bpl ; 64-GOOD-RA-NEXT: sete %bpl
; 64-ALL-NEXT: callq foo ; 64-GOOD-RA-NEXT: callq foo
; 64-ALL-NEXT: testb %bpl, %bpl ; 64-GOOD-RA-NEXT: testb %bpl, %bpl
; 64-ALL-NEXT: cmovnel %ebx, %eax ; 64-GOOD-RA-NEXT: cmovnel %ebx, %eax
; 64-ALL-NEXT: addq $8, %rsp ; 64-GOOD-RA-NEXT: addq $8, %rsp
; 64-ALL-NEXT: popq %rbx ; 64-GOOD-RA-NEXT: popq %rbx
; 64-ALL-NEXT: popq %rbp ; 64-GOOD-RA-NEXT: popq %rbp
; 64-ALL-NEXT: retq ; 64-GOOD-RA-NEXT: retq
;
; 64-FAST-RA-LABEL: test_feed_cmov:
; 64-FAST-RA: # %bb.0: # %entry
; 64-FAST-RA-NEXT: pushq %rbp
; 64-FAST-RA-NEXT: pushq %rbx
; 64-FAST-RA-NEXT: pushq %rax
; 64-FAST-RA-NEXT: movl %edx, %ebx
; 64-FAST-RA-NEXT: movl %esi, %eax
; 64-FAST-RA-NEXT: lock cmpxchgl %edx, (%rdi)
; 64-FAST-RA-NEXT: sete %bpl
; 64-FAST-RA-NEXT: callq foo
; 64-FAST-RA-NEXT: testb %bpl, %bpl
; 64-FAST-RA-NEXT: cmovnel %ebx, %eax
; 64-FAST-RA-NEXT: addq $8, %rsp
; 64-FAST-RA-NEXT: popq %rbx
; 64-FAST-RA-NEXT: popq %rbp
; 64-FAST-RA-NEXT: retq
;
; 64-GOOD-RA-SAHF-GENERIC-LABEL: test_feed_cmov:
; 64-GOOD-RA-SAHF-GENERIC: # %bb.0: # %entry
; 64-GOOD-RA-SAHF-GENERIC-NEXT: pushq %rbp
; 64-GOOD-RA-SAHF-GENERIC-NEXT: pushq %rbx
; 64-GOOD-RA-SAHF-GENERIC-NEXT: pushq %rax
; 64-GOOD-RA-SAHF-GENERIC-NEXT: movl %edx, %ebx
; 64-GOOD-RA-SAHF-GENERIC-NEXT: movl %esi, %eax
; 64-GOOD-RA-SAHF-GENERIC-NEXT: lock cmpxchgl %edx, (%rdi)
; 64-GOOD-RA-SAHF-GENERIC-NEXT: sete %bpl
; 64-GOOD-RA-SAHF-GENERIC-NEXT: callq foo
; 64-GOOD-RA-SAHF-GENERIC-NEXT: testb %bpl, %bpl
; 64-GOOD-RA-SAHF-GENERIC-NEXT: cmovnel %ebx, %eax
; 64-GOOD-RA-SAHF-GENERIC-NEXT: addq $8, %rsp
; 64-GOOD-RA-SAHF-GENERIC-NEXT: popq %rbx
; 64-GOOD-RA-SAHF-GENERIC-NEXT: popq %rbp
; 64-GOOD-RA-SAHF-GENERIC-NEXT: retq
;
; 64-FAST-RA-SAHF-LABEL: test_feed_cmov:
; 64-FAST-RA-SAHF: # %bb.0: # %entry
; 64-FAST-RA-SAHF-NEXT: pushq %rbp
; 64-FAST-RA-SAHF-NEXT: pushq %rbx
; 64-FAST-RA-SAHF-NEXT: pushq %rax
; 64-FAST-RA-SAHF-NEXT: movl %edx, %ebx
; 64-FAST-RA-SAHF-NEXT: movl %esi, %eax
; 64-FAST-RA-SAHF-NEXT: lock cmpxchgl %edx, (%rdi)
; 64-FAST-RA-SAHF-NEXT: sete %bpl
; 64-FAST-RA-SAHF-NEXT: callq foo
; 64-FAST-RA-SAHF-NEXT: testb %bpl, %bpl
; 64-FAST-RA-SAHF-NEXT: cmovnel %ebx, %eax
; 64-FAST-RA-SAHF-NEXT: addq $8, %rsp
; 64-FAST-RA-SAHF-NEXT: popq %rbx
; 64-FAST-RA-SAHF-NEXT: popq %rbp
; 64-FAST-RA-SAHF-NEXT: retq
;
; 64-GOOD-RA-SAHF-COREI7-LABEL: test_feed_cmov:
; 64-GOOD-RA-SAHF-COREI7: # %bb.0: # %entry
; 64-GOOD-RA-SAHF-COREI7-NEXT: pushq %rbp
; 64-GOOD-RA-SAHF-COREI7-NEXT: pushq %rbx
; 64-GOOD-RA-SAHF-COREI7-NEXT: pushq %rax
; 64-GOOD-RA-SAHF-COREI7-NEXT: movl %esi, %eax
; 64-GOOD-RA-SAHF-COREI7-NEXT: movl %edx, %ebx
; 64-GOOD-RA-SAHF-COREI7-NEXT: lock cmpxchgl %edx, (%rdi)
; 64-GOOD-RA-SAHF-COREI7-NEXT: sete %bpl
; 64-GOOD-RA-SAHF-COREI7-NEXT: callq foo
; 64-GOOD-RA-SAHF-COREI7-NEXT: testb %bpl, %bpl
; 64-GOOD-RA-SAHF-COREI7-NEXT: cmovnel %ebx, %eax
; 64-GOOD-RA-SAHF-COREI7-NEXT: addq $8, %rsp
; 64-GOOD-RA-SAHF-COREI7-NEXT: popq %rbx
; 64-GOOD-RA-SAHF-COREI7-NEXT: popq %rbp
; 64-GOOD-RA-SAHF-COREI7-NEXT: retq
entry: entry:
%res = cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst seq_cst %res = cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst seq_cst
%success = extractvalue { i32, i1 } %res, 1 %success = extractvalue { i32, i1 } %res, 1
%rhs = call i32 @foo() %rhs = call i32 @foo()
%ret = select i1 %success, i32 %new, i32 %rhs %ret = select i1 %success, i32 %new, i32 %rhs
ret i32 %ret ret i32 %ret
} }

llvm/test/CodeGen/X86/cmpxchg8b.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown- -mcpu=core2 | FileCheck %s --check-prefixes=CHECK,X86 ; RUN: llc < %s -mtriple=i686-unknown- -mcpu=core2 | FileCheck %s --check-prefixes=CHECK,X86,X86-CORE2
; RUN: llc < %s -mtriple=x86_64-unknown- -mcpu=core2 | FileCheck %s --check-prefixes=CHECK,X64 ; RUN: llc < %s -mtriple=x86_64-unknown- -mcpu=core2 | FileCheck %s --check-prefixes=CHECK,X64
; RUN: llc < %s -mtriple=i686-unknown- -mcpu=i486 | FileCheck %s --check-prefixes=I486 ; RUN: llc < %s -mtriple=i686-unknown- -mcpu=i486 | FileCheck %s --check-prefixes=I486
; RUN: llc < %s -mtriple=i686-unknown- -mcpu=znver1 | FileCheck %s --check-prefixes=CHECK,X86 ; RUN: llc < %s -mtriple=i686-unknown- -mcpu=znver1 | FileCheck %s --check-prefixes=CHECK,X86,X86-ZNVER1
; Basic 64-bit cmpxchg ; Basic 64-bit cmpxchg
define void @t1(i64* nocapture %p) nounwind ssp { define void @t1(i64* nocapture %p) nounwind ssp {
; X86-LABEL: t1: ; X86-CORE2-LABEL: t1:
; X86: # %bb.0: # %entry ; X86-CORE2: # %bb.0: # %entry
; X86-NEXT: pushl %ebx ; X86-CORE2-NEXT: pushl %ebx
; X86-NEXT: pushl %esi ; X86-CORE2-NEXT: pushl %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-CORE2-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: xorl %eax, %eax ; X86-CORE2-NEXT: movl $1, %ebx
; X86-NEXT: xorl %edx, %edx ; X86-CORE2-NEXT: xorl %eax, %eax
; X86-NEXT: xorl %ecx, %ecx ; X86-CORE2-NEXT: xorl %edx, %edx
; X86-NEXT: movl $1, %ebx ; X86-CORE2-NEXT: xorl %ecx, %ecx
; X86-NEXT: lock cmpxchg8b (%esi) ; X86-CORE2-NEXT: lock cmpxchg8b (%esi)
; X86-NEXT: popl %esi ; X86-CORE2-NEXT: popl %esi
; X86-NEXT: popl %ebx ; X86-CORE2-NEXT: popl %ebx
; X86-NEXT: retl ; X86-CORE2-NEXT: retl
; ;
; X64-LABEL: t1: ; X64-LABEL: t1:
; X64: # %bb.0: # %entry ; X64: # %bb.0: # %entry
; X64-NEXT: movl $1, %ecx ; X64-NEXT: movl $1, %ecx
; X64-NEXT: xorl %eax, %eax ; X64-NEXT: xorl %eax, %eax
; X64-NEXT: lock cmpxchgq %rcx, (%rdi) ; X64-NEXT: lock cmpxchgq %rcx, (%rdi)
; X64-NEXT: retq ; X64-NEXT: retq
; ;
Show All 13 Lines
; I486-NEXT: pushl $1 ; I486-NEXT: pushl $1
; I486-NEXT: pushl %ecx ; I486-NEXT: pushl %ecx
; I486-NEXT: pushl %eax ; I486-NEXT: pushl %eax
; I486-NEXT: calll __atomic_compare_exchange_8 ; I486-NEXT: calll __atomic_compare_exchange_8
; I486-NEXT: addl $24, %esp ; I486-NEXT: addl $24, %esp
; I486-NEXT: movl %ebp, %esp ; I486-NEXT: movl %ebp, %esp
; I486-NEXT: popl %ebp ; I486-NEXT: popl %ebp
; I486-NEXT: retl ; I486-NEXT: retl
;
; X86-ZNVER1-LABEL: t1:
; X86-ZNVER1: # %bb.0: # %entry
; X86-ZNVER1-NEXT: pushl %ebx
; X86-ZNVER1-NEXT: pushl %esi
; X86-ZNVER1-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-ZNVER1-NEXT: xorl %eax, %eax
; X86-ZNVER1-NEXT: xorl %edx, %edx
; X86-ZNVER1-NEXT: xorl %ecx, %ecx
; X86-ZNVER1-NEXT: movl $1, %ebx
; X86-ZNVER1-NEXT: lock cmpxchg8b (%esi)
; X86-ZNVER1-NEXT: popl %esi
; X86-ZNVER1-NEXT: popl %ebx
; X86-ZNVER1-NEXT: retl
entry: entry:
%r = cmpxchg i64* %p, i64 0, i64 1 seq_cst seq_cst %r = cmpxchg i64* %p, i64 0, i64 1 seq_cst seq_cst
ret void ret void
} }

llvm/test/CodeGen/X86/coalescer-commute1.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-apple-darwin -mcpu=corei7-avx -mattr=+sse2 | FileCheck %s ; RUN: llc < %s -mtriple=i686-apple-darwin -mcpu=corei7-avx -mattr=+sse2 | FileCheck %s
; PR1877 ; PR1877
@NNTOT = weak global i32 0 ; <i32*> [#uses=1] @NNTOT = weak global i32 0 ; <i32*> [#uses=1]
@G = weak global float 0.000000e+00 ; <float*> [#uses=1] @G = weak global float 0.000000e+00 ; <float*> [#uses=1]
define void @runcont(i32* %source) nounwind { define void @runcont(i32* %source) nounwind {
; CHECK-LABEL: runcont: ; CHECK-LABEL: runcont:
; CHECK: ## %bb.0: ## %entry ; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl L_NNTOT$non_lazy_ptr, %ecx ; CHECK-NEXT: movl L_NNTOT$non_lazy_ptr, %ecx
; CHECK-NEXT: movl (%ecx), %ecx ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
; CHECK-NEXT: xorl %edx, %edx ; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: movl (%ecx), %ecx
; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: LBB0_1: ## %bb ; CHECK-NEXT: LBB0_1: ## %bb
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vcvtsi2ssl (%eax,%edx,4), %xmm2, %xmm1 ; CHECK-NEXT: vcvtsi2ssl (%eax,%edx,4), %xmm2, %xmm1
; CHECK-NEXT: vaddss %xmm0, %xmm1, %xmm0
; CHECK-NEXT: incl %edx ; CHECK-NEXT: incl %edx
; CHECK-NEXT: vaddss %xmm0, %xmm1, %xmm0
; CHECK-NEXT: cmpl %edx, %ecx ; CHECK-NEXT: cmpl %edx, %ecx
; CHECK-NEXT: jne LBB0_1 ; CHECK-NEXT: jne LBB0_1
; CHECK-NEXT: ## %bb.2: ## %bb13 ; CHECK-NEXT: ## %bb.2: ## %bb13
; CHECK-NEXT: movl L_G$non_lazy_ptr, %eax ; CHECK-NEXT: movl L_G$non_lazy_ptr, %eax
; CHECK-NEXT: vmovss %xmm0, (%eax) ; CHECK-NEXT: vmovss %xmm0, (%eax)
; CHECK-NEXT: retl ; CHECK-NEXT: retl
entry: entry:
%tmp10 = load i32, i32* @NNTOT, align 4 ; <i32> [#uses=1] %tmp10 = load i32, i32* @NNTOT, align 4 ; <i32> [#uses=1]
Show All 17 Lines

llvm/test/CodeGen/X86/combine-or.ll

Show First 20 Lines • Show All 233 Lines • ▼ Show 20 Lines
} }
define <4 x i32> @test18(<4 x i32> %a, <4 x i32> %b) { define <4 x i32> @test18(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test18: ; CHECK-LABEL: test18:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: pxor %xmm2, %xmm2 ; CHECK-NEXT: pxor %xmm2, %xmm2
; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3,4,5,6,7] ; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3,4,5,6,7]
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,0,1,1]
; CHECK-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7] ; CHECK-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7]
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,0,1,1]
; CHECK-NEXT: por %xmm1, %xmm0 ; CHECK-NEXT: por %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 0, i32 4, i32 4> %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 0, i32 4, i32 4>
%shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 4, i32 4, i32 4> %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 4, i32 4, i32 4>
%or = or <4 x i32> %shuf1, %shuf2 %or = or <4 x i32> %shuf1, %shuf2
ret <4 x i32> %or ret <4 x i32> %or
} }
define <4 x i32> @test19(<4 x i32> %a, <4 x i32> %b) { define <4 x i32> @test19(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: test19: ; CHECK-LABEL: test19:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm0[0,0,2,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm0[0,0,2,3]
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,1,2,2]
; CHECK-NEXT: pxor %xmm3, %xmm3 ; CHECK-NEXT: pxor %xmm3, %xmm3
; CHECK-NEXT: pblendw {{.*#+}} xmm2 = xmm3[0,1],xmm2[2,3],xmm3[4,5],xmm2[6,7] ; CHECK-NEXT: pblendw {{.*#+}} xmm2 = xmm3[0,1],xmm2[2,3],xmm3[4,5],xmm2[6,7]
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,1,2,2]
; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm3[2,3],xmm0[4,5,6,7] ; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm3[2,3],xmm0[4,5,6,7]
; CHECK-NEXT: por %xmm2, %xmm0 ; CHECK-NEXT: por %xmm2, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 0, i32 4, i32 3> %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 0, i32 4, i32 3>
%shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 4, i32 2, i32 2> %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 4, i32 2, i32 2>
%or = or <4 x i32> %shuf1, %shuf2 %or = or <4 x i32> %shuf1, %shuf2
ret <4 x i32> %or ret <4 x i32> %or
} }
▲ Show 20 Lines • Show All 223 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/commute-two-addr.ll

Show All 32 Lines
} }
; rdar://8762995 ; rdar://8762995
%0 = type { i64, i32 } %0 = type { i64, i32 }
define %0 @t3(i32 %lb, i8 zeroext %has_lb, i8 zeroext %lb_inclusive, i32 %ub, i8 zeroext %has_ub, i8 zeroext %ub_inclusive) nounwind { define %0 @t3(i32 %lb, i8 zeroext %has_lb, i8 zeroext %lb_inclusive, i32 %ub, i8 zeroext %has_ub, i8 zeroext %ub_inclusive) nounwind {
entry: entry:
; DARWIN-LABEL: t3: ; DARWIN-LABEL: t3:
; DARWIN: shll $8
; DARWIN: shlq $32, %rcx ; DARWIN: shlq $32, %rcx
; DARWIN-NEXT: orq %rcx, %rax ; DARWIN: orq %rcx, %rax
; DARWIN-NEXT: shll $8
; DARWIN-NOT: leaq ; DARWIN-NOT: leaq
%tmp21 = zext i32 %lb to i64 %tmp21 = zext i32 %lb to i64
%tmp23 = zext i32 %ub to i64 %tmp23 = zext i32 %ub to i64
%tmp24 = shl i64 %tmp23, 32 %tmp24 = shl i64 %tmp23, 32
%ins26 = or i64 %tmp24, %tmp21 %ins26 = or i64 %tmp24, %tmp21
%tmp28 = zext i8 %has_lb to i32 %tmp28 = zext i8 %has_lb to i32
%tmp33 = zext i8 %has_ub to i32 %tmp33 = zext i8 %has_ub to i32
%tmp34 = shl i32 %tmp33, 8 %tmp34 = shl i32 %tmp33, 8
Show All 11 Lines

llvm/test/CodeGen/X86/cvtv2f32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-linux-pc -mcpu=corei7 | FileCheck %s --check-prefix=X32 ; RUN: llc < %s -mtriple=i686-linux-pc -mcpu=corei7 | FileCheck %s --check-prefix=X32
; RUN: llc < %s -mtriple=x86_64-linux-pc -mcpu=corei7 | FileCheck %s --check-prefix=X64 ; RUN: llc < %s -mtriple=x86_64-linux-pc -mcpu=corei7 | FileCheck %s --check-prefix=X64
; uitofp <2 x i32> codegen from buildvector or legalization is different but gives the same results ; uitofp <2 x i32> codegen from buildvector or legalization is different but gives the same results
; across the full 0 - 0xFFFFFFFF u32 range. ; across the full 0 - 0xFFFFFFFF u32 range.
define <2 x float> @uitofp_2i32_cvt_buildvector(i32 %x, i32 %y, <2 x float> %v) { define <2 x float> @uitofp_2i32_cvt_buildvector(i32 %x, i32 %y, <2 x float> %v) {
; X32-LABEL: uitofp_2i32_cvt_buildvector: ; X32-LABEL: uitofp_2i32_cvt_buildvector:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; X32-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; X32-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero ; X32-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
; X32-NEXT: orpd %xmm2, %xmm1
; X32-NEXT: subsd %xmm2, %xmm1
; X32-NEXT: cvtsd2ss %xmm1, %xmm1
; X32-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero ; X32-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
; X32-NEXT: orpd %xmm2, %xmm1
; X32-NEXT: orpd %xmm2, %xmm3 ; X32-NEXT: orpd %xmm2, %xmm3
; X32-NEXT: subsd %xmm2, %xmm1
; X32-NEXT: subsd %xmm2, %xmm3 ; X32-NEXT: subsd %xmm2, %xmm3
; X32-NEXT: cvtsd2ss %xmm1, %xmm1
; X32-NEXT: xorps %xmm2, %xmm2 ; X32-NEXT: xorps %xmm2, %xmm2
; X32-NEXT: cvtsd2ss %xmm3, %xmm2 ; X32-NEXT: cvtsd2ss %xmm3, %xmm2
; X32-NEXT: insertps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[2,3] ; X32-NEXT: insertps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[2,3]
; X32-NEXT: mulps %xmm1, %xmm0 ; X32-NEXT: mulps %xmm1, %xmm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: uitofp_2i32_cvt_buildvector: ; X64-LABEL: uitofp_2i32_cvt_buildvector:
; X64: # %bb.0: ; X64: # %bb.0:
Show All 10 Lines; X64-NEXT: retq
%t4 = insertelement <2 x float> %t2, float %t3, i32 1 %t4 = insertelement <2 x float> %t2, float %t3, i32 1
%t5 = fmul <2 x float> %v, %t4 %t5 = fmul <2 x float> %v, %t4
ret <2 x float> %t5 ret <2 x float> %t5
} }
define <2 x float> @uitofp_2i32_buildvector_cvt(i32 %x, i32 %y, <2 x float> %v) { define <2 x float> @uitofp_2i32_buildvector_cvt(i32 %x, i32 %y, <2 x float> %v) {
; X32-LABEL: uitofp_2i32_buildvector_cvt: ; X32-LABEL: uitofp_2i32_buildvector_cvt:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: movdqa {{.*#+}} xmm1 = [4.503599627370496E+15,4.503599627370496E+15]
; X32-NEXT: pmovzxdq {{.*#+}} xmm2 = mem[0],zero,mem[1],zero ; X32-NEXT: pmovzxdq {{.*#+}} xmm2 = mem[0],zero,mem[1],zero
; X32-NEXT: movdqa {{.*#+}} xmm1 = [4.503599627370496E+15,4.503599627370496E+15]
; X32-NEXT: por %xmm1, %xmm2 ; X32-NEXT: por %xmm1, %xmm2
; X32-NEXT: subpd %xmm1, %xmm2 ; X32-NEXT: subpd %xmm1, %xmm2
; X32-NEXT: cvtpd2ps %xmm2, %xmm1 ; X32-NEXT: cvtpd2ps %xmm2, %xmm1
; X32-NEXT: mulps %xmm1, %xmm0 ; X32-NEXT: mulps %xmm1, %xmm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: uitofp_2i32_buildvector_cvt: ; X64-LABEL: uitofp_2i32_buildvector_cvt:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: movdqa {{.*#+}} xmm2 = [4.503599627370496E+15,4.503599627370496E+15]
; X64-NEXT: movd %edi, %xmm1 ; X64-NEXT: movd %edi, %xmm1
; X64-NEXT: pinsrd $1, %esi, %xmm1 ; X64-NEXT: pinsrd $1, %esi, %xmm1
; X64-NEXT: pmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero ; X64-NEXT: pmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
; X64-NEXT: movdqa {{.*#+}} xmm2 = [4.503599627370496E+15,4.503599627370496E+15]
; X64-NEXT: por %xmm2, %xmm1 ; X64-NEXT: por %xmm2, %xmm1
; X64-NEXT: subpd %xmm2, %xmm1 ; X64-NEXT: subpd %xmm2, %xmm1
; X64-NEXT: cvtpd2ps %xmm1, %xmm1 ; X64-NEXT: cvtpd2ps %xmm1, %xmm1
; X64-NEXT: mulps %xmm1, %xmm0 ; X64-NEXT: mulps %xmm1, %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%t1 = insertelement <2 x i32> undef, i32 %x, i32 0 %t1 = insertelement <2 x i32> undef, i32 %x, i32 0
%t2 = insertelement <2 x i32> %t1, i32 %y, i32 1 %t2 = insertelement <2 x i32> %t1, i32 %y, i32 1
%t3 = uitofp <2 x i32> %t2 to <2 x float> %t3 = uitofp <2 x i32> %t2 to <2 x float>
%t4 = fmul <2 x float> %v, %t3 %t4 = fmul <2 x float> %v, %t3
ret <2 x float> %t4 ret <2 x float> %t4
} }
define <2 x float> @uitofp_2i32_legalized(<2 x i32> %in, <2 x float> %v) { define <2 x float> @uitofp_2i32_legalized(<2 x i32> %in, <2 x float> %v) {
; X32-LABEL: uitofp_2i32_legalized: ; X32-LABEL: uitofp_2i32_legalized:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: pmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; X32-NEXT: movdqa {{.*#+}} xmm2 = [4.503599627370496E+15,4.503599627370496E+15] ; X32-NEXT: movdqa {{.*#+}} xmm2 = [4.503599627370496E+15,4.503599627370496E+15]
; X32-NEXT: pmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; X32-NEXT: por %xmm2, %xmm0 ; X32-NEXT: por %xmm2, %xmm0
; X32-NEXT: subpd %xmm2, %xmm0 ; X32-NEXT: subpd %xmm2, %xmm0
; X32-NEXT: cvtpd2ps %xmm0, %xmm0 ; X32-NEXT: cvtpd2ps %xmm0, %xmm0
; X32-NEXT: mulps %xmm1, %xmm0 ; X32-NEXT: mulps %xmm1, %xmm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: uitofp_2i32_legalized: ; X64-LABEL: uitofp_2i32_legalized:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: pmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; X64-NEXT: movdqa {{.*#+}} xmm2 = [4.503599627370496E+15,4.503599627370496E+15] ; X64-NEXT: movdqa {{.*#+}} xmm2 = [4.503599627370496E+15,4.503599627370496E+15]
; X64-NEXT: pmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; X64-NEXT: por %xmm2, %xmm0 ; X64-NEXT: por %xmm2, %xmm0
; X64-NEXT: subpd %xmm2, %xmm0 ; X64-NEXT: subpd %xmm2, %xmm0
; X64-NEXT: cvtpd2ps %xmm0, %xmm0 ; X64-NEXT: cvtpd2ps %xmm0, %xmm0
; X64-NEXT: mulps %xmm1, %xmm0 ; X64-NEXT: mulps %xmm1, %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%t1 = uitofp <2 x i32> %in to <2 x float> %t1 = uitofp <2 x i32> %in to <2 x float>
%t2 = fmul <2 x float> %v, %t1 %t2 = fmul <2 x float> %v, %t1
ret <2 x float> %t2 ret <2 x float> %t2
} }

llvm/test/CodeGen/X86/dagcombine-buildvector.ll

Show All 14 Linesentry:
%tmp7.i = shufflevector <4 x double> %src, <4 x double> undef, <2 x i32> <i32 0, i32 2> %tmp7.i = shufflevector <4 x double> %src, <4 x double> undef, <2 x i32> <i32 0, i32 2>
store <2 x double> %tmp7.i, <2 x double>* %dst store <2 x double> %tmp7.i, <2 x double>* %dst
ret void ret void
} }
define void @test2(<4 x i16>* %src, <4 x i32>* %dest) nounwind { define void @test2(<4 x i16>* %src, <4 x i32>* %dest) nounwind {
; CHECK-LABEL: test2: ; CHECK-LABEL: test2:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: pmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero ; CHECK-NEXT: pmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
; CHECK-NEXT: movdqa %xmm0, (%eax) ; CHECK-NEXT: movdqa %xmm0, (%eax)
; CHECK-NEXT: retl ; CHECK-NEXT: retl
entry: entry:
%tmp1 = load <4 x i16>, <4 x i16>* %src %tmp1 = load <4 x i16>, <4 x i16>* %src
%tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef> %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
%0 = tail call <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16> %tmp3) %0 = tail call <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16> %tmp3)
store <4 x i32> %0, <4 x i32>* %dest store <4 x i32> %0, <4 x i32>* %dest
ret void ret void
} }
declare <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16>) nounwind readnone declare <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16>) nounwind readnone

llvm/test/CodeGen/X86/extractelement-legalization-store-ordering.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=yonah | FileCheck %s ; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=yonah | FileCheck %s
target datalayout = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128" target datalayout = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"
; Make sure we don't break load/store ordering when turning an extractelement ; Make sure we don't break load/store ordering when turning an extractelement
; into loads, off the stack or a previous store. ; into loads, off the stack or a previous store.
; Be very explicit about the ordering/stack offsets. ; Be very explicit about the ordering/stack offsets.
define void @test_extractelement_legalization_storereuse(<4 x i32> %a, i32* nocapture %x, i32* nocapture readonly %y, i32 %i) #0 { define void @test_extractelement_legalization_storereuse(<4 x i32> %a, i32* nocapture %x, i32* nocapture readonly %y, i32 %i) #0 {
; CHECK-LABEL: test_extractelement_legalization_storereuse: ; CHECK-LABEL: test_extractelement_legalization_storereuse:
; CHECK: ## %bb.0: ## %entry ; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: pushl %ebx ; CHECK-NEXT: pushl %ebx
; CHECK-NEXT: pushl %edi ; CHECK-NEXT: pushl %edi
; CHECK-NEXT: pushl %esi ; CHECK-NEXT: pushl %esi
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: paddd (%edx), %xmm0 ; CHECK-NEXT: paddd (%edx), %xmm0
; CHECK-NEXT: shll $4, %ecx
; CHECK-NEXT: movdqa %xmm0, (%edx) ; CHECK-NEXT: movdqa %xmm0, (%edx)
; CHECK-NEXT: movl (%edx), %esi ; CHECK-NEXT: movl (%edx), %esi
; CHECK-NEXT: movl 4(%edx), %edi ; CHECK-NEXT: movl 4(%edx), %edi
; CHECK-NEXT: shll $4, %ecx
; CHECK-NEXT: movl 8(%edx), %ebx ; CHECK-NEXT: movl 8(%edx), %ebx
; CHECK-NEXT: movl 12(%edx), %edx ; CHECK-NEXT: movl 12(%edx), %edx
; CHECK-NEXT: movl %esi, 12(%eax,%ecx) ; CHECK-NEXT: movl %esi, 12(%eax,%ecx)
; CHECK-NEXT: movl %edi, (%eax,%ecx) ; CHECK-NEXT: movl %edi, (%eax,%ecx)
; CHECK-NEXT: movl %ebx, 8(%eax,%ecx) ; CHECK-NEXT: movl %ebx, 8(%eax,%ecx)
; CHECK-NEXT: movl %edx, 4(%eax,%ecx) ; CHECK-NEXT: movl %edx, 4(%eax,%ecx)
; CHECK-NEXT: popl %esi ; CHECK-NEXT: popl %esi
; CHECK-NEXT: popl %edi ; CHECK-NEXT: popl %edi
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llvm/test/CodeGen/X86/fmf-flags.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64 | FileCheck %s -check-prefix=X64 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64 | FileCheck %s -check-prefix=X64
; RUN: llc < %s -mtriple=i686-unknown | FileCheck %s -check-prefix=X86 ; RUN: llc < %s -mtriple=i686-unknown | FileCheck %s -check-prefix=X86
declare float @llvm.sqrt.f32(float %x); declare float @llvm.sqrt.f32(float %x);
define float @fast_recip_sqrt(float %x) { define float @fast_recip_sqrt(float %x) {
; X64-LABEL: fast_recip_sqrt: ; X64-LABEL: fast_recip_sqrt:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: rsqrtss %xmm0, %xmm1 ; X64-NEXT: rsqrtss %xmm0, %xmm1
; X64-NEXT: mulss %xmm1, %xmm0 ; X64-NEXT: mulss %xmm1, %xmm0
; X64-NEXT: mulss %xmm1, %xmm0 ; X64-NEXT: mulss %xmm1, %xmm0
; X64-NEXT: addss {{.*}}(%rip), %xmm0
; X64-NEXT: mulss {{.*}}(%rip), %xmm1 ; X64-NEXT: mulss {{.*}}(%rip), %xmm1
; X64-NEXT: addss {{.*}}(%rip), %xmm0
; X64-NEXT: mulss %xmm1, %xmm0 ; X64-NEXT: mulss %xmm1, %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X86-LABEL: fast_recip_sqrt: ; X86-LABEL: fast_recip_sqrt:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: flds {{[0-9]+}}(%esp) ; X86-NEXT: flds {{[0-9]+}}(%esp)
; X86-NEXT: fsqrt ; X86-NEXT: fsqrt
; X86-NEXT: fld1 ; X86-NEXT: fld1
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define float @not_so_fast_recip_sqrt(float %x) { define float @not_so_fast_recip_sqrt(float %x) {
; X64-LABEL: not_so_fast_recip_sqrt: ; X64-LABEL: not_so_fast_recip_sqrt:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: rsqrtss %xmm0, %xmm1 ; X64-NEXT: rsqrtss %xmm0, %xmm1
; X64-NEXT: sqrtss %xmm0, %xmm2 ; X64-NEXT: sqrtss %xmm0, %xmm2
; X64-NEXT: mulss %xmm1, %xmm0 ; X64-NEXT: mulss %xmm1, %xmm0
; X64-NEXT: mulss %xmm1, %xmm0 ; X64-NEXT: mulss %xmm1, %xmm0
; X64-NEXT: addss {{.*}}(%rip), %xmm0
; X64-NEXT: mulss {{.*}}(%rip), %xmm1 ; X64-NEXT: mulss {{.*}}(%rip), %xmm1
; X64-NEXT: mulss %xmm1, %xmm0 ; X64-NEXT: addss {{.*}}(%rip), %xmm0
; X64-NEXT: movss %xmm2, {{.*}}(%rip) ; X64-NEXT: movss %xmm2, {{.*}}(%rip)
; X64-NEXT: mulss %xmm1, %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X86-LABEL: not_so_fast_recip_sqrt: ; X86-LABEL: not_so_fast_recip_sqrt:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: flds {{[0-9]+}}(%esp) ; X86-NEXT: flds {{[0-9]+}}(%esp)
; X86-NEXT: fsqrt ; X86-NEXT: fsqrt
; X86-NEXT: fld1 ; X86-NEXT: fld1
; X86-NEXT: fdiv %st(1), %st ; X86-NEXT: fdiv %st(1), %st
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llvm/test/CodeGen/X86/fold-load-vec.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=corei7 -mattr=+sse4.1 | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=corei7 -mattr=+sse4.1 | FileCheck %s
; rdar://12721174 ; rdar://12721174
; We should not fold movss into pshufd since pshufd expects m128 while movss ; We should not fold movss into pshufd since pshufd expects m128 while movss
; loads from m32. ; loads from m32.
define void @sample_test(<4 x float>* %source, <2 x float>* %dest) nounwind { define void @sample_test(<4 x float>* %source, <2 x float>* %dest) nounwind {
; CHECK-LABEL: sample_test: ; CHECK-LABEL: sample_test:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subq $24, %rsp ; CHECK-NEXT: subq $24, %rsp
; CHECK-NEXT: xorps %xmm0, %xmm0
; CHECK-NEXT: movq %rdi, {{[0-9]+}}(%rsp) ; CHECK-NEXT: movq %rdi, {{[0-9]+}}(%rsp)
; CHECK-NEXT: movq %rsi, {{[0-9]+}}(%rsp) ; CHECK-NEXT: movq %rsi, {{[0-9]+}}(%rsp)
; CHECK-NEXT: xorps %xmm0, %xmm0
; CHECK-NEXT: movlps %xmm0, (%rsp) ; CHECK-NEXT: movlps %xmm0, (%rsp)
; CHECK-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1] ; CHECK-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; CHECK-NEXT: movlps %xmm0, (%rsp) ; CHECK-NEXT: movlps %xmm0, (%rsp)
; CHECK-NEXT: movlps %xmm0, (%rsi) ; CHECK-NEXT: movlps %xmm0, (%rsi)
; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax ; CHECK-NEXT: movq {{[0-9]+}}(%rsp), %rax
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; CHECK-NEXT: callq ext ; CHECK-NEXT: callq ext
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llvm/test/CodeGen/X86/fold-pcmpeqd-2.ll

Show All 25 Lines
; X32-NEXT: jg LBB0_3 ; X32-NEXT: jg LBB0_3
; X32-NEXT: LBB0_2: ## %ifthen ; X32-NEXT: LBB0_2: ## %ifthen
; X32-NEXT: addl $88, %esp ; X32-NEXT: addl $88, %esp
; X32-NEXT: popl %esi ; X32-NEXT: popl %esi
; X32-NEXT: retl ; X32-NEXT: retl
; X32-NEXT: LBB0_3: ## %forbody ; X32-NEXT: LBB0_3: ## %forbody
; X32-NEXT: movaps {{.*#+}} xmm1 = [1.28E+2,1.28E+2,1.28E+2,1.28E+2] ; X32-NEXT: movaps {{.*#+}} xmm1 = [1.28E+2,1.28E+2,1.28E+2,1.28E+2]
; X32-NEXT: minps LCPI0_3, %xmm1 ; X32-NEXT: minps LCPI0_3, %xmm1
; X32-NEXT: xorl %esi, %esi
; X32-NEXT: xorps %xmm3, %xmm3
; X32-NEXT: cvttps2dq %xmm1, %xmm0 ; X32-NEXT: cvttps2dq %xmm1, %xmm0
; X32-NEXT: cvtdq2ps %xmm0, %xmm0 ; X32-NEXT: cvtdq2ps %xmm0, %xmm0
; X32-NEXT: subps %xmm0, %xmm1 ; X32-NEXT: subps %xmm0, %xmm1
; X32-NEXT: movaps %xmm1, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill ; X32-NEXT: movaps %xmm1, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill
; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload ; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
; X32-NEXT: mulps LCPI0_3, %xmm0 ; X32-NEXT: mulps LCPI0_3, %xmm0
; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill ; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill
; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload ; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
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; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill ; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill
; X32-NEXT: xorps %xmm0, %xmm0 ; X32-NEXT: xorps %xmm0, %xmm0
; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill ; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill
; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload ; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
; X32-NEXT: cmpunordps %xmm0, %xmm0 ; X32-NEXT: cmpunordps %xmm0, %xmm0
; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill ; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill
; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload ; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
; X32-NEXT: minps LCPI0_3, %xmm0 ; X32-NEXT: minps LCPI0_3, %xmm0
; X32-NEXT: movdqa {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 ## 16-byte Reload
; X32-NEXT: movl $0, (%esp)
; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill ; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill
; X32-NEXT: xorps %xmm0, %xmm0 ; X32-NEXT: xorps %xmm0, %xmm0
; X32-NEXT: movaps %xmm0, {{[0-9]+}}(%esp) ; X32-NEXT: movaps %xmm0, {{[0-9]+}}(%esp)
; X32-NEXT: movl $0, (%esp)
; X32-NEXT: xorl %esi, %esi
; X32-NEXT: xorps %xmm3, %xmm3
; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload ; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
; X32-NEXT: movdqa {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 ## 16-byte Reload
; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm2 ## 16-byte Reload ; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm2 ## 16-byte Reload
; X32-NEXT: calll *%esi ; X32-NEXT: calll *%esi
; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload ; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
; X32-NEXT: minps LCPI0_3, %xmm0 ; X32-NEXT: minps LCPI0_3, %xmm0
; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill
; X32-NEXT: pxor %xmm1, %xmm1 ; X32-NEXT: pxor %xmm1, %xmm1
; X32-NEXT: psubd {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 ## 16-byte Folded Reload ; X32-NEXT: psubd {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 ## 16-byte Folded Reload
; X32-NEXT: xorps %xmm3, %xmm3
; X32-NEXT: movaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill
; X32-NEXT: movdqa {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload ; X32-NEXT: movdqa {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
; X32-NEXT: psubd LCPI0_4, %xmm0 ; X32-NEXT: psubd LCPI0_4, %xmm0
; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm2 ## 16-byte Reload
; X32-NEXT: movl $0, (%esp)
; X32-NEXT: movdqa %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill ; X32-NEXT: movdqa %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill
; X32-NEXT: movdqa {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload ; X32-NEXT: movdqa {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
; X32-NEXT: por %xmm1, %xmm0 ; X32-NEXT: por %xmm1, %xmm0
; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 ## 16-byte Reload
; X32-NEXT: movdqa %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill ; X32-NEXT: movdqa %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) ## 16-byte Spill
; X32-NEXT: pxor %xmm0, %xmm0 ; X32-NEXT: pxor %xmm0, %xmm0
; X32-NEXT: movdqa %xmm0, {{[0-9]+}}(%esp) ; X32-NEXT: movdqa %xmm0, {{[0-9]+}}(%esp)
; X32-NEXT: movl $0, (%esp)
; X32-NEXT: xorps %xmm3, %xmm3
; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload ; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 ## 16-byte Reload
; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm1 ## 16-byte Reload
; X32-NEXT: movaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm2 ## 16-byte Reload
; X32-NEXT: calll *%esi ; X32-NEXT: calll *%esi
; X32-NEXT: ud2 ; X32-NEXT: ud2
; ;
; X64-LABEL: program_1: ; X64-LABEL: program_1:
; X64: ## %bb.0: ## %entry ; X64: ## %bb.0: ## %entry
; X64-NEXT: pushq %rbx ; X64-NEXT: pushq %rbx
; X64-NEXT: subq $64, %rsp ; X64-NEXT: subq $64, %rsp
; X64-NEXT: cmpl $0, 0 ; X64-NEXT: cmpl $0, 0
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llvm/test/CodeGen/X86/fp-load-trunc.ll

Show First 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
} }
define <8 x float> @test4(<8 x double>* %p) nounwind { define <8 x float> @test4(<8 x double>* %p) nounwind {
; CHECK-LABEL: test4: ; CHECK-LABEL: test4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: cvtpd2ps 16(%eax), %xmm1 ; CHECK-NEXT: cvtpd2ps 16(%eax), %xmm1
; CHECK-NEXT: cvtpd2ps (%eax), %xmm0 ; CHECK-NEXT: cvtpd2ps (%eax), %xmm0
; CHECK-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; CHECK-NEXT: cvtpd2ps 48(%eax), %xmm2 ; CHECK-NEXT: cvtpd2ps 48(%eax), %xmm2
; CHECK-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; CHECK-NEXT: cvtpd2ps 32(%eax), %xmm1 ; CHECK-NEXT: cvtpd2ps 32(%eax), %xmm1
; CHECK-NEXT: unpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0] ; CHECK-NEXT: unpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; CHECK-NEXT: retl ; CHECK-NEXT: retl
; ;
; AVX-LABEL: test4: ; AVX-LABEL: test4:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: movl {{[0-9]+}}(%esp), %eax ; AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
; AVX-NEXT: vcvtpd2psy (%eax), %xmm0 ; AVX-NEXT: vcvtpd2psy (%eax), %xmm0
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llvm/test/CodeGen/X86/fp-trunc.ll

Show First 20 Lines • Show All 55 Lines • ▼ Show 20 Lines; AVX-NEXT: retl
%y = fptrunc <4 x double> %x to <4 x float> %y = fptrunc <4 x double> %x to <4 x float>
ret <4 x float> %y ret <4 x float> %y
} }
define <8 x float> @test4(<8 x double> %x) nounwind { define <8 x float> @test4(<8 x double> %x) nounwind {
; CHECK-LABEL: test4: ; CHECK-LABEL: test4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: subl $12, %esp ; CHECK-NEXT: subl $12, %esp
; CHECK-NEXT: cvtpd2ps {{[0-9]+}}(%esp), %xmm3
; CHECK-NEXT: cvtpd2ps %xmm1, %xmm1 ; CHECK-NEXT: cvtpd2ps %xmm1, %xmm1
; CHECK-NEXT: cvtpd2ps %xmm0, %xmm0 ; CHECK-NEXT: cvtpd2ps %xmm0, %xmm0
; CHECK-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; CHECK-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; CHECK-NEXT: cvtpd2ps %xmm2, %xmm1 ; CHECK-NEXT: cvtpd2ps %xmm2, %xmm1
; CHECK-NEXT: cvtpd2ps {{[0-9]+}}(%esp), %xmm2 ; CHECK-NEXT: unpcklpd {{.*#+}} xmm1 = xmm1[0],xmm3[0]
; CHECK-NEXT: unpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; CHECK-NEXT: addl $12, %esp ; CHECK-NEXT: addl $12, %esp
; CHECK-NEXT: retl ; CHECK-NEXT: retl
; ;
; AVX-LABEL: test4: ; AVX-LABEL: test4:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vcvtpd2ps %ymm0, %xmm0 ; AVX-NEXT: vcvtpd2ps %ymm0, %xmm0
; AVX-NEXT: vcvtpd2ps %ymm1, %xmm1 ; AVX-NEXT: vcvtpd2ps %ymm1, %xmm1
; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX-NEXT: retl ; AVX-NEXT: retl
%y = fptrunc <8 x double> %x to <8 x float> %y = fptrunc <8 x double> %x to <8 x float>
ret <8 x float> %y ret <8 x float> %y
} }

llvm/test/CodeGen/X86/fp128-i128.ll

Show First 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; u.bits.manh = n; ; u.bits.manh = n;
; w = u.e; ; w = u.e;
; foo(w); ; foo(w);
; } ; }
define void @TestUnionLD1(fp128 %s, i64 %n) #0 { define void @TestUnionLD1(fp128 %s, i64 %n) #0 {
; SSE-LABEL: TestUnionLD1: ; SSE-LABEL: TestUnionLD1:
; SSE: # %bb.0: # %entry ; SSE: # %bb.0: # %entry
; SSE-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) ; SSE-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
; SSE-NEXT: movabsq $281474976710655, %rdx # imm = 0xFFFFFFFFFFFF
; SSE-NEXT: movzwl -{{[0-9]+}}(%rsp), %eax ; SSE-NEXT: movzwl -{{[0-9]+}}(%rsp), %eax
; SSE-NEXT: shlq $48, %rax
; SSE-NEXT: movq -{{[0-9]+}}(%rsp), %rcx ; SSE-NEXT: movq -{{[0-9]+}}(%rsp), %rcx
; SSE-NEXT: movabsq $281474976710655, %rdx # imm = 0xFFFFFFFFFFFF
; SSE-NEXT: andq %rdi, %rdx ; SSE-NEXT: andq %rdi, %rdx
; SSE-NEXT: orq %rax, %rdx ; SSE-NEXT: shlq $48, %rax
; SSE-NEXT: movq %rcx, -{{[0-9]+}}(%rsp) ; SSE-NEXT: movq %rcx, -{{[0-9]+}}(%rsp)
; SSE-NEXT: orq %rax, %rdx
; SSE-NEXT: movq %rdx, -{{[0-9]+}}(%rsp) ; SSE-NEXT: movq %rdx, -{{[0-9]+}}(%rsp)
; SSE-NEXT: movaps -{{[0-9]+}}(%rsp), %xmm0 ; SSE-NEXT: movaps -{{[0-9]+}}(%rsp), %xmm0
; SSE-NEXT: jmp foo # TAILCALL ; SSE-NEXT: jmp foo # TAILCALL
; ;
; AVX-LABEL: TestUnionLD1: ; AVX-LABEL: TestUnionLD1:
; AVX: # %bb.0: # %entry ; AVX: # %bb.0: # %entry
; AVX-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp) ; AVX-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)
; AVX-NEXT: movabsq $281474976710655, %rdx # imm = 0xFFFFFFFFFFFF
; AVX-NEXT: movzwl -{{[0-9]+}}(%rsp), %eax ; AVX-NEXT: movzwl -{{[0-9]+}}(%rsp), %eax
; AVX-NEXT: shlq $48, %rax
; AVX-NEXT: movq -{{[0-9]+}}(%rsp), %rcx ; AVX-NEXT: movq -{{[0-9]+}}(%rsp), %rcx
; AVX-NEXT: movabsq $281474976710655, %rdx # imm = 0xFFFFFFFFFFFF
; AVX-NEXT: andq %rdi, %rdx ; AVX-NEXT: andq %rdi, %rdx
; AVX-NEXT: orq %rax, %rdx ; AVX-NEXT: shlq $48, %rax
; AVX-NEXT: movq %rcx, -{{[0-9]+}}(%rsp) ; AVX-NEXT: movq %rcx, -{{[0-9]+}}(%rsp)
; AVX-NEXT: orq %rax, %rdx
; AVX-NEXT: movq %rdx, -{{[0-9]+}}(%rsp) ; AVX-NEXT: movq %rdx, -{{[0-9]+}}(%rsp)
; AVX-NEXT: vmovaps -{{[0-9]+}}(%rsp), %xmm0 ; AVX-NEXT: vmovaps -{{[0-9]+}}(%rsp), %xmm0
; AVX-NEXT: jmp foo # TAILCALL ; AVX-NEXT: jmp foo # TAILCALL
entry: entry:
%0 = bitcast fp128 %s to i128 %0 = bitcast fp128 %s to i128
%1 = zext i64 %n to i128 %1 = zext i64 %n to i128
%bf.value = shl nuw i128 %1, 64 %bf.value = shl nuw i128 %1, 64
%bf.shl = and i128 %bf.value, 5192296858534809181786422619668480 %bf.shl = and i128 %bf.value, 5192296858534809181786422619668480
Show All 13 Lines
; w = u.e; ; w = u.e;
; return w; ; return w;
; } ; }
define fp128 @TestUnionLD2(fp128 %s) #0 { define fp128 @TestUnionLD2(fp128 %s) #0 {
; SSE-LABEL: TestUnionLD2: ; SSE-LABEL: TestUnionLD2:
; SSE: # %bb.0: # %entry ; SSE: # %bb.0: # %entry
; SSE-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) ; SSE-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
; SSE-NEXT: movq -{{[0-9]+}}(%rsp), %rax ; SSE-NEXT: movq -{{[0-9]+}}(%rsp), %rax
; SSE-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
; SSE-NEXT: movq $0, -{{[0-9]+}}(%rsp) ; SSE-NEXT: movq $0, -{{[0-9]+}}(%rsp)
; SSE-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
; SSE-NEXT: movaps -{{[0-9]+}}(%rsp), %xmm0 ; SSE-NEXT: movaps -{{[0-9]+}}(%rsp), %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: TestUnionLD2: ; AVX-LABEL: TestUnionLD2:
; AVX: # %bb.0: # %entry ; AVX: # %bb.0: # %entry
; AVX-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp) ; AVX-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)
; AVX-NEXT: movq -{{[0-9]+}}(%rsp), %rax ; AVX-NEXT: movq -{{[0-9]+}}(%rsp), %rax
; AVX-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
; AVX-NEXT: movq $0, -{{[0-9]+}}(%rsp) ; AVX-NEXT: movq $0, -{{[0-9]+}}(%rsp)
; AVX-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
; AVX-NEXT: vmovaps -{{[0-9]+}}(%rsp), %xmm0 ; AVX-NEXT: vmovaps -{{[0-9]+}}(%rsp), %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
entry: entry:
%0 = bitcast fp128 %s to i128 %0 = bitcast fp128 %s to i128
%bf.clear = and i128 %0, -18446744073709551616 %bf.clear = and i128 %0, -18446744073709551616
%1 = bitcast i128 %bf.clear to fp128 %1 = bitcast i128 %bf.clear to fp128
ret fp128 %1 ret fp128 %1
} }
; C code: ; C code:
; __float128 TestI128_1(__float128 x) ; __float128 TestI128_1(__float128 x)
; { ; {
; union IEEEl2bits z; ; union IEEEl2bits z;
; z.e = x; ; z.e = x;
; z.bits.sign = 0; ; z.bits.sign = 0;
; return (z.e < 0.1L) ? 1.0L : 2.0L; ; return (z.e < 0.1L) ? 1.0L : 2.0L;
; } ; }
define fp128 @TestI128_1(fp128 %x) #0 { define fp128 @TestI128_1(fp128 %x) #0 {
; SSE-LABEL: TestI128_1: ; SSE-LABEL: TestI128_1:
; SSE: # %bb.0: # %entry ; SSE: # %bb.0: # %entry
; SSE-NEXT: subq $40, %rsp ; SSE-NEXT: subq $40, %rsp
; SSE-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp) ; SSE-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
; SSE-NEXT: movabsq $9223372036854775807, %rax # imm = 0x7FFFFFFFFFFFFFFF ; SSE-NEXT: movabsq $9223372036854775807, %rax # imm = 0x7FFFFFFFFFFFFFFF
; SSE-NEXT: movaps {{.*}}(%rip), %xmm1
; SSE-NEXT: andq {{[0-9]+}}(%rsp), %rax ; SSE-NEXT: andq {{[0-9]+}}(%rsp), %rax
; SSE-NEXT: movq {{[0-9]+}}(%rsp), %rcx ; SSE-NEXT: movq {{[0-9]+}}(%rsp), %rcx
; SSE-NEXT: movq %rax, {{[0-9]+}}(%rsp)
; SSE-NEXT: movq %rcx, (%rsp) ; SSE-NEXT: movq %rcx, (%rsp)
; SSE-NEXT: movq %rax, {{[0-9]+}}(%rsp)
; SSE-NEXT: movaps (%rsp), %xmm0 ; SSE-NEXT: movaps (%rsp), %xmm0
; SSE-NEXT: movaps {{.*}}(%rip), %xmm1
; SSE-NEXT: callq __lttf2 ; SSE-NEXT: callq __lttf2
; SSE-NEXT: xorl %ecx, %ecx ; SSE-NEXT: xorl %ecx, %ecx
; SSE-NEXT: testl %eax, %eax ; SSE-NEXT: testl %eax, %eax
; SSE-NEXT: sets %cl ; SSE-NEXT: sets %cl
; SSE-NEXT: shlq $4, %rcx ; SSE-NEXT: shlq $4, %rcx
; SSE-NEXT: movaps {{\.LCPI.*}}(%rcx), %xmm0 ; SSE-NEXT: movaps {{\.LCPI.*}}(%rcx), %xmm0
; SSE-NEXT: addq $40, %rsp ; SSE-NEXT: addq $40, %rsp
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: TestI128_1: ; AVX-LABEL: TestI128_1:
; AVX: # %bb.0: # %entry ; AVX: # %bb.0: # %entry
; AVX-NEXT: subq $40, %rsp ; AVX-NEXT: subq $40, %rsp
; AVX-NEXT: vmovaps %xmm0, {{[0-9]+}}(%rsp) ; AVX-NEXT: vmovaps %xmm0, {{[0-9]+}}(%rsp)
; AVX-NEXT: movabsq $9223372036854775807, %rax # imm = 0x7FFFFFFFFFFFFFFF ; AVX-NEXT: movabsq $9223372036854775807, %rax # imm = 0x7FFFFFFFFFFFFFFF
; AVX-NEXT: vmovaps {{.*}}(%rip), %xmm1
; AVX-NEXT: andq {{[0-9]+}}(%rsp), %rax ; AVX-NEXT: andq {{[0-9]+}}(%rsp), %rax
; AVX-NEXT: movq {{[0-9]+}}(%rsp), %rcx ; AVX-NEXT: movq {{[0-9]+}}(%rsp), %rcx
; AVX-NEXT: movq %rax, {{[0-9]+}}(%rsp)
; AVX-NEXT: movq %rcx, (%rsp) ; AVX-NEXT: movq %rcx, (%rsp)
; AVX-NEXT: movq %rax, {{[0-9]+}}(%rsp)
; AVX-NEXT: vmovaps (%rsp), %xmm0 ; AVX-NEXT: vmovaps (%rsp), %xmm0
; AVX-NEXT: vmovaps {{.*}}(%rip), %xmm1
; AVX-NEXT: callq __lttf2 ; AVX-NEXT: callq __lttf2
; AVX-NEXT: xorl %ecx, %ecx ; AVX-NEXT: xorl %ecx, %ecx
; AVX-NEXT: testl %eax, %eax ; AVX-NEXT: testl %eax, %eax
; AVX-NEXT: sets %cl ; AVX-NEXT: sets %cl
; AVX-NEXT: shlq $4, %rcx ; AVX-NEXT: shlq $4, %rcx
; AVX-NEXT: vmovaps {{\.LCPI.*}}(%rcx), %xmm0 ; AVX-NEXT: vmovaps {{\.LCPI.*}}(%rcx), %xmm0
; AVX-NEXT: addq $40, %rsp ; AVX-NEXT: addq $40, %rsp
; AVX-NEXT: retq ; AVX-NEXT: retq
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
; } ; }
; return (u.e); ; return (u.e);
; } ; }
define fp128 @TestI128_3(fp128 %x, i32* nocapture readnone %ex) #0 { define fp128 @TestI128_3(fp128 %x, i32* nocapture readnone %ex) #0 {
; SSE-LABEL: TestI128_3: ; SSE-LABEL: TestI128_3:
; SSE: # %bb.0: # %entry ; SSE: # %bb.0: # %entry
; SSE-NEXT: subq $56, %rsp ; SSE-NEXT: subq $56, %rsp
; SSE-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp) ; SSE-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
; SSE-NEXT: movq {{[0-9]+}}(%rsp), %rax
; SSE-NEXT: movabsq $9223090561878065152, %rcx # imm = 0x7FFF000000000000 ; SSE-NEXT: movabsq $9223090561878065152, %rcx # imm = 0x7FFF000000000000
; SSE-NEXT: movq {{[0-9]+}}(%rsp), %rax
; SSE-NEXT: testq %rcx, %rax ; SSE-NEXT: testq %rcx, %rax
; SSE-NEXT: je .LBB4_2 ; SSE-NEXT: je .LBB4_2
; SSE-NEXT: # %bb.1: ; SSE-NEXT: # %bb.1:
; SSE-NEXT: movq {{[0-9]+}}(%rsp), %rcx ; SSE-NEXT: movq {{[0-9]+}}(%rsp), %rcx
; SSE-NEXT: jmp .LBB4_3 ; SSE-NEXT: jmp .LBB4_3
; SSE-NEXT: .LBB4_2: # %if.then ; SSE-NEXT: .LBB4_2: # %if.then
; SSE-NEXT: movaps {{.*}}(%rip), %xmm1 ; SSE-NEXT: movaps {{.*}}(%rip), %xmm1
; SSE-NEXT: callq __multf3 ; SSE-NEXT: callq __multf3
; SSE-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp) ; SSE-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
; SSE-NEXT: movq {{[0-9]+}}(%rsp), %rcx
; SSE-NEXT: movabsq $-9223090561878065153, %rdx # imm = 0x8000FFFFFFFFFFFF ; SSE-NEXT: movabsq $-9223090561878065153, %rdx # imm = 0x8000FFFFFFFFFFFF
; SSE-NEXT: andq {{[0-9]+}}(%rsp), %rdx
; SSE-NEXT: movabsq $4611123068473966592, %rax # imm = 0x3FFE000000000000 ; SSE-NEXT: movabsq $4611123068473966592, %rax # imm = 0x3FFE000000000000
; SSE-NEXT: andq {{[0-9]+}}(%rsp), %rdx
; SSE-NEXT: movq {{[0-9]+}}(%rsp), %rcx
; SSE-NEXT: orq %rdx, %rax ; SSE-NEXT: orq %rdx, %rax
; SSE-NEXT: .LBB4_3: # %if.end ; SSE-NEXT: .LBB4_3: # %if.end
; SSE-NEXT: movq %rcx, (%rsp) ; SSE-NEXT: movq %rcx, (%rsp)
; SSE-NEXT: movq %rax, {{[0-9]+}}(%rsp) ; SSE-NEXT: movq %rax, {{[0-9]+}}(%rsp)
; SSE-NEXT: movaps (%rsp), %xmm0 ; SSE-NEXT: movaps (%rsp), %xmm0
; SSE-NEXT: addq $56, %rsp ; SSE-NEXT: addq $56, %rsp
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: TestI128_3: ; AVX-LABEL: TestI128_3:
; AVX: # %bb.0: # %entry ; AVX: # %bb.0: # %entry
; AVX-NEXT: subq $56, %rsp ; AVX-NEXT: subq $56, %rsp
; AVX-NEXT: vmovaps %xmm0, {{[0-9]+}}(%rsp) ; AVX-NEXT: vmovaps %xmm0, {{[0-9]+}}(%rsp)
; AVX-NEXT: movq {{[0-9]+}}(%rsp), %rax
; AVX-NEXT: movabsq $9223090561878065152, %rcx # imm = 0x7FFF000000000000 ; AVX-NEXT: movabsq $9223090561878065152, %rcx # imm = 0x7FFF000000000000
; AVX-NEXT: movq {{[0-9]+}}(%rsp), %rax
; AVX-NEXT: testq %rcx, %rax ; AVX-NEXT: testq %rcx, %rax
; AVX-NEXT: je .LBB4_2 ; AVX-NEXT: je .LBB4_2
; AVX-NEXT: # %bb.1: ; AVX-NEXT: # %bb.1:
; AVX-NEXT: movq {{[0-9]+}}(%rsp), %rcx ; AVX-NEXT: movq {{[0-9]+}}(%rsp), %rcx
; AVX-NEXT: jmp .LBB4_3 ; AVX-NEXT: jmp .LBB4_3
; AVX-NEXT: .LBB4_2: # %if.then ; AVX-NEXT: .LBB4_2: # %if.then
; AVX-NEXT: vmovaps {{.*}}(%rip), %xmm1 ; AVX-NEXT: vmovaps {{.*}}(%rip), %xmm1
; AVX-NEXT: callq __multf3 ; AVX-NEXT: callq __multf3
; AVX-NEXT: vmovaps %xmm0, {{[0-9]+}}(%rsp) ; AVX-NEXT: vmovaps %xmm0, {{[0-9]+}}(%rsp)
; AVX-NEXT: movq {{[0-9]+}}(%rsp), %rcx
; AVX-NEXT: movabsq $-9223090561878065153, %rdx # imm = 0x8000FFFFFFFFFFFF ; AVX-NEXT: movabsq $-9223090561878065153, %rdx # imm = 0x8000FFFFFFFFFFFF
; AVX-NEXT: andq {{[0-9]+}}(%rsp), %rdx
; AVX-NEXT: movabsq $4611123068473966592, %rax # imm = 0x3FFE000000000000 ; AVX-NEXT: movabsq $4611123068473966592, %rax # imm = 0x3FFE000000000000
; AVX-NEXT: andq {{[0-9]+}}(%rsp), %rdx
; AVX-NEXT: movq {{[0-9]+}}(%rsp), %rcx
; AVX-NEXT: orq %rdx, %rax ; AVX-NEXT: orq %rdx, %rax
; AVX-NEXT: .LBB4_3: # %if.end ; AVX-NEXT: .LBB4_3: # %if.end
; AVX-NEXT: movq %rcx, (%rsp) ; AVX-NEXT: movq %rcx, (%rsp)
; AVX-NEXT: movq %rax, {{[0-9]+}}(%rsp) ; AVX-NEXT: movq %rax, {{[0-9]+}}(%rsp)
; AVX-NEXT: vmovaps (%rsp), %xmm0 ; AVX-NEXT: vmovaps (%rsp), %xmm0
; AVX-NEXT: addq $56, %rsp ; AVX-NEXT: addq $56, %rsp
; AVX-NEXT: retq ; AVX-NEXT: retq
entry: entry:
Show All 23 Lines
; u.e = x; ; u.e = x;
; u.xbits.manl = 0; ; u.xbits.manl = 0;
; df = u.e; ; df = u.e;
; return x + df; ; return x + df;
; } ; }
define fp128 @TestI128_4(fp128 %x) #0 { define fp128 @TestI128_4(fp128 %x) #0 {
; SSE-LABEL: TestI128_4: ; SSE-LABEL: TestI128_4:
; SSE: # %bb.0: # %entry ; SSE: # %bb.0: # %entry
; SSE-NEXT: movaps %xmm0, %xmm1
; SSE-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) ; SSE-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
; SSE-NEXT: movaps %xmm0, %xmm1
; SSE-NEXT: movq -{{[0-9]+}}(%rsp), %rax ; SSE-NEXT: movq -{{[0-9]+}}(%rsp), %rax
; SSE-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
; SSE-NEXT: movq $0, -{{[0-9]+}}(%rsp) ; SSE-NEXT: movq $0, -{{[0-9]+}}(%rsp)
; SSE-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
; SSE-NEXT: movaps -{{[0-9]+}}(%rsp), %xmm0 ; SSE-NEXT: movaps -{{[0-9]+}}(%rsp), %xmm0
; SSE-NEXT: jmp __addtf3 # TAILCALL ; SSE-NEXT: jmp __addtf3 # TAILCALL
; ;
; AVX-LABEL: TestI128_4: ; AVX-LABEL: TestI128_4:
; AVX: # %bb.0: # %entry ; AVX: # %bb.0: # %entry
; AVX-NEXT: vmovaps %xmm0, %xmm1
; AVX-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp) ; AVX-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)
; AVX-NEXT: vmovaps %xmm0, %xmm1
; AVX-NEXT: movq -{{[0-9]+}}(%rsp), %rax ; AVX-NEXT: movq -{{[0-9]+}}(%rsp), %rax
; AVX-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
; AVX-NEXT: movq $0, -{{[0-9]+}}(%rsp) ; AVX-NEXT: movq $0, -{{[0-9]+}}(%rsp)
; AVX-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
; AVX-NEXT: vmovaps -{{[0-9]+}}(%rsp), %xmm0 ; AVX-NEXT: vmovaps -{{[0-9]+}}(%rsp), %xmm0
; AVX-NEXT: jmp __addtf3 # TAILCALL ; AVX-NEXT: jmp __addtf3 # TAILCALL
entry: entry:
%0 = bitcast fp128 %x to i128 %0 = bitcast fp128 %x to i128
%bf.clear = and i128 %0, -18446744073709551616 %bf.clear = and i128 %0, -18446744073709551616
%1 = bitcast i128 %bf.clear to fp128 %1 = bitcast i128 %bf.clear to fp128
%add = fadd fp128 %1, %x %add = fadd fp128 %1, %x
ret fp128 %add ret fp128 %add
Show All 24 Linesentry:
%or = or i128 %shl, %1 %or = or i128 %shl, %1
store i128 %or, i128* @v128, align 16 store i128 %or, i128* @v128, align 16
ret void ret void
} }
define fp128 @acosl(fp128 %x) #0 { define fp128 @acosl(fp128 %x) #0 {
; SSE-LABEL: acosl: ; SSE-LABEL: acosl:
; SSE: # %bb.0: # %entry ; SSE: # %bb.0: # %entry
; SSE-NEXT: movaps %xmm0, %xmm1
; SSE-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) ; SSE-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
; SSE-NEXT: movaps %xmm0, %xmm1
; SSE-NEXT: movq -{{[0-9]+}}(%rsp), %rax ; SSE-NEXT: movq -{{[0-9]+}}(%rsp), %rax
; SSE-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
; SSE-NEXT: movq $0, -{{[0-9]+}}(%rsp) ; SSE-NEXT: movq $0, -{{[0-9]+}}(%rsp)
; SSE-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
; SSE-NEXT: movaps -{{[0-9]+}}(%rsp), %xmm0 ; SSE-NEXT: movaps -{{[0-9]+}}(%rsp), %xmm0
; SSE-NEXT: jmp __addtf3 # TAILCALL ; SSE-NEXT: jmp __addtf3 # TAILCALL
; ;
; AVX-LABEL: acosl: ; AVX-LABEL: acosl:
; AVX: # %bb.0: # %entry ; AVX: # %bb.0: # %entry
; AVX-NEXT: vmovaps %xmm0, %xmm1
; AVX-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp) ; AVX-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)
; AVX-NEXT: vmovaps %xmm0, %xmm1
; AVX-NEXT: movq -{{[0-9]+}}(%rsp), %rax ; AVX-NEXT: movq -{{[0-9]+}}(%rsp), %rax
; AVX-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
; AVX-NEXT: movq $0, -{{[0-9]+}}(%rsp) ; AVX-NEXT: movq $0, -{{[0-9]+}}(%rsp)
; AVX-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
; AVX-NEXT: vmovaps -{{[0-9]+}}(%rsp), %xmm0 ; AVX-NEXT: vmovaps -{{[0-9]+}}(%rsp), %xmm0
; AVX-NEXT: jmp __addtf3 # TAILCALL ; AVX-NEXT: jmp __addtf3 # TAILCALL
entry: entry:
%0 = bitcast fp128 %x to i128 %0 = bitcast fp128 %x to i128
%bf.clear = and i128 %0, -18446744073709551616 %bf.clear = and i128 %0, -18446744073709551616
%1 = bitcast i128 %bf.clear to fp128 %1 = bitcast i128 %bf.clear to fp128
%add = fadd fp128 %1, %x %add = fadd fp128 %1, %x
ret fp128 %add ret fp128 %add
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
; Test more complicated logical operations generated from copysignl. ; Test more complicated logical operations generated from copysignl.
define void @TestCopySign({ fp128, fp128 }* noalias nocapture sret %agg.result, { fp128, fp128 }* byval nocapture readonly align 16 %z) #0 { define void @TestCopySign({ fp128, fp128 }* noalias nocapture sret %agg.result, { fp128, fp128 }* byval nocapture readonly align 16 %z) #0 {
; SSE-LABEL: TestCopySign: ; SSE-LABEL: TestCopySign:
; SSE: # %bb.0: # %entry ; SSE: # %bb.0: # %entry
; SSE-NEXT: pushq %rbp ; SSE-NEXT: pushq %rbp
; SSE-NEXT: pushq %rbx ; SSE-NEXT: pushq %rbx
; SSE-NEXT: subq $40, %rsp ; SSE-NEXT: subq $40, %rsp
; SSE-NEXT: movq %rdi, %rbx
; SSE-NEXT: movaps {{[0-9]+}}(%rsp), %xmm0 ; SSE-NEXT: movaps {{[0-9]+}}(%rsp), %xmm0
; SSE-NEXT: movaps {{[0-9]+}}(%rsp), %xmm1 ; SSE-NEXT: movaps {{[0-9]+}}(%rsp), %xmm1
; SSE-NEXT: movq %rdi, %rbx
; SSE-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; SSE-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill ; SSE-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; SSE-NEXT: callq __gttf2 ; SSE-NEXT: callq __gttf2
; SSE-NEXT: movl %eax, %ebp
; SSE-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; SSE-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; SSE-NEXT: movl %eax, %ebp
; SSE-NEXT: movaps %xmm0, %xmm1 ; SSE-NEXT: movaps %xmm0, %xmm1
; SSE-NEXT: callq __subtf3 ; SSE-NEXT: callq __subtf3
; SSE-NEXT: testl %ebp, %ebp ; SSE-NEXT: testl %ebp, %ebp
; SSE-NEXT: jle .LBB10_1 ; SSE-NEXT: jle .LBB10_1
; SSE-NEXT: # %bb.2: # %if.then ; SSE-NEXT: # %bb.2: # %if.then
; SSE-NEXT: movaps %xmm0, %xmm1 ; SSE-NEXT: movaps %xmm0, %xmm1
; SSE-NEXT: andps {{.*}}(%rip), %xmm1 ; SSE-NEXT: andps {{.*}}(%rip), %xmm1
; SSE-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload ; SSE-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; SSE-NEXT: jmp .LBB10_3 ; SSE-NEXT: jmp .LBB10_3
; SSE-NEXT: .LBB10_1: ; SSE-NEXT: .LBB10_1:
; SSE-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload ; SSE-NEXT: movaps (%rsp), %xmm1 # 16-byte Reload
; SSE-NEXT: .LBB10_3: # %cleanup ; SSE-NEXT: .LBB10_3: # %cleanup
; SSE-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload ; SSE-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 16-byte Reload
; SSE-NEXT: andps {{.*}}(%rip), %xmm2 ; SSE-NEXT: andps {{.*}}(%rip), %xmm2
; SSE-NEXT: andps {{.*}}(%rip), %xmm0 ; SSE-NEXT: andps {{.*}}(%rip), %xmm0
; SSE-NEXT: orps %xmm2, %xmm0
; SSE-NEXT: movaps %xmm1, (%rbx) ; SSE-NEXT: movaps %xmm1, (%rbx)
; SSE-NEXT: movaps %xmm0, 16(%rbx)
; SSE-NEXT: movq %rbx, %rax ; SSE-NEXT: movq %rbx, %rax
; SSE-NEXT: orps %xmm2, %xmm0
; SSE-NEXT: movaps %xmm0, 16(%rbx)
; SSE-NEXT: addq $40, %rsp ; SSE-NEXT: addq $40, %rsp
; SSE-NEXT: popq %rbx ; SSE-NEXT: popq %rbx
; SSE-NEXT: popq %rbp ; SSE-NEXT: popq %rbp
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: TestCopySign: ; AVX-LABEL: TestCopySign:
; AVX: # %bb.0: # %entry ; AVX: # %bb.0: # %entry
; AVX-NEXT: pushq %rbp ; AVX-NEXT: pushq %rbp
; AVX-NEXT: pushq %rbx ; AVX-NEXT: pushq %rbx
; AVX-NEXT: subq $40, %rsp ; AVX-NEXT: subq $40, %rsp
; AVX-NEXT: movq %rdi, %rbx
; AVX-NEXT: vmovaps {{[0-9]+}}(%rsp), %xmm0 ; AVX-NEXT: vmovaps {{[0-9]+}}(%rsp), %xmm0
; AVX-NEXT: vmovaps {{[0-9]+}}(%rsp), %xmm1 ; AVX-NEXT: vmovaps {{[0-9]+}}(%rsp), %xmm1
; AVX-NEXT: movq %rdi, %rbx
; AVX-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; AVX-NEXT: vmovaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; AVX-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill ; AVX-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; AVX-NEXT: callq __gttf2 ; AVX-NEXT: callq __gttf2
; AVX-NEXT: movl %eax, %ebp
; AVX-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; AVX-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; AVX-NEXT: movl %eax, %ebp
; AVX-NEXT: vmovaps %xmm0, %xmm1 ; AVX-NEXT: vmovaps %xmm0, %xmm1
; AVX-NEXT: callq __subtf3 ; AVX-NEXT: callq __subtf3
; AVX-NEXT: testl %ebp, %ebp ; AVX-NEXT: testl %ebp, %ebp
; AVX-NEXT: jle .LBB10_1 ; AVX-NEXT: jle .LBB10_1
; AVX-NEXT: # %bb.2: # %if.then ; AVX-NEXT: # %bb.2: # %if.then
; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm2 ; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm2
; AVX-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload ; AVX-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
; AVX-NEXT: jmp .LBB10_3 ; AVX-NEXT: jmp .LBB10_3
; AVX-NEXT: .LBB10_1: ; AVX-NEXT: .LBB10_1:
; AVX-NEXT: vmovaps (%rsp), %xmm2 # 16-byte Reload ; AVX-NEXT: vmovaps (%rsp), %xmm2 # 16-byte Reload
; AVX-NEXT: .LBB10_3: # %cleanup ; AVX-NEXT: .LBB10_3: # %cleanup
; AVX-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; AVX-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; AVX-NEXT: vandps {{.*}}(%rip), %xmm1, %xmm1 ; AVX-NEXT: vandps {{.*}}(%rip), %xmm1, %xmm1
; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0 ; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0
; AVX-NEXT: vmovaps %xmm2, (%rbx) ; AVX-NEXT: vmovaps %xmm2, (%rbx)
; AVX-NEXT: vmovaps %xmm0, 16(%rbx)
; AVX-NEXT: movq %rbx, %rax ; AVX-NEXT: movq %rbx, %rax
; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0
; AVX-NEXT: vmovaps %xmm0, 16(%rbx)
; AVX-NEXT: addq $40, %rsp ; AVX-NEXT: addq $40, %rsp
; AVX-NEXT: popq %rbx ; AVX-NEXT: popq %rbx
; AVX-NEXT: popq %rbp ; AVX-NEXT: popq %rbp
; AVX-NEXT: retq ; AVX-NEXT: retq
entry: entry:
%z.realp = getelementptr inbounds { fp128, fp128 }, { fp128, fp128 }* %z, i64 0, i32 0 %z.realp = getelementptr inbounds { fp128, fp128 }, { fp128, fp128 }* %z, i64 0, i32 0
%z.real = load fp128, fp128* %z.realp, align 16 %z.real = load fp128, fp128* %z.realp, align 16
%z.imagp = getelementptr inbounds { fp128, fp128 }, { fp128, fp128 }* %z, i64 0, i32 1 %z.imagp = getelementptr inbounds { fp128, fp128 }, { fp128, fp128 }* %z, i64 0, i32 1
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llvm/test/CodeGen/X86/gather-addresses.ll

Show All 34 Lines
; LIN-SSE4: # %bb.0: ; LIN-SSE4: # %bb.0:
; LIN-SSE4-NEXT: movdqa (%rsi), %xmm0 ; LIN-SSE4-NEXT: movdqa (%rsi), %xmm0
; LIN-SSE4-NEXT: pand (%rdx), %xmm0 ; LIN-SSE4-NEXT: pand (%rdx), %xmm0
; LIN-SSE4-NEXT: movd %xmm0, %eax ; LIN-SSE4-NEXT: movd %xmm0, %eax
; LIN-SSE4-NEXT: pextrd $1, %xmm0, %ecx ; LIN-SSE4-NEXT: pextrd $1, %xmm0, %ecx
; LIN-SSE4-NEXT: pextrd $2, %xmm0, %edx ; LIN-SSE4-NEXT: pextrd $2, %xmm0, %edx
; LIN-SSE4-NEXT: pextrd $3, %xmm0, %esi ; LIN-SSE4-NEXT: pextrd $3, %xmm0, %esi
; LIN-SSE4-NEXT: cltq ; LIN-SSE4-NEXT: cltq
; LIN-SSE4-NEXT: movslq %ecx, %rcx
; LIN-SSE4-NEXT: movslq %edx, %rdx ; LIN-SSE4-NEXT: movslq %edx, %rdx
; LIN-SSE4-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; LIN-SSE4-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; LIN-SSE4-NEXT: movhps {{.*#+}} xmm0 = xmm0[0,1],mem[0,1] ; LIN-SSE4-NEXT: movslq %ecx, %rcx
; LIN-SSE4-NEXT: movslq %esi, %rax ; LIN-SSE4-NEXT: movslq %esi, %rax
; LIN-SSE4-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero ; LIN-SSE4-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; LIN-SSE4-NEXT: movhps {{.*#+}} xmm0 = xmm0[0,1],mem[0,1]
; LIN-SSE4-NEXT: movhps {{.*#+}} xmm1 = xmm1[0,1],mem[0,1] ; LIN-SSE4-NEXT: movhps {{.*#+}} xmm1 = xmm1[0,1],mem[0,1]
; LIN-SSE4-NEXT: retq ; LIN-SSE4-NEXT: retq
; ;
; WIN-SSE2-LABEL: foo: ; WIN-SSE2-LABEL: foo:
; WIN-SSE2: # %bb.0: ; WIN-SSE2: # %bb.0:
; WIN-SSE2-NEXT: movdqa (%rdx), %xmm0 ; WIN-SSE2-NEXT: movdqa (%rdx), %xmm0
; WIN-SSE2-NEXT: pand (%r8), %xmm0 ; WIN-SSE2-NEXT: pand (%r8), %xmm0
; WIN-SSE2-NEXT: movd %xmm0, %r8d ; WIN-SSE2-NEXT: movd %xmm0, %r8d
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; WIN-SSE4: # %bb.0: ; WIN-SSE4: # %bb.0:
; WIN-SSE4-NEXT: movdqa (%rdx), %xmm0 ; WIN-SSE4-NEXT: movdqa (%rdx), %xmm0
; WIN-SSE4-NEXT: pand (%r8), %xmm0 ; WIN-SSE4-NEXT: pand (%r8), %xmm0
; WIN-SSE4-NEXT: movd %xmm0, %eax ; WIN-SSE4-NEXT: movd %xmm0, %eax
; WIN-SSE4-NEXT: pextrd $1, %xmm0, %edx ; WIN-SSE4-NEXT: pextrd $1, %xmm0, %edx
; WIN-SSE4-NEXT: pextrd $2, %xmm0, %r8d ; WIN-SSE4-NEXT: pextrd $2, %xmm0, %r8d
; WIN-SSE4-NEXT: pextrd $3, %xmm0, %r9d ; WIN-SSE4-NEXT: pextrd $3, %xmm0, %r9d
; WIN-SSE4-NEXT: cltq ; WIN-SSE4-NEXT: cltq
; WIN-SSE4-NEXT: movslq %edx, %rdx
; WIN-SSE4-NEXT: movslq %r8d, %r8 ; WIN-SSE4-NEXT: movslq %r8d, %r8
; WIN-SSE4-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; WIN-SSE4-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; WIN-SSE4-NEXT: movhps {{.*#+}} xmm0 = xmm0[0,1],mem[0,1] ; WIN-SSE4-NEXT: movslq %edx, %rdx
; WIN-SSE4-NEXT: movslq %r9d, %rax ; WIN-SSE4-NEXT: movslq %r9d, %rax
; WIN-SSE4-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero ; WIN-SSE4-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; WIN-SSE4-NEXT: movhps {{.*#+}} xmm0 = xmm0[0,1],mem[0,1]
; WIN-SSE4-NEXT: movhps {{.*#+}} xmm1 = xmm1[0,1],mem[0,1] ; WIN-SSE4-NEXT: movhps {{.*#+}} xmm1 = xmm1[0,1],mem[0,1]
; WIN-SSE4-NEXT: retq ; WIN-SSE4-NEXT: retq
; ;
; LIN32-LABEL: foo: ; LIN32-LABEL: foo:
; LIN32: # %bb.0: ; LIN32: # %bb.0:
; LIN32-NEXT: pushl %edi ; LIN32-NEXT: pushl %edi
; LIN32-NEXT: pushl %esi ; LIN32-NEXT: pushl %esi
; LIN32-NEXT: movl {{[0-9]+}}(%esp), %eax
; LIN32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; LIN32-NEXT: movl {{[0-9]+}}(%esp), %edx ; LIN32-NEXT: movl {{[0-9]+}}(%esp), %edx
; LIN32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; LIN32-NEXT: movl {{[0-9]+}}(%esp), %eax
; LIN32-NEXT: movdqa (%edx), %xmm0 ; LIN32-NEXT: movdqa (%edx), %xmm0
; LIN32-NEXT: pand (%ecx), %xmm0 ; LIN32-NEXT: pand (%ecx), %xmm0
; LIN32-NEXT: pextrd $1, %xmm0, %ecx
; LIN32-NEXT: pextrd $2, %xmm0, %edx ; LIN32-NEXT: pextrd $2, %xmm0, %edx
; LIN32-NEXT: pextrd $1, %xmm0, %ecx
; LIN32-NEXT: pextrd $3, %xmm0, %esi ; LIN32-NEXT: pextrd $3, %xmm0, %esi
; LIN32-NEXT: movd %xmm0, %edi ; LIN32-NEXT: movd %xmm0, %edi
; LIN32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; LIN32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; LIN32-NEXT: movhps {{.*#+}} xmm0 = xmm0[0,1],mem[0,1]
; LIN32-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero ; LIN32-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; LIN32-NEXT: movhps {{.*#+}} xmm0 = xmm0[0,1],mem[0,1]
; LIN32-NEXT: movhps {{.*#+}} xmm1 = xmm1[0,1],mem[0,1] ; LIN32-NEXT: movhps {{.*#+}} xmm1 = xmm1[0,1],mem[0,1]
; LIN32-NEXT: popl %esi ; LIN32-NEXT: popl %esi
; LIN32-NEXT: popl %edi ; LIN32-NEXT: popl %edi
; LIN32-NEXT: retl ; LIN32-NEXT: retl
%a = load <4 x i32>, <4 x i32>* %i %a = load <4 x i32>, <4 x i32>* %i
%b = load <4 x i32>, <4 x i32>* %h %b = load <4 x i32>, <4 x i32>* %h
%j = and <4 x i32> %a, %b %j = and <4 x i32> %a, %b
%d0 = extractelement <4 x i32> %j, i32 0 %d0 = extractelement <4 x i32> %j, i32 0
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
; LIN-SSE2-NEXT: movq %rsi, %xmm1 ; LIN-SSE2-NEXT: movq %rsi, %xmm1
; LIN-SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0] ; LIN-SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; LIN-SSE2-NEXT: retq ; LIN-SSE2-NEXT: retq
; ;
; LIN-SSE4-LABEL: old: ; LIN-SSE4-LABEL: old:
; LIN-SSE4: # %bb.0: ; LIN-SSE4: # %bb.0:
; LIN-SSE4-NEXT: movdqa (%rsi), %xmm0 ; LIN-SSE4-NEXT: movdqa (%rsi), %xmm0
; LIN-SSE4-NEXT: pand (%rdx), %xmm0 ; LIN-SSE4-NEXT: pand (%rdx), %xmm0
; LIN-SSE4-NEXT: movd %xmm0, %eax
; LIN-SSE4-NEXT: pextrd $1, %xmm0, %edx ; LIN-SSE4-NEXT: pextrd $1, %xmm0, %edx
; LIN-SSE4-NEXT: movd %xmm0, %eax
; LIN-SSE4-NEXT: pextrd $2, %xmm0, %esi ; LIN-SSE4-NEXT: pextrd $2, %xmm0, %esi
; LIN-SSE4-NEXT: pextrd $3, %xmm0, %edi ; LIN-SSE4-NEXT: pextrd $3, %xmm0, %edi
; LIN-SSE4-NEXT: andl %ecx, %eax ; LIN-SSE4-NEXT: andl %ecx, %eax
; LIN-SSE4-NEXT: andl %ecx, %edx ; LIN-SSE4-NEXT: andl %ecx, %edx
; LIN-SSE4-NEXT: andl %ecx, %esi
; LIN-SSE4-NEXT: andl %ecx, %edi ; LIN-SSE4-NEXT: andl %ecx, %edi
; LIN-SSE4-NEXT: movq %rdx, %xmm1 ; LIN-SSE4-NEXT: andl %ecx, %esi
; LIN-SSE4-NEXT: movq %rax, %xmm0 ; LIN-SSE4-NEXT: movq %rax, %xmm0
; LIN-SSE4-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; LIN-SSE4-NEXT: movq %rdx, %xmm1
; LIN-SSE4-NEXT: movq %rdi, %xmm2 ; LIN-SSE4-NEXT: movq %rdi, %xmm2
; LIN-SSE4-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; LIN-SSE4-NEXT: movq %rsi, %xmm1 ; LIN-SSE4-NEXT: movq %rsi, %xmm1
; LIN-SSE4-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0] ; LIN-SSE4-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; LIN-SSE4-NEXT: retq ; LIN-SSE4-NEXT: retq
; ;
; WIN-SSE2-LABEL: old: ; WIN-SSE2-LABEL: old:
; WIN-SSE2: # %bb.0: ; WIN-SSE2: # %bb.0:
; WIN-SSE2-NEXT: movdqa (%rdx), %xmm0 ; WIN-SSE2-NEXT: movdqa (%rdx), %xmm0
; WIN-SSE2-NEXT: pand (%r8), %xmm0 ; WIN-SSE2-NEXT: pand (%r8), %xmm0
Show All 15 Lines
; WIN-SSE2-NEXT: movq %r8, %xmm1 ; WIN-SSE2-NEXT: movq %r8, %xmm1
; WIN-SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0] ; WIN-SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; WIN-SSE2-NEXT: retq ; WIN-SSE2-NEXT: retq
; ;
; WIN-SSE4-LABEL: old: ; WIN-SSE4-LABEL: old:
; WIN-SSE4: # %bb.0: ; WIN-SSE4: # %bb.0:
; WIN-SSE4-NEXT: movdqa (%rdx), %xmm0 ; WIN-SSE4-NEXT: movdqa (%rdx), %xmm0
; WIN-SSE4-NEXT: pand (%r8), %xmm0 ; WIN-SSE4-NEXT: pand (%r8), %xmm0
; WIN-SSE4-NEXT: movd %xmm0, %eax
; WIN-SSE4-NEXT: pextrd $1, %xmm0, %ecx ; WIN-SSE4-NEXT: pextrd $1, %xmm0, %ecx
; WIN-SSE4-NEXT: movd %xmm0, %eax
; WIN-SSE4-NEXT: pextrd $2, %xmm0, %r8d ; WIN-SSE4-NEXT: pextrd $2, %xmm0, %r8d
; WIN-SSE4-NEXT: pextrd $3, %xmm0, %edx ; WIN-SSE4-NEXT: pextrd $3, %xmm0, %edx
; WIN-SSE4-NEXT: andl %r9d, %eax ; WIN-SSE4-NEXT: andl %r9d, %eax
; WIN-SSE4-NEXT: andl %r9d, %ecx ; WIN-SSE4-NEXT: andl %r9d, %ecx
; WIN-SSE4-NEXT: andl %r9d, %r8d
; WIN-SSE4-NEXT: andl %r9d, %edx ; WIN-SSE4-NEXT: andl %r9d, %edx
; WIN-SSE4-NEXT: movq %rcx, %xmm1 ; WIN-SSE4-NEXT: andl %r9d, %r8d
; WIN-SSE4-NEXT: movq %rax, %xmm0 ; WIN-SSE4-NEXT: movq %rax, %xmm0
; WIN-SSE4-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; WIN-SSE4-NEXT: movq %rcx, %xmm1
; WIN-SSE4-NEXT: movq %rdx, %xmm2 ; WIN-SSE4-NEXT: movq %rdx, %xmm2
; WIN-SSE4-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; WIN-SSE4-NEXT: movq %r8, %xmm1 ; WIN-SSE4-NEXT: movq %r8, %xmm1
; WIN-SSE4-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0] ; WIN-SSE4-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; WIN-SSE4-NEXT: retq ; WIN-SSE4-NEXT: retq
; ;
; LIN32-LABEL: old: ; LIN32-LABEL: old:
; LIN32: # %bb.0: ; LIN32: # %bb.0:
; LIN32-NEXT: pushl %edi ; LIN32-NEXT: pushl %edi
; LIN32-NEXT: pushl %esi ; LIN32-NEXT: pushl %esi
; LIN32-NEXT: movl {{[0-9]+}}(%esp), %eax
; LIN32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; LIN32-NEXT: movl {{[0-9]+}}(%esp), %edx ; LIN32-NEXT: movl {{[0-9]+}}(%esp), %edx
; LIN32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; LIN32-NEXT: movl {{[0-9]+}}(%esp), %eax
; LIN32-NEXT: movdqa (%edx), %xmm0 ; LIN32-NEXT: movdqa (%edx), %xmm0
; LIN32-NEXT: pand (%ecx), %xmm0 ; LIN32-NEXT: pand (%ecx), %xmm0
; LIN32-NEXT: movd %xmm0, %ecx
; LIN32-NEXT: pextrd $1, %xmm0, %edx ; LIN32-NEXT: pextrd $1, %xmm0, %edx
; LIN32-NEXT: movd %xmm0, %ecx
; LIN32-NEXT: pextrd $2, %xmm0, %esi ; LIN32-NEXT: pextrd $2, %xmm0, %esi
; LIN32-NEXT: pextrd $3, %xmm0, %edi ; LIN32-NEXT: pextrd $3, %xmm0, %edi
; LIN32-NEXT: andl %eax, %ecx ; LIN32-NEXT: andl %eax, %ecx
; LIN32-NEXT: andl %eax, %edx ; LIN32-NEXT: andl %eax, %edx
; LIN32-NEXT: andl %eax, %esi
; LIN32-NEXT: andl %eax, %edi ; LIN32-NEXT: andl %eax, %edi
; LIN32-NEXT: movd %edx, %xmm1 ; LIN32-NEXT: andl %eax, %esi
; LIN32-NEXT: movd %ecx, %xmm0 ; LIN32-NEXT: movd %ecx, %xmm0
; LIN32-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; LIN32-NEXT: movd %edx, %xmm1
; LIN32-NEXT: movd %edi, %xmm2 ; LIN32-NEXT: movd %edi, %xmm2
; LIN32-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; LIN32-NEXT: movd %esi, %xmm1 ; LIN32-NEXT: movd %esi, %xmm1
; LIN32-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0] ; LIN32-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; LIN32-NEXT: popl %esi ; LIN32-NEXT: popl %esi
; LIN32-NEXT: popl %edi ; LIN32-NEXT: popl %edi
; LIN32-NEXT: retl ; LIN32-NEXT: retl
%a = load <4 x i32>, <4 x i32>* %i %a = load <4 x i32>, <4 x i32>* %i
%b = load <4 x i32>, <4 x i32>* %h %b = load <4 x i32>, <4 x i32>* %h
%j = and <4 x i32> %a, %b %j = and <4 x i32> %a, %b
Show All 18 Lines

llvm/test/CodeGen/X86/inreg.ll

; RUN: llc -fast-isel-sink-local-values < %s -mtriple=i686-pc-linux -mcpu=corei7 | FileCheck --check-prefix=DAG %s ; RUN: llc -fast-isel-sink-local-values < %s -mtriple=i686-pc-linux -mcpu=corei7 | FileCheck --check-prefix=DAG %s
; RUN: llc -fast-isel-sink-local-values < %s -mtriple=i686-pc-linux -mcpu=corei7 -O0 | FileCheck --check-prefix=FAST %s ; RUN: llc -fast-isel-sink-local-values < %s -mtriple=i686-pc-linux -mcpu=corei7 -O0 | FileCheck --check-prefix=FAST %s
%struct.s1 = type { double, float } %struct.s1 = type { double, float }
define void @g1() nounwind { define void @g1() nounwind {
entry: entry:
%tmp = alloca %struct.s1, align 4 %tmp = alloca %struct.s1, align 4
call void @f(%struct.s1* inreg sret %tmp, i32 inreg 41, i32 inreg 42, i32 43) call void @f(%struct.s1* inreg sret %tmp, i32 inreg 41, i32 inreg 42, i32 43)
ret void ret void
; DAG-LABEL: g1: ; DAG-LABEL: g1:
; DAG: subl $[[AMT:.*]], %esp ; DAG: subl $[[AMT:.*]], %esp
; DAG-NEXT: $43, (%esp)
; DAG-NEXT: leal 16(%esp), %eax ; DAG-NEXT: leal 16(%esp), %eax
; DAG-NEXT: movl $41, %edx ; DAG-NEXT: movl $41, %edx
; DAG-NEXT: movl $42, %ecx ; DAG-NEXT: movl $42, %ecx
; DAG-NEXT: $43, (%esp)
; DAG-NEXT: calll f ; DAG-NEXT: calll f
; DAG-NEXT: addl $[[AMT]], %esp ; DAG-NEXT: addl $[[AMT]], %esp
; DAG-NEXT: ret ; DAG-NEXT: ret
; FAST-LABEL: g1: ; FAST-LABEL: g1:
; FAST: subl $[[AMT:.*]], %esp ; FAST: subl $[[AMT:.*]], %esp
; FAST-NEXT: leal 16(%esp), %eax ; FAST-NEXT: leal 16(%esp), %eax
; FAST-NEXT: movl $41, %edx ; FAST-NEXT: movl $41, %edx
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llvm/test/CodeGen/X86/lifetime-alias.ll

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; Function Attrs: norecurse uwtable ; Function Attrs: norecurse uwtable
define i8 @main() local_unnamed_addr #0 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { define i8 @main() local_unnamed_addr #0 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
; CHECK-LABEL: main: ; CHECK-LABEL: main:
; CHECK: # %bb.0: # %_ZNSt3__312basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEED2Ev.exit50 ; CHECK: # %bb.0: # %_ZNSt3__312basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEED2Ev.exit50
; CHECK-NEXT: pushq %rax ; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: movaps {{.*#+}} xmm0 = [97,97,97,97,97,97,97,97,97,97,97,97,97,97,97,97] ; CHECK-NEXT: movaps {{.*#+}} xmm0 = [97,97,97,97,97,97,97,97,97,97,97,97,97,97,97,97]
; CHECK-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movabsq $8389209137051166804, %r9 # imm = 0x746C754320656854
; CHECK-NEXT: movups {{.*}}(%rip), %xmm1
; CHECK-NEXT: movq $0, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movabsq $7308613581744070988, %rdx # imm = 0x656D69547473614C
; CHECK-NEXT: movq $0, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movabsq $7016996765293437281, %rax # imm = 0x6161616161616161 ; CHECK-NEXT: movabsq $7016996765293437281, %rax # imm = 0x6161616161616161
; CHECK-NEXT: movq %rax, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movw $5632, {{[0-9]+}}(%rsp) # imm = 0x1600
; CHECK-NEXT: xorps %xmm0, %xmm0 ; CHECK-NEXT: xorps %xmm0, %xmm0
; CHECK-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movq $0, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movb $11, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movb $11, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movabsq $8389209137051166804, %rax # imm = 0x746C754320656854 ; CHECK-NEXT: movq %r9, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movl $1701999988, -{{[0-9]+}}(%rsp) # imm = 0x65727574 ; CHECK-NEXT: movl $1701999988, -{{[0-9]+}}(%rsp) # imm = 0x65727574
; CHECK-NEXT: movb $0, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movb $0, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movq $0, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movb $21, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movb $21, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movabsq $7308613581744070988, %rax # imm = 0x656D69547473614C ; CHECK-NEXT: movq %rdx, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movups {{.*}}(%rip), %xmm1
; CHECK-NEXT: movaps %xmm1, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movaps %xmm1, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movb $0, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movb $0, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movq -{{[0-9]+}}(%rsp), %rax
; CHECK-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movq -{{[0-9]+}}(%rsp), %rax
; CHECK-NEXT: movq %rax, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movzwl -{{[0-9]+}}(%rsp), %eax ; CHECK-NEXT: movw $5632, {{[0-9]+}}(%rsp) # imm = 0x1600
; CHECK-NEXT: movw %ax, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movb -{{[0-9]+}}(%rsp), %cl
; CHECK-NEXT: movb -{{[0-9]+}}(%rsp), %al ; CHECK-NEXT: movq -{{[0-9]+}}(%rsp), %r9
; CHECK-NEXT: movb %al, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movq -{{[0-9]+}}(%rsp), %rdx
; CHECK-NEXT: movb -{{[0-9]+}}(%rsp), %al ; CHECK-NEXT: movzwl -{{[0-9]+}}(%rsp), %r8d
; CHECK-NEXT: movb %al, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movb -{{[0-9]+}}(%rsp), %dil
; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %eax ; CHECK-NEXT: movl -{{[0-9]+}}(%rsp), %esi
; CHECK-NEXT: movl %eax, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movaps -{{[0-9]+}}(%rsp), %xmm1
; CHECK-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movq $0, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movq $0, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movq -{{[0-9]+}}(%rsp), %rax
; CHECK-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movaps -{{[0-9]+}}(%rsp), %xmm1
; CHECK-NEXT: movups %xmm1, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movb %cl, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movq -{{[0-9]+}}(%rsp), %rcx
; CHECK-NEXT: movq %rdx, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movq %r9, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movw %r8w, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movb %dil, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movl %esi, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: leaq -{{[0-9]+}}(%rsp), %rdx
; CHECK-NEXT: movq $0, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movq $0, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: leaq -{{[0-9]+}}(%rsp), %rax ; CHECK-NEXT: movups %xmm1, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: movq %rax, do_not_optimize{{.*}}(%rip) ; CHECK-NEXT: movq %rcx, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: leaq -{{[0-9]+}}(%rsp), %rax ; CHECK-NEXT: leaq -{{[0-9]+}}(%rsp), %rcx
; CHECK-NEXT: movq %rax, do_not_optimize{{.*}}(%rip) ; CHECK-NEXT: movq %rdx, {{.*}}(%rip)
; CHECK-NEXT: movq %rcx, {{.*}}(%rip)
; CHECK-NEXT: cmpb $0, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: cmpb $0, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: jns .LBB0_1 ; CHECK-NEXT: jns .LBB0_1
; CHECK-NEXT: # %bb.2: # %_ZNSt3__312basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEED2Ev.exit50 ; CHECK-NEXT: # %bb.2: # %_ZNSt3__312basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEED2Ev.exit50
; CHECK-NEXT: movq -{{[0-9]+}}(%rsp), %rax ; CHECK-NEXT: movq -{{[0-9]+}}(%rsp), %rax
; CHECK-NEXT: jmp .LBB0_3 ; CHECK-NEXT: jmp .LBB0_3
; CHECK-NEXT: .LBB0_1: ; CHECK-NEXT: .LBB0_1:
; CHECK-NEXT: leaq -{{[0-9]+}}(%rsp), %rax ; CHECK-NEXT: leaq -{{[0-9]+}}(%rsp), %rax
; CHECK-NEXT: .LBB0_3: # %_ZNSt3__312basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEED2Ev.exit50 ; CHECK-NEXT: .LBB0_3: # %_ZNSt3__312basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEED2Ev.exit50
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llvm/test/CodeGen/X86/machine-combiner-int-vec.ll

Show All 10 Lines
; SSE-NEXT: paddd %xmm1, %xmm0 ; SSE-NEXT: paddd %xmm1, %xmm0
; SSE-NEXT: pand %xmm3, %xmm2 ; SSE-NEXT: pand %xmm3, %xmm2
; SSE-NEXT: pand %xmm2, %xmm0 ; SSE-NEXT: pand %xmm2, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX2-LABEL: reassociate_and_v4i32: ; AVX2-LABEL: reassociate_and_v4i32:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm0 ; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpand %xmm3, %xmm2, %xmm1 ; AVX2-NEXT: vpand %xmm3, %xmm2, %xmm2
; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 ; AVX2-NEXT: vpand %xmm2, %xmm0, %xmm0
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: reassociate_and_v4i32: ; AVX512-LABEL: reassociate_and_v4i32:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vpaddd %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vpaddd %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpternlogd $128, %xmm2, %xmm3, %xmm0 ; AVX512-NEXT: vpternlogd $128, %xmm2, %xmm3, %xmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
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; SSE-NEXT: paddd %xmm1, %xmm0 ; SSE-NEXT: paddd %xmm1, %xmm0
; SSE-NEXT: por %xmm3, %xmm2 ; SSE-NEXT: por %xmm3, %xmm2
; SSE-NEXT: por %xmm2, %xmm0 ; SSE-NEXT: por %xmm2, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX2-LABEL: reassociate_or_v4i32: ; AVX2-LABEL: reassociate_or_v4i32:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm0 ; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpor %xmm3, %xmm2, %xmm1 ; AVX2-NEXT: vpor %xmm3, %xmm2, %xmm2
; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0 ; AVX2-NEXT: vpor %xmm2, %xmm0, %xmm0
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: reassociate_or_v4i32: ; AVX512-LABEL: reassociate_or_v4i32:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vpaddd %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vpaddd %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpternlogd $254, %xmm2, %xmm3, %xmm0 ; AVX512-NEXT: vpternlogd $254, %xmm2, %xmm3, %xmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
Show All 9 Lines
; SSE-NEXT: paddd %xmm1, %xmm0 ; SSE-NEXT: paddd %xmm1, %xmm0
; SSE-NEXT: pxor %xmm3, %xmm2 ; SSE-NEXT: pxor %xmm3, %xmm2
; SSE-NEXT: pxor %xmm2, %xmm0 ; SSE-NEXT: pxor %xmm2, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX2-LABEL: reassociate_xor_v4i32: ; AVX2-LABEL: reassociate_xor_v4i32:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm0 ; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpxor %xmm3, %xmm2, %xmm1 ; AVX2-NEXT: vpxor %xmm3, %xmm2, %xmm2
; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; AVX2-NEXT: vpxor %xmm2, %xmm0, %xmm0
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: reassociate_xor_v4i32: ; AVX512-LABEL: reassociate_xor_v4i32:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vpaddd %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vpaddd %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpternlogd $150, %xmm2, %xmm3, %xmm0 ; AVX512-NEXT: vpternlogd $150, %xmm2, %xmm3, %xmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%t0 = add <4 x i32> %x0, %x1 %t0 = add <4 x i32> %x0, %x1
%t1 = xor <4 x i32> %x2, %t0 %t1 = xor <4 x i32> %x2, %t0
%t2 = xor <4 x i32> %x3, %t1 %t2 = xor <4 x i32> %x3, %t1
ret <4 x i32> %t2 ret <4 x i32> %t2
} }
; Verify that 256-bit vector logical ops are reassociated. ; Verify that 256-bit vector logical ops are reassociated.
define <8 x i32> @reassociate_and_v8i32(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, <8 x i32> %x3) { define <8 x i32> @reassociate_and_v8i32(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, <8 x i32> %x3) {
; SSE-LABEL: reassociate_and_v8i32: ; SSE-LABEL: reassociate_and_v8i32:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: paddd %xmm2, %xmm0 ; SSE-NEXT: paddd %xmm2, %xmm0
; SSE-NEXT: pand %xmm6, %xmm4 ; SSE-NEXT: pand %xmm6, %xmm4
; SSE-NEXT: pand %xmm4, %xmm0
; SSE-NEXT: paddd %xmm3, %xmm1 ; SSE-NEXT: paddd %xmm3, %xmm1
; SSE-NEXT: pand %xmm7, %xmm5 ; SSE-NEXT: pand %xmm7, %xmm5
; SSE-NEXT: pand %xmm4, %xmm0
; SSE-NEXT: pand %xmm5, %xmm1 ; SSE-NEXT: pand %xmm5, %xmm1
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX2-LABEL: reassociate_and_v8i32: ; AVX2-LABEL: reassociate_and_v8i32:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpaddd %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpaddd %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpand %ymm3, %ymm2, %ymm1 ; AVX2-NEXT: vpand %ymm3, %ymm2, %ymm2
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpand %ymm2, %ymm0, %ymm0
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: reassociate_and_v8i32: ; AVX512-LABEL: reassociate_and_v8i32:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vpaddd %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: vpaddd %ymm1, %ymm0, %ymm0
; AVX512-NEXT: vpternlogd $128, %ymm2, %ymm3, %ymm0 ; AVX512-NEXT: vpternlogd $128, %ymm2, %ymm3, %ymm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%t0 = add <8 x i32> %x0, %x1 %t0 = add <8 x i32> %x0, %x1
%t1 = and <8 x i32> %x2, %t0 %t1 = and <8 x i32> %x2, %t0
%t2 = and <8 x i32> %x3, %t1 %t2 = and <8 x i32> %x3, %t1
ret <8 x i32> %t2 ret <8 x i32> %t2
} }
define <8 x i32> @reassociate_or_v8i32(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, <8 x i32> %x3) { define <8 x i32> @reassociate_or_v8i32(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, <8 x i32> %x3) {
; SSE-LABEL: reassociate_or_v8i32: ; SSE-LABEL: reassociate_or_v8i32:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: paddd %xmm2, %xmm0 ; SSE-NEXT: paddd %xmm2, %xmm0
; SSE-NEXT: por %xmm6, %xmm4 ; SSE-NEXT: por %xmm6, %xmm4
; SSE-NEXT: por %xmm4, %xmm0
; SSE-NEXT: paddd %xmm3, %xmm1 ; SSE-NEXT: paddd %xmm3, %xmm1
; SSE-NEXT: por %xmm7, %xmm5 ; SSE-NEXT: por %xmm7, %xmm5
; SSE-NEXT: por %xmm4, %xmm0
; SSE-NEXT: por %xmm5, %xmm1 ; SSE-NEXT: por %xmm5, %xmm1
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX2-LABEL: reassociate_or_v8i32: ; AVX2-LABEL: reassociate_or_v8i32:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpaddd %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpaddd %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpor %ymm3, %ymm2, %ymm1 ; AVX2-NEXT: vpor %ymm3, %ymm2, %ymm2
; AVX2-NEXT: vpor %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpor %ymm2, %ymm0, %ymm0
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: reassociate_or_v8i32: ; AVX512-LABEL: reassociate_or_v8i32:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vpaddd %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: vpaddd %ymm1, %ymm0, %ymm0
; AVX512-NEXT: vpternlogd $254, %ymm2, %ymm3, %ymm0 ; AVX512-NEXT: vpternlogd $254, %ymm2, %ymm3, %ymm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%t0 = add <8 x i32> %x0, %x1 %t0 = add <8 x i32> %x0, %x1
%t1 = or <8 x i32> %x2, %t0 %t1 = or <8 x i32> %x2, %t0
%t2 = or <8 x i32> %x3, %t1 %t2 = or <8 x i32> %x3, %t1
ret <8 x i32> %t2 ret <8 x i32> %t2
} }
define <8 x i32> @reassociate_xor_v8i32(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, <8 x i32> %x3) { define <8 x i32> @reassociate_xor_v8i32(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, <8 x i32> %x3) {
; SSE-LABEL: reassociate_xor_v8i32: ; SSE-LABEL: reassociate_xor_v8i32:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: paddd %xmm2, %xmm0 ; SSE-NEXT: paddd %xmm2, %xmm0
; SSE-NEXT: pxor %xmm6, %xmm4 ; SSE-NEXT: pxor %xmm6, %xmm4
; SSE-NEXT: pxor %xmm4, %xmm0
; SSE-NEXT: paddd %xmm3, %xmm1 ; SSE-NEXT: paddd %xmm3, %xmm1
; SSE-NEXT: pxor %xmm7, %xmm5 ; SSE-NEXT: pxor %xmm7, %xmm5
; SSE-NEXT: pxor %xmm4, %xmm0
; SSE-NEXT: pxor %xmm5, %xmm1 ; SSE-NEXT: pxor %xmm5, %xmm1
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX2-LABEL: reassociate_xor_v8i32: ; AVX2-LABEL: reassociate_xor_v8i32:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpaddd %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpaddd %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpxor %ymm3, %ymm2, %ymm1 ; AVX2-NEXT: vpxor %ymm3, %ymm2, %ymm2
; AVX2-NEXT: vpxor %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpxor %ymm2, %ymm0, %ymm0
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: reassociate_xor_v8i32: ; AVX512-LABEL: reassociate_xor_v8i32:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vpaddd %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: vpaddd %ymm1, %ymm0, %ymm0
; AVX512-NEXT: vpternlogd $150, %ymm2, %ymm3, %ymm0 ; AVX512-NEXT: vpternlogd $150, %ymm2, %ymm3, %ymm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
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; SSE-NEXT: pand {{[0-9]+}}(%rsp), %xmm0 ; SSE-NEXT: pand {{[0-9]+}}(%rsp), %xmm0
; SSE-NEXT: pand {{[0-9]+}}(%rsp), %xmm1 ; SSE-NEXT: pand {{[0-9]+}}(%rsp), %xmm1
; SSE-NEXT: pand {{[0-9]+}}(%rsp), %xmm2 ; SSE-NEXT: pand {{[0-9]+}}(%rsp), %xmm2
; SSE-NEXT: pand {{[0-9]+}}(%rsp), %xmm3 ; SSE-NEXT: pand {{[0-9]+}}(%rsp), %xmm3
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX2-LABEL: reassociate_and_v16i32: ; AVX2-LABEL: reassociate_and_v16i32:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpaddd %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpand %ymm6, %ymm4, %ymm2
; AVX2-NEXT: vpand %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpaddd %ymm3, %ymm1, %ymm1 ; AVX2-NEXT: vpaddd %ymm3, %ymm1, %ymm1
; AVX2-NEXT: vpand %ymm7, %ymm5, %ymm2 ; AVX2-NEXT: vpand %ymm7, %ymm5, %ymm3
; AVX2-NEXT: vpand %ymm2, %ymm1, %ymm1 ; AVX2-NEXT: vpaddd %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpand %ymm6, %ymm4, %ymm4
; AVX2-NEXT: vpand %ymm4, %ymm0, %ymm0
; AVX2-NEXT: vpand %ymm3, %ymm1, %ymm1
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: reassociate_and_v16i32: ; AVX512-LABEL: reassociate_and_v16i32:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vpaddd %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vpaddd %zmm1, %zmm0, %zmm0
; AVX512-NEXT: vpternlogd $128, %zmm2, %zmm3, %zmm0 ; AVX512-NEXT: vpternlogd $128, %zmm2, %zmm3, %zmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
Show All 17 Lines
; SSE-NEXT: por {{[0-9]+}}(%rsp), %xmm0 ; SSE-NEXT: por {{[0-9]+}}(%rsp), %xmm0
; SSE-NEXT: por {{[0-9]+}}(%rsp), %xmm1 ; SSE-NEXT: por {{[0-9]+}}(%rsp), %xmm1
; SSE-NEXT: por {{[0-9]+}}(%rsp), %xmm2 ; SSE-NEXT: por {{[0-9]+}}(%rsp), %xmm2
; SSE-NEXT: por {{[0-9]+}}(%rsp), %xmm3 ; SSE-NEXT: por {{[0-9]+}}(%rsp), %xmm3
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX2-LABEL: reassociate_or_v16i32: ; AVX2-LABEL: reassociate_or_v16i32:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpaddd %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpor %ymm6, %ymm4, %ymm2
; AVX2-NEXT: vpor %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpaddd %ymm3, %ymm1, %ymm1 ; AVX2-NEXT: vpaddd %ymm3, %ymm1, %ymm1
; AVX2-NEXT: vpor %ymm7, %ymm5, %ymm2 ; AVX2-NEXT: vpor %ymm7, %ymm5, %ymm3
; AVX2-NEXT: vpor %ymm2, %ymm1, %ymm1 ; AVX2-NEXT: vpaddd %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpor %ymm6, %ymm4, %ymm4
; AVX2-NEXT: vpor %ymm4, %ymm0, %ymm0
; AVX2-NEXT: vpor %ymm3, %ymm1, %ymm1
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: reassociate_or_v16i32: ; AVX512-LABEL: reassociate_or_v16i32:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vpaddd %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vpaddd %zmm1, %zmm0, %zmm0
; AVX512-NEXT: vpternlogd $254, %zmm2, %zmm3, %zmm0 ; AVX512-NEXT: vpternlogd $254, %zmm2, %zmm3, %zmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
Show All 17 Lines
; SSE-NEXT: pxor {{[0-9]+}}(%rsp), %xmm0 ; SSE-NEXT: pxor {{[0-9]+}}(%rsp), %xmm0
; SSE-NEXT: pxor {{[0-9]+}}(%rsp), %xmm1 ; SSE-NEXT: pxor {{[0-9]+}}(%rsp), %xmm1
; SSE-NEXT: pxor {{[0-9]+}}(%rsp), %xmm2 ; SSE-NEXT: pxor {{[0-9]+}}(%rsp), %xmm2
; SSE-NEXT: pxor {{[0-9]+}}(%rsp), %xmm3 ; SSE-NEXT: pxor {{[0-9]+}}(%rsp), %xmm3
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX2-LABEL: reassociate_xor_v16i32: ; AVX2-LABEL: reassociate_xor_v16i32:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpaddd %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpxor %ymm6, %ymm4, %ymm2
; AVX2-NEXT: vpxor %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpaddd %ymm3, %ymm1, %ymm1 ; AVX2-NEXT: vpaddd %ymm3, %ymm1, %ymm1
; AVX2-NEXT: vpxor %ymm7, %ymm5, %ymm2 ; AVX2-NEXT: vpxor %ymm7, %ymm5, %ymm3
; AVX2-NEXT: vpxor %ymm2, %ymm1, %ymm1 ; AVX2-NEXT: vpaddd %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpxor %ymm6, %ymm4, %ymm4
; AVX2-NEXT: vpxor %ymm4, %ymm0, %ymm0
; AVX2-NEXT: vpxor %ymm3, %ymm1, %ymm1
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: reassociate_xor_v16i32: ; AVX512-LABEL: reassociate_xor_v16i32:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vpaddd %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vpaddd %zmm1, %zmm0, %zmm0
; AVX512-NEXT: vpternlogd $150, %zmm2, %zmm3, %zmm0 ; AVX512-NEXT: vpternlogd $150, %zmm2, %zmm3, %zmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
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; SSE-NEXT: paddb %xmm1, %xmm0 ; SSE-NEXT: paddb %xmm1, %xmm0
; SSE-NEXT: pmaxub %xmm3, %xmm2 ; SSE-NEXT: pmaxub %xmm3, %xmm2
; SSE-NEXT: pmaxub %xmm2, %xmm0 ; SSE-NEXT: pmaxub %xmm2, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: reassociate_umax_v16i8: ; AVX-LABEL: reassociate_umax_v16i8:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpaddb %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpaddb %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpmaxub %xmm3, %xmm2, %xmm1 ; AVX-NEXT: vpmaxub %xmm3, %xmm2, %xmm2
; AVX-NEXT: vpmaxub %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpmaxub %xmm2, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%t0 = add <16 x i8> %x0, %x1 %t0 = add <16 x i8> %x0, %x1
%t1 = icmp ugt <16 x i8> %x2, %t0 %t1 = icmp ugt <16 x i8> %x2, %t0
%t2 = select <16 x i1> %t1, <16 x i8> %x2, <16 x i8> %t0 %t2 = select <16 x i1> %t1, <16 x i8> %x2, <16 x i8> %t0
%t3 = icmp ugt <16 x i8> %x3, %t2 %t3 = icmp ugt <16 x i8> %x3, %t2
%t4 = select <16 x i1> %t3, <16 x i8> %x3, <16 x i8> %t2 %t4 = select <16 x i1> %t3, <16 x i8> %x3, <16 x i8> %t2
ret <16 x i8> %t4 ret <16 x i8> %t4
} }
define <8 x i16> @reassociate_umax_v8i16(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, <8 x i16> %x3) { define <8 x i16> @reassociate_umax_v8i16(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, <8 x i16> %x3) {
; SSE-LABEL: reassociate_umax_v8i16: ; SSE-LABEL: reassociate_umax_v8i16:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movdqa {{.*#+}} xmm4 = [32768,32768,32768,32768,32768,32768,32768,32768]
; SSE-NEXT: paddw %xmm1, %xmm0 ; SSE-NEXT: paddw %xmm1, %xmm0
; SSE-NEXT: movdqa {{.*#+}} xmm1 = [32768,32768,32768,32768,32768,32768,32768,32768] ; SSE-NEXT: pxor %xmm4, %xmm2
; SSE-NEXT: pxor %xmm1, %xmm2 ; SSE-NEXT: pxor %xmm4, %xmm0
; SSE-NEXT: pxor %xmm1, %xmm0 ; SSE-NEXT: pxor %xmm4, %xmm3
; SSE-NEXT: pmaxsw %xmm2, %xmm0 ; SSE-NEXT: pmaxsw %xmm2, %xmm0
; SSE-NEXT: pxor %xmm1, %xmm3
; SSE-NEXT: pmaxsw %xmm3, %xmm0 ; SSE-NEXT: pmaxsw %xmm3, %xmm0
; SSE-NEXT: pxor %xmm1, %xmm0 ; SSE-NEXT: pxor %xmm4, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: reassociate_umax_v8i16: ; AVX-LABEL: reassociate_umax_v8i16:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpaddw %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpaddw %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpmaxuw %xmm3, %xmm2, %xmm1 ; AVX-NEXT: vpmaxuw %xmm3, %xmm2, %xmm2
; AVX-NEXT: vpmaxuw %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpmaxuw %xmm2, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%t0 = add <8 x i16> %x0, %x1 %t0 = add <8 x i16> %x0, %x1
%t1 = icmp ugt <8 x i16> %x2, %t0 %t1 = icmp ugt <8 x i16> %x2, %t0
%t2 = select <8 x i1> %t1, <8 x i16> %x2, <8 x i16> %t0 %t2 = select <8 x i1> %t1, <8 x i16> %x2, <8 x i16> %t0
%t3 = icmp ugt <8 x i16> %x3, %t2 %t3 = icmp ugt <8 x i16> %x3, %t2
%t4 = select <8 x i1> %t3, <8 x i16> %x3, <8 x i16> %t2 %t4 = select <8 x i1> %t3, <8 x i16> %x3, <8 x i16> %t2
ret <8 x i16> %t4 ret <8 x i16> %t4
} }
define <4 x i32> @reassociate_umax_v4i32(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, <4 x i32> %x3) { define <4 x i32> @reassociate_umax_v4i32(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, <4 x i32> %x3) {
; SSE-LABEL: reassociate_umax_v4i32: ; SSE-LABEL: reassociate_umax_v4i32:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movdqa {{.*#+}} xmm6 = [2147483648,2147483648,2147483648,2147483648]
; SSE-NEXT: paddd %xmm1, %xmm0 ; SSE-NEXT: paddd %xmm1, %xmm0
; SSE-NEXT: movdqa {{.*#+}} xmm1 = [2147483648,2147483648,2147483648,2147483648]
; SSE-NEXT: movdqa %xmm2, %xmm4 ; SSE-NEXT: movdqa %xmm2, %xmm4
; SSE-NEXT: pxor %xmm1, %xmm4
; SSE-NEXT: movdqa %xmm0, %xmm5 ; SSE-NEXT: movdqa %xmm0, %xmm5
; SSE-NEXT: pxor %xmm1, %xmm5 ; SSE-NEXT: pxor %xmm6, %xmm4
; SSE-NEXT: pxor %xmm6, %xmm5
; SSE-NEXT: pcmpgtd %xmm5, %xmm4 ; SSE-NEXT: pcmpgtd %xmm5, %xmm4
; SSE-NEXT: pand %xmm4, %xmm2 ; SSE-NEXT: pand %xmm4, %xmm2
; SSE-NEXT: pandn %xmm0, %xmm4 ; SSE-NEXT: pandn %xmm0, %xmm4
; SSE-NEXT: por %xmm2, %xmm4 ; SSE-NEXT: por %xmm2, %xmm4
; SSE-NEXT: movdqa %xmm4, %xmm0 ; SSE-NEXT: movdqa %xmm4, %xmm0
; SSE-NEXT: pxor %xmm1, %xmm0 ; SSE-NEXT: pxor %xmm6, %xmm0
; SSE-NEXT: pxor %xmm3, %xmm1 ; SSE-NEXT: pxor %xmm3, %xmm6
; SSE-NEXT: pcmpgtd %xmm0, %xmm1 ; SSE-NEXT: pcmpgtd %xmm0, %xmm6
; SSE-NEXT: pand %xmm1, %xmm3 ; SSE-NEXT: pand %xmm6, %xmm3
; SSE-NEXT: pandn %xmm4, %xmm1 ; SSE-NEXT: pandn %xmm4, %xmm6
; SSE-NEXT: por %xmm3, %xmm1 ; SSE-NEXT: por %xmm3, %xmm6
; SSE-NEXT: movdqa %xmm1, %xmm0 ; SSE-NEXT: movdqa %xmm6, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: reassociate_umax_v4i32: ; AVX-LABEL: reassociate_umax_v4i32:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpmaxud %xmm3, %xmm2, %xmm1 ; AVX-NEXT: vpmaxud %xmm3, %xmm2, %xmm2
; AVX-NEXT: vpmaxud %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpmaxud %xmm2, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%t0 = add <4 x i32> %x0, %x1 %t0 = add <4 x i32> %x0, %x1
%t1 = icmp ugt <4 x i32> %x2, %t0 %t1 = icmp ugt <4 x i32> %x2, %t0
%t2 = select <4 x i1> %t1, <4 x i32> %x2, <4 x i32> %t0 %t2 = select <4 x i1> %t1, <4 x i32> %x2, <4 x i32> %t0
%t3 = icmp ugt <4 x i32> %x3, %t2 %t3 = icmp ugt <4 x i32> %x3, %t2
%t4 = select <4 x i1> %t3, <4 x i32> %x3, <4 x i32> %t2 %t4 = select <4 x i1> %t3, <4 x i32> %x3, <4 x i32> %t2
ret <4 x i32> %t4 ret <4 x i32> %t4
} }
define <2 x i64> @reassociate_umax_v2i64(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, <2 x i64> %x3) { define <2 x i64> @reassociate_umax_v2i64(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, <2 x i64> %x3) {
; SSE-LABEL: reassociate_umax_v2i64: ; SSE-LABEL: reassociate_umax_v2i64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: paddq %xmm1, %xmm0 ; SSE-NEXT: paddq %xmm1, %xmm0
; SSE-NEXT: movdqa {{.*#+}} xmm1 = [9223372039002259456,9223372039002259456] ; SSE-NEXT: movdqa {{.*#+}} xmm1 = [9223372039002259456,9223372039002259456]
; SSE-NEXT: movdqa %xmm2, %xmm4 ; SSE-NEXT: movdqa %xmm2, %xmm4
; SSE-NEXT: pxor %xmm1, %xmm4
; SSE-NEXT: movdqa %xmm0, %xmm5 ; SSE-NEXT: movdqa %xmm0, %xmm5
; SSE-NEXT: pxor %xmm1, %xmm4
; SSE-NEXT: pxor %xmm1, %xmm5 ; SSE-NEXT: pxor %xmm1, %xmm5
; SSE-NEXT: movdqa %xmm4, %xmm6 ; SSE-NEXT: movdqa %xmm4, %xmm6
; SSE-NEXT: pcmpgtd %xmm5, %xmm6 ; SSE-NEXT: pcmpgtd %xmm5, %xmm6
; SSE-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2]
; SSE-NEXT: pcmpeqd %xmm4, %xmm5 ; SSE-NEXT: pcmpeqd %xmm4, %xmm5
; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm5[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm5[1,1,3,3]
; SSE-NEXT: pand %xmm7, %xmm4 ; SSE-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm6[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm6[1,1,3,3]
; SSE-NEXT: pand %xmm7, %xmm4
; SSE-NEXT: por %xmm4, %xmm5 ; SSE-NEXT: por %xmm4, %xmm5
; SSE-NEXT: pand %xmm5, %xmm2 ; SSE-NEXT: pand %xmm5, %xmm2
; SSE-NEXT: pandn %xmm0, %xmm5 ; SSE-NEXT: pandn %xmm0, %xmm5
; SSE-NEXT: por %xmm2, %xmm5 ; SSE-NEXT: por %xmm2, %xmm5
; SSE-NEXT: movdqa %xmm5, %xmm0 ; SSE-NEXT: movdqa %xmm5, %xmm0
; SSE-NEXT: pxor %xmm1, %xmm0 ; SSE-NEXT: pxor %xmm1, %xmm0
; SSE-NEXT: pxor %xmm3, %xmm1 ; SSE-NEXT: pxor %xmm3, %xmm1
; SSE-NEXT: movdqa %xmm1, %xmm2 ; SSE-NEXT: movdqa %xmm1, %xmm2
; SSE-NEXT: pcmpgtd %xmm0, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm2[0,0,2,2]
; SSE-NEXT: pcmpeqd %xmm0, %xmm1 ; SSE-NEXT: pcmpeqd %xmm0, %xmm1
; SSE-NEXT: pcmpgtd %xmm0, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; SSE-NEXT: pand %xmm4, %xmm1 ; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm2[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,3,3]
; SSE-NEXT: pand %xmm4, %xmm1
; SSE-NEXT: por %xmm1, %xmm0 ; SSE-NEXT: por %xmm1, %xmm0
; SSE-NEXT: pand %xmm0, %xmm3 ; SSE-NEXT: pand %xmm0, %xmm3
; SSE-NEXT: pandn %xmm5, %xmm0 ; SSE-NEXT: pandn %xmm5, %xmm0
; SSE-NEXT: por %xmm3, %xmm0 ; SSE-NEXT: por %xmm3, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX2-LABEL: reassociate_umax_v2i64: ; AVX2-LABEL: reassociate_umax_v2i64:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpaddq %xmm1, %xmm0, %xmm0 ; AVX2-NEXT: vpaddq %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vmovdqa {{.*#+}} xmm1 = [9223372036854775808,9223372036854775808] ; AVX2-NEXT: vmovdqa {{.*#+}} xmm1 = [9223372036854775808,9223372036854775808]
; AVX2-NEXT: vpxor %xmm1, %xmm2, %xmm4 ; AVX2-NEXT: vpxor %xmm1, %xmm2, %xmm4
; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm5 ; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm5
; AVX2-NEXT: vpcmpgtq %xmm5, %xmm4, %xmm4 ; AVX2-NEXT: vpcmpgtq %xmm5, %xmm4, %xmm4
; AVX2-NEXT: vblendvpd %xmm4, %xmm2, %xmm0, %xmm0 ; AVX2-NEXT: vblendvpd %xmm4, %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vxorpd %xmm1, %xmm0, %xmm2 ; AVX2-NEXT: vxorpd %xmm1, %xmm0, %xmm2
; AVX2-NEXT: vpxor %xmm1, %xmm3, %xmm1 ; AVX2-NEXT: vpxor %xmm1, %xmm3, %xmm1
; AVX2-NEXT: vpcmpgtq %xmm2, %xmm1, %xmm1 ; AVX2-NEXT: vpcmpgtq %xmm2, %xmm1, %xmm1
; AVX2-NEXT: vblendvpd %xmm1, %xmm3, %xmm0, %xmm0 ; AVX2-NEXT: vblendvpd %xmm1, %xmm3, %xmm0, %xmm0
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: reassociate_umax_v2i64: ; AVX512-LABEL: reassociate_umax_v2i64:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vpaddq %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vpaddq %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpmaxuq %xmm3, %xmm2, %xmm1 ; AVX512-NEXT: vpmaxuq %xmm3, %xmm2, %xmm2
; AVX512-NEXT: vpmaxuq %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vpmaxuq %xmm2, %xmm0, %xmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%t0 = add <2 x i64> %x0, %x1 %t0 = add <2 x i64> %x0, %x1
%t1 = icmp ugt <2 x i64> %x2, %t0 %t1 = icmp ugt <2 x i64> %x2, %t0
%t2 = select <2 x i1> %t1, <2 x i64> %x2, <2 x i64> %t0 %t2 = select <2 x i1> %t1, <2 x i64> %x2, <2 x i64> %t0
%t3 = icmp ugt <2 x i64> %x3, %t2 %t3 = icmp ugt <2 x i64> %x3, %t2
%t4 = select <2 x i1> %t3, <2 x i64> %x3, <2 x i64> %t2 %t4 = select <2 x i1> %t3, <2 x i64> %x3, <2 x i64> %t2
ret <2 x i64> %t4 ret <2 x i64> %t4
} }
define <16 x i8> @reassociate_smax_v16i8(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, <16 x i8> %x3) { define <16 x i8> @reassociate_smax_v16i8(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, <16 x i8> %x3) {
; SSE-LABEL: reassociate_smax_v16i8: ; SSE-LABEL: reassociate_smax_v16i8:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: paddb %xmm1, %xmm0 ; SSE-NEXT: paddb %xmm1, %xmm0
; SSE-NEXT: movdqa %xmm2, %xmm1 ; SSE-NEXT: movdqa %xmm2, %xmm4
; SSE-NEXT: pcmpgtb %xmm0, %xmm1 ; SSE-NEXT: pcmpgtb %xmm0, %xmm4
; SSE-NEXT: pand %xmm1, %xmm2 ; SSE-NEXT: pand %xmm4, %xmm2
; SSE-NEXT: pandn %xmm0, %xmm1 ; SSE-NEXT: pandn %xmm0, %xmm4
; SSE-NEXT: por %xmm2, %xmm1
; SSE-NEXT: movdqa %xmm3, %xmm0 ; SSE-NEXT: movdqa %xmm3, %xmm0
; SSE-NEXT: pcmpgtb %xmm1, %xmm0 ; SSE-NEXT: por %xmm2, %xmm4
; SSE-NEXT: pcmpgtb %xmm4, %xmm0
; SSE-NEXT: pand %xmm0, %xmm3 ; SSE-NEXT: pand %xmm0, %xmm3
; SSE-NEXT: pandn %xmm1, %xmm0 ; SSE-NEXT: pandn %xmm4, %xmm0
; SSE-NEXT: por %xmm3, %xmm0 ; SSE-NEXT: por %xmm3, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: reassociate_smax_v16i8: ; AVX-LABEL: reassociate_smax_v16i8:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpaddb %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpaddb %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpmaxsb %xmm3, %xmm2, %xmm1 ; AVX-NEXT: vpmaxsb %xmm3, %xmm2, %xmm2
; AVX-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpmaxsb %xmm2, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%t0 = add <16 x i8> %x0, %x1 %t0 = add <16 x i8> %x0, %x1
%t1 = icmp sgt <16 x i8> %x2, %t0 %t1 = icmp sgt <16 x i8> %x2, %t0
%t2 = select <16 x i1> %t1, <16 x i8> %x2, <16 x i8> %t0 %t2 = select <16 x i1> %t1, <16 x i8> %x2, <16 x i8> %t0
%t3 = icmp sgt <16 x i8> %x3, %t2 %t3 = icmp sgt <16 x i8> %x3, %t2
%t4 = select <16 x i1> %t3, <16 x i8> %x3, <16 x i8> %t2 %t4 = select <16 x i1> %t3, <16 x i8> %x3, <16 x i8> %t2
ret <16 x i8> %t4 ret <16 x i8> %t4
} }
define <8 x i16> @reassociate_smax_v8i16(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, <8 x i16> %x3) { define <8 x i16> @reassociate_smax_v8i16(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, <8 x i16> %x3) {
; SSE-LABEL: reassociate_smax_v8i16: ; SSE-LABEL: reassociate_smax_v8i16:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: paddw %xmm1, %xmm0 ; SSE-NEXT: paddw %xmm1, %xmm0
; SSE-NEXT: pmaxsw %xmm3, %xmm2 ; SSE-NEXT: pmaxsw %xmm3, %xmm2
; SSE-NEXT: pmaxsw %xmm2, %xmm0 ; SSE-NEXT: pmaxsw %xmm2, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: reassociate_smax_v8i16: ; AVX-LABEL: reassociate_smax_v8i16:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpaddw %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpaddw %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpmaxsw %xmm3, %xmm2, %xmm1 ; AVX-NEXT: vpmaxsw %xmm3, %xmm2, %xmm2
; AVX-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpmaxsw %xmm2, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%t0 = add <8 x i16> %x0, %x1 %t0 = add <8 x i16> %x0, %x1
%t1 = icmp sgt <8 x i16> %x2, %t0 %t1 = icmp sgt <8 x i16> %x2, %t0
%t2 = select <8 x i1> %t1, <8 x i16> %x2, <8 x i16> %t0 %t2 = select <8 x i1> %t1, <8 x i16> %x2, <8 x i16> %t0
%t3 = icmp sgt <8 x i16> %x3, %t2 %t3 = icmp sgt <8 x i16> %x3, %t2
%t4 = select <8 x i1> %t3, <8 x i16> %x3, <8 x i16> %t2 %t4 = select <8 x i1> %t3, <8 x i16> %x3, <8 x i16> %t2
ret <8 x i16> %t4 ret <8 x i16> %t4
} }
define <4 x i32> @reassociate_smax_v4i32(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, <4 x i32> %x3) { define <4 x i32> @reassociate_smax_v4i32(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, <4 x i32> %x3) {
; SSE-LABEL: reassociate_smax_v4i32: ; SSE-LABEL: reassociate_smax_v4i32:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: paddd %xmm1, %xmm0 ; SSE-NEXT: paddd %xmm1, %xmm0
; SSE-NEXT: movdqa %xmm2, %xmm1 ; SSE-NEXT: movdqa %xmm2, %xmm4
; SSE-NEXT: pcmpgtd %xmm0, %xmm1 ; SSE-NEXT: pcmpgtd %xmm0, %xmm4
; SSE-NEXT: pand %xmm1, %xmm2 ; SSE-NEXT: pand %xmm4, %xmm2
; SSE-NEXT: pandn %xmm0, %xmm1 ; SSE-NEXT: pandn %xmm0, %xmm4
; SSE-NEXT: por %xmm2, %xmm1
; SSE-NEXT: movdqa %xmm3, %xmm0 ; SSE-NEXT: movdqa %xmm3, %xmm0
; SSE-NEXT: pcmpgtd %xmm1, %xmm0 ; SSE-NEXT: por %xmm2, %xmm4
; SSE-NEXT: pcmpgtd %xmm4, %xmm0
; SSE-NEXT: pand %xmm0, %xmm3 ; SSE-NEXT: pand %xmm0, %xmm3
; SSE-NEXT: pandn %xmm1, %xmm0 ; SSE-NEXT: pandn %xmm4, %xmm0
; SSE-NEXT: por %xmm3, %xmm0 ; SSE-NEXT: por %xmm3, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: reassociate_smax_v4i32: ; AVX-LABEL: reassociate_smax_v4i32:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpmaxsd %xmm3, %xmm2, %xmm1 ; AVX-NEXT: vpmaxsd %xmm3, %xmm2, %xmm2
; AVX-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpmaxsd %xmm2, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%t0 = add <4 x i32> %x0, %x1 %t0 = add <4 x i32> %x0, %x1
%t1 = icmp sgt <4 x i32> %x2, %t0 %t1 = icmp sgt <4 x i32> %x2, %t0
%t2 = select <4 x i1> %t1, <4 x i32> %x2, <4 x i32> %t0 %t2 = select <4 x i1> %t1, <4 x i32> %x2, <4 x i32> %t0
%t3 = icmp sgt <4 x i32> %x3, %t2 %t3 = icmp sgt <4 x i32> %x3, %t2
%t4 = select <4 x i1> %t3, <4 x i32> %x3, <4 x i32> %t2 %t4 = select <4 x i1> %t3, <4 x i32> %x3, <4 x i32> %t2
ret <4 x i32> %t4 ret <4 x i32> %t4
} }
define <2 x i64> @reassociate_smax_v2i64(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, <2 x i64> %x3) { define <2 x i64> @reassociate_smax_v2i64(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, <2 x i64> %x3) {
; SSE-LABEL: reassociate_smax_v2i64: ; SSE-LABEL: reassociate_smax_v2i64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: paddq %xmm1, %xmm0 ; SSE-NEXT: paddq %xmm1, %xmm0
; SSE-NEXT: movdqa {{.*#+}} xmm1 = [2147483648,2147483648] ; SSE-NEXT: movdqa {{.*#+}} xmm1 = [2147483648,2147483648]
; SSE-NEXT: movdqa %xmm2, %xmm4 ; SSE-NEXT: movdqa %xmm2, %xmm4
; SSE-NEXT: pxor %xmm1, %xmm4
; SSE-NEXT: movdqa %xmm0, %xmm5 ; SSE-NEXT: movdqa %xmm0, %xmm5
; SSE-NEXT: pxor %xmm1, %xmm4
; SSE-NEXT: pxor %xmm1, %xmm5 ; SSE-NEXT: pxor %xmm1, %xmm5
; SSE-NEXT: movdqa %xmm4, %xmm6 ; SSE-NEXT: movdqa %xmm4, %xmm6
; SSE-NEXT: pcmpgtd %xmm5, %xmm6 ; SSE-NEXT: pcmpgtd %xmm5, %xmm6
; SSE-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2]
; SSE-NEXT: pcmpeqd %xmm4, %xmm5 ; SSE-NEXT: pcmpeqd %xmm4, %xmm5
; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm5[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm5[1,1,3,3]
; SSE-NEXT: pand %xmm7, %xmm4 ; SSE-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm6[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm6[1,1,3,3]
; SSE-NEXT: pand %xmm7, %xmm4
; SSE-NEXT: por %xmm4, %xmm5 ; SSE-NEXT: por %xmm4, %xmm5
; SSE-NEXT: pand %xmm5, %xmm2 ; SSE-NEXT: pand %xmm5, %xmm2
; SSE-NEXT: pandn %xmm0, %xmm5 ; SSE-NEXT: pandn %xmm0, %xmm5
; SSE-NEXT: por %xmm2, %xmm5 ; SSE-NEXT: por %xmm2, %xmm5
; SSE-NEXT: movdqa %xmm5, %xmm0 ; SSE-NEXT: movdqa %xmm5, %xmm0
; SSE-NEXT: pxor %xmm1, %xmm0 ; SSE-NEXT: pxor %xmm1, %xmm0
; SSE-NEXT: pxor %xmm3, %xmm1 ; SSE-NEXT: pxor %xmm3, %xmm1
; SSE-NEXT: movdqa %xmm1, %xmm2 ; SSE-NEXT: movdqa %xmm1, %xmm2
; SSE-NEXT: pcmpgtd %xmm0, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm2[0,0,2,2]
; SSE-NEXT: pcmpeqd %xmm0, %xmm1 ; SSE-NEXT: pcmpeqd %xmm0, %xmm1
; SSE-NEXT: pcmpgtd %xmm0, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; SSE-NEXT: pand %xmm4, %xmm1 ; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm2[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,3,3]
; SSE-NEXT: pand %xmm4, %xmm1
; SSE-NEXT: por %xmm1, %xmm0 ; SSE-NEXT: por %xmm1, %xmm0
; SSE-NEXT: pand %xmm0, %xmm3 ; SSE-NEXT: pand %xmm0, %xmm3
; SSE-NEXT: pandn %xmm5, %xmm0 ; SSE-NEXT: pandn %xmm5, %xmm0
; SSE-NEXT: por %xmm3, %xmm0 ; SSE-NEXT: por %xmm3, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX2-LABEL: reassociate_smax_v2i64: ; AVX2-LABEL: reassociate_smax_v2i64:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpaddq %xmm1, %xmm0, %xmm0 ; AVX2-NEXT: vpaddq %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpcmpgtq %xmm0, %xmm2, %xmm1 ; AVX2-NEXT: vpcmpgtq %xmm0, %xmm2, %xmm1
; AVX2-NEXT: vblendvpd %xmm1, %xmm2, %xmm0, %xmm0 ; AVX2-NEXT: vblendvpd %xmm1, %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpcmpgtq %xmm0, %xmm3, %xmm1 ; AVX2-NEXT: vpcmpgtq %xmm0, %xmm3, %xmm1
; AVX2-NEXT: vblendvpd %xmm1, %xmm3, %xmm0, %xmm0 ; AVX2-NEXT: vblendvpd %xmm1, %xmm3, %xmm0, %xmm0
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: reassociate_smax_v2i64: ; AVX512-LABEL: reassociate_smax_v2i64:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vpaddq %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vpaddq %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpmaxsq %xmm3, %xmm2, %xmm1 ; AVX512-NEXT: vpmaxsq %xmm3, %xmm2, %xmm2
; AVX512-NEXT: vpmaxsq %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vpmaxsq %xmm2, %xmm0, %xmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%t0 = add <2 x i64> %x0, %x1 %t0 = add <2 x i64> %x0, %x1
%t1 = icmp sgt <2 x i64> %x2, %t0 %t1 = icmp sgt <2 x i64> %x2, %t0
%t2 = select <2 x i1> %t1, <2 x i64> %x2, <2 x i64> %t0 %t2 = select <2 x i1> %t1, <2 x i64> %x2, <2 x i64> %t0
%t3 = icmp sgt <2 x i64> %x3, %t2 %t3 = icmp sgt <2 x i64> %x3, %t2
%t4 = select <2 x i1> %t3, <2 x i64> %x3, <2 x i64> %t2 %t4 = select <2 x i1> %t3, <2 x i64> %x3, <2 x i64> %t2
ret <2 x i64> %t4 ret <2 x i64> %t4
} }
define <16 x i8> @reassociate_umin_v16i8(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, <16 x i8> %x3) { define <16 x i8> @reassociate_umin_v16i8(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, <16 x i8> %x3) {
; SSE-LABEL: reassociate_umin_v16i8: ; SSE-LABEL: reassociate_umin_v16i8:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: paddb %xmm1, %xmm0 ; SSE-NEXT: paddb %xmm1, %xmm0
; SSE-NEXT: pminub %xmm3, %xmm2 ; SSE-NEXT: pminub %xmm3, %xmm2
; SSE-NEXT: pminub %xmm2, %xmm0 ; SSE-NEXT: pminub %xmm2, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: reassociate_umin_v16i8: ; AVX-LABEL: reassociate_umin_v16i8:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpaddb %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpaddb %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpminub %xmm3, %xmm2, %xmm1 ; AVX-NEXT: vpminub %xmm3, %xmm2, %xmm2
; AVX-NEXT: vpminub %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpminub %xmm2, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%t0 = add <16 x i8> %x0, %x1 %t0 = add <16 x i8> %x0, %x1
%t1 = icmp ult <16 x i8> %x2, %t0 %t1 = icmp ult <16 x i8> %x2, %t0
%t2 = select <16 x i1> %t1, <16 x i8> %x2, <16 x i8> %t0 %t2 = select <16 x i1> %t1, <16 x i8> %x2, <16 x i8> %t0
%t3 = icmp ult <16 x i8> %x3, %t2 %t3 = icmp ult <16 x i8> %x3, %t2
%t4 = select <16 x i1> %t3, <16 x i8> %x3, <16 x i8> %t2 %t4 = select <16 x i1> %t3, <16 x i8> %x3, <16 x i8> %t2
ret <16 x i8> %t4 ret <16 x i8> %t4
} }
define <8 x i16> @reassociate_umin_v8i16(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, <8 x i16> %x3) { define <8 x i16> @reassociate_umin_v8i16(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, <8 x i16> %x3) {
; SSE-LABEL: reassociate_umin_v8i16: ; SSE-LABEL: reassociate_umin_v8i16:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movdqa {{.*#+}} xmm4 = [32768,32768,32768,32768,32768,32768,32768,32768]
; SSE-NEXT: paddw %xmm1, %xmm0 ; SSE-NEXT: paddw %xmm1, %xmm0
; SSE-NEXT: movdqa {{.*#+}} xmm1 = [32768,32768,32768,32768,32768,32768,32768,32768] ; SSE-NEXT: pxor %xmm4, %xmm2
; SSE-NEXT: pxor %xmm1, %xmm2 ; SSE-NEXT: pxor %xmm4, %xmm0
; SSE-NEXT: pxor %xmm1, %xmm0 ; SSE-NEXT: pxor %xmm4, %xmm3
; SSE-NEXT: pminsw %xmm2, %xmm0 ; SSE-NEXT: pminsw %xmm2, %xmm0
; SSE-NEXT: pxor %xmm1, %xmm3
; SSE-NEXT: pminsw %xmm3, %xmm0 ; SSE-NEXT: pminsw %xmm3, %xmm0
; SSE-NEXT: pxor %xmm1, %xmm0 ; SSE-NEXT: pxor %xmm4, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: reassociate_umin_v8i16: ; AVX-LABEL: reassociate_umin_v8i16:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpaddw %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpaddw %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpminuw %xmm3, %xmm2, %xmm1 ; AVX-NEXT: vpminuw %xmm3, %xmm2, %xmm2
; AVX-NEXT: vpminuw %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpminuw %xmm2, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%t0 = add <8 x i16> %x0, %x1 %t0 = add <8 x i16> %x0, %x1
%t1 = icmp ult <8 x i16> %x2, %t0 %t1 = icmp ult <8 x i16> %x2, %t0
%t2 = select <8 x i1> %t1, <8 x i16> %x2, <8 x i16> %t0 %t2 = select <8 x i1> %t1, <8 x i16> %x2, <8 x i16> %t0
%t3 = icmp ult <8 x i16> %x3, %t2 %t3 = icmp ult <8 x i16> %x3, %t2
%t4 = select <8 x i1> %t3, <8 x i16> %x3, <8 x i16> %t2 %t4 = select <8 x i1> %t3, <8 x i16> %x3, <8 x i16> %t2
ret <8 x i16> %t4 ret <8 x i16> %t4
} }
define <4 x i32> @reassociate_umin_v4i32(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, <4 x i32> %x3) { define <4 x i32> @reassociate_umin_v4i32(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, <4 x i32> %x3) {
; SSE-LABEL: reassociate_umin_v4i32: ; SSE-LABEL: reassociate_umin_v4i32:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movdqa {{.*#+}} xmm6 = [2147483648,2147483648,2147483648,2147483648]
; SSE-NEXT: paddd %xmm1, %xmm0 ; SSE-NEXT: paddd %xmm1, %xmm0
; SSE-NEXT: movdqa {{.*#+}} xmm1 = [2147483648,2147483648,2147483648,2147483648]
; SSE-NEXT: movdqa %xmm2, %xmm4 ; SSE-NEXT: movdqa %xmm2, %xmm4
; SSE-NEXT: pxor %xmm1, %xmm4
; SSE-NEXT: movdqa %xmm0, %xmm5 ; SSE-NEXT: movdqa %xmm0, %xmm5
; SSE-NEXT: pxor %xmm1, %xmm5 ; SSE-NEXT: pxor %xmm6, %xmm4
; SSE-NEXT: pxor %xmm6, %xmm5
; SSE-NEXT: pcmpgtd %xmm4, %xmm5 ; SSE-NEXT: pcmpgtd %xmm4, %xmm5
; SSE-NEXT: pand %xmm5, %xmm2 ; SSE-NEXT: pand %xmm5, %xmm2
; SSE-NEXT: pandn %xmm0, %xmm5 ; SSE-NEXT: pandn %xmm0, %xmm5
; SSE-NEXT: por %xmm2, %xmm5 ; SSE-NEXT: por %xmm2, %xmm5
; SSE-NEXT: movdqa %xmm5, %xmm0 ; SSE-NEXT: movdqa %xmm5, %xmm0
; SSE-NEXT: pxor %xmm1, %xmm0 ; SSE-NEXT: pxor %xmm6, %xmm0
; SSE-NEXT: pxor %xmm3, %xmm1 ; SSE-NEXT: pxor %xmm3, %xmm6
; SSE-NEXT: pcmpgtd %xmm1, %xmm0 ; SSE-NEXT: pcmpgtd %xmm6, %xmm0
; SSE-NEXT: pand %xmm0, %xmm3 ; SSE-NEXT: pand %xmm0, %xmm3
; SSE-NEXT: pandn %xmm5, %xmm0 ; SSE-NEXT: pandn %xmm5, %xmm0
; SSE-NEXT: por %xmm3, %xmm0 ; SSE-NEXT: por %xmm3, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: reassociate_umin_v4i32: ; AVX-LABEL: reassociate_umin_v4i32:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpminud %xmm3, %xmm2, %xmm1 ; AVX-NEXT: vpminud %xmm3, %xmm2, %xmm2
; AVX-NEXT: vpminud %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpminud %xmm2, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%t0 = add <4 x i32> %x0, %x1 %t0 = add <4 x i32> %x0, %x1
%t1 = icmp ult <4 x i32> %x2, %t0 %t1 = icmp ult <4 x i32> %x2, %t0
%t2 = select <4 x i1> %t1, <4 x i32> %x2, <4 x i32> %t0 %t2 = select <4 x i1> %t1, <4 x i32> %x2, <4 x i32> %t0
%t3 = icmp ult <4 x i32> %x3, %t2 %t3 = icmp ult <4 x i32> %x3, %t2
%t4 = select <4 x i1> %t3, <4 x i32> %x3, <4 x i32> %t2 %t4 = select <4 x i1> %t3, <4 x i32> %x3, <4 x i32> %t2
ret <4 x i32> %t4 ret <4 x i32> %t4
} }
define <2 x i64> @reassociate_umin_v2i64(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, <2 x i64> %x3) { define <2 x i64> @reassociate_umin_v2i64(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, <2 x i64> %x3) {
; SSE-LABEL: reassociate_umin_v2i64: ; SSE-LABEL: reassociate_umin_v2i64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: paddq %xmm1, %xmm0 ; SSE-NEXT: paddq %xmm1, %xmm0
; SSE-NEXT: movdqa {{.*#+}} xmm1 = [9223372039002259456,9223372039002259456] ; SSE-NEXT: movdqa {{.*#+}} xmm1 = [9223372039002259456,9223372039002259456]
; SSE-NEXT: movdqa %xmm2, %xmm4 ; SSE-NEXT: movdqa %xmm2, %xmm4
; SSE-NEXT: pxor %xmm1, %xmm4
; SSE-NEXT: movdqa %xmm0, %xmm5 ; SSE-NEXT: movdqa %xmm0, %xmm5
; SSE-NEXT: pxor %xmm1, %xmm5 ; SSE-NEXT: pxor %xmm1, %xmm5
; SSE-NEXT: pxor %xmm1, %xmm4
; SSE-NEXT: movdqa %xmm5, %xmm6 ; SSE-NEXT: movdqa %xmm5, %xmm6
; SSE-NEXT: pcmpgtd %xmm4, %xmm6
; SSE-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2]
; SSE-NEXT: pcmpeqd %xmm4, %xmm5 ; SSE-NEXT: pcmpeqd %xmm4, %xmm5
; SSE-NEXT: pcmpgtd %xmm4, %xmm6
; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm5[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm5[1,1,3,3]
; SSE-NEXT: pand %xmm7, %xmm4 ; SSE-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm6[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm6[1,1,3,3]
; SSE-NEXT: pand %xmm7, %xmm4
; SSE-NEXT: por %xmm4, %xmm5 ; SSE-NEXT: por %xmm4, %xmm5
; SSE-NEXT: pand %xmm5, %xmm2 ; SSE-NEXT: pand %xmm5, %xmm2
; SSE-NEXT: pandn %xmm0, %xmm5 ; SSE-NEXT: pandn %xmm0, %xmm5
; SSE-NEXT: por %xmm2, %xmm5 ; SSE-NEXT: por %xmm2, %xmm5
; SSE-NEXT: movdqa %xmm5, %xmm0 ; SSE-NEXT: movdqa %xmm5, %xmm0
; SSE-NEXT: pxor %xmm1, %xmm0 ; SSE-NEXT: pxor %xmm1, %xmm0
; SSE-NEXT: pxor %xmm3, %xmm1 ; SSE-NEXT: pxor %xmm3, %xmm1
; SSE-NEXT: movdqa %xmm0, %xmm2 ; SSE-NEXT: movdqa %xmm0, %xmm2
; SSE-NEXT: pcmpgtd %xmm1, %xmm2 ; SSE-NEXT: pcmpgtd %xmm1, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm2[0,0,2,2]
; SSE-NEXT: pcmpeqd %xmm0, %xmm1 ; SSE-NEXT: pcmpeqd %xmm0, %xmm1
; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm2[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; SSE-NEXT: pand %xmm4, %xmm1
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,3,3]
; SSE-NEXT: pand %xmm4, %xmm1
; SSE-NEXT: por %xmm1, %xmm0 ; SSE-NEXT: por %xmm1, %xmm0
; SSE-NEXT: pand %xmm0, %xmm3 ; SSE-NEXT: pand %xmm0, %xmm3
; SSE-NEXT: pandn %xmm5, %xmm0 ; SSE-NEXT: pandn %xmm5, %xmm0
; SSE-NEXT: por %xmm3, %xmm0 ; SSE-NEXT: por %xmm3, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX2-LABEL: reassociate_umin_v2i64: ; AVX2-LABEL: reassociate_umin_v2i64:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpaddq %xmm1, %xmm0, %xmm0 ; AVX2-NEXT: vpaddq %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vmovdqa {{.*#+}} xmm1 = [9223372036854775808,9223372036854775808] ; AVX2-NEXT: vmovdqa {{.*#+}} xmm1 = [9223372036854775808,9223372036854775808]
; AVX2-NEXT: vpxor %xmm1, %xmm2, %xmm4 ; AVX2-NEXT: vpxor %xmm1, %xmm2, %xmm4
; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm5 ; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm5
; AVX2-NEXT: vpcmpgtq %xmm4, %xmm5, %xmm4 ; AVX2-NEXT: vpcmpgtq %xmm4, %xmm5, %xmm4
; AVX2-NEXT: vblendvpd %xmm4, %xmm2, %xmm0, %xmm0 ; AVX2-NEXT: vblendvpd %xmm4, %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vxorpd %xmm1, %xmm0, %xmm2 ; AVX2-NEXT: vxorpd %xmm1, %xmm0, %xmm2
; AVX2-NEXT: vpxor %xmm1, %xmm3, %xmm1 ; AVX2-NEXT: vpxor %xmm1, %xmm3, %xmm1
; AVX2-NEXT: vpcmpgtq %xmm1, %xmm2, %xmm1 ; AVX2-NEXT: vpcmpgtq %xmm1, %xmm2, %xmm1
; AVX2-NEXT: vblendvpd %xmm1, %xmm3, %xmm0, %xmm0 ; AVX2-NEXT: vblendvpd %xmm1, %xmm3, %xmm0, %xmm0
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: reassociate_umin_v2i64: ; AVX512-LABEL: reassociate_umin_v2i64:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vpaddq %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vpaddq %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpminuq %xmm3, %xmm2, %xmm1 ; AVX512-NEXT: vpminuq %xmm3, %xmm2, %xmm2
; AVX512-NEXT: vpminuq %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vpminuq %xmm2, %xmm0, %xmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%t0 = add <2 x i64> %x0, %x1 %t0 = add <2 x i64> %x0, %x1
%t1 = icmp ult <2 x i64> %x2, %t0 %t1 = icmp ult <2 x i64> %x2, %t0
%t2 = select <2 x i1> %t1, <2 x i64> %x2, <2 x i64> %t0 %t2 = select <2 x i1> %t1, <2 x i64> %x2, <2 x i64> %t0
%t3 = icmp ult <2 x i64> %x3, %t2 %t3 = icmp ult <2 x i64> %x3, %t2
%t4 = select <2 x i1> %t3, <2 x i64> %x3, <2 x i64> %t2 %t4 = select <2 x i1> %t3, <2 x i64> %x3, <2 x i64> %t2
ret <2 x i64> %t4 ret <2 x i64> %t4
Show All 13 Lines
; SSE-NEXT: pand %xmm0, %xmm3 ; SSE-NEXT: pand %xmm0, %xmm3
; SSE-NEXT: pandn %xmm1, %xmm0 ; SSE-NEXT: pandn %xmm1, %xmm0
; SSE-NEXT: por %xmm3, %xmm0 ; SSE-NEXT: por %xmm3, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: reassociate_smin_v16i8: ; AVX-LABEL: reassociate_smin_v16i8:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpaddb %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpaddb %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpminsb %xmm3, %xmm2, %xmm1 ; AVX-NEXT: vpminsb %xmm3, %xmm2, %xmm2
; AVX-NEXT: vpminsb %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpminsb %xmm2, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%t0 = add <16 x i8> %x0, %x1 %t0 = add <16 x i8> %x0, %x1
%t1 = icmp slt <16 x i8> %x2, %t0 %t1 = icmp slt <16 x i8> %x2, %t0
%t2 = select <16 x i1> %t1, <16 x i8> %x2, <16 x i8> %t0 %t2 = select <16 x i1> %t1, <16 x i8> %x2, <16 x i8> %t0
%t3 = icmp slt <16 x i8> %x3, %t2 %t3 = icmp slt <16 x i8> %x3, %t2
%t4 = select <16 x i1> %t3, <16 x i8> %x3, <16 x i8> %t2 %t4 = select <16 x i1> %t3, <16 x i8> %x3, <16 x i8> %t2
ret <16 x i8> %t4 ret <16 x i8> %t4
} }
define <8 x i16> @reassociate_smin_v8i16(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, <8 x i16> %x3) { define <8 x i16> @reassociate_smin_v8i16(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, <8 x i16> %x3) {
; SSE-LABEL: reassociate_smin_v8i16: ; SSE-LABEL: reassociate_smin_v8i16:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: paddw %xmm1, %xmm0 ; SSE-NEXT: paddw %xmm1, %xmm0
; SSE-NEXT: pminsw %xmm3, %xmm2 ; SSE-NEXT: pminsw %xmm3, %xmm2
; SSE-NEXT: pminsw %xmm2, %xmm0 ; SSE-NEXT: pminsw %xmm2, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: reassociate_smin_v8i16: ; AVX-LABEL: reassociate_smin_v8i16:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpaddw %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpaddw %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpminsw %xmm3, %xmm2, %xmm1 ; AVX-NEXT: vpminsw %xmm3, %xmm2, %xmm2
; AVX-NEXT: vpminsw %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpminsw %xmm2, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%t0 = add <8 x i16> %x0, %x1 %t0 = add <8 x i16> %x0, %x1
%t1 = icmp slt <8 x i16> %x2, %t0 %t1 = icmp slt <8 x i16> %x2, %t0
%t2 = select <8 x i1> %t1, <8 x i16> %x2, <8 x i16> %t0 %t2 = select <8 x i1> %t1, <8 x i16> %x2, <8 x i16> %t0
%t3 = icmp slt <8 x i16> %x3, %t2 %t3 = icmp slt <8 x i16> %x3, %t2
%t4 = select <8 x i1> %t3, <8 x i16> %x3, <8 x i16> %t2 %t4 = select <8 x i1> %t3, <8 x i16> %x3, <8 x i16> %t2
ret <8 x i16> %t4 ret <8 x i16> %t4
Show All 13 Lines
; SSE-NEXT: pand %xmm0, %xmm3 ; SSE-NEXT: pand %xmm0, %xmm3
; SSE-NEXT: pandn %xmm1, %xmm0 ; SSE-NEXT: pandn %xmm1, %xmm0
; SSE-NEXT: por %xmm3, %xmm0 ; SSE-NEXT: por %xmm3, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: reassociate_smin_v4i32: ; AVX-LABEL: reassociate_smin_v4i32:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpminsd %xmm3, %xmm2, %xmm1 ; AVX-NEXT: vpminsd %xmm3, %xmm2, %xmm2
; AVX-NEXT: vpminsd %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpminsd %xmm2, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%t0 = add <4 x i32> %x0, %x1 %t0 = add <4 x i32> %x0, %x1
%t1 = icmp slt <4 x i32> %x2, %t0 %t1 = icmp slt <4 x i32> %x2, %t0
%t2 = select <4 x i1> %t1, <4 x i32> %x2, <4 x i32> %t0 %t2 = select <4 x i1> %t1, <4 x i32> %x2, <4 x i32> %t0
%t3 = icmp slt <4 x i32> %x3, %t2 %t3 = icmp slt <4 x i32> %x3, %t2
%t4 = select <4 x i1> %t3, <4 x i32> %x3, <4 x i32> %t2 %t4 = select <4 x i1> %t3, <4 x i32> %x3, <4 x i32> %t2
ret <4 x i32> %t4 ret <4 x i32> %t4
} }
define <2 x i64> @reassociate_smin_v2i64(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, <2 x i64> %x3) { define <2 x i64> @reassociate_smin_v2i64(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, <2 x i64> %x3) {
; SSE-LABEL: reassociate_smin_v2i64: ; SSE-LABEL: reassociate_smin_v2i64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: paddq %xmm1, %xmm0 ; SSE-NEXT: paddq %xmm1, %xmm0
; SSE-NEXT: movdqa {{.*#+}} xmm1 = [2147483648,2147483648] ; SSE-NEXT: movdqa {{.*#+}} xmm1 = [2147483648,2147483648]
; SSE-NEXT: movdqa %xmm2, %xmm4 ; SSE-NEXT: movdqa %xmm2, %xmm4
; SSE-NEXT: pxor %xmm1, %xmm4
; SSE-NEXT: movdqa %xmm0, %xmm5 ; SSE-NEXT: movdqa %xmm0, %xmm5
; SSE-NEXT: pxor %xmm1, %xmm5 ; SSE-NEXT: pxor %xmm1, %xmm5
; SSE-NEXT: pxor %xmm1, %xmm4
; SSE-NEXT: movdqa %xmm5, %xmm6 ; SSE-NEXT: movdqa %xmm5, %xmm6
; SSE-NEXT: pcmpgtd %xmm4, %xmm6
; SSE-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2]
; SSE-NEXT: pcmpeqd %xmm4, %xmm5 ; SSE-NEXT: pcmpeqd %xmm4, %xmm5
; SSE-NEXT: pcmpgtd %xmm4, %xmm6
; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm5[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm5[1,1,3,3]
; SSE-NEXT: pand %xmm7, %xmm4 ; SSE-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm6[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm6[1,1,3,3]
; SSE-NEXT: pand %xmm7, %xmm4
; SSE-NEXT: por %xmm4, %xmm5 ; SSE-NEXT: por %xmm4, %xmm5
; SSE-NEXT: pand %xmm5, %xmm2 ; SSE-NEXT: pand %xmm5, %xmm2
; SSE-NEXT: pandn %xmm0, %xmm5 ; SSE-NEXT: pandn %xmm0, %xmm5
; SSE-NEXT: por %xmm2, %xmm5 ; SSE-NEXT: por %xmm2, %xmm5
; SSE-NEXT: movdqa %xmm5, %xmm0 ; SSE-NEXT: movdqa %xmm5, %xmm0
; SSE-NEXT: pxor %xmm1, %xmm0 ; SSE-NEXT: pxor %xmm1, %xmm0
; SSE-NEXT: pxor %xmm3, %xmm1 ; SSE-NEXT: pxor %xmm3, %xmm1
; SSE-NEXT: movdqa %xmm0, %xmm2 ; SSE-NEXT: movdqa %xmm0, %xmm2
; SSE-NEXT: pcmpgtd %xmm1, %xmm2 ; SSE-NEXT: pcmpgtd %xmm1, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm2[0,0,2,2]
; SSE-NEXT: pcmpeqd %xmm0, %xmm1 ; SSE-NEXT: pcmpeqd %xmm0, %xmm1
; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm2[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; SSE-NEXT: pand %xmm4, %xmm1
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,3,3]
; SSE-NEXT: pand %xmm4, %xmm1
; SSE-NEXT: por %xmm1, %xmm0 ; SSE-NEXT: por %xmm1, %xmm0
; SSE-NEXT: pand %xmm0, %xmm3 ; SSE-NEXT: pand %xmm0, %xmm3
; SSE-NEXT: pandn %xmm5, %xmm0 ; SSE-NEXT: pandn %xmm5, %xmm0
; SSE-NEXT: por %xmm3, %xmm0 ; SSE-NEXT: por %xmm3, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX2-LABEL: reassociate_smin_v2i64: ; AVX2-LABEL: reassociate_smin_v2i64:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpaddq %xmm1, %xmm0, %xmm0 ; AVX2-NEXT: vpaddq %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpcmpgtq %xmm2, %xmm0, %xmm1 ; AVX2-NEXT: vpcmpgtq %xmm2, %xmm0, %xmm1
; AVX2-NEXT: vblendvpd %xmm1, %xmm2, %xmm0, %xmm0 ; AVX2-NEXT: vblendvpd %xmm1, %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpcmpgtq %xmm3, %xmm0, %xmm1 ; AVX2-NEXT: vpcmpgtq %xmm3, %xmm0, %xmm1
; AVX2-NEXT: vblendvpd %xmm1, %xmm3, %xmm0, %xmm0 ; AVX2-NEXT: vblendvpd %xmm1, %xmm3, %xmm0, %xmm0
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: reassociate_smin_v2i64: ; AVX512-LABEL: reassociate_smin_v2i64:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vpaddq %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vpaddq %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vpminsq %xmm3, %xmm2, %xmm1 ; AVX512-NEXT: vpminsq %xmm3, %xmm2, %xmm2
; AVX512-NEXT: vpminsq %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vpminsq %xmm2, %xmm0, %xmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%t0 = add <2 x i64> %x0, %x1 %t0 = add <2 x i64> %x0, %x1
%t1 = icmp slt <2 x i64> %x2, %t0 %t1 = icmp slt <2 x i64> %x2, %t0
%t2 = select <2 x i1> %t1, <2 x i64> %x2, <2 x i64> %t0 %t2 = select <2 x i1> %t1, <2 x i64> %x2, <2 x i64> %t0
%t3 = icmp slt <2 x i64> %x3, %t2 %t3 = icmp slt <2 x i64> %x3, %t2
%t4 = select <2 x i1> %t3, <2 x i64> %x3, <2 x i64> %t2 %t4 = select <2 x i1> %t3, <2 x i64> %x3, <2 x i64> %t2
ret <2 x i64> %t4 ret <2 x i64> %t4
} }
; Verify that 256-bit vector min/max are reassociated. ; Verify that 256-bit vector min/max are reassociated.
define <32 x i8> @reassociate_umax_v32i8(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, <32 x i8> %x3) { define <32 x i8> @reassociate_umax_v32i8(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, <32 x i8> %x3) {
; SSE-LABEL: reassociate_umax_v32i8: ; SSE-LABEL: reassociate_umax_v32i8:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: paddb %xmm2, %xmm0 ; SSE-NEXT: paddb %xmm2, %xmm0
; SSE-NEXT: paddb %xmm3, %xmm1
; SSE-NEXT: pmaxub %xmm6, %xmm4 ; SSE-NEXT: pmaxub %xmm6, %xmm4
; SSE-NEXT: pmaxub %xmm4, %xmm0 ; SSE-NEXT: paddb %xmm3, %xmm1
; SSE-NEXT: pmaxub %xmm7, %xmm5 ; SSE-NEXT: pmaxub %xmm7, %xmm5
; SSE-NEXT: pmaxub %xmm4, %xmm0
; SSE-NEXT: pmaxub %xmm5, %xmm1 ; SSE-NEXT: pmaxub %xmm5, %xmm1
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: reassociate_umax_v32i8: ; AVX-LABEL: reassociate_umax_v32i8:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpaddb %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vpaddb %ymm1, %ymm0, %ymm0
; AVX-NEXT: vpmaxub %ymm3, %ymm2, %ymm1 ; AVX-NEXT: vpmaxub %ymm3, %ymm2, %ymm2
; AVX-NEXT: vpmaxub %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vpmaxub %ymm2, %ymm0, %ymm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%t0 = add <32 x i8> %x0, %x1 %t0 = add <32 x i8> %x0, %x1
%t1 = icmp ugt <32 x i8> %x2, %t0 %t1 = icmp ugt <32 x i8> %x2, %t0
%t2 = select <32 x i1> %t1, <32 x i8> %x2, <32 x i8> %t0 %t2 = select <32 x i1> %t1, <32 x i8> %x2, <32 x i8> %t0
%t3 = icmp ugt <32 x i8> %x3, %t2 %t3 = icmp ugt <32 x i8> %x3, %t2
%t4 = select <32 x i1> %t3, <32 x i8> %x3, <32 x i8> %t2 %t4 = select <32 x i1> %t3, <32 x i8> %x3, <32 x i8> %t2
ret <32 x i8> %t4 ret <32 x i8> %t4
} }
define <16 x i16> @reassociate_umax_v16i16(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, <16 x i16> %x3) { define <16 x i16> @reassociate_umax_v16i16(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, <16 x i16> %x3) {
; SSE-LABEL: reassociate_umax_v16i16: ; SSE-LABEL: reassociate_umax_v16i16:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: paddw %xmm2, %xmm0
; SSE-NEXT: paddw %xmm3, %xmm1 ; SSE-NEXT: paddw %xmm3, %xmm1
; SSE-NEXT: movdqa {{.*#+}} xmm2 = [32768,32768,32768,32768,32768,32768,32768,32768] ; SSE-NEXT: movdqa {{.*#+}} xmm3 = [32768,32768,32768,32768,32768,32768,32768,32768]
; SSE-NEXT: pxor %xmm2, %xmm5 ; SSE-NEXT: paddw %xmm2, %xmm0
; SSE-NEXT: pxor %xmm2, %xmm1 ; SSE-NEXT: pxor %xmm3, %xmm5
; SSE-NEXT: pxor %xmm3, %xmm1
; SSE-NEXT: pxor %xmm3, %xmm4
; SSE-NEXT: pxor %xmm3, %xmm0
; SSE-NEXT: pxor %xmm3, %xmm6
; SSE-NEXT: pxor %xmm3, %xmm7
; SSE-NEXT: pmaxsw %xmm5, %xmm1 ; SSE-NEXT: pmaxsw %xmm5, %xmm1
; SSE-NEXT: pxor %xmm2, %xmm4
; SSE-NEXT: pxor %xmm2, %xmm0
; SSE-NEXT: pmaxsw %xmm4, %xmm0 ; SSE-NEXT: pmaxsw %xmm4, %xmm0
; SSE-NEXT: pxor %xmm2, %xmm6
; SSE-NEXT: pmaxsw %xmm6, %xmm0 ; SSE-NEXT: pmaxsw %xmm6, %xmm0
; SSE-NEXT: pxor %xmm2, %xmm0
; SSE-NEXT: pxor %xmm2, %xmm7
; SSE-NEXT: pmaxsw %xmm7, %xmm1 ; SSE-NEXT: pmaxsw %xmm7, %xmm1
; SSE-NEXT: pxor %xmm2, %xmm1 ; SSE-NEXT: pxor %xmm3, %xmm0
; SSE-NEXT: pxor %xmm3, %xmm1
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: reassociate_umax_v16i16: ; AVX-LABEL: reassociate_umax_v16i16:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpaddw %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vpaddw %ymm1, %ymm0, %ymm0
; AVX-NEXT: vpmaxuw %ymm3, %ymm2, %ymm1 ; AVX-NEXT: vpmaxuw %ymm3, %ymm2, %ymm2
; AVX-NEXT: vpmaxuw %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vpmaxuw %ymm2, %ymm0, %ymm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%t0 = add <16 x i16> %x0, %x1 %t0 = add <16 x i16> %x0, %x1
%t1 = icmp ugt <16 x i16> %x2, %t0 %t1 = icmp ugt <16 x i16> %x2, %t0
%t2 = select <16 x i1> %t1, <16 x i16> %x2, <16 x i16> %t0 %t2 = select <16 x i1> %t1, <16 x i16> %x2, <16 x i16> %t0
%t3 = icmp ugt <16 x i16> %x3, %t2 %t3 = icmp ugt <16 x i16> %x3, %t2
%t4 = select <16 x i1> %t3, <16 x i16> %x3, <16 x i16> %t2 %t4 = select <16 x i1> %t3, <16 x i16> %x3, <16 x i16> %t2
ret <16 x i16> %t4 ret <16 x i16> %t4
} }
define <8 x i32> @reassociate_umax_v8i32(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, <8 x i32> %x3) { define <8 x i32> @reassociate_umax_v8i32(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, <8 x i32> %x3) {
; SSE-LABEL: reassociate_umax_v8i32: ; SSE-LABEL: reassociate_umax_v8i32:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movdqa %xmm1, %xmm8 ; SSE-NEXT: movdqa %xmm1, %xmm8
; SSE-NEXT: paddd %xmm2, %xmm0
; SSE-NEXT: paddd %xmm3, %xmm8
; SSE-NEXT: movdqa {{.*#+}} xmm1 = [2147483648,2147483648,2147483648,2147483648] ; SSE-NEXT: movdqa {{.*#+}} xmm1 = [2147483648,2147483648,2147483648,2147483648]
; SSE-NEXT: paddd %xmm2, %xmm0
; SSE-NEXT: movdqa %xmm5, %xmm2 ; SSE-NEXT: movdqa %xmm5, %xmm2
; SSE-NEXT: pxor %xmm1, %xmm2 ; SSE-NEXT: paddd %xmm3, %xmm8
; SSE-NEXT: movdqa %xmm8, %xmm3 ; SSE-NEXT: movdqa %xmm8, %xmm3
; SSE-NEXT: pxor %xmm1, %xmm2
; SSE-NEXT: pxor %xmm1, %xmm3 ; SSE-NEXT: pxor %xmm1, %xmm3
; SSE-NEXT: pcmpgtd %xmm3, %xmm2 ; SSE-NEXT: pcmpgtd %xmm3, %xmm2
; SSE-NEXT: movdqa %xmm4, %xmm3
; SSE-NEXT: pand %xmm2, %xmm5 ; SSE-NEXT: pand %xmm2, %xmm5
; SSE-NEXT: pandn %xmm8, %xmm2 ; SSE-NEXT: pandn %xmm8, %xmm2
; SSE-NEXT: por %xmm5, %xmm2 ; SSE-NEXT: movdqa %xmm0, %xmm8
; SSE-NEXT: movdqa %xmm4, %xmm3
; SSE-NEXT: pxor %xmm1, %xmm3 ; SSE-NEXT: pxor %xmm1, %xmm3
; SSE-NEXT: movdqa %xmm0, %xmm5 ; SSE-NEXT: pxor %xmm1, %xmm8
; SSE-NEXT: pxor %xmm1, %xmm5 ; SSE-NEXT: por %xmm5, %xmm2
; SSE-NEXT: pcmpgtd %xmm5, %xmm3 ; SSE-NEXT: pcmpgtd %xmm8, %xmm3
; SSE-NEXT: pand %xmm3, %xmm4 ; SSE-NEXT: pand %xmm3, %xmm4
; SSE-NEXT: pandn %xmm0, %xmm3 ; SSE-NEXT: pandn %xmm0, %xmm3
; SSE-NEXT: movdqa %xmm6, %xmm0
; SSE-NEXT: por %xmm4, %xmm3 ; SSE-NEXT: por %xmm4, %xmm3
; SSE-NEXT: pxor %xmm1, %xmm0
; SSE-NEXT: movdqa %xmm3, %xmm4 ; SSE-NEXT: movdqa %xmm3, %xmm4
; SSE-NEXT: pxor %xmm1, %xmm4 ; SSE-NEXT: pxor %xmm1, %xmm4
; SSE-NEXT: movdqa %xmm6, %xmm0
; SSE-NEXT: pxor %xmm1, %xmm0
; SSE-NEXT: pcmpgtd %xmm4, %xmm0 ; SSE-NEXT: pcmpgtd %xmm4, %xmm0
; SSE-NEXT: movdqa %xmm2, %xmm4
; SSE-NEXT: pxor %xmm1, %xmm4
; SSE-NEXT: pxor %xmm7, %xmm1
; SSE-NEXT: pand %xmm0, %xmm6 ; SSE-NEXT: pand %xmm0, %xmm6
; SSE-NEXT: pandn %xmm3, %xmm0 ; SSE-NEXT: pandn %xmm3, %xmm0
; SSE-NEXT: pcmpgtd %xmm4, %xmm1
; SSE-NEXT: por %xmm6, %xmm0 ; SSE-NEXT: por %xmm6, %xmm0
; SSE-NEXT: movdqa %xmm2, %xmm3
; SSE-NEXT: pxor %xmm1, %xmm3
; SSE-NEXT: pxor %xmm7, %xmm1
; SSE-NEXT: pcmpgtd %xmm3, %xmm1
; SSE-NEXT: pand %xmm1, %xmm7 ; SSE-NEXT: pand %xmm1, %xmm7
; SSE-NEXT: pandn %xmm2, %xmm1 ; SSE-NEXT: pandn %xmm2, %xmm1
; SSE-NEXT: por %xmm7, %xmm1 ; SSE-NEXT: por %xmm7, %xmm1
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: reassociate_umax_v8i32: ; AVX-LABEL: reassociate_umax_v8i32:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpaddd %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vpaddd %ymm1, %ymm0, %ymm0
; AVX-NEXT: vpmaxud %ymm3, %ymm2, %ymm1 ; AVX-NEXT: vpmaxud %ymm3, %ymm2, %ymm2
; AVX-NEXT: vpmaxud %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vpmaxud %ymm2, %ymm0, %ymm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%t0 = add <8 x i32> %x0, %x1 %t0 = add <8 x i32> %x0, %x1
%t1 = icmp ugt <8 x i32> %x2, %t0 %t1 = icmp ugt <8 x i32> %x2, %t0
%t2 = select <8 x i1> %t1, <8 x i32> %x2, <8 x i32> %t0 %t2 = select <8 x i1> %t1, <8 x i32> %x2, <8 x i32> %t0
%t3 = icmp ugt <8 x i32> %x3, %t2 %t3 = icmp ugt <8 x i32> %x3, %t2
%t4 = select <8 x i1> %t3, <8 x i32> %x3, <8 x i32> %t2 %t4 = select <8 x i1> %t3, <8 x i32> %x3, <8 x i32> %t2
ret <8 x i32> %t4 ret <8 x i32> %t4
} }
define <4 x i64> @reassociate_umax_v4i64(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, <4 x i64> %x3) { define <4 x i64> @reassociate_umax_v4i64(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, <4 x i64> %x3) {
; SSE-LABEL: reassociate_umax_v4i64: ; SSE-LABEL: reassociate_umax_v4i64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: paddq %xmm2, %xmm0
; SSE-NEXT: paddq %xmm3, %xmm1
; SSE-NEXT: movdqa {{.*#+}} xmm8 = [9223372039002259456,9223372039002259456] ; SSE-NEXT: movdqa {{.*#+}} xmm8 = [9223372039002259456,9223372039002259456]
; SSE-NEXT: paddq %xmm3, %xmm1
; SSE-NEXT: movdqa %xmm5, %xmm3 ; SSE-NEXT: movdqa %xmm5, %xmm3
; SSE-NEXT: pxor %xmm8, %xmm3 ; SSE-NEXT: paddq %xmm2, %xmm0
; SSE-NEXT: movdqa %xmm1, %xmm2 ; SSE-NEXT: movdqa %xmm1, %xmm2
; SSE-NEXT: pxor %xmm8, %xmm3
; SSE-NEXT: pxor %xmm8, %xmm2 ; SSE-NEXT: pxor %xmm8, %xmm2
; SSE-NEXT: movdqa %xmm3, %xmm9 ; SSE-NEXT: movdqa %xmm3, %xmm9
; SSE-NEXT: pcmpgtd %xmm2, %xmm9 ; SSE-NEXT: pcmpgtd %xmm2, %xmm9
; SSE-NEXT: pshufd {{.*#+}} xmm10 = xmm9[0,0,2,2]
; SSE-NEXT: pcmpeqd %xmm3, %xmm2 ; SSE-NEXT: pcmpeqd %xmm3, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm10 = xmm9[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; SSE-NEXT: pand %xmm10, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm9[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm9[1,1,3,3]
; SSE-NEXT: pand %xmm10, %xmm2
; SSE-NEXT: por %xmm2, %xmm3 ; SSE-NEXT: por %xmm2, %xmm3
; SSE-NEXT: movdqa %xmm0, %xmm2
; SSE-NEXT: pand %xmm3, %xmm5 ; SSE-NEXT: pand %xmm3, %xmm5
; SSE-NEXT: pandn %xmm1, %xmm3 ; SSE-NEXT: pandn %xmm1, %xmm3
; SSE-NEXT: por %xmm5, %xmm3
; SSE-NEXT: movdqa %xmm4, %xmm1 ; SSE-NEXT: movdqa %xmm4, %xmm1
; SSE-NEXT: pxor %xmm8, %xmm1
; SSE-NEXT: movdqa %xmm0, %xmm2
; SSE-NEXT: pxor %xmm8, %xmm2 ; SSE-NEXT: pxor %xmm8, %xmm2
; SSE-NEXT: pxor %xmm8, %xmm1
; SSE-NEXT: por %xmm5, %xmm3
; SSE-NEXT: movdqa %xmm1, %xmm5 ; SSE-NEXT: movdqa %xmm1, %xmm5
; SSE-NEXT: pcmpgtd %xmm2, %xmm5 ; SSE-NEXT: pcmpgtd %xmm2, %xmm5
; SSE-NEXT: pshufd {{.*#+}} xmm9 = xmm5[0,0,2,2]
; SSE-NEXT: pcmpeqd %xmm1, %xmm2 ; SSE-NEXT: pcmpeqd %xmm1, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3]
; SSE-NEXT: pand %xmm9, %xmm1 ; SSE-NEXT: pshufd {{.*#+}} xmm9 = xmm5[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm5[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm5[1,1,3,3]
; SSE-NEXT: pand %xmm9, %xmm1
; SSE-NEXT: por %xmm1, %xmm2 ; SSE-NEXT: por %xmm1, %xmm2
; SSE-NEXT: movdqa %xmm6, %xmm1
; SSE-NEXT: pand %xmm2, %xmm4 ; SSE-NEXT: pand %xmm2, %xmm4
; SSE-NEXT: pandn %xmm0, %xmm2 ; SSE-NEXT: pandn %xmm0, %xmm2
; SSE-NEXT: pxor %xmm8, %xmm1
; SSE-NEXT: por %xmm4, %xmm2 ; SSE-NEXT: por %xmm4, %xmm2
; SSE-NEXT: movdqa %xmm1, %xmm4
; SSE-NEXT: movdqa %xmm2, %xmm0 ; SSE-NEXT: movdqa %xmm2, %xmm0
; SSE-NEXT: pxor %xmm8, %xmm0 ; SSE-NEXT: pxor %xmm8, %xmm0
; SSE-NEXT: movdqa %xmm6, %xmm1 ; SSE-NEXT: pcmpeqd %xmm0, %xmm1
; SSE-NEXT: pxor %xmm8, %xmm1
; SSE-NEXT: movdqa %xmm1, %xmm4
; SSE-NEXT: pcmpgtd %xmm0, %xmm4 ; SSE-NEXT: pcmpgtd %xmm0, %xmm4
; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2] ; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
; SSE-NEXT: pcmpeqd %xmm0, %xmm1
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; SSE-NEXT: pand %xmm5, %xmm1
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm4[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm4[1,1,3,3]
; SSE-NEXT: pand %xmm5, %xmm1
; SSE-NEXT: por %xmm1, %xmm0 ; SSE-NEXT: por %xmm1, %xmm0
; SSE-NEXT: pand %xmm0, %xmm6
; SSE-NEXT: pandn %xmm2, %xmm0
; SSE-NEXT: por %xmm6, %xmm0
; SSE-NEXT: movdqa %xmm3, %xmm1 ; SSE-NEXT: movdqa %xmm3, %xmm1
; SSE-NEXT: pxor %xmm8, %xmm1 ; SSE-NEXT: pxor %xmm8, %xmm1
; SSE-NEXT: pxor %xmm7, %xmm8 ; SSE-NEXT: pxor %xmm7, %xmm8
; SSE-NEXT: pand %xmm0, %xmm6
; SSE-NEXT: pandn %xmm2, %xmm0
; SSE-NEXT: movdqa %xmm8, %xmm2 ; SSE-NEXT: movdqa %xmm8, %xmm2
; SSE-NEXT: pcmpgtd %xmm1, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm2[0,0,2,2]
; SSE-NEXT: pcmpeqd %xmm1, %xmm8 ; SSE-NEXT: pcmpeqd %xmm1, %xmm8
; SSE-NEXT: por %xmm6, %xmm0
; SSE-NEXT: pcmpgtd %xmm1, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm8[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm8[1,1,3,3]
; SSE-NEXT: pand %xmm4, %xmm5 ; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm2[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3]
; SSE-NEXT: pand %xmm4, %xmm5
; SSE-NEXT: por %xmm5, %xmm1 ; SSE-NEXT: por %xmm5, %xmm1
; SSE-NEXT: pand %xmm1, %xmm7 ; SSE-NEXT: pand %xmm1, %xmm7
; SSE-NEXT: pandn %xmm3, %xmm1 ; SSE-NEXT: pandn %xmm3, %xmm1
; SSE-NEXT: por %xmm7, %xmm1 ; SSE-NEXT: por %xmm7, %xmm1
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX2-LABEL: reassociate_umax_v4i64: ; AVX2-LABEL: reassociate_umax_v4i64:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpaddq %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpaddq %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808] ; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808]
; AVX2-NEXT: vpxor %ymm1, %ymm2, %ymm4 ; AVX2-NEXT: vpxor %ymm1, %ymm2, %ymm4
; AVX2-NEXT: vpxor %ymm1, %ymm0, %ymm5 ; AVX2-NEXT: vpxor %ymm1, %ymm0, %ymm5
; AVX2-NEXT: vpcmpgtq %ymm5, %ymm4, %ymm4 ; AVX2-NEXT: vpcmpgtq %ymm5, %ymm4, %ymm4
; AVX2-NEXT: vblendvpd %ymm4, %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vblendvpd %ymm4, %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vxorpd %ymm1, %ymm0, %ymm2 ; AVX2-NEXT: vxorpd %ymm1, %ymm0, %ymm2
; AVX2-NEXT: vpxor %ymm1, %ymm3, %ymm1 ; AVX2-NEXT: vpxor %ymm1, %ymm3, %ymm1
; AVX2-NEXT: vpcmpgtq %ymm2, %ymm1, %ymm1 ; AVX2-NEXT: vpcmpgtq %ymm2, %ymm1, %ymm1
; AVX2-NEXT: vblendvpd %ymm1, %ymm3, %ymm0, %ymm0 ; AVX2-NEXT: vblendvpd %ymm1, %ymm3, %ymm0, %ymm0
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: reassociate_umax_v4i64: ; AVX512-LABEL: reassociate_umax_v4i64:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vpaddq %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: vpaddq %ymm1, %ymm0, %ymm0
; AVX512-NEXT: vpmaxuq %ymm3, %ymm2, %ymm1 ; AVX512-NEXT: vpmaxuq %ymm3, %ymm2, %ymm2
; AVX512-NEXT: vpmaxuq %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: vpmaxuq %ymm2, %ymm0, %ymm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%t0 = add <4 x i64> %x0, %x1 %t0 = add <4 x i64> %x0, %x1
%t1 = icmp ugt <4 x i64> %x2, %t0 %t1 = icmp ugt <4 x i64> %x2, %t0
%t2 = select <4 x i1> %t1, <4 x i64> %x2, <4 x i64> %t0 %t2 = select <4 x i1> %t1, <4 x i64> %x2, <4 x i64> %t0
%t3 = icmp ugt <4 x i64> %x3, %t2 %t3 = icmp ugt <4 x i64> %x3, %t2
%t4 = select <4 x i1> %t3, <4 x i64> %x3, <4 x i64> %t2 %t4 = select <4 x i1> %t3, <4 x i64> %x3, <4 x i64> %t2
ret <4 x i64> %t4 ret <4 x i64> %t4
} }
define <32 x i8> @reassociate_smax_v32i8(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, <32 x i8> %x3) { define <32 x i8> @reassociate_smax_v32i8(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, <32 x i8> %x3) {
; SSE-LABEL: reassociate_smax_v32i8: ; SSE-LABEL: reassociate_smax_v32i8:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: paddb %xmm2, %xmm0
; SSE-NEXT: paddb %xmm3, %xmm1 ; SSE-NEXT: paddb %xmm3, %xmm1
; SSE-NEXT: movdqa %xmm5, %xmm2 ; SSE-NEXT: movdqa %xmm5, %xmm3
; SSE-NEXT: pcmpgtb %xmm1, %xmm2 ; SSE-NEXT: paddb %xmm2, %xmm0
; SSE-NEXT: pand %xmm2, %xmm5 ; SSE-NEXT: pcmpgtb %xmm1, %xmm3
; SSE-NEXT: pandn %xmm1, %xmm2 ; SSE-NEXT: pand %xmm3, %xmm5
; SSE-NEXT: por %xmm5, %xmm2 ; SSE-NEXT: pandn %xmm1, %xmm3
; SSE-NEXT: movdqa %xmm4, %xmm1 ; SSE-NEXT: movdqa %xmm4, %xmm1
; SSE-NEXT: pcmpgtb %xmm0, %xmm1 ; SSE-NEXT: pcmpgtb %xmm0, %xmm1
; SSE-NEXT: por %xmm5, %xmm3
; SSE-NEXT: pand %xmm1, %xmm4 ; SSE-NEXT: pand %xmm1, %xmm4
; SSE-NEXT: pandn %xmm0, %xmm1 ; SSE-NEXT: pandn %xmm0, %xmm1
; SSE-NEXT: por %xmm4, %xmm1
; SSE-NEXT: movdqa %xmm6, %xmm0 ; SSE-NEXT: movdqa %xmm6, %xmm0
; SSE-NEXT: por %xmm4, %xmm1
; SSE-NEXT: pcmpgtb %xmm1, %xmm0 ; SSE-NEXT: pcmpgtb %xmm1, %xmm0
; SSE-NEXT: pand %xmm0, %xmm6 ; SSE-NEXT: pand %xmm0, %xmm6
; SSE-NEXT: pandn %xmm1, %xmm0 ; SSE-NEXT: pandn %xmm1, %xmm0
; SSE-NEXT: por %xmm6, %xmm0
; SSE-NEXT: movdqa %xmm7, %xmm1 ; SSE-NEXT: movdqa %xmm7, %xmm1
; SSE-NEXT: pcmpgtb %xmm2, %xmm1 ; SSE-NEXT: pcmpgtb %xmm3, %xmm1
; SSE-NEXT: por %xmm6, %xmm0
; SSE-NEXT: pand %xmm1, %xmm7 ; SSE-NEXT: pand %xmm1, %xmm7
; SSE-NEXT: pandn %xmm2, %xmm1 ; SSE-NEXT: pandn %xmm3, %xmm1
; SSE-NEXT: por %xmm7, %xmm1 ; SSE-NEXT: por %xmm7, %xmm1
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: reassociate_smax_v32i8: ; AVX-LABEL: reassociate_smax_v32i8:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpaddb %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vpaddb %ymm1, %ymm0, %ymm0
; AVX-NEXT: vpmaxsb %ymm3, %ymm2, %ymm1 ; AVX-NEXT: vpmaxsb %ymm3, %ymm2, %ymm2
; AVX-NEXT: vpmaxsb %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vpmaxsb %ymm2, %ymm0, %ymm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%t0 = add <32 x i8> %x0, %x1 %t0 = add <32 x i8> %x0, %x1
%t1 = icmp sgt <32 x i8> %x2, %t0 %t1 = icmp sgt <32 x i8> %x2, %t0
%t2 = select <32 x i1> %t1, <32 x i8> %x2, <32 x i8> %t0 %t2 = select <32 x i1> %t1, <32 x i8> %x2, <32 x i8> %t0
%t3 = icmp sgt <32 x i8> %x3, %t2 %t3 = icmp sgt <32 x i8> %x3, %t2
%t4 = select <32 x i1> %t3, <32 x i8> %x3, <32 x i8> %t2 %t4 = select <32 x i1> %t3, <32 x i8> %x3, <32 x i8> %t2
ret <32 x i8> %t4 ret <32 x i8> %t4
} }
define <16 x i16> @reassociate_smax_v16i16(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, <16 x i16> %x3) { define <16 x i16> @reassociate_smax_v16i16(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, <16 x i16> %x3) {
; SSE-LABEL: reassociate_smax_v16i16: ; SSE-LABEL: reassociate_smax_v16i16:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: paddw %xmm2, %xmm0 ; SSE-NEXT: paddw %xmm2, %xmm0
; SSE-NEXT: paddw %xmm3, %xmm1
; SSE-NEXT: pmaxsw %xmm6, %xmm4 ; SSE-NEXT: pmaxsw %xmm6, %xmm4
; SSE-NEXT: pmaxsw %xmm4, %xmm0 ; SSE-NEXT: paddw %xmm3, %xmm1
; SSE-NEXT: pmaxsw %xmm7, %xmm5 ; SSE-NEXT: pmaxsw %xmm7, %xmm5
; SSE-NEXT: pmaxsw %xmm4, %xmm0
; SSE-NEXT: pmaxsw %xmm5, %xmm1 ; SSE-NEXT: pmaxsw %xmm5, %xmm1
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: reassociate_smax_v16i16: ; AVX-LABEL: reassociate_smax_v16i16:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpaddw %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vpaddw %ymm1, %ymm0, %ymm0
; AVX-NEXT: vpmaxsw %ymm3, %ymm2, %ymm1 ; AVX-NEXT: vpmaxsw %ymm3, %ymm2, %ymm2
; AVX-NEXT: vpmaxsw %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vpmaxsw %ymm2, %ymm0, %ymm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%t0 = add <16 x i16> %x0, %x1 %t0 = add <16 x i16> %x0, %x1
%t1 = icmp sgt <16 x i16> %x2, %t0 %t1 = icmp sgt <16 x i16> %x2, %t0
%t2 = select <16 x i1> %t1, <16 x i16> %x2, <16 x i16> %t0 %t2 = select <16 x i1> %t1, <16 x i16> %x2, <16 x i16> %t0
%t3 = icmp sgt <16 x i16> %x3, %t2 %t3 = icmp sgt <16 x i16> %x3, %t2
%t4 = select <16 x i1> %t3, <16 x i16> %x3, <16 x i16> %t2 %t4 = select <16 x i1> %t3, <16 x i16> %x3, <16 x i16> %t2
ret <16 x i16> %t4 ret <16 x i16> %t4
} }
define <8 x i32> @reassociate_smax_v8i32(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, <8 x i32> %x3) { define <8 x i32> @reassociate_smax_v8i32(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, <8 x i32> %x3) {
; SSE-LABEL: reassociate_smax_v8i32: ; SSE-LABEL: reassociate_smax_v8i32:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: paddd %xmm2, %xmm0
; SSE-NEXT: paddd %xmm3, %xmm1 ; SSE-NEXT: paddd %xmm3, %xmm1
; SSE-NEXT: movdqa %xmm5, %xmm2 ; SSE-NEXT: movdqa %xmm5, %xmm3
; SSE-NEXT: pcmpgtd %xmm1, %xmm2 ; SSE-NEXT: paddd %xmm2, %xmm0
; SSE-NEXT: pand %xmm2, %xmm5 ; SSE-NEXT: pcmpgtd %xmm1, %xmm3
; SSE-NEXT: pandn %xmm1, %xmm2 ; SSE-NEXT: pand %xmm3, %xmm5
; SSE-NEXT: por %xmm5, %xmm2 ; SSE-NEXT: pandn %xmm1, %xmm3
; SSE-NEXT: movdqa %xmm4, %xmm1 ; SSE-NEXT: movdqa %xmm4, %xmm1
; SSE-NEXT: pcmpgtd %xmm0, %xmm1 ; SSE-NEXT: pcmpgtd %xmm0, %xmm1
; SSE-NEXT: por %xmm5, %xmm3
; SSE-NEXT: pand %xmm1, %xmm4 ; SSE-NEXT: pand %xmm1, %xmm4
; SSE-NEXT: pandn %xmm0, %xmm1 ; SSE-NEXT: pandn %xmm0, %xmm1
; SSE-NEXT: por %xmm4, %xmm1
; SSE-NEXT: movdqa %xmm6, %xmm0 ; SSE-NEXT: movdqa %xmm6, %xmm0
; SSE-NEXT: por %xmm4, %xmm1
; SSE-NEXT: pcmpgtd %xmm1, %xmm0 ; SSE-NEXT: pcmpgtd %xmm1, %xmm0
; SSE-NEXT: pand %xmm0, %xmm6 ; SSE-NEXT: pand %xmm0, %xmm6
; SSE-NEXT: pandn %xmm1, %xmm0 ; SSE-NEXT: pandn %xmm1, %xmm0
; SSE-NEXT: por %xmm6, %xmm0
; SSE-NEXT: movdqa %xmm7, %xmm1 ; SSE-NEXT: movdqa %xmm7, %xmm1
; SSE-NEXT: pcmpgtd %xmm2, %xmm1 ; SSE-NEXT: pcmpgtd %xmm3, %xmm1
; SSE-NEXT: por %xmm6, %xmm0
; SSE-NEXT: pand %xmm1, %xmm7 ; SSE-NEXT: pand %xmm1, %xmm7
; SSE-NEXT: pandn %xmm2, %xmm1 ; SSE-NEXT: pandn %xmm3, %xmm1
; SSE-NEXT: por %xmm7, %xmm1 ; SSE-NEXT: por %xmm7, %xmm1
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: reassociate_smax_v8i32: ; AVX-LABEL: reassociate_smax_v8i32:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpaddd %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vpaddd %ymm1, %ymm0, %ymm0
; AVX-NEXT: vpmaxsd %ymm3, %ymm2, %ymm1 ; AVX-NEXT: vpmaxsd %ymm3, %ymm2, %ymm2
; AVX-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vpmaxsd %ymm2, %ymm0, %ymm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%t0 = add <8 x i32> %x0, %x1 %t0 = add <8 x i32> %x0, %x1
%t1 = icmp sgt <8 x i32> %x2, %t0 %t1 = icmp sgt <8 x i32> %x2, %t0
%t2 = select <8 x i1> %t1, <8 x i32> %x2, <8 x i32> %t0 %t2 = select <8 x i1> %t1, <8 x i32> %x2, <8 x i32> %t0
%t3 = icmp sgt <8 x i32> %x3, %t2 %t3 = icmp sgt <8 x i32> %x3, %t2
%t4 = select <8 x i1> %t3, <8 x i32> %x3, <8 x i32> %t2 %t4 = select <8 x i1> %t3, <8 x i32> %x3, <8 x i32> %t2
ret <8 x i32> %t4 ret <8 x i32> %t4
} }
define <4 x i64> @reassociate_smax_v4i64(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, <4 x i64> %x3) { define <4 x i64> @reassociate_smax_v4i64(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, <4 x i64> %x3) {
; SSE-LABEL: reassociate_smax_v4i64: ; SSE-LABEL: reassociate_smax_v4i64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: paddq %xmm2, %xmm0
; SSE-NEXT: paddq %xmm3, %xmm1
; SSE-NEXT: movdqa {{.*#+}} xmm8 = [2147483648,2147483648] ; SSE-NEXT: movdqa {{.*#+}} xmm8 = [2147483648,2147483648]
; SSE-NEXT: paddq %xmm3, %xmm1
; SSE-NEXT: movdqa %xmm5, %xmm3 ; SSE-NEXT: movdqa %xmm5, %xmm3
; SSE-NEXT: pxor %xmm8, %xmm3 ; SSE-NEXT: paddq %xmm2, %xmm0
; SSE-NEXT: movdqa %xmm1, %xmm2 ; SSE-NEXT: movdqa %xmm1, %xmm2
; SSE-NEXT: pxor %xmm8, %xmm3
; SSE-NEXT: pxor %xmm8, %xmm2 ; SSE-NEXT: pxor %xmm8, %xmm2
; SSE-NEXT: movdqa %xmm3, %xmm9 ; SSE-NEXT: movdqa %xmm3, %xmm9
; SSE-NEXT: pcmpgtd %xmm2, %xmm9 ; SSE-NEXT: pcmpgtd %xmm2, %xmm9
; SSE-NEXT: pshufd {{.*#+}} xmm10 = xmm9[0,0,2,2]
; SSE-NEXT: pcmpeqd %xmm3, %xmm2 ; SSE-NEXT: pcmpeqd %xmm3, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm10 = xmm9[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; SSE-NEXT: pand %xmm10, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm9[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm9[1,1,3,3]
; SSE-NEXT: pand %xmm10, %xmm2
; SSE-NEXT: por %xmm2, %xmm3 ; SSE-NEXT: por %xmm2, %xmm3
; SSE-NEXT: movdqa %xmm0, %xmm2
; SSE-NEXT: pand %xmm3, %xmm5 ; SSE-NEXT: pand %xmm3, %xmm5
; SSE-NEXT: pandn %xmm1, %xmm3 ; SSE-NEXT: pandn %xmm1, %xmm3
; SSE-NEXT: por %xmm5, %xmm3
; SSE-NEXT: movdqa %xmm4, %xmm1 ; SSE-NEXT: movdqa %xmm4, %xmm1
; SSE-NEXT: pxor %xmm8, %xmm1
; SSE-NEXT: movdqa %xmm0, %xmm2
; SSE-NEXT: pxor %xmm8, %xmm2 ; SSE-NEXT: pxor %xmm8, %xmm2
; SSE-NEXT: pxor %xmm8, %xmm1
; SSE-NEXT: por %xmm5, %xmm3
; SSE-NEXT: movdqa %xmm1, %xmm5 ; SSE-NEXT: movdqa %xmm1, %xmm5
; SSE-NEXT: pcmpgtd %xmm2, %xmm5 ; SSE-NEXT: pcmpgtd %xmm2, %xmm5
; SSE-NEXT: pshufd {{.*#+}} xmm9 = xmm5[0,0,2,2]
; SSE-NEXT: pcmpeqd %xmm1, %xmm2 ; SSE-NEXT: pcmpeqd %xmm1, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3]
; SSE-NEXT: pand %xmm9, %xmm1 ; SSE-NEXT: pshufd {{.*#+}} xmm9 = xmm5[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm5[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm5[1,1,3,3]
; SSE-NEXT: pand %xmm9, %xmm1
; SSE-NEXT: por %xmm1, %xmm2 ; SSE-NEXT: por %xmm1, %xmm2
; SSE-NEXT: movdqa %xmm6, %xmm1
; SSE-NEXT: pand %xmm2, %xmm4 ; SSE-NEXT: pand %xmm2, %xmm4
; SSE-NEXT: pandn %xmm0, %xmm2 ; SSE-NEXT: pandn %xmm0, %xmm2
; SSE-NEXT: pxor %xmm8, %xmm1
; SSE-NEXT: por %xmm4, %xmm2 ; SSE-NEXT: por %xmm4, %xmm2
; SSE-NEXT: movdqa %xmm1, %xmm4
; SSE-NEXT: movdqa %xmm2, %xmm0 ; SSE-NEXT: movdqa %xmm2, %xmm0
; SSE-NEXT: pxor %xmm8, %xmm0 ; SSE-NEXT: pxor %xmm8, %xmm0
; SSE-NEXT: movdqa %xmm6, %xmm1 ; SSE-NEXT: pcmpeqd %xmm0, %xmm1
; SSE-NEXT: pxor %xmm8, %xmm1
; SSE-NEXT: movdqa %xmm1, %xmm4
; SSE-NEXT: pcmpgtd %xmm0, %xmm4 ; SSE-NEXT: pcmpgtd %xmm0, %xmm4
; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2] ; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
; SSE-NEXT: pcmpeqd %xmm0, %xmm1
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; SSE-NEXT: pand %xmm5, %xmm1
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm4[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm4[1,1,3,3]
; SSE-NEXT: pand %xmm5, %xmm1
; SSE-NEXT: por %xmm1, %xmm0 ; SSE-NEXT: por %xmm1, %xmm0
; SSE-NEXT: pand %xmm0, %xmm6
; SSE-NEXT: pandn %xmm2, %xmm0
; SSE-NEXT: por %xmm6, %xmm0
; SSE-NEXT: movdqa %xmm3, %xmm1 ; SSE-NEXT: movdqa %xmm3, %xmm1
; SSE-NEXT: pxor %xmm8, %xmm1 ; SSE-NEXT: pxor %xmm8, %xmm1
; SSE-NEXT: pxor %xmm7, %xmm8 ; SSE-NEXT: pxor %xmm7, %xmm8
; SSE-NEXT: pand %xmm0, %xmm6
; SSE-NEXT: pandn %xmm2, %xmm0
; SSE-NEXT: movdqa %xmm8, %xmm2 ; SSE-NEXT: movdqa %xmm8, %xmm2
; SSE-NEXT: pcmpgtd %xmm1, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm2[0,0,2,2]
; SSE-NEXT: pcmpeqd %xmm1, %xmm8 ; SSE-NEXT: pcmpeqd %xmm1, %xmm8
; SSE-NEXT: por %xmm6, %xmm0
; SSE-NEXT: pcmpgtd %xmm1, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm8[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm8[1,1,3,3]
; SSE-NEXT: pand %xmm4, %xmm5 ; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm2[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3]
; SSE-NEXT: pand %xmm4, %xmm5
; SSE-NEXT: por %xmm5, %xmm1 ; SSE-NEXT: por %xmm5, %xmm1
; SSE-NEXT: pand %xmm1, %xmm7 ; SSE-NEXT: pand %xmm1, %xmm7
; SSE-NEXT: pandn %xmm3, %xmm1 ; SSE-NEXT: pandn %xmm3, %xmm1
; SSE-NEXT: por %xmm7, %xmm1 ; SSE-NEXT: por %xmm7, %xmm1
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX2-LABEL: reassociate_smax_v4i64: ; AVX2-LABEL: reassociate_smax_v4i64:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpaddq %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpaddq %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpcmpgtq %ymm0, %ymm2, %ymm1 ; AVX2-NEXT: vpcmpgtq %ymm0, %ymm2, %ymm1
; AVX2-NEXT: vblendvpd %ymm1, %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vblendvpd %ymm1, %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpcmpgtq %ymm0, %ymm3, %ymm1 ; AVX2-NEXT: vpcmpgtq %ymm0, %ymm3, %ymm1
; AVX2-NEXT: vblendvpd %ymm1, %ymm3, %ymm0, %ymm0 ; AVX2-NEXT: vblendvpd %ymm1, %ymm3, %ymm0, %ymm0
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: reassociate_smax_v4i64: ; AVX512-LABEL: reassociate_smax_v4i64:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vpaddq %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: vpaddq %ymm1, %ymm0, %ymm0
; AVX512-NEXT: vpmaxsq %ymm3, %ymm2, %ymm1 ; AVX512-NEXT: vpmaxsq %ymm3, %ymm2, %ymm2
; AVX512-NEXT: vpmaxsq %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: vpmaxsq %ymm2, %ymm0, %ymm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%t0 = add <4 x i64> %x0, %x1 %t0 = add <4 x i64> %x0, %x1
%t1 = icmp sgt <4 x i64> %x2, %t0 %t1 = icmp sgt <4 x i64> %x2, %t0
%t2 = select <4 x i1> %t1, <4 x i64> %x2, <4 x i64> %t0 %t2 = select <4 x i1> %t1, <4 x i64> %x2, <4 x i64> %t0
%t3 = icmp sgt <4 x i64> %x3, %t2 %t3 = icmp sgt <4 x i64> %x3, %t2
%t4 = select <4 x i1> %t3, <4 x i64> %x3, <4 x i64> %t2 %t4 = select <4 x i1> %t3, <4 x i64> %x3, <4 x i64> %t2
ret <4 x i64> %t4 ret <4 x i64> %t4
} }
define <32 x i8> @reassociate_umin_v32i8(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, <32 x i8> %x3) { define <32 x i8> @reassociate_umin_v32i8(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, <32 x i8> %x3) {
; SSE-LABEL: reassociate_umin_v32i8: ; SSE-LABEL: reassociate_umin_v32i8:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: paddb %xmm2, %xmm0 ; SSE-NEXT: paddb %xmm2, %xmm0
; SSE-NEXT: paddb %xmm3, %xmm1
; SSE-NEXT: pminub %xmm6, %xmm4 ; SSE-NEXT: pminub %xmm6, %xmm4
; SSE-NEXT: pminub %xmm4, %xmm0 ; SSE-NEXT: paddb %xmm3, %xmm1
; SSE-NEXT: pminub %xmm7, %xmm5 ; SSE-NEXT: pminub %xmm7, %xmm5
; SSE-NEXT: pminub %xmm4, %xmm0
; SSE-NEXT: pminub %xmm5, %xmm1 ; SSE-NEXT: pminub %xmm5, %xmm1
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: reassociate_umin_v32i8: ; AVX-LABEL: reassociate_umin_v32i8:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpaddb %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vpaddb %ymm1, %ymm0, %ymm0
; AVX-NEXT: vpminub %ymm3, %ymm2, %ymm1 ; AVX-NEXT: vpminub %ymm3, %ymm2, %ymm2
; AVX-NEXT: vpminub %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vpminub %ymm2, %ymm0, %ymm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%t0 = add <32 x i8> %x0, %x1 %t0 = add <32 x i8> %x0, %x1
%t1 = icmp ult <32 x i8> %x2, %t0 %t1 = icmp ult <32 x i8> %x2, %t0
%t2 = select <32 x i1> %t1, <32 x i8> %x2, <32 x i8> %t0 %t2 = select <32 x i1> %t1, <32 x i8> %x2, <32 x i8> %t0
%t3 = icmp ult <32 x i8> %x3, %t2 %t3 = icmp ult <32 x i8> %x3, %t2
%t4 = select <32 x i1> %t3, <32 x i8> %x3, <32 x i8> %t2 %t4 = select <32 x i1> %t3, <32 x i8> %x3, <32 x i8> %t2
ret <32 x i8> %t4 ret <32 x i8> %t4
} }
define <16 x i16> @reassociate_umin_v16i16(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, <16 x i16> %x3) { define <16 x i16> @reassociate_umin_v16i16(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, <16 x i16> %x3) {
; SSE-LABEL: reassociate_umin_v16i16: ; SSE-LABEL: reassociate_umin_v16i16:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: paddw %xmm2, %xmm0
; SSE-NEXT: paddw %xmm3, %xmm1 ; SSE-NEXT: paddw %xmm3, %xmm1
; SSE-NEXT: movdqa {{.*#+}} xmm2 = [32768,32768,32768,32768,32768,32768,32768,32768] ; SSE-NEXT: movdqa {{.*#+}} xmm3 = [32768,32768,32768,32768,32768,32768,32768,32768]
; SSE-NEXT: pxor %xmm2, %xmm5 ; SSE-NEXT: paddw %xmm2, %xmm0
; SSE-NEXT: pxor %xmm2, %xmm1 ; SSE-NEXT: pxor %xmm3, %xmm5
; SSE-NEXT: pxor %xmm3, %xmm1
; SSE-NEXT: pxor %xmm3, %xmm4
; SSE-NEXT: pxor %xmm3, %xmm0
; SSE-NEXT: pxor %xmm3, %xmm6
; SSE-NEXT: pxor %xmm3, %xmm7
; SSE-NEXT: pminsw %xmm5, %xmm1 ; SSE-NEXT: pminsw %xmm5, %xmm1
; SSE-NEXT: pxor %xmm2, %xmm4
; SSE-NEXT: pxor %xmm2, %xmm0
; SSE-NEXT: pminsw %xmm4, %xmm0 ; SSE-NEXT: pminsw %xmm4, %xmm0
; SSE-NEXT: pxor %xmm2, %xmm6
; SSE-NEXT: pminsw %xmm6, %xmm0 ; SSE-NEXT: pminsw %xmm6, %xmm0
; SSE-NEXT: pxor %xmm2, %xmm0
; SSE-NEXT: pxor %xmm2, %xmm7
; SSE-NEXT: pminsw %xmm7, %xmm1 ; SSE-NEXT: pminsw %xmm7, %xmm1
; SSE-NEXT: pxor %xmm2, %xmm1 ; SSE-NEXT: pxor %xmm3, %xmm0
; SSE-NEXT: pxor %xmm3, %xmm1
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: reassociate_umin_v16i16: ; AVX-LABEL: reassociate_umin_v16i16:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpaddw %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vpaddw %ymm1, %ymm0, %ymm0
; AVX-NEXT: vpminuw %ymm3, %ymm2, %ymm1 ; AVX-NEXT: vpminuw %ymm3, %ymm2, %ymm2
; AVX-NEXT: vpminuw %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vpminuw %ymm2, %ymm0, %ymm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%t0 = add <16 x i16> %x0, %x1 %t0 = add <16 x i16> %x0, %x1
%t1 = icmp ult <16 x i16> %x2, %t0 %t1 = icmp ult <16 x i16> %x2, %t0
%t2 = select <16 x i1> %t1, <16 x i16> %x2, <16 x i16> %t0 %t2 = select <16 x i1> %t1, <16 x i16> %x2, <16 x i16> %t0
%t3 = icmp ult <16 x i16> %x3, %t2 %t3 = icmp ult <16 x i16> %x3, %t2
%t4 = select <16 x i1> %t3, <16 x i16> %x3, <16 x i16> %t2 %t4 = select <16 x i1> %t3, <16 x i16> %x3, <16 x i16> %t2
ret <16 x i16> %t4 ret <16 x i16> %t4
} }
define <8 x i32> @reassociate_umin_v8i32(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, <8 x i32> %x3) { define <8 x i32> @reassociate_umin_v8i32(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, <8 x i32> %x3) {
; SSE-LABEL: reassociate_umin_v8i32: ; SSE-LABEL: reassociate_umin_v8i32:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: paddd %xmm2, %xmm0 ; SSE-NEXT: movdqa {{.*#+}} xmm9 = [2147483648,2147483648,2147483648,2147483648]
; SSE-NEXT: paddd %xmm3, %xmm1 ; SSE-NEXT: paddd %xmm3, %xmm1
; SSE-NEXT: movdqa {{.*#+}} xmm3 = [2147483648,2147483648,2147483648,2147483648]
; SSE-NEXT: movdqa %xmm5, %xmm8 ; SSE-NEXT: movdqa %xmm5, %xmm8
; SSE-NEXT: pxor %xmm3, %xmm8 ; SSE-NEXT: paddd %xmm2, %xmm0
; SSE-NEXT: movdqa %xmm1, %xmm2 ; SSE-NEXT: movdqa %xmm1, %xmm2
; SSE-NEXT: pxor %xmm3, %xmm2 ; SSE-NEXT: pxor %xmm9, %xmm8
; SSE-NEXT: pxor %xmm9, %xmm2
; SSE-NEXT: pcmpgtd %xmm8, %xmm2 ; SSE-NEXT: pcmpgtd %xmm8, %xmm2
; SSE-NEXT: movdqa %xmm0, %xmm8
; SSE-NEXT: pand %xmm2, %xmm5 ; SSE-NEXT: pand %xmm2, %xmm5
; SSE-NEXT: pandn %xmm1, %xmm2 ; SSE-NEXT: pandn %xmm1, %xmm2
; SSE-NEXT: por %xmm5, %xmm2
; SSE-NEXT: movdqa %xmm4, %xmm1 ; SSE-NEXT: movdqa %xmm4, %xmm1
; SSE-NEXT: pxor %xmm3, %xmm1 ; SSE-NEXT: pxor %xmm9, %xmm8
; SSE-NEXT: movdqa %xmm0, %xmm5 ; SSE-NEXT: pxor %xmm9, %xmm1
; SSE-NEXT: pxor %xmm3, %xmm5 ; SSE-NEXT: por %xmm5, %xmm2
; SSE-NEXT: pcmpgtd %xmm1, %xmm5 ; SSE-NEXT: pcmpgtd %xmm1, %xmm8
; SSE-NEXT: pand %xmm5, %xmm4
; SSE-NEXT: pandn %xmm0, %xmm5
; SSE-NEXT: por %xmm4, %xmm5
; SSE-NEXT: movdqa %xmm5, %xmm0
; SSE-NEXT: pxor %xmm3, %xmm0
; SSE-NEXT: movdqa %xmm6, %xmm1 ; SSE-NEXT: movdqa %xmm6, %xmm1
; SSE-NEXT: pxor %xmm3, %xmm1 ; SSE-NEXT: pand %xmm8, %xmm4
; SSE-NEXT: pandn %xmm0, %xmm8
; SSE-NEXT: pxor %xmm9, %xmm1
; SSE-NEXT: por %xmm4, %xmm8
; SSE-NEXT: movdqa %xmm8, %xmm0
; SSE-NEXT: pxor %xmm9, %xmm0
; SSE-NEXT: pcmpgtd %xmm1, %xmm0 ; SSE-NEXT: pcmpgtd %xmm1, %xmm0
; SSE-NEXT: movdqa %xmm2, %xmm1
; SSE-NEXT: pxor %xmm9, %xmm1
; SSE-NEXT: pxor %xmm7, %xmm9
; SSE-NEXT: pand %xmm0, %xmm6 ; SSE-NEXT: pand %xmm0, %xmm6
; SSE-NEXT: pandn %xmm5, %xmm0 ; SSE-NEXT: pandn %xmm8, %xmm0
; SSE-NEXT: pcmpgtd %xmm9, %xmm1
; SSE-NEXT: por %xmm6, %xmm0 ; SSE-NEXT: por %xmm6, %xmm0
; SSE-NEXT: movdqa %xmm2, %xmm1
; SSE-NEXT: pxor %xmm3, %xmm1
; SSE-NEXT: pxor %xmm7, %xmm3
; SSE-NEXT: pcmpgtd %xmm3, %xmm1
; SSE-NEXT: pand %xmm1, %xmm7 ; SSE-NEXT: pand %xmm1, %xmm7
; SSE-NEXT: pandn %xmm2, %xmm1 ; SSE-NEXT: pandn %xmm2, %xmm1
; SSE-NEXT: por %xmm7, %xmm1 ; SSE-NEXT: por %xmm7, %xmm1
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: reassociate_umin_v8i32: ; AVX-LABEL: reassociate_umin_v8i32:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpaddd %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vpaddd %ymm1, %ymm0, %ymm0
; AVX-NEXT: vpminud %ymm3, %ymm2, %ymm1 ; AVX-NEXT: vpminud %ymm3, %ymm2, %ymm2
; AVX-NEXT: vpminud %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vpminud %ymm2, %ymm0, %ymm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%t0 = add <8 x i32> %x0, %x1 %t0 = add <8 x i32> %x0, %x1
%t1 = icmp ult <8 x i32> %x2, %t0 %t1 = icmp ult <8 x i32> %x2, %t0
%t2 = select <8 x i1> %t1, <8 x i32> %x2, <8 x i32> %t0 %t2 = select <8 x i1> %t1, <8 x i32> %x2, <8 x i32> %t0
%t3 = icmp ult <8 x i32> %x3, %t2 %t3 = icmp ult <8 x i32> %x3, %t2
%t4 = select <8 x i1> %t3, <8 x i32> %x3, <8 x i32> %t2 %t4 = select <8 x i1> %t3, <8 x i32> %x3, <8 x i32> %t2
ret <8 x i32> %t4 ret <8 x i32> %t4
} }
define <4 x i64> @reassociate_umin_v4i64(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, <4 x i64> %x3) { define <4 x i64> @reassociate_umin_v4i64(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, <4 x i64> %x3) {
; SSE-LABEL: reassociate_umin_v4i64: ; SSE-LABEL: reassociate_umin_v4i64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: paddq %xmm2, %xmm0
; SSE-NEXT: paddq %xmm3, %xmm1
; SSE-NEXT: movdqa {{.*#+}} xmm8 = [9223372039002259456,9223372039002259456] ; SSE-NEXT: movdqa {{.*#+}} xmm8 = [9223372039002259456,9223372039002259456]
; SSE-NEXT: paddq %xmm3, %xmm1
; SSE-NEXT: paddq %xmm2, %xmm0
; SSE-NEXT: movdqa %xmm5, %xmm3 ; SSE-NEXT: movdqa %xmm5, %xmm3
; SSE-NEXT: pxor %xmm8, %xmm3
; SSE-NEXT: movdqa %xmm1, %xmm2 ; SSE-NEXT: movdqa %xmm1, %xmm2
; SSE-NEXT: pxor %xmm8, %xmm2 ; SSE-NEXT: pxor %xmm8, %xmm2
; SSE-NEXT: pxor %xmm8, %xmm3
; SSE-NEXT: movdqa %xmm2, %xmm9 ; SSE-NEXT: movdqa %xmm2, %xmm9
; SSE-NEXT: pcmpgtd %xmm3, %xmm9
; SSE-NEXT: pshufd {{.*#+}} xmm10 = xmm9[0,0,2,2]
; SSE-NEXT: pcmpeqd %xmm3, %xmm2 ; SSE-NEXT: pcmpeqd %xmm3, %xmm2
; SSE-NEXT: pcmpgtd %xmm3, %xmm9
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; SSE-NEXT: pand %xmm10, %xmm2 ; SSE-NEXT: pshufd {{.*#+}} xmm10 = xmm9[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm9[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm9[1,1,3,3]
; SSE-NEXT: pand %xmm10, %xmm2
; SSE-NEXT: por %xmm2, %xmm3 ; SSE-NEXT: por %xmm2, %xmm3
; SSE-NEXT: movdqa %xmm0, %xmm2
; SSE-NEXT: pand %xmm3, %xmm5 ; SSE-NEXT: pand %xmm3, %xmm5
; SSE-NEXT: pandn %xmm1, %xmm3 ; SSE-NEXT: pandn %xmm1, %xmm3
; SSE-NEXT: por %xmm5, %xmm3
; SSE-NEXT: movdqa %xmm4, %xmm1 ; SSE-NEXT: movdqa %xmm4, %xmm1
; SSE-NEXT: pxor %xmm8, %xmm1
; SSE-NEXT: movdqa %xmm0, %xmm2
; SSE-NEXT: pxor %xmm8, %xmm2 ; SSE-NEXT: pxor %xmm8, %xmm2
; SSE-NEXT: por %xmm5, %xmm3
; SSE-NEXT: pxor %xmm8, %xmm1
; SSE-NEXT: movdqa %xmm2, %xmm5 ; SSE-NEXT: movdqa %xmm2, %xmm5
; SSE-NEXT: pcmpgtd %xmm1, %xmm5 ; SSE-NEXT: pcmpgtd %xmm1, %xmm5
; SSE-NEXT: pshufd {{.*#+}} xmm9 = xmm5[0,0,2,2]
; SSE-NEXT: pcmpeqd %xmm1, %xmm2 ; SSE-NEXT: pcmpeqd %xmm1, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3]
; SSE-NEXT: pand %xmm9, %xmm1 ; SSE-NEXT: pshufd {{.*#+}} xmm9 = xmm5[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm5[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm5[1,1,3,3]
; SSE-NEXT: pand %xmm9, %xmm1
; SSE-NEXT: por %xmm1, %xmm2 ; SSE-NEXT: por %xmm1, %xmm2
; SSE-NEXT: movdqa %xmm6, %xmm1
; SSE-NEXT: pand %xmm2, %xmm4 ; SSE-NEXT: pand %xmm2, %xmm4
; SSE-NEXT: pandn %xmm0, %xmm2 ; SSE-NEXT: pandn %xmm0, %xmm2
; SSE-NEXT: pxor %xmm8, %xmm1
; SSE-NEXT: por %xmm4, %xmm2 ; SSE-NEXT: por %xmm4, %xmm2
; SSE-NEXT: movdqa %xmm2, %xmm0 ; SSE-NEXT: movdqa %xmm2, %xmm0
; SSE-NEXT: pxor %xmm8, %xmm0 ; SSE-NEXT: pxor %xmm8, %xmm0
; SSE-NEXT: movdqa %xmm6, %xmm1
; SSE-NEXT: pxor %xmm8, %xmm1
; SSE-NEXT: movdqa %xmm0, %xmm4 ; SSE-NEXT: movdqa %xmm0, %xmm4
; SSE-NEXT: pcmpgtd %xmm1, %xmm4 ; SSE-NEXT: pcmpgtd %xmm1, %xmm4
; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
; SSE-NEXT: pcmpeqd %xmm0, %xmm1 ; SSE-NEXT: pcmpeqd %xmm0, %xmm1
; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; SSE-NEXT: pand %xmm5, %xmm1
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm4[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm4[1,1,3,3]
; SSE-NEXT: pand %xmm5, %xmm1
; SSE-NEXT: por %xmm1, %xmm0 ; SSE-NEXT: por %xmm1, %xmm0
; SSE-NEXT: pand %xmm0, %xmm6
; SSE-NEXT: pandn %xmm2, %xmm0
; SSE-NEXT: por %xmm6, %xmm0
; SSE-NEXT: movdqa %xmm3, %xmm1 ; SSE-NEXT: movdqa %xmm3, %xmm1
; SSE-NEXT: pxor %xmm8, %xmm1 ; SSE-NEXT: pxor %xmm8, %xmm1
; SSE-NEXT: pand %xmm0, %xmm6
; SSE-NEXT: pandn %xmm2, %xmm0
; SSE-NEXT: pxor %xmm7, %xmm8 ; SSE-NEXT: pxor %xmm7, %xmm8
; SSE-NEXT: movdqa %xmm1, %xmm2 ; SSE-NEXT: movdqa %xmm1, %xmm2
; SSE-NEXT: por %xmm6, %xmm0
; SSE-NEXT: pcmpgtd %xmm8, %xmm2 ; SSE-NEXT: pcmpgtd %xmm8, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm2[0,0,2,2]
; SSE-NEXT: pcmpeqd %xmm1, %xmm8 ; SSE-NEXT: pcmpeqd %xmm1, %xmm8
; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm2[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm8[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm8[1,1,3,3]
; SSE-NEXT: pand %xmm4, %xmm5
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3]
; SSE-NEXT: pand %xmm4, %xmm5
; SSE-NEXT: por %xmm5, %xmm1 ; SSE-NEXT: por %xmm5, %xmm1
; SSE-NEXT: pand %xmm1, %xmm7 ; SSE-NEXT: pand %xmm1, %xmm7
; SSE-NEXT: pandn %xmm3, %xmm1 ; SSE-NEXT: pandn %xmm3, %xmm1
; SSE-NEXT: por %xmm7, %xmm1 ; SSE-NEXT: por %xmm7, %xmm1
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX2-LABEL: reassociate_umin_v4i64: ; AVX2-LABEL: reassociate_umin_v4i64:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpaddq %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpaddq %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808] ; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808]
; AVX2-NEXT: vpxor %ymm1, %ymm2, %ymm4 ; AVX2-NEXT: vpxor %ymm1, %ymm2, %ymm4
; AVX2-NEXT: vpxor %ymm1, %ymm0, %ymm5 ; AVX2-NEXT: vpxor %ymm1, %ymm0, %ymm5
; AVX2-NEXT: vpcmpgtq %ymm4, %ymm5, %ymm4 ; AVX2-NEXT: vpcmpgtq %ymm4, %ymm5, %ymm4
; AVX2-NEXT: vblendvpd %ymm4, %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vblendvpd %ymm4, %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vxorpd %ymm1, %ymm0, %ymm2 ; AVX2-NEXT: vxorpd %ymm1, %ymm0, %ymm2
; AVX2-NEXT: vpxor %ymm1, %ymm3, %ymm1 ; AVX2-NEXT: vpxor %ymm1, %ymm3, %ymm1
; AVX2-NEXT: vpcmpgtq %ymm1, %ymm2, %ymm1 ; AVX2-NEXT: vpcmpgtq %ymm1, %ymm2, %ymm1
; AVX2-NEXT: vblendvpd %ymm1, %ymm3, %ymm0, %ymm0 ; AVX2-NEXT: vblendvpd %ymm1, %ymm3, %ymm0, %ymm0
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: reassociate_umin_v4i64: ; AVX512-LABEL: reassociate_umin_v4i64:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vpaddq %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: vpaddq %ymm1, %ymm0, %ymm0
; AVX512-NEXT: vpminuq %ymm3, %ymm2, %ymm1 ; AVX512-NEXT: vpminuq %ymm3, %ymm2, %ymm2
; AVX512-NEXT: vpminuq %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: vpminuq %ymm2, %ymm0, %ymm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%t0 = add <4 x i64> %x0, %x1 %t0 = add <4 x i64> %x0, %x1
%t1 = icmp ult <4 x i64> %x2, %t0 %t1 = icmp ult <4 x i64> %x2, %t0
%t2 = select <4 x i1> %t1, <4 x i64> %x2, <4 x i64> %t0 %t2 = select <4 x i1> %t1, <4 x i64> %x2, <4 x i64> %t0
%t3 = icmp ult <4 x i64> %x3, %t2 %t3 = icmp ult <4 x i64> %x3, %t2
%t4 = select <4 x i1> %t3, <4 x i64> %x3, <4 x i64> %t2 %t4 = select <4 x i1> %t3, <4 x i64> %x3, <4 x i64> %t2
ret <4 x i64> %t4 ret <4 x i64> %t4
} }
define <32 x i8> @reassociate_smin_v32i8(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, <32 x i8> %x3) { define <32 x i8> @reassociate_smin_v32i8(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, <32 x i8> %x3) {
; SSE-LABEL: reassociate_smin_v32i8: ; SSE-LABEL: reassociate_smin_v32i8:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: paddb %xmm2, %xmm0
; SSE-NEXT: paddb %xmm3, %xmm1 ; SSE-NEXT: paddb %xmm3, %xmm1
; SSE-NEXT: paddb %xmm2, %xmm0
; SSE-NEXT: movdqa %xmm1, %xmm2 ; SSE-NEXT: movdqa %xmm1, %xmm2
; SSE-NEXT: pcmpgtb %xmm5, %xmm2 ; SSE-NEXT: pcmpgtb %xmm5, %xmm2
; SSE-NEXT: pand %xmm2, %xmm5 ; SSE-NEXT: pand %xmm2, %xmm5
; SSE-NEXT: pandn %xmm1, %xmm2 ; SSE-NEXT: pandn %xmm1, %xmm2
; SSE-NEXT: por %xmm5, %xmm2
; SSE-NEXT: movdqa %xmm0, %xmm1 ; SSE-NEXT: movdqa %xmm0, %xmm1
; SSE-NEXT: pcmpgtb %xmm4, %xmm1 ; SSE-NEXT: pcmpgtb %xmm4, %xmm1
; SSE-NEXT: por %xmm5, %xmm2
; SSE-NEXT: pand %xmm1, %xmm4 ; SSE-NEXT: pand %xmm1, %xmm4
; SSE-NEXT: pandn %xmm0, %xmm1 ; SSE-NEXT: pandn %xmm0, %xmm1
; SSE-NEXT: por %xmm4, %xmm1 ; SSE-NEXT: por %xmm4, %xmm1
; SSE-NEXT: movdqa %xmm1, %xmm0 ; SSE-NEXT: movdqa %xmm1, %xmm0
; SSE-NEXT: pcmpgtb %xmm6, %xmm0 ; SSE-NEXT: pcmpgtb %xmm6, %xmm0
; SSE-NEXT: pand %xmm0, %xmm6 ; SSE-NEXT: pand %xmm0, %xmm6
; SSE-NEXT: pandn %xmm1, %xmm0 ; SSE-NEXT: pandn %xmm1, %xmm0
; SSE-NEXT: por %xmm6, %xmm0
; SSE-NEXT: movdqa %xmm2, %xmm1 ; SSE-NEXT: movdqa %xmm2, %xmm1
; SSE-NEXT: pcmpgtb %xmm7, %xmm1 ; SSE-NEXT: pcmpgtb %xmm7, %xmm1
; SSE-NEXT: por %xmm6, %xmm0
; SSE-NEXT: pand %xmm1, %xmm7 ; SSE-NEXT: pand %xmm1, %xmm7
; SSE-NEXT: pandn %xmm2, %xmm1 ; SSE-NEXT: pandn %xmm2, %xmm1
; SSE-NEXT: por %xmm7, %xmm1 ; SSE-NEXT: por %xmm7, %xmm1
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: reassociate_smin_v32i8: ; AVX-LABEL: reassociate_smin_v32i8:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpaddb %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vpaddb %ymm1, %ymm0, %ymm0
; AVX-NEXT: vpminsb %ymm3, %ymm2, %ymm1 ; AVX-NEXT: vpminsb %ymm3, %ymm2, %ymm2
; AVX-NEXT: vpminsb %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vpminsb %ymm2, %ymm0, %ymm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%t0 = add <32 x i8> %x0, %x1 %t0 = add <32 x i8> %x0, %x1
%t1 = icmp slt <32 x i8> %x2, %t0 %t1 = icmp slt <32 x i8> %x2, %t0
%t2 = select <32 x i1> %t1, <32 x i8> %x2, <32 x i8> %t0 %t2 = select <32 x i1> %t1, <32 x i8> %x2, <32 x i8> %t0
%t3 = icmp slt <32 x i8> %x3, %t2 %t3 = icmp slt <32 x i8> %x3, %t2
%t4 = select <32 x i1> %t3, <32 x i8> %x3, <32 x i8> %t2 %t4 = select <32 x i1> %t3, <32 x i8> %x3, <32 x i8> %t2
ret <32 x i8> %t4 ret <32 x i8> %t4
} }
define <16 x i16> @reassociate_smin_v16i16(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, <16 x i16> %x3) { define <16 x i16> @reassociate_smin_v16i16(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, <16 x i16> %x3) {
; SSE-LABEL: reassociate_smin_v16i16: ; SSE-LABEL: reassociate_smin_v16i16:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: paddw %xmm2, %xmm0 ; SSE-NEXT: paddw %xmm2, %xmm0
; SSE-NEXT: paddw %xmm3, %xmm1
; SSE-NEXT: pminsw %xmm6, %xmm4 ; SSE-NEXT: pminsw %xmm6, %xmm4
; SSE-NEXT: pminsw %xmm4, %xmm0 ; SSE-NEXT: paddw %xmm3, %xmm1
; SSE-NEXT: pminsw %xmm7, %xmm5 ; SSE-NEXT: pminsw %xmm7, %xmm5
; SSE-NEXT: pminsw %xmm4, %xmm0
; SSE-NEXT: pminsw %xmm5, %xmm1 ; SSE-NEXT: pminsw %xmm5, %xmm1
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: reassociate_smin_v16i16: ; AVX-LABEL: reassociate_smin_v16i16:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpaddw %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vpaddw %ymm1, %ymm0, %ymm0
; AVX-NEXT: vpminsw %ymm3, %ymm2, %ymm1 ; AVX-NEXT: vpminsw %ymm3, %ymm2, %ymm2
; AVX-NEXT: vpminsw %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vpminsw %ymm2, %ymm0, %ymm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%t0 = add <16 x i16> %x0, %x1 %t0 = add <16 x i16> %x0, %x1
%t1 = icmp slt <16 x i16> %x2, %t0 %t1 = icmp slt <16 x i16> %x2, %t0
%t2 = select <16 x i1> %t1, <16 x i16> %x2, <16 x i16> %t0 %t2 = select <16 x i1> %t1, <16 x i16> %x2, <16 x i16> %t0
%t3 = icmp slt <16 x i16> %x3, %t2 %t3 = icmp slt <16 x i16> %x3, %t2
%t4 = select <16 x i1> %t3, <16 x i16> %x3, <16 x i16> %t2 %t4 = select <16 x i1> %t3, <16 x i16> %x3, <16 x i16> %t2
ret <16 x i16> %t4 ret <16 x i16> %t4
} }
define <8 x i32> @reassociate_smin_v8i32(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, <8 x i32> %x3) { define <8 x i32> @reassociate_smin_v8i32(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, <8 x i32> %x3) {
; SSE-LABEL: reassociate_smin_v8i32: ; SSE-LABEL: reassociate_smin_v8i32:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: paddd %xmm2, %xmm0
; SSE-NEXT: paddd %xmm3, %xmm1 ; SSE-NEXT: paddd %xmm3, %xmm1
; SSE-NEXT: paddd %xmm2, %xmm0
; SSE-NEXT: movdqa %xmm1, %xmm2 ; SSE-NEXT: movdqa %xmm1, %xmm2
; SSE-NEXT: pcmpgtd %xmm5, %xmm2 ; SSE-NEXT: pcmpgtd %xmm5, %xmm2
; SSE-NEXT: pand %xmm2, %xmm5 ; SSE-NEXT: pand %xmm2, %xmm5
; SSE-NEXT: pandn %xmm1, %xmm2 ; SSE-NEXT: pandn %xmm1, %xmm2
; SSE-NEXT: por %xmm5, %xmm2
; SSE-NEXT: movdqa %xmm0, %xmm1 ; SSE-NEXT: movdqa %xmm0, %xmm1
; SSE-NEXT: pcmpgtd %xmm4, %xmm1 ; SSE-NEXT: pcmpgtd %xmm4, %xmm1
; SSE-NEXT: por %xmm5, %xmm2
; SSE-NEXT: pand %xmm1, %xmm4 ; SSE-NEXT: pand %xmm1, %xmm4
; SSE-NEXT: pandn %xmm0, %xmm1 ; SSE-NEXT: pandn %xmm0, %xmm1
; SSE-NEXT: por %xmm4, %xmm1 ; SSE-NEXT: por %xmm4, %xmm1
; SSE-NEXT: movdqa %xmm1, %xmm0 ; SSE-NEXT: movdqa %xmm1, %xmm0
; SSE-NEXT: pcmpgtd %xmm6, %xmm0 ; SSE-NEXT: pcmpgtd %xmm6, %xmm0
; SSE-NEXT: pand %xmm0, %xmm6 ; SSE-NEXT: pand %xmm0, %xmm6
; SSE-NEXT: pandn %xmm1, %xmm0 ; SSE-NEXT: pandn %xmm1, %xmm0
; SSE-NEXT: por %xmm6, %xmm0
; SSE-NEXT: movdqa %xmm2, %xmm1 ; SSE-NEXT: movdqa %xmm2, %xmm1
; SSE-NEXT: pcmpgtd %xmm7, %xmm1 ; SSE-NEXT: pcmpgtd %xmm7, %xmm1
; SSE-NEXT: por %xmm6, %xmm0
; SSE-NEXT: pand %xmm1, %xmm7 ; SSE-NEXT: pand %xmm1, %xmm7
; SSE-NEXT: pandn %xmm2, %xmm1 ; SSE-NEXT: pandn %xmm2, %xmm1
; SSE-NEXT: por %xmm7, %xmm1 ; SSE-NEXT: por %xmm7, %xmm1
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: reassociate_smin_v8i32: ; AVX-LABEL: reassociate_smin_v8i32:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpaddd %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vpaddd %ymm1, %ymm0, %ymm0
; AVX-NEXT: vpminsd %ymm3, %ymm2, %ymm1 ; AVX-NEXT: vpminsd %ymm3, %ymm2, %ymm2
; AVX-NEXT: vpminsd %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vpminsd %ymm2, %ymm0, %ymm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%t0 = add <8 x i32> %x0, %x1 %t0 = add <8 x i32> %x0, %x1
%t1 = icmp slt <8 x i32> %x2, %t0 %t1 = icmp slt <8 x i32> %x2, %t0
%t2 = select <8 x i1> %t1, <8 x i32> %x2, <8 x i32> %t0 %t2 = select <8 x i1> %t1, <8 x i32> %x2, <8 x i32> %t0
%t3 = icmp slt <8 x i32> %x3, %t2 %t3 = icmp slt <8 x i32> %x3, %t2
%t4 = select <8 x i1> %t3, <8 x i32> %x3, <8 x i32> %t2 %t4 = select <8 x i1> %t3, <8 x i32> %x3, <8 x i32> %t2
ret <8 x i32> %t4 ret <8 x i32> %t4
} }
define <4 x i64> @reassociate_smin_v4i64(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, <4 x i64> %x3) { define <4 x i64> @reassociate_smin_v4i64(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, <4 x i64> %x3) {
; SSE-LABEL: reassociate_smin_v4i64: ; SSE-LABEL: reassociate_smin_v4i64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: paddq %xmm2, %xmm0
; SSE-NEXT: paddq %xmm3, %xmm1
; SSE-NEXT: movdqa {{.*#+}} xmm8 = [2147483648,2147483648] ; SSE-NEXT: movdqa {{.*#+}} xmm8 = [2147483648,2147483648]
; SSE-NEXT: paddq %xmm3, %xmm1
; SSE-NEXT: paddq %xmm2, %xmm0
; SSE-NEXT: movdqa %xmm5, %xmm3 ; SSE-NEXT: movdqa %xmm5, %xmm3
; SSE-NEXT: pxor %xmm8, %xmm3
; SSE-NEXT: movdqa %xmm1, %xmm2 ; SSE-NEXT: movdqa %xmm1, %xmm2
; SSE-NEXT: pxor %xmm8, %xmm2 ; SSE-NEXT: pxor %xmm8, %xmm2
; SSE-NEXT: pxor %xmm8, %xmm3
; SSE-NEXT: movdqa %xmm2, %xmm9 ; SSE-NEXT: movdqa %xmm2, %xmm9
; SSE-NEXT: pcmpgtd %xmm3, %xmm9
; SSE-NEXT: pshufd {{.*#+}} xmm10 = xmm9[0,0,2,2]
; SSE-NEXT: pcmpeqd %xmm3, %xmm2 ; SSE-NEXT: pcmpeqd %xmm3, %xmm2
; SSE-NEXT: pcmpgtd %xmm3, %xmm9
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; SSE-NEXT: pand %xmm10, %xmm2 ; SSE-NEXT: pshufd {{.*#+}} xmm10 = xmm9[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm9[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm9[1,1,3,3]
; SSE-NEXT: pand %xmm10, %xmm2
; SSE-NEXT: por %xmm2, %xmm3 ; SSE-NEXT: por %xmm2, %xmm3
; SSE-NEXT: movdqa %xmm0, %xmm2
; SSE-NEXT: pand %xmm3, %xmm5 ; SSE-NEXT: pand %xmm3, %xmm5
; SSE-NEXT: pandn %xmm1, %xmm3 ; SSE-NEXT: pandn %xmm1, %xmm3
; SSE-NEXT: por %xmm5, %xmm3
; SSE-NEXT: movdqa %xmm4, %xmm1 ; SSE-NEXT: movdqa %xmm4, %xmm1
; SSE-NEXT: pxor %xmm8, %xmm1
; SSE-NEXT: movdqa %xmm0, %xmm2
; SSE-NEXT: pxor %xmm8, %xmm2 ; SSE-NEXT: pxor %xmm8, %xmm2
; SSE-NEXT: por %xmm5, %xmm3
; SSE-NEXT: pxor %xmm8, %xmm1
; SSE-NEXT: movdqa %xmm2, %xmm5 ; SSE-NEXT: movdqa %xmm2, %xmm5
; SSE-NEXT: pcmpgtd %xmm1, %xmm5 ; SSE-NEXT: pcmpgtd %xmm1, %xmm5
; SSE-NEXT: pshufd {{.*#+}} xmm9 = xmm5[0,0,2,2]
; SSE-NEXT: pcmpeqd %xmm1, %xmm2 ; SSE-NEXT: pcmpeqd %xmm1, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3]
; SSE-NEXT: pand %xmm9, %xmm1 ; SSE-NEXT: pshufd {{.*#+}} xmm9 = xmm5[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm5[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm5[1,1,3,3]
; SSE-NEXT: pand %xmm9, %xmm1
; SSE-NEXT: por %xmm1, %xmm2 ; SSE-NEXT: por %xmm1, %xmm2
; SSE-NEXT: movdqa %xmm6, %xmm1
; SSE-NEXT: pand %xmm2, %xmm4 ; SSE-NEXT: pand %xmm2, %xmm4
; SSE-NEXT: pandn %xmm0, %xmm2 ; SSE-NEXT: pandn %xmm0, %xmm2
; SSE-NEXT: pxor %xmm8, %xmm1
; SSE-NEXT: por %xmm4, %xmm2 ; SSE-NEXT: por %xmm4, %xmm2
; SSE-NEXT: movdqa %xmm2, %xmm0 ; SSE-NEXT: movdqa %xmm2, %xmm0
; SSE-NEXT: pxor %xmm8, %xmm0 ; SSE-NEXT: pxor %xmm8, %xmm0
; SSE-NEXT: movdqa %xmm6, %xmm1
; SSE-NEXT: pxor %xmm8, %xmm1
; SSE-NEXT: movdqa %xmm0, %xmm4 ; SSE-NEXT: movdqa %xmm0, %xmm4
; SSE-NEXT: pcmpgtd %xmm1, %xmm4 ; SSE-NEXT: pcmpgtd %xmm1, %xmm4
; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
; SSE-NEXT: pcmpeqd %xmm0, %xmm1 ; SSE-NEXT: pcmpeqd %xmm0, %xmm1
; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; SSE-NEXT: pand %xmm5, %xmm1
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm4[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm4[1,1,3,3]
; SSE-NEXT: pand %xmm5, %xmm1
; SSE-NEXT: por %xmm1, %xmm0 ; SSE-NEXT: por %xmm1, %xmm0
; SSE-NEXT: pand %xmm0, %xmm6
; SSE-NEXT: pandn %xmm2, %xmm0
; SSE-NEXT: por %xmm6, %xmm0
; SSE-NEXT: movdqa %xmm3, %xmm1 ; SSE-NEXT: movdqa %xmm3, %xmm1
; SSE-NEXT: pxor %xmm8, %xmm1 ; SSE-NEXT: pxor %xmm8, %xmm1
; SSE-NEXT: pand %xmm0, %xmm6
; SSE-NEXT: pandn %xmm2, %xmm0
; SSE-NEXT: pxor %xmm7, %xmm8 ; SSE-NEXT: pxor %xmm7, %xmm8
; SSE-NEXT: movdqa %xmm1, %xmm2 ; SSE-NEXT: movdqa %xmm1, %xmm2
; SSE-NEXT: por %xmm6, %xmm0
; SSE-NEXT: pcmpgtd %xmm8, %xmm2 ; SSE-NEXT: pcmpgtd %xmm8, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm2[0,0,2,2]
; SSE-NEXT: pcmpeqd %xmm1, %xmm8 ; SSE-NEXT: pcmpeqd %xmm1, %xmm8
; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm2[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm8[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm8[1,1,3,3]
; SSE-NEXT: pand %xmm4, %xmm5
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3]
; SSE-NEXT: pand %xmm4, %xmm5
; SSE-NEXT: por %xmm5, %xmm1 ; SSE-NEXT: por %xmm5, %xmm1
; SSE-NEXT: pand %xmm1, %xmm7 ; SSE-NEXT: pand %xmm1, %xmm7
; SSE-NEXT: pandn %xmm3, %xmm1 ; SSE-NEXT: pandn %xmm3, %xmm1
; SSE-NEXT: por %xmm7, %xmm1 ; SSE-NEXT: por %xmm7, %xmm1
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX2-LABEL: reassociate_smin_v4i64: ; AVX2-LABEL: reassociate_smin_v4i64:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpaddq %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: vpaddq %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpcmpgtq %ymm2, %ymm0, %ymm1 ; AVX2-NEXT: vpcmpgtq %ymm2, %ymm0, %ymm1
; AVX2-NEXT: vblendvpd %ymm1, %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vblendvpd %ymm1, %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpcmpgtq %ymm3, %ymm0, %ymm1 ; AVX2-NEXT: vpcmpgtq %ymm3, %ymm0, %ymm1
; AVX2-NEXT: vblendvpd %ymm1, %ymm3, %ymm0, %ymm0 ; AVX2-NEXT: vblendvpd %ymm1, %ymm3, %ymm0, %ymm0
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: reassociate_smin_v4i64: ; AVX512-LABEL: reassociate_smin_v4i64:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vpaddq %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: vpaddq %ymm1, %ymm0, %ymm0
; AVX512-NEXT: vpminsq %ymm3, %ymm2, %ymm1 ; AVX512-NEXT: vpminsq %ymm3, %ymm2, %ymm2
; AVX512-NEXT: vpminsq %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: vpminsq %ymm2, %ymm0, %ymm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%t0 = add <4 x i64> %x0, %x1 %t0 = add <4 x i64> %x0, %x1
%t1 = icmp slt <4 x i64> %x2, %t0 %t1 = icmp slt <4 x i64> %x2, %t0
%t2 = select <4 x i1> %t1, <4 x i64> %x2, <4 x i64> %t0 %t2 = select <4 x i1> %t1, <4 x i64> %x2, <4 x i64> %t0
%t3 = icmp slt <4 x i64> %x3, %t2 %t3 = icmp slt <4 x i64> %x3, %t2
%t4 = select <4 x i1> %t3, <4 x i64> %x3, <4 x i64> %t2 %t4 = select <4 x i1> %t3, <4 x i64> %x3, <4 x i64> %t2
ret <4 x i64> %t4 ret <4 x i64> %t4
Show All 15 Lines
; SSE-NEXT: pmaxub {{[0-9]+}}(%rsp), %xmm0 ; SSE-NEXT: pmaxub {{[0-9]+}}(%rsp), %xmm0
; SSE-NEXT: pmaxub {{[0-9]+}}(%rsp), %xmm1 ; SSE-NEXT: pmaxub {{[0-9]+}}(%rsp), %xmm1
; SSE-NEXT: pmaxub {{[0-9]+}}(%rsp), %xmm2 ; SSE-NEXT: pmaxub {{[0-9]+}}(%rsp), %xmm2
; SSE-NEXT: pmaxub {{[0-9]+}}(%rsp), %xmm3 ; SSE-NEXT: pmaxub {{[0-9]+}}(%rsp), %xmm3
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX2-LABEL: reassociate_umax_v64i8: ; AVX2-LABEL: reassociate_umax_v64i8:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpaddb %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpaddb %ymm3, %ymm1, %ymm1 ; AVX2-NEXT: vpaddb %ymm3, %ymm1, %ymm1
; AVX2-NEXT: vpmaxub %ymm6, %ymm4, %ymm2 ; AVX2-NEXT: vpmaxub %ymm7, %ymm5, %ymm3
; AVX2-NEXT: vpmaxub %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpaddb %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpmaxub %ymm7, %ymm5, %ymm2 ; AVX2-NEXT: vpmaxub %ymm6, %ymm4, %ymm4
; AVX2-NEXT: vpmaxub %ymm2, %ymm1, %ymm1 ; AVX2-NEXT: vpmaxub %ymm4, %ymm0, %ymm0
; AVX2-NEXT: vpmaxub %ymm3, %ymm1, %ymm1
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: reassociate_umax_v64i8: ; AVX512-LABEL: reassociate_umax_v64i8:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vpaddb %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vpaddb %zmm1, %zmm0, %zmm0
; AVX512-NEXT: vpmaxub %zmm3, %zmm2, %zmm1 ; AVX512-NEXT: vpmaxub %zmm3, %zmm2, %zmm2
; AVX512-NEXT: vpmaxub %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vpmaxub %zmm2, %zmm0, %zmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%t0 = add <64 x i8> %x0, %x1 %t0 = add <64 x i8> %x0, %x1
%t1 = icmp ugt <64 x i8> %x2, %t0 %t1 = icmp ugt <64 x i8> %x2, %t0
%t2 = select <64 x i1> %t1, <64 x i8> %x2, <64 x i8> %t0 %t2 = select <64 x i1> %t1, <64 x i8> %x2, <64 x i8> %t0
%t3 = icmp ugt <64 x i8> %x3, %t2 %t3 = icmp ugt <64 x i8> %x3, %t2
%t4 = select <64 x i1> %t3, <64 x i8> %x3, <64 x i8> %t2 %t4 = select <64 x i1> %t3, <64 x i8> %x3, <64 x i8> %t2
ret <64 x i8> %t4 ret <64 x i8> %t4
} }
define <32 x i16> @reassociate_umax_v32i16(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, <32 x i16> %x3) { define <32 x i16> @reassociate_umax_v32i16(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, <32 x i16> %x3) {
; SSE-LABEL: reassociate_umax_v32i16: ; SSE-LABEL: reassociate_umax_v32i16:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: paddw %xmm4, %xmm0 ; SSE-NEXT: paddw %xmm4, %xmm0
; SSE-NEXT: paddw %xmm5, %xmm1
; SSE-NEXT: paddw %xmm6, %xmm2 ; SSE-NEXT: paddw %xmm6, %xmm2
; SSE-NEXT: paddw %xmm7, %xmm3
; SSE-NEXT: movdqa {{.*#+}} xmm4 = [32768,32768,32768,32768,32768,32768,32768,32768] ; SSE-NEXT: movdqa {{.*#+}} xmm4 = [32768,32768,32768,32768,32768,32768,32768,32768]
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm6
; SSE-NEXT: paddw %xmm7, %xmm3
; SSE-NEXT: paddw %xmm5, %xmm1
; SSE-NEXT: pxor %xmm4, %xmm3 ; SSE-NEXT: pxor %xmm4, %xmm3
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm5 ; SSE-NEXT: pxor %xmm4, %xmm6
; SSE-NEXT: pxor %xmm4, %xmm5
; SSE-NEXT: pmaxsw %xmm3, %xmm5
; SSE-NEXT: pxor %xmm4, %xmm2 ; SSE-NEXT: pxor %xmm4, %xmm2
; SSE-NEXT: pxor %xmm4, %xmm1
; SSE-NEXT: pxor %xmm4, %xmm0
; SSE-NEXT: pmaxsw %xmm3, %xmm6
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm3 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm3
; SSE-NEXT: pxor %xmm4, %xmm3 ; SSE-NEXT: pxor %xmm4, %xmm3
; SSE-NEXT: pmaxsw %xmm2, %xmm3 ; SSE-NEXT: pmaxsw %xmm2, %xmm3
; SSE-NEXT: pxor %xmm4, %xmm1
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm2 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm2
; SSE-NEXT: pxor %xmm4, %xmm2 ; SSE-NEXT: pxor %xmm4, %xmm2
; SSE-NEXT: pmaxsw %xmm1, %xmm2 ; SSE-NEXT: pmaxsw %xmm1, %xmm2
; SSE-NEXT: pxor %xmm4, %xmm0
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm1 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm1
; SSE-NEXT: pxor %xmm4, %xmm1 ; SSE-NEXT: pxor %xmm4, %xmm1
; SSE-NEXT: pmaxsw %xmm0, %xmm1 ; SSE-NEXT: pmaxsw %xmm0, %xmm1
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm0 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm0
; SSE-NEXT: pxor %xmm4, %xmm0 ; SSE-NEXT: pxor %xmm4, %xmm0
; SSE-NEXT: pmaxsw %xmm1, %xmm0 ; SSE-NEXT: pmaxsw %xmm1, %xmm0
; SSE-NEXT: pxor %xmm4, %xmm0
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm1 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm1
; SSE-NEXT: pxor %xmm4, %xmm0
; SSE-NEXT: pxor %xmm4, %xmm1 ; SSE-NEXT: pxor %xmm4, %xmm1
; SSE-NEXT: pmaxsw %xmm2, %xmm1 ; SSE-NEXT: pmaxsw %xmm2, %xmm1
; SSE-NEXT: pxor %xmm4, %xmm1
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm2 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm2
; SSE-NEXT: pxor %xmm4, %xmm1
; SSE-NEXT: pxor %xmm4, %xmm2 ; SSE-NEXT: pxor %xmm4, %xmm2
; SSE-NEXT: pmaxsw %xmm3, %xmm2 ; SSE-NEXT: pmaxsw %xmm3, %xmm2
; SSE-NEXT: pxor %xmm4, %xmm2
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm3 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm3
; SSE-NEXT: pxor %xmm4, %xmm2
; SSE-NEXT: pxor %xmm4, %xmm3 ; SSE-NEXT: pxor %xmm4, %xmm3
; SSE-NEXT: pmaxsw %xmm5, %xmm3 ; SSE-NEXT: pmaxsw %xmm6, %xmm3
; SSE-NEXT: pxor %xmm4, %xmm3 ; SSE-NEXT: pxor %xmm4, %xmm3
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX2-LABEL: reassociate_umax_v32i16: ; AVX2-LABEL: reassociate_umax_v32i16:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpaddw %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpaddw %ymm3, %ymm1, %ymm1 ; AVX2-NEXT: vpaddw %ymm3, %ymm1, %ymm1
; AVX2-NEXT: vpmaxuw %ymm6, %ymm4, %ymm2 ; AVX2-NEXT: vpmaxuw %ymm7, %ymm5, %ymm3
; AVX2-NEXT: vpmaxuw %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpaddw %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpmaxuw %ymm7, %ymm5, %ymm2 ; AVX2-NEXT: vpmaxuw %ymm6, %ymm4, %ymm4
; AVX2-NEXT: vpmaxuw %ymm2, %ymm1, %ymm1 ; AVX2-NEXT: vpmaxuw %ymm4, %ymm0, %ymm0
; AVX2-NEXT: vpmaxuw %ymm3, %ymm1, %ymm1
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: reassociate_umax_v32i16: ; AVX512-LABEL: reassociate_umax_v32i16:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vpaddw %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vpaddw %zmm1, %zmm0, %zmm0
; AVX512-NEXT: vpmaxuw %zmm3, %zmm2, %zmm1 ; AVX512-NEXT: vpmaxuw %zmm3, %zmm2, %zmm2
; AVX512-NEXT: vpmaxuw %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vpmaxuw %zmm2, %zmm0, %zmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%t0 = add <32 x i16> %x0, %x1 %t0 = add <32 x i16> %x0, %x1
%t1 = icmp ugt <32 x i16> %x2, %t0 %t1 = icmp ugt <32 x i16> %x2, %t0
%t2 = select <32 x i1> %t1, <32 x i16> %x2, <32 x i16> %t0 %t2 = select <32 x i1> %t1, <32 x i16> %x2, <32 x i16> %t0
%t3 = icmp ugt <32 x i16> %x3, %t2 %t3 = icmp ugt <32 x i16> %x3, %t2
%t4 = select <32 x i1> %t3, <32 x i16> %x3, <32 x i16> %t2 %t4 = select <32 x i1> %t3, <32 x i16> %x3, <32 x i16> %t2
ret <32 x i16> %t4 ret <32 x i16> %t4
} }
define <16 x i32> @reassociate_umax_v16i32(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, <16 x i32> %x3) { define <16 x i32> @reassociate_umax_v16i32(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, <16 x i32> %x3) {
; SSE-LABEL: reassociate_umax_v16i32: ; SSE-LABEL: reassociate_umax_v16i32:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movdqa %xmm7, %xmm9 ; SSE-NEXT: movdqa %xmm7, %xmm9
; SSE-NEXT: movdqa %xmm4, %xmm7 ; SSE-NEXT: movdqa %xmm4, %xmm7
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm4
; SSE-NEXT: movdqa %xmm3, %xmm8 ; SSE-NEXT: movdqa %xmm3, %xmm8
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm10 ; SSE-NEXT: movdqa {{.*#+}} xmm3 = [2147483648,2147483648,2147483648,2147483648]
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm11
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm12
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm13
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm14
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm15 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm15
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm4
; SSE-NEXT: paddd %xmm7, %xmm0
; SSE-NEXT: paddd %xmm5, %xmm1
; SSE-NEXT: paddd %xmm6, %xmm2 ; SSE-NEXT: paddd %xmm6, %xmm2
; SSE-NEXT: paddd %xmm5, %xmm1
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm14
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm13
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm12
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm11
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm10
; SSE-NEXT: paddd %xmm9, %xmm8 ; SSE-NEXT: paddd %xmm9, %xmm8
; SSE-NEXT: movdqa {{.*#+}} xmm3 = [2147483648,2147483648,2147483648,2147483648] ; SSE-NEXT: paddd %xmm7, %xmm0
; SSE-NEXT: movdqa %xmm4, %xmm6 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm7
; SSE-NEXT: pxor %xmm3, %xmm6
; SSE-NEXT: movdqa %xmm8, %xmm5 ; SSE-NEXT: movdqa %xmm8, %xmm5
; SSE-NEXT: movdqa %xmm4, %xmm6
; SSE-NEXT: pxor %xmm3, %xmm5 ; SSE-NEXT: pxor %xmm3, %xmm5
; SSE-NEXT: pxor %xmm3, %xmm6
; SSE-NEXT: pcmpgtd %xmm5, %xmm6 ; SSE-NEXT: pcmpgtd %xmm5, %xmm6
; SSE-NEXT: movdqa %xmm15, %xmm5
; SSE-NEXT: pand %xmm6, %xmm4 ; SSE-NEXT: pand %xmm6, %xmm4
; SSE-NEXT: pandn %xmm8, %xmm6 ; SSE-NEXT: pandn %xmm8, %xmm6
; SSE-NEXT: por %xmm4, %xmm6
; SSE-NEXT: movdqa %xmm15, %xmm5
; SSE-NEXT: pxor %xmm3, %xmm5 ; SSE-NEXT: pxor %xmm3, %xmm5
; SSE-NEXT: por %xmm4, %xmm6
; SSE-NEXT: movdqa %xmm2, %xmm4 ; SSE-NEXT: movdqa %xmm2, %xmm4
; SSE-NEXT: pxor %xmm3, %xmm4 ; SSE-NEXT: pxor %xmm3, %xmm4
; SSE-NEXT: pcmpgtd %xmm4, %xmm5 ; SSE-NEXT: pcmpgtd %xmm4, %xmm5
; SSE-NEXT: movdqa %xmm1, %xmm4
; SSE-NEXT: pand %xmm5, %xmm15 ; SSE-NEXT: pand %xmm5, %xmm15
; SSE-NEXT: pandn %xmm2, %xmm5 ; SSE-NEXT: pandn %xmm2, %xmm5
; SSE-NEXT: por %xmm15, %xmm5
; SSE-NEXT: movdqa %xmm14, %xmm2 ; SSE-NEXT: movdqa %xmm14, %xmm2
; SSE-NEXT: pxor %xmm3, %xmm2
; SSE-NEXT: movdqa %xmm1, %xmm4
; SSE-NEXT: pxor %xmm3, %xmm4 ; SSE-NEXT: pxor %xmm3, %xmm4
; SSE-NEXT: pxor %xmm3, %xmm2
; SSE-NEXT: por %xmm15, %xmm5
; SSE-NEXT: pcmpgtd %xmm4, %xmm2 ; SSE-NEXT: pcmpgtd %xmm4, %xmm2
; SSE-NEXT: movdqa %xmm0, %xmm4
; SSE-NEXT: pand %xmm2, %xmm14 ; SSE-NEXT: pand %xmm2, %xmm14
; SSE-NEXT: pandn %xmm1, %xmm2 ; SSE-NEXT: pandn %xmm1, %xmm2
; SSE-NEXT: por %xmm14, %xmm2
; SSE-NEXT: movdqa %xmm13, %xmm1 ; SSE-NEXT: movdqa %xmm13, %xmm1
; SSE-NEXT: pxor %xmm3, %xmm1
; SSE-NEXT: movdqa %xmm0, %xmm4
; SSE-NEXT: pxor %xmm3, %xmm4 ; SSE-NEXT: pxor %xmm3, %xmm4
; SSE-NEXT: pxor %xmm3, %xmm1
; SSE-NEXT: por %xmm14, %xmm2
; SSE-NEXT: pcmpgtd %xmm4, %xmm1 ; SSE-NEXT: pcmpgtd %xmm4, %xmm1
; SSE-NEXT: pand %xmm1, %xmm13 ; SSE-NEXT: pand %xmm1, %xmm13
; SSE-NEXT: pandn %xmm0, %xmm1 ; SSE-NEXT: pandn %xmm0, %xmm1
; SSE-NEXT: movdqa %xmm12, %xmm0
; SSE-NEXT: por %xmm13, %xmm1 ; SSE-NEXT: por %xmm13, %xmm1
; SSE-NEXT: pxor %xmm3, %xmm0
; SSE-NEXT: movdqa %xmm1, %xmm4 ; SSE-NEXT: movdqa %xmm1, %xmm4
; SSE-NEXT: pxor %xmm3, %xmm4 ; SSE-NEXT: pxor %xmm3, %xmm4
; SSE-NEXT: movdqa %xmm12, %xmm0
; SSE-NEXT: pxor %xmm3, %xmm0
; SSE-NEXT: pcmpgtd %xmm4, %xmm0 ; SSE-NEXT: pcmpgtd %xmm4, %xmm0
; SSE-NEXT: movdqa %xmm2, %xmm4
; SSE-NEXT: pand %xmm0, %xmm12 ; SSE-NEXT: pand %xmm0, %xmm12
; SSE-NEXT: pandn %xmm1, %xmm0 ; SSE-NEXT: pandn %xmm1, %xmm0
; SSE-NEXT: por %xmm12, %xmm0
; SSE-NEXT: movdqa %xmm2, %xmm4
; SSE-NEXT: pxor %xmm3, %xmm4
; SSE-NEXT: movdqa %xmm11, %xmm1 ; SSE-NEXT: movdqa %xmm11, %xmm1
; SSE-NEXT: pxor %xmm3, %xmm4
; SSE-NEXT: pxor %xmm3, %xmm1 ; SSE-NEXT: pxor %xmm3, %xmm1
; SSE-NEXT: por %xmm12, %xmm0
; SSE-NEXT: pcmpgtd %xmm4, %xmm1 ; SSE-NEXT: pcmpgtd %xmm4, %xmm1
; SSE-NEXT: movdqa %xmm5, %xmm4
; SSE-NEXT: pand %xmm1, %xmm11 ; SSE-NEXT: pand %xmm1, %xmm11
; SSE-NEXT: pandn %xmm2, %xmm1 ; SSE-NEXT: pandn %xmm2, %xmm1
; SSE-NEXT: por %xmm11, %xmm1
; SSE-NEXT: movdqa %xmm5, %xmm4
; SSE-NEXT: pxor %xmm3, %xmm4
; SSE-NEXT: movdqa %xmm10, %xmm2 ; SSE-NEXT: movdqa %xmm10, %xmm2
; SSE-NEXT: pxor %xmm3, %xmm4
; SSE-NEXT: pxor %xmm3, %xmm2 ; SSE-NEXT: pxor %xmm3, %xmm2
; SSE-NEXT: por %xmm11, %xmm1
; SSE-NEXT: pcmpgtd %xmm4, %xmm2 ; SSE-NEXT: pcmpgtd %xmm4, %xmm2
; SSE-NEXT: pand %xmm2, %xmm10
; SSE-NEXT: pandn %xmm5, %xmm2
; SSE-NEXT: por %xmm10, %xmm2
; SSE-NEXT: movdqa %xmm6, %xmm4 ; SSE-NEXT: movdqa %xmm6, %xmm4
; SSE-NEXT: pxor %xmm3, %xmm4 ; SSE-NEXT: pxor %xmm3, %xmm4
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm5 ; SSE-NEXT: pxor %xmm7, %xmm3
; SSE-NEXT: pxor %xmm5, %xmm3 ; SSE-NEXT: pand %xmm2, %xmm10
; SSE-NEXT: pandn %xmm5, %xmm2
; SSE-NEXT: pcmpgtd %xmm4, %xmm3 ; SSE-NEXT: pcmpgtd %xmm4, %xmm3
; SSE-NEXT: pand %xmm3, %xmm5 ; SSE-NEXT: por %xmm10, %xmm2
; SSE-NEXT: pand %xmm3, %xmm7
; SSE-NEXT: pandn %xmm6, %xmm3 ; SSE-NEXT: pandn %xmm6, %xmm3
; SSE-NEXT: por %xmm5, %xmm3 ; SSE-NEXT: por %xmm7, %xmm3
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX2-LABEL: reassociate_umax_v16i32: ; AVX2-LABEL: reassociate_umax_v16i32:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpaddd %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpaddd %ymm3, %ymm1, %ymm1 ; AVX2-NEXT: vpaddd %ymm3, %ymm1, %ymm1
; AVX2-NEXT: vpmaxud %ymm6, %ymm4, %ymm2 ; AVX2-NEXT: vpmaxud %ymm7, %ymm5, %ymm3
; AVX2-NEXT: vpmaxud %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpaddd %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpmaxud %ymm7, %ymm5, %ymm2 ; AVX2-NEXT: vpmaxud %ymm6, %ymm4, %ymm4
; AVX2-NEXT: vpmaxud %ymm2, %ymm1, %ymm1 ; AVX2-NEXT: vpmaxud %ymm4, %ymm0, %ymm0
; AVX2-NEXT: vpmaxud %ymm3, %ymm1, %ymm1
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: reassociate_umax_v16i32: ; AVX512-LABEL: reassociate_umax_v16i32:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vpaddd %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vpaddd %zmm1, %zmm0, %zmm0
; AVX512-NEXT: vpmaxud %zmm3, %zmm2, %zmm1 ; AVX512-NEXT: vpmaxud %zmm3, %zmm2, %zmm2
; AVX512-NEXT: vpmaxud %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vpmaxud %zmm2, %zmm0, %zmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%t0 = add <16 x i32> %x0, %x1 %t0 = add <16 x i32> %x0, %x1
%t1 = icmp ugt <16 x i32> %x2, %t0 %t1 = icmp ugt <16 x i32> %x2, %t0
%t2 = select <16 x i1> %t1, <16 x i32> %x2, <16 x i32> %t0 %t2 = select <16 x i1> %t1, <16 x i32> %x2, <16 x i32> %t0
%t3 = icmp ugt <16 x i32> %x3, %t2 %t3 = icmp ugt <16 x i32> %x3, %t2
%t4 = select <16 x i1> %t3, <16 x i32> %x3, <16 x i32> %t2 %t4 = select <16 x i1> %t3, <16 x i32> %x3, <16 x i32> %t2
ret <16 x i32> %t4 ret <16 x i32> %t4
} }
define <8 x i64> @reassociate_umax_v8i64(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, <8 x i64> %x3) { define <8 x i64> @reassociate_umax_v8i64(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, <8 x i64> %x3) {
; SSE-LABEL: reassociate_umax_v8i64: ; SSE-LABEL: reassociate_umax_v8i64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm8 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm8
; SSE-NEXT: paddq %xmm4, %xmm0 ; SSE-NEXT: paddq %xmm4, %xmm0
; SSE-NEXT: movdqa {{.*#+}} xmm4 = [9223372039002259456,9223372039002259456]
; SSE-NEXT: paddq %xmm5, %xmm1 ; SSE-NEXT: paddq %xmm5, %xmm1
; SSE-NEXT: paddq %xmm6, %xmm2
; SSE-NEXT: paddq %xmm7, %xmm3 ; SSE-NEXT: paddq %xmm7, %xmm3
; SSE-NEXT: movdqa {{.*#+}} xmm4 = [9223372039002259456,9223372039002259456] ; SSE-NEXT: paddq %xmm6, %xmm2
; SSE-NEXT: movdqa %xmm8, %xmm5
; SSE-NEXT: pxor %xmm4, %xmm5
; SSE-NEXT: movdqa %xmm3, %xmm6 ; SSE-NEXT: movdqa %xmm3, %xmm6
; SSE-NEXT: movdqa %xmm8, %xmm5
; SSE-NEXT: pxor %xmm4, %xmm6 ; SSE-NEXT: pxor %xmm4, %xmm6
; SSE-NEXT: pxor %xmm4, %xmm5
; SSE-NEXT: movdqa %xmm5, %xmm7 ; SSE-NEXT: movdqa %xmm5, %xmm7
; SSE-NEXT: pcmpgtd %xmm6, %xmm7 ; SSE-NEXT: pcmpgtd %xmm6, %xmm7
; SSE-NEXT: pcmpeqd %xmm5, %xmm6 ; SSE-NEXT: pcmpeqd %xmm5, %xmm6
; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm7[0,0,2,2] ; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm7[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm6[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm6[1,1,3,3]
; SSE-NEXT: pshufd {{.*#+}} xmm9 = xmm7[1,1,3,3]
; SSE-NEXT: pand %xmm5, %xmm6 ; SSE-NEXT: pand %xmm5, %xmm6
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm5 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm5
; SSE-NEXT: pshufd {{.*#+}} xmm9 = xmm7[1,1,3,3]
; SSE-NEXT: por %xmm6, %xmm9 ; SSE-NEXT: por %xmm6, %xmm9
; SSE-NEXT: movdqa %xmm2, %xmm6
; SSE-NEXT: pand %xmm9, %xmm8 ; SSE-NEXT: pand %xmm9, %xmm8
; SSE-NEXT: pandn %xmm3, %xmm9 ; SSE-NEXT: pandn %xmm3, %xmm9
; SSE-NEXT: pxor %xmm4, %xmm6
; SSE-NEXT: por %xmm8, %xmm9 ; SSE-NEXT: por %xmm8, %xmm9
; SSE-NEXT: movdqa %xmm5, %xmm3 ; SSE-NEXT: movdqa %xmm5, %xmm3
; SSE-NEXT: pxor %xmm4, %xmm3 ; SSE-NEXT: pxor %xmm4, %xmm3
; SSE-NEXT: movdqa %xmm2, %xmm6
; SSE-NEXT: pxor %xmm4, %xmm6
; SSE-NEXT: movdqa %xmm3, %xmm7 ; SSE-NEXT: movdqa %xmm3, %xmm7
; SSE-NEXT: pcmpgtd %xmm6, %xmm7 ; SSE-NEXT: pcmpgtd %xmm6, %xmm7
; SSE-NEXT: pcmpeqd %xmm3, %xmm6 ; SSE-NEXT: pcmpeqd %xmm3, %xmm6
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm7[0,0,2,2] ; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm7[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm6[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm6[1,1,3,3]
; SSE-NEXT: pshufd {{.*#+}} xmm8 = xmm7[1,1,3,3]
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm7
; SSE-NEXT: pand %xmm3, %xmm6 ; SSE-NEXT: pand %xmm3, %xmm6
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm3 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm3
; SSE-NEXT: pshufd {{.*#+}} xmm8 = xmm7[1,1,3,3]
; SSE-NEXT: por %xmm6, %xmm8 ; SSE-NEXT: por %xmm6, %xmm8
; SSE-NEXT: pand %xmm8, %xmm5 ; SSE-NEXT: pand %xmm8, %xmm5
; SSE-NEXT: pandn %xmm2, %xmm8 ; SSE-NEXT: pandn %xmm2, %xmm8
; SSE-NEXT: por %xmm5, %xmm8 ; SSE-NEXT: por %xmm5, %xmm8
; SSE-NEXT: movdqa %xmm3, %xmm2
; SSE-NEXT: pxor %xmm4, %xmm2
; SSE-NEXT: movdqa %xmm1, %xmm5 ; SSE-NEXT: movdqa %xmm1, %xmm5
; SSE-NEXT: pxor %xmm4, %xmm5 ; SSE-NEXT: pxor %xmm4, %xmm5
; SSE-NEXT: movdqa %xmm3, %xmm2
; SSE-NEXT: pxor %xmm4, %xmm2
; SSE-NEXT: movdqa %xmm2, %xmm6 ; SSE-NEXT: movdqa %xmm2, %xmm6
; SSE-NEXT: pcmpgtd %xmm5, %xmm6 ; SSE-NEXT: pcmpgtd %xmm5, %xmm6
; SSE-NEXT: pcmpeqd %xmm2, %xmm5 ; SSE-NEXT: pcmpeqd %xmm2, %xmm5
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm6[0,0,2,2] ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm6[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm5[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm5[1,1,3,3]
; SSE-NEXT: pand %xmm2, %xmm5 ; SSE-NEXT: pand %xmm2, %xmm5
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm7
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm6[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm6[1,1,3,3]
; SSE-NEXT: por %xmm5, %xmm2 ; SSE-NEXT: por %xmm5, %xmm2
; SSE-NEXT: pand %xmm2, %xmm3 ; SSE-NEXT: pand %xmm2, %xmm3
; SSE-NEXT: pandn %xmm1, %xmm2 ; SSE-NEXT: pandn %xmm1, %xmm2
; SSE-NEXT: por %xmm3, %xmm2
; SSE-NEXT: movdqa %xmm7, %xmm1 ; SSE-NEXT: movdqa %xmm7, %xmm1
; SSE-NEXT: pxor %xmm4, %xmm1 ; SSE-NEXT: por %xmm3, %xmm2
; SSE-NEXT: movdqa %xmm0, %xmm3 ; SSE-NEXT: movdqa %xmm0, %xmm3
; SSE-NEXT: pxor %xmm4, %xmm1
; SSE-NEXT: pxor %xmm4, %xmm3 ; SSE-NEXT: pxor %xmm4, %xmm3
; SSE-NEXT: movdqa %xmm1, %xmm5 ; SSE-NEXT: movdqa %xmm1, %xmm5
; SSE-NEXT: pcmpgtd %xmm3, %xmm5 ; SSE-NEXT: pcmpgtd %xmm3, %xmm5
; SSE-NEXT: pcmpeqd %xmm1, %xmm3 ; SSE-NEXT: pcmpeqd %xmm1, %xmm3
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm5[0,0,2,2] ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm5[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm5[1,1,3,3]
; SSE-NEXT: pand %xmm1, %xmm3 ; SSE-NEXT: pand %xmm1, %xmm3
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm1 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm1
; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm5[1,1,3,3]
; SSE-NEXT: por %xmm3, %xmm5 ; SSE-NEXT: por %xmm3, %xmm5
; SSE-NEXT: pand %xmm5, %xmm7 ; SSE-NEXT: pand %xmm5, %xmm7
; SSE-NEXT: pandn %xmm0, %xmm5 ; SSE-NEXT: pandn %xmm0, %xmm5
; SSE-NEXT: por %xmm7, %xmm5 ; SSE-NEXT: por %xmm7, %xmm5
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm7
; SSE-NEXT: movdqa %xmm5, %xmm0 ; SSE-NEXT: movdqa %xmm5, %xmm0
; SSE-NEXT: pxor %xmm4, %xmm0 ; SSE-NEXT: pxor %xmm4, %xmm0
; SSE-NEXT: movdqa %xmm1, %xmm3 ; SSE-NEXT: movdqa %xmm1, %xmm3
; SSE-NEXT: pxor %xmm4, %xmm3 ; SSE-NEXT: pxor %xmm4, %xmm3
; SSE-NEXT: movdqa %xmm3, %xmm6 ; SSE-NEXT: movdqa %xmm3, %xmm6
; SSE-NEXT: pcmpgtd %xmm0, %xmm6
; SSE-NEXT: pcmpeqd %xmm0, %xmm3 ; SSE-NEXT: pcmpeqd %xmm0, %xmm3
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm6[0,0,2,2] ; SSE-NEXT: pcmpgtd %xmm0, %xmm6
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm6[0,0,2,2]
; SSE-NEXT: pand %xmm0, %xmm3 ; SSE-NEXT: pand %xmm0, %xmm3
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm7
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm6[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm6[1,1,3,3]
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm6
; SSE-NEXT: por %xmm3, %xmm0 ; SSE-NEXT: por %xmm3, %xmm0
; SSE-NEXT: movdqa %xmm7, %xmm3
; SSE-NEXT: pand %xmm0, %xmm1 ; SSE-NEXT: pand %xmm0, %xmm1
; SSE-NEXT: pandn %xmm5, %xmm0 ; SSE-NEXT: pandn %xmm5, %xmm0
; SSE-NEXT: pxor %xmm4, %xmm3
; SSE-NEXT: por %xmm1, %xmm0 ; SSE-NEXT: por %xmm1, %xmm0
; SSE-NEXT: movdqa %xmm2, %xmm1 ; SSE-NEXT: movdqa %xmm2, %xmm1
; SSE-NEXT: pxor %xmm4, %xmm1
; SSE-NEXT: movdqa %xmm7, %xmm3
; SSE-NEXT: pxor %xmm4, %xmm3
; SSE-NEXT: movdqa %xmm3, %xmm5 ; SSE-NEXT: movdqa %xmm3, %xmm5
; SSE-NEXT: pcmpgtd %xmm1, %xmm5 ; SSE-NEXT: pxor %xmm4, %xmm1
; SSE-NEXT: pcmpeqd %xmm1, %xmm3 ; SSE-NEXT: pcmpeqd %xmm1, %xmm3
; SSE-NEXT: pcmpgtd %xmm1, %xmm5
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm5[0,0,2,2] ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm5[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
; SSE-NEXT: pand %xmm1, %xmm3 ; SSE-NEXT: pand %xmm1, %xmm3
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm6
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm5[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm5[1,1,3,3]
; SSE-NEXT: por %xmm3, %xmm1 ; SSE-NEXT: por %xmm3, %xmm1
; SSE-NEXT: movdqa %xmm6, %xmm3
; SSE-NEXT: pand %xmm1, %xmm7 ; SSE-NEXT: pand %xmm1, %xmm7
; SSE-NEXT: pandn %xmm2, %xmm1 ; SSE-NEXT: pandn %xmm2, %xmm1
; SSE-NEXT: por %xmm7, %xmm1
; SSE-NEXT: movdqa %xmm8, %xmm2 ; SSE-NEXT: movdqa %xmm8, %xmm2
; SSE-NEXT: pxor %xmm4, %xmm2
; SSE-NEXT: movdqa %xmm6, %xmm3
; SSE-NEXT: pxor %xmm4, %xmm3 ; SSE-NEXT: pxor %xmm4, %xmm3
; SSE-NEXT: por %xmm7, %xmm1
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm7
; SSE-NEXT: pxor %xmm4, %xmm2
; SSE-NEXT: movdqa %xmm3, %xmm5 ; SSE-NEXT: movdqa %xmm3, %xmm5
; SSE-NEXT: pcmpgtd %xmm2, %xmm5
; SSE-NEXT: pcmpeqd %xmm2, %xmm3 ; SSE-NEXT: pcmpeqd %xmm2, %xmm3
; SSE-NEXT: pcmpgtd %xmm2, %xmm5
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm5[0,0,2,2] ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm5[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
; SSE-NEXT: pand %xmm2, %xmm3 ; SSE-NEXT: pand %xmm2, %xmm3
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm5[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm5[1,1,3,3]
; SSE-NEXT: por %xmm3, %xmm2 ; SSE-NEXT: por %xmm3, %xmm2
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm5 ; SSE-NEXT: movdqa %xmm9, %xmm3
; SSE-NEXT: pand %xmm2, %xmm6 ; SSE-NEXT: pand %xmm2, %xmm6
; SSE-NEXT: pandn %xmm8, %xmm2 ; SSE-NEXT: pandn %xmm8, %xmm2
; SSE-NEXT: por %xmm6, %xmm2
; SSE-NEXT: movdqa %xmm9, %xmm3
; SSE-NEXT: pxor %xmm4, %xmm3 ; SSE-NEXT: pxor %xmm4, %xmm3
; SSE-NEXT: pxor %xmm5, %xmm4 ; SSE-NEXT: pxor %xmm7, %xmm4
; SSE-NEXT: por %xmm6, %xmm2
; SSE-NEXT: movdqa %xmm4, %xmm6 ; SSE-NEXT: movdqa %xmm4, %xmm6
; SSE-NEXT: pcmpgtd %xmm3, %xmm6
; SSE-NEXT: pcmpeqd %xmm3, %xmm4 ; SSE-NEXT: pcmpeqd %xmm3, %xmm4
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm6[0,0,2,2] ; SSE-NEXT: pcmpgtd %xmm3, %xmm6
; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm6[0,0,2,2]
; SSE-NEXT: pand %xmm3, %xmm4 ; SSE-NEXT: pand %xmm3, %xmm4
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm6[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm6[1,1,3,3]
; SSE-NEXT: por %xmm4, %xmm3 ; SSE-NEXT: por %xmm4, %xmm3
; SSE-NEXT: pand %xmm3, %xmm5 ; SSE-NEXT: pand %xmm3, %xmm7
; SSE-NEXT: pandn %xmm9, %xmm3 ; SSE-NEXT: pandn %xmm9, %xmm3
; SSE-NEXT: por %xmm5, %xmm3 ; SSE-NEXT: por %xmm7, %xmm3
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX2-LABEL: reassociate_umax_v8i64: ; AVX2-LABEL: reassociate_umax_v8i64:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpaddq %ymm3, %ymm1, %ymm1 ; AVX2-NEXT: vpaddq %ymm3, %ymm1, %ymm1
; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm3 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808] ; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm3 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808]
; AVX2-NEXT: vpaddq %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpxor %ymm3, %ymm5, %ymm8 ; AVX2-NEXT: vpxor %ymm3, %ymm5, %ymm8
; AVX2-NEXT: vpxor %ymm3, %ymm1, %ymm9 ; AVX2-NEXT: vpxor %ymm3, %ymm1, %ymm9
; AVX2-NEXT: vpxor %ymm3, %ymm4, %ymm2
; AVX2-NEXT: vpcmpgtq %ymm9, %ymm8, %ymm8 ; AVX2-NEXT: vpcmpgtq %ymm9, %ymm8, %ymm8
; AVX2-NEXT: vblendvpd %ymm8, %ymm5, %ymm1, %ymm1 ; AVX2-NEXT: vblendvpd %ymm8, %ymm5, %ymm1, %ymm1
; AVX2-NEXT: vpaddq %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpxor %ymm3, %ymm0, %ymm8
; AVX2-NEXT: vpxor %ymm3, %ymm4, %ymm2 ; AVX2-NEXT: vpcmpgtq %ymm8, %ymm2, %ymm2
; AVX2-NEXT: vpxor %ymm3, %ymm0, %ymm5
; AVX2-NEXT: vpcmpgtq %ymm5, %ymm2, %ymm2
; AVX2-NEXT: vblendvpd %ymm2, %ymm4, %ymm0, %ymm0 ; AVX2-NEXT: vblendvpd %ymm2, %ymm4, %ymm0, %ymm0
; AVX2-NEXT: vxorpd %ymm3, %ymm0, %ymm2
; AVX2-NEXT: vpxor %ymm3, %ymm6, %ymm4 ; AVX2-NEXT: vpxor %ymm3, %ymm6, %ymm4
; AVX2-NEXT: vxorpd %ymm3, %ymm0, %ymm2
; AVX2-NEXT: vpcmpgtq %ymm2, %ymm4, %ymm2 ; AVX2-NEXT: vpcmpgtq %ymm2, %ymm4, %ymm2
; AVX2-NEXT: vblendvpd %ymm2, %ymm6, %ymm0, %ymm0 ; AVX2-NEXT: vblendvpd %ymm2, %ymm6, %ymm0, %ymm0
; AVX2-NEXT: vxorpd %ymm3, %ymm1, %ymm2 ; AVX2-NEXT: vxorpd %ymm3, %ymm1, %ymm2
; AVX2-NEXT: vpxor %ymm3, %ymm7, %ymm3 ; AVX2-NEXT: vpxor %ymm3, %ymm7, %ymm3
; AVX2-NEXT: vpcmpgtq %ymm2, %ymm3, %ymm2 ; AVX2-NEXT: vpcmpgtq %ymm2, %ymm3, %ymm2
; AVX2-NEXT: vblendvpd %ymm2, %ymm7, %ymm1, %ymm1 ; AVX2-NEXT: vblendvpd %ymm2, %ymm7, %ymm1, %ymm1
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: reassociate_umax_v8i64: ; AVX512-LABEL: reassociate_umax_v8i64:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vpaddq %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vpaddq %zmm1, %zmm0, %zmm0
; AVX512-NEXT: vpmaxuq %zmm3, %zmm2, %zmm1 ; AVX512-NEXT: vpmaxuq %zmm3, %zmm2, %zmm2
; AVX512-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vpmaxuq %zmm2, %zmm0, %zmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%t0 = add <8 x i64> %x0, %x1 %t0 = add <8 x i64> %x0, %x1
%t1 = icmp ugt <8 x i64> %x2, %t0 %t1 = icmp ugt <8 x i64> %x2, %t0
%t2 = select <8 x i1> %t1, <8 x i64> %x2, <8 x i64> %t0 %t2 = select <8 x i1> %t1, <8 x i64> %x2, <8 x i64> %t0
%t3 = icmp ugt <8 x i64> %x3, %t2 %t3 = icmp ugt <8 x i64> %x3, %t2
%t4 = select <8 x i1> %t3, <8 x i64> %x3, <8 x i64> %t2 %t4 = select <8 x i1> %t3, <8 x i64> %x3, <8 x i64> %t2
ret <8 x i64> %t4 ret <8 x i64> %t4
} }
define <64 x i8> @reassociate_smax_v64i8(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, <64 x i8> %x3) { define <64 x i8> @reassociate_smax_v64i8(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, <64 x i8> %x3) {
; SSE-LABEL: reassociate_smax_v64i8: ; SSE-LABEL: reassociate_smax_v64i8:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm8
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm9
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm10
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm11
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm12
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm13
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm14
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm15 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm15
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm14
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm13
; SSE-NEXT: paddb %xmm4, %xmm0 ; SSE-NEXT: paddb %xmm4, %xmm0
; SSE-NEXT: paddb %xmm5, %xmm1 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm12
; SSE-NEXT: paddb %xmm6, %xmm2
; SSE-NEXT: paddb %xmm7, %xmm3 ; SSE-NEXT: paddb %xmm7, %xmm3
; SSE-NEXT: paddb %xmm6, %xmm2
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm11
; SSE-NEXT: paddb %xmm5, %xmm1
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm10
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm9
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm8
; SSE-NEXT: movdqa %xmm15, %xmm4 ; SSE-NEXT: movdqa %xmm15, %xmm4
; SSE-NEXT: pcmpgtb %xmm3, %xmm4 ; SSE-NEXT: pcmpgtb %xmm3, %xmm4
; SSE-NEXT: pand %xmm4, %xmm15 ; SSE-NEXT: pand %xmm4, %xmm15
; SSE-NEXT: pandn %xmm3, %xmm4 ; SSE-NEXT: pandn %xmm3, %xmm4
; SSE-NEXT: por %xmm15, %xmm4
; SSE-NEXT: movdqa %xmm14, %xmm3 ; SSE-NEXT: movdqa %xmm14, %xmm3
; SSE-NEXT: pcmpgtb %xmm2, %xmm3 ; SSE-NEXT: pcmpgtb %xmm2, %xmm3
; SSE-NEXT: por %xmm15, %xmm4
; SSE-NEXT: pand %xmm3, %xmm14 ; SSE-NEXT: pand %xmm3, %xmm14
; SSE-NEXT: pandn %xmm2, %xmm3 ; SSE-NEXT: pandn %xmm2, %xmm3
; SSE-NEXT: por %xmm14, %xmm3
; SSE-NEXT: movdqa %xmm13, %xmm2 ; SSE-NEXT: movdqa %xmm13, %xmm2
; SSE-NEXT: pcmpgtb %xmm1, %xmm2 ; SSE-NEXT: pcmpgtb %xmm1, %xmm2
; SSE-NEXT: por %xmm14, %xmm3
; SSE-NEXT: pand %xmm2, %xmm13 ; SSE-NEXT: pand %xmm2, %xmm13
; SSE-NEXT: pandn %xmm1, %xmm2 ; SSE-NEXT: pandn %xmm1, %xmm2
; SSE-NEXT: por %xmm13, %xmm2
; SSE-NEXT: movdqa %xmm12, %xmm1 ; SSE-NEXT: movdqa %xmm12, %xmm1
; SSE-NEXT: pcmpgtb %xmm0, %xmm1 ; SSE-NEXT: pcmpgtb %xmm0, %xmm1
; SSE-NEXT: por %xmm13, %xmm2
; SSE-NEXT: pand %xmm1, %xmm12 ; SSE-NEXT: pand %xmm1, %xmm12
; SSE-NEXT: pandn %xmm0, %xmm1 ; SSE-NEXT: pandn %xmm0, %xmm1
; SSE-NEXT: por %xmm12, %xmm1
; SSE-NEXT: movdqa %xmm11, %xmm0 ; SSE-NEXT: movdqa %xmm11, %xmm0
; SSE-NEXT: por %xmm12, %xmm1
; SSE-NEXT: pcmpgtb %xmm1, %xmm0 ; SSE-NEXT: pcmpgtb %xmm1, %xmm0
; SSE-NEXT: pand %xmm0, %xmm11 ; SSE-NEXT: pand %xmm0, %xmm11
; SSE-NEXT: pandn %xmm1, %xmm0 ; SSE-NEXT: pandn %xmm1, %xmm0
; SSE-NEXT: por %xmm11, %xmm0
; SSE-NEXT: movdqa %xmm10, %xmm1 ; SSE-NEXT: movdqa %xmm10, %xmm1
; SSE-NEXT: pcmpgtb %xmm2, %xmm1 ; SSE-NEXT: pcmpgtb %xmm2, %xmm1
; SSE-NEXT: por %xmm11, %xmm0
; SSE-NEXT: pand %xmm1, %xmm10 ; SSE-NEXT: pand %xmm1, %xmm10
; SSE-NEXT: pandn %xmm2, %xmm1 ; SSE-NEXT: pandn %xmm2, %xmm1
; SSE-NEXT: por %xmm10, %xmm1
; SSE-NEXT: movdqa %xmm9, %xmm2 ; SSE-NEXT: movdqa %xmm9, %xmm2
; SSE-NEXT: pcmpgtb %xmm3, %xmm2 ; SSE-NEXT: pcmpgtb %xmm3, %xmm2
; SSE-NEXT: por %xmm10, %xmm1
; SSE-NEXT: pand %xmm2, %xmm9 ; SSE-NEXT: pand %xmm2, %xmm9
; SSE-NEXT: pandn %xmm3, %xmm2 ; SSE-NEXT: pandn %xmm3, %xmm2
; SSE-NEXT: por %xmm9, %xmm2
; SSE-NEXT: movdqa %xmm8, %xmm3 ; SSE-NEXT: movdqa %xmm8, %xmm3
; SSE-NEXT: pcmpgtb %xmm4, %xmm3 ; SSE-NEXT: pcmpgtb %xmm4, %xmm3
; SSE-NEXT: por %xmm9, %xmm2
; SSE-NEXT: pand %xmm3, %xmm8 ; SSE-NEXT: pand %xmm3, %xmm8
; SSE-NEXT: pandn %xmm4, %xmm3 ; SSE-NEXT: pandn %xmm4, %xmm3
; SSE-NEXT: por %xmm8, %xmm3 ; SSE-NEXT: por %xmm8, %xmm3
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX2-LABEL: reassociate_smax_v64i8: ; AVX2-LABEL: reassociate_smax_v64i8:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpaddb %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpaddb %ymm3, %ymm1, %ymm1 ; AVX2-NEXT: vpaddb %ymm3, %ymm1, %ymm1
; AVX2-NEXT: vpmaxsb %ymm6, %ymm4, %ymm2 ; AVX2-NEXT: vpmaxsb %ymm7, %ymm5, %ymm3
; AVX2-NEXT: vpmaxsb %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpaddb %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpmaxsb %ymm7, %ymm5, %ymm2 ; AVX2-NEXT: vpmaxsb %ymm6, %ymm4, %ymm4
; AVX2-NEXT: vpmaxsb %ymm2, %ymm1, %ymm1 ; AVX2-NEXT: vpmaxsb %ymm4, %ymm0, %ymm0
; AVX2-NEXT: vpmaxsb %ymm3, %ymm1, %ymm1
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: reassociate_smax_v64i8: ; AVX512-LABEL: reassociate_smax_v64i8:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vpaddb %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vpaddb %zmm1, %zmm0, %zmm0
; AVX512-NEXT: vpmaxsb %zmm3, %zmm2, %zmm1 ; AVX512-NEXT: vpmaxsb %zmm3, %zmm2, %zmm2
; AVX512-NEXT: vpmaxsb %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vpmaxsb %zmm2, %zmm0, %zmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%t0 = add <64 x i8> %x0, %x1 %t0 = add <64 x i8> %x0, %x1
%t1 = icmp sgt <64 x i8> %x2, %t0 %t1 = icmp sgt <64 x i8> %x2, %t0
%t2 = select <64 x i1> %t1, <64 x i8> %x2, <64 x i8> %t0 %t2 = select <64 x i1> %t1, <64 x i8> %x2, <64 x i8> %t0
%t3 = icmp sgt <64 x i8> %x3, %t2 %t3 = icmp sgt <64 x i8> %x3, %t2
%t4 = select <64 x i1> %t3, <64 x i8> %x3, <64 x i8> %t2 %t4 = select <64 x i1> %t3, <64 x i8> %x3, <64 x i8> %t2
ret <64 x i8> %t4 ret <64 x i8> %t4
Show All 13 Lines
; SSE-NEXT: pmaxsw {{[0-9]+}}(%rsp), %xmm0 ; SSE-NEXT: pmaxsw {{[0-9]+}}(%rsp), %xmm0
; SSE-NEXT: pmaxsw {{[0-9]+}}(%rsp), %xmm1 ; SSE-NEXT: pmaxsw {{[0-9]+}}(%rsp), %xmm1
; SSE-NEXT: pmaxsw {{[0-9]+}}(%rsp), %xmm2 ; SSE-NEXT: pmaxsw {{[0-9]+}}(%rsp), %xmm2
; SSE-NEXT: pmaxsw {{[0-9]+}}(%rsp), %xmm3 ; SSE-NEXT: pmaxsw {{[0-9]+}}(%rsp), %xmm3
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX2-LABEL: reassociate_smax_v32i16: ; AVX2-LABEL: reassociate_smax_v32i16:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpaddw %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpaddw %ymm3, %ymm1, %ymm1 ; AVX2-NEXT: vpaddw %ymm3, %ymm1, %ymm1
; AVX2-NEXT: vpmaxsw %ymm6, %ymm4, %ymm2 ; AVX2-NEXT: vpmaxsw %ymm7, %ymm5, %ymm3
; AVX2-NEXT: vpmaxsw %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpaddw %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpmaxsw %ymm7, %ymm5, %ymm2 ; AVX2-NEXT: vpmaxsw %ymm6, %ymm4, %ymm4
; AVX2-NEXT: vpmaxsw %ymm2, %ymm1, %ymm1 ; AVX2-NEXT: vpmaxsw %ymm4, %ymm0, %ymm0
; AVX2-NEXT: vpmaxsw %ymm3, %ymm1, %ymm1
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: reassociate_smax_v32i16: ; AVX512-LABEL: reassociate_smax_v32i16:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vpaddw %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vpaddw %zmm1, %zmm0, %zmm0
; AVX512-NEXT: vpmaxsw %zmm3, %zmm2, %zmm1 ; AVX512-NEXT: vpmaxsw %zmm3, %zmm2, %zmm2
; AVX512-NEXT: vpmaxsw %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vpmaxsw %zmm2, %zmm0, %zmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%t0 = add <32 x i16> %x0, %x1 %t0 = add <32 x i16> %x0, %x1
%t1 = icmp sgt <32 x i16> %x2, %t0 %t1 = icmp sgt <32 x i16> %x2, %t0
%t2 = select <32 x i1> %t1, <32 x i16> %x2, <32 x i16> %t0 %t2 = select <32 x i1> %t1, <32 x i16> %x2, <32 x i16> %t0
%t3 = icmp sgt <32 x i16> %x3, %t2 %t3 = icmp sgt <32 x i16> %x3, %t2
%t4 = select <32 x i1> %t3, <32 x i16> %x3, <32 x i16> %t2 %t4 = select <32 x i1> %t3, <32 x i16> %x3, <32 x i16> %t2
ret <32 x i16> %t4 ret <32 x i16> %t4
} }
define <16 x i32> @reassociate_smax_v16i32(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, <16 x i32> %x3) { define <16 x i32> @reassociate_smax_v16i32(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, <16 x i32> %x3) {
; SSE-LABEL: reassociate_smax_v16i32: ; SSE-LABEL: reassociate_smax_v16i32:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm8
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm9
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm10
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm11
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm12
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm13
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm14
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm15 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm15
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm14
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm13
; SSE-NEXT: paddd %xmm4, %xmm0 ; SSE-NEXT: paddd %xmm4, %xmm0
; SSE-NEXT: paddd %xmm5, %xmm1 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm12
; SSE-NEXT: paddd %xmm6, %xmm2
; SSE-NEXT: paddd %xmm7, %xmm3 ; SSE-NEXT: paddd %xmm7, %xmm3
; SSE-NEXT: paddd %xmm6, %xmm2
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm11
; SSE-NEXT: paddd %xmm5, %xmm1
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm10
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm9
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm8
; SSE-NEXT: movdqa %xmm15, %xmm4 ; SSE-NEXT: movdqa %xmm15, %xmm4
; SSE-NEXT: pcmpgtd %xmm3, %xmm4 ; SSE-NEXT: pcmpgtd %xmm3, %xmm4
; SSE-NEXT: pand %xmm4, %xmm15 ; SSE-NEXT: pand %xmm4, %xmm15
; SSE-NEXT: pandn %xmm3, %xmm4 ; SSE-NEXT: pandn %xmm3, %xmm4
; SSE-NEXT: por %xmm15, %xmm4
; SSE-NEXT: movdqa %xmm14, %xmm3 ; SSE-NEXT: movdqa %xmm14, %xmm3
; SSE-NEXT: pcmpgtd %xmm2, %xmm3 ; SSE-NEXT: pcmpgtd %xmm2, %xmm3
; SSE-NEXT: por %xmm15, %xmm4
; SSE-NEXT: pand %xmm3, %xmm14 ; SSE-NEXT: pand %xmm3, %xmm14
; SSE-NEXT: pandn %xmm2, %xmm3 ; SSE-NEXT: pandn %xmm2, %xmm3
; SSE-NEXT: por %xmm14, %xmm3
; SSE-NEXT: movdqa %xmm13, %xmm2 ; SSE-NEXT: movdqa %xmm13, %xmm2
; SSE-NEXT: pcmpgtd %xmm1, %xmm2 ; SSE-NEXT: pcmpgtd %xmm1, %xmm2
; SSE-NEXT: por %xmm14, %xmm3
; SSE-NEXT: pand %xmm2, %xmm13 ; SSE-NEXT: pand %xmm2, %xmm13
; SSE-NEXT: pandn %xmm1, %xmm2 ; SSE-NEXT: pandn %xmm1, %xmm2
; SSE-NEXT: por %xmm13, %xmm2
; SSE-NEXT: movdqa %xmm12, %xmm1 ; SSE-NEXT: movdqa %xmm12, %xmm1
; SSE-NEXT: pcmpgtd %xmm0, %xmm1 ; SSE-NEXT: pcmpgtd %xmm0, %xmm1
; SSE-NEXT: por %xmm13, %xmm2
; SSE-NEXT: pand %xmm1, %xmm12 ; SSE-NEXT: pand %xmm1, %xmm12
; SSE-NEXT: pandn %xmm0, %xmm1 ; SSE-NEXT: pandn %xmm0, %xmm1
; SSE-NEXT: por %xmm12, %xmm1
; SSE-NEXT: movdqa %xmm11, %xmm0 ; SSE-NEXT: movdqa %xmm11, %xmm0
; SSE-NEXT: por %xmm12, %xmm1
; SSE-NEXT: pcmpgtd %xmm1, %xmm0 ; SSE-NEXT: pcmpgtd %xmm1, %xmm0
; SSE-NEXT: pand %xmm0, %xmm11 ; SSE-NEXT: pand %xmm0, %xmm11
; SSE-NEXT: pandn %xmm1, %xmm0 ; SSE-NEXT: pandn %xmm1, %xmm0
; SSE-NEXT: por %xmm11, %xmm0
; SSE-NEXT: movdqa %xmm10, %xmm1 ; SSE-NEXT: movdqa %xmm10, %xmm1
; SSE-NEXT: pcmpgtd %xmm2, %xmm1 ; SSE-NEXT: pcmpgtd %xmm2, %xmm1
; SSE-NEXT: por %xmm11, %xmm0
; SSE-NEXT: pand %xmm1, %xmm10 ; SSE-NEXT: pand %xmm1, %xmm10
; SSE-NEXT: pandn %xmm2, %xmm1 ; SSE-NEXT: pandn %xmm2, %xmm1
; SSE-NEXT: por %xmm10, %xmm1
; SSE-NEXT: movdqa %xmm9, %xmm2 ; SSE-NEXT: movdqa %xmm9, %xmm2
; SSE-NEXT: pcmpgtd %xmm3, %xmm2 ; SSE-NEXT: pcmpgtd %xmm3, %xmm2
; SSE-NEXT: por %xmm10, %xmm1
; SSE-NEXT: pand %xmm2, %xmm9 ; SSE-NEXT: pand %xmm2, %xmm9
; SSE-NEXT: pandn %xmm3, %xmm2 ; SSE-NEXT: pandn %xmm3, %xmm2
; SSE-NEXT: por %xmm9, %xmm2
; SSE-NEXT: movdqa %xmm8, %xmm3 ; SSE-NEXT: movdqa %xmm8, %xmm3
; SSE-NEXT: pcmpgtd %xmm4, %xmm3 ; SSE-NEXT: pcmpgtd %xmm4, %xmm3
; SSE-NEXT: por %xmm9, %xmm2
; SSE-NEXT: pand %xmm3, %xmm8 ; SSE-NEXT: pand %xmm3, %xmm8
; SSE-NEXT: pandn %xmm4, %xmm3 ; SSE-NEXT: pandn %xmm4, %xmm3
; SSE-NEXT: por %xmm8, %xmm3 ; SSE-NEXT: por %xmm8, %xmm3
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX2-LABEL: reassociate_smax_v16i32: ; AVX2-LABEL: reassociate_smax_v16i32:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpaddd %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpaddd %ymm3, %ymm1, %ymm1 ; AVX2-NEXT: vpaddd %ymm3, %ymm1, %ymm1
; AVX2-NEXT: vpmaxsd %ymm6, %ymm4, %ymm2 ; AVX2-NEXT: vpmaxsd %ymm7, %ymm5, %ymm3
; AVX2-NEXT: vpmaxsd %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpaddd %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpmaxsd %ymm7, %ymm5, %ymm2 ; AVX2-NEXT: vpmaxsd %ymm6, %ymm4, %ymm4
; AVX2-NEXT: vpmaxsd %ymm2, %ymm1, %ymm1 ; AVX2-NEXT: vpmaxsd %ymm4, %ymm0, %ymm0
; AVX2-NEXT: vpmaxsd %ymm3, %ymm1, %ymm1
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: reassociate_smax_v16i32: ; AVX512-LABEL: reassociate_smax_v16i32:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vpaddd %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vpaddd %zmm1, %zmm0, %zmm0
; AVX512-NEXT: vpmaxsd %zmm3, %zmm2, %zmm1 ; AVX512-NEXT: vpmaxsd %zmm3, %zmm2, %zmm2
; AVX512-NEXT: vpmaxsd %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vpmaxsd %zmm2, %zmm0, %zmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%t0 = add <16 x i32> %x0, %x1 %t0 = add <16 x i32> %x0, %x1
%t1 = icmp sgt <16 x i32> %x2, %t0 %t1 = icmp sgt <16 x i32> %x2, %t0
%t2 = select <16 x i1> %t1, <16 x i32> %x2, <16 x i32> %t0 %t2 = select <16 x i1> %t1, <16 x i32> %x2, <16 x i32> %t0
%t3 = icmp sgt <16 x i32> %x3, %t2 %t3 = icmp sgt <16 x i32> %x3, %t2
%t4 = select <16 x i1> %t3, <16 x i32> %x3, <16 x i32> %t2 %t4 = select <16 x i1> %t3, <16 x i32> %x3, <16 x i32> %t2
ret <16 x i32> %t4 ret <16 x i32> %t4
} }
define <8 x i64> @reassociate_smax_v8i64(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, <8 x i64> %x3) { define <8 x i64> @reassociate_smax_v8i64(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, <8 x i64> %x3) {
; SSE-LABEL: reassociate_smax_v8i64: ; SSE-LABEL: reassociate_smax_v8i64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm8 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm8
; SSE-NEXT: paddq %xmm4, %xmm0 ; SSE-NEXT: paddq %xmm4, %xmm0
; SSE-NEXT: movdqa {{.*#+}} xmm4 = [2147483648,2147483648]
; SSE-NEXT: paddq %xmm5, %xmm1 ; SSE-NEXT: paddq %xmm5, %xmm1
; SSE-NEXT: paddq %xmm6, %xmm2
; SSE-NEXT: paddq %xmm7, %xmm3 ; SSE-NEXT: paddq %xmm7, %xmm3
; SSE-NEXT: movdqa {{.*#+}} xmm4 = [2147483648,2147483648] ; SSE-NEXT: paddq %xmm6, %xmm2
; SSE-NEXT: movdqa %xmm8, %xmm5
; SSE-NEXT: pxor %xmm4, %xmm5
; SSE-NEXT: movdqa %xmm3, %xmm6 ; SSE-NEXT: movdqa %xmm3, %xmm6
; SSE-NEXT: movdqa %xmm8, %xmm5
; SSE-NEXT: pxor %xmm4, %xmm6 ; SSE-NEXT: pxor %xmm4, %xmm6
; SSE-NEXT: pxor %xmm4, %xmm5
; SSE-NEXT: movdqa %xmm5, %xmm7 ; SSE-NEXT: movdqa %xmm5, %xmm7
; SSE-NEXT: pcmpgtd %xmm6, %xmm7 ; SSE-NEXT: pcmpgtd %xmm6, %xmm7
; SSE-NEXT: pcmpeqd %xmm5, %xmm6 ; SSE-NEXT: pcmpeqd %xmm5, %xmm6
; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm7[0,0,2,2] ; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm7[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm6[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm6[1,1,3,3]
; SSE-NEXT: pshufd {{.*#+}} xmm9 = xmm7[1,1,3,3]
; SSE-NEXT: pand %xmm5, %xmm6 ; SSE-NEXT: pand %xmm5, %xmm6
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm5 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm5
; SSE-NEXT: pshufd {{.*#+}} xmm9 = xmm7[1,1,3,3]
; SSE-NEXT: por %xmm6, %xmm9 ; SSE-NEXT: por %xmm6, %xmm9
; SSE-NEXT: movdqa %xmm2, %xmm6
; SSE-NEXT: pand %xmm9, %xmm8 ; SSE-NEXT: pand %xmm9, %xmm8
; SSE-NEXT: pandn %xmm3, %xmm9 ; SSE-NEXT: pandn %xmm3, %xmm9
; SSE-NEXT: pxor %xmm4, %xmm6
; SSE-NEXT: por %xmm8, %xmm9 ; SSE-NEXT: por %xmm8, %xmm9
; SSE-NEXT: movdqa %xmm5, %xmm3 ; SSE-NEXT: movdqa %xmm5, %xmm3
; SSE-NEXT: pxor %xmm4, %xmm3 ; SSE-NEXT: pxor %xmm4, %xmm3
; SSE-NEXT: movdqa %xmm2, %xmm6
; SSE-NEXT: pxor %xmm4, %xmm6
; SSE-NEXT: movdqa %xmm3, %xmm7 ; SSE-NEXT: movdqa %xmm3, %xmm7
; SSE-NEXT: pcmpgtd %xmm6, %xmm7 ; SSE-NEXT: pcmpgtd %xmm6, %xmm7
; SSE-NEXT: pcmpeqd %xmm3, %xmm6 ; SSE-NEXT: pcmpeqd %xmm3, %xmm6
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm7[0,0,2,2] ; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm7[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm6[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm6[1,1,3,3]
; SSE-NEXT: pshufd {{.*#+}} xmm8 = xmm7[1,1,3,3]
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm7
; SSE-NEXT: pand %xmm3, %xmm6 ; SSE-NEXT: pand %xmm3, %xmm6
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm3 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm3
; SSE-NEXT: pshufd {{.*#+}} xmm8 = xmm7[1,1,3,3]
; SSE-NEXT: por %xmm6, %xmm8 ; SSE-NEXT: por %xmm6, %xmm8
; SSE-NEXT: pand %xmm8, %xmm5 ; SSE-NEXT: pand %xmm8, %xmm5
; SSE-NEXT: pandn %xmm2, %xmm8 ; SSE-NEXT: pandn %xmm2, %xmm8
; SSE-NEXT: por %xmm5, %xmm8 ; SSE-NEXT: por %xmm5, %xmm8
; SSE-NEXT: movdqa %xmm3, %xmm2
; SSE-NEXT: pxor %xmm4, %xmm2
; SSE-NEXT: movdqa %xmm1, %xmm5 ; SSE-NEXT: movdqa %xmm1, %xmm5
; SSE-NEXT: pxor %xmm4, %xmm5 ; SSE-NEXT: pxor %xmm4, %xmm5
; SSE-NEXT: movdqa %xmm3, %xmm2
; SSE-NEXT: pxor %xmm4, %xmm2
; SSE-NEXT: movdqa %xmm2, %xmm6 ; SSE-NEXT: movdqa %xmm2, %xmm6
; SSE-NEXT: pcmpgtd %xmm5, %xmm6 ; SSE-NEXT: pcmpgtd %xmm5, %xmm6
; SSE-NEXT: pcmpeqd %xmm2, %xmm5 ; SSE-NEXT: pcmpeqd %xmm2, %xmm5
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm6[0,0,2,2] ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm6[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm5[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm5[1,1,3,3]
; SSE-NEXT: pand %xmm2, %xmm5 ; SSE-NEXT: pand %xmm2, %xmm5
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm7
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm6[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm6[1,1,3,3]
; SSE-NEXT: por %xmm5, %xmm2 ; SSE-NEXT: por %xmm5, %xmm2
; SSE-NEXT: pand %xmm2, %xmm3 ; SSE-NEXT: pand %xmm2, %xmm3
; SSE-NEXT: pandn %xmm1, %xmm2 ; SSE-NEXT: pandn %xmm1, %xmm2
; SSE-NEXT: por %xmm3, %xmm2
; SSE-NEXT: movdqa %xmm7, %xmm1 ; SSE-NEXT: movdqa %xmm7, %xmm1
; SSE-NEXT: pxor %xmm4, %xmm1 ; SSE-NEXT: por %xmm3, %xmm2
; SSE-NEXT: movdqa %xmm0, %xmm3 ; SSE-NEXT: movdqa %xmm0, %xmm3
; SSE-NEXT: pxor %xmm4, %xmm1
; SSE-NEXT: pxor %xmm4, %xmm3 ; SSE-NEXT: pxor %xmm4, %xmm3
; SSE-NEXT: movdqa %xmm1, %xmm5 ; SSE-NEXT: movdqa %xmm1, %xmm5
; SSE-NEXT: pcmpgtd %xmm3, %xmm5 ; SSE-NEXT: pcmpgtd %xmm3, %xmm5
; SSE-NEXT: pcmpeqd %xmm1, %xmm3 ; SSE-NEXT: pcmpeqd %xmm1, %xmm3
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm5[0,0,2,2] ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm5[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm5[1,1,3,3]
; SSE-NEXT: pand %xmm1, %xmm3 ; SSE-NEXT: pand %xmm1, %xmm3
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm1 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm1
; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm5[1,1,3,3]
; SSE-NEXT: por %xmm3, %xmm5 ; SSE-NEXT: por %xmm3, %xmm5
; SSE-NEXT: pand %xmm5, %xmm7 ; SSE-NEXT: pand %xmm5, %xmm7
; SSE-NEXT: pandn %xmm0, %xmm5 ; SSE-NEXT: pandn %xmm0, %xmm5
; SSE-NEXT: por %xmm7, %xmm5 ; SSE-NEXT: por %xmm7, %xmm5
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm7
; SSE-NEXT: movdqa %xmm5, %xmm0 ; SSE-NEXT: movdqa %xmm5, %xmm0
; SSE-NEXT: pxor %xmm4, %xmm0 ; SSE-NEXT: pxor %xmm4, %xmm0
; SSE-NEXT: movdqa %xmm1, %xmm3 ; SSE-NEXT: movdqa %xmm1, %xmm3
; SSE-NEXT: pxor %xmm4, %xmm3 ; SSE-NEXT: pxor %xmm4, %xmm3
; SSE-NEXT: movdqa %xmm3, %xmm6 ; SSE-NEXT: movdqa %xmm3, %xmm6
; SSE-NEXT: pcmpgtd %xmm0, %xmm6
; SSE-NEXT: pcmpeqd %xmm0, %xmm3 ; SSE-NEXT: pcmpeqd %xmm0, %xmm3
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm6[0,0,2,2] ; SSE-NEXT: pcmpgtd %xmm0, %xmm6
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm6[0,0,2,2]
; SSE-NEXT: pand %xmm0, %xmm3 ; SSE-NEXT: pand %xmm0, %xmm3
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm7
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm6[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm6[1,1,3,3]
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm6
; SSE-NEXT: por %xmm3, %xmm0 ; SSE-NEXT: por %xmm3, %xmm0
; SSE-NEXT: movdqa %xmm7, %xmm3
; SSE-NEXT: pand %xmm0, %xmm1 ; SSE-NEXT: pand %xmm0, %xmm1
; SSE-NEXT: pandn %xmm5, %xmm0 ; SSE-NEXT: pandn %xmm5, %xmm0
; SSE-NEXT: pxor %xmm4, %xmm3
; SSE-NEXT: por %xmm1, %xmm0 ; SSE-NEXT: por %xmm1, %xmm0
; SSE-NEXT: movdqa %xmm2, %xmm1 ; SSE-NEXT: movdqa %xmm2, %xmm1
; SSE-NEXT: pxor %xmm4, %xmm1
; SSE-NEXT: movdqa %xmm7, %xmm3
; SSE-NEXT: pxor %xmm4, %xmm3
; SSE-NEXT: movdqa %xmm3, %xmm5 ; SSE-NEXT: movdqa %xmm3, %xmm5
; SSE-NEXT: pcmpgtd %xmm1, %xmm5 ; SSE-NEXT: pxor %xmm4, %xmm1
; SSE-NEXT: pcmpeqd %xmm1, %xmm3 ; SSE-NEXT: pcmpeqd %xmm1, %xmm3
; SSE-NEXT: pcmpgtd %xmm1, %xmm5
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm5[0,0,2,2] ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm5[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
; SSE-NEXT: pand %xmm1, %xmm3 ; SSE-NEXT: pand %xmm1, %xmm3
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm6
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm5[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm5[1,1,3,3]
; SSE-NEXT: por %xmm3, %xmm1 ; SSE-NEXT: por %xmm3, %xmm1
; SSE-NEXT: movdqa %xmm6, %xmm3
; SSE-NEXT: pand %xmm1, %xmm7 ; SSE-NEXT: pand %xmm1, %xmm7
; SSE-NEXT: pandn %xmm2, %xmm1 ; SSE-NEXT: pandn %xmm2, %xmm1
; SSE-NEXT: por %xmm7, %xmm1
; SSE-NEXT: movdqa %xmm8, %xmm2 ; SSE-NEXT: movdqa %xmm8, %xmm2
; SSE-NEXT: pxor %xmm4, %xmm2
; SSE-NEXT: movdqa %xmm6, %xmm3
; SSE-NEXT: pxor %xmm4, %xmm3 ; SSE-NEXT: pxor %xmm4, %xmm3
; SSE-NEXT: por %xmm7, %xmm1
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm7
; SSE-NEXT: pxor %xmm4, %xmm2
; SSE-NEXT: movdqa %xmm3, %xmm5 ; SSE-NEXT: movdqa %xmm3, %xmm5
; SSE-NEXT: pcmpgtd %xmm2, %xmm5
; SSE-NEXT: pcmpeqd %xmm2, %xmm3 ; SSE-NEXT: pcmpeqd %xmm2, %xmm3
; SSE-NEXT: pcmpgtd %xmm2, %xmm5
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm5[0,0,2,2] ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm5[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
; SSE-NEXT: pand %xmm2, %xmm3 ; SSE-NEXT: pand %xmm2, %xmm3
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm5[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm5[1,1,3,3]
; SSE-NEXT: por %xmm3, %xmm2 ; SSE-NEXT: por %xmm3, %xmm2
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm5 ; SSE-NEXT: movdqa %xmm9, %xmm3
; SSE-NEXT: pand %xmm2, %xmm6 ; SSE-NEXT: pand %xmm2, %xmm6
; SSE-NEXT: pandn %xmm8, %xmm2 ; SSE-NEXT: pandn %xmm8, %xmm2
; SSE-NEXT: por %xmm6, %xmm2
; SSE-NEXT: movdqa %xmm9, %xmm3
; SSE-NEXT: pxor %xmm4, %xmm3 ; SSE-NEXT: pxor %xmm4, %xmm3
; SSE-NEXT: pxor %xmm5, %xmm4 ; SSE-NEXT: pxor %xmm7, %xmm4
; SSE-NEXT: por %xmm6, %xmm2
; SSE-NEXT: movdqa %xmm4, %xmm6 ; SSE-NEXT: movdqa %xmm4, %xmm6
; SSE-NEXT: pcmpgtd %xmm3, %xmm6
; SSE-NEXT: pcmpeqd %xmm3, %xmm4 ; SSE-NEXT: pcmpeqd %xmm3, %xmm4
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm6[0,0,2,2] ; SSE-NEXT: pcmpgtd %xmm3, %xmm6
; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm6[0,0,2,2]
; SSE-NEXT: pand %xmm3, %xmm4 ; SSE-NEXT: pand %xmm3, %xmm4
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm6[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm6[1,1,3,3]
; SSE-NEXT: por %xmm4, %xmm3 ; SSE-NEXT: por %xmm4, %xmm3
; SSE-NEXT: pand %xmm3, %xmm5 ; SSE-NEXT: pand %xmm3, %xmm7
; SSE-NEXT: pandn %xmm9, %xmm3 ; SSE-NEXT: pandn %xmm9, %xmm3
; SSE-NEXT: por %xmm5, %xmm3 ; SSE-NEXT: por %xmm7, %xmm3
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX2-LABEL: reassociate_smax_v8i64: ; AVX2-LABEL: reassociate_smax_v8i64:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpaddq %ymm3, %ymm1, %ymm1 ; AVX2-NEXT: vpaddq %ymm3, %ymm1, %ymm1
; AVX2-NEXT: vpcmpgtq %ymm1, %ymm5, %ymm3
; AVX2-NEXT: vblendvpd %ymm3, %ymm5, %ymm1, %ymm1
; AVX2-NEXT: vpaddq %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpaddq %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpcmpgtq %ymm1, %ymm5, %ymm3
; AVX2-NEXT: vpcmpgtq %ymm0, %ymm4, %ymm2 ; AVX2-NEXT: vpcmpgtq %ymm0, %ymm4, %ymm2
; AVX2-NEXT: vblendvpd %ymm3, %ymm5, %ymm1, %ymm1
; AVX2-NEXT: vblendvpd %ymm2, %ymm4, %ymm0, %ymm0 ; AVX2-NEXT: vblendvpd %ymm2, %ymm4, %ymm0, %ymm0
; AVX2-NEXT: vpcmpgtq %ymm0, %ymm6, %ymm2 ; AVX2-NEXT: vpcmpgtq %ymm0, %ymm6, %ymm2
; AVX2-NEXT: vpcmpgtq %ymm1, %ymm7, %ymm3
; AVX2-NEXT: vblendvpd %ymm2, %ymm6, %ymm0, %ymm0 ; AVX2-NEXT: vblendvpd %ymm2, %ymm6, %ymm0, %ymm0
; AVX2-NEXT: vpcmpgtq %ymm1, %ymm7, %ymm2 ; AVX2-NEXT: vblendvpd %ymm3, %ymm7, %ymm1, %ymm1
; AVX2-NEXT: vblendvpd %ymm2, %ymm7, %ymm1, %ymm1
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: reassociate_smax_v8i64: ; AVX512-LABEL: reassociate_smax_v8i64:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vpaddq %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vpaddq %zmm1, %zmm0, %zmm0
; AVX512-NEXT: vpmaxsq %zmm3, %zmm2, %zmm1 ; AVX512-NEXT: vpmaxsq %zmm3, %zmm2, %zmm2
; AVX512-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vpmaxsq %zmm2, %zmm0, %zmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%t0 = add <8 x i64> %x0, %x1 %t0 = add <8 x i64> %x0, %x1
%t1 = icmp sgt <8 x i64> %x2, %t0 %t1 = icmp sgt <8 x i64> %x2, %t0
%t2 = select <8 x i1> %t1, <8 x i64> %x2, <8 x i64> %t0 %t2 = select <8 x i1> %t1, <8 x i64> %x2, <8 x i64> %t0
%t3 = icmp sgt <8 x i64> %x3, %t2 %t3 = icmp sgt <8 x i64> %x3, %t2
%t4 = select <8 x i1> %t3, <8 x i64> %x3, <8 x i64> %t2 %t4 = select <8 x i1> %t3, <8 x i64> %x3, <8 x i64> %t2
ret <8 x i64> %t4 ret <8 x i64> %t4
Show All 13 Lines
; SSE-NEXT: pminub {{[0-9]+}}(%rsp), %xmm0 ; SSE-NEXT: pminub {{[0-9]+}}(%rsp), %xmm0
; SSE-NEXT: pminub {{[0-9]+}}(%rsp), %xmm1 ; SSE-NEXT: pminub {{[0-9]+}}(%rsp), %xmm1
; SSE-NEXT: pminub {{[0-9]+}}(%rsp), %xmm2 ; SSE-NEXT: pminub {{[0-9]+}}(%rsp), %xmm2
; SSE-NEXT: pminub {{[0-9]+}}(%rsp), %xmm3 ; SSE-NEXT: pminub {{[0-9]+}}(%rsp), %xmm3
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX2-LABEL: reassociate_umin_v64i8: ; AVX2-LABEL: reassociate_umin_v64i8:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpaddb %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpaddb %ymm3, %ymm1, %ymm1 ; AVX2-NEXT: vpaddb %ymm3, %ymm1, %ymm1
; AVX2-NEXT: vpminub %ymm6, %ymm4, %ymm2 ; AVX2-NEXT: vpminub %ymm7, %ymm5, %ymm3
; AVX2-NEXT: vpminub %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpaddb %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpminub %ymm7, %ymm5, %ymm2 ; AVX2-NEXT: vpminub %ymm6, %ymm4, %ymm4
; AVX2-NEXT: vpminub %ymm2, %ymm1, %ymm1 ; AVX2-NEXT: vpminub %ymm4, %ymm0, %ymm0
; AVX2-NEXT: vpminub %ymm3, %ymm1, %ymm1
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: reassociate_umin_v64i8: ; AVX512-LABEL: reassociate_umin_v64i8:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vpaddb %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vpaddb %zmm1, %zmm0, %zmm0
; AVX512-NEXT: vpminub %zmm3, %zmm2, %zmm1 ; AVX512-NEXT: vpminub %zmm3, %zmm2, %zmm2
; AVX512-NEXT: vpminub %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vpminub %zmm2, %zmm0, %zmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%t0 = add <64 x i8> %x0, %x1 %t0 = add <64 x i8> %x0, %x1
%t1 = icmp ult <64 x i8> %x2, %t0 %t1 = icmp ult <64 x i8> %x2, %t0
%t2 = select <64 x i1> %t1, <64 x i8> %x2, <64 x i8> %t0 %t2 = select <64 x i1> %t1, <64 x i8> %x2, <64 x i8> %t0
%t3 = icmp ult <64 x i8> %x3, %t2 %t3 = icmp ult <64 x i8> %x3, %t2
%t4 = select <64 x i1> %t3, <64 x i8> %x3, <64 x i8> %t2 %t4 = select <64 x i1> %t3, <64 x i8> %x3, <64 x i8> %t2
ret <64 x i8> %t4 ret <64 x i8> %t4
} }
define <32 x i16> @reassociate_umin_v32i16(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, <32 x i16> %x3) { define <32 x i16> @reassociate_umin_v32i16(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, <32 x i16> %x3) {
; SSE-LABEL: reassociate_umin_v32i16: ; SSE-LABEL: reassociate_umin_v32i16:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: paddw %xmm4, %xmm0 ; SSE-NEXT: paddw %xmm4, %xmm0
; SSE-NEXT: paddw %xmm5, %xmm1
; SSE-NEXT: paddw %xmm6, %xmm2 ; SSE-NEXT: paddw %xmm6, %xmm2
; SSE-NEXT: paddw %xmm7, %xmm3
; SSE-NEXT: movdqa {{.*#+}} xmm4 = [32768,32768,32768,32768,32768,32768,32768,32768] ; SSE-NEXT: movdqa {{.*#+}} xmm4 = [32768,32768,32768,32768,32768,32768,32768,32768]
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm6
; SSE-NEXT: paddw %xmm7, %xmm3
; SSE-NEXT: paddw %xmm5, %xmm1
; SSE-NEXT: pxor %xmm4, %xmm3 ; SSE-NEXT: pxor %xmm4, %xmm3
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm5 ; SSE-NEXT: pxor %xmm4, %xmm6
; SSE-NEXT: pxor %xmm4, %xmm5
; SSE-NEXT: pminsw %xmm3, %xmm5
; SSE-NEXT: pxor %xmm4, %xmm2 ; SSE-NEXT: pxor %xmm4, %xmm2
; SSE-NEXT: pxor %xmm4, %xmm1
; SSE-NEXT: pxor %xmm4, %xmm0
; SSE-NEXT: pminsw %xmm3, %xmm6
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm3 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm3
; SSE-NEXT: pxor %xmm4, %xmm3 ; SSE-NEXT: pxor %xmm4, %xmm3
; SSE-NEXT: pminsw %xmm2, %xmm3 ; SSE-NEXT: pminsw %xmm2, %xmm3
; SSE-NEXT: pxor %xmm4, %xmm1
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm2 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm2
; SSE-NEXT: pxor %xmm4, %xmm2 ; SSE-NEXT: pxor %xmm4, %xmm2
; SSE-NEXT: pminsw %xmm1, %xmm2 ; SSE-NEXT: pminsw %xmm1, %xmm2
; SSE-NEXT: pxor %xmm4, %xmm0
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm1 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm1
; SSE-NEXT: pxor %xmm4, %xmm1 ; SSE-NEXT: pxor %xmm4, %xmm1
; SSE-NEXT: pminsw %xmm0, %xmm1 ; SSE-NEXT: pminsw %xmm0, %xmm1
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm0 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm0
; SSE-NEXT: pxor %xmm4, %xmm0 ; SSE-NEXT: pxor %xmm4, %xmm0
; SSE-NEXT: pminsw %xmm1, %xmm0 ; SSE-NEXT: pminsw %xmm1, %xmm0
; SSE-NEXT: pxor %xmm4, %xmm0
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm1 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm1
; SSE-NEXT: pxor %xmm4, %xmm0
; SSE-NEXT: pxor %xmm4, %xmm1 ; SSE-NEXT: pxor %xmm4, %xmm1
; SSE-NEXT: pminsw %xmm2, %xmm1 ; SSE-NEXT: pminsw %xmm2, %xmm1
; SSE-NEXT: pxor %xmm4, %xmm1
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm2 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm2
; SSE-NEXT: pxor %xmm4, %xmm1
; SSE-NEXT: pxor %xmm4, %xmm2 ; SSE-NEXT: pxor %xmm4, %xmm2
; SSE-NEXT: pminsw %xmm3, %xmm2 ; SSE-NEXT: pminsw %xmm3, %xmm2
; SSE-NEXT: pxor %xmm4, %xmm2
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm3 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm3
; SSE-NEXT: pxor %xmm4, %xmm2
; SSE-NEXT: pxor %xmm4, %xmm3 ; SSE-NEXT: pxor %xmm4, %xmm3
; SSE-NEXT: pminsw %xmm5, %xmm3 ; SSE-NEXT: pminsw %xmm6, %xmm3
; SSE-NEXT: pxor %xmm4, %xmm3 ; SSE-NEXT: pxor %xmm4, %xmm3
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX2-LABEL: reassociate_umin_v32i16: ; AVX2-LABEL: reassociate_umin_v32i16:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpaddw %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpaddw %ymm3, %ymm1, %ymm1 ; AVX2-NEXT: vpaddw %ymm3, %ymm1, %ymm1
; AVX2-NEXT: vpminuw %ymm6, %ymm4, %ymm2 ; AVX2-NEXT: vpminuw %ymm7, %ymm5, %ymm3
; AVX2-NEXT: vpminuw %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpaddw %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpminuw %ymm7, %ymm5, %ymm2 ; AVX2-NEXT: vpminuw %ymm6, %ymm4, %ymm4
; AVX2-NEXT: vpminuw %ymm2, %ymm1, %ymm1 ; AVX2-NEXT: vpminuw %ymm4, %ymm0, %ymm0
; AVX2-NEXT: vpminuw %ymm3, %ymm1, %ymm1
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: reassociate_umin_v32i16: ; AVX512-LABEL: reassociate_umin_v32i16:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vpaddw %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vpaddw %zmm1, %zmm0, %zmm0
; AVX512-NEXT: vpminuw %zmm3, %zmm2, %zmm1 ; AVX512-NEXT: vpminuw %zmm3, %zmm2, %zmm2
; AVX512-NEXT: vpminuw %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vpminuw %zmm2, %zmm0, %zmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%t0 = add <32 x i16> %x0, %x1 %t0 = add <32 x i16> %x0, %x1
%t1 = icmp ult <32 x i16> %x2, %t0 %t1 = icmp ult <32 x i16> %x2, %t0
%t2 = select <32 x i1> %t1, <32 x i16> %x2, <32 x i16> %t0 %t2 = select <32 x i1> %t1, <32 x i16> %x2, <32 x i16> %t0
%t3 = icmp ult <32 x i16> %x3, %t2 %t3 = icmp ult <32 x i16> %x3, %t2
%t4 = select <32 x i1> %t3, <32 x i16> %x3, <32 x i16> %t2 %t4 = select <32 x i1> %t3, <32 x i16> %x3, <32 x i16> %t2
ret <32 x i16> %t4 ret <32 x i16> %t4
} }
define <16 x i32> @reassociate_umin_v16i32(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, <16 x i32> %x3) { define <16 x i32> @reassociate_umin_v16i32(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, <16 x i32> %x3) {
; SSE-LABEL: reassociate_umin_v16i32: ; SSE-LABEL: reassociate_umin_v16i32:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm8
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm9
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm10
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm11
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm12
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm13
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm14
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm15 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm15
; SSE-NEXT: paddd %xmm4, %xmm0
; SSE-NEXT: paddd %xmm5, %xmm1 ; SSE-NEXT: paddd %xmm5, %xmm1
; SSE-NEXT: paddd %xmm6, %xmm2
; SSE-NEXT: paddd %xmm7, %xmm3
; SSE-NEXT: movdqa {{.*#+}} xmm5 = [2147483648,2147483648,2147483648,2147483648] ; SSE-NEXT: movdqa {{.*#+}} xmm5 = [2147483648,2147483648,2147483648,2147483648]
; SSE-NEXT: movdqa %xmm15, %xmm6 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm14
; SSE-NEXT: pxor %xmm5, %xmm6 ; SSE-NEXT: paddd %xmm7, %xmm3
; SSE-NEXT: paddd %xmm4, %xmm0
; SSE-NEXT: paddd %xmm6, %xmm2
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm13
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm12
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm11
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm10
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm9
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm8
; SSE-NEXT: movdqa %xmm3, %xmm4 ; SSE-NEXT: movdqa %xmm3, %xmm4
; SSE-NEXT: movdqa %xmm15, %xmm6
; SSE-NEXT: pxor %xmm5, %xmm4 ; SSE-NEXT: pxor %xmm5, %xmm4
; SSE-NEXT: pxor %xmm5, %xmm6
; SSE-NEXT: pcmpgtd %xmm6, %xmm4 ; SSE-NEXT: pcmpgtd %xmm6, %xmm4
; SSE-NEXT: movdqa %xmm14, %xmm6
; SSE-NEXT: pand %xmm4, %xmm15 ; SSE-NEXT: pand %xmm4, %xmm15
; SSE-NEXT: pandn %xmm3, %xmm4 ; SSE-NEXT: pandn %xmm3, %xmm4
; SSE-NEXT: por %xmm15, %xmm4
; SSE-NEXT: movdqa %xmm14, %xmm6
; SSE-NEXT: pxor %xmm5, %xmm6
; SSE-NEXT: movdqa %xmm2, %xmm3 ; SSE-NEXT: movdqa %xmm2, %xmm3
; SSE-NEXT: pxor %xmm5, %xmm6
; SSE-NEXT: pxor %xmm5, %xmm3 ; SSE-NEXT: pxor %xmm5, %xmm3
; SSE-NEXT: por %xmm15, %xmm4
; SSE-NEXT: pcmpgtd %xmm6, %xmm3 ; SSE-NEXT: pcmpgtd %xmm6, %xmm3
; SSE-NEXT: movdqa %xmm13, %xmm6
; SSE-NEXT: pand %xmm3, %xmm14 ; SSE-NEXT: pand %xmm3, %xmm14
; SSE-NEXT: pandn %xmm2, %xmm3 ; SSE-NEXT: pandn %xmm2, %xmm3
; SSE-NEXT: por %xmm14, %xmm3
; SSE-NEXT: movdqa %xmm13, %xmm6
; SSE-NEXT: pxor %xmm5, %xmm6
; SSE-NEXT: movdqa %xmm1, %xmm2 ; SSE-NEXT: movdqa %xmm1, %xmm2
; SSE-NEXT: pxor %xmm5, %xmm6
; SSE-NEXT: pxor %xmm5, %xmm2 ; SSE-NEXT: pxor %xmm5, %xmm2
; SSE-NEXT: por %xmm14, %xmm3
; SSE-NEXT: pcmpgtd %xmm6, %xmm2 ; SSE-NEXT: pcmpgtd %xmm6, %xmm2
; SSE-NEXT: movdqa %xmm0, %xmm6
; SSE-NEXT: pand %xmm2, %xmm13 ; SSE-NEXT: pand %xmm2, %xmm13
; SSE-NEXT: pandn %xmm1, %xmm2 ; SSE-NEXT: pandn %xmm1, %xmm2
; SSE-NEXT: por %xmm13, %xmm2
; SSE-NEXT: movdqa %xmm12, %xmm1 ; SSE-NEXT: movdqa %xmm12, %xmm1
; SSE-NEXT: pxor %xmm5, %xmm1
; SSE-NEXT: movdqa %xmm0, %xmm6
; SSE-NEXT: pxor %xmm5, %xmm6 ; SSE-NEXT: pxor %xmm5, %xmm6
; SSE-NEXT: pxor %xmm5, %xmm1
; SSE-NEXT: por %xmm13, %xmm2
; SSE-NEXT: pcmpgtd %xmm1, %xmm6 ; SSE-NEXT: pcmpgtd %xmm1, %xmm6
; SSE-NEXT: movdqa %xmm11, %xmm1
; SSE-NEXT: pand %xmm6, %xmm12 ; SSE-NEXT: pand %xmm6, %xmm12
; SSE-NEXT: pandn %xmm0, %xmm6 ; SSE-NEXT: pandn %xmm0, %xmm6
; SSE-NEXT: pxor %xmm5, %xmm1
; SSE-NEXT: por %xmm12, %xmm6 ; SSE-NEXT: por %xmm12, %xmm6
; SSE-NEXT: movdqa %xmm6, %xmm0 ; SSE-NEXT: movdqa %xmm6, %xmm0
; SSE-NEXT: pxor %xmm5, %xmm0 ; SSE-NEXT: pxor %xmm5, %xmm0
; SSE-NEXT: movdqa %xmm11, %xmm1
; SSE-NEXT: pxor %xmm5, %xmm1
; SSE-NEXT: pcmpgtd %xmm1, %xmm0 ; SSE-NEXT: pcmpgtd %xmm1, %xmm0
; SSE-NEXT: movdqa %xmm2, %xmm1
; SSE-NEXT: pand %xmm0, %xmm11 ; SSE-NEXT: pand %xmm0, %xmm11
; SSE-NEXT: pandn %xmm6, %xmm0 ; SSE-NEXT: pandn %xmm6, %xmm0
; SSE-NEXT: por %xmm11, %xmm0
; SSE-NEXT: movdqa %xmm2, %xmm1
; SSE-NEXT: pxor %xmm5, %xmm1
; SSE-NEXT: movdqa %xmm10, %xmm6 ; SSE-NEXT: movdqa %xmm10, %xmm6
; SSE-NEXT: pxor %xmm5, %xmm1
; SSE-NEXT: pxor %xmm5, %xmm6 ; SSE-NEXT: pxor %xmm5, %xmm6
; SSE-NEXT: por %xmm11, %xmm0
; SSE-NEXT: pcmpgtd %xmm6, %xmm1 ; SSE-NEXT: pcmpgtd %xmm6, %xmm1
; SSE-NEXT: movdqa %xmm9, %xmm6
; SSE-NEXT: pand %xmm1, %xmm10 ; SSE-NEXT: pand %xmm1, %xmm10
; SSE-NEXT: pandn %xmm2, %xmm1 ; SSE-NEXT: pandn %xmm2, %xmm1
; SSE-NEXT: por %xmm10, %xmm1
; SSE-NEXT: movdqa %xmm3, %xmm2 ; SSE-NEXT: movdqa %xmm3, %xmm2
; SSE-NEXT: pxor %xmm5, %xmm2
; SSE-NEXT: movdqa %xmm9, %xmm6
; SSE-NEXT: pxor %xmm5, %xmm6 ; SSE-NEXT: pxor %xmm5, %xmm6
; SSE-NEXT: pxor %xmm5, %xmm2
; SSE-NEXT: por %xmm10, %xmm1
; SSE-NEXT: pcmpgtd %xmm6, %xmm2 ; SSE-NEXT: pcmpgtd %xmm6, %xmm2
; SSE-NEXT: pand %xmm2, %xmm9 ; SSE-NEXT: pand %xmm2, %xmm9
; SSE-NEXT: pandn %xmm3, %xmm2 ; SSE-NEXT: pandn %xmm3, %xmm2
; SSE-NEXT: por %xmm9, %xmm2
; SSE-NEXT: movdqa %xmm4, %xmm3 ; SSE-NEXT: movdqa %xmm4, %xmm3
; SSE-NEXT: pxor %xmm5, %xmm3 ; SSE-NEXT: pxor %xmm5, %xmm3
; SSE-NEXT: pxor %xmm8, %xmm5 ; SSE-NEXT: pxor %xmm8, %xmm5
; SSE-NEXT: por %xmm9, %xmm2
; SSE-NEXT: pcmpgtd %xmm5, %xmm3 ; SSE-NEXT: pcmpgtd %xmm5, %xmm3
; SSE-NEXT: pand %xmm3, %xmm8 ; SSE-NEXT: pand %xmm3, %xmm8
; SSE-NEXT: pandn %xmm4, %xmm3 ; SSE-NEXT: pandn %xmm4, %xmm3
; SSE-NEXT: por %xmm8, %xmm3 ; SSE-NEXT: por %xmm8, %xmm3
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX2-LABEL: reassociate_umin_v16i32: ; AVX2-LABEL: reassociate_umin_v16i32:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpaddd %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpaddd %ymm3, %ymm1, %ymm1 ; AVX2-NEXT: vpaddd %ymm3, %ymm1, %ymm1
; AVX2-NEXT: vpminud %ymm6, %ymm4, %ymm2 ; AVX2-NEXT: vpminud %ymm7, %ymm5, %ymm3
; AVX2-NEXT: vpminud %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpaddd %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpminud %ymm7, %ymm5, %ymm2 ; AVX2-NEXT: vpminud %ymm6, %ymm4, %ymm4
; AVX2-NEXT: vpminud %ymm2, %ymm1, %ymm1 ; AVX2-NEXT: vpminud %ymm4, %ymm0, %ymm0
; AVX2-NEXT: vpminud %ymm3, %ymm1, %ymm1
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: reassociate_umin_v16i32: ; AVX512-LABEL: reassociate_umin_v16i32:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vpaddd %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vpaddd %zmm1, %zmm0, %zmm0
; AVX512-NEXT: vpminud %zmm3, %zmm2, %zmm1 ; AVX512-NEXT: vpminud %zmm3, %zmm2, %zmm2
; AVX512-NEXT: vpminud %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vpminud %zmm2, %zmm0, %zmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%t0 = add <16 x i32> %x0, %x1 %t0 = add <16 x i32> %x0, %x1
%t1 = icmp ult <16 x i32> %x2, %t0 %t1 = icmp ult <16 x i32> %x2, %t0
%t2 = select <16 x i1> %t1, <16 x i32> %x2, <16 x i32> %t0 %t2 = select <16 x i1> %t1, <16 x i32> %x2, <16 x i32> %t0
%t3 = icmp ult <16 x i32> %x3, %t2 %t3 = icmp ult <16 x i32> %x3, %t2
%t4 = select <16 x i1> %t3, <16 x i32> %x3, <16 x i32> %t2 %t4 = select <16 x i1> %t3, <16 x i32> %x3, <16 x i32> %t2
ret <16 x i32> %t4 ret <16 x i32> %t4
} }
define <8 x i64> @reassociate_umin_v8i64(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, <8 x i64> %x3) { define <8 x i64> @reassociate_umin_v8i64(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, <8 x i64> %x3) {
; SSE-LABEL: reassociate_umin_v8i64: ; SSE-LABEL: reassociate_umin_v8i64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm8
; SSE-NEXT: paddq %xmm4, %xmm0 ; SSE-NEXT: paddq %xmm4, %xmm0
; SSE-NEXT: paddq %xmm5, %xmm1 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm8
; SSE-NEXT: paddq %xmm6, %xmm2
; SSE-NEXT: paddq %xmm7, %xmm3
; SSE-NEXT: movdqa {{.*#+}} xmm4 = [9223372039002259456,9223372039002259456] ; SSE-NEXT: movdqa {{.*#+}} xmm4 = [9223372039002259456,9223372039002259456]
; SSE-NEXT: movdqa %xmm8, %xmm5 ; SSE-NEXT: paddq %xmm7, %xmm3
; SSE-NEXT: pxor %xmm4, %xmm5 ; SSE-NEXT: paddq %xmm6, %xmm2
; SSE-NEXT: paddq %xmm5, %xmm1
; SSE-NEXT: movdqa %xmm3, %xmm6 ; SSE-NEXT: movdqa %xmm3, %xmm6
; SSE-NEXT: movdqa %xmm8, %xmm5
; SSE-NEXT: pxor %xmm4, %xmm6 ; SSE-NEXT: pxor %xmm4, %xmm6
; SSE-NEXT: pxor %xmm4, %xmm5
; SSE-NEXT: movdqa %xmm6, %xmm7 ; SSE-NEXT: movdqa %xmm6, %xmm7
; SSE-NEXT: pcmpgtd %xmm5, %xmm7
; SSE-NEXT: pcmpeqd %xmm5, %xmm6 ; SSE-NEXT: pcmpeqd %xmm5, %xmm6
; SSE-NEXT: pcmpgtd %xmm5, %xmm7
; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm7[0,0,2,2] ; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm7[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm6[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm6[1,1,3,3]
; SSE-NEXT: pshufd {{.*#+}} xmm9 = xmm7[1,1,3,3]
; SSE-NEXT: pand %xmm5, %xmm6 ; SSE-NEXT: pand %xmm5, %xmm6
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm5 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm5
; SSE-NEXT: pshufd {{.*#+}} xmm9 = xmm7[1,1,3,3]
; SSE-NEXT: por %xmm6, %xmm9 ; SSE-NEXT: por %xmm6, %xmm9
; SSE-NEXT: movdqa %xmm2, %xmm6
; SSE-NEXT: pand %xmm9, %xmm8 ; SSE-NEXT: pand %xmm9, %xmm8
; SSE-NEXT: pandn %xmm3, %xmm9 ; SSE-NEXT: pandn %xmm3, %xmm9
; SSE-NEXT: pxor %xmm4, %xmm6
; SSE-NEXT: movdqa %xmm6, %xmm7
; SSE-NEXT: por %xmm8, %xmm9 ; SSE-NEXT: por %xmm8, %xmm9
; SSE-NEXT: movdqa %xmm5, %xmm3 ; SSE-NEXT: movdqa %xmm5, %xmm3
; SSE-NEXT: pxor %xmm4, %xmm3 ; SSE-NEXT: pxor %xmm4, %xmm3
; SSE-NEXT: movdqa %xmm2, %xmm6
; SSE-NEXT: pxor %xmm4, %xmm6
; SSE-NEXT: movdqa %xmm6, %xmm7
; SSE-NEXT: pcmpgtd %xmm3, %xmm7
; SSE-NEXT: pcmpeqd %xmm3, %xmm6 ; SSE-NEXT: pcmpeqd %xmm3, %xmm6
; SSE-NEXT: pcmpgtd %xmm3, %xmm7
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm7[0,0,2,2] ; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm7[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm6[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm6[1,1,3,3]
; SSE-NEXT: pshufd {{.*#+}} xmm8 = xmm7[1,1,3,3]
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm7
; SSE-NEXT: pand %xmm3, %xmm6 ; SSE-NEXT: pand %xmm3, %xmm6
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm3 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm3
; SSE-NEXT: pshufd {{.*#+}} xmm8 = xmm7[1,1,3,3]
; SSE-NEXT: por %xmm6, %xmm8 ; SSE-NEXT: por %xmm6, %xmm8
; SSE-NEXT: pand %xmm8, %xmm5 ; SSE-NEXT: pand %xmm8, %xmm5
; SSE-NEXT: pandn %xmm2, %xmm8 ; SSE-NEXT: pandn %xmm2, %xmm8
; SSE-NEXT: por %xmm5, %xmm8 ; SSE-NEXT: por %xmm5, %xmm8
; SSE-NEXT: movdqa %xmm3, %xmm2
; SSE-NEXT: pxor %xmm4, %xmm2
; SSE-NEXT: movdqa %xmm1, %xmm5 ; SSE-NEXT: movdqa %xmm1, %xmm5
; SSE-NEXT: pxor %xmm4, %xmm5 ; SSE-NEXT: pxor %xmm4, %xmm5
; SSE-NEXT: movdqa %xmm5, %xmm6 ; SSE-NEXT: movdqa %xmm5, %xmm6
; SSE-NEXT: pcmpgtd %xmm2, %xmm6 ; SSE-NEXT: movdqa %xmm3, %xmm2
; SSE-NEXT: pxor %xmm4, %xmm2
; SSE-NEXT: pcmpeqd %xmm2, %xmm5 ; SSE-NEXT: pcmpeqd %xmm2, %xmm5
; SSE-NEXT: pcmpgtd %xmm2, %xmm6
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm6[0,0,2,2] ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm6[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm5[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm5[1,1,3,3]
; SSE-NEXT: pand %xmm2, %xmm5 ; SSE-NEXT: pand %xmm2, %xmm5
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm7
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm6[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm6[1,1,3,3]
; SSE-NEXT: por %xmm5, %xmm2 ; SSE-NEXT: por %xmm5, %xmm2
; SSE-NEXT: pand %xmm2, %xmm3 ; SSE-NEXT: pand %xmm2, %xmm3
; SSE-NEXT: pandn %xmm1, %xmm2 ; SSE-NEXT: pandn %xmm1, %xmm2
; SSE-NEXT: por %xmm3, %xmm2
; SSE-NEXT: movdqa %xmm7, %xmm1 ; SSE-NEXT: movdqa %xmm7, %xmm1
; SSE-NEXT: pxor %xmm4, %xmm1 ; SSE-NEXT: por %xmm3, %xmm2
; SSE-NEXT: movdqa %xmm0, %xmm3 ; SSE-NEXT: movdqa %xmm0, %xmm3
; SSE-NEXT: pxor %xmm4, %xmm1
; SSE-NEXT: pxor %xmm4, %xmm3 ; SSE-NEXT: pxor %xmm4, %xmm3
; SSE-NEXT: movdqa %xmm3, %xmm5 ; SSE-NEXT: movdqa %xmm3, %xmm5
; SSE-NEXT: pcmpgtd %xmm1, %xmm5
; SSE-NEXT: pcmpeqd %xmm1, %xmm3 ; SSE-NEXT: pcmpeqd %xmm1, %xmm3
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm5[0,0,2,2] ; SSE-NEXT: pcmpgtd %xmm1, %xmm5
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm5[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm5[1,1,3,3]
; SSE-NEXT: pand %xmm1, %xmm3 ; SSE-NEXT: pand %xmm1, %xmm3
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm1 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm1
; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm5[1,1,3,3]
; SSE-NEXT: por %xmm3, %xmm5 ; SSE-NEXT: por %xmm3, %xmm5
; SSE-NEXT: pand %xmm5, %xmm7 ; SSE-NEXT: pand %xmm5, %xmm7
; SSE-NEXT: pandn %xmm0, %xmm5 ; SSE-NEXT: pandn %xmm0, %xmm5
; SSE-NEXT: por %xmm7, %xmm5 ; SSE-NEXT: por %xmm7, %xmm5
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm7
; SSE-NEXT: movdqa %xmm5, %xmm0 ; SSE-NEXT: movdqa %xmm5, %xmm0
; SSE-NEXT: pxor %xmm4, %xmm0 ; SSE-NEXT: pxor %xmm4, %xmm0
; SSE-NEXT: movdqa %xmm1, %xmm3 ; SSE-NEXT: movdqa %xmm1, %xmm3
; SSE-NEXT: pxor %xmm4, %xmm3
; SSE-NEXT: movdqa %xmm0, %xmm6 ; SSE-NEXT: movdqa %xmm0, %xmm6
; SSE-NEXT: pxor %xmm4, %xmm3
; SSE-NEXT: pcmpgtd %xmm3, %xmm6 ; SSE-NEXT: pcmpgtd %xmm3, %xmm6
; SSE-NEXT: pcmpeqd %xmm0, %xmm3 ; SSE-NEXT: pcmpeqd %xmm0, %xmm3
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm6[0,0,2,2] ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm6[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
; SSE-NEXT: pand %xmm0, %xmm3 ; SSE-NEXT: pand %xmm0, %xmm3
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm7
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm6[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm6[1,1,3,3]
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm6
; SSE-NEXT: por %xmm3, %xmm0 ; SSE-NEXT: por %xmm3, %xmm0
; SSE-NEXT: movdqa %xmm7, %xmm3
; SSE-NEXT: pand %xmm0, %xmm1 ; SSE-NEXT: pand %xmm0, %xmm1
; SSE-NEXT: pandn %xmm5, %xmm0 ; SSE-NEXT: pandn %xmm5, %xmm0
; SSE-NEXT: pxor %xmm4, %xmm3
; SSE-NEXT: por %xmm1, %xmm0 ; SSE-NEXT: por %xmm1, %xmm0
; SSE-NEXT: movdqa %xmm2, %xmm1 ; SSE-NEXT: movdqa %xmm2, %xmm1
; SSE-NEXT: pxor %xmm4, %xmm1 ; SSE-NEXT: pxor %xmm4, %xmm1
; SSE-NEXT: movdqa %xmm7, %xmm3
; SSE-NEXT: pxor %xmm4, %xmm3
; SSE-NEXT: movdqa %xmm1, %xmm5 ; SSE-NEXT: movdqa %xmm1, %xmm5
; SSE-NEXT: pcmpgtd %xmm3, %xmm5 ; SSE-NEXT: pcmpgtd %xmm3, %xmm5
; SSE-NEXT: pcmpeqd %xmm1, %xmm3 ; SSE-NEXT: pcmpeqd %xmm1, %xmm3
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm5[0,0,2,2] ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm5[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
; SSE-NEXT: pand %xmm1, %xmm3 ; SSE-NEXT: pand %xmm1, %xmm3
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm6
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm5[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm5[1,1,3,3]
; SSE-NEXT: por %xmm3, %xmm1 ; SSE-NEXT: por %xmm3, %xmm1
; SSE-NEXT: movdqa %xmm6, %xmm3
; SSE-NEXT: pand %xmm1, %xmm7 ; SSE-NEXT: pand %xmm1, %xmm7
; SSE-NEXT: pandn %xmm2, %xmm1 ; SSE-NEXT: pandn %xmm2, %xmm1
; SSE-NEXT: por %xmm7, %xmm1
; SSE-NEXT: movdqa %xmm8, %xmm2 ; SSE-NEXT: movdqa %xmm8, %xmm2
; SSE-NEXT: pxor %xmm4, %xmm2
; SSE-NEXT: movdqa %xmm6, %xmm3
; SSE-NEXT: pxor %xmm4, %xmm3 ; SSE-NEXT: pxor %xmm4, %xmm3
; SSE-NEXT: pxor %xmm4, %xmm2
; SSE-NEXT: por %xmm7, %xmm1
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm7
; SSE-NEXT: movdqa %xmm2, %xmm5 ; SSE-NEXT: movdqa %xmm2, %xmm5
; SSE-NEXT: pcmpgtd %xmm3, %xmm5 ; SSE-NEXT: pcmpgtd %xmm3, %xmm5
; SSE-NEXT: pcmpeqd %xmm2, %xmm3 ; SSE-NEXT: pcmpeqd %xmm2, %xmm3
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm5[0,0,2,2] ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm5[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
; SSE-NEXT: pand %xmm2, %xmm3 ; SSE-NEXT: pand %xmm2, %xmm3
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm5[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm5[1,1,3,3]
; SSE-NEXT: por %xmm3, %xmm2 ; SSE-NEXT: por %xmm3, %xmm2
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm5 ; SSE-NEXT: movdqa %xmm9, %xmm3
; SSE-NEXT: pand %xmm2, %xmm6 ; SSE-NEXT: pand %xmm2, %xmm6
; SSE-NEXT: pandn %xmm8, %xmm2 ; SSE-NEXT: pandn %xmm8, %xmm2
; SSE-NEXT: por %xmm6, %xmm2
; SSE-NEXT: movdqa %xmm9, %xmm3
; SSE-NEXT: pxor %xmm4, %xmm3 ; SSE-NEXT: pxor %xmm4, %xmm3
; SSE-NEXT: pxor %xmm5, %xmm4 ; SSE-NEXT: pxor %xmm7, %xmm4
; SSE-NEXT: por %xmm6, %xmm2
; SSE-NEXT: movdqa %xmm3, %xmm6 ; SSE-NEXT: movdqa %xmm3, %xmm6
; SSE-NEXT: pcmpgtd %xmm4, %xmm6 ; SSE-NEXT: pcmpgtd %xmm4, %xmm6
; SSE-NEXT: pcmpeqd %xmm3, %xmm4 ; SSE-NEXT: pcmpeqd %xmm3, %xmm4
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm6[0,0,2,2] ; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm6[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
; SSE-NEXT: pand %xmm3, %xmm4 ; SSE-NEXT: pand %xmm3, %xmm4
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm6[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm6[1,1,3,3]
; SSE-NEXT: por %xmm4, %xmm3 ; SSE-NEXT: por %xmm4, %xmm3
; SSE-NEXT: pand %xmm3, %xmm5 ; SSE-NEXT: pand %xmm3, %xmm7
; SSE-NEXT: pandn %xmm9, %xmm3 ; SSE-NEXT: pandn %xmm9, %xmm3
; SSE-NEXT: por %xmm5, %xmm3 ; SSE-NEXT: por %xmm7, %xmm3
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX2-LABEL: reassociate_umin_v8i64: ; AVX2-LABEL: reassociate_umin_v8i64:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpaddq %ymm3, %ymm1, %ymm1 ; AVX2-NEXT: vpaddq %ymm3, %ymm1, %ymm1
; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm3 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808] ; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm3 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808]
; AVX2-NEXT: vpaddq %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpxor %ymm3, %ymm5, %ymm8 ; AVX2-NEXT: vpxor %ymm3, %ymm5, %ymm8
; AVX2-NEXT: vpxor %ymm3, %ymm1, %ymm9 ; AVX2-NEXT: vpxor %ymm3, %ymm1, %ymm9
; AVX2-NEXT: vpxor %ymm3, %ymm4, %ymm2
; AVX2-NEXT: vpcmpgtq %ymm8, %ymm9, %ymm8 ; AVX2-NEXT: vpcmpgtq %ymm8, %ymm9, %ymm8
; AVX2-NEXT: vblendvpd %ymm8, %ymm5, %ymm1, %ymm1 ; AVX2-NEXT: vblendvpd %ymm8, %ymm5, %ymm1, %ymm1
; AVX2-NEXT: vpaddq %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpxor %ymm3, %ymm0, %ymm8
; AVX2-NEXT: vpxor %ymm3, %ymm4, %ymm2 ; AVX2-NEXT: vpcmpgtq %ymm2, %ymm8, %ymm2
; AVX2-NEXT: vpxor %ymm3, %ymm0, %ymm5
; AVX2-NEXT: vpcmpgtq %ymm2, %ymm5, %ymm2
; AVX2-NEXT: vblendvpd %ymm2, %ymm4, %ymm0, %ymm0 ; AVX2-NEXT: vblendvpd %ymm2, %ymm4, %ymm0, %ymm0
; AVX2-NEXT: vxorpd %ymm3, %ymm0, %ymm2
; AVX2-NEXT: vpxor %ymm3, %ymm6, %ymm4 ; AVX2-NEXT: vpxor %ymm3, %ymm6, %ymm4
; AVX2-NEXT: vxorpd %ymm3, %ymm0, %ymm2
; AVX2-NEXT: vpcmpgtq %ymm4, %ymm2, %ymm2 ; AVX2-NEXT: vpcmpgtq %ymm4, %ymm2, %ymm2
; AVX2-NEXT: vblendvpd %ymm2, %ymm6, %ymm0, %ymm0 ; AVX2-NEXT: vblendvpd %ymm2, %ymm6, %ymm0, %ymm0
; AVX2-NEXT: vxorpd %ymm3, %ymm1, %ymm2 ; AVX2-NEXT: vxorpd %ymm3, %ymm1, %ymm2
; AVX2-NEXT: vpxor %ymm3, %ymm7, %ymm3 ; AVX2-NEXT: vpxor %ymm3, %ymm7, %ymm3
; AVX2-NEXT: vpcmpgtq %ymm3, %ymm2, %ymm2 ; AVX2-NEXT: vpcmpgtq %ymm3, %ymm2, %ymm2
; AVX2-NEXT: vblendvpd %ymm2, %ymm7, %ymm1, %ymm1 ; AVX2-NEXT: vblendvpd %ymm2, %ymm7, %ymm1, %ymm1
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: reassociate_umin_v8i64: ; AVX512-LABEL: reassociate_umin_v8i64:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vpaddq %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vpaddq %zmm1, %zmm0, %zmm0
; AVX512-NEXT: vpminuq %zmm3, %zmm2, %zmm1 ; AVX512-NEXT: vpminuq %zmm3, %zmm2, %zmm2
; AVX512-NEXT: vpminuq %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vpminuq %zmm2, %zmm0, %zmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%t0 = add <8 x i64> %x0, %x1 %t0 = add <8 x i64> %x0, %x1
%t1 = icmp ult <8 x i64> %x2, %t0 %t1 = icmp ult <8 x i64> %x2, %t0
%t2 = select <8 x i1> %t1, <8 x i64> %x2, <8 x i64> %t0 %t2 = select <8 x i1> %t1, <8 x i64> %x2, <8 x i64> %t0
%t3 = icmp ult <8 x i64> %x3, %t2 %t3 = icmp ult <8 x i64> %x3, %t2
%t4 = select <8 x i1> %t3, <8 x i64> %x3, <8 x i64> %t2 %t4 = select <8 x i1> %t3, <8 x i64> %x3, <8 x i64> %t2
ret <8 x i64> %t4 ret <8 x i64> %t4
} }
define <64 x i8> @reassociate_smin_v64i8(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, <64 x i8> %x3) { define <64 x i8> @reassociate_smin_v64i8(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, <64 x i8> %x3) {
; SSE-LABEL: reassociate_smin_v64i8: ; SSE-LABEL: reassociate_smin_v64i8:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm8
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm9
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm10
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm11
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm12
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm13
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm14
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm15 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm15
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm14
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm13
; SSE-NEXT: paddb %xmm7, %xmm3
; SSE-NEXT: paddb %xmm4, %xmm0 ; SSE-NEXT: paddb %xmm4, %xmm0
; SSE-NEXT: paddb %xmm5, %xmm1 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm12
; SSE-NEXT: paddb %xmm6, %xmm2 ; SSE-NEXT: paddb %xmm6, %xmm2
; SSE-NEXT: paddb %xmm7, %xmm3 ; SSE-NEXT: paddb %xmm5, %xmm1
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm11
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm10
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm9
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm8
; SSE-NEXT: movdqa %xmm3, %xmm4 ; SSE-NEXT: movdqa %xmm3, %xmm4
; SSE-NEXT: pcmpgtb %xmm15, %xmm4 ; SSE-NEXT: pcmpgtb %xmm15, %xmm4
; SSE-NEXT: pand %xmm4, %xmm15 ; SSE-NEXT: pand %xmm4, %xmm15
; SSE-NEXT: pandn %xmm3, %xmm4 ; SSE-NEXT: pandn %xmm3, %xmm4
; SSE-NEXT: por %xmm15, %xmm4
; SSE-NEXT: movdqa %xmm2, %xmm3 ; SSE-NEXT: movdqa %xmm2, %xmm3
; SSE-NEXT: pcmpgtb %xmm14, %xmm3 ; SSE-NEXT: pcmpgtb %xmm14, %xmm3
; SSE-NEXT: por %xmm15, %xmm4
; SSE-NEXT: pand %xmm3, %xmm14 ; SSE-NEXT: pand %xmm3, %xmm14
; SSE-NEXT: pandn %xmm2, %xmm3 ; SSE-NEXT: pandn %xmm2, %xmm3
; SSE-NEXT: por %xmm14, %xmm3
; SSE-NEXT: movdqa %xmm1, %xmm2 ; SSE-NEXT: movdqa %xmm1, %xmm2
; SSE-NEXT: pcmpgtb %xmm13, %xmm2 ; SSE-NEXT: pcmpgtb %xmm13, %xmm2
; SSE-NEXT: por %xmm14, %xmm3
; SSE-NEXT: pand %xmm2, %xmm13 ; SSE-NEXT: pand %xmm2, %xmm13
; SSE-NEXT: pandn %xmm1, %xmm2 ; SSE-NEXT: pandn %xmm1, %xmm2
; SSE-NEXT: por %xmm13, %xmm2
; SSE-NEXT: movdqa %xmm0, %xmm1 ; SSE-NEXT: movdqa %xmm0, %xmm1
; SSE-NEXT: pcmpgtb %xmm12, %xmm1 ; SSE-NEXT: pcmpgtb %xmm12, %xmm1
; SSE-NEXT: por %xmm13, %xmm2
; SSE-NEXT: pand %xmm1, %xmm12 ; SSE-NEXT: pand %xmm1, %xmm12
; SSE-NEXT: pandn %xmm0, %xmm1 ; SSE-NEXT: pandn %xmm0, %xmm1
; SSE-NEXT: por %xmm12, %xmm1 ; SSE-NEXT: por %xmm12, %xmm1
; SSE-NEXT: movdqa %xmm1, %xmm0 ; SSE-NEXT: movdqa %xmm1, %xmm0
; SSE-NEXT: pcmpgtb %xmm11, %xmm0 ; SSE-NEXT: pcmpgtb %xmm11, %xmm0
; SSE-NEXT: pand %xmm0, %xmm11 ; SSE-NEXT: pand %xmm0, %xmm11
; SSE-NEXT: pandn %xmm1, %xmm0 ; SSE-NEXT: pandn %xmm1, %xmm0
; SSE-NEXT: por %xmm11, %xmm0
; SSE-NEXT: movdqa %xmm2, %xmm1 ; SSE-NEXT: movdqa %xmm2, %xmm1
; SSE-NEXT: pcmpgtb %xmm10, %xmm1 ; SSE-NEXT: pcmpgtb %xmm10, %xmm1
; SSE-NEXT: por %xmm11, %xmm0
; SSE-NEXT: pand %xmm1, %xmm10 ; SSE-NEXT: pand %xmm1, %xmm10
; SSE-NEXT: pandn %xmm2, %xmm1 ; SSE-NEXT: pandn %xmm2, %xmm1
; SSE-NEXT: por %xmm10, %xmm1
; SSE-NEXT: movdqa %xmm3, %xmm2 ; SSE-NEXT: movdqa %xmm3, %xmm2
; SSE-NEXT: pcmpgtb %xmm9, %xmm2 ; SSE-NEXT: pcmpgtb %xmm9, %xmm2
; SSE-NEXT: por %xmm10, %xmm1
; SSE-NEXT: pand %xmm2, %xmm9 ; SSE-NEXT: pand %xmm2, %xmm9
; SSE-NEXT: pandn %xmm3, %xmm2 ; SSE-NEXT: pandn %xmm3, %xmm2
; SSE-NEXT: por %xmm9, %xmm2
; SSE-NEXT: movdqa %xmm4, %xmm3 ; SSE-NEXT: movdqa %xmm4, %xmm3
; SSE-NEXT: pcmpgtb %xmm8, %xmm3 ; SSE-NEXT: pcmpgtb %xmm8, %xmm3
; SSE-NEXT: por %xmm9, %xmm2
; SSE-NEXT: pand %xmm3, %xmm8 ; SSE-NEXT: pand %xmm3, %xmm8
; SSE-NEXT: pandn %xmm4, %xmm3 ; SSE-NEXT: pandn %xmm4, %xmm3
; SSE-NEXT: por %xmm8, %xmm3 ; SSE-NEXT: por %xmm8, %xmm3
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX2-LABEL: reassociate_smin_v64i8: ; AVX2-LABEL: reassociate_smin_v64i8:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpaddb %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpaddb %ymm3, %ymm1, %ymm1 ; AVX2-NEXT: vpaddb %ymm3, %ymm1, %ymm1
; AVX2-NEXT: vpminsb %ymm6, %ymm4, %ymm2 ; AVX2-NEXT: vpminsb %ymm7, %ymm5, %ymm3
; AVX2-NEXT: vpminsb %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpaddb %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpminsb %ymm7, %ymm5, %ymm2 ; AVX2-NEXT: vpminsb %ymm6, %ymm4, %ymm4
; AVX2-NEXT: vpminsb %ymm2, %ymm1, %ymm1 ; AVX2-NEXT: vpminsb %ymm4, %ymm0, %ymm0
; AVX2-NEXT: vpminsb %ymm3, %ymm1, %ymm1
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: reassociate_smin_v64i8: ; AVX512-LABEL: reassociate_smin_v64i8:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vpaddb %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vpaddb %zmm1, %zmm0, %zmm0
; AVX512-NEXT: vpminsb %zmm3, %zmm2, %zmm1 ; AVX512-NEXT: vpminsb %zmm3, %zmm2, %zmm2
; AVX512-NEXT: vpminsb %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vpminsb %zmm2, %zmm0, %zmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%t0 = add <64 x i8> %x0, %x1 %t0 = add <64 x i8> %x0, %x1
%t1 = icmp slt <64 x i8> %x2, %t0 %t1 = icmp slt <64 x i8> %x2, %t0
%t2 = select <64 x i1> %t1, <64 x i8> %x2, <64 x i8> %t0 %t2 = select <64 x i1> %t1, <64 x i8> %x2, <64 x i8> %t0
%t3 = icmp slt <64 x i8> %x3, %t2 %t3 = icmp slt <64 x i8> %x3, %t2
%t4 = select <64 x i1> %t3, <64 x i8> %x3, <64 x i8> %t2 %t4 = select <64 x i1> %t3, <64 x i8> %x3, <64 x i8> %t2
ret <64 x i8> %t4 ret <64 x i8> %t4
Show All 13 Lines
; SSE-NEXT: pminsw {{[0-9]+}}(%rsp), %xmm0 ; SSE-NEXT: pminsw {{[0-9]+}}(%rsp), %xmm0
; SSE-NEXT: pminsw {{[0-9]+}}(%rsp), %xmm1 ; SSE-NEXT: pminsw {{[0-9]+}}(%rsp), %xmm1
; SSE-NEXT: pminsw {{[0-9]+}}(%rsp), %xmm2 ; SSE-NEXT: pminsw {{[0-9]+}}(%rsp), %xmm2
; SSE-NEXT: pminsw {{[0-9]+}}(%rsp), %xmm3 ; SSE-NEXT: pminsw {{[0-9]+}}(%rsp), %xmm3
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX2-LABEL: reassociate_smin_v32i16: ; AVX2-LABEL: reassociate_smin_v32i16:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpaddw %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpaddw %ymm3, %ymm1, %ymm1 ; AVX2-NEXT: vpaddw %ymm3, %ymm1, %ymm1
; AVX2-NEXT: vpminsw %ymm6, %ymm4, %ymm2 ; AVX2-NEXT: vpminsw %ymm7, %ymm5, %ymm3
; AVX2-NEXT: vpminsw %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpaddw %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpminsw %ymm7, %ymm5, %ymm2 ; AVX2-NEXT: vpminsw %ymm6, %ymm4, %ymm4
; AVX2-NEXT: vpminsw %ymm2, %ymm1, %ymm1 ; AVX2-NEXT: vpminsw %ymm4, %ymm0, %ymm0
; AVX2-NEXT: vpminsw %ymm3, %ymm1, %ymm1
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: reassociate_smin_v32i16: ; AVX512-LABEL: reassociate_smin_v32i16:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vpaddw %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vpaddw %zmm1, %zmm0, %zmm0
; AVX512-NEXT: vpminsw %zmm3, %zmm2, %zmm1 ; AVX512-NEXT: vpminsw %zmm3, %zmm2, %zmm2
; AVX512-NEXT: vpminsw %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vpminsw %zmm2, %zmm0, %zmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%t0 = add <32 x i16> %x0, %x1 %t0 = add <32 x i16> %x0, %x1
%t1 = icmp slt <32 x i16> %x2, %t0 %t1 = icmp slt <32 x i16> %x2, %t0
%t2 = select <32 x i1> %t1, <32 x i16> %x2, <32 x i16> %t0 %t2 = select <32 x i1> %t1, <32 x i16> %x2, <32 x i16> %t0
%t3 = icmp slt <32 x i16> %x3, %t2 %t3 = icmp slt <32 x i16> %x3, %t2
%t4 = select <32 x i1> %t3, <32 x i16> %x3, <32 x i16> %t2 %t4 = select <32 x i1> %t3, <32 x i16> %x3, <32 x i16> %t2
ret <32 x i16> %t4 ret <32 x i16> %t4
} }
define <16 x i32> @reassociate_smin_v16i32(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, <16 x i32> %x3) { define <16 x i32> @reassociate_smin_v16i32(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, <16 x i32> %x3) {
; SSE-LABEL: reassociate_smin_v16i32: ; SSE-LABEL: reassociate_smin_v16i32:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm8
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm9
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm10
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm11
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm12
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm13
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm14
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm15 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm15
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm14
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm13
; SSE-NEXT: paddd %xmm7, %xmm3
; SSE-NEXT: paddd %xmm4, %xmm0 ; SSE-NEXT: paddd %xmm4, %xmm0
; SSE-NEXT: paddd %xmm5, %xmm1 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm12
; SSE-NEXT: paddd %xmm6, %xmm2 ; SSE-NEXT: paddd %xmm6, %xmm2
; SSE-NEXT: paddd %xmm7, %xmm3 ; SSE-NEXT: paddd %xmm5, %xmm1
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm11
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm10
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm9
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm8
; SSE-NEXT: movdqa %xmm3, %xmm4 ; SSE-NEXT: movdqa %xmm3, %xmm4
; SSE-NEXT: pcmpgtd %xmm15, %xmm4 ; SSE-NEXT: pcmpgtd %xmm15, %xmm4
; SSE-NEXT: pand %xmm4, %xmm15 ; SSE-NEXT: pand %xmm4, %xmm15
; SSE-NEXT: pandn %xmm3, %xmm4 ; SSE-NEXT: pandn %xmm3, %xmm4
; SSE-NEXT: por %xmm15, %xmm4
; SSE-NEXT: movdqa %xmm2, %xmm3 ; SSE-NEXT: movdqa %xmm2, %xmm3
; SSE-NEXT: pcmpgtd %xmm14, %xmm3 ; SSE-NEXT: pcmpgtd %xmm14, %xmm3
; SSE-NEXT: por %xmm15, %xmm4
; SSE-NEXT: pand %xmm3, %xmm14 ; SSE-NEXT: pand %xmm3, %xmm14
; SSE-NEXT: pandn %xmm2, %xmm3 ; SSE-NEXT: pandn %xmm2, %xmm3
; SSE-NEXT: por %xmm14, %xmm3
; SSE-NEXT: movdqa %xmm1, %xmm2 ; SSE-NEXT: movdqa %xmm1, %xmm2
; SSE-NEXT: pcmpgtd %xmm13, %xmm2 ; SSE-NEXT: pcmpgtd %xmm13, %xmm2
; SSE-NEXT: por %xmm14, %xmm3
; SSE-NEXT: pand %xmm2, %xmm13 ; SSE-NEXT: pand %xmm2, %xmm13
; SSE-NEXT: pandn %xmm1, %xmm2 ; SSE-NEXT: pandn %xmm1, %xmm2
; SSE-NEXT: por %xmm13, %xmm2
; SSE-NEXT: movdqa %xmm0, %xmm1 ; SSE-NEXT: movdqa %xmm0, %xmm1
; SSE-NEXT: pcmpgtd %xmm12, %xmm1 ; SSE-NEXT: pcmpgtd %xmm12, %xmm1
; SSE-NEXT: por %xmm13, %xmm2
; SSE-NEXT: pand %xmm1, %xmm12 ; SSE-NEXT: pand %xmm1, %xmm12
; SSE-NEXT: pandn %xmm0, %xmm1 ; SSE-NEXT: pandn %xmm0, %xmm1
; SSE-NEXT: por %xmm12, %xmm1 ; SSE-NEXT: por %xmm12, %xmm1
; SSE-NEXT: movdqa %xmm1, %xmm0 ; SSE-NEXT: movdqa %xmm1, %xmm0
; SSE-NEXT: pcmpgtd %xmm11, %xmm0 ; SSE-NEXT: pcmpgtd %xmm11, %xmm0
; SSE-NEXT: pand %xmm0, %xmm11 ; SSE-NEXT: pand %xmm0, %xmm11
; SSE-NEXT: pandn %xmm1, %xmm0 ; SSE-NEXT: pandn %xmm1, %xmm0
; SSE-NEXT: por %xmm11, %xmm0
; SSE-NEXT: movdqa %xmm2, %xmm1 ; SSE-NEXT: movdqa %xmm2, %xmm1
; SSE-NEXT: pcmpgtd %xmm10, %xmm1 ; SSE-NEXT: pcmpgtd %xmm10, %xmm1
; SSE-NEXT: por %xmm11, %xmm0
; SSE-NEXT: pand %xmm1, %xmm10 ; SSE-NEXT: pand %xmm1, %xmm10
; SSE-NEXT: pandn %xmm2, %xmm1 ; SSE-NEXT: pandn %xmm2, %xmm1
; SSE-NEXT: por %xmm10, %xmm1
; SSE-NEXT: movdqa %xmm3, %xmm2 ; SSE-NEXT: movdqa %xmm3, %xmm2
; SSE-NEXT: pcmpgtd %xmm9, %xmm2 ; SSE-NEXT: pcmpgtd %xmm9, %xmm2
; SSE-NEXT: por %xmm10, %xmm1
; SSE-NEXT: pand %xmm2, %xmm9 ; SSE-NEXT: pand %xmm2, %xmm9
; SSE-NEXT: pandn %xmm3, %xmm2 ; SSE-NEXT: pandn %xmm3, %xmm2
; SSE-NEXT: por %xmm9, %xmm2
; SSE-NEXT: movdqa %xmm4, %xmm3 ; SSE-NEXT: movdqa %xmm4, %xmm3
; SSE-NEXT: pcmpgtd %xmm8, %xmm3 ; SSE-NEXT: pcmpgtd %xmm8, %xmm3
; SSE-NEXT: por %xmm9, %xmm2
; SSE-NEXT: pand %xmm3, %xmm8 ; SSE-NEXT: pand %xmm3, %xmm8
; SSE-NEXT: pandn %xmm4, %xmm3 ; SSE-NEXT: pandn %xmm4, %xmm3
; SSE-NEXT: por %xmm8, %xmm3 ; SSE-NEXT: por %xmm8, %xmm3
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX2-LABEL: reassociate_smin_v16i32: ; AVX2-LABEL: reassociate_smin_v16i32:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpaddd %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpaddd %ymm3, %ymm1, %ymm1 ; AVX2-NEXT: vpaddd %ymm3, %ymm1, %ymm1
; AVX2-NEXT: vpminsd %ymm6, %ymm4, %ymm2 ; AVX2-NEXT: vpminsd %ymm7, %ymm5, %ymm3
; AVX2-NEXT: vpminsd %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpaddd %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpminsd %ymm7, %ymm5, %ymm2 ; AVX2-NEXT: vpminsd %ymm6, %ymm4, %ymm4
; AVX2-NEXT: vpminsd %ymm2, %ymm1, %ymm1 ; AVX2-NEXT: vpminsd %ymm4, %ymm0, %ymm0
; AVX2-NEXT: vpminsd %ymm3, %ymm1, %ymm1
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: reassociate_smin_v16i32: ; AVX512-LABEL: reassociate_smin_v16i32:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vpaddd %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vpaddd %zmm1, %zmm0, %zmm0
; AVX512-NEXT: vpminsd %zmm3, %zmm2, %zmm1 ; AVX512-NEXT: vpminsd %zmm3, %zmm2, %zmm2
; AVX512-NEXT: vpminsd %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vpminsd %zmm2, %zmm0, %zmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%t0 = add <16 x i32> %x0, %x1 %t0 = add <16 x i32> %x0, %x1
%t1 = icmp slt <16 x i32> %x2, %t0 %t1 = icmp slt <16 x i32> %x2, %t0
%t2 = select <16 x i1> %t1, <16 x i32> %x2, <16 x i32> %t0 %t2 = select <16 x i1> %t1, <16 x i32> %x2, <16 x i32> %t0
%t3 = icmp slt <16 x i32> %x3, %t2 %t3 = icmp slt <16 x i32> %x3, %t2
%t4 = select <16 x i1> %t3, <16 x i32> %x3, <16 x i32> %t2 %t4 = select <16 x i1> %t3, <16 x i32> %x3, <16 x i32> %t2
ret <16 x i32> %t4 ret <16 x i32> %t4
} }
define <8 x i64> @reassociate_smin_v8i64(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, <8 x i64> %x3) { define <8 x i64> @reassociate_smin_v8i64(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, <8 x i64> %x3) {
; SSE-LABEL: reassociate_smin_v8i64: ; SSE-LABEL: reassociate_smin_v8i64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm8
; SSE-NEXT: paddq %xmm4, %xmm0 ; SSE-NEXT: paddq %xmm4, %xmm0
; SSE-NEXT: paddq %xmm5, %xmm1 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm8
; SSE-NEXT: paddq %xmm6, %xmm2
; SSE-NEXT: paddq %xmm7, %xmm3
; SSE-NEXT: movdqa {{.*#+}} xmm4 = [2147483648,2147483648] ; SSE-NEXT: movdqa {{.*#+}} xmm4 = [2147483648,2147483648]
; SSE-NEXT: movdqa %xmm8, %xmm5 ; SSE-NEXT: paddq %xmm7, %xmm3
; SSE-NEXT: pxor %xmm4, %xmm5 ; SSE-NEXT: paddq %xmm6, %xmm2
; SSE-NEXT: paddq %xmm5, %xmm1
; SSE-NEXT: movdqa %xmm3, %xmm6 ; SSE-NEXT: movdqa %xmm3, %xmm6
; SSE-NEXT: movdqa %xmm8, %xmm5
; SSE-NEXT: pxor %xmm4, %xmm6 ; SSE-NEXT: pxor %xmm4, %xmm6
; SSE-NEXT: pxor %xmm4, %xmm5
; SSE-NEXT: movdqa %xmm6, %xmm7 ; SSE-NEXT: movdqa %xmm6, %xmm7
; SSE-NEXT: pcmpgtd %xmm5, %xmm7
; SSE-NEXT: pcmpeqd %xmm5, %xmm6 ; SSE-NEXT: pcmpeqd %xmm5, %xmm6
; SSE-NEXT: pcmpgtd %xmm5, %xmm7
; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm7[0,0,2,2] ; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm7[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm6[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm6[1,1,3,3]
; SSE-NEXT: pshufd {{.*#+}} xmm9 = xmm7[1,1,3,3]
; SSE-NEXT: pand %xmm5, %xmm6 ; SSE-NEXT: pand %xmm5, %xmm6
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm5 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm5
; SSE-NEXT: pshufd {{.*#+}} xmm9 = xmm7[1,1,3,3]
; SSE-NEXT: por %xmm6, %xmm9 ; SSE-NEXT: por %xmm6, %xmm9
; SSE-NEXT: movdqa %xmm2, %xmm6
; SSE-NEXT: pand %xmm9, %xmm8 ; SSE-NEXT: pand %xmm9, %xmm8
; SSE-NEXT: pandn %xmm3, %xmm9 ; SSE-NEXT: pandn %xmm3, %xmm9
; SSE-NEXT: pxor %xmm4, %xmm6
; SSE-NEXT: movdqa %xmm6, %xmm7
; SSE-NEXT: por %xmm8, %xmm9 ; SSE-NEXT: por %xmm8, %xmm9
; SSE-NEXT: movdqa %xmm5, %xmm3 ; SSE-NEXT: movdqa %xmm5, %xmm3
; SSE-NEXT: pxor %xmm4, %xmm3 ; SSE-NEXT: pxor %xmm4, %xmm3
; SSE-NEXT: movdqa %xmm2, %xmm6
; SSE-NEXT: pxor %xmm4, %xmm6
; SSE-NEXT: movdqa %xmm6, %xmm7
; SSE-NEXT: pcmpgtd %xmm3, %xmm7
; SSE-NEXT: pcmpeqd %xmm3, %xmm6 ; SSE-NEXT: pcmpeqd %xmm3, %xmm6
; SSE-NEXT: pcmpgtd %xmm3, %xmm7
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm7[0,0,2,2] ; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm7[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm6[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm6[1,1,3,3]
; SSE-NEXT: pshufd {{.*#+}} xmm8 = xmm7[1,1,3,3]
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm7
; SSE-NEXT: pand %xmm3, %xmm6 ; SSE-NEXT: pand %xmm3, %xmm6
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm3 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm3
; SSE-NEXT: pshufd {{.*#+}} xmm8 = xmm7[1,1,3,3]
; SSE-NEXT: por %xmm6, %xmm8 ; SSE-NEXT: por %xmm6, %xmm8
; SSE-NEXT: pand %xmm8, %xmm5 ; SSE-NEXT: pand %xmm8, %xmm5
; SSE-NEXT: pandn %xmm2, %xmm8 ; SSE-NEXT: pandn %xmm2, %xmm8
; SSE-NEXT: por %xmm5, %xmm8 ; SSE-NEXT: por %xmm5, %xmm8
; SSE-NEXT: movdqa %xmm3, %xmm2
; SSE-NEXT: pxor %xmm4, %xmm2
; SSE-NEXT: movdqa %xmm1, %xmm5 ; SSE-NEXT: movdqa %xmm1, %xmm5
; SSE-NEXT: pxor %xmm4, %xmm5 ; SSE-NEXT: pxor %xmm4, %xmm5
; SSE-NEXT: movdqa %xmm5, %xmm6 ; SSE-NEXT: movdqa %xmm5, %xmm6
; SSE-NEXT: pcmpgtd %xmm2, %xmm6 ; SSE-NEXT: movdqa %xmm3, %xmm2
; SSE-NEXT: pxor %xmm4, %xmm2
; SSE-NEXT: pcmpeqd %xmm2, %xmm5 ; SSE-NEXT: pcmpeqd %xmm2, %xmm5
; SSE-NEXT: pcmpgtd %xmm2, %xmm6
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm6[0,0,2,2] ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm6[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm5[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm5[1,1,3,3]
; SSE-NEXT: pand %xmm2, %xmm5 ; SSE-NEXT: pand %xmm2, %xmm5
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm7
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm6[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm6[1,1,3,3]
; SSE-NEXT: por %xmm5, %xmm2 ; SSE-NEXT: por %xmm5, %xmm2
; SSE-NEXT: pand %xmm2, %xmm3 ; SSE-NEXT: pand %xmm2, %xmm3
; SSE-NEXT: pandn %xmm1, %xmm2 ; SSE-NEXT: pandn %xmm1, %xmm2
; SSE-NEXT: por %xmm3, %xmm2
; SSE-NEXT: movdqa %xmm7, %xmm1 ; SSE-NEXT: movdqa %xmm7, %xmm1
; SSE-NEXT: pxor %xmm4, %xmm1 ; SSE-NEXT: por %xmm3, %xmm2
; SSE-NEXT: movdqa %xmm0, %xmm3 ; SSE-NEXT: movdqa %xmm0, %xmm3
; SSE-NEXT: pxor %xmm4, %xmm1
; SSE-NEXT: pxor %xmm4, %xmm3 ; SSE-NEXT: pxor %xmm4, %xmm3
; SSE-NEXT: movdqa %xmm3, %xmm5 ; SSE-NEXT: movdqa %xmm3, %xmm5
; SSE-NEXT: pcmpgtd %xmm1, %xmm5
; SSE-NEXT: pcmpeqd %xmm1, %xmm3 ; SSE-NEXT: pcmpeqd %xmm1, %xmm3
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm5[0,0,2,2] ; SSE-NEXT: pcmpgtd %xmm1, %xmm5
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm5[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm5[1,1,3,3]
; SSE-NEXT: pand %xmm1, %xmm3 ; SSE-NEXT: pand %xmm1, %xmm3
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm1 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm1
; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm5[1,1,3,3]
; SSE-NEXT: por %xmm3, %xmm5 ; SSE-NEXT: por %xmm3, %xmm5
; SSE-NEXT: pand %xmm5, %xmm7 ; SSE-NEXT: pand %xmm5, %xmm7
; SSE-NEXT: pandn %xmm0, %xmm5 ; SSE-NEXT: pandn %xmm0, %xmm5
; SSE-NEXT: por %xmm7, %xmm5 ; SSE-NEXT: por %xmm7, %xmm5
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm7
; SSE-NEXT: movdqa %xmm5, %xmm0 ; SSE-NEXT: movdqa %xmm5, %xmm0
; SSE-NEXT: pxor %xmm4, %xmm0 ; SSE-NEXT: pxor %xmm4, %xmm0
; SSE-NEXT: movdqa %xmm1, %xmm3 ; SSE-NEXT: movdqa %xmm1, %xmm3
; SSE-NEXT: pxor %xmm4, %xmm3
; SSE-NEXT: movdqa %xmm0, %xmm6 ; SSE-NEXT: movdqa %xmm0, %xmm6
; SSE-NEXT: pxor %xmm4, %xmm3
; SSE-NEXT: pcmpgtd %xmm3, %xmm6 ; SSE-NEXT: pcmpgtd %xmm3, %xmm6
; SSE-NEXT: pcmpeqd %xmm0, %xmm3 ; SSE-NEXT: pcmpeqd %xmm0, %xmm3
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm6[0,0,2,2] ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm6[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
; SSE-NEXT: pand %xmm0, %xmm3 ; SSE-NEXT: pand %xmm0, %xmm3
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm7
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm6[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm6[1,1,3,3]
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm6
; SSE-NEXT: por %xmm3, %xmm0 ; SSE-NEXT: por %xmm3, %xmm0
; SSE-NEXT: movdqa %xmm7, %xmm3
; SSE-NEXT: pand %xmm0, %xmm1 ; SSE-NEXT: pand %xmm0, %xmm1
; SSE-NEXT: pandn %xmm5, %xmm0 ; SSE-NEXT: pandn %xmm5, %xmm0
; SSE-NEXT: pxor %xmm4, %xmm3
; SSE-NEXT: por %xmm1, %xmm0 ; SSE-NEXT: por %xmm1, %xmm0
; SSE-NEXT: movdqa %xmm2, %xmm1 ; SSE-NEXT: movdqa %xmm2, %xmm1
; SSE-NEXT: pxor %xmm4, %xmm1 ; SSE-NEXT: pxor %xmm4, %xmm1
; SSE-NEXT: movdqa %xmm7, %xmm3
; SSE-NEXT: pxor %xmm4, %xmm3
; SSE-NEXT: movdqa %xmm1, %xmm5 ; SSE-NEXT: movdqa %xmm1, %xmm5
; SSE-NEXT: pcmpgtd %xmm3, %xmm5 ; SSE-NEXT: pcmpgtd %xmm3, %xmm5
; SSE-NEXT: pcmpeqd %xmm1, %xmm3 ; SSE-NEXT: pcmpeqd %xmm1, %xmm3
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm5[0,0,2,2] ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm5[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
; SSE-NEXT: pand %xmm1, %xmm3 ; SSE-NEXT: pand %xmm1, %xmm3
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm6
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm5[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm5[1,1,3,3]
; SSE-NEXT: por %xmm3, %xmm1 ; SSE-NEXT: por %xmm3, %xmm1
; SSE-NEXT: movdqa %xmm6, %xmm3
; SSE-NEXT: pand %xmm1, %xmm7 ; SSE-NEXT: pand %xmm1, %xmm7
; SSE-NEXT: pandn %xmm2, %xmm1 ; SSE-NEXT: pandn %xmm2, %xmm1
; SSE-NEXT: por %xmm7, %xmm1
; SSE-NEXT: movdqa %xmm8, %xmm2 ; SSE-NEXT: movdqa %xmm8, %xmm2
; SSE-NEXT: pxor %xmm4, %xmm2
; SSE-NEXT: movdqa %xmm6, %xmm3
; SSE-NEXT: pxor %xmm4, %xmm3 ; SSE-NEXT: pxor %xmm4, %xmm3
; SSE-NEXT: pxor %xmm4, %xmm2
; SSE-NEXT: por %xmm7, %xmm1
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm7
; SSE-NEXT: movdqa %xmm2, %xmm5 ; SSE-NEXT: movdqa %xmm2, %xmm5
; SSE-NEXT: pcmpgtd %xmm3, %xmm5 ; SSE-NEXT: pcmpgtd %xmm3, %xmm5
; SSE-NEXT: pcmpeqd %xmm2, %xmm3 ; SSE-NEXT: pcmpeqd %xmm2, %xmm3
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm5[0,0,2,2] ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm5[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
; SSE-NEXT: pand %xmm2, %xmm3 ; SSE-NEXT: pand %xmm2, %xmm3
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm5[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm5[1,1,3,3]
; SSE-NEXT: por %xmm3, %xmm2 ; SSE-NEXT: por %xmm3, %xmm2
; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm5 ; SSE-NEXT: movdqa %xmm9, %xmm3
; SSE-NEXT: pand %xmm2, %xmm6 ; SSE-NEXT: pand %xmm2, %xmm6
; SSE-NEXT: pandn %xmm8, %xmm2 ; SSE-NEXT: pandn %xmm8, %xmm2
; SSE-NEXT: por %xmm6, %xmm2
; SSE-NEXT: movdqa %xmm9, %xmm3
; SSE-NEXT: pxor %xmm4, %xmm3 ; SSE-NEXT: pxor %xmm4, %xmm3
; SSE-NEXT: pxor %xmm5, %xmm4 ; SSE-NEXT: pxor %xmm7, %xmm4
; SSE-NEXT: por %xmm6, %xmm2
; SSE-NEXT: movdqa %xmm3, %xmm6 ; SSE-NEXT: movdqa %xmm3, %xmm6
; SSE-NEXT: pcmpgtd %xmm4, %xmm6 ; SSE-NEXT: pcmpgtd %xmm4, %xmm6
; SSE-NEXT: pcmpeqd %xmm3, %xmm4 ; SSE-NEXT: pcmpeqd %xmm3, %xmm4
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm6[0,0,2,2] ; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm6[0,0,2,2]
; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
; SSE-NEXT: pand %xmm3, %xmm4 ; SSE-NEXT: pand %xmm3, %xmm4
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm6[1,1,3,3] ; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm6[1,1,3,3]
; SSE-NEXT: por %xmm4, %xmm3 ; SSE-NEXT: por %xmm4, %xmm3
; SSE-NEXT: pand %xmm3, %xmm5 ; SSE-NEXT: pand %xmm3, %xmm7
; SSE-NEXT: pandn %xmm9, %xmm3 ; SSE-NEXT: pandn %xmm9, %xmm3
; SSE-NEXT: por %xmm5, %xmm3 ; SSE-NEXT: por %xmm7, %xmm3
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX2-LABEL: reassociate_smin_v8i64: ; AVX2-LABEL: reassociate_smin_v8i64:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpaddq %ymm3, %ymm1, %ymm1 ; AVX2-NEXT: vpaddq %ymm3, %ymm1, %ymm1
; AVX2-NEXT: vpcmpgtq %ymm5, %ymm1, %ymm3
; AVX2-NEXT: vblendvpd %ymm3, %ymm5, %ymm1, %ymm1
; AVX2-NEXT: vpaddq %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpaddq %ymm2, %ymm0, %ymm0
; AVX2-NEXT: vpcmpgtq %ymm5, %ymm1, %ymm3
; AVX2-NEXT: vpcmpgtq %ymm4, %ymm0, %ymm2 ; AVX2-NEXT: vpcmpgtq %ymm4, %ymm0, %ymm2
; AVX2-NEXT: vblendvpd %ymm3, %ymm5, %ymm1, %ymm1
; AVX2-NEXT: vblendvpd %ymm2, %ymm4, %ymm0, %ymm0 ; AVX2-NEXT: vblendvpd %ymm2, %ymm4, %ymm0, %ymm0
; AVX2-NEXT: vpcmpgtq %ymm6, %ymm0, %ymm2 ; AVX2-NEXT: vpcmpgtq %ymm6, %ymm0, %ymm2
; AVX2-NEXT: vpcmpgtq %ymm7, %ymm1, %ymm3
; AVX2-NEXT: vblendvpd %ymm2, %ymm6, %ymm0, %ymm0 ; AVX2-NEXT: vblendvpd %ymm2, %ymm6, %ymm0, %ymm0
; AVX2-NEXT: vpcmpgtq %ymm7, %ymm1, %ymm2 ; AVX2-NEXT: vblendvpd %ymm3, %ymm7, %ymm1, %ymm1
; AVX2-NEXT: vblendvpd %ymm2, %ymm7, %ymm1, %ymm1
; AVX2-NEXT: retq ; AVX2-NEXT: retq
; ;
; AVX512-LABEL: reassociate_smin_v8i64: ; AVX512-LABEL: reassociate_smin_v8i64:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vpaddq %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vpaddq %zmm1, %zmm0, %zmm0
; AVX512-NEXT: vpminsq %zmm3, %zmm2, %zmm1 ; AVX512-NEXT: vpminsq %zmm3, %zmm2, %zmm2
; AVX512-NEXT: vpminsq %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vpminsq %zmm2, %zmm0, %zmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%t0 = add <8 x i64> %x0, %x1 %t0 = add <8 x i64> %x0, %x1
%t1 = icmp slt <8 x i64> %x2, %t0 %t1 = icmp slt <8 x i64> %x2, %t0
%t2 = select <8 x i1> %t1, <8 x i64> %x2, <8 x i64> %t0 %t2 = select <8 x i1> %t1, <8 x i64> %x2, <8 x i64> %t0
%t3 = icmp slt <8 x i64> %x3, %t2 %t3 = icmp slt <8 x i64> %x3, %t2
%t4 = select <8 x i1> %t3, <8 x i64> %x3, <8 x i64> %t2 %t4 = select <8 x i1> %t3, <8 x i64> %x3, <8 x i64> %t2
ret <8 x i64> %t4 ret <8 x i64> %t4
} }

llvm/test/CodeGen/X86/machine-combiner-int.ll

; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -machine-combiner-verify-pattern-order=true | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -machine-combiner-verify-pattern-order=true | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -stop-after machine-combiner -machine-combiner-verify-pattern-order=true -o - | FileCheck %s --check-prefix=DEAD ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -stop-after machine-combiner -machine-combiner-verify-pattern-order=true -o - | FileCheck %s --check-prefix=DEAD
; Verify that integer multiplies are reassociated. The first multiply in ; Verify that integer multiplies are reassociated. The first multiply in
; each test should be independent of the result of the preceding add (lea). ; each test should be independent of the result of the preceding add (lea).
; TODO: This test does not actually test i16 machine instruction reassociation ; TODO: This test does not actually test i16 machine instruction reassociation
; because the operands are being promoted to i32 types. ; because the operands are being promoted to i32 types.
define i16 @reassociate_muls_i16(i16 %x0, i16 %x1, i16 %x2, i16 %x3) { define i16 @reassociate_muls_i16(i16 %x0, i16 %x1, i16 %x2, i16 %x3) {
; CHECK-LABEL: reassociate_muls_i16: ; CHECK-LABEL: reassociate_muls_i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: imull %ecx, %edx
; CHECK-NEXT: # kill ; CHECK-NEXT: # kill
; CHECK-NEXT: # kill ; CHECK-NEXT: # kill
; CHECK-NEXT: leal (%rdi,%rsi), %eax ; CHECK-NEXT: leal (%rdi,%rsi), %eax
; CHECK-NEXT: imull %ecx, %edx
; CHECK-NEXT: imull %edx, %eax ; CHECK-NEXT: imull %edx, %eax
; CHECK-NEXT: # kill ; CHECK-NEXT: # kill
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%t0 = add i16 %x0, %x1 %t0 = add i16 %x0, %x1
%t1 = mul i16 %x2, %t0 %t1 = mul i16 %x2, %t0
%t2 = mul i16 %x3, %t1 %t2 = mul i16 %x3, %t1
ret i16 %t2 ret i16 %t2
} }
define i32 @reassociate_muls_i32(i32 %x0, i32 %x1, i32 %x2, i32 %x3) { define i32 @reassociate_muls_i32(i32 %x0, i32 %x1, i32 %x2, i32 %x3) {
; CHECK-LABEL: reassociate_muls_i32: ; CHECK-LABEL: reassociate_muls_i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: imull %ecx, %edx
; CHECK-NEXT: # kill ; CHECK-NEXT: # kill
; CHECK-NEXT: # kill ; CHECK-NEXT: # kill
; CHECK-NEXT: leal (%rdi,%rsi), %eax ; CHECK-NEXT: leal (%rdi,%rsi), %eax
; CHECK-NEXT: imull %ecx, %edx
; CHECK-NEXT: imull %edx, %eax ; CHECK-NEXT: imull %edx, %eax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; DEAD: ADD32rr ; DEAD: ADD32rr
; DEAD-NEXT: IMUL32rr{{.*}}implicit-def dead $eflags ; DEAD-NEXT: IMUL32rr{{.*}}implicit-def dead $eflags
; DEAD-NEXT: IMUL32rr{{.*}}implicit-def dead $eflags ; DEAD-NEXT: IMUL32rr{{.*}}implicit-def dead $eflags
%t0 = add i32 %x0, %x1 %t0 = add i32 %x0, %x1
%t1 = mul i32 %x2, %t0 %t1 = mul i32 %x2, %t0
%t2 = mul i32 %x3, %t1 %t2 = mul i32 %x3, %t1
ret i32 %t2 ret i32 %t2
} }
define i64 @reassociate_muls_i64(i64 %x0, i64 %x1, i64 %x2, i64 %x3) { define i64 @reassociate_muls_i64(i64 %x0, i64 %x1, i64 %x2, i64 %x3) {
; CHECK-LABEL: reassociate_muls_i64: ; CHECK-LABEL: reassociate_muls_i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: leaq (%rdi,%rsi), %rax
; CHECK-NEXT: imulq %rcx, %rdx ; CHECK-NEXT: imulq %rcx, %rdx
; CHECK-NEXT: leaq (%rdi,%rsi), %rax
; CHECK-NEXT: imulq %rdx, %rax ; CHECK-NEXT: imulq %rdx, %rax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%t0 = add i64 %x0, %x1 %t0 = add i64 %x0, %x1
%t1 = mul i64 %x2, %t0 %t1 = mul i64 %x2, %t0
%t2 = mul i64 %x3, %t1 %t2 = mul i64 %x3, %t1
ret i64 %t2 ret i64 %t2
} }
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llvm/test/CodeGen/X86/machine-combiner.ll

Show All 17 Lines
; SSE-NEXT: addss %xmm1, %xmm0 ; SSE-NEXT: addss %xmm1, %xmm0
; SSE-NEXT: addss %xmm3, %xmm2 ; SSE-NEXT: addss %xmm3, %xmm2
; SSE-NEXT: addss %xmm2, %xmm0 ; SSE-NEXT: addss %xmm2, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: reassociate_adds1: ; AVX-LABEL: reassociate_adds1:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vaddss %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vaddss %xmm1, %xmm0, %xmm0
; AVX-NEXT: vaddss %xmm3, %xmm2, %xmm1 ; AVX-NEXT: vaddss %xmm3, %xmm2, %xmm2
; AVX-NEXT: vaddss %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vaddss %xmm2, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%t0 = fadd reassoc nsz float %x0, %x1 %t0 = fadd reassoc nsz float %x0, %x1
%t1 = fadd reassoc nsz float %t0, %x2 %t1 = fadd reassoc nsz float %t0, %x2
%t2 = fadd reassoc nsz float %t1, %x3 %t2 = fadd reassoc nsz float %t1, %x3
ret float %t2 ret float %t2
} }
define float @reassociate_adds2(float %x0, float %x1, float %x2, float %x3) { define float @reassociate_adds2(float %x0, float %x1, float %x2, float %x3) {
; SSE-LABEL: reassociate_adds2: ; SSE-LABEL: reassociate_adds2:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: addss %xmm1, %xmm0 ; SSE-NEXT: addss %xmm1, %xmm0
; SSE-NEXT: addss %xmm3, %xmm2 ; SSE-NEXT: addss %xmm3, %xmm2
; SSE-NEXT: addss %xmm2, %xmm0 ; SSE-NEXT: addss %xmm2, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: reassociate_adds2: ; AVX-LABEL: reassociate_adds2:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vaddss %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vaddss %xmm1, %xmm0, %xmm0
; AVX-NEXT: vaddss %xmm3, %xmm2, %xmm1 ; AVX-NEXT: vaddss %xmm3, %xmm2, %xmm2
; AVX-NEXT: vaddss %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vaddss %xmm2, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%t0 = fadd reassoc nsz float %x0, %x1 %t0 = fadd reassoc nsz float %x0, %x1
%t1 = fadd reassoc nsz float %x2, %t0 %t1 = fadd reassoc nsz float %x2, %t0
%t2 = fadd reassoc nsz float %t1, %x3 %t2 = fadd reassoc nsz float %t1, %x3
ret float %t2 ret float %t2
} }
define float @reassociate_adds3(float %x0, float %x1, float %x2, float %x3) { define float @reassociate_adds3(float %x0, float %x1, float %x2, float %x3) {
; SSE-LABEL: reassociate_adds3: ; SSE-LABEL: reassociate_adds3:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: addss %xmm1, %xmm0 ; SSE-NEXT: addss %xmm1, %xmm0
; SSE-NEXT: addss %xmm3, %xmm2 ; SSE-NEXT: addss %xmm3, %xmm2
; SSE-NEXT: addss %xmm2, %xmm0 ; SSE-NEXT: addss %xmm2, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: reassociate_adds3: ; AVX-LABEL: reassociate_adds3:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vaddss %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vaddss %xmm1, %xmm0, %xmm0
; AVX-NEXT: vaddss %xmm3, %xmm2, %xmm1 ; AVX-NEXT: vaddss %xmm3, %xmm2, %xmm2
; AVX-NEXT: vaddss %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vaddss %xmm2, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%t0 = fadd reassoc nsz float %x0, %x1 %t0 = fadd reassoc nsz float %x0, %x1
%t1 = fadd reassoc nsz float %t0, %x2 %t1 = fadd reassoc nsz float %t0, %x2
%t2 = fadd reassoc nsz float %x3, %t1 %t2 = fadd reassoc nsz float %x3, %t1
ret float %t2 ret float %t2
} }
define float @reassociate_adds4(float %x0, float %x1, float %x2, float %x3) { define float @reassociate_adds4(float %x0, float %x1, float %x2, float %x3) {
; SSE-LABEL: reassociate_adds4: ; SSE-LABEL: reassociate_adds4:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: addss %xmm1, %xmm0 ; SSE-NEXT: addss %xmm1, %xmm0
; SSE-NEXT: addss %xmm3, %xmm2 ; SSE-NEXT: addss %xmm3, %xmm2
; SSE-NEXT: addss %xmm2, %xmm0 ; SSE-NEXT: addss %xmm2, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: reassociate_adds4: ; AVX-LABEL: reassociate_adds4:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vaddss %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vaddss %xmm1, %xmm0, %xmm0
; AVX-NEXT: vaddss %xmm3, %xmm2, %xmm1 ; AVX-NEXT: vaddss %xmm3, %xmm2, %xmm2
; AVX-NEXT: vaddss %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vaddss %xmm2, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%t0 = fadd reassoc nsz float %x0, %x1 %t0 = fadd reassoc nsz float %x0, %x1
%t1 = fadd reassoc nsz float %x2, %t0 %t1 = fadd reassoc nsz float %x2, %t0
%t2 = fadd reassoc nsz float %x3, %t1 %t2 = fadd reassoc nsz float %x3, %t1
ret float %t2 ret float %t2
} }
; Verify that we reassociate some of these ops. The optimal balanced tree of adds is not ; Verify that we reassociate some of these ops. The optimal balanced tree of adds is not
; produced because that would cost more compile time. ; produced because that would cost more compile time.
define float @reassociate_adds5(float %x0, float %x1, float %x2, float %x3, float %x4, float %x5, float %x6, float %x7) { define float @reassociate_adds5(float %x0, float %x1, float %x2, float %x3, float %x4, float %x5, float %x6, float %x7) {
; SSE-LABEL: reassociate_adds5: ; SSE-LABEL: reassociate_adds5:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: addss %xmm5, %xmm4
; SSE-NEXT: addss %xmm1, %xmm0 ; SSE-NEXT: addss %xmm1, %xmm0
; SSE-NEXT: addss %xmm3, %xmm2 ; SSE-NEXT: addss %xmm3, %xmm2
; SSE-NEXT: addss %xmm2, %xmm0 ; SSE-NEXT: addss %xmm2, %xmm0
; SSE-NEXT: addss %xmm5, %xmm4
; SSE-NEXT: addss %xmm6, %xmm4 ; SSE-NEXT: addss %xmm6, %xmm4
; SSE-NEXT: addss %xmm4, %xmm0 ; SSE-NEXT: addss %xmm4, %xmm0
; SSE-NEXT: addss %xmm7, %xmm0 ; SSE-NEXT: addss %xmm7, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: reassociate_adds5: ; AVX-LABEL: reassociate_adds5:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vaddss %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vaddss %xmm1, %xmm0, %xmm0
▲ Show 20 Lines • Show All 161 Lines • ▼ Show 20 Lines; AVX512-NEXT: retq
ret <2 x double> %t2 ret <2 x double> %t2
} }
; Verify that SSE and AVX 128-bit vector single-precision multiplies are reassociated. ; Verify that SSE and AVX 128-bit vector single-precision multiplies are reassociated.
define <4 x float> @reassociate_muls_v4f32(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) { define <4 x float> @reassociate_muls_v4f32(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) {
; SSE-LABEL: reassociate_muls_v4f32: ; SSE-LABEL: reassociate_muls_v4f32:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: addps %xmm1, %xmm0
; SSE-NEXT: mulps %xmm3, %xmm2 ; SSE-NEXT: mulps %xmm3, %xmm2
; SSE-NEXT: addps %xmm1, %xmm0
; SSE-NEXT: mulps %xmm2, %xmm0 ; SSE-NEXT: mulps %xmm2, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: reassociate_muls_v4f32: ; AVX-LABEL: reassociate_muls_v4f32:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmulps %xmm3, %xmm2, %xmm2
; AVX-NEXT: vaddps %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vaddps %xmm1, %xmm0, %xmm0
; AVX-NEXT: vmulps %xmm3, %xmm2, %xmm1 ; AVX-NEXT: vmulps %xmm2, %xmm0, %xmm0
; AVX-NEXT: vmulps %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%t0 = fadd reassoc nsz <4 x float> %x0, %x1 %t0 = fadd reassoc nsz <4 x float> %x0, %x1
%t1 = fmul reassoc nsz <4 x float> %x2, %t0 %t1 = fmul reassoc nsz <4 x float> %x2, %t0
%t2 = fmul reassoc nsz <4 x float> %x3, %t1 %t2 = fmul reassoc nsz <4 x float> %x3, %t1
ret <4 x float> %t2 ret <4 x float> %t2
} }
; Verify that SSE and AVX 128-bit vector double-precision multiplies are reassociated. ; Verify that SSE and AVX 128-bit vector double-precision multiplies are reassociated.
define <2 x double> @reassociate_muls_v2f64(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, <2 x double> %x3) { define <2 x double> @reassociate_muls_v2f64(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, <2 x double> %x3) {
; SSE-LABEL: reassociate_muls_v2f64: ; SSE-LABEL: reassociate_muls_v2f64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: addpd %xmm1, %xmm0
; SSE-NEXT: mulpd %xmm3, %xmm2 ; SSE-NEXT: mulpd %xmm3, %xmm2
; SSE-NEXT: addpd %xmm1, %xmm0
; SSE-NEXT: mulpd %xmm2, %xmm0 ; SSE-NEXT: mulpd %xmm2, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: reassociate_muls_v2f64: ; AVX-LABEL: reassociate_muls_v2f64:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmulpd %xmm3, %xmm2, %xmm2
; AVX-NEXT: vaddpd %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vaddpd %xmm1, %xmm0, %xmm0
; AVX-NEXT: vmulpd %xmm3, %xmm2, %xmm1 ; AVX-NEXT: vmulpd %xmm2, %xmm0, %xmm0
; AVX-NEXT: vmulpd %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%t0 = fadd reassoc nsz <2 x double> %x0, %x1 %t0 = fadd reassoc nsz <2 x double> %x0, %x1
%t1 = fmul reassoc nsz <2 x double> %x2, %t0 %t1 = fmul reassoc nsz <2 x double> %x2, %t0
%t2 = fmul reassoc nsz <2 x double> %x3, %t1 %t2 = fmul reassoc nsz <2 x double> %x3, %t1
ret <2 x double> %t2 ret <2 x double> %t2
} }
; Verify that AVX 256-bit vector single-precision adds are reassociated. ; Verify that AVX 256-bit vector single-precision adds are reassociated.
define <8 x float> @reassociate_adds_v8f32(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, <8 x float> %x3) { define <8 x float> @reassociate_adds_v8f32(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, <8 x float> %x3) {
; SSE-LABEL: reassociate_adds_v8f32: ; SSE-LABEL: reassociate_adds_v8f32:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: mulps %xmm2, %xmm0 ; SSE-NEXT: mulps %xmm2, %xmm0
; SSE-NEXT: mulps %xmm3, %xmm1 ; SSE-NEXT: mulps %xmm3, %xmm1
; SSE-NEXT: addps %xmm6, %xmm4 ; SSE-NEXT: addps %xmm6, %xmm4
; SSE-NEXT: addps %xmm4, %xmm0
; SSE-NEXT: addps %xmm7, %xmm5 ; SSE-NEXT: addps %xmm7, %xmm5
; SSE-NEXT: addps %xmm4, %xmm0
; SSE-NEXT: addps %xmm5, %xmm1 ; SSE-NEXT: addps %xmm5, %xmm1
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: reassociate_adds_v8f32: ; AVX1-LABEL: reassociate_adds_v8f32:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vmulps %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: vmulps %ymm1, %ymm0, %ymm0
; AVX1-NEXT: vaddps %ymm3, %ymm2, %ymm1 ; AVX1-NEXT: vaddps %ymm3, %ymm2, %ymm1
; AVX1-NEXT: vaddps %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: vaddps %ymm1, %ymm0, %ymm0
Show All 13 Lines
; Verify that AVX 256-bit vector double-precision adds are reassociated. ; Verify that AVX 256-bit vector double-precision adds are reassociated.
define <4 x double> @reassociate_adds_v4f64(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, <4 x double> %x3) { define <4 x double> @reassociate_adds_v4f64(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, <4 x double> %x3) {
; SSE-LABEL: reassociate_adds_v4f64: ; SSE-LABEL: reassociate_adds_v4f64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: mulpd %xmm2, %xmm0 ; SSE-NEXT: mulpd %xmm2, %xmm0
; SSE-NEXT: mulpd %xmm3, %xmm1 ; SSE-NEXT: mulpd %xmm3, %xmm1
; SSE-NEXT: addpd %xmm6, %xmm4 ; SSE-NEXT: addpd %xmm6, %xmm4
; SSE-NEXT: addpd %xmm4, %xmm0
; SSE-NEXT: addpd %xmm7, %xmm5 ; SSE-NEXT: addpd %xmm7, %xmm5
; SSE-NEXT: addpd %xmm4, %xmm0
; SSE-NEXT: addpd %xmm5, %xmm1 ; SSE-NEXT: addpd %xmm5, %xmm1
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: reassociate_adds_v4f64: ; AVX1-LABEL: reassociate_adds_v4f64:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vmulpd %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: vmulpd %ymm1, %ymm0, %ymm0
; AVX1-NEXT: vaddpd %ymm3, %ymm2, %ymm1 ; AVX1-NEXT: vaddpd %ymm3, %ymm2, %ymm1
; AVX1-NEXT: vaddpd %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: vaddpd %ymm1, %ymm0, %ymm0
Show All 10 Lines; AVX512-NEXT: retq
ret <4 x double> %t2 ret <4 x double> %t2
} }
; Verify that AVX 256-bit vector single-precision multiplies are reassociated. ; Verify that AVX 256-bit vector single-precision multiplies are reassociated.
define <8 x float> @reassociate_muls_v8f32(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, <8 x float> %x3) { define <8 x float> @reassociate_muls_v8f32(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, <8 x float> %x3) {
; SSE-LABEL: reassociate_muls_v8f32: ; SSE-LABEL: reassociate_muls_v8f32:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: mulps %xmm6, %xmm4
; SSE-NEXT: mulps %xmm7, %xmm5
; SSE-NEXT: addps %xmm2, %xmm0 ; SSE-NEXT: addps %xmm2, %xmm0
; SSE-NEXT: addps %xmm3, %xmm1 ; SSE-NEXT: addps %xmm3, %xmm1
; SSE-NEXT: mulps %xmm6, %xmm4
; SSE-NEXT: mulps %xmm4, %xmm0 ; SSE-NEXT: mulps %xmm4, %xmm0
; SSE-NEXT: mulps %xmm7, %xmm5
; SSE-NEXT: mulps %xmm5, %xmm1 ; SSE-NEXT: mulps %xmm5, %xmm1
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: reassociate_muls_v8f32: ; AVX-LABEL: reassociate_muls_v8f32:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmulps %ymm3, %ymm2, %ymm2
; AVX-NEXT: vaddps %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vaddps %ymm1, %ymm0, %ymm0
; AVX-NEXT: vmulps %ymm3, %ymm2, %ymm1 ; AVX-NEXT: vmulps %ymm2, %ymm0, %ymm0
; AVX-NEXT: vmulps %ymm1, %ymm0, %ymm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%t0 = fadd reassoc nsz <8 x float> %x0, %x1 %t0 = fadd reassoc nsz <8 x float> %x0, %x1
%t1 = fmul reassoc nsz <8 x float> %x2, %t0 %t1 = fmul reassoc nsz <8 x float> %x2, %t0
%t2 = fmul reassoc nsz <8 x float> %x3, %t1 %t2 = fmul reassoc nsz <8 x float> %x3, %t1
ret <8 x float> %t2 ret <8 x float> %t2
} }
; Verify that AVX 256-bit vector double-precision multiplies are reassociated. ; Verify that AVX 256-bit vector double-precision multiplies are reassociated.
define <4 x double> @reassociate_muls_v4f64(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, <4 x double> %x3) { define <4 x double> @reassociate_muls_v4f64(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, <4 x double> %x3) {
; SSE-LABEL: reassociate_muls_v4f64: ; SSE-LABEL: reassociate_muls_v4f64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: mulpd %xmm6, %xmm4
; SSE-NEXT: mulpd %xmm7, %xmm5
; SSE-NEXT: addpd %xmm2, %xmm0 ; SSE-NEXT: addpd %xmm2, %xmm0
; SSE-NEXT: addpd %xmm3, %xmm1 ; SSE-NEXT: addpd %xmm3, %xmm1
; SSE-NEXT: mulpd %xmm6, %xmm4
; SSE-NEXT: mulpd %xmm4, %xmm0 ; SSE-NEXT: mulpd %xmm4, %xmm0
; SSE-NEXT: mulpd %xmm7, %xmm5
; SSE-NEXT: mulpd %xmm5, %xmm1 ; SSE-NEXT: mulpd %xmm5, %xmm1
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: reassociate_muls_v4f64: ; AVX-LABEL: reassociate_muls_v4f64:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmulpd %ymm3, %ymm2, %ymm2
; AVX-NEXT: vaddpd %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vaddpd %ymm1, %ymm0, %ymm0
; AVX-NEXT: vmulpd %ymm3, %ymm2, %ymm1 ; AVX-NEXT: vmulpd %ymm2, %ymm0, %ymm0
; AVX-NEXT: vmulpd %ymm1, %ymm0, %ymm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%t0 = fadd reassoc nsz <4 x double> %x0, %x1 %t0 = fadd reassoc nsz <4 x double> %x0, %x1
%t1 = fmul reassoc nsz <4 x double> %x2, %t0 %t1 = fmul reassoc nsz <4 x double> %x2, %t0
%t2 = fmul reassoc nsz <4 x double> %x3, %t1 %t2 = fmul reassoc nsz <4 x double> %x3, %t1
ret <4 x double> %t2 ret <4 x double> %t2
} }
; Verify that AVX512 512-bit vector single-precision adds are reassociated. ; Verify that AVX512 512-bit vector single-precision adds are reassociated.
Show All 15 Lines
; SSE-NEXT: addps {{[0-9]+}}(%rsp), %xmm3 ; SSE-NEXT: addps {{[0-9]+}}(%rsp), %xmm3
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: reassociate_adds_v16f32: ; AVX1-LABEL: reassociate_adds_v16f32:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vmulps %ymm2, %ymm0, %ymm0 ; AVX1-NEXT: vmulps %ymm2, %ymm0, %ymm0
; AVX1-NEXT: vmulps %ymm3, %ymm1, %ymm1 ; AVX1-NEXT: vmulps %ymm3, %ymm1, %ymm1
; AVX1-NEXT: vaddps %ymm6, %ymm4, %ymm2 ; AVX1-NEXT: vaddps %ymm6, %ymm4, %ymm2
; AVX1-NEXT: vaddps %ymm7, %ymm5, %ymm3
; AVX1-NEXT: vaddps %ymm2, %ymm0, %ymm0 ; AVX1-NEXT: vaddps %ymm2, %ymm0, %ymm0
; AVX1-NEXT: vaddps %ymm7, %ymm5, %ymm2 ; AVX1-NEXT: vaddps %ymm3, %ymm1, %ymm1
; AVX1-NEXT: vaddps %ymm2, %ymm1, %ymm1
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX512-LABEL: reassociate_adds_v16f32: ; AVX512-LABEL: reassociate_adds_v16f32:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vfmadd213ps {{.*#+}} zmm0 = (zmm1 * zmm0) + zmm2 ; AVX512-NEXT: vfmadd213ps {{.*#+}} zmm0 = (zmm1 * zmm0) + zmm2
; AVX512-NEXT: vaddps %zmm0, %zmm3, %zmm0 ; AVX512-NEXT: vaddps %zmm0, %zmm3, %zmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%t0 = fmul reassoc nsz <16 x float> %x0, %x1 %t0 = fmul reassoc nsz <16 x float> %x0, %x1
Show All 21 Lines
; SSE-NEXT: addpd {{[0-9]+}}(%rsp), %xmm3 ; SSE-NEXT: addpd {{[0-9]+}}(%rsp), %xmm3
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: reassociate_adds_v8f64: ; AVX1-LABEL: reassociate_adds_v8f64:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vmulpd %ymm2, %ymm0, %ymm0 ; AVX1-NEXT: vmulpd %ymm2, %ymm0, %ymm0
; AVX1-NEXT: vmulpd %ymm3, %ymm1, %ymm1 ; AVX1-NEXT: vmulpd %ymm3, %ymm1, %ymm1
; AVX1-NEXT: vaddpd %ymm6, %ymm4, %ymm2 ; AVX1-NEXT: vaddpd %ymm6, %ymm4, %ymm2
; AVX1-NEXT: vaddpd %ymm7, %ymm5, %ymm3
; AVX1-NEXT: vaddpd %ymm2, %ymm0, %ymm0 ; AVX1-NEXT: vaddpd %ymm2, %ymm0, %ymm0
; AVX1-NEXT: vaddpd %ymm7, %ymm5, %ymm2 ; AVX1-NEXT: vaddpd %ymm3, %ymm1, %ymm1
; AVX1-NEXT: vaddpd %ymm2, %ymm1, %ymm1
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX512-LABEL: reassociate_adds_v8f64: ; AVX512-LABEL: reassociate_adds_v8f64:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vfmadd213pd {{.*#+}} zmm0 = (zmm1 * zmm0) + zmm2 ; AVX512-NEXT: vfmadd213pd {{.*#+}} zmm0 = (zmm1 * zmm0) + zmm2
; AVX512-NEXT: vaddpd %zmm0, %zmm3, %zmm0 ; AVX512-NEXT: vaddpd %zmm0, %zmm3, %zmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%t0 = fmul reassoc nsz <8 x double> %x0, %x1 %t0 = fmul reassoc nsz <8 x double> %x0, %x1
Show All 18 Lines
; SSE-NEXT: mulps {{[0-9]+}}(%rsp), %xmm0 ; SSE-NEXT: mulps {{[0-9]+}}(%rsp), %xmm0
; SSE-NEXT: mulps {{[0-9]+}}(%rsp), %xmm1 ; SSE-NEXT: mulps {{[0-9]+}}(%rsp), %xmm1
; SSE-NEXT: mulps {{[0-9]+}}(%rsp), %xmm2 ; SSE-NEXT: mulps {{[0-9]+}}(%rsp), %xmm2
; SSE-NEXT: mulps {{[0-9]+}}(%rsp), %xmm3 ; SSE-NEXT: mulps {{[0-9]+}}(%rsp), %xmm3
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: reassociate_muls_v16f32: ; AVX1-LABEL: reassociate_muls_v16f32:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vaddps %ymm2, %ymm0, %ymm0
; AVX1-NEXT: vaddps %ymm3, %ymm1, %ymm1 ; AVX1-NEXT: vaddps %ymm3, %ymm1, %ymm1
; AVX1-NEXT: vmulps %ymm6, %ymm4, %ymm2 ; AVX1-NEXT: vmulps %ymm7, %ymm5, %ymm3
; AVX1-NEXT: vmulps %ymm2, %ymm0, %ymm0 ; AVX1-NEXT: vmulps %ymm6, %ymm4, %ymm4
; AVX1-NEXT: vmulps %ymm7, %ymm5, %ymm2 ; AVX1-NEXT: vaddps %ymm2, %ymm0, %ymm0
; AVX1-NEXT: vmulps %ymm2, %ymm1, %ymm1 ; AVX1-NEXT: vmulps %ymm4, %ymm0, %ymm0
; AVX1-NEXT: vmulps %ymm3, %ymm1, %ymm1
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX512-LABEL: reassociate_muls_v16f32: ; AVX512-LABEL: reassociate_muls_v16f32:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vmulps %zmm3, %zmm2, %zmm2
; AVX512-NEXT: vaddps %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vaddps %zmm1, %zmm0, %zmm0
; AVX512-NEXT: vmulps %zmm3, %zmm2, %zmm1 ; AVX512-NEXT: vmulps %zmm2, %zmm0, %zmm0
; AVX512-NEXT: vmulps %zmm1, %zmm0, %zmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%t0 = fadd reassoc nsz <16 x float> %x0, %x1 %t0 = fadd reassoc nsz <16 x float> %x0, %x1
%t1 = fmul reassoc nsz <16 x float> %x2, %t0 %t1 = fmul reassoc nsz <16 x float> %x2, %t0
%t2 = fmul reassoc nsz <16 x float> %x3, %t1 %t2 = fmul reassoc nsz <16 x float> %x3, %t1
ret <16 x float> %t2 ret <16 x float> %t2
} }
; Verify that AVX512 512-bit vector double-precision multiplies are reassociated. ; Verify that AVX512 512-bit vector double-precision multiplies are reassociated.
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; SSE-NEXT: mulpd {{[0-9]+}}(%rsp), %xmm0 ; SSE-NEXT: mulpd {{[0-9]+}}(%rsp), %xmm0
; SSE-NEXT: mulpd {{[0-9]+}}(%rsp), %xmm1 ; SSE-NEXT: mulpd {{[0-9]+}}(%rsp), %xmm1
; SSE-NEXT: mulpd {{[0-9]+}}(%rsp), %xmm2 ; SSE-NEXT: mulpd {{[0-9]+}}(%rsp), %xmm2
; SSE-NEXT: mulpd {{[0-9]+}}(%rsp), %xmm3 ; SSE-NEXT: mulpd {{[0-9]+}}(%rsp), %xmm3
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: reassociate_muls_v8f64: ; AVX1-LABEL: reassociate_muls_v8f64:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vaddpd %ymm2, %ymm0, %ymm0
; AVX1-NEXT: vaddpd %ymm3, %ymm1, %ymm1 ; AVX1-NEXT: vaddpd %ymm3, %ymm1, %ymm1
; AVX1-NEXT: vmulpd %ymm6, %ymm4, %ymm2 ; AVX1-NEXT: vmulpd %ymm7, %ymm5, %ymm3
; AVX1-NEXT: vmulpd %ymm2, %ymm0, %ymm0 ; AVX1-NEXT: vmulpd %ymm6, %ymm4, %ymm4
; AVX1-NEXT: vmulpd %ymm7, %ymm5, %ymm2 ; AVX1-NEXT: vaddpd %ymm2, %ymm0, %ymm0
; AVX1-NEXT: vmulpd %ymm2, %ymm1, %ymm1 ; AVX1-NEXT: vmulpd %ymm4, %ymm0, %ymm0
; AVX1-NEXT: vmulpd %ymm3, %ymm1, %ymm1
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX512-LABEL: reassociate_muls_v8f64: ; AVX512-LABEL: reassociate_muls_v8f64:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vmulpd %zmm3, %zmm2, %zmm2
; AVX512-NEXT: vaddpd %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vaddpd %zmm1, %zmm0, %zmm0
; AVX512-NEXT: vmulpd %zmm3, %zmm2, %zmm1 ; AVX512-NEXT: vmulpd %zmm2, %zmm0, %zmm0
; AVX512-NEXT: vmulpd %zmm1, %zmm0, %zmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%t0 = fadd reassoc nsz <8 x double> %x0, %x1 %t0 = fadd reassoc nsz <8 x double> %x0, %x1
%t1 = fmul reassoc nsz <8 x double> %x2, %t0 %t1 = fmul reassoc nsz <8 x double> %x2, %t0
%t2 = fmul reassoc nsz <8 x double> %x3, %t1 %t2 = fmul reassoc nsz <8 x double> %x3, %t1
ret <8 x double> %t2 ret <8 x double> %t2
} }
; Verify that SSE and AVX scalar single-precision minimum ops are reassociated. ; Verify that SSE and AVX scalar single-precision minimum ops are reassociated.
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; SSE-NEXT: addps %xmm1, %xmm0 ; SSE-NEXT: addps %xmm1, %xmm0
; SSE-NEXT: minps %xmm3, %xmm2 ; SSE-NEXT: minps %xmm3, %xmm2
; SSE-NEXT: minps %xmm2, %xmm0 ; SSE-NEXT: minps %xmm2, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: reassociate_mins_v4f32: ; AVX-LABEL: reassociate_mins_v4f32:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vaddps %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vaddps %xmm1, %xmm0, %xmm0
; AVX-NEXT: vminps %xmm3, %xmm2, %xmm1 ; AVX-NEXT: vminps %xmm3, %xmm2, %xmm2
; AVX-NEXT: vminps %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vminps %xmm2, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%t0 = fadd <4 x float> %x0, %x1 %t0 = fadd <4 x float> %x0, %x1
%cmp1 = fcmp olt <4 x float> %x2, %t0 %cmp1 = fcmp olt <4 x float> %x2, %t0
%sel1 = select <4 x i1> %cmp1, <4 x float> %x2, <4 x float> %t0 %sel1 = select <4 x i1> %cmp1, <4 x float> %x2, <4 x float> %t0
%cmp2 = fcmp olt <4 x float> %x3, %sel1 %cmp2 = fcmp olt <4 x float> %x3, %sel1
%sel2 = select <4 x i1> %cmp2, <4 x float> %x3, <4 x float> %sel1 %sel2 = select <4 x i1> %cmp2, <4 x float> %x3, <4 x float> %sel1
ret <4 x float> %sel2 ret <4 x float> %sel2
} }
; Verify that SSE and AVX 128-bit vector single-precision maximum ops are reassociated. ; Verify that SSE and AVX 128-bit vector single-precision maximum ops are reassociated.
define <4 x float> @reassociate_maxs_v4f32(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) { define <4 x float> @reassociate_maxs_v4f32(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) {
; SSE-LABEL: reassociate_maxs_v4f32: ; SSE-LABEL: reassociate_maxs_v4f32:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: addps %xmm1, %xmm0 ; SSE-NEXT: addps %xmm1, %xmm0
; SSE-NEXT: maxps %xmm3, %xmm2 ; SSE-NEXT: maxps %xmm3, %xmm2
; SSE-NEXT: maxps %xmm2, %xmm0 ; SSE-NEXT: maxps %xmm2, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: reassociate_maxs_v4f32: ; AVX-LABEL: reassociate_maxs_v4f32:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vaddps %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vaddps %xmm1, %xmm0, %xmm0
; AVX-NEXT: vmaxps %xmm3, %xmm2, %xmm1 ; AVX-NEXT: vmaxps %xmm3, %xmm2, %xmm2
; AVX-NEXT: vmaxps %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vmaxps %xmm2, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%t0 = fadd <4 x float> %x0, %x1 %t0 = fadd <4 x float> %x0, %x1
%cmp1 = fcmp ogt <4 x float> %x2, %t0 %cmp1 = fcmp ogt <4 x float> %x2, %t0
%sel1 = select <4 x i1> %cmp1, <4 x float> %x2, <4 x float> %t0 %sel1 = select <4 x i1> %cmp1, <4 x float> %x2, <4 x float> %t0
%cmp2 = fcmp ogt <4 x float> %x3, %sel1 %cmp2 = fcmp ogt <4 x float> %x3, %sel1
%sel2 = select <4 x i1> %cmp2, <4 x float> %x3, <4 x float> %sel1 %sel2 = select <4 x i1> %cmp2, <4 x float> %x3, <4 x float> %sel1
ret <4 x float> %sel2 ret <4 x float> %sel2
} }
; Verify that SSE and AVX 128-bit vector double-precision minimum ops are reassociated. ; Verify that SSE and AVX 128-bit vector double-precision minimum ops are reassociated.
define <2 x double> @reassociate_mins_v2f64(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, <2 x double> %x3) { define <2 x double> @reassociate_mins_v2f64(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, <2 x double> %x3) {
; SSE-LABEL: reassociate_mins_v2f64: ; SSE-LABEL: reassociate_mins_v2f64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: addpd %xmm1, %xmm0 ; SSE-NEXT: addpd %xmm1, %xmm0
; SSE-NEXT: minpd %xmm3, %xmm2 ; SSE-NEXT: minpd %xmm3, %xmm2
; SSE-NEXT: minpd %xmm2, %xmm0 ; SSE-NEXT: minpd %xmm2, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: reassociate_mins_v2f64: ; AVX-LABEL: reassociate_mins_v2f64:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vaddpd %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vaddpd %xmm1, %xmm0, %xmm0
; AVX-NEXT: vminpd %xmm3, %xmm2, %xmm1 ; AVX-NEXT: vminpd %xmm3, %xmm2, %xmm2
; AVX-NEXT: vminpd %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vminpd %xmm2, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%t0 = fadd <2 x double> %x0, %x1 %t0 = fadd <2 x double> %x0, %x1
%cmp1 = fcmp olt <2 x double> %x2, %t0 %cmp1 = fcmp olt <2 x double> %x2, %t0
%sel1 = select <2 x i1> %cmp1, <2 x double> %x2, <2 x double> %t0 %sel1 = select <2 x i1> %cmp1, <2 x double> %x2, <2 x double> %t0
%cmp2 = fcmp olt <2 x double> %x3, %sel1 %cmp2 = fcmp olt <2 x double> %x3, %sel1
%sel2 = select <2 x i1> %cmp2, <2 x double> %x3, <2 x double> %sel1 %sel2 = select <2 x i1> %cmp2, <2 x double> %x3, <2 x double> %sel1
ret <2 x double> %sel2 ret <2 x double> %sel2
} }
; Verify that SSE and AVX 128-bit vector double-precision maximum ops are reassociated. ; Verify that SSE and AVX 128-bit vector double-precision maximum ops are reassociated.
define <2 x double> @reassociate_maxs_v2f64(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, <2 x double> %x3) { define <2 x double> @reassociate_maxs_v2f64(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, <2 x double> %x3) {
; SSE-LABEL: reassociate_maxs_v2f64: ; SSE-LABEL: reassociate_maxs_v2f64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: addpd %xmm1, %xmm0 ; SSE-NEXT: addpd %xmm1, %xmm0
; SSE-NEXT: maxpd %xmm3, %xmm2 ; SSE-NEXT: maxpd %xmm3, %xmm2
; SSE-NEXT: maxpd %xmm2, %xmm0 ; SSE-NEXT: maxpd %xmm2, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: reassociate_maxs_v2f64: ; AVX-LABEL: reassociate_maxs_v2f64:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vaddpd %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vaddpd %xmm1, %xmm0, %xmm0
; AVX-NEXT: vmaxpd %xmm3, %xmm2, %xmm1 ; AVX-NEXT: vmaxpd %xmm3, %xmm2, %xmm2
; AVX-NEXT: vmaxpd %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vmaxpd %xmm2, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%t0 = fadd <2 x double> %x0, %x1 %t0 = fadd <2 x double> %x0, %x1
%cmp1 = fcmp ogt <2 x double> %x2, %t0 %cmp1 = fcmp ogt <2 x double> %x2, %t0
%sel1 = select <2 x i1> %cmp1, <2 x double> %x2, <2 x double> %t0 %sel1 = select <2 x i1> %cmp1, <2 x double> %x2, <2 x double> %t0
%cmp2 = fcmp ogt <2 x double> %x3, %sel1 %cmp2 = fcmp ogt <2 x double> %x3, %sel1
%sel2 = select <2 x i1> %cmp2, <2 x double> %x3, <2 x double> %sel1 %sel2 = select <2 x i1> %cmp2, <2 x double> %x3, <2 x double> %sel1
ret <2 x double> %sel2 ret <2 x double> %sel2
} }
; Verify that AVX 256-bit vector single-precision minimum ops are reassociated. ; Verify that AVX 256-bit vector single-precision minimum ops are reassociated.
define <8 x float> @reassociate_mins_v8f32(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, <8 x float> %x3) { define <8 x float> @reassociate_mins_v8f32(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, <8 x float> %x3) {
; SSE-LABEL: reassociate_mins_v8f32: ; SSE-LABEL: reassociate_mins_v8f32:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: addps %xmm2, %xmm0 ; SSE-NEXT: addps %xmm2, %xmm0
; SSE-NEXT: addps %xmm3, %xmm1
; SSE-NEXT: minps %xmm6, %xmm4 ; SSE-NEXT: minps %xmm6, %xmm4
; SSE-NEXT: minps %xmm4, %xmm0 ; SSE-NEXT: addps %xmm3, %xmm1
; SSE-NEXT: minps %xmm7, %xmm5 ; SSE-NEXT: minps %xmm7, %xmm5
; SSE-NEXT: minps %xmm4, %xmm0
; SSE-NEXT: minps %xmm5, %xmm1 ; SSE-NEXT: minps %xmm5, %xmm1
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: reassociate_mins_v8f32: ; AVX-LABEL: reassociate_mins_v8f32:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vaddps %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vaddps %ymm1, %ymm0, %ymm0
; AVX-NEXT: vminps %ymm3, %ymm2, %ymm1 ; AVX-NEXT: vminps %ymm3, %ymm2, %ymm2
; AVX-NEXT: vminps %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vminps %ymm2, %ymm0, %ymm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%t0 = fadd <8 x float> %x0, %x1 %t0 = fadd <8 x float> %x0, %x1
%cmp1 = fcmp olt <8 x float> %x2, %t0 %cmp1 = fcmp olt <8 x float> %x2, %t0
%sel1 = select <8 x i1> %cmp1, <8 x float> %x2, <8 x float> %t0 %sel1 = select <8 x i1> %cmp1, <8 x float> %x2, <8 x float> %t0
%cmp2 = fcmp olt <8 x float> %x3, %sel1 %cmp2 = fcmp olt <8 x float> %x3, %sel1
%sel2 = select <8 x i1> %cmp2, <8 x float> %x3, <8 x float> %sel1 %sel2 = select <8 x i1> %cmp2, <8 x float> %x3, <8 x float> %sel1
ret <8 x float> %sel2 ret <8 x float> %sel2
} }
; Verify that AVX 256-bit vector single-precision maximum ops are reassociated. ; Verify that AVX 256-bit vector single-precision maximum ops are reassociated.
define <8 x float> @reassociate_maxs_v8f32(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, <8 x float> %x3) { define <8 x float> @reassociate_maxs_v8f32(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, <8 x float> %x3) {
; SSE-LABEL: reassociate_maxs_v8f32: ; SSE-LABEL: reassociate_maxs_v8f32:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: addps %xmm2, %xmm0 ; SSE-NEXT: addps %xmm2, %xmm0
; SSE-NEXT: addps %xmm3, %xmm1
; SSE-NEXT: maxps %xmm6, %xmm4 ; SSE-NEXT: maxps %xmm6, %xmm4
; SSE-NEXT: maxps %xmm4, %xmm0 ; SSE-NEXT: addps %xmm3, %xmm1
; SSE-NEXT: maxps %xmm7, %xmm5 ; SSE-NEXT: maxps %xmm7, %xmm5
; SSE-NEXT: maxps %xmm4, %xmm0
; SSE-NEXT: maxps %xmm5, %xmm1 ; SSE-NEXT: maxps %xmm5, %xmm1
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: reassociate_maxs_v8f32: ; AVX-LABEL: reassociate_maxs_v8f32:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vaddps %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vaddps %ymm1, %ymm0, %ymm0
; AVX-NEXT: vmaxps %ymm3, %ymm2, %ymm1 ; AVX-NEXT: vmaxps %ymm3, %ymm2, %ymm2
; AVX-NEXT: vmaxps %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vmaxps %ymm2, %ymm0, %ymm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%t0 = fadd <8 x float> %x0, %x1 %t0 = fadd <8 x float> %x0, %x1
%cmp1 = fcmp ogt <8 x float> %x2, %t0 %cmp1 = fcmp ogt <8 x float> %x2, %t0
%sel1 = select <8 x i1> %cmp1, <8 x float> %x2, <8 x float> %t0 %sel1 = select <8 x i1> %cmp1, <8 x float> %x2, <8 x float> %t0
%cmp2 = fcmp ogt <8 x float> %x3, %sel1 %cmp2 = fcmp ogt <8 x float> %x3, %sel1
%sel2 = select <8 x i1> %cmp2, <8 x float> %x3, <8 x float> %sel1 %sel2 = select <8 x i1> %cmp2, <8 x float> %x3, <8 x float> %sel1
ret <8 x float> %sel2 ret <8 x float> %sel2
} }
; Verify that AVX 256-bit vector double-precision minimum ops are reassociated. ; Verify that AVX 256-bit vector double-precision minimum ops are reassociated.
define <4 x double> @reassociate_mins_v4f64(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, <4 x double> %x3) { define <4 x double> @reassociate_mins_v4f64(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, <4 x double> %x3) {
; SSE-LABEL: reassociate_mins_v4f64: ; SSE-LABEL: reassociate_mins_v4f64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: addpd %xmm2, %xmm0 ; SSE-NEXT: addpd %xmm2, %xmm0
; SSE-NEXT: addpd %xmm3, %xmm1
; SSE-NEXT: minpd %xmm6, %xmm4 ; SSE-NEXT: minpd %xmm6, %xmm4
; SSE-NEXT: minpd %xmm4, %xmm0 ; SSE-NEXT: addpd %xmm3, %xmm1
; SSE-NEXT: minpd %xmm7, %xmm5 ; SSE-NEXT: minpd %xmm7, %xmm5
; SSE-NEXT: minpd %xmm4, %xmm0
; SSE-NEXT: minpd %xmm5, %xmm1 ; SSE-NEXT: minpd %xmm5, %xmm1
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: reassociate_mins_v4f64: ; AVX-LABEL: reassociate_mins_v4f64:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vaddpd %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vaddpd %ymm1, %ymm0, %ymm0
; AVX-NEXT: vminpd %ymm3, %ymm2, %ymm1 ; AVX-NEXT: vminpd %ymm3, %ymm2, %ymm2
; AVX-NEXT: vminpd %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vminpd %ymm2, %ymm0, %ymm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%t0 = fadd <4 x double> %x0, %x1 %t0 = fadd <4 x double> %x0, %x1
%cmp1 = fcmp olt <4 x double> %x2, %t0 %cmp1 = fcmp olt <4 x double> %x2, %t0
%sel1 = select <4 x i1> %cmp1, <4 x double> %x2, <4 x double> %t0 %sel1 = select <4 x i1> %cmp1, <4 x double> %x2, <4 x double> %t0
%cmp2 = fcmp olt <4 x double> %x3, %sel1 %cmp2 = fcmp olt <4 x double> %x3, %sel1
%sel2 = select <4 x i1> %cmp2, <4 x double> %x3, <4 x double> %sel1 %sel2 = select <4 x i1> %cmp2, <4 x double> %x3, <4 x double> %sel1
ret <4 x double> %sel2 ret <4 x double> %sel2
} }
; Verify that AVX 256-bit vector double-precision maximum ops are reassociated. ; Verify that AVX 256-bit vector double-precision maximum ops are reassociated.
define <4 x double> @reassociate_maxs_v4f64(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, <4 x double> %x3) { define <4 x double> @reassociate_maxs_v4f64(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, <4 x double> %x3) {
; SSE-LABEL: reassociate_maxs_v4f64: ; SSE-LABEL: reassociate_maxs_v4f64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: addpd %xmm2, %xmm0 ; SSE-NEXT: addpd %xmm2, %xmm0
; SSE-NEXT: addpd %xmm3, %xmm1
; SSE-NEXT: maxpd %xmm6, %xmm4 ; SSE-NEXT: maxpd %xmm6, %xmm4
; SSE-NEXT: maxpd %xmm4, %xmm0 ; SSE-NEXT: addpd %xmm3, %xmm1
; SSE-NEXT: maxpd %xmm7, %xmm5 ; SSE-NEXT: maxpd %xmm7, %xmm5
; SSE-NEXT: maxpd %xmm4, %xmm0
; SSE-NEXT: maxpd %xmm5, %xmm1 ; SSE-NEXT: maxpd %xmm5, %xmm1
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: reassociate_maxs_v4f64: ; AVX-LABEL: reassociate_maxs_v4f64:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vaddpd %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vaddpd %ymm1, %ymm0, %ymm0
; AVX-NEXT: vmaxpd %ymm3, %ymm2, %ymm1 ; AVX-NEXT: vmaxpd %ymm3, %ymm2, %ymm2
; AVX-NEXT: vmaxpd %ymm1, %ymm0, %ymm0 ; AVX-NEXT: vmaxpd %ymm2, %ymm0, %ymm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%t0 = fadd <4 x double> %x0, %x1 %t0 = fadd <4 x double> %x0, %x1
%cmp1 = fcmp ogt <4 x double> %x2, %t0 %cmp1 = fcmp ogt <4 x double> %x2, %t0
%sel1 = select <4 x i1> %cmp1, <4 x double> %x2, <4 x double> %t0 %sel1 = select <4 x i1> %cmp1, <4 x double> %x2, <4 x double> %t0
%cmp2 = fcmp ogt <4 x double> %x3, %sel1 %cmp2 = fcmp ogt <4 x double> %x3, %sel1
%sel2 = select <4 x i1> %cmp2, <4 x double> %x3, <4 x double> %sel1 %sel2 = select <4 x i1> %cmp2, <4 x double> %x3, <4 x double> %sel1
ret <4 x double> %sel2 ret <4 x double> %sel2
} }
Show All 14 Lines
; SSE-NEXT: minps {{[0-9]+}}(%rsp), %xmm0 ; SSE-NEXT: minps {{[0-9]+}}(%rsp), %xmm0
; SSE-NEXT: minps {{[0-9]+}}(%rsp), %xmm1 ; SSE-NEXT: minps {{[0-9]+}}(%rsp), %xmm1
; SSE-NEXT: minps {{[0-9]+}}(%rsp), %xmm2 ; SSE-NEXT: minps {{[0-9]+}}(%rsp), %xmm2
; SSE-NEXT: minps {{[0-9]+}}(%rsp), %xmm3 ; SSE-NEXT: minps {{[0-9]+}}(%rsp), %xmm3
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: reassociate_mins_v16f32: ; AVX1-LABEL: reassociate_mins_v16f32:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vaddps %ymm2, %ymm0, %ymm0
; AVX1-NEXT: vaddps %ymm3, %ymm1, %ymm1 ; AVX1-NEXT: vaddps %ymm3, %ymm1, %ymm1
; AVX1-NEXT: vminps %ymm6, %ymm4, %ymm2 ; AVX1-NEXT: vminps %ymm7, %ymm5, %ymm3
; AVX1-NEXT: vminps %ymm2, %ymm0, %ymm0 ; AVX1-NEXT: vaddps %ymm2, %ymm0, %ymm0
; AVX1-NEXT: vminps %ymm7, %ymm5, %ymm2 ; AVX1-NEXT: vminps %ymm6, %ymm4, %ymm4
; AVX1-NEXT: vminps %ymm2, %ymm1, %ymm1 ; AVX1-NEXT: vminps %ymm4, %ymm0, %ymm0
; AVX1-NEXT: vminps %ymm3, %ymm1, %ymm1
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX512-LABEL: reassociate_mins_v16f32: ; AVX512-LABEL: reassociate_mins_v16f32:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vaddps %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vaddps %zmm1, %zmm0, %zmm0
; AVX512-NEXT: vminps %zmm3, %zmm2, %zmm1 ; AVX512-NEXT: vminps %zmm3, %zmm2, %zmm2
; AVX512-NEXT: vminps %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vminps %zmm2, %zmm0, %zmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%t0 = fadd <16 x float> %x0, %x1 %t0 = fadd <16 x float> %x0, %x1
%cmp1 = fcmp olt <16 x float> %x2, %t0 %cmp1 = fcmp olt <16 x float> %x2, %t0
%sel1 = select <16 x i1> %cmp1, <16 x float> %x2, <16 x float> %t0 %sel1 = select <16 x i1> %cmp1, <16 x float> %x2, <16 x float> %t0
%cmp2 = fcmp olt <16 x float> %x3, %sel1 %cmp2 = fcmp olt <16 x float> %x3, %sel1
%sel2 = select <16 x i1> %cmp2, <16 x float> %x3, <16 x float> %sel1 %sel2 = select <16 x i1> %cmp2, <16 x float> %x3, <16 x float> %sel1
ret <16 x float> %sel2 ret <16 x float> %sel2
} }
Show All 14 Lines
; SSE-NEXT: maxps {{[0-9]+}}(%rsp), %xmm0 ; SSE-NEXT: maxps {{[0-9]+}}(%rsp), %xmm0
; SSE-NEXT: maxps {{[0-9]+}}(%rsp), %xmm1 ; SSE-NEXT: maxps {{[0-9]+}}(%rsp), %xmm1
; SSE-NEXT: maxps {{[0-9]+}}(%rsp), %xmm2 ; SSE-NEXT: maxps {{[0-9]+}}(%rsp), %xmm2
; SSE-NEXT: maxps {{[0-9]+}}(%rsp), %xmm3 ; SSE-NEXT: maxps {{[0-9]+}}(%rsp), %xmm3
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: reassociate_maxs_v16f32: ; AVX1-LABEL: reassociate_maxs_v16f32:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vaddps %ymm2, %ymm0, %ymm0
; AVX1-NEXT: vaddps %ymm3, %ymm1, %ymm1 ; AVX1-NEXT: vaddps %ymm3, %ymm1, %ymm1
; AVX1-NEXT: vmaxps %ymm6, %ymm4, %ymm2 ; AVX1-NEXT: vmaxps %ymm7, %ymm5, %ymm3
; AVX1-NEXT: vmaxps %ymm2, %ymm0, %ymm0 ; AVX1-NEXT: vaddps %ymm2, %ymm0, %ymm0
; AVX1-NEXT: vmaxps %ymm7, %ymm5, %ymm2 ; AVX1-NEXT: vmaxps %ymm6, %ymm4, %ymm4
; AVX1-NEXT: vmaxps %ymm2, %ymm1, %ymm1 ; AVX1-NEXT: vmaxps %ymm4, %ymm0, %ymm0
; AVX1-NEXT: vmaxps %ymm3, %ymm1, %ymm1
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX512-LABEL: reassociate_maxs_v16f32: ; AVX512-LABEL: reassociate_maxs_v16f32:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vaddps %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vaddps %zmm1, %zmm0, %zmm0
; AVX512-NEXT: vmaxps %zmm3, %zmm2, %zmm1 ; AVX512-NEXT: vmaxps %zmm3, %zmm2, %zmm2
; AVX512-NEXT: vmaxps %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vmaxps %zmm2, %zmm0, %zmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%t0 = fadd <16 x float> %x0, %x1 %t0 = fadd <16 x float> %x0, %x1
%cmp1 = fcmp ogt <16 x float> %x2, %t0 %cmp1 = fcmp ogt <16 x float> %x2, %t0
%sel1 = select <16 x i1> %cmp1, <16 x float> %x2, <16 x float> %t0 %sel1 = select <16 x i1> %cmp1, <16 x float> %x2, <16 x float> %t0
%cmp2 = fcmp ogt <16 x float> %x3, %sel1 %cmp2 = fcmp ogt <16 x float> %x3, %sel1
%sel2 = select <16 x i1> %cmp2, <16 x float> %x3, <16 x float> %sel1 %sel2 = select <16 x i1> %cmp2, <16 x float> %x3, <16 x float> %sel1
ret <16 x float> %sel2 ret <16 x float> %sel2
} }
Show All 14 Lines
; SSE-NEXT: minpd {{[0-9]+}}(%rsp), %xmm0 ; SSE-NEXT: minpd {{[0-9]+}}(%rsp), %xmm0
; SSE-NEXT: minpd {{[0-9]+}}(%rsp), %xmm1 ; SSE-NEXT: minpd {{[0-9]+}}(%rsp), %xmm1
; SSE-NEXT: minpd {{[0-9]+}}(%rsp), %xmm2 ; SSE-NEXT: minpd {{[0-9]+}}(%rsp), %xmm2
; SSE-NEXT: minpd {{[0-9]+}}(%rsp), %xmm3 ; SSE-NEXT: minpd {{[0-9]+}}(%rsp), %xmm3
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: reassociate_mins_v8f64: ; AVX1-LABEL: reassociate_mins_v8f64:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vaddpd %ymm2, %ymm0, %ymm0
; AVX1-NEXT: vaddpd %ymm3, %ymm1, %ymm1 ; AVX1-NEXT: vaddpd %ymm3, %ymm1, %ymm1
; AVX1-NEXT: vminpd %ymm6, %ymm4, %ymm2 ; AVX1-NEXT: vminpd %ymm7, %ymm5, %ymm3
; AVX1-NEXT: vminpd %ymm2, %ymm0, %ymm0 ; AVX1-NEXT: vaddpd %ymm2, %ymm0, %ymm0
; AVX1-NEXT: vminpd %ymm7, %ymm5, %ymm2 ; AVX1-NEXT: vminpd %ymm6, %ymm4, %ymm4
; AVX1-NEXT: vminpd %ymm2, %ymm1, %ymm1 ; AVX1-NEXT: vminpd %ymm4, %ymm0, %ymm0
; AVX1-NEXT: vminpd %ymm3, %ymm1, %ymm1
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX512-LABEL: reassociate_mins_v8f64: ; AVX512-LABEL: reassociate_mins_v8f64:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vaddpd %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vaddpd %zmm1, %zmm0, %zmm0
; AVX512-NEXT: vminpd %zmm3, %zmm2, %zmm1 ; AVX512-NEXT: vminpd %zmm3, %zmm2, %zmm2
; AVX512-NEXT: vminpd %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vminpd %zmm2, %zmm0, %zmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%t0 = fadd <8 x double> %x0, %x1 %t0 = fadd <8 x double> %x0, %x1
%cmp1 = fcmp olt <8 x double> %x2, %t0 %cmp1 = fcmp olt <8 x double> %x2, %t0
%sel1 = select <8 x i1> %cmp1, <8 x double> %x2, <8 x double> %t0 %sel1 = select <8 x i1> %cmp1, <8 x double> %x2, <8 x double> %t0
%cmp2 = fcmp olt <8 x double> %x3, %sel1 %cmp2 = fcmp olt <8 x double> %x3, %sel1
%sel2 = select <8 x i1> %cmp2, <8 x double> %x3, <8 x double> %sel1 %sel2 = select <8 x i1> %cmp2, <8 x double> %x3, <8 x double> %sel1
ret <8 x double> %sel2 ret <8 x double> %sel2
} }
Show All 14 Lines
; SSE-NEXT: maxpd {{[0-9]+}}(%rsp), %xmm0 ; SSE-NEXT: maxpd {{[0-9]+}}(%rsp), %xmm0
; SSE-NEXT: maxpd {{[0-9]+}}(%rsp), %xmm1 ; SSE-NEXT: maxpd {{[0-9]+}}(%rsp), %xmm1
; SSE-NEXT: maxpd {{[0-9]+}}(%rsp), %xmm2 ; SSE-NEXT: maxpd {{[0-9]+}}(%rsp), %xmm2
; SSE-NEXT: maxpd {{[0-9]+}}(%rsp), %xmm3 ; SSE-NEXT: maxpd {{[0-9]+}}(%rsp), %xmm3
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: reassociate_maxs_v8f64: ; AVX1-LABEL: reassociate_maxs_v8f64:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vaddpd %ymm2, %ymm0, %ymm0
; AVX1-NEXT: vaddpd %ymm3, %ymm1, %ymm1 ; AVX1-NEXT: vaddpd %ymm3, %ymm1, %ymm1
; AVX1-NEXT: vmaxpd %ymm6, %ymm4, %ymm2 ; AVX1-NEXT: vmaxpd %ymm7, %ymm5, %ymm3
; AVX1-NEXT: vmaxpd %ymm2, %ymm0, %ymm0 ; AVX1-NEXT: vaddpd %ymm2, %ymm0, %ymm0
; AVX1-NEXT: vmaxpd %ymm7, %ymm5, %ymm2 ; AVX1-NEXT: vmaxpd %ymm6, %ymm4, %ymm4
; AVX1-NEXT: vmaxpd %ymm2, %ymm1, %ymm1 ; AVX1-NEXT: vmaxpd %ymm4, %ymm0, %ymm0
; AVX1-NEXT: vmaxpd %ymm3, %ymm1, %ymm1
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX512-LABEL: reassociate_maxs_v8f64: ; AVX512-LABEL: reassociate_maxs_v8f64:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vaddpd %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vaddpd %zmm1, %zmm0, %zmm0
; AVX512-NEXT: vmaxpd %zmm3, %zmm2, %zmm1 ; AVX512-NEXT: vmaxpd %zmm3, %zmm2, %zmm2
; AVX512-NEXT: vmaxpd %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vmaxpd %zmm2, %zmm0, %zmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%t0 = fadd <8 x double> %x0, %x1 %t0 = fadd <8 x double> %x0, %x1
%cmp1 = fcmp ogt <8 x double> %x2, %t0 %cmp1 = fcmp ogt <8 x double> %x2, %t0
%sel1 = select <8 x i1> %cmp1, <8 x double> %x2, <8 x double> %t0 %sel1 = select <8 x i1> %cmp1, <8 x double> %x2, <8 x double> %t0
%cmp2 = fcmp ogt <8 x double> %x3, %sel1 %cmp2 = fcmp ogt <8 x double> %x3, %sel1
%sel2 = select <8 x i1> %cmp2, <8 x double> %x3, <8 x double> %sel1 %sel2 = select <8 x i1> %cmp2, <8 x double> %x3, <8 x double> %sel1
ret <8 x double> %sel2 ret <8 x double> %sel2
} }
Show All 12 Lines
; SSE-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; SSE-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; SSE-NEXT: callq bar ; SSE-NEXT: callq bar
; SSE-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; SSE-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; SSE-NEXT: callq bar ; SSE-NEXT: callq bar
; SSE-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill ; SSE-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
; SSE-NEXT: callq bar ; SSE-NEXT: callq bar
; SSE-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload ; SSE-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
; SSE-NEXT: # xmm1 = mem[0],zero ; SSE-NEXT: # xmm1 = mem[0],zero
; SSE-NEXT: addsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Folded Reload
; SSE-NEXT: addsd (%rsp), %xmm0 # 8-byte Folded Reload ; SSE-NEXT: addsd (%rsp), %xmm0 # 8-byte Folded Reload
; SSE-NEXT: addsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Folded Reload
; SSE-NEXT: addsd %xmm1, %xmm0 ; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: addq $24, %rsp ; SSE-NEXT: addq $24, %rsp
; SSE-NEXT: .cfi_def_cfa_offset 8 ; SSE-NEXT: .cfi_def_cfa_offset 8
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: reassociate_adds_from_calls: ; AVX1-LABEL: reassociate_adds_from_calls:
; AVX: # %bb.0: ; AVX1: # %bb.0:
; AVX-NEXT: subq $24, %rsp ; AVX1-NEXT: subq $24, %rsp
; AVX-NEXT: .cfi_def_cfa_offset 32 ; AVX1-NEXT: .cfi_def_cfa_offset 32
; AVX-NEXT: callq bar ; AVX1-NEXT: callq bar
; AVX-NEXT: vmovsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; AVX1-NEXT: vmovsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; AVX-NEXT: callq bar ; AVX1-NEXT: callq bar
; AVX-NEXT: vmovsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; AVX1-NEXT: vmovsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; AVX-NEXT: callq bar ; AVX1-NEXT: callq bar
; AVX-NEXT: vmovsd %xmm0, (%rsp) # 8-byte Spill ; AVX1-NEXT: vmovsd %xmm0, (%rsp) # 8-byte Spill
; AVX-NEXT: callq bar ; AVX1-NEXT: callq bar
; AVX-NEXT: vmovsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload ; AVX1-NEXT: vmovsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
; AVX-NEXT: # xmm1 = mem[0],zero ; AVX1-NEXT: # xmm1 = mem[0],zero
; AVX-NEXT: vaddsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1, %xmm1 # 8-byte Folded Reload ; AVX1-NEXT: vaddsd (%rsp), %xmm0, %xmm0 # 8-byte Folded Reload
; AVX-NEXT: vaddsd (%rsp), %xmm0, %xmm0 # 8-byte Folded Reload ; AVX1-NEXT: vaddsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1, %xmm1 # 8-byte Folded Reload
; AVX-NEXT: vaddsd %xmm0, %xmm1, %xmm0 ; AVX1-NEXT: vaddsd %xmm0, %xmm1, %xmm0
; AVX-NEXT: addq $24, %rsp ; AVX1-NEXT: addq $24, %rsp
; AVX-NEXT: .cfi_def_cfa_offset 8 ; AVX1-NEXT: .cfi_def_cfa_offset 8
; AVX-NEXT: retq ; AVX1-NEXT: retq
;
; AVX512-LABEL: reassociate_adds_from_calls:
; AVX512: # %bb.0:
; AVX512-NEXT: subq $24, %rsp
; AVX512-NEXT: .cfi_def_cfa_offset 32
; AVX512-NEXT: callq bar
; AVX512-NEXT: vmovsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; AVX512-NEXT: callq bar
; AVX512-NEXT: vmovsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; AVX512-NEXT: callq bar
; AVX512-NEXT: vmovsd %xmm0, (%rsp) # 8-byte Spill
; AVX512-NEXT: callq bar
; AVX512-NEXT: vmovsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
; AVX512-NEXT: # xmm1 = mem[0],zero
; AVX512-NEXT: vaddsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1, %xmm1 # 8-byte Folded Reload
; AVX512-NEXT: vaddsd (%rsp), %xmm0, %xmm0 # 8-byte Folded Reload
; AVX512-NEXT: vaddsd %xmm0, %xmm1, %xmm0
; AVX512-NEXT: addq $24, %rsp
; AVX512-NEXT: .cfi_def_cfa_offset 8
; AVX512-NEXT: retq
%x0 = call double @bar() %x0 = call double @bar()
%x1 = call double @bar() %x1 = call double @bar()
%x2 = call double @bar() %x2 = call double @bar()
%x3 = call double @bar() %x3 = call double @bar()
%t0 = fadd reassoc nsz double %x0, %x1 %t0 = fadd reassoc nsz double %x0, %x1
%t1 = fadd reassoc nsz double %t0, %x2 %t1 = fadd reassoc nsz double %t0, %x2
%t2 = fadd reassoc nsz double %t1, %x3 %t2 = fadd reassoc nsz double %t1, %x3
Show All 9 Lines
; SSE-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; SSE-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; SSE-NEXT: callq bar ; SSE-NEXT: callq bar
; SSE-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; SSE-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; SSE-NEXT: callq bar ; SSE-NEXT: callq bar
; SSE-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill ; SSE-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
; SSE-NEXT: callq bar ; SSE-NEXT: callq bar
; SSE-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload ; SSE-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
; SSE-NEXT: # xmm1 = mem[0],zero ; SSE-NEXT: # xmm1 = mem[0],zero
; SSE-NEXT: addsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Folded Reload
; SSE-NEXT: addsd (%rsp), %xmm0 # 8-byte Folded Reload ; SSE-NEXT: addsd (%rsp), %xmm0 # 8-byte Folded Reload
; SSE-NEXT: addsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Folded Reload
; SSE-NEXT: addsd %xmm1, %xmm0 ; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: addq $24, %rsp ; SSE-NEXT: addq $24, %rsp
; SSE-NEXT: .cfi_def_cfa_offset 8 ; SSE-NEXT: .cfi_def_cfa_offset 8
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: already_reassociated: ; AVX1-LABEL: already_reassociated:
; AVX: # %bb.0: ; AVX1: # %bb.0:
; AVX-NEXT: subq $24, %rsp ; AVX1-NEXT: subq $24, %rsp
; AVX-NEXT: .cfi_def_cfa_offset 32 ; AVX1-NEXT: .cfi_def_cfa_offset 32
; AVX-NEXT: callq bar ; AVX1-NEXT: callq bar
; AVX-NEXT: vmovsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; AVX1-NEXT: vmovsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; AVX-NEXT: callq bar ; AVX1-NEXT: callq bar
; AVX-NEXT: vmovsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; AVX1-NEXT: vmovsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; AVX-NEXT: callq bar ; AVX1-NEXT: callq bar
; AVX-NEXT: vmovsd %xmm0, (%rsp) # 8-byte Spill ; AVX1-NEXT: vmovsd %xmm0, (%rsp) # 8-byte Spill
; AVX-NEXT: callq bar ; AVX1-NEXT: callq bar
; AVX-NEXT: vmovsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload ; AVX1-NEXT: vmovsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
; AVX-NEXT: # xmm1 = mem[0],zero ; AVX1-NEXT: # xmm1 = mem[0],zero
; AVX-NEXT: vaddsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1, %xmm1 # 8-byte Folded Reload ; AVX1-NEXT: vaddsd (%rsp), %xmm0, %xmm0 # 8-byte Folded Reload
; AVX-NEXT: vaddsd (%rsp), %xmm0, %xmm0 # 8-byte Folded Reload ; AVX1-NEXT: vaddsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1, %xmm1 # 8-byte Folded Reload
; AVX-NEXT: vaddsd %xmm0, %xmm1, %xmm0 ; AVX1-NEXT: vaddsd %xmm0, %xmm1, %xmm0
; AVX-NEXT: addq $24, %rsp ; AVX1-NEXT: addq $24, %rsp
; AVX-NEXT: .cfi_def_cfa_offset 8 ; AVX1-NEXT: .cfi_def_cfa_offset 8
; AVX-NEXT: retq ; AVX1-NEXT: retq
;
; AVX512-LABEL: already_reassociated:
; AVX512: # %bb.0:
; AVX512-NEXT: subq $24, %rsp
; AVX512-NEXT: .cfi_def_cfa_offset 32
; AVX512-NEXT: callq bar
; AVX512-NEXT: vmovsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; AVX512-NEXT: callq bar
; AVX512-NEXT: vmovsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; AVX512-NEXT: callq bar
; AVX512-NEXT: vmovsd %xmm0, (%rsp) # 8-byte Spill
; AVX512-NEXT: callq bar
; AVX512-NEXT: vmovsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
; AVX512-NEXT: # xmm1 = mem[0],zero
; AVX512-NEXT: vaddsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1, %xmm1 # 8-byte Folded Reload
; AVX512-NEXT: vaddsd (%rsp), %xmm0, %xmm0 # 8-byte Folded Reload
; AVX512-NEXT: vaddsd %xmm0, %xmm1, %xmm0
; AVX512-NEXT: addq $24, %rsp
; AVX512-NEXT: .cfi_def_cfa_offset 8
; AVX512-NEXT: retq
%x0 = call double @bar() %x0 = call double @bar()
%x1 = call double @bar() %x1 = call double @bar()
%x2 = call double @bar() %x2 = call double @bar()
%x3 = call double @bar() %x3 = call double @bar()
%t0 = fadd reassoc nsz double %x0, %x1 %t0 = fadd reassoc nsz double %x0, %x1
%t1 = fadd reassoc nsz double %x2, %x3 %t1 = fadd reassoc nsz double %x2, %x3
%t2 = fadd reassoc nsz double %t0, %t1 %t2 = fadd reassoc nsz double %t0, %t1
ret double %t2 ret double %t2
} }

llvm/test/CodeGen/X86/machine-trace-metrics-crash.ll

Show All 23 Lines
; CHECK-NEXT: .LBB0_2: # %if.then ; CHECK-NEXT: .LBB0_2: # %if.then
; CHECK-NEXT: xorps %xmm0, %xmm0 ; CHECK-NEXT: xorps %xmm0, %xmm0
; CHECK-NEXT: .LBB0_3: # %if.end ; CHECK-NEXT: .LBB0_3: # %if.end
; CHECK-NEXT: movss %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill ; CHECK-NEXT: movss %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
; CHECK-NEXT: callq foo ; CHECK-NEXT: callq foo
; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-NEXT: movss {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 4-byte Reload ; CHECK-NEXT: movss {{[-0-9]+}}(%r{{[sb]}}p), %xmm2 # 4-byte Reload
; CHECK-NEXT: # xmm2 = mem[0],zero,zero,zero ; CHECK-NEXT: # xmm2 = mem[0],zero,zero,zero
; CHECK-NEXT: mulss %xmm0, %xmm2
; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; CHECK-NEXT: mulss %xmm0, %xmm2
; CHECK-NEXT: addss %xmm1, %xmm0 ; CHECK-NEXT: addss %xmm1, %xmm0
; CHECK-NEXT: addss %xmm2, %xmm0 ; CHECK-NEXT: addss %xmm2, %xmm0
; CHECK-NEXT: movss %xmm0, (%rax) ; CHECK-NEXT: movss %xmm0, (%rax)
; CHECK-NEXT: testl %ebx, %ebx ; CHECK-NEXT: testl %ebx, %ebx
; CHECK-NEXT: jne .LBB0_5 ; CHECK-NEXT: jne .LBB0_5
; CHECK-NEXT: # %bb.4: # %if.end ; CHECK-NEXT: # %bb.4: # %if.end
; CHECK-NEXT: xorps %xmm1, %xmm1 ; CHECK-NEXT: xorps %xmm1, %xmm1
; CHECK-NEXT: .LBB0_5: # %if.end ; CHECK-NEXT: .LBB0_5: # %if.end
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llvm/test/CodeGen/X86/memcpy-2.ll

; RUN: llc < %s -mattr=+sse2 -mtriple=i686-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=SSE2-Darwin ; RUN: llc < %s -mattr=+sse2 -mtriple=i686-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=SSE2-Darwin
; RUN: llc < %s -mattr=+sse2 -mtriple=i686-pc-mingw32 -mcpu=core2 | FileCheck %s -check-prefix=SSE2-Mingw32 ; RUN: llc < %s -mattr=+sse2 -mtriple=i686-pc-mingw32 -mcpu=core2 | FileCheck %s -check-prefix=SSE2-Mingw32
; RUN: llc < %s -mattr=+sse,-sse2 -mtriple=i686-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=SSE1 ; RUN: llc < %s -mattr=+sse,-sse2 -mtriple=i686-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=SSE1
; RUN: llc < %s -mattr=-sse -mtriple=i686-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=NOSSE ; RUN: llc < %s -mattr=-sse -mtriple=i686-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=NOSSE
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=X86-64 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=X86-64
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=nehalem | FileCheck %s -check-prefix=NHM_64 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=nehalem | FileCheck %s -check-prefix=NHM_64
@.str = internal constant [25 x i8] c"image\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00" @.str = internal constant [25 x i8] c"image\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00"
@.str2 = internal constant [30 x i8] c"xxxxxxxxxxxxxxxxxxxxxxxxxxxxx\00", align 4 @.str2 = internal constant [30 x i8] c"xxxxxxxxxxxxxxxxxxxxxxxxxxxxx\00", align 4
define void @t1(i32 %argc, i8** %argv) nounwind { define void @t1(i32 %argc, i8** %argv) nounwind {
entry: entry:
; SSE2-Darwin-LABEL: t1: ; SSE2-Darwin-LABEL: t1:
; SSE2-Darwin: movsd _.str+16, %xmm0 ; SSE2-Darwin: movsd _.str+16, %xmm0
; SSE2-Darwin: movsd %xmm0, 16(%esp) ; SSE2-Darwin: movaps _.str, %xmm1
; SSE2-Darwin: movaps _.str, %xmm0
; SSE2-Darwin: movaps %xmm0
; SSE2-Darwin: movb $0, 24(%esp) ; SSE2-Darwin: movb $0, 24(%esp)
; SSE2-Darwin: movsd %xmm0, 16(%esp)
; SSE2-Darwin: movaps %xmm1
; SSE2-Mingw32-LABEL: t1: ; SSE2-Mingw32-LABEL: t1:
; SSE2-Mingw32: movsd _.str+16, %xmm0 ; SSE2-Mingw32: movsd _.str+16, %xmm0
; SSE2-Mingw32: movsd %xmm0, 16(%esp) ; SSE2-Mingw32: movaps _.str, %xmm1
; SSE2-Mingw32: movaps _.str, %xmm0
; SSE2-Mingw32: movups %xmm0
; SSE2-Mingw32: movb $0, 24(%esp) ; SSE2-Mingw32: movb $0, 24(%esp)
; SSE2-Mingw32: movsd %xmm0, 16(%esp)
; SSE2-Mingw32: movups %xmm1
; SSE1-LABEL: t1: ; SSE1-LABEL: t1:
; SSE1: movaps _.str, %xmm0 ; SSE1: movaps _.str, %xmm0
; SSE1: movaps %xmm0
; SSE1: movb $0, 24(%esp) ; SSE1: movb $0, 24(%esp)
; SSE1: movl $0, 20(%esp) ; SSE1: movl $0, 20(%esp)
; SSE1: movl $0, 16(%esp) ; SSE1: movl $0, 16(%esp)
; SSE1: movaps %xmm0
; NOSSE-LABEL: t1: ; NOSSE-LABEL: t1:
; NOSSE: movb $0 ; NOSSE: movb $0
; NOSSE: movl $0 ; NOSSE: movl $0
; NOSSE: movl $0 ; NOSSE: movl $0
; NOSSE: movl $0 ; NOSSE: movl $0
; NOSSE: movl $0 ; NOSSE: movl $0
; NOSSE: movl $101 ; NOSSE: movl $101
; NOSSE: movl $1734438249 ; NOSSE: movl $1734438249
; X86-64-LABEL: t1: ; X86-64-LABEL: t1:
; X86-64: movaps _.str(%rip), %xmm0 ; X86-64: movaps _.str(%rip), %xmm0
; X86-64: movaps %xmm0
; X86-64: movb $0 ; X86-64: movb $0
; X86-64: movq $0 ; X86-64: movq $0
; X86-64: movaps %xmm0
%tmp1 = alloca [25 x i8] %tmp1 = alloca [25 x i8]
%tmp2 = bitcast [25 x i8]* %tmp1 to i8* %tmp2 = bitcast [25 x i8]* %tmp1 to i8*
call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 1 %tmp2, i8* align 1 getelementptr inbounds ([25 x i8], [25 x i8]* @.str, i32 0, i32 0), i32 25, i1 false) call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 1 %tmp2, i8* align 1 getelementptr inbounds ([25 x i8], [25 x i8]* @.str, i32 0, i32 0), i32 25, i1 false)
unreachable unreachable
} }
;rdar://7774704 ;rdar://7774704
%struct.s0 = type { [2 x double] } %struct.s0 = type { [2 x double] }
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; NOSSE: movl $2021161080 ; NOSSE: movl $2021161080
;;; TODO: (1) Some of the loads and stores are certainly unaligned and (2) the first load and first ;;; TODO: (1) Some of the loads and stores are certainly unaligned and (2) the first load and first
;;; store overlap with the second load and second store respectively. ;;; store overlap with the second load and second store respectively.
;;; ;;;
;;; Is either of the sequences ideal? ;;; Is either of the sequences ideal?
; X86-64-LABEL: t4: ; X86-64-LABEL: t4:
; X86-64: movabsq $8680820740569200760, %rcx ## imm = 0x7878787878787878
; X86-64: movabsq $33909456017848440, %rax ## imm = 0x78787878787878 ; X86-64: movabsq $33909456017848440, %rax ## imm = 0x78787878787878
; X86-64: movq %rax, -10(%rsp) ; X86-64: movq %rax, -10(%rsp)
; X86-64: movabsq $8680820740569200760, %rax ## imm = 0x7878787878787878 ; X86-64: movq %rcx, -16(%rsp)
; X86-64: movq %rax, -16(%rsp) ; X86-64: movq %rcx, -24(%rsp)
; X86-64: movq %rax, -24(%rsp) ; X86-64: movq %rcx, -32(%rsp)
; X86-64: movq %rax, -32(%rsp)
; NHM_64-LABEL: t4: ; NHM_64-LABEL: t4:
; NHM_64: movups _.str2+14(%rip), %xmm0 ; NHM_64: movups _.str2+14(%rip), %xmm0
; NHM_64: movups _.str2(%rip), %xmm1
; NHM_64: movups %xmm0, -26(%rsp) ; NHM_64: movups %xmm0, -26(%rsp)
; NHM_64: movups _.str2(%rip), %xmm0 ; NHM_64: movaps %xmm1, -40(%rsp)
; NHM_64: movaps %xmm0, -40(%rsp)
%tmp1 = alloca [30 x i8] %tmp1 = alloca [30 x i8]
%tmp2 = bitcast [30 x i8]* %tmp1 to i8* %tmp2 = bitcast [30 x i8]* %tmp1 to i8*
call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 1 %tmp2, i8* align 1 getelementptr inbounds ([30 x i8], [30 x i8]* @.str2, i32 0, i32 0), i32 30, i1 false) call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 1 %tmp2, i8* align 1 getelementptr inbounds ([30 x i8], [30 x i8]* @.str2, i32 0, i32 0), i32 30, i1 false)
unreachable unreachable
} }
declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i1) nounwind declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i1) nounwind

llvm/test/CodeGen/X86/memcpy.ll

Show First 20 Lines • Show All 134 Lines • ▼ Show 20 Lines
; LINUX-AVX512BW-NEXT: vzeroupper ; LINUX-AVX512BW-NEXT: vzeroupper
; LINUX-AVX512BW-NEXT: retq ; LINUX-AVX512BW-NEXT: retq
entry: entry:
tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %A, i8* %B, i64 64, i1 false) tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %A, i8* %B, i64 64, i1 false)
ret void ret void
} }
define void @test3_pgso(i8* nocapture %A, i8* nocapture %B) nounwind noredzone !prof !14 { define void @test3_pgso(i8* nocapture %A, i8* nocapture %B) nounwind noredzone !prof !14 {
; LINUX-LABEL: test3_pgso:
; LINUX: # %bb.0: # %entry
; LINUX-NEXT: movl $64, %edx
; LINUX-NEXT: jmp memcpy # TAILCALL
;
; DARWIN-LABEL: test3_pgso: ; DARWIN-LABEL: test3_pgso:
; DARWIN: ## %bb.0: ## %entry ; DARWIN: ## %bb.0: ## %entry
; DARWIN-NEXT: movq 56(%rsi), %rax ; DARWIN-NEXT: movq 56(%rsi), %rax
; DARWIN-NEXT: movq %rax, 56(%rdi) ; DARWIN-NEXT: movq %rax, 56(%rdi)
; DARWIN-NEXT: movq 48(%rsi), %rax ; DARWIN-NEXT: movq 48(%rsi), %rax
; DARWIN-NEXT: movq %rax, 48(%rdi) ; DARWIN-NEXT: movq %rax, 48(%rdi)
; DARWIN-NEXT: movq 40(%rsi), %rax ; DARWIN-NEXT: movq 40(%rsi), %rax
; DARWIN-NEXT: movq %rax, 40(%rdi) ; DARWIN-NEXT: movq %rax, 40(%rdi)
; DARWIN-NEXT: movq 32(%rsi), %rax ; DARWIN-NEXT: movq 32(%rsi), %rax
; DARWIN-NEXT: movq %rax, 32(%rdi) ; DARWIN-NEXT: movq %rax, 32(%rdi)
; DARWIN-NEXT: movq 24(%rsi), %rax ; DARWIN-NEXT: movq 24(%rsi), %rax
; DARWIN-NEXT: movq %rax, 24(%rdi) ; DARWIN-NEXT: movq %rax, 24(%rdi)
; DARWIN-NEXT: movq 16(%rsi), %rax ; DARWIN-NEXT: movq 16(%rsi), %rax
; DARWIN-NEXT: movq %rax, 16(%rdi) ; DARWIN-NEXT: movq %rax, 16(%rdi)
; DARWIN-NEXT: movq (%rsi), %rax ; DARWIN-NEXT: movq (%rsi), %rax
; DARWIN-NEXT: movq 8(%rsi), %rcx ; DARWIN-NEXT: movq 8(%rsi), %rcx
; DARWIN-NEXT: movq %rcx, 8(%rdi) ; DARWIN-NEXT: movq %rcx, 8(%rdi)
; DARWIN-NEXT: movq %rax, (%rdi) ; DARWIN-NEXT: movq %rax, (%rdi)
; DARWIN-NEXT: retq ; DARWIN-NEXT: retq
;
; LINUX-LABEL: test3_pgso:
; LINUX: # %bb.0: # %entry
; LINUX-NEXT: movl $64, %edx
; LINUX-NEXT: jmp memcpy # TAILCALL
;
; LINUX-SKL-LABEL: test3_pgso:
; LINUX-SKL: # %bb.0: # %entry
; LINUX-SKL-NEXT: vmovups (%rsi), %ymm0
; LINUX-SKL-NEXT: vmovups 32(%rsi), %ymm1
; LINUX-SKL-NEXT: vmovups %ymm1, 32(%rdi)
; LINUX-SKL-NEXT: vmovups %ymm0, (%rdi)
; LINUX-SKL-NEXT: vzeroupper
; LINUX-SKL-NEXT: retq
;
; LINUX-SKX-LABEL: test3_pgso:
; LINUX-SKX: # %bb.0: # %entry
; LINUX-SKX-NEXT: vmovups (%rsi), %ymm0
; LINUX-SKX-NEXT: vmovups 32(%rsi), %ymm1
; LINUX-SKX-NEXT: vmovups %ymm1, 32(%rdi)
; LINUX-SKX-NEXT: vmovups %ymm0, (%rdi)
; LINUX-SKX-NEXT: vzeroupper
; LINUX-SKX-NEXT: retq
;
; LINUX-KNL-LABEL: test3_pgso:
; LINUX-KNL: # %bb.0: # %entry
; LINUX-KNL-NEXT: vmovups (%rsi), %zmm0
; LINUX-KNL-NEXT: vmovups %zmm0, (%rdi)
; LINUX-KNL-NEXT: retq
;
; LINUX-AVX512BW-LABEL: test3_pgso:
; LINUX-AVX512BW: # %bb.0: # %entry
; LINUX-AVX512BW-NEXT: vmovups (%rsi), %zmm0
; LINUX-AVX512BW-NEXT: vmovups %zmm0, (%rdi)
; LINUX-AVX512BW-NEXT: vzeroupper
; LINUX-AVX512BW-NEXT: retq
entry: entry:
tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %A, i8* %B, i64 64, i1 false) tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %A, i8* %B, i64 64, i1 false)
ret void ret void
} }
define void @test3_minsize(i8* nocapture %A, i8* nocapture %B) nounwind minsize noredzone { define void @test3_minsize(i8* nocapture %A, i8* nocapture %B) nounwind minsize noredzone {
; DARWIN-LABEL: test3_minsize: ; DARWIN-LABEL: test3_minsize:
; DARWIN: ## %bb.0: ; DARWIN: ## %bb.0:
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@.str = private unnamed_addr constant [30 x i8] c"\00aaaaaaaaaaaaaaaaaaaaaaaaaaaa\00", align 1 @.str = private unnamed_addr constant [30 x i8] c"\00aaaaaaaaaaaaaaaaaaaaaaaaaaaa\00", align 1
define void @test5(i8* nocapture %C) nounwind uwtable ssp { define void @test5(i8* nocapture %C) nounwind uwtable ssp {
; DARWIN-LABEL: test5: ; DARWIN-LABEL: test5:
; DARWIN: ## %bb.0: ## %entry ; DARWIN: ## %bb.0: ## %entry
; DARWIN-NEXT: movabsq $7016996765293437281, %rax ## imm = 0x6161616161616161 ; DARWIN-NEXT: movabsq $7016996765293437281, %rax ## imm = 0x6161616161616161
; DARWIN-NEXT: movabsq $7016996765293437184, %rcx ## imm = 0x6161616161616100
; DARWIN-NEXT: movq %rax, 8(%rdi) ; DARWIN-NEXT: movq %rax, 8(%rdi)
; DARWIN-NEXT: movabsq $7016996765293437184, %rax ## imm = 0x6161616161616100 ; DARWIN-NEXT: movq %rcx, (%rdi)
; DARWIN-NEXT: movq %rax, (%rdi)
; DARWIN-NEXT: retq ; DARWIN-NEXT: retq
; ;
; LINUX-LABEL: test5: ; LINUX-LABEL: test5:
; LINUX: # %bb.0: # %entry ; LINUX: # %bb.0: # %entry
; LINUX-NEXT: movabsq $7016996765293437281, %rax # imm = 0x6161616161616161 ; LINUX-NEXT: movabsq $7016996765293437281, %rax # imm = 0x6161616161616161
; LINUX-NEXT: movabsq $7016996765293437184, %rcx # imm = 0x6161616161616100
; LINUX-NEXT: movq %rax, 8(%rdi) ; LINUX-NEXT: movq %rax, 8(%rdi)
; LINUX-NEXT: movabsq $7016996765293437184, %rax # imm = 0x6161616161616100 ; LINUX-NEXT: movq %rcx, (%rdi)
; LINUX-NEXT: movq %rax, (%rdi)
; LINUX-NEXT: retq ; LINUX-NEXT: retq
; ;
; LINUX-SKL-LABEL: test5: ; LINUX-SKL-LABEL: test5:
; LINUX-SKL: # %bb.0: # %entry ; LINUX-SKL: # %bb.0: # %entry
; LINUX-SKL-NEXT: vmovups {{.*}}(%rip), %xmm0 ; LINUX-SKL-NEXT: vmovups {{.*}}(%rip), %xmm0
; LINUX-SKL-NEXT: vmovups %xmm0, (%rdi) ; LINUX-SKL-NEXT: vmovups %xmm0, (%rdi)
; LINUX-SKL-NEXT: retq ; LINUX-SKL-NEXT: retq
; ;
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llvm/test/CodeGen/X86/memset-2.ll

Show All 28 Linesentry:
unreachable unreachable
} }
declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i1) nounwind declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i1) nounwind
define void @t3(i8* nocapture %s, i8 %a) nounwind { define void @t3(i8* nocapture %s, i8 %a) nounwind {
; CHECK-LABEL: t3: ; CHECK-LABEL: t3:
; CHECK: ## %bb.0: ## %entry ; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movzbl {{[0-9]+}}(%esp), %ecx ; CHECK-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: imull $16843009, %ecx, %ecx ## imm = 0x1010101 ; CHECK-NEXT: imull $16843009, %ecx, %ecx ## imm = 0x1010101
; CHECK-NEXT: movl %ecx, 4(%eax) ; CHECK-NEXT: movl %ecx, 4(%eax)
; CHECK-NEXT: movl %ecx, (%eax) ; CHECK-NEXT: movl %ecx, (%eax)
; CHECK-NEXT: retl ; CHECK-NEXT: retl
entry: entry:
tail call void @llvm.memset.p0i8.i32(i8* %s, i8 %a, i32 8, i1 false) tail call void @llvm.memset.p0i8.i32(i8* %s, i8 %a, i32 8, i1 false)
ret void ret void
} }
define void @t4(i8* nocapture %s, i8 %a) nounwind { define void @t4(i8* nocapture %s, i8 %a) nounwind {
; CHECK-LABEL: t4: ; CHECK-LABEL: t4:
; CHECK: ## %bb.0: ## %entry ; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movzbl {{[0-9]+}}(%esp), %ecx ; CHECK-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: imull $16843009, %ecx, %ecx ## imm = 0x1010101 ; CHECK-NEXT: imull $16843009, %ecx, %ecx ## imm = 0x1010101
; CHECK-NEXT: movl %ecx, 11(%eax) ; CHECK-NEXT: movl %ecx, 11(%eax)
; CHECK-NEXT: movl %ecx, 8(%eax) ; CHECK-NEXT: movl %ecx, 8(%eax)
; CHECK-NEXT: movl %ecx, 4(%eax) ; CHECK-NEXT: movl %ecx, 4(%eax)
; CHECK-NEXT: movl %ecx, (%eax) ; CHECK-NEXT: movl %ecx, (%eax)
; CHECK-NEXT: retl ; CHECK-NEXT: retl
entry: entry:
tail call void @llvm.memset.p0i8.i32(i8* %s, i8 %a, i32 15, i1 false) tail call void @llvm.memset.p0i8.i32(i8* %s, i8 %a, i32 15, i1 false)
ret void ret void
} }

llvm/test/CodeGen/X86/memset-sse-stack-realignment.ll

Show All 27 Lines
; NOSSE-NEXT: calll __alloca ; NOSSE-NEXT: calll __alloca
; NOSSE-NEXT: movl %esp, %eax ; NOSSE-NEXT: movl %esp, %eax
; NOSSE-NEXT: pushl %eax ; NOSSE-NEXT: pushl %eax
; NOSSE-NEXT: calll _dummy ; NOSSE-NEXT: calll _dummy
; NOSSE-NEXT: movl %ebp, %esp ; NOSSE-NEXT: movl %ebp, %esp
; NOSSE-NEXT: popl %ebp ; NOSSE-NEXT: popl %ebp
; NOSSE-NEXT: retl ; NOSSE-NEXT: retl
; ;
; SSE-LABEL: test1: ; SSE1-LABEL: test1:
; SSE: # %bb.0: ; SSE1: # %bb.0:
; SSE-NEXT: pushl %ebp ; SSE1-NEXT: pushl %ebp
; SSE-NEXT: movl %esp, %ebp ; SSE1-NEXT: movl %esp, %ebp
; SSE-NEXT: pushl %esi ; SSE1-NEXT: pushl %esi
; SSE-NEXT: andl $-16, %esp ; SSE1-NEXT: andl $-16, %esp
; SSE-NEXT: subl $48, %esp ; SSE1-NEXT: subl $48, %esp
; SSE-NEXT: movl %esp, %esi ; SSE1-NEXT: movl %esp, %esi
; SSE-NEXT: movl 8(%ebp), %eax ; SSE1-NEXT: movl 8(%ebp), %eax
; SSE-NEXT: xorps %xmm0, %xmm0 ; SSE1-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: movaps %xmm0, 16(%esi) ; SSE1-NEXT: movaps %xmm0, 16(%esi)
; SSE-NEXT: movaps %xmm0, (%esi) ; SSE1-NEXT: movaps %xmm0, (%esi)
; SSE-NEXT: addl $3, %eax ; SSE1-NEXT: addl $3, %eax
; SSE-NEXT: andl $-4, %eax ; SSE1-NEXT: andl $-4, %eax
; SSE-NEXT: calll __alloca ; SSE1-NEXT: calll __alloca
; SSE-NEXT: movl %esp, %eax ; SSE1-NEXT: movl %esp, %eax
; SSE-NEXT: pushl %eax ; SSE1-NEXT: pushl %eax
; SSE-NEXT: calll _dummy ; SSE1-NEXT: calll _dummy
; SSE-NEXT: leal -4(%ebp), %esp ; SSE1-NEXT: leal -4(%ebp), %esp
; SSE-NEXT: popl %esi ; SSE1-NEXT: popl %esi
; SSE-NEXT: popl %ebp ; SSE1-NEXT: popl %ebp
; SSE-NEXT: retl ; SSE1-NEXT: retl
; ;
; AVX-LABEL: test1: ; SSE2-LABEL: test1:
; AVX: # %bb.0: ; SSE2: # %bb.0:
; AVX-NEXT: pushl %ebp ; SSE2-NEXT: pushl %ebp
; AVX-NEXT: movl %esp, %ebp ; SSE2-NEXT: movl %esp, %ebp
; AVX-NEXT: pushl %esi ; SSE2-NEXT: pushl %esi
; AVX-NEXT: andl $-32, %esp ; SSE2-NEXT: andl $-16, %esp
; AVX-NEXT: subl $64, %esp ; SSE2-NEXT: subl $48, %esp
; AVX-NEXT: movl %esp, %esi ; SSE2-NEXT: movl 8(%ebp), %eax
; AVX-NEXT: movl 8(%ebp), %eax ; SSE2-NEXT: movl %esp, %esi
; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; SSE2-NEXT: xorps %xmm0, %xmm0
; AVX-NEXT: vmovaps %ymm0, (%esi) ; SSE2-NEXT: movaps %xmm0, 16(%esi)
; AVX-NEXT: addl $3, %eax ; SSE2-NEXT: movaps %xmm0, (%esi)
; AVX-NEXT: andl $-4, %eax ; SSE2-NEXT: addl $3, %eax
; AVX-NEXT: calll __alloca ; SSE2-NEXT: andl $-4, %eax
; AVX-NEXT: movl %esp, %eax ; SSE2-NEXT: calll __alloca
; AVX-NEXT: pushl %eax ; SSE2-NEXT: movl %esp, %eax
; AVX-NEXT: vzeroupper ; SSE2-NEXT: pushl %eax
; AVX-NEXT: calll _dummy ; SSE2-NEXT: calll _dummy
; AVX-NEXT: leal -4(%ebp), %esp ; SSE2-NEXT: leal -4(%ebp), %esp
; AVX-NEXT: popl %esi ; SSE2-NEXT: popl %esi
; AVX-NEXT: popl %ebp ; SSE2-NEXT: popl %ebp
; AVX-NEXT: retl ; SSE2-NEXT: retl
;
; AVX1-LABEL: test1:
; AVX1: # %bb.0:
; AVX1-NEXT: pushl %ebp
; AVX1-NEXT: movl %esp, %ebp
; AVX1-NEXT: pushl %esi
; AVX1-NEXT: andl $-32, %esp
; AVX1-NEXT: subl $64, %esp
; AVX1-NEXT: movl 8(%ebp), %eax
; AVX1-NEXT: movl %esp, %esi
; AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX1-NEXT: vmovaps %ymm0, (%esi)
; AVX1-NEXT: addl $3, %eax
; AVX1-NEXT: andl $-4, %eax
; AVX1-NEXT: calll __alloca
; AVX1-NEXT: movl %esp, %eax
; AVX1-NEXT: pushl %eax
; AVX1-NEXT: vzeroupper
; AVX1-NEXT: calll _dummy
; AVX1-NEXT: leal -4(%ebp), %esp
; AVX1-NEXT: popl %esi
; AVX1-NEXT: popl %ebp
; AVX1-NEXT: retl
;
; AVX2-LABEL: test1:
; AVX2: # %bb.0:
; AVX2-NEXT: pushl %ebp
; AVX2-NEXT: movl %esp, %ebp
; AVX2-NEXT: pushl %esi
; AVX2-NEXT: andl $-32, %esp
; AVX2-NEXT: subl $64, %esp
; AVX2-NEXT: movl %esp, %esi
; AVX2-NEXT: movl 8(%ebp), %eax
; AVX2-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX2-NEXT: vmovaps %ymm0, (%esi)
; AVX2-NEXT: addl $3, %eax
; AVX2-NEXT: andl $-4, %eax
; AVX2-NEXT: calll __alloca
; AVX2-NEXT: movl %esp, %eax
; AVX2-NEXT: pushl %eax
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: calll _dummy
; AVX2-NEXT: leal -4(%ebp), %esp
; AVX2-NEXT: popl %esi
; AVX2-NEXT: popl %ebp
; AVX2-NEXT: retl
%tmp1210 = alloca i8, i32 32, align 4 %tmp1210 = alloca i8, i32 32, align 4
call void @llvm.memset.p0i8.i64(i8* align 4 %tmp1210, i8 0, i64 32, i1 false) call void @llvm.memset.p0i8.i64(i8* align 4 %tmp1210, i8 0, i64 32, i1 false)
%x = alloca i8, i32 %t %x = alloca i8, i32 %t
call void @dummy(i8* %x) call void @dummy(i8* %x)
ret void ret void
} }
define void @test2(i32 %t) nounwind { define void @test2(i32 %t) nounwind {
Show All 12 Lines
; NOSSE-NEXT: calll __alloca ; NOSSE-NEXT: calll __alloca
; NOSSE-NEXT: movl %esp, %eax ; NOSSE-NEXT: movl %esp, %eax
; NOSSE-NEXT: pushl %eax ; NOSSE-NEXT: pushl %eax
; NOSSE-NEXT: calll _dummy ; NOSSE-NEXT: calll _dummy
; NOSSE-NEXT: movl %ebp, %esp ; NOSSE-NEXT: movl %ebp, %esp
; NOSSE-NEXT: popl %ebp ; NOSSE-NEXT: popl %ebp
; NOSSE-NEXT: retl ; NOSSE-NEXT: retl
; ;
; SSE-LABEL: test2: ; SSE1-LABEL: test2:
; SSE: # %bb.0: ; SSE1: # %bb.0:
; SSE-NEXT: pushl %ebp ; SSE1-NEXT: pushl %ebp
; SSE-NEXT: movl %esp, %ebp ; SSE1-NEXT: movl %esp, %ebp
; SSE-NEXT: pushl %esi ; SSE1-NEXT: pushl %esi
; SSE-NEXT: andl $-16, %esp ; SSE1-NEXT: andl $-16, %esp
; SSE-NEXT: subl $32, %esp ; SSE1-NEXT: subl $32, %esp
; SSE-NEXT: movl %esp, %esi ; SSE1-NEXT: movl %esp, %esi
; SSE-NEXT: movl 8(%ebp), %eax ; SSE1-NEXT: movl 8(%ebp), %eax
; SSE-NEXT: xorps %xmm0, %xmm0 ; SSE1-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: movaps %xmm0, (%esi) ; SSE1-NEXT: movaps %xmm0, (%esi)
; SSE-NEXT: addl $3, %eax ; SSE1-NEXT: addl $3, %eax
; SSE-NEXT: andl $-4, %eax ; SSE1-NEXT: andl $-4, %eax
; SSE-NEXT: calll __alloca ; SSE1-NEXT: calll __alloca
; SSE-NEXT: movl %esp, %eax ; SSE1-NEXT: movl %esp, %eax
; SSE-NEXT: pushl %eax ; SSE1-NEXT: pushl %eax
; SSE-NEXT: calll _dummy ; SSE1-NEXT: calll _dummy
; SSE-NEXT: leal -4(%ebp), %esp ; SSE1-NEXT: leal -4(%ebp), %esp
; SSE-NEXT: popl %esi ; SSE1-NEXT: popl %esi
; SSE-NEXT: popl %ebp ; SSE1-NEXT: popl %ebp
; SSE-NEXT: retl ; SSE1-NEXT: retl
; ;
; AVX-LABEL: test2: ; SSE2-LABEL: test2:
; AVX: # %bb.0: ; SSE2: # %bb.0:
; AVX-NEXT: pushl %ebp ; SSE2-NEXT: pushl %ebp
; AVX-NEXT: movl %esp, %ebp ; SSE2-NEXT: movl %esp, %ebp
; AVX-NEXT: pushl %esi ; SSE2-NEXT: pushl %esi
; AVX-NEXT: andl $-16, %esp ; SSE2-NEXT: andl $-16, %esp
; AVX-NEXT: subl $32, %esp ; SSE2-NEXT: subl $32, %esp
; AVX-NEXT: movl %esp, %esi ; SSE2-NEXT: movl 8(%ebp), %eax
; AVX-NEXT: movl 8(%ebp), %eax ; SSE2-NEXT: movl %esp, %esi
; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; SSE2-NEXT: xorps %xmm0, %xmm0
; AVX-NEXT: vmovaps %xmm0, (%esi) ; SSE2-NEXT: movaps %xmm0, (%esi)
; AVX-NEXT: addl $3, %eax ; SSE2-NEXT: addl $3, %eax
; AVX-NEXT: andl $-4, %eax ; SSE2-NEXT: andl $-4, %eax
; AVX-NEXT: calll __alloca ; SSE2-NEXT: calll __alloca
; AVX-NEXT: movl %esp, %eax ; SSE2-NEXT: movl %esp, %eax
; AVX-NEXT: pushl %eax ; SSE2-NEXT: pushl %eax
; AVX-NEXT: calll _dummy ; SSE2-NEXT: calll _dummy
; AVX-NEXT: leal -4(%ebp), %esp ; SSE2-NEXT: leal -4(%ebp), %esp
; AVX-NEXT: popl %esi ; SSE2-NEXT: popl %esi
; AVX-NEXT: popl %ebp ; SSE2-NEXT: popl %ebp
; AVX-NEXT: retl ; SSE2-NEXT: retl
;
; AVX1-LABEL: test2:
; AVX1: # %bb.0:
; AVX1-NEXT: pushl %ebp
; AVX1-NEXT: movl %esp, %ebp
; AVX1-NEXT: pushl %esi
; AVX1-NEXT: andl $-16, %esp
; AVX1-NEXT: subl $32, %esp
; AVX1-NEXT: movl 8(%ebp), %eax
; AVX1-NEXT: movl %esp, %esi
; AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX1-NEXT: vmovaps %xmm0, (%esi)
; AVX1-NEXT: addl $3, %eax
; AVX1-NEXT: andl $-4, %eax
; AVX1-NEXT: calll __alloca
; AVX1-NEXT: movl %esp, %eax
; AVX1-NEXT: pushl %eax
; AVX1-NEXT: calll _dummy
; AVX1-NEXT: leal -4(%ebp), %esp
; AVX1-NEXT: popl %esi
; AVX1-NEXT: popl %ebp
; AVX1-NEXT: retl
;
; AVX2-LABEL: test2:
; AVX2: # %bb.0:
; AVX2-NEXT: pushl %ebp
; AVX2-NEXT: movl %esp, %ebp
; AVX2-NEXT: pushl %esi
; AVX2-NEXT: andl $-16, %esp
; AVX2-NEXT: subl $32, %esp
; AVX2-NEXT: movl %esp, %esi
; AVX2-NEXT: movl 8(%ebp), %eax
; AVX2-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX2-NEXT: vmovaps %xmm0, (%esi)
; AVX2-NEXT: addl $3, %eax
; AVX2-NEXT: andl $-4, %eax
; AVX2-NEXT: calll __alloca
; AVX2-NEXT: movl %esp, %eax
; AVX2-NEXT: pushl %eax
; AVX2-NEXT: calll _dummy
; AVX2-NEXT: leal -4(%ebp), %esp
; AVX2-NEXT: popl %esi
; AVX2-NEXT: popl %ebp
; AVX2-NEXT: retl
%tmp1210 = alloca i8, i32 16, align 4 %tmp1210 = alloca i8, i32 16, align 4
call void @llvm.memset.p0i8.i64(i8* align 4 %tmp1210, i8 0, i64 16, i1 false) call void @llvm.memset.p0i8.i64(i8* align 4 %tmp1210, i8 0, i64 16, i1 false)
%x = alloca i8, i32 %t %x = alloca i8, i32 %t
call void @dummy(i8* %x) call void @dummy(i8* %x)
ret void ret void
} }
declare void @dummy(i8*) declare void @dummy(i8*)
declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1) nounwind declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1) nounwind

llvm/test/CodeGen/X86/misched-aa-colored.ll

Show First 20 Lines • Show All 162 Lines • ▼ Show 20 Linesentry:
%1 = bitcast %"class.llvm::SDValue.3.603.963.1923.2043.2283.4083"* %Op.i to i8* %1 = bitcast %"class.llvm::SDValue.3.603.963.1923.2043.2283.4083"* %Op.i to i8*
call void @llvm.lifetime.start.p0i8(i64 16, i8* %1) #1 call void @llvm.lifetime.start.p0i8(i64 16, i8* %1) #1
%2 = getelementptr %"class.llvm::SDValue.3.603.963.1923.2043.2283.4083", %"class.llvm::SDValue.3.603.963.1923.2043.2283.4083"* %Op.i, i64 0, i32 1 %2 = getelementptr %"class.llvm::SDValue.3.603.963.1923.2043.2283.4083", %"class.llvm::SDValue.3.603.963.1923.2043.2283.4083"* %Op.i, i64 0, i32 1
store i32 %agg.tmp8.sroa.2.0.copyload, i32* %2, align 8 store i32 %agg.tmp8.sroa.2.0.copyload, i32* %2, align 8
; CHECK: movl (%rax), %eax ; CHECK: movl (%rax), %eax
; CHECK-NOT: movl %eax, {{[0-9]+}}(%rsp) ; CHECK-NOT: movl %eax, {{[0-9]+}}(%rsp)
; CHECK: movl [[OFF:[0-9]+]](%rsp), %r8d ; CHECK: movl [[OFF:[0-9]+]](%rsp), %r8d
; CHECK: movl %eax, [[OFF]](%rsp)
; CHECK: movl $-1, %ecx ; CHECK: movl $-1, %ecx
; CHECK: movl %eax, [[OFF]](%rsp)
; CHECK: callq _ZN4llvm12SelectionDAG7getNodeEjNS_5SDLocENS_3EVTENS_7SDValueES3_ ; CHECK: callq _ZN4llvm12SelectionDAG7getNodeEjNS_5SDLocENS_3EVTENS_7SDValueES3_
%call18 = call { %"class.llvm::SDNode.10.610.970.1930.2050.2290.4090"*, i32 } @_ZN4llvm12SelectionDAG7getNodeEjNS_5SDLocENS_3EVTENS_7SDValueES3_(%"class.llvm::SelectionDAG.104.704.1064.2024.2144.2384.4184"* undef, i32 undef, i8* undef, i32 -1, i32 %retval.sroa.0.0.copyload.i37, %"class.llvm::Type.7.607.967.1927.2047.2287.4087"* undef, %"class.llvm::SDValue.3.603.963.1923.2043.2283.4083"* byval align 8 undef, %"class.llvm::SDValue.3.603.963.1923.2043.2283.4083"* byval align 8 undef) #1 %call18 = call { %"class.llvm::SDNode.10.610.970.1930.2050.2290.4090"*, i32 } @_ZN4llvm12SelectionDAG7getNodeEjNS_5SDLocENS_3EVTENS_7SDValueES3_(%"class.llvm::SelectionDAG.104.704.1064.2024.2144.2384.4184"* undef, i32 undef, i8* undef, i32 -1, i32 %retval.sroa.0.0.copyload.i37, %"class.llvm::Type.7.607.967.1927.2047.2287.4087"* undef, %"class.llvm::SDValue.3.603.963.1923.2043.2283.4083"* byval align 8 undef, %"class.llvm::SDValue.3.603.963.1923.2043.2283.4083"* byval align 8 undef) #1
ret { %"class.llvm::SDNode.10.610.970.1930.2050.2290.4090"*, i32 } %call18 ret { %"class.llvm::SDNode.10.610.970.1930.2050.2290.4090"*, i32 } %call18
} }
; Function Attrs: nounwind uwtable ; Function Attrs: nounwind uwtable
declare hidden %"class.llvm::SDValue.3.603.963.1923.2043.2283.4083"* @_ZN4llvm12DenseMapBaseINS_13SmallDenseMapINS_7SDValueES2_Lj8ENS_12DenseMapInfoIS2_EEEES2_S2_S4_EixERKS2_(%"class.llvm::DenseMapBase.73.118.718.1078.2038.2158.2398.4198"*, %"class.llvm::SDValue.3.603.963.1923.2043.2283.4083"* nocapture readonly) #2 align 2 declare hidden %"class.llvm::SDValue.3.603.963.1923.2043.2283.4083"* @_ZN4llvm12DenseMapBaseINS_13SmallDenseMapINS_7SDValueES2_Lj8ENS_12DenseMapInfoIS2_EEEES2_S2_S4_EixERKS2_(%"class.llvm::DenseMapBase.73.118.718.1078.2038.2158.2398.4198"*, %"class.llvm::SDValue.3.603.963.1923.2043.2283.4083"* nocapture readonly) #2 align 2
Show All 10 Lines

llvm/test/CodeGen/X86/misched-matrix.ll

; RUN: llc < %s -mtriple=x86_64-- -mcpu=core2 -pre-RA-sched=source -enable-misched \ ; RUN: llc < %s -mtriple=x86_64-- -mcpu=core2 -pre-RA-sched=source -enable-misched \
; RUN: -misched-topdown -verify-machineinstrs \ ; RUN: -misched-topdown -verify-machineinstrs \
; RUN: | FileCheck %s -check-prefix=TOPDOWN ; RUN: | FileCheck %s -check-prefix=TOPDOWN
; RUN: llc < %s -mtriple=x86_64-- -mcpu=core2 -pre-RA-sched=source -enable-misched \ ; RUN: llc < %s -mtriple=x86_64-- -mcpu=core2 -pre-RA-sched=source -enable-misched \
; RUN: -misched=ilpmin -verify-machineinstrs \ ; RUN: -misched=ilpmin -verify-machineinstrs -disable-post-ra \
; RUN: | FileCheck %s -check-prefix=ILPMIN ; RUN: | FileCheck %s -check-prefix=ILPMIN
; RUN: llc < %s -mtriple=x86_64-- -mcpu=core2 -pre-RA-sched=source -enable-misched \ ; RUN: llc < %s -mtriple=x86_64-- -mcpu=core2 -pre-RA-sched=source -enable-misched \
; RUN: -misched=ilpmax -verify-machineinstrs \ ; RUN: -misched=ilpmax -verify-machineinstrs -disable-post-ra \
; RUN: | FileCheck %s -check-prefix=ILPMAX ; RUN: | FileCheck %s -check-prefix=ILPMAX
; ;
; Verify that the MI scheduler minimizes register pressure for a ; Verify that the MI scheduler minimizes register pressure for a
; uniform set of bottom-up subtrees (unrolled matrix multiply). ; uniform set of bottom-up subtrees (unrolled matrix multiply).
; ;
; For current top-down heuristics, ensure that some folded imulls have ; For current top-down heuristics, ensure that some folded imulls have
; been reordered with the stores. This tests the scheduler's cheap ; been reordered with the stores. This tests the scheduler's cheap
; alias analysis ability (that doesn't require any AliasAnalysis pass). ; alias analysis ability (that doesn't require any AliasAnalysis pass).
▲ Show 20 Lines • Show All 175 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/misched-new.ll

Show All 10 Lines
; FIXME: There should be an assert in the coalescer that we're not rematting ; FIXME: There should be an assert in the coalescer that we're not rematting
; "not-quite-dead" copies, but that breaks a lot of tests <rdar://problem/11148682>. ; "not-quite-dead" copies, but that breaks a lot of tests <rdar://problem/11148682>.
declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i1) nounwind declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i1) nounwind
; From oggenc. ; From oggenc.
; After coalescing, we have a dead superreg (RAX) definition. ; After coalescing, we have a dead superreg (RAX) definition.
; ;
; CHECK: xorl %esi, %esi
; CHECK: movl $32, %ecx ; CHECK: movl $32, %ecx
; CHECK: xorl %esi, %esi
; CHECK: rep;movsl ; CHECK: rep;movsl
define fastcc void @_preextrapolate_helper() nounwind uwtable ssp { define fastcc void @_preextrapolate_helper() nounwind uwtable ssp {
entry: entry:
br i1 undef, label %for.cond.preheader, label %if.end br i1 undef, label %for.cond.preheader, label %if.end
for.cond.preheader: ; preds = %entry for.cond.preheader: ; preds = %entry
call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 undef, i8* align 4 null, i64 128, i1 false) nounwind call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 undef, i8* align 4 null, i64 128, i1 false) nounwind
unreachable unreachable
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llvm/test/CodeGen/X86/movgs.ll

Show First 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
} }
; The two loads here both look identical to selection DAG, except for their ; The two loads here both look identical to selection DAG, except for their
; address spaces. Make sure they aren't CSE'd. ; address spaces. Make sure they aren't CSE'd.
define i32 @test_no_cse() nounwind readonly { define i32 @test_no_cse() nounwind readonly {
; X32-LABEL: test_no_cse: ; X32-LABEL: test_no_cse:
; X32: # %bb.0: # %entry ; X32: # %bb.0: # %entry
; X32-NEXT: movl %gs:196, %eax ; X32-NEXT: movl %gs:196, %eax
; X32-NEXT: movl (%eax), %eax
; X32-NEXT: movl %fs:196, %ecx ; X32-NEXT: movl %fs:196, %ecx
; X32-NEXT: movl (%eax), %eax
; X32-NEXT: addl (%ecx), %eax ; X32-NEXT: addl (%ecx), %eax
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_no_cse: ; X64-LABEL: test_no_cse:
; X64: # %bb.0: # %entry ; X64: # %bb.0: # %entry
; X64-NEXT: movq %gs:320, %rax ; X64-NEXT: movq %gs:320, %rax
; X64-NEXT: movl (%rax), %eax
; X64-NEXT: movq %fs:320, %rcx ; X64-NEXT: movq %fs:320, %rcx
; X64-NEXT: movl (%rax), %eax
; X64-NEXT: addl (%rcx), %eax ; X64-NEXT: addl (%rcx), %eax
; X64-NEXT: retq ; X64-NEXT: retq
entry: entry:
%tmp = load i32*, i32* addrspace(256)* getelementptr (i32*, i32* addrspace(256)* inttoptr (i32 72 to i32* addrspace(256)*), i32 31) ; <i32*> [#uses=1] %tmp = load i32*, i32* addrspace(256)* getelementptr (i32*, i32* addrspace(256)* inttoptr (i32 72 to i32* addrspace(256)*), i32 31) ; <i32*> [#uses=1]
%tmp1 = load i32, i32* %tmp ; <i32> [#uses=1] %tmp1 = load i32, i32* %tmp ; <i32> [#uses=1]
%tmp2 = load i32*, i32* addrspace(257)* getelementptr (i32*, i32* addrspace(257)* inttoptr (i32 72 to i32* addrspace(257)*), i32 31) ; <i32*> [#uses=1] %tmp2 = load i32*, i32* addrspace(257)* getelementptr (i32*, i32* addrspace(257)* inttoptr (i32 72 to i32* addrspace(257)*), i32 31) ; <i32*> [#uses=1]
%tmp3 = load i32, i32* %tmp2 ; <i32> [#uses=1] %tmp3 = load i32, i32* %tmp2 ; <i32> [#uses=1]
%tmp4 = add i32 %tmp1, %tmp3 %tmp4 = add i32 %tmp1, %tmp3
ret i32 %tmp4 ret i32 %tmp4
} }

llvm/test/CodeGen/X86/patchpoint-webkit_jscc.ll

; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=corei7 < %s | FileCheck %s ; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=corei7 < %s | FileCheck %s
; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=corei7 -fast-isel -fast-isel-abort=1 < %s | FileCheck %s --check-prefix=FAST ; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=corei7 -fast-isel -fast-isel-abort=1 < %s | FileCheck %s --check-prefix=FAST
; Test the webkit_jscc calling convention. ; Test the webkit_jscc calling convention.
; One argument will be passed in register, the other will be pushed on the stack. ; One argument will be passed in register, the other will be pushed on the stack.
; Return value in $rax. ; Return value in $rax.
define void @jscall_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) { define void @jscall_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
entry: entry:
; CHECK-LABEL: jscall_patchpoint_codegen: ; CHECK-LABEL: jscall_patchpoint_codegen:
; CHECK: movq %r{{.+}}, (%rsp)
; CHECK: movq %r{{.+}}, %rax ; CHECK: movq %r{{.+}}, %rax
; CHECK: movq %r{{.+}}, (%rsp)
; CHECK: Ltmp ; CHECK: Ltmp
; CHECK-NEXT: movabsq $-559038736, %r11 ; CHECK-NEXT: movabsq $-559038736, %r11
; CHECK-NEXT: callq *%r11 ; CHECK-NEXT: callq *%r11
; CHECK: movq %rax, (%rsp) ; CHECK: movq %rax, (%rsp)
; CHECK: callq ; CHECK: callq
; FAST-LABEL: jscall_patchpoint_codegen: ; FAST-LABEL: jscall_patchpoint_codegen:
; FAST: movq %r{{.+}}, (%rsp)
; FAST: movq %r{{.+}}, %rax ; FAST: movq %r{{.+}}, %rax
; FAST: movq %r{{.+}}, (%rsp)
; FAST: Ltmp ; FAST: Ltmp
; FAST-NEXT: movabsq $-559038736, %r11 ; FAST-NEXT: movabsq $-559038736, %r11
; FAST-NEXT: callq *%r11 ; FAST-NEXT: callq *%r11
; FAST: movq %rax, (%rsp) ; FAST: movq %rax, (%rsp)
; FAST: callq ; FAST: callq
%resolveCall2 = inttoptr i64 -559038736 to i8* %resolveCall2 = inttoptr i64 -559038736 to i8*
%result = tail call webkit_jscc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 15, i8* %resolveCall2, i32 2, i64 %p4, i64 %p2) %result = tail call webkit_jscc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 15, i8* %resolveCall2, i32 2, i64 %p4, i64 %p2)
%resolveCall3 = inttoptr i64 -559038737 to i8* %resolveCall3 = inttoptr i64 -559038737 to i8*
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llvm/test/CodeGen/X86/patchpoint.ll

; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=corei7 < %s | FileCheck %s ; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=corei7 < %s | FileCheck %s
; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=corei7 -fast-isel -fast-isel-abort=1 < %s | FileCheck %s ; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=corei7 -fast-isel -fast-isel-abort=1 < %s | FileCheck %s
; Trivial patchpoint codegen ; Trivial patchpoint codegen
; ;
define i64 @trivial_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) { define i64 @trivial_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
entry: entry:
; CHECK-LABEL: trivial_patchpoint_codegen: ; CHECK-LABEL: trivial_patchpoint_codegen:
; CHECK: movabsq $-559038736, %r11 ; CHECK: movabsq $-559038736, %r11
; CHECK-NEXT: callq *%r11 ; CHECK-NEXT: callq *%r11
; CHECK-NEXT: xchgw %ax, %ax ; CHECK-NEXT: xchgw %ax, %ax
; CHECK: movq %rax, %[[REG:r.+]] ; CHECK: movq %rax, %rbx
; CHECK: callq *%r11 ; CHECK: callq *%r11
; CHECK-NEXT: xchgw %ax, %ax ; CHECK-NEXT: xchgw %ax, %ax
; CHECK: movq %[[REG]], %rax ; CHECK: movq %rbx, %rax
; CHECK: ret ; CHECK: ret
%resolveCall2 = inttoptr i64 -559038736 to i8* %resolveCall2 = inttoptr i64 -559038736 to i8*
%result = tail call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 15, i8* %resolveCall2, i32 4, i64 %p1, i64 %p2, i64 %p3, i64 %p4) %result = tail call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 15, i8* %resolveCall2, i32 4, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
%resolveCall3 = inttoptr i64 -559038737 to i8* %resolveCall3 = inttoptr i64 -559038737 to i8*
tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 3, i32 15, i8* %resolveCall3, i32 2, i64 %p1, i64 %result) tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 3, i32 15, i8* %resolveCall3, i32 2, i64 %p1, i64 %result)
ret i64 %result ret i64 %result
} }
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llvm/test/CodeGen/X86/pointer-vector.ll

Show First 20 Lines • Show All 122 Lines • ▼ Show 20 Linesentry:
%G = load <2 x i8*>, <2 x i8*>* %p %G = load <2 x i8*>, <2 x i8*>* %p
%T = bitcast <2 x i8*> %G to <2 x i32*> %T = bitcast <2 x i8*> %G to <2 x i32*>
ret <2 x i32*> %T ret <2 x i32*> %T
} }
define <4 x i32> @ICMP0(<4 x i8*>* %p0, <4 x i8*>* %p1) nounwind { define <4 x i32> @ICMP0(<4 x i8*>* %p0, <4 x i8*>* %p1) nounwind {
; CHECK-LABEL: ICMP0: ; CHECK-LABEL: ICMP0:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movaps {{.*#+}} xmm1 = [9,8,7,6]
; CHECK-NEXT: movdqa (%ecx), %xmm0 ; CHECK-NEXT: movdqa (%ecx), %xmm0
; CHECK-NEXT: pcmpgtd (%eax), %xmm0 ; CHECK-NEXT: pcmpgtd (%eax), %xmm0
; CHECK-NEXT: movaps {{.*#+}} xmm1 = [9,8,7,6]
; CHECK-NEXT: blendvps %xmm0, {{\.LCPI.*}}, %xmm1 ; CHECK-NEXT: blendvps %xmm0, {{\.LCPI.*}}, %xmm1
; CHECK-NEXT: movaps %xmm1, %xmm0 ; CHECK-NEXT: movaps %xmm1, %xmm0
; CHECK-NEXT: retl ; CHECK-NEXT: retl
entry: entry:
%g0 = load <4 x i8*>, <4 x i8*>* %p0 %g0 = load <4 x i8*>, <4 x i8*>* %p0
%g1 = load <4 x i8*>, <4 x i8*>* %p1 %g1 = load <4 x i8*>, <4 x i8*>* %p1
%k = icmp sgt <4 x i8*> %g0, %g1 %k = icmp sgt <4 x i8*> %g0, %g1
%j = select <4 x i1> %k, <4 x i32> <i32 0, i32 1, i32 2, i32 4>, <4 x i32> <i32 9, i32 8, i32 7, i32 6> %j = select <4 x i1> %k, <4 x i32> <i32 0, i32 1, i32 2, i32 4>, <4 x i32> <i32 9, i32 8, i32 7, i32 6>
ret <4 x i32> %j ret <4 x i32> %j
} }
define <4 x i32> @ICMP1(<4 x i8*>* %p0, <4 x i8*>* %p1) nounwind { define <4 x i32> @ICMP1(<4 x i8*>* %p0, <4 x i8*>* %p1) nounwind {
; CHECK-LABEL: ICMP1: ; CHECK-LABEL: ICMP1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movaps {{.*#+}} xmm1 = [9,8,7,6]
; CHECK-NEXT: movdqa (%ecx), %xmm0 ; CHECK-NEXT: movdqa (%ecx), %xmm0
; CHECK-NEXT: pcmpeqd (%eax), %xmm0 ; CHECK-NEXT: pcmpeqd (%eax), %xmm0
; CHECK-NEXT: movaps {{.*#+}} xmm1 = [9,8,7,6]
; CHECK-NEXT: blendvps %xmm0, {{\.LCPI.*}}, %xmm1 ; CHECK-NEXT: blendvps %xmm0, {{\.LCPI.*}}, %xmm1
; CHECK-NEXT: movaps %xmm1, %xmm0 ; CHECK-NEXT: movaps %xmm1, %xmm0
; CHECK-NEXT: retl ; CHECK-NEXT: retl
entry: entry:
%g0 = load <4 x i8*>, <4 x i8*>* %p0 %g0 = load <4 x i8*>, <4 x i8*>* %p0
%g1 = load <4 x i8*>, <4 x i8*>* %p1 %g1 = load <4 x i8*>, <4 x i8*>* %p1
%k = icmp eq <4 x i8*> %g0, %g1 %k = icmp eq <4 x i8*> %g0, %g1
%j = select <4 x i1> %k, <4 x i32> <i32 0, i32 1, i32 2, i32 4>, <4 x i32> <i32 9, i32 8, i32 7, i32 6> %j = select <4 x i1> %k, <4 x i32> <i32 0, i32 1, i32 2, i32 4>, <4 x i32> <i32 9, i32 8, i32 7, i32 6>
ret <4 x i32> %j ret <4 x i32> %j
} }

llvm/test/CodeGen/X86/post-ra-sched.ll

Show All 16 Lines
@idxa = common global i32 0, align 4 @idxa = common global i32 0, align 4
@idxb = common global i32 0, align 4 @idxb = common global i32 0, align 4
@res = common global i32 0, align 4 @res = common global i32 0, align 4
define void @addindirect() { define void @addindirect() {
; PENTIUM4-LABEL: addindirect: ; PENTIUM4-LABEL: addindirect:
; PENTIUM4: # %bb.0: # %entry ; PENTIUM4: # %bb.0: # %entry
; PENTIUM4-NEXT: movl idxa, %eax ; PENTIUM4-NEXT: movl idxa, %eax
; PENTIUM4-NEXT: movl ptrs(,%eax,4), %eax
; PENTIUM4-NEXT: movl idxb, %ecx ; PENTIUM4-NEXT: movl idxb, %ecx
; PENTIUM4-NEXT: movl ptrs(,%ecx,4), %ecx ; PENTIUM4-NEXT: movl ptrs(,%ecx,4), %ecx
; PENTIUM4-NEXT: movl ptrs(,%eax,4), %eax
; PENTIUM4-NEXT: movl (%ecx), %ecx ; PENTIUM4-NEXT: movl (%ecx), %ecx
; PENTIUM4-NEXT: addl (%eax), %ecx ; PENTIUM4-NEXT: addl (%eax), %ecx
; PENTIUM4-NEXT: movl %ecx, res ; PENTIUM4-NEXT: movl %ecx, res
; PENTIUM4-NEXT: retl ; PENTIUM4-NEXT: retl
; ;
; CHECK-LABEL: addindirect: ; CHECK-LABEL: addindirect:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl idxb, %ecx ; CHECK-NEXT: movl idxb, %ecx
Show All 20 Lines

llvm/test/CodeGen/X86/pow.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64 | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64 | FileCheck %s
declare float @llvm.pow.f32(float, float) declare float @llvm.pow.f32(float, float)
declare <4 x float> @llvm.pow.v4f32(<4 x float>, <4 x float>) declare <4 x float> @llvm.pow.v4f32(<4 x float>, <4 x float>)
declare double @llvm.pow.f64(double, double) declare double @llvm.pow.f64(double, double)
declare <2 x double> @llvm.pow.v2f64(<2 x double>, <2 x double>) declare <2 x double> @llvm.pow.v2f64(<2 x double>, <2 x double>)
declare x86_fp80 @llvm.pow.f80(x86_fp80, x86_fp80) declare x86_fp80 @llvm.pow.f80(x86_fp80, x86_fp80)
define float @pow_f32_one_fourth_fmf_ieee(float %x) nounwind { define float @pow_f32_one_fourth_fmf_ieee(float %x) nounwind {
; CHECK-LABEL: pow_f32_one_fourth_fmf_ieee: ; CHECK-LABEL: pow_f32_one_fourth_fmf_ieee:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: rsqrtss %xmm0, %xmm1 ; CHECK-NEXT: rsqrtss %xmm0, %xmm1
; CHECK-NEXT: movaps %xmm0, %xmm3 ; CHECK-NEXT: movaps %xmm0, %xmm3
; CHECK-NEXT: mulss %xmm1, %xmm3
; CHECK-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; CHECK-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; CHECK-NEXT: movss {{.*#+}} xmm5 = mem[0],zero,zero,zero
; CHECK-NEXT: movss {{.*#+}} xmm6 = mem[0],zero,zero,zero
; CHECK-NEXT: mulss %xmm1, %xmm3
; CHECK-NEXT: movaps %xmm3, %xmm4 ; CHECK-NEXT: movaps %xmm3, %xmm4
; CHECK-NEXT: mulss %xmm2, %xmm4
; CHECK-NEXT: mulss %xmm1, %xmm3 ; CHECK-NEXT: mulss %xmm1, %xmm3
; CHECK-NEXT: movss {{.*#+}} xmm5 = mem[0],zero,zero,zero
; CHECK-NEXT: addss %xmm5, %xmm3
; CHECK-NEXT: mulss %xmm4, %xmm3
; CHECK-NEXT: movaps {{.*#+}} xmm1 = [NaN,NaN,NaN,NaN] ; CHECK-NEXT: movaps {{.*#+}} xmm1 = [NaN,NaN,NaN,NaN]
; CHECK-NEXT: mulss %xmm2, %xmm4
; CHECK-NEXT: addss %xmm5, %xmm3
; CHECK-NEXT: andps %xmm1, %xmm0 ; CHECK-NEXT: andps %xmm1, %xmm0
; CHECK-NEXT: movss {{.*#+}} xmm4 = mem[0],zero,zero,zero ; CHECK-NEXT: cmpltss %xmm6, %xmm0
; CHECK-NEXT: cmpltss %xmm4, %xmm0 ; CHECK-NEXT: mulss %xmm4, %xmm3
; CHECK-NEXT: andnps %xmm3, %xmm0 ; CHECK-NEXT: andnps %xmm3, %xmm0
; CHECK-NEXT: xorps %xmm3, %xmm3 ; CHECK-NEXT: xorps %xmm3, %xmm3
; CHECK-NEXT: rsqrtss %xmm0, %xmm3 ; CHECK-NEXT: rsqrtss %xmm0, %xmm3
; CHECK-NEXT: andps %xmm0, %xmm1 ; CHECK-NEXT: andps %xmm0, %xmm1
; CHECK-NEXT: cmpltss %xmm6, %xmm1
; CHECK-NEXT: mulss %xmm3, %xmm0 ; CHECK-NEXT: mulss %xmm3, %xmm0
; CHECK-NEXT: mulss %xmm0, %xmm2 ; CHECK-NEXT: mulss %xmm0, %xmm2
; CHECK-NEXT: mulss %xmm3, %xmm0 ; CHECK-NEXT: mulss %xmm3, %xmm0
; CHECK-NEXT: addss %xmm5, %xmm0 ; CHECK-NEXT: addss %xmm5, %xmm0
; CHECK-NEXT: mulss %xmm2, %xmm0 ; CHECK-NEXT: mulss %xmm2, %xmm0
; CHECK-NEXT: cmpltss %xmm4, %xmm1
; CHECK-NEXT: andnps %xmm0, %xmm1 ; CHECK-NEXT: andnps %xmm0, %xmm1
; CHECK-NEXT: movaps %xmm1, %xmm0 ; CHECK-NEXT: movaps %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%r = call nsz ninf afn float @llvm.pow.f32(float %x, float 2.5e-01) %r = call nsz ninf afn float @llvm.pow.f32(float %x, float 2.5e-01)
ret float %r ret float %r
} }
define float @pow_f32_one_fourth_fmf_daz(float %x) #0 { define float @pow_f32_one_fourth_fmf_daz(float %x) #0 {
; CHECK-LABEL: pow_f32_one_fourth_fmf_daz: ; CHECK-LABEL: pow_f32_one_fourth_fmf_daz:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: rsqrtss %xmm0, %xmm1 ; CHECK-NEXT: rsqrtss %xmm0, %xmm1
; CHECK-NEXT: movaps %xmm0, %xmm2 ; CHECK-NEXT: movaps %xmm0, %xmm2
; CHECK-NEXT: mulss %xmm1, %xmm2
; CHECK-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero ; CHECK-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
; CHECK-NEXT: movss {{.*#+}} xmm6 = mem[0],zero,zero,zero
; CHECK-NEXT: mulss %xmm1, %xmm2
; CHECK-NEXT: movaps %xmm2, %xmm4 ; CHECK-NEXT: movaps %xmm2, %xmm4
; CHECK-NEXT: mulss %xmm3, %xmm4
; CHECK-NEXT: mulss %xmm1, %xmm2 ; CHECK-NEXT: mulss %xmm1, %xmm2
; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; CHECK-NEXT: mulss %xmm3, %xmm4
; CHECK-NEXT: addss %xmm1, %xmm2 ; CHECK-NEXT: addss %xmm6, %xmm2
; CHECK-NEXT: mulss %xmm4, %xmm2 ; CHECK-NEXT: mulss %xmm4, %xmm2
; CHECK-NEXT: xorps %xmm4, %xmm4 ; CHECK-NEXT: xorps %xmm4, %xmm4
; CHECK-NEXT: cmpeqss %xmm4, %xmm0 ; CHECK-NEXT: cmpeqss %xmm4, %xmm0
; CHECK-NEXT: andnps %xmm2, %xmm0 ; CHECK-NEXT: andnps %xmm2, %xmm0
; CHECK-NEXT: xorps %xmm2, %xmm2 ; CHECK-NEXT: xorps %xmm2, %xmm2
; CHECK-NEXT: rsqrtss %xmm0, %xmm2 ; CHECK-NEXT: rsqrtss %xmm0, %xmm2
; CHECK-NEXT: movaps %xmm0, %xmm5 ; CHECK-NEXT: movaps %xmm0, %xmm5
; CHECK-NEXT: cmpeqss %xmm4, %xmm0
; CHECK-NEXT: mulss %xmm2, %xmm5 ; CHECK-NEXT: mulss %xmm2, %xmm5
; CHECK-NEXT: mulss %xmm5, %xmm3 ; CHECK-NEXT: mulss %xmm5, %xmm3
; CHECK-NEXT: mulss %xmm2, %xmm5 ; CHECK-NEXT: mulss %xmm2, %xmm5
; CHECK-NEXT: addss %xmm1, %xmm5 ; CHECK-NEXT: addss %xmm6, %xmm5
; CHECK-NEXT: mulss %xmm3, %xmm5 ; CHECK-NEXT: mulss %xmm3, %xmm5
; CHECK-NEXT: cmpeqss %xmm4, %xmm0
; CHECK-NEXT: andnps %xmm5, %xmm0 ; CHECK-NEXT: andnps %xmm5, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%r = call nsz ninf afn float @llvm.pow.f32(float %x, float 2.5e-01) %r = call nsz ninf afn float @llvm.pow.f32(float %x, float 2.5e-01)
ret float %r ret float %r
} }
define double @pow_f64_one_fourth_fmf(double %x) nounwind { define double @pow_f64_one_fourth_fmf(double %x) nounwind {
; CHECK-LABEL: pow_f64_one_fourth_fmf: ; CHECK-LABEL: pow_f64_one_fourth_fmf:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: sqrtsd %xmm0, %xmm0 ; CHECK-NEXT: sqrtsd %xmm0, %xmm0
; CHECK-NEXT: sqrtsd %xmm0, %xmm0 ; CHECK-NEXT: sqrtsd %xmm0, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%r = call nsz ninf afn double @llvm.pow.f64(double %x, double 2.5e-01) %r = call nsz ninf afn double @llvm.pow.f64(double %x, double 2.5e-01)
ret double %r ret double %r
} }
define <4 x float> @pow_v4f32_one_fourth_fmf(<4 x float> %x) nounwind { define <4 x float> @pow_v4f32_one_fourth_fmf(<4 x float> %x) nounwind {
; CHECK-LABEL: pow_v4f32_one_fourth_fmf: ; CHECK-LABEL: pow_v4f32_one_fourth_fmf:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: rsqrtps %xmm0, %xmm1 ; CHECK-NEXT: rsqrtps %xmm0, %xmm1
; CHECK-NEXT: movaps %xmm0, %xmm2 ; CHECK-NEXT: movaps %xmm0, %xmm2
; CHECK-NEXT: mulps %xmm1, %xmm2
; CHECK-NEXT: movaps {{.*#+}} xmm3 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1] ; CHECK-NEXT: movaps {{.*#+}} xmm3 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
; CHECK-NEXT: movaps {{.*#+}} xmm5 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0]
; CHECK-NEXT: movaps {{.*#+}} xmm7 = [NaN,NaN,NaN,NaN]
; CHECK-NEXT: mulps %xmm1, %xmm2
; CHECK-NEXT: andps %xmm7, %xmm0
; CHECK-NEXT: movaps %xmm2, %xmm4 ; CHECK-NEXT: movaps %xmm2, %xmm4
; CHECK-NEXT: mulps %xmm3, %xmm4
; CHECK-NEXT: mulps %xmm1, %xmm2 ; CHECK-NEXT: mulps %xmm1, %xmm2
; CHECK-NEXT: movaps {{.*#+}} xmm5 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0]
; CHECK-NEXT: addps %xmm5, %xmm2
; CHECK-NEXT: mulps %xmm4, %xmm2
; CHECK-NEXT: movaps {{.*#+}} xmm4 = [NaN,NaN,NaN,NaN]
; CHECK-NEXT: andps %xmm4, %xmm0
; CHECK-NEXT: movaps {{.*#+}} xmm1 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38] ; CHECK-NEXT: movaps {{.*#+}} xmm1 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38]
; CHECK-NEXT: mulps %xmm3, %xmm4
; CHECK-NEXT: addps %xmm5, %xmm2
; CHECK-NEXT: movaps %xmm1, %xmm6 ; CHECK-NEXT: movaps %xmm1, %xmm6
; CHECK-NEXT: cmpleps %xmm0, %xmm6 ; CHECK-NEXT: cmpleps %xmm0, %xmm6
; CHECK-NEXT: mulps %xmm4, %xmm2
; CHECK-NEXT: andps %xmm2, %xmm6 ; CHECK-NEXT: andps %xmm2, %xmm6
; CHECK-NEXT: rsqrtps %xmm6, %xmm0 ; CHECK-NEXT: rsqrtps %xmm6, %xmm0
; CHECK-NEXT: movaps %xmm6, %xmm2 ; CHECK-NEXT: movaps %xmm6, %xmm2
; CHECK-NEXT: andps %xmm7, %xmm6
; CHECK-NEXT: cmpleps %xmm6, %xmm1
; CHECK-NEXT: mulps %xmm0, %xmm2 ; CHECK-NEXT: mulps %xmm0, %xmm2
; CHECK-NEXT: mulps %xmm2, %xmm3 ; CHECK-NEXT: mulps %xmm2, %xmm3
; CHECK-NEXT: mulps %xmm0, %xmm2 ; CHECK-NEXT: mulps %xmm0, %xmm2
; CHECK-NEXT: addps %xmm5, %xmm2 ; CHECK-NEXT: addps %xmm5, %xmm2
; CHECK-NEXT: mulps %xmm3, %xmm2 ; CHECK-NEXT: mulps %xmm3, %xmm2
; CHECK-NEXT: andps %xmm4, %xmm6
; CHECK-NEXT: cmpleps %xmm6, %xmm1
; CHECK-NEXT: andps %xmm2, %xmm1 ; CHECK-NEXT: andps %xmm2, %xmm1
; CHECK-NEXT: movaps %xmm1, %xmm0 ; CHECK-NEXT: movaps %xmm1, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%r = call fast <4 x float> @llvm.pow.v4f32(<4 x float> %x, <4 x float> <float 2.5e-1, float 2.5e-1, float 2.5e-01, float 2.5e-01>) %r = call fast <4 x float> @llvm.pow.v4f32(<4 x float> %x, <4 x float> <float 2.5e-1, float 2.5e-1, float 2.5e-01, float 2.5e-01>)
ret <4 x float> %r ret <4 x float> %r
} }
define <2 x double> @pow_v2f64_one_fourth_fmf(<2 x double> %x) nounwind { define <2 x double> @pow_v2f64_one_fourth_fmf(<2 x double> %x) nounwind {
Show All 23 Lines; CHECK-NEXT: jmp pow # TAILCALL
%r = call nsz ninf double @llvm.pow.f64(double %x, double 2.5e-01) %r = call nsz ninf double @llvm.pow.f64(double %x, double 2.5e-01)
ret double %r ret double %r
} }
define <4 x float> @pow_v4f32_one_fourth_not_enough_fmf(<4 x float> %x) nounwind { define <4 x float> @pow_v4f32_one_fourth_not_enough_fmf(<4 x float> %x) nounwind {
; CHECK-LABEL: pow_v4f32_one_fourth_not_enough_fmf: ; CHECK-LABEL: pow_v4f32_one_fourth_not_enough_fmf:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: subq $56, %rsp ; CHECK-NEXT: subq $56, %rsp
; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1,2,3] ; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1,2,3]
; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; CHECK-NEXT: callq powf ; CHECK-NEXT: callq powf
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill ; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: callq powf ; CHECK-NEXT: callq powf
; CHECK-NEXT: unpcklps (%rsp), %xmm0 # 16-byte Folded Reload ; CHECK-NEXT: unpcklps (%rsp), %xmm0 # 16-byte Folded Reload
; CHECK-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1] ; CHECK-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill ; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; CHECK-NEXT: callq powf ; CHECK-NEXT: callq powf
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,2,3]
; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,2,3]
; CHECK-NEXT: callq powf ; CHECK-NEXT: callq powf
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; CHECK-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; CHECK-NEXT: unpcklpd (%rsp), %xmm1 # 16-byte Folded Reload ; CHECK-NEXT: unpcklpd (%rsp), %xmm1 # 16-byte Folded Reload
; CHECK-NEXT: # xmm1 = xmm1[0],mem[0] ; CHECK-NEXT: # xmm1 = xmm1[0],mem[0]
; CHECK-NEXT: movaps %xmm1, %xmm0 ; CHECK-NEXT: movaps %xmm1, %xmm0
; CHECK-NEXT: addq $56, %rsp ; CHECK-NEXT: addq $56, %rsp
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%r = call afn nsz <4 x float> @llvm.pow.v4f32(<4 x float> %x, <4 x float> <float 2.5e-1, float 2.5e-1, float 2.5e-01, float 2.5e-01>) %r = call afn nsz <4 x float> @llvm.pow.v4f32(<4 x float> %x, <4 x float> <float 2.5e-1, float 2.5e-1, float 2.5e-01, float 2.5e-01>)
ret <4 x float> %r ret <4 x float> %r
} }
define <2 x double> @pow_v2f64_one_fourth_not_enough_fmf(<2 x double> %x) nounwind { define <2 x double> @pow_v2f64_one_fourth_not_enough_fmf(<2 x double> %x) nounwind {
; CHECK-LABEL: pow_v2f64_one_fourth_not_enough_fmf: ; CHECK-LABEL: pow_v2f64_one_fourth_not_enough_fmf:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: subq $40, %rsp ; CHECK-NEXT: subq $40, %rsp
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; CHECK-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
; CHECK-NEXT: callq pow ; CHECK-NEXT: callq pow
; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload ; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; CHECK-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: callq pow ; CHECK-NEXT: callq pow
; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0]
; CHECK-NEXT: movaps %xmm1, %xmm0 ; CHECK-NEXT: movaps %xmm1, %xmm0
; CHECK-NEXT: addq $40, %rsp ; CHECK-NEXT: addq $40, %rsp
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%r = call nsz nnan reassoc <2 x double> @llvm.pow.v2f64(<2 x double> %x, <2 x double> <double 2.5e-1, double 2.5e-1>) %r = call nsz nnan reassoc <2 x double> @llvm.pow.v2f64(<2 x double> %x, <2 x double> <double 2.5e-1, double 2.5e-1>)
ret <2 x double> %r ret <2 x double> %r
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llvm/test/CodeGen/X86/pr11334.ll

Show All 17 Lines
} }
define <3 x double> @v3f2d_ext_vec(<3 x float> %v1) nounwind { define <3 x double> @v3f2d_ext_vec(<3 x float> %v1) nounwind {
; SSE-LABEL: v3f2d_ext_vec: ; SSE-LABEL: v3f2d_ext_vec:
; SSE: # %bb.0: # %entry ; SSE: # %bb.0: # %entry
; SSE-NEXT: cvtps2pd %xmm0, %xmm2 ; SSE-NEXT: cvtps2pd %xmm0, %xmm2
; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE-NEXT: cvtps2pd %xmm0, %xmm0 ; SSE-NEXT: cvtps2pd %xmm0, %xmm0
; SSE-NEXT: movlps %xmm0, -{{[0-9]+}}(%rsp)
; SSE-NEXT: movaps %xmm2, %xmm1 ; SSE-NEXT: movaps %xmm2, %xmm1
; SSE-NEXT: movlps %xmm0, -{{[0-9]+}}(%rsp)
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm2[1] ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm2[1]
; SSE-NEXT: fldl -{{[0-9]+}}(%rsp)
; SSE-NEXT: movaps %xmm2, %xmm0 ; SSE-NEXT: movaps %xmm2, %xmm0
; SSE-NEXT: fldl -{{[0-9]+}}(%rsp)
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: v3f2d_ext_vec: ; AVX-LABEL: v3f2d_ext_vec:
; AVX: # %bb.0: # %entry ; AVX: # %bb.0: # %entry
; AVX-NEXT: vcvtps2pd %xmm0, %ymm0 ; AVX-NEXT: vcvtps2pd %xmm0, %ymm0
; AVX-NEXT: retq ; AVX-NEXT: retq
entry: entry:
%f1 = fpext <3 x float> %v1 to <3 x double> %f1 = fpext <3 x float> %v1 to <3 x double>
Show All 17 Linesentry:
%f1 = fpext <4 x float> %v1 to <4 x double> %f1 = fpext <4 x float> %v1 to <4 x double>
ret <4 x double> %f1 ret <4 x double> %f1
} }
define <8 x double> @v8f2d_ext_vec(<8 x float> %v1) nounwind { define <8 x double> @v8f2d_ext_vec(<8 x float> %v1) nounwind {
; SSE-LABEL: v8f2d_ext_vec: ; SSE-LABEL: v8f2d_ext_vec:
; SSE: # %bb.0: # %entry ; SSE: # %bb.0: # %entry
; SSE-NEXT: cvtps2pd %xmm0, %xmm5 ; SSE-NEXT: cvtps2pd %xmm0, %xmm5
; SSE-NEXT: cvtps2pd %xmm1, %xmm2
; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1] ; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE-NEXT: cvtps2pd %xmm0, %xmm4 ; SSE-NEXT: cvtps2pd %xmm1, %xmm2
; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1] ; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
; SSE-NEXT: cvtps2pd %xmm0, %xmm4
; SSE-NEXT: cvtps2pd %xmm1, %xmm3 ; SSE-NEXT: cvtps2pd %xmm1, %xmm3
; SSE-NEXT: movaps %xmm5, %xmm0 ; SSE-NEXT: movaps %xmm5, %xmm0
; SSE-NEXT: movaps %xmm4, %xmm1 ; SSE-NEXT: movaps %xmm4, %xmm1
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: v8f2d_ext_vec: ; AVX-LABEL: v8f2d_ext_vec:
; AVX: # %bb.0: # %entry ; AVX: # %bb.0: # %entry
; AVX-NEXT: vcvtps2pd %xmm0, %ymm2 ; AVX-NEXT: vcvtps2pd %xmm0, %ymm2
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llvm/test/CodeGen/X86/pr14088.ll

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; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl $-1, %eax ; CHECK-NEXT: movl $-1, %eax
; CHECK-NEXT: testb $1, %dil ; CHECK-NEXT: testb $1, %dil
; CHECK-NEXT: jne .LBB0_2 ; CHECK-NEXT: jne .LBB0_2
; CHECK-NEXT: # %bb.1: # %if.end ; CHECK-NEXT: # %bb.1: # %if.end
; CHECK-NEXT: movslq %r8d, %rax ; CHECK-NEXT: movslq %r8d, %rax
; CHECK-NEXT: imulq $1374389535, %rax, %rcx # imm = 0x51EB851F ; CHECK-NEXT: imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
; CHECK-NEXT: movq %rcx, %rdi ; CHECK-NEXT: movq %rcx, %rdi
; CHECK-NEXT: shrq $63, %rdi
; CHECK-NEXT: sarq $37, %rcx ; CHECK-NEXT: sarq $37, %rcx
; CHECK-NEXT: shrq $63, %rdi
; CHECK-NEXT: addl %edi, %ecx ; CHECK-NEXT: addl %edi, %ecx
; CHECK-NEXT: imull $100, %ecx, %ecx ; CHECK-NEXT: imull $100, %ecx, %ecx
; CHECK-NEXT: subl %ecx, %eax ; CHECK-NEXT: subl %ecx, %eax
; CHECK-NEXT: movw %ax, (%rsi) ; CHECK-NEXT: movw %ax, (%rsi)
; CHECK-NEXT: cwtl ; CHECK-NEXT: cwtl
; CHECK-NEXT: cltq ; CHECK-NEXT: cltq
; CHECK-NEXT: imulq $1717986919, %rax, %rax # imm = 0x66666667 ; CHECK-NEXT: imulq $1717986919, %rax, %rax # imm = 0x66666667
; CHECK-NEXT: movq %rax, %rcx ; CHECK-NEXT: movq %rax, %rcx
; CHECK-NEXT: shrq $63, %rcx
; CHECK-NEXT: shrq $34, %rax ; CHECK-NEXT: shrq $34, %rax
; CHECK-NEXT: shrq $63, %rcx
; CHECK-NEXT: addl %ecx, %eax ; CHECK-NEXT: addl %ecx, %eax
; CHECK-NEXT: movb %al, (%rdx) ; CHECK-NEXT: movb %al, (%rdx)
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: .LBB0_2: # %return ; CHECK-NEXT: .LBB0_2: # %return
; CHECK-NEXT: retq ; CHECK-NEXT: retq
entry: entry:
br i1 %foo, label %return, label %if.end br i1 %foo, label %return, label %if.end
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llvm/test/CodeGen/X86/pr14314.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i386-pc-linux -mcpu=corei7 | FileCheck %s ; RUN: llc < %s -mtriple=i386-pc-linux -mcpu=corei7 | FileCheck %s
define i64 @atomicSub(i64* %a, i64 %b) nounwind { define i64 @atomicSub(i64* %a, i64 %b) nounwind {
; CHECK-LABEL: atomicSub: ; CHECK-LABEL: atomicSub:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushl %ebp ; CHECK-NEXT: pushl %ebp
; CHECK-NEXT: pushl %ebx ; CHECK-NEXT: pushl %ebx
; CHECK-NEXT: pushl %edi ; CHECK-NEXT: pushl %edi
; CHECK-NEXT: pushl %esi ; CHECK-NEXT: pushl %esi
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ebp
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edi ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edi
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ebp
; CHECK-NEXT: movl (%ebp), %eax ; CHECK-NEXT: movl (%ebp), %eax
; CHECK-NEXT: movl 4(%ebp), %edx ; CHECK-NEXT: movl 4(%ebp), %edx
; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_1: # %atomicrmw.start ; CHECK-NEXT: .LBB0_1: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movl %eax, %ebx ; CHECK-NEXT: movl %eax, %ebx
; CHECK-NEXT: subl %edi, %ebx
; CHECK-NEXT: movl %edx, %ecx ; CHECK-NEXT: movl %edx, %ecx
; CHECK-NEXT: subl %edi, %ebx
; CHECK-NEXT: sbbl %esi, %ecx ; CHECK-NEXT: sbbl %esi, %ecx
; CHECK-NEXT: lock cmpxchg8b (%ebp) ; CHECK-NEXT: lock cmpxchg8b (%ebp)
; CHECK-NEXT: jne .LBB0_1 ; CHECK-NEXT: jne .LBB0_1
; CHECK-NEXT: # %bb.2: # %atomicrmw.end ; CHECK-NEXT: # %bb.2: # %atomicrmw.end
; CHECK-NEXT: popl %esi ; CHECK-NEXT: popl %esi
; CHECK-NEXT: popl %edi ; CHECK-NEXT: popl %edi
; CHECK-NEXT: popl %ebx ; CHECK-NEXT: popl %ebx
; CHECK-NEXT: popl %ebp ; CHECK-NEXT: popl %ebp
; CHECK-NEXT: retl ; CHECK-NEXT: retl
entry: entry:
%0 = atomicrmw sub i64* %a, i64 %b seq_cst %0 = atomicrmw sub i64* %a, i64 %b seq_cst
ret i64 %0 ret i64 %0
} }

llvm/test/CodeGen/X86/pr15267.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=corei7-avx | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=corei7-avx | FileCheck %s
define <4 x i3> @test1(<4 x i3>* %in) nounwind { define <4 x i3> @test1(<4 x i3>* %in) nounwind {
; CHECK-LABEL: test1: ; CHECK-LABEL: test1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: movzwl (%rdi), %eax ; CHECK-NEXT: movzwl (%rdi), %eax
; CHECK-NEXT: movl %eax, %ecx ; CHECK-NEXT: movl %eax, %ecx
; CHECK-NEXT: shrl $3, %ecx
; CHECK-NEXT: andl $7, %ecx
; CHECK-NEXT: movl %eax, %edx ; CHECK-NEXT: movl %eax, %edx
; CHECK-NEXT: shrl $3, %ecx
; CHECK-NEXT: andl $7, %edx ; CHECK-NEXT: andl $7, %edx
; CHECK-NEXT: vmovd %edx, %xmm0 ; CHECK-NEXT: vmovd %edx, %xmm0
; CHECK-NEXT: vpinsrw $2, %ecx, %xmm0, %xmm0 ; CHECK-NEXT: movl %eax, %edx
; CHECK-NEXT: movl %eax, %ecx
; CHECK-NEXT: shrl $6, %ecx
; CHECK-NEXT: andl $7, %ecx ; CHECK-NEXT: andl $7, %ecx
; CHECK-NEXT: vpinsrw $4, %ecx, %xmm0, %xmm0
; CHECK-NEXT: shrl $9, %eax ; CHECK-NEXT: shrl $9, %eax
; CHECK-NEXT: shrl $6, %edx
; CHECK-NEXT: vpinsrw $2, %ecx, %xmm0, %xmm0
; CHECK-NEXT: andl $7, %eax ; CHECK-NEXT: andl $7, %eax
; CHECK-NEXT: andl $7, %edx
; CHECK-NEXT: vpinsrw $4, %edx, %xmm0, %xmm0
; CHECK-NEXT: vpinsrw $6, %eax, %xmm0, %xmm0 ; CHECK-NEXT: vpinsrw $6, %eax, %xmm0, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%ret = load <4 x i3>, <4 x i3>* %in, align 1 %ret = load <4 x i3>, <4 x i3>* %in, align 1
ret <4 x i3> %ret ret <4 x i3> %ret
} }
define <4 x i1> @test2(<4 x i1>* %in) nounwind { define <4 x i1> @test2(<4 x i1>* %in) nounwind {
; CHECK-LABEL: test2: ; CHECK-LABEL: test2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: movb (%rdi), %al ; CHECK-NEXT: movb (%rdi), %al
; CHECK-NEXT: movl %eax, %ecx ; CHECK-NEXT: movl %eax, %ecx
; CHECK-NEXT: shrb %cl
; CHECK-NEXT: andb $1, %cl
; CHECK-NEXT: movzbl %cl, %ecx
; CHECK-NEXT: movl %eax, %edx ; CHECK-NEXT: movl %eax, %edx
; CHECK-NEXT: andb $1, %dl ; CHECK-NEXT: andb $1, %dl
; CHECK-NEXT: shrb %cl
; CHECK-NEXT: andb $1, %cl
; CHECK-NEXT: movzbl %dl, %edx ; CHECK-NEXT: movzbl %dl, %edx
; CHECK-NEXT: movzbl %cl, %ecx
; CHECK-NEXT: vmovd %edx, %xmm0 ; CHECK-NEXT: vmovd %edx, %xmm0
; CHECK-NEXT: vpinsrb $4, %ecx, %xmm0, %xmm0 ; CHECK-NEXT: vpinsrb $4, %ecx, %xmm0, %xmm0
; CHECK-NEXT: movl %eax, %ecx ; CHECK-NEXT: movl %eax, %ecx
; CHECK-NEXT: shrb $3, %al
; CHECK-NEXT: shrb $2, %cl ; CHECK-NEXT: shrb $2, %cl
; CHECK-NEXT: movzbl %al, %eax
; CHECK-NEXT: andb $1, %cl ; CHECK-NEXT: andb $1, %cl
; CHECK-NEXT: movzbl %cl, %ecx ; CHECK-NEXT: movzbl %cl, %ecx
; CHECK-NEXT: vpinsrb $8, %ecx, %xmm0, %xmm0 ; CHECK-NEXT: vpinsrb $8, %ecx, %xmm0, %xmm0
; CHECK-NEXT: shrb $3, %al
; CHECK-NEXT: movzbl %al, %eax
; CHECK-NEXT: vpinsrb $12, %eax, %xmm0, %xmm0 ; CHECK-NEXT: vpinsrb $12, %eax, %xmm0, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%ret = load <4 x i1>, <4 x i1>* %in, align 1 %ret = load <4 x i1>, <4 x i1>* %in, align 1
ret <4 x i1> %ret ret <4 x i1> %ret
} }
define <4 x i64> @test3(<4 x i1>* %in) nounwind { define <4 x i64> @test3(<4 x i1>* %in) nounwind {
; CHECK-LABEL: test3: ; CHECK-LABEL: test3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: movb (%rdi), %al ; CHECK-NEXT: movb (%rdi), %al
; CHECK-NEXT: movzbl %al, %ecx ; CHECK-NEXT: movzbl %al, %ecx
; CHECK-NEXT: shrb %al ; CHECK-NEXT: shrb %al
; CHECK-NEXT: movzbl %al, %eax
; CHECK-NEXT: andl $1, %eax
; CHECK-NEXT: negl %eax
; CHECK-NEXT: movl %ecx, %edx ; CHECK-NEXT: movl %ecx, %edx
; CHECK-NEXT: movzbl %al, %eax
; CHECK-NEXT: andl $1, %edx ; CHECK-NEXT: andl $1, %edx
; CHECK-NEXT: andl $1, %eax
; CHECK-NEXT: negl %edx ; CHECK-NEXT: negl %edx
; CHECK-NEXT: negl %eax
; CHECK-NEXT: vmovd %edx, %xmm0 ; CHECK-NEXT: vmovd %edx, %xmm0
; CHECK-NEXT: vpinsrd $1, %eax, %xmm0, %xmm0 ; CHECK-NEXT: vpinsrd $1, %eax, %xmm0, %xmm0
; CHECK-NEXT: movl %ecx, %eax ; CHECK-NEXT: movl %ecx, %eax
; CHECK-NEXT: shrb $3, %cl
; CHECK-NEXT: shrb $2, %al ; CHECK-NEXT: shrb $2, %al
; CHECK-NEXT: movzbl %cl, %edx
; CHECK-NEXT: movzbl %al, %eax ; CHECK-NEXT: movzbl %al, %eax
; CHECK-NEXT: negl %edx
; CHECK-NEXT: andl $1, %eax ; CHECK-NEXT: andl $1, %eax
; CHECK-NEXT: negl %eax ; CHECK-NEXT: negl %eax
; CHECK-NEXT: vpinsrd $2, %eax, %xmm0, %xmm0 ; CHECK-NEXT: vpinsrd $2, %eax, %xmm0, %xmm0
; CHECK-NEXT: shrb $3, %cl ; CHECK-NEXT: vpinsrd $3, %edx, %xmm0, %xmm0
; CHECK-NEXT: movzbl %cl, %eax
; CHECK-NEXT: negl %eax
; CHECK-NEXT: vpinsrd $3, %eax, %xmm0, %xmm0
; CHECK-NEXT: vpmovsxdq %xmm0, %xmm1 ; CHECK-NEXT: vpmovsxdq %xmm0, %xmm1
; CHECK-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] ; CHECK-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
; CHECK-NEXT: vpmovsxdq %xmm0, %xmm0 ; CHECK-NEXT: vpmovsxdq %xmm0, %xmm0
; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%wide.load35 = load <4 x i1>, <4 x i1>* %in, align 1 %wide.load35 = load <4 x i1>, <4 x i1>* %in, align 1
%sext = sext <4 x i1> %wide.load35 to <4 x i64> %sext = sext <4 x i1> %wide.load35 to <4 x i64>
ret <4 x i64> %sext ret <4 x i64> %sext
} }
define <16 x i4> @test4(<16 x i4>* %in) nounwind { define <16 x i4> @test4(<16 x i4>* %in) nounwind {
; CHECK-LABEL: test4: ; CHECK-LABEL: test4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: movq (%rdi), %rax ; CHECK-NEXT: movq (%rdi), %rax
; CHECK-NEXT: movl %eax, %ecx ; CHECK-NEXT: movl %eax, %ecx
; CHECK-NEXT: shrl $4, %ecx
; CHECK-NEXT: andl $15, %ecx
; CHECK-NEXT: movl %eax, %edx ; CHECK-NEXT: movl %eax, %edx
; CHECK-NEXT: shrl $4, %ecx
; CHECK-NEXT: andl $15, %edx ; CHECK-NEXT: andl $15, %edx
; CHECK-NEXT: andl $15, %ecx
; CHECK-NEXT: vmovd %edx, %xmm0 ; CHECK-NEXT: vmovd %edx, %xmm0
; CHECK-NEXT: vpinsrb $1, %ecx, %xmm0, %xmm0 ; CHECK-NEXT: vpinsrb $1, %ecx, %xmm0, %xmm0
; CHECK-NEXT: movl %eax, %ecx ; CHECK-NEXT: movl %eax, %ecx
; CHECK-NEXT: shrl $8, %ecx ; CHECK-NEXT: shrl $8, %ecx
; CHECK-NEXT: andl $15, %ecx ; CHECK-NEXT: andl $15, %ecx
; CHECK-NEXT: vpinsrb $2, %ecx, %xmm0, %xmm0 ; CHECK-NEXT: vpinsrb $2, %ecx, %xmm0, %xmm0
; CHECK-NEXT: movl %eax, %ecx ; CHECK-NEXT: movl %eax, %ecx
; CHECK-NEXT: shrl $12, %ecx ; CHECK-NEXT: shrl $12, %ecx
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; CHECK-NEXT: shrq $48, %rcx ; CHECK-NEXT: shrq $48, %rcx
; CHECK-NEXT: andl $15, %ecx ; CHECK-NEXT: andl $15, %ecx
; CHECK-NEXT: vpinsrb $12, %ecx, %xmm0, %xmm0 ; CHECK-NEXT: vpinsrb $12, %ecx, %xmm0, %xmm0
; CHECK-NEXT: movq %rax, %rcx ; CHECK-NEXT: movq %rax, %rcx
; CHECK-NEXT: shrq $52, %rcx ; CHECK-NEXT: shrq $52, %rcx
; CHECK-NEXT: andl $15, %ecx ; CHECK-NEXT: andl $15, %ecx
; CHECK-NEXT: vpinsrb $13, %ecx, %xmm0, %xmm0 ; CHECK-NEXT: vpinsrb $13, %ecx, %xmm0, %xmm0
; CHECK-NEXT: movq %rax, %rcx ; CHECK-NEXT: movq %rax, %rcx
; CHECK-NEXT: shrq $60, %rax
; CHECK-NEXT: shrq $56, %rcx ; CHECK-NEXT: shrq $56, %rcx
; CHECK-NEXT: andl $15, %ecx ; CHECK-NEXT: andl $15, %ecx
; CHECK-NEXT: vpinsrb $14, %ecx, %xmm0, %xmm0 ; CHECK-NEXT: vpinsrb $14, %ecx, %xmm0, %xmm0
; CHECK-NEXT: shrq $60, %rax
; CHECK-NEXT: vpinsrb $15, %eax, %xmm0, %xmm0 ; CHECK-NEXT: vpinsrb $15, %eax, %xmm0, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%ret = load <16 x i4>, <16 x i4>* %in, align 1 %ret = load <16 x i4>, <16 x i4>* %in, align 1
ret <16 x i4> %ret ret <16 x i4> %ret
} }

llvm/test/CodeGen/X86/pr21792.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-linux -mcpu=corei7 | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-linux -mcpu=corei7 | FileCheck %s
; This fixes a missing cases in the MI scheduler's constrainLocalCopy exposed by ; This fixes a missing cases in the MI scheduler's constrainLocalCopy exposed by
; PR21792 ; PR21792
@stuff = external constant [256 x double], align 16 @stuff = external constant [256 x double], align 16
define void @func(<4 x float> %vx) { define void @func(<4 x float> %vx) {
; CHECK-LABEL: func: ; CHECK-LABEL: func:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax ; CHECK-NEXT: pushq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: pand {{.*}}(%rip), %xmm0 ; CHECK-NEXT: pand {{.*}}(%rip), %xmm0
; CHECK-NEXT: movd %xmm0, %r8d
; CHECK-NEXT: leaq stuff(%r8), %rdi
; CHECK-NEXT: pextrd $1, %xmm0, %eax ; CHECK-NEXT: pextrd $1, %xmm0, %eax
; CHECK-NEXT: leaq stuff(%rax), %rsi
; CHECK-NEXT: pextrd $2, %xmm0, %edx ; CHECK-NEXT: pextrd $2, %xmm0, %edx
; CHECK-NEXT: pextrd $3, %xmm0, %ecx ; CHECK-NEXT: pextrd $3, %xmm0, %ecx
; CHECK-NEXT: movd %xmm0, %r8d
; CHECK-NEXT: leaq stuff(%r8), %rdi
; CHECK-NEXT: leaq stuff+8(%r8), %r8
; CHECK-NEXT: leaq stuff(%rax), %rsi
; CHECK-NEXT: leaq stuff(%rdx), %rdx ; CHECK-NEXT: leaq stuff(%rdx), %rdx
; CHECK-NEXT: leaq stuff(%rcx), %rcx ; CHECK-NEXT: leaq stuff(%rcx), %rcx
; CHECK-NEXT: leaq stuff+8(%r8), %r8
; CHECK-NEXT: leaq stuff+8(%rax), %r9 ; CHECK-NEXT: leaq stuff+8(%rax), %r9
; CHECK-NEXT: callq toto ; CHECK-NEXT: callq toto
; CHECK-NEXT: popq %rax ; CHECK-NEXT: popq %rax
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq ; CHECK-NEXT: retq
entry: entry:
%tmp2 = bitcast <4 x float> %vx to <2 x i64> %tmp2 = bitcast <4 x float> %vx to <2 x i64>
%and.i = and <2 x i64> %tmp2, <i64 8727373547504, i64 8727373547504> %and.i = and <2 x i64> %tmp2, <i64 8727373547504, i64 8727373547504>
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llvm/test/CodeGen/X86/pr31045.ll

Show All 15 Lines
; Function Attrs: norecurse nounwind uwtable ; Function Attrs: norecurse nounwind uwtable
define void @_Z1av() local_unnamed_addr #0 { define void @_Z1av() local_unnamed_addr #0 {
; CHECK-LABEL: _Z1av: ; CHECK-LABEL: _Z1av:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl struct_obj_3+{{.*}}(%rip), %eax ; CHECK-NEXT: movl struct_obj_3+{{.*}}(%rip), %eax
; CHECK-NEXT: movzbl {{.*}}(%rip), %ecx ; CHECK-NEXT: movzbl {{.*}}(%rip), %ecx
; CHECK-NEXT: movzbl {{.*}}(%rip), %edx ; CHECK-NEXT: movzbl {{.*}}(%rip), %edx
; CHECK-NEXT: movb $0, {{.*}}(%rip)
; CHECK-NEXT: andl $1, %eax ; CHECK-NEXT: andl $1, %eax
; CHECK-NEXT: addl %eax, %eax ; CHECK-NEXT: addl %eax, %eax
; CHECK-NEXT: subl %ecx, %eax ; CHECK-NEXT: subl %ecx, %eax
; CHECK-NEXT: subl %edx, %eax ; CHECK-NEXT: subl %edx, %eax
; CHECK-NEXT: notl %eax ; CHECK-NEXT: notl %eax
; CHECK-NEXT: movzbl %al, %eax ; CHECK-NEXT: movzbl %al, %eax
; CHECK-NEXT: movw %ax, struct_obj_12+{{.*}}(%rip) ; CHECK-NEXT: movw %ax, struct_obj_12+{{.*}}(%rip)
; CHECK-NEXT: movb $0, {{.*}}(%rip)
; CHECK-NEXT: retq ; CHECK-NEXT: retq
entry: entry:
%bf.load = load i32, i32* bitcast (i24* getelementptr inbounds (%struct.d.3.7.11.15.39.71.75.91.95.99.107.123.363, %struct.d.3.7.11.15.39.71.75.91.95.99.107.123.363* @struct_obj_3, i64 0, i32 0, i32 2) to i32*), align 2 %bf.load = load i32, i32* bitcast (i24* getelementptr inbounds (%struct.d.3.7.11.15.39.71.75.91.95.99.107.123.363, %struct.d.3.7.11.15.39.71.75.91.95.99.107.123.363* @struct_obj_3, i64 0, i32 0, i32 2) to i32*), align 2
%tmp = load i8, i8* @var_46, align 1 %tmp = load i8, i8* @var_46, align 1
%conv1 = sext i8 %tmp to i32 %conv1 = sext i8 %tmp to i32
%tmp1 = load i8, i8* @var_49, align 1 %tmp1 = load i8, i8* @var_49, align 1
%tmp2 = zext i8 %tmp1 to i32 %tmp2 = zext i8 %tmp1 to i32
%tmp3 = shl i32 %bf.load, 1 %tmp3 = shl i32 %bf.load, 1
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llvm/test/CodeGen/X86/pr32610.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=i386-apple-macosx10.13.0 -o - %s | FileCheck %s ; RUN: llc -mtriple=i386-apple-macosx10.13.0 -o - %s | FileCheck %s
target datalayout = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128" target datalayout = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"
@c = external local_unnamed_addr global i32, align 4 @c = external local_unnamed_addr global i32, align 4
@b = external local_unnamed_addr global [1 x i32], align 4 @b = external local_unnamed_addr global [1 x i32], align 4
@d = external local_unnamed_addr global i32, align 4 @d = external local_unnamed_addr global i32, align 4
define void @pr32610(i32 %a0, i32 %a1) #0 { define void @pr32610(i32 %a0, i32 %a1) #0 {
; CHECK-LABEL: pr32610: ; CHECK-LABEL: pr32610:
; CHECK: ## %bb.0: ## %entry ; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: pushl %ebp ; CHECK-NEXT: pushl %ebp
; CHECK-NEXT: movl %esp, %ebp ; CHECK-NEXT: movl %esp, %ebp
; CHECK-NEXT: pushl %esi ; CHECK-NEXT: pushl %esi
; CHECK-NEXT: movl 8(%ebp), %ecx
; CHECK-NEXT: movl L_b$non_lazy_ptr, %edx ; CHECK-NEXT: movl L_b$non_lazy_ptr, %edx
; CHECK-NEXT: movl 8(%ebp), %ecx
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: cmpl (%edx), %ecx ; CHECK-NEXT: cmpl (%edx), %ecx
; CHECK-NEXT: sete %al ; CHECK-NEXT: sete %al
; CHECK-NEXT: xorl %esi, %esi ; CHECK-NEXT: xorl %esi, %esi
; CHECK-NEXT: incl %esi ; CHECK-NEXT: incl %esi
; CHECK-NEXT: cmpl $0, 12(%ebp) ; CHECK-NEXT: cmpl $0, 12(%ebp)
; CHECK-NEXT: cmovel %esi, %eax ; CHECK-NEXT: cmovel %esi, %eax
; CHECK-NEXT: cmpl (%edx), %ecx ; CHECK-NEXT: cmpl (%edx), %ecx
; CHECK-NEXT: cmovnel %esi, %eax
; CHECK-NEXT: movl L_c$non_lazy_ptr, %ecx ; CHECK-NEXT: movl L_c$non_lazy_ptr, %ecx
; CHECK-NEXT: cmovnel %esi, %eax
; CHECK-NEXT: movl (%edx), %esi
; CHECK-NEXT: movl L_d$non_lazy_ptr, %edx
; CHECK-NEXT: movl %eax, (%ecx) ; CHECK-NEXT: movl %eax, (%ecx)
; CHECK-NEXT: movl (%edx), %eax
; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: movl $2, %ecx ; CHECK-NEXT: movl $2, %ecx
; CHECK-NEXT: cmovnel %eax, %ecx ; CHECK-NEXT: testl %esi, %esi
; CHECK-NEXT: movl L_d$non_lazy_ptr, %eax ; CHECK-NEXT: cmovnel %esi, %ecx
; CHECK-NEXT: movl %ecx, (%eax) ; CHECK-NEXT: movl %ecx, (%edx)
; CHECK-NEXT: popl %esi ; CHECK-NEXT: popl %esi
; CHECK-NEXT: popl %ebp ; CHECK-NEXT: popl %ebp
; CHECK-NEXT: retl ; CHECK-NEXT: retl
entry: entry:
%0 = load i32, i32* getelementptr ([1 x i32], [1 x i32]* @b, i32 0, i32 undef), align 4, !tbaa !1 %0 = load i32, i32* getelementptr ([1 x i32], [1 x i32]* @b, i32 0, i32 undef), align 4, !tbaa !1
%cmp = icmp eq i32 %a0, %0 %cmp = icmp eq i32 %a0, %0
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
%tobool1.i = icmp ne i32 %a1, 0 %tobool1.i = icmp ne i32 %a1, 0
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llvm/test/CodeGen/X86/pr34088.ll

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; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: .cfi_offset %ebp, -8 ; CHECK-NEXT: .cfi_offset %ebp, -8
; CHECK-NEXT: movl %esp, %ebp ; CHECK-NEXT: movl %esp, %ebp
; CHECK-NEXT: .cfi_def_cfa_register %ebp ; CHECK-NEXT: .cfi_def_cfa_register %ebp
; CHECK-NEXT: andl $-16, %esp ; CHECK-NEXT: andl $-16, %esp
; CHECK-NEXT: subl $32, %esp ; CHECK-NEXT: subl $32, %esp
; CHECK-NEXT: xorps %xmm0, %xmm0 ; CHECK-NEXT: xorps %xmm0, %xmm0
; CHECK-NEXT: movaps %xmm0, (%esp) ; CHECK-NEXT: movaps %xmm0, (%esp)
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: movaps {{.*#+}} xmm1 = [205,205,205,205,205,205,205,205,205,205,205,205,205,205,205,205] ; CHECK-NEXT: movaps {{.*#+}} xmm1 = [205,205,205,205,205,205,205,205,205,205,205,205,205,205,205,205]
; CHECK-NEXT: movaps %xmm1, (%esp) ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: movl $-842150451, {{[0-9]+}}(%esp) # imm = 0xCDCDCDCD ; CHECK-NEXT: movl $-842150451, {{[0-9]+}}(%esp) # imm = 0xCDCDCDCD
; CHECK-NEXT: movaps %xmm1, (%esp)
; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%esp) ; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%esp)
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: movl %ebp, %esp ; CHECK-NEXT: movl %ebp, %esp
; CHECK-NEXT: popl %ebp ; CHECK-NEXT: popl %ebp
; CHECK-NEXT: .cfi_def_cfa %esp, 4 ; CHECK-NEXT: .cfi_def_cfa %esp, 4
; CHECK-NEXT: retl ; CHECK-NEXT: retl
entry: entry:
%foo = alloca %struct.Foo, align 4 %foo = alloca %struct.Foo, align 4
%0 = bitcast %struct.Foo* %foo to i8* %0 = bitcast %struct.Foo* %foo to i8*
call void @llvm.memset.p0i8.i32(i8* align 4 nonnull %0, i8 0, i32 20, i1 false) call void @llvm.memset.p0i8.i32(i8* align 4 nonnull %0, i8 0, i32 20, i1 false)
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llvm/test/CodeGen/X86/pr34629.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
@b = common local_unnamed_addr global i64 0, align 8 @b = common local_unnamed_addr global i64 0, align 8
@a = common local_unnamed_addr global i8 0, align 1 @a = common local_unnamed_addr global i8 0, align 1
; Function Attrs: norecurse nounwind uwtable ; Function Attrs: norecurse nounwind uwtable
define void @c() local_unnamed_addr #0 { define void @c() local_unnamed_addr #0 {
; CHECK-LABEL: c: ; CHECK-LABEL: c:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movq {{.*}}(%rip), %rax ; CHECK-NEXT: movq {{.*}}(%rip), %rax
; CHECK-NEXT: leaq (%rax,%rax,4), %rcx ; CHECK-NEXT: leaq (%rax,%rax,4), %rcx
; CHECK-NEXT: negq %rcx
; CHECK-NEXT: leaq (%rax,%rax,8), %rax ; CHECK-NEXT: leaq (%rax,%rax,8), %rax
; CHECK-NEXT: negq %rcx
; CHECK-NEXT: leaq (%rax,%rax,4), %rax ; CHECK-NEXT: leaq (%rax,%rax,4), %rax
; CHECK-NEXT: testq %rax, %rcx ; CHECK-NEXT: testq %rax, %rcx
; CHECK-NEXT: je .LBB0_2 ; CHECK-NEXT: je .LBB0_2
; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: movb $0, {{.*}}(%rip) ; CHECK-NEXT: movb $0, {{.*}}(%rip)
; CHECK-NEXT: .LBB0_2: # %if.end ; CHECK-NEXT: .LBB0_2: # %if.end
; CHECK-NEXT: retq ; CHECK-NEXT: retq
entry: entry:
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llvm/test/CodeGen/X86/pr40539.ll

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@fpi = external global float, align 4 @fpi = external global float, align 4
define zeroext i1 @_Z8test_cosv() { define zeroext i1 @_Z8test_cosv() {
; CHECK-LABEL: _Z8test_cosv: ; CHECK-LABEL: _Z8test_cosv:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subl $8, %esp ; CHECK-NEXT: subl $8, %esp
; CHECK-NEXT: .cfi_def_cfa_offset 12 ; CHECK-NEXT: .cfi_def_cfa_offset 12
; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; CHECK-NEXT: divss {{\.LCPI.*}}, %xmm0 ; CHECK-NEXT: divss {{\.LCPI.*}}, %xmm0
; CHECK-NEXT: movss %xmm0, {{[0-9]+}}(%esp) ; CHECK-NEXT: movss %xmm0, {{[0-9]+}}(%esp)
; CHECK-NEXT: flds {{[0-9]+}}(%esp) ; CHECK-NEXT: flds {{[0-9]+}}(%esp)
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: fcos ; CHECK-NEXT: fcos
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: fstps (%esp) ; CHECK-NEXT: fstps (%esp)
; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; CHECK-NEXT: ucomiss %xmm0, %xmm1 ; CHECK-NEXT: ucomiss %xmm0, %xmm1
; CHECK-NEXT: setae %cl ; CHECK-NEXT: setae %cl
; CHECK-NEXT: ucomiss {{\.LCPI.*}}, %xmm0 ; CHECK-NEXT: ucomiss {{\.LCPI.*}}, %xmm0
; CHECK-NEXT: setae %al ; CHECK-NEXT: setae %al
; CHECK-NEXT: andb %cl, %al ; CHECK-NEXT: andb %cl, %al
; CHECK-NEXT: addl $8, %esp ; CHECK-NEXT: addl $8, %esp
; CHECK-NEXT: .cfi_def_cfa_offset 4 ; CHECK-NEXT: .cfi_def_cfa_offset 4
; CHECK-NEXT: retl ; CHECK-NEXT: retl
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llvm/test/CodeGen/X86/preserve_mostcc64.ll

Show All 37 Lines;AVX-NEXT: pushq %rbx
ret void ret void
} }
; Make sure R11 and XMMs are saved before the call ; Make sure R11 and XMMs are saved before the call
declare preserve_mostcc void @foo(i64, i64, double, double) declare preserve_mostcc void @foo(i64, i64, double, double)
define void @preserve_mostcc2() nounwind { define void @preserve_mostcc2() nounwind {
entry: entry:
;SSE-LABEL: preserve_mostcc2 ;SSE-LABEL: preserve_mostcc2
;SSE: movq %r11, [[REG:%[a-z0-9]+]]
;SSE: movaps %xmm2 ;SSE: movaps %xmm2
;SSE: movaps %xmm3 ;SSE: movaps %xmm3
;SSE: movaps %xmm4 ;SSE: movaps %xmm4
;SSE: movaps %xmm5 ;SSE: movaps %xmm5
;SSE: movaps %xmm6 ;SSE: movaps %xmm6
;SSE: movaps %xmm7 ;SSE: movaps %xmm7
;SSE: movaps %xmm8 ;SSE: movaps %xmm8
;SSE: movaps %xmm9 ;SSE: movaps %xmm9
;SSE: movaps %xmm10 ;SSE: movaps %xmm10
;SSE: movaps %xmm11 ;SSE: movaps %xmm11
;SSE: movaps %xmm12 ;SSE: movaps %xmm12
;SSE: movaps %xmm13 ;SSE: movaps %xmm13
;SSE: movaps %xmm14 ;SSE: movaps %xmm14
;SSE: movq %r11, [[REG:%[a-z0-9]+]]
;SSE: movaps %xmm15 ;SSE: movaps %xmm15
;SSE: movq [[REG]], %r11 ;SSE: movq [[REG]], %r11
%a0 = call i64 asm sideeffect "", "={rax}"() nounwind %a0 = call i64 asm sideeffect "", "={rax}"() nounwind
%a1 = call i64 asm sideeffect "", "={rcx}"() nounwind %a1 = call i64 asm sideeffect "", "={rcx}"() nounwind
%a2 = call i64 asm sideeffect "", "={rdx}"() nounwind %a2 = call i64 asm sideeffect "", "={rdx}"() nounwind
%a3 = call i64 asm sideeffect "", "={r8}"() nounwind %a3 = call i64 asm sideeffect "", "={r8}"() nounwind
%a4 = call i64 asm sideeffect "", "={r9}"() nounwind %a4 = call i64 asm sideeffect "", "={r9}"() nounwind
%a5 = call i64 asm sideeffect "", "={r10}"() nounwind %a5 = call i64 asm sideeffect "", "={r10}"() nounwind
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llvm/test/CodeGen/X86/rdrand.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown-unknown -mcpu=core-avx-i -mattr=+rdrnd | FileCheck %s --check-prefix=X86 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mcpu=core-avx-i -mattr=+rdrnd | FileCheck %s --check-prefix=X86
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=core-avx-i -mattr=+rdrnd | FileCheck %s --check-prefix=X64 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=core-avx-i -mattr=+rdrnd | FileCheck %s --check-prefix=X64
declare {i16, i32} @llvm.x86.rdrand.16() declare {i16, i32} @llvm.x86.rdrand.16()
declare {i32, i32} @llvm.x86.rdrand.32() declare {i32, i32} @llvm.x86.rdrand.32()
define i32 @_rdrand16_step(i16* %random_val) { define i32 @_rdrand16_step(i16* %random_val) {
; X86-LABEL: _rdrand16_step: ; X86-LABEL: _rdrand16_step:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: rdrandw %ax ; X86-NEXT: rdrandw %ax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movzwl %ax, %edx ; X86-NEXT: movzwl %ax, %edx
; X86-NEXT: movl $1, %eax ; X86-NEXT: movl $1, %eax
; X86-NEXT: cmovael %edx, %eax ; X86-NEXT: cmovael %edx, %eax
; X86-NEXT: movw %dx, (%ecx) ; X86-NEXT: movw %dx, (%ecx)
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: _rdrand16_step: ; X64-LABEL: _rdrand16_step:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: rdrandw %ax ; X64-NEXT: rdrandw %ax
; X64-NEXT: movzwl %ax, %ecx ; X64-NEXT: movzwl %ax, %ecx
; X64-NEXT: movl $1, %eax ; X64-NEXT: movl $1, %eax
; X64-NEXT: cmovael %ecx, %eax ; X64-NEXT: cmovael %ecx, %eax
; X64-NEXT: movw %cx, (%rdi) ; X64-NEXT: movw %cx, (%rdi)
; X64-NEXT: retq ; X64-NEXT: retq
%call = call {i16, i32} @llvm.x86.rdrand.16() %call = call {i16, i32} @llvm.x86.rdrand.16()
%randval = extractvalue {i16, i32} %call, 0 %randval = extractvalue {i16, i32} %call, 0
store i16 %randval, i16* %random_val store i16 %randval, i16* %random_val
%isvalid = extractvalue {i16, i32} %call, 1 %isvalid = extractvalue {i16, i32} %call, 1
ret i32 %isvalid ret i32 %isvalid
} }
define i32 @_rdrand32_step(i32* %random_val) { define i32 @_rdrand32_step(i32* %random_val) {
; X86-LABEL: _rdrand32_step: ; X86-LABEL: _rdrand32_step:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: rdrandl %edx ; X86-NEXT: rdrandl %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl $1, %eax ; X86-NEXT: movl $1, %eax
; X86-NEXT: cmovael %edx, %eax ; X86-NEXT: cmovael %edx, %eax
; X86-NEXT: movl %edx, (%ecx) ; X86-NEXT: movl %edx, (%ecx)
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: _rdrand32_step: ; X64-LABEL: _rdrand32_step:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: rdrandl %ecx ; X64-NEXT: rdrandl %ecx
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llvm/test/CodeGen/X86/rdseed.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown-unknown -mcpu=core-avx-i -mattr=+rdseed | FileCheck %s --check-prefix=X86 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mcpu=core-avx-i -mattr=+rdseed | FileCheck %s --check-prefix=X86
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=core-avx-i -mattr=+rdseed | FileCheck %s --check-prefix=X64 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=core-avx-i -mattr=+rdseed | FileCheck %s --check-prefix=X64
declare {i16, i32} @llvm.x86.rdseed.16() declare {i16, i32} @llvm.x86.rdseed.16()
declare {i32, i32} @llvm.x86.rdseed.32() declare {i32, i32} @llvm.x86.rdseed.32()
define i32 @_rdseed16_step(i16* %random_val) { define i32 @_rdseed16_step(i16* %random_val) {
; X86-LABEL: _rdseed16_step: ; X86-LABEL: _rdseed16_step:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: rdseedw %ax ; X86-NEXT: rdseedw %ax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movzwl %ax, %edx ; X86-NEXT: movzwl %ax, %edx
; X86-NEXT: movl $1, %eax ; X86-NEXT: movl $1, %eax
; X86-NEXT: cmovael %edx, %eax ; X86-NEXT: cmovael %edx, %eax
; X86-NEXT: movw %dx, (%ecx) ; X86-NEXT: movw %dx, (%ecx)
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: _rdseed16_step: ; X64-LABEL: _rdseed16_step:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: rdseedw %ax ; X64-NEXT: rdseedw %ax
; X64-NEXT: movzwl %ax, %ecx ; X64-NEXT: movzwl %ax, %ecx
; X64-NEXT: movl $1, %eax ; X64-NEXT: movl $1, %eax
; X64-NEXT: cmovael %ecx, %eax ; X64-NEXT: cmovael %ecx, %eax
; X64-NEXT: movw %cx, (%rdi) ; X64-NEXT: movw %cx, (%rdi)
; X64-NEXT: retq ; X64-NEXT: retq
%call = call {i16, i32} @llvm.x86.rdseed.16() %call = call {i16, i32} @llvm.x86.rdseed.16()
%randval = extractvalue {i16, i32} %call, 0 %randval = extractvalue {i16, i32} %call, 0
store i16 %randval, i16* %random_val store i16 %randval, i16* %random_val
%isvalid = extractvalue {i16, i32} %call, 1 %isvalid = extractvalue {i16, i32} %call, 1
ret i32 %isvalid ret i32 %isvalid
} }
define i32 @_rdseed32_step(i32* %random_val) { define i32 @_rdseed32_step(i32* %random_val) {
; X86-LABEL: _rdseed32_step: ; X86-LABEL: _rdseed32_step:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: rdseedl %edx ; X86-NEXT: rdseedl %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl $1, %eax ; X86-NEXT: movl $1, %eax
; X86-NEXT: cmovael %edx, %eax ; X86-NEXT: cmovael %edx, %eax
; X86-NEXT: movl %edx, (%ecx) ; X86-NEXT: movl %edx, (%ecx)
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: _rdseed32_step: ; X64-LABEL: _rdseed32_step:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: rdseedl %ecx ; X64-NEXT: rdseedl %ecx
Show All 10 Lines

llvm/test/CodeGen/X86/recip-fastmath.ll

Show First 20 Lines • Show All 78 Lines • ▼ Show 20 Lines
; BTVER2-NEXT: vsubss %xmm0, %xmm2, %xmm0 ; BTVER2-NEXT: vsubss %xmm0, %xmm2, %xmm0
; BTVER2-NEXT: vmulss %xmm0, %xmm1, %xmm0 ; BTVER2-NEXT: vmulss %xmm0, %xmm1, %xmm0
; BTVER2-NEXT: vaddss %xmm0, %xmm1, %xmm0 ; BTVER2-NEXT: vaddss %xmm0, %xmm1, %xmm0
; BTVER2-NEXT: retq ; BTVER2-NEXT: retq
; ;
; SANDY-LABEL: f32_one_step: ; SANDY-LABEL: f32_one_step:
; SANDY: # %bb.0: ; SANDY: # %bb.0:
; SANDY-NEXT: vrcpss %xmm0, %xmm0, %xmm1 ; SANDY-NEXT: vrcpss %xmm0, %xmm0, %xmm1
; SANDY-NEXT: vmulss %xmm1, %xmm0, %xmm0
; SANDY-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SANDY-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; SANDY-NEXT: vmulss %xmm1, %xmm0, %xmm0
; SANDY-NEXT: vsubss %xmm0, %xmm2, %xmm0 ; SANDY-NEXT: vsubss %xmm0, %xmm2, %xmm0
; SANDY-NEXT: vmulss %xmm0, %xmm1, %xmm0 ; SANDY-NEXT: vmulss %xmm0, %xmm1, %xmm0
; SANDY-NEXT: vaddss %xmm0, %xmm1, %xmm0 ; SANDY-NEXT: vaddss %xmm0, %xmm1, %xmm0
; SANDY-NEXT: retq ; SANDY-NEXT: retq
; ;
; HASWELL-LABEL: f32_one_step: ; HASWELL-LABEL: f32_one_step:
; HASWELL: # %bb.0: ; HASWELL: # %bb.0:
; HASWELL-NEXT: vrcpss %xmm0, %xmm0, %xmm1 ; HASWELL-NEXT: vrcpss %xmm0, %xmm0, %xmm1
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; BTVER2-NEXT: vsubss %xmm0, %xmm3, %xmm0 ; BTVER2-NEXT: vsubss %xmm0, %xmm3, %xmm0
; BTVER2-NEXT: vmulss %xmm0, %xmm1, %xmm0 ; BTVER2-NEXT: vmulss %xmm0, %xmm1, %xmm0
; BTVER2-NEXT: vaddss %xmm0, %xmm1, %xmm0 ; BTVER2-NEXT: vaddss %xmm0, %xmm1, %xmm0
; BTVER2-NEXT: retq ; BTVER2-NEXT: retq
; ;
; SANDY-LABEL: f32_two_step: ; SANDY-LABEL: f32_two_step:
; SANDY: # %bb.0: ; SANDY: # %bb.0:
; SANDY-NEXT: vrcpss %xmm0, %xmm0, %xmm1 ; SANDY-NEXT: vrcpss %xmm0, %xmm0, %xmm1
; SANDY-NEXT: vmulss %xmm1, %xmm0, %xmm2
; SANDY-NEXT: vmovss {{.*#+}} xmm3 = mem[0],zero,zero,zero ; SANDY-NEXT: vmovss {{.*#+}} xmm3 = mem[0],zero,zero,zero
; SANDY-NEXT: vmulss %xmm1, %xmm0, %xmm2
; SANDY-NEXT: vsubss %xmm2, %xmm3, %xmm2 ; SANDY-NEXT: vsubss %xmm2, %xmm3, %xmm2
; SANDY-NEXT: vmulss %xmm2, %xmm1, %xmm2 ; SANDY-NEXT: vmulss %xmm2, %xmm1, %xmm2
; SANDY-NEXT: vaddss %xmm2, %xmm1, %xmm1 ; SANDY-NEXT: vaddss %xmm2, %xmm1, %xmm1
; SANDY-NEXT: vmulss %xmm1, %xmm0, %xmm0 ; SANDY-NEXT: vmulss %xmm1, %xmm0, %xmm0
; SANDY-NEXT: vsubss %xmm0, %xmm3, %xmm0 ; SANDY-NEXT: vsubss %xmm0, %xmm3, %xmm0
; SANDY-NEXT: vmulss %xmm0, %xmm1, %xmm0 ; SANDY-NEXT: vmulss %xmm0, %xmm1, %xmm0
; SANDY-NEXT: vaddss %xmm0, %xmm1, %xmm0 ; SANDY-NEXT: vaddss %xmm0, %xmm1, %xmm0
; SANDY-NEXT: retq ; SANDY-NEXT: retq
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; BTVER2-NEXT: vsubps %xmm0, %xmm2, %xmm0 ; BTVER2-NEXT: vsubps %xmm0, %xmm2, %xmm0
; BTVER2-NEXT: vmulps %xmm0, %xmm1, %xmm0 ; BTVER2-NEXT: vmulps %xmm0, %xmm1, %xmm0
; BTVER2-NEXT: vaddps %xmm0, %xmm1, %xmm0 ; BTVER2-NEXT: vaddps %xmm0, %xmm1, %xmm0
; BTVER2-NEXT: retq ; BTVER2-NEXT: retq
; ;
; SANDY-LABEL: v4f32_one_step: ; SANDY-LABEL: v4f32_one_step:
; SANDY: # %bb.0: ; SANDY: # %bb.0:
; SANDY-NEXT: vrcpps %xmm0, %xmm1 ; SANDY-NEXT: vrcpps %xmm0, %xmm1
; SANDY-NEXT: vmulps %xmm1, %xmm0, %xmm0
; SANDY-NEXT: vmovaps {{.*#+}} xmm2 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0] ; SANDY-NEXT: vmovaps {{.*#+}} xmm2 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0]
; SANDY-NEXT: vmulps %xmm1, %xmm0, %xmm0
; SANDY-NEXT: vsubps %xmm0, %xmm2, %xmm0 ; SANDY-NEXT: vsubps %xmm0, %xmm2, %xmm0
; SANDY-NEXT: vmulps %xmm0, %xmm1, %xmm0 ; SANDY-NEXT: vmulps %xmm0, %xmm1, %xmm0
; SANDY-NEXT: vaddps %xmm0, %xmm1, %xmm0 ; SANDY-NEXT: vaddps %xmm0, %xmm1, %xmm0
; SANDY-NEXT: retq ; SANDY-NEXT: retq
; ;
; HASWELL-LABEL: v4f32_one_step: ; HASWELL-LABEL: v4f32_one_step:
; HASWELL: # %bb.0: ; HASWELL: # %bb.0:
; HASWELL-NEXT: vrcpps %xmm0, %xmm2 ; HASWELL-NEXT: vrcpps %xmm0, %xmm2
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; BTVER2-NEXT: vsubps %xmm0, %xmm3, %xmm0 ; BTVER2-NEXT: vsubps %xmm0, %xmm3, %xmm0
; BTVER2-NEXT: vmulps %xmm0, %xmm1, %xmm0 ; BTVER2-NEXT: vmulps %xmm0, %xmm1, %xmm0
; BTVER2-NEXT: vaddps %xmm0, %xmm1, %xmm0 ; BTVER2-NEXT: vaddps %xmm0, %xmm1, %xmm0
; BTVER2-NEXT: retq ; BTVER2-NEXT: retq
; ;
; SANDY-LABEL: v4f32_two_step: ; SANDY-LABEL: v4f32_two_step:
; SANDY: # %bb.0: ; SANDY: # %bb.0:
; SANDY-NEXT: vrcpps %xmm0, %xmm1 ; SANDY-NEXT: vrcpps %xmm0, %xmm1
; SANDY-NEXT: vmulps %xmm1, %xmm0, %xmm2
; SANDY-NEXT: vmovaps {{.*#+}} xmm3 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0] ; SANDY-NEXT: vmovaps {{.*#+}} xmm3 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0]
; SANDY-NEXT: vmulps %xmm1, %xmm0, %xmm2
; SANDY-NEXT: vsubps %xmm2, %xmm3, %xmm2 ; SANDY-NEXT: vsubps %xmm2, %xmm3, %xmm2
; SANDY-NEXT: vmulps %xmm2, %xmm1, %xmm2 ; SANDY-NEXT: vmulps %xmm2, %xmm1, %xmm2
; SANDY-NEXT: vaddps %xmm2, %xmm1, %xmm1 ; SANDY-NEXT: vaddps %xmm2, %xmm1, %xmm1
; SANDY-NEXT: vmulps %xmm1, %xmm0, %xmm0 ; SANDY-NEXT: vmulps %xmm1, %xmm0, %xmm0
; SANDY-NEXT: vsubps %xmm0, %xmm3, %xmm0 ; SANDY-NEXT: vsubps %xmm0, %xmm3, %xmm0
; SANDY-NEXT: vmulps %xmm0, %xmm1, %xmm0 ; SANDY-NEXT: vmulps %xmm0, %xmm1, %xmm0
; SANDY-NEXT: vaddps %xmm0, %xmm1, %xmm0 ; SANDY-NEXT: vaddps %xmm0, %xmm1, %xmm0
; SANDY-NEXT: retq ; SANDY-NEXT: retq
▲ Show 20 Lines • Show All 150 Lines • ▼ Show 20 Lines
; BTVER2-NEXT: vsubps %ymm0, %ymm2, %ymm0 ; BTVER2-NEXT: vsubps %ymm0, %ymm2, %ymm0
; BTVER2-NEXT: vmulps %ymm0, %ymm1, %ymm0 ; BTVER2-NEXT: vmulps %ymm0, %ymm1, %ymm0
; BTVER2-NEXT: vaddps %ymm0, %ymm1, %ymm0 ; BTVER2-NEXT: vaddps %ymm0, %ymm1, %ymm0
; BTVER2-NEXT: retq ; BTVER2-NEXT: retq
; ;
; SANDY-LABEL: v8f32_one_step: ; SANDY-LABEL: v8f32_one_step:
; SANDY: # %bb.0: ; SANDY: # %bb.0:
; SANDY-NEXT: vrcpps %ymm0, %ymm1 ; SANDY-NEXT: vrcpps %ymm0, %ymm1
; SANDY-NEXT: vmulps %ymm1, %ymm0, %ymm0
; SANDY-NEXT: vmovaps {{.*#+}} ymm2 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0] ; SANDY-NEXT: vmovaps {{.*#+}} ymm2 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]
; SANDY-NEXT: vmulps %ymm1, %ymm0, %ymm0
; SANDY-NEXT: vsubps %ymm0, %ymm2, %ymm0 ; SANDY-NEXT: vsubps %ymm0, %ymm2, %ymm0
; SANDY-NEXT: vmulps %ymm0, %ymm1, %ymm0 ; SANDY-NEXT: vmulps %ymm0, %ymm1, %ymm0
; SANDY-NEXT: vaddps %ymm0, %ymm1, %ymm0 ; SANDY-NEXT: vaddps %ymm0, %ymm1, %ymm0
; SANDY-NEXT: retq ; SANDY-NEXT: retq
; ;
; HASWELL-LABEL: v8f32_one_step: ; HASWELL-LABEL: v8f32_one_step:
; HASWELL: # %bb.0: ; HASWELL: # %bb.0:
; HASWELL-NEXT: vrcpps %ymm0, %ymm2 ; HASWELL-NEXT: vrcpps %ymm0, %ymm2
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; BTVER2-NEXT: vsubps %ymm0, %ymm3, %ymm0 ; BTVER2-NEXT: vsubps %ymm0, %ymm3, %ymm0
; BTVER2-NEXT: vmulps %ymm0, %ymm1, %ymm0 ; BTVER2-NEXT: vmulps %ymm0, %ymm1, %ymm0
; BTVER2-NEXT: vaddps %ymm0, %ymm1, %ymm0 ; BTVER2-NEXT: vaddps %ymm0, %ymm1, %ymm0
; BTVER2-NEXT: retq ; BTVER2-NEXT: retq
; ;
; SANDY-LABEL: v8f32_two_step: ; SANDY-LABEL: v8f32_two_step:
; SANDY: # %bb.0: ; SANDY: # %bb.0:
; SANDY-NEXT: vrcpps %ymm0, %ymm1 ; SANDY-NEXT: vrcpps %ymm0, %ymm1
; SANDY-NEXT: vmulps %ymm1, %ymm0, %ymm2
; SANDY-NEXT: vmovaps {{.*#+}} ymm3 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0] ; SANDY-NEXT: vmovaps {{.*#+}} ymm3 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]
; SANDY-NEXT: vmulps %ymm1, %ymm0, %ymm2
; SANDY-NEXT: vsubps %ymm2, %ymm3, %ymm2 ; SANDY-NEXT: vsubps %ymm2, %ymm3, %ymm2
; SANDY-NEXT: vmulps %ymm2, %ymm1, %ymm2 ; SANDY-NEXT: vmulps %ymm2, %ymm1, %ymm2
; SANDY-NEXT: vaddps %ymm2, %ymm1, %ymm1 ; SANDY-NEXT: vaddps %ymm2, %ymm1, %ymm1
; SANDY-NEXT: vmulps %ymm1, %ymm0, %ymm0 ; SANDY-NEXT: vmulps %ymm1, %ymm0, %ymm0
; SANDY-NEXT: vsubps %ymm0, %ymm3, %ymm0 ; SANDY-NEXT: vsubps %ymm0, %ymm3, %ymm0
; SANDY-NEXT: vmulps %ymm0, %ymm1, %ymm0 ; SANDY-NEXT: vmulps %ymm0, %ymm1, %ymm0
; SANDY-NEXT: vaddps %ymm0, %ymm1, %ymm0 ; SANDY-NEXT: vaddps %ymm0, %ymm1, %ymm0
; SANDY-NEXT: retq ; SANDY-NEXT: retq
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; BTVER2-NEXT: vmulps %ymm1, %ymm4, %ymm1 ; BTVER2-NEXT: vmulps %ymm1, %ymm4, %ymm1
; BTVER2-NEXT: vaddps %ymm0, %ymm2, %ymm0 ; BTVER2-NEXT: vaddps %ymm0, %ymm2, %ymm0
; BTVER2-NEXT: vaddps %ymm1, %ymm4, %ymm1 ; BTVER2-NEXT: vaddps %ymm1, %ymm4, %ymm1
; BTVER2-NEXT: retq ; BTVER2-NEXT: retq
; ;
; SANDY-LABEL: v16f32_one_step: ; SANDY-LABEL: v16f32_one_step:
; SANDY: # %bb.0: ; SANDY: # %bb.0:
; SANDY-NEXT: vrcpps %ymm0, %ymm2 ; SANDY-NEXT: vrcpps %ymm0, %ymm2
; SANDY-NEXT: vmulps %ymm2, %ymm0, %ymm0 ; SANDY-NEXT: vrcpps %ymm1, %ymm4
; SANDY-NEXT: vmovaps {{.*#+}} ymm3 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0] ; SANDY-NEXT: vmovaps {{.*#+}} ymm3 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]
; SANDY-NEXT: vmulps %ymm2, %ymm0, %ymm0
; SANDY-NEXT: vmulps %ymm4, %ymm1, %ymm1
; SANDY-NEXT: vsubps %ymm0, %ymm3, %ymm0 ; SANDY-NEXT: vsubps %ymm0, %ymm3, %ymm0
; SANDY-NEXT: vsubps %ymm1, %ymm3, %ymm1
; SANDY-NEXT: vmulps %ymm0, %ymm2, %ymm0 ; SANDY-NEXT: vmulps %ymm0, %ymm2, %ymm0
; SANDY-NEXT: vmulps %ymm1, %ymm4, %ymm1
; SANDY-NEXT: vaddps %ymm0, %ymm2, %ymm0 ; SANDY-NEXT: vaddps %ymm0, %ymm2, %ymm0
; SANDY-NEXT: vrcpps %ymm1, %ymm2 ; SANDY-NEXT: vaddps %ymm1, %ymm4, %ymm1
; SANDY-NEXT: vmulps %ymm2, %ymm1, %ymm1
; SANDY-NEXT: vsubps %ymm1, %ymm3, %ymm1
; SANDY-NEXT: vmulps %ymm1, %ymm2, %ymm1
; SANDY-NEXT: vaddps %ymm1, %ymm2, %ymm1
; SANDY-NEXT: retq ; SANDY-NEXT: retq
; ;
; HASWELL-LABEL: v16f32_one_step: ; HASWELL-LABEL: v16f32_one_step:
; HASWELL: # %bb.0: ; HASWELL: # %bb.0:
; HASWELL-NEXT: vrcpps %ymm0, %ymm2 ; HASWELL-NEXT: vrcpps %ymm0, %ymm2
; HASWELL-NEXT: vbroadcastss {{.*#+}} ymm3 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0] ; HASWELL-NEXT: vbroadcastss {{.*#+}} ymm3 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]
; HASWELL-NEXT: vrcpps %ymm1, %ymm4 ; HASWELL-NEXT: vrcpps %ymm1, %ymm4
; HASWELL-NEXT: vfmsub213ps {{.*#+}} ymm0 = (ymm2 * ymm0) - ymm3 ; HASWELL-NEXT: vfmsub213ps {{.*#+}} ymm0 = (ymm2 * ymm0) - ymm3
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; BTVER2-NEXT: vsubps %ymm1, %ymm4, %ymm1 ; BTVER2-NEXT: vsubps %ymm1, %ymm4, %ymm1
; BTVER2-NEXT: vmulps %ymm1, %ymm2, %ymm1 ; BTVER2-NEXT: vmulps %ymm1, %ymm2, %ymm1
; BTVER2-NEXT: vaddps %ymm1, %ymm2, %ymm1 ; BTVER2-NEXT: vaddps %ymm1, %ymm2, %ymm1
; BTVER2-NEXT: retq ; BTVER2-NEXT: retq
; ;
; SANDY-LABEL: v16f32_two_step: ; SANDY-LABEL: v16f32_two_step:
; SANDY: # %bb.0: ; SANDY: # %bb.0:
; SANDY-NEXT: vrcpps %ymm0, %ymm2 ; SANDY-NEXT: vrcpps %ymm0, %ymm2
; SANDY-NEXT: vmulps %ymm2, %ymm0, %ymm3
; SANDY-NEXT: vmovaps {{.*#+}} ymm4 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0] ; SANDY-NEXT: vmovaps {{.*#+}} ymm4 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]
; SANDY-NEXT: vmulps %ymm2, %ymm0, %ymm3
; SANDY-NEXT: vsubps %ymm3, %ymm4, %ymm3 ; SANDY-NEXT: vsubps %ymm3, %ymm4, %ymm3
; SANDY-NEXT: vmulps %ymm3, %ymm2, %ymm3 ; SANDY-NEXT: vmulps %ymm3, %ymm2, %ymm3
; SANDY-NEXT: vaddps %ymm3, %ymm2, %ymm2 ; SANDY-NEXT: vaddps %ymm3, %ymm2, %ymm2
; SANDY-NEXT: vmulps %ymm2, %ymm0, %ymm0 ; SANDY-NEXT: vmulps %ymm2, %ymm0, %ymm0
; SANDY-NEXT: vsubps %ymm0, %ymm4, %ymm0 ; SANDY-NEXT: vsubps %ymm0, %ymm4, %ymm0
; SANDY-NEXT: vmulps %ymm0, %ymm2, %ymm0 ; SANDY-NEXT: vmulps %ymm0, %ymm2, %ymm0
; SANDY-NEXT: vaddps %ymm0, %ymm2, %ymm0 ; SANDY-NEXT: vaddps %ymm0, %ymm2, %ymm0
; SANDY-NEXT: vrcpps %ymm1, %ymm2 ; SANDY-NEXT: vrcpps %ymm1, %ymm2
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llvm/test/CodeGen/X86/recip-fastmath2.ll

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; BTVER2-NEXT: vmulss %xmm3, %xmm0, %xmm0 ; BTVER2-NEXT: vmulss %xmm3, %xmm0, %xmm0
; BTVER2-NEXT: vsubss %xmm0, %xmm2, %xmm0 ; BTVER2-NEXT: vsubss %xmm0, %xmm2, %xmm0
; BTVER2-NEXT: vmulss %xmm0, %xmm1, %xmm0 ; BTVER2-NEXT: vmulss %xmm0, %xmm1, %xmm0
; BTVER2-NEXT: vaddss %xmm0, %xmm3, %xmm0 ; BTVER2-NEXT: vaddss %xmm0, %xmm3, %xmm0
; BTVER2-NEXT: retq ; BTVER2-NEXT: retq
; ;
; SANDY-LABEL: f32_one_step_2: ; SANDY-LABEL: f32_one_step_2:
; SANDY: # %bb.0: ; SANDY: # %bb.0:
; SANDY-NEXT: vrcpss %xmm0, %xmm0, %xmm1
; SANDY-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SANDY-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; SANDY-NEXT: vrcpss %xmm0, %xmm0, %xmm1
; SANDY-NEXT: vmulss %xmm2, %xmm1, %xmm3 ; SANDY-NEXT: vmulss %xmm2, %xmm1, %xmm3
; SANDY-NEXT: vmulss %xmm3, %xmm0, %xmm0 ; SANDY-NEXT: vmulss %xmm3, %xmm0, %xmm0
; SANDY-NEXT: vsubss %xmm0, %xmm2, %xmm0 ; SANDY-NEXT: vsubss %xmm0, %xmm2, %xmm0
; SANDY-NEXT: vmulss %xmm0, %xmm1, %xmm0 ; SANDY-NEXT: vmulss %xmm0, %xmm1, %xmm0
; SANDY-NEXT: vaddss %xmm0, %xmm3, %xmm0 ; SANDY-NEXT: vaddss %xmm0, %xmm3, %xmm0
; SANDY-NEXT: retq ; SANDY-NEXT: retq
; ;
; HASWELL-LABEL: f32_one_step_2: ; HASWELL-LABEL: f32_one_step_2:
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; BTVER2-NEXT: vaddss %xmm0, %xmm1, %xmm0 ; BTVER2-NEXT: vaddss %xmm0, %xmm1, %xmm0
; BTVER2-NEXT: vmulss {{.*}}(%rip), %xmm0, %xmm1 ; BTVER2-NEXT: vmulss {{.*}}(%rip), %xmm0, %xmm1
; BTVER2-NEXT: vmulss %xmm0, %xmm1, %xmm0 ; BTVER2-NEXT: vmulss %xmm0, %xmm1, %xmm0
; BTVER2-NEXT: retq ; BTVER2-NEXT: retq
; ;
; SANDY-LABEL: f32_one_step_2_divs: ; SANDY-LABEL: f32_one_step_2_divs:
; SANDY: # %bb.0: ; SANDY: # %bb.0:
; SANDY-NEXT: vrcpss %xmm0, %xmm0, %xmm1 ; SANDY-NEXT: vrcpss %xmm0, %xmm0, %xmm1
; SANDY-NEXT: vmulss %xmm1, %xmm0, %xmm0
; SANDY-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SANDY-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; SANDY-NEXT: vmulss %xmm1, %xmm0, %xmm0
; SANDY-NEXT: vsubss %xmm0, %xmm2, %xmm0 ; SANDY-NEXT: vsubss %xmm0, %xmm2, %xmm0
; SANDY-NEXT: vmulss %xmm0, %xmm1, %xmm0 ; SANDY-NEXT: vmulss %xmm0, %xmm1, %xmm0
; SANDY-NEXT: vaddss %xmm0, %xmm1, %xmm0 ; SANDY-NEXT: vaddss %xmm0, %xmm1, %xmm0
; SANDY-NEXT: vmulss {{.*}}(%rip), %xmm0, %xmm1 ; SANDY-NEXT: vmulss {{.*}}(%rip), %xmm0, %xmm1
; SANDY-NEXT: vmulss %xmm0, %xmm1, %xmm0 ; SANDY-NEXT: vmulss %xmm0, %xmm1, %xmm0
; SANDY-NEXT: retq ; SANDY-NEXT: retq
; ;
; HASWELL-LABEL: f32_one_step_2_divs: ; HASWELL-LABEL: f32_one_step_2_divs:
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; BTVER2-NEXT: vsubss %xmm0, %xmm4, %xmm0 ; BTVER2-NEXT: vsubss %xmm0, %xmm4, %xmm0
; BTVER2-NEXT: vmulss %xmm0, %xmm1, %xmm0 ; BTVER2-NEXT: vmulss %xmm0, %xmm1, %xmm0
; BTVER2-NEXT: vaddss %xmm0, %xmm3, %xmm0 ; BTVER2-NEXT: vaddss %xmm0, %xmm3, %xmm0
; BTVER2-NEXT: retq ; BTVER2-NEXT: retq
; ;
; SANDY-LABEL: f32_two_step_2: ; SANDY-LABEL: f32_two_step_2:
; SANDY: # %bb.0: ; SANDY: # %bb.0:
; SANDY-NEXT: vrcpss %xmm0, %xmm0, %xmm1 ; SANDY-NEXT: vrcpss %xmm0, %xmm0, %xmm1
; SANDY-NEXT: vmulss %xmm1, %xmm0, %xmm2
; SANDY-NEXT: vmovss {{.*#+}} xmm3 = mem[0],zero,zero,zero ; SANDY-NEXT: vmovss {{.*#+}} xmm3 = mem[0],zero,zero,zero
; SANDY-NEXT: vmovss {{.*#+}} xmm4 = mem[0],zero,zero,zero
; SANDY-NEXT: vmulss %xmm1, %xmm0, %xmm2
; SANDY-NEXT: vsubss %xmm2, %xmm3, %xmm2 ; SANDY-NEXT: vsubss %xmm2, %xmm3, %xmm2
; SANDY-NEXT: vmulss %xmm2, %xmm1, %xmm2 ; SANDY-NEXT: vmulss %xmm2, %xmm1, %xmm2
; SANDY-NEXT: vaddss %xmm2, %xmm1, %xmm1 ; SANDY-NEXT: vaddss %xmm2, %xmm1, %xmm1
; SANDY-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; SANDY-NEXT: vmulss %xmm4, %xmm1, %xmm3
; SANDY-NEXT: vmulss %xmm2, %xmm1, %xmm3
; SANDY-NEXT: vmulss %xmm3, %xmm0, %xmm0 ; SANDY-NEXT: vmulss %xmm3, %xmm0, %xmm0
; SANDY-NEXT: vsubss %xmm0, %xmm2, %xmm0 ; SANDY-NEXT: vsubss %xmm0, %xmm4, %xmm0
; SANDY-NEXT: vmulss %xmm0, %xmm1, %xmm0 ; SANDY-NEXT: vmulss %xmm0, %xmm1, %xmm0
; SANDY-NEXT: vaddss %xmm0, %xmm3, %xmm0 ; SANDY-NEXT: vaddss %xmm0, %xmm3, %xmm0
; SANDY-NEXT: retq ; SANDY-NEXT: retq
; ;
; HASWELL-LABEL: f32_two_step_2: ; HASWELL-LABEL: f32_two_step_2:
; HASWELL: # %bb.0: ; HASWELL: # %bb.0:
; HASWELL-NEXT: vrcpss %xmm0, %xmm0, %xmm1 ; HASWELL-NEXT: vrcpss %xmm0, %xmm0, %xmm1
; HASWELL-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; HASWELL-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
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; BTVER2-NEXT: vmulps %xmm3, %xmm0, %xmm0 ; BTVER2-NEXT: vmulps %xmm3, %xmm0, %xmm0
; BTVER2-NEXT: vsubps %xmm0, %xmm2, %xmm0 ; BTVER2-NEXT: vsubps %xmm0, %xmm2, %xmm0
; BTVER2-NEXT: vmulps %xmm0, %xmm1, %xmm0 ; BTVER2-NEXT: vmulps %xmm0, %xmm1, %xmm0
; BTVER2-NEXT: vaddps %xmm0, %xmm3, %xmm0 ; BTVER2-NEXT: vaddps %xmm0, %xmm3, %xmm0
; BTVER2-NEXT: retq ; BTVER2-NEXT: retq
; ;
; SANDY-LABEL: v4f32_one_step2: ; SANDY-LABEL: v4f32_one_step2:
; SANDY: # %bb.0: ; SANDY: # %bb.0:
; SANDY-NEXT: vrcpps %xmm0, %xmm1
; SANDY-NEXT: vmovaps {{.*#+}} xmm2 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0] ; SANDY-NEXT: vmovaps {{.*#+}} xmm2 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0]
; SANDY-NEXT: vrcpps %xmm0, %xmm1
; SANDY-NEXT: vmulps %xmm2, %xmm1, %xmm3 ; SANDY-NEXT: vmulps %xmm2, %xmm1, %xmm3
; SANDY-NEXT: vmulps %xmm3, %xmm0, %xmm0 ; SANDY-NEXT: vmulps %xmm3, %xmm0, %xmm0
; SANDY-NEXT: vsubps %xmm0, %xmm2, %xmm0 ; SANDY-NEXT: vsubps %xmm0, %xmm2, %xmm0
; SANDY-NEXT: vmulps %xmm0, %xmm1, %xmm0 ; SANDY-NEXT: vmulps %xmm0, %xmm1, %xmm0
; SANDY-NEXT: vaddps %xmm0, %xmm3, %xmm0 ; SANDY-NEXT: vaddps %xmm0, %xmm3, %xmm0
; SANDY-NEXT: retq ; SANDY-NEXT: retq
; ;
; HASWELL-LABEL: v4f32_one_step2: ; HASWELL-LABEL: v4f32_one_step2:
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; BTVER2-NEXT: vaddps %xmm0, %xmm1, %xmm0 ; BTVER2-NEXT: vaddps %xmm0, %xmm1, %xmm0
; BTVER2-NEXT: vmulps {{.*}}(%rip), %xmm0, %xmm1 ; BTVER2-NEXT: vmulps {{.*}}(%rip), %xmm0, %xmm1
; BTVER2-NEXT: vmulps %xmm0, %xmm1, %xmm0 ; BTVER2-NEXT: vmulps %xmm0, %xmm1, %xmm0
; BTVER2-NEXT: retq ; BTVER2-NEXT: retq
; ;
; SANDY-LABEL: v4f32_one_step_2_divs: ; SANDY-LABEL: v4f32_one_step_2_divs:
; SANDY: # %bb.0: ; SANDY: # %bb.0:
; SANDY-NEXT: vrcpps %xmm0, %xmm1 ; SANDY-NEXT: vrcpps %xmm0, %xmm1
; SANDY-NEXT: vmulps %xmm1, %xmm0, %xmm0
; SANDY-NEXT: vmovaps {{.*#+}} xmm2 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0] ; SANDY-NEXT: vmovaps {{.*#+}} xmm2 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0]
; SANDY-NEXT: vmulps %xmm1, %xmm0, %xmm0
; SANDY-NEXT: vsubps %xmm0, %xmm2, %xmm0 ; SANDY-NEXT: vsubps %xmm0, %xmm2, %xmm0
; SANDY-NEXT: vmulps %xmm0, %xmm1, %xmm0 ; SANDY-NEXT: vmulps %xmm0, %xmm1, %xmm0
; SANDY-NEXT: vaddps %xmm0, %xmm1, %xmm0 ; SANDY-NEXT: vaddps %xmm0, %xmm1, %xmm0
; SANDY-NEXT: vmulps {{.*}}(%rip), %xmm0, %xmm1 ; SANDY-NEXT: vmulps {{.*}}(%rip), %xmm0, %xmm1
; SANDY-NEXT: vmulps %xmm0, %xmm1, %xmm0 ; SANDY-NEXT: vmulps %xmm0, %xmm1, %xmm0
; SANDY-NEXT: retq ; SANDY-NEXT: retq
; ;
; HASWELL-LABEL: v4f32_one_step_2_divs: ; HASWELL-LABEL: v4f32_one_step_2_divs:
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; BTVER2-NEXT: vsubps %xmm0, %xmm4, %xmm0 ; BTVER2-NEXT: vsubps %xmm0, %xmm4, %xmm0
; BTVER2-NEXT: vmulps %xmm0, %xmm1, %xmm0 ; BTVER2-NEXT: vmulps %xmm0, %xmm1, %xmm0
; BTVER2-NEXT: vaddps %xmm0, %xmm3, %xmm0 ; BTVER2-NEXT: vaddps %xmm0, %xmm3, %xmm0
; BTVER2-NEXT: retq ; BTVER2-NEXT: retq
; ;
; SANDY-LABEL: v4f32_two_step2: ; SANDY-LABEL: v4f32_two_step2:
; SANDY: # %bb.0: ; SANDY: # %bb.0:
; SANDY-NEXT: vrcpps %xmm0, %xmm1 ; SANDY-NEXT: vrcpps %xmm0, %xmm1
; SANDY-NEXT: vmulps %xmm1, %xmm0, %xmm2
; SANDY-NEXT: vmovaps {{.*#+}} xmm3 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0] ; SANDY-NEXT: vmovaps {{.*#+}} xmm3 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0]
; SANDY-NEXT: vmovaps {{.*#+}} xmm4 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0]
; SANDY-NEXT: vmulps %xmm1, %xmm0, %xmm2
; SANDY-NEXT: vsubps %xmm2, %xmm3, %xmm2 ; SANDY-NEXT: vsubps %xmm2, %xmm3, %xmm2
; SANDY-NEXT: vmulps %xmm2, %xmm1, %xmm2 ; SANDY-NEXT: vmulps %xmm2, %xmm1, %xmm2
; SANDY-NEXT: vaddps %xmm2, %xmm1, %xmm1 ; SANDY-NEXT: vaddps %xmm2, %xmm1, %xmm1
; SANDY-NEXT: vmovaps {{.*#+}} xmm2 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0] ; SANDY-NEXT: vmulps %xmm4, %xmm1, %xmm3
; SANDY-NEXT: vmulps %xmm2, %xmm1, %xmm3
; SANDY-NEXT: vmulps %xmm3, %xmm0, %xmm0 ; SANDY-NEXT: vmulps %xmm3, %xmm0, %xmm0
; SANDY-NEXT: vsubps %xmm0, %xmm2, %xmm0 ; SANDY-NEXT: vsubps %xmm0, %xmm4, %xmm0
; SANDY-NEXT: vmulps %xmm0, %xmm1, %xmm0 ; SANDY-NEXT: vmulps %xmm0, %xmm1, %xmm0
; SANDY-NEXT: vaddps %xmm0, %xmm3, %xmm0 ; SANDY-NEXT: vaddps %xmm0, %xmm3, %xmm0
; SANDY-NEXT: retq ; SANDY-NEXT: retq
; ;
; HASWELL-LABEL: v4f32_two_step2: ; HASWELL-LABEL: v4f32_two_step2:
; HASWELL: # %bb.0: ; HASWELL: # %bb.0:
; HASWELL-NEXT: vrcpps %xmm0, %xmm1 ; HASWELL-NEXT: vrcpps %xmm0, %xmm1
; HASWELL-NEXT: vbroadcastss {{.*#+}} xmm2 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0] ; HASWELL-NEXT: vbroadcastss {{.*#+}} xmm2 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0]
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; BTVER2-NEXT: vaddps %ymm0, %ymm1, %ymm0 ; BTVER2-NEXT: vaddps %ymm0, %ymm1, %ymm0
; BTVER2-NEXT: vmulps {{.*}}(%rip), %ymm0, %ymm1 ; BTVER2-NEXT: vmulps {{.*}}(%rip), %ymm0, %ymm1
; BTVER2-NEXT: vmulps %ymm0, %ymm1, %ymm0 ; BTVER2-NEXT: vmulps %ymm0, %ymm1, %ymm0
; BTVER2-NEXT: retq ; BTVER2-NEXT: retq
; ;
; SANDY-LABEL: v8f32_one_step_2_divs: ; SANDY-LABEL: v8f32_one_step_2_divs:
; SANDY: # %bb.0: ; SANDY: # %bb.0:
; SANDY-NEXT: vrcpps %ymm0, %ymm1 ; SANDY-NEXT: vrcpps %ymm0, %ymm1
; SANDY-NEXT: vmulps %ymm1, %ymm0, %ymm0
; SANDY-NEXT: vmovaps {{.*#+}} ymm2 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0] ; SANDY-NEXT: vmovaps {{.*#+}} ymm2 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]
; SANDY-NEXT: vmulps %ymm1, %ymm0, %ymm0
; SANDY-NEXT: vsubps %ymm0, %ymm2, %ymm0 ; SANDY-NEXT: vsubps %ymm0, %ymm2, %ymm0
; SANDY-NEXT: vmulps %ymm0, %ymm1, %ymm0 ; SANDY-NEXT: vmulps %ymm0, %ymm1, %ymm0
; SANDY-NEXT: vaddps %ymm0, %ymm1, %ymm0 ; SANDY-NEXT: vaddps %ymm0, %ymm1, %ymm0
; SANDY-NEXT: vmulps {{.*}}(%rip), %ymm0, %ymm1 ; SANDY-NEXT: vmulps {{.*}}(%rip), %ymm0, %ymm1
; SANDY-NEXT: vmulps %ymm0, %ymm1, %ymm0 ; SANDY-NEXT: vmulps %ymm0, %ymm1, %ymm0
; SANDY-NEXT: retq ; SANDY-NEXT: retq
; ;
; HASWELL-LABEL: v8f32_one_step_2_divs: ; HASWELL-LABEL: v8f32_one_step_2_divs:
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; BTVER2-NEXT: vsubps %ymm0, %ymm4, %ymm0 ; BTVER2-NEXT: vsubps %ymm0, %ymm4, %ymm0
; BTVER2-NEXT: vmulps %ymm0, %ymm1, %ymm0 ; BTVER2-NEXT: vmulps %ymm0, %ymm1, %ymm0
; BTVER2-NEXT: vaddps %ymm0, %ymm3, %ymm0 ; BTVER2-NEXT: vaddps %ymm0, %ymm3, %ymm0
; BTVER2-NEXT: retq ; BTVER2-NEXT: retq
; ;
; SANDY-LABEL: v8f32_two_step2: ; SANDY-LABEL: v8f32_two_step2:
; SANDY: # %bb.0: ; SANDY: # %bb.0:
; SANDY-NEXT: vrcpps %ymm0, %ymm1 ; SANDY-NEXT: vrcpps %ymm0, %ymm1
; SANDY-NEXT: vmulps %ymm1, %ymm0, %ymm2
; SANDY-NEXT: vmovaps {{.*#+}} ymm3 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0] ; SANDY-NEXT: vmovaps {{.*#+}} ymm3 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]
; SANDY-NEXT: vmovaps {{.*#+}} ymm4 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0,5.0E+0,6.0E+0,7.0E+0,8.0E+0]
; SANDY-NEXT: vmulps %ymm1, %ymm0, %ymm2
; SANDY-NEXT: vsubps %ymm2, %ymm3, %ymm2 ; SANDY-NEXT: vsubps %ymm2, %ymm3, %ymm2
; SANDY-NEXT: vmulps %ymm2, %ymm1, %ymm2 ; SANDY-NEXT: vmulps %ymm2, %ymm1, %ymm2
; SANDY-NEXT: vaddps %ymm2, %ymm1, %ymm1 ; SANDY-NEXT: vaddps %ymm2, %ymm1, %ymm1
; SANDY-NEXT: vmovaps {{.*#+}} ymm2 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0,5.0E+0,6.0E+0,7.0E+0,8.0E+0] ; SANDY-NEXT: vmulps %ymm4, %ymm1, %ymm3
; SANDY-NEXT: vmulps %ymm2, %ymm1, %ymm3
; SANDY-NEXT: vmulps %ymm3, %ymm0, %ymm0 ; SANDY-NEXT: vmulps %ymm3, %ymm0, %ymm0
; SANDY-NEXT: vsubps %ymm0, %ymm2, %ymm0 ; SANDY-NEXT: vsubps %ymm0, %ymm4, %ymm0
; SANDY-NEXT: vmulps %ymm0, %ymm1, %ymm0 ; SANDY-NEXT: vmulps %ymm0, %ymm1, %ymm0
; SANDY-NEXT: vaddps %ymm0, %ymm3, %ymm0 ; SANDY-NEXT: vaddps %ymm0, %ymm3, %ymm0
; SANDY-NEXT: retq ; SANDY-NEXT: retq
; ;
; HASWELL-LABEL: v8f32_two_step2: ; HASWELL-LABEL: v8f32_two_step2:
; HASWELL: # %bb.0: ; HASWELL: # %bb.0:
; HASWELL-NEXT: vrcpps %ymm0, %ymm1 ; HASWELL-NEXT: vrcpps %ymm0, %ymm1
; HASWELL-NEXT: vbroadcastss {{.*#+}} ymm2 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0] ; HASWELL-NEXT: vbroadcastss {{.*#+}} ymm2 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]
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; BTVER2-NEXT: vmulps %ymm1, %ymm2, %ymm1 ; BTVER2-NEXT: vmulps %ymm1, %ymm2, %ymm1
; BTVER2-NEXT: vaddps %ymm1, %ymm5, %ymm1 ; BTVER2-NEXT: vaddps %ymm1, %ymm5, %ymm1
; BTVER2-NEXT: retq ; BTVER2-NEXT: retq
; ;
; SANDY-LABEL: v16f32_one_step2: ; SANDY-LABEL: v16f32_one_step2:
; SANDY: # %bb.0: ; SANDY: # %bb.0:
; SANDY-NEXT: vrcpps %ymm0, %ymm2 ; SANDY-NEXT: vrcpps %ymm0, %ymm2
; SANDY-NEXT: vmovaps {{.*#+}} ymm3 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0,5.0E+0,6.0E+0,7.0E+0,8.0E+0] ; SANDY-NEXT: vmovaps {{.*#+}} ymm3 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0,5.0E+0,6.0E+0,7.0E+0,8.0E+0]
; SANDY-NEXT: vmovaps {{.*#+}} ymm5 = [9.0E+0,1.0E+1,1.1E+1,1.2E+1,1.3E+1,1.4E+1,1.5E+1,1.6E+1]
; SANDY-NEXT: vmulps %ymm3, %ymm2, %ymm4 ; SANDY-NEXT: vmulps %ymm3, %ymm2, %ymm4
; SANDY-NEXT: vmulps %ymm4, %ymm0, %ymm0 ; SANDY-NEXT: vmulps %ymm4, %ymm0, %ymm0
; SANDY-NEXT: vsubps %ymm0, %ymm3, %ymm0 ; SANDY-NEXT: vsubps %ymm0, %ymm3, %ymm0
; SANDY-NEXT: vrcpps %ymm1, %ymm3 ; SANDY-NEXT: vrcpps %ymm1, %ymm3
; SANDY-NEXT: vmulps %ymm0, %ymm2, %ymm0 ; SANDY-NEXT: vmulps %ymm0, %ymm2, %ymm0
; SANDY-NEXT: vaddps %ymm0, %ymm4, %ymm0 ; SANDY-NEXT: vaddps %ymm0, %ymm4, %ymm0
; SANDY-NEXT: vmovaps {{.*#+}} ymm2 = [9.0E+0,1.0E+1,1.1E+1,1.2E+1,1.3E+1,1.4E+1,1.5E+1,1.6E+1] ; SANDY-NEXT: vmulps %ymm5, %ymm3, %ymm4
; SANDY-NEXT: vmulps %ymm2, %ymm3, %ymm4
; SANDY-NEXT: vmulps %ymm4, %ymm1, %ymm1 ; SANDY-NEXT: vmulps %ymm4, %ymm1, %ymm1
; SANDY-NEXT: vsubps %ymm1, %ymm2, %ymm1 ; SANDY-NEXT: vsubps %ymm1, %ymm5, %ymm1
; SANDY-NEXT: vmulps %ymm1, %ymm3, %ymm1 ; SANDY-NEXT: vmulps %ymm1, %ymm3, %ymm1
; SANDY-NEXT: vaddps %ymm1, %ymm4, %ymm1 ; SANDY-NEXT: vaddps %ymm1, %ymm4, %ymm1
; SANDY-NEXT: retq ; SANDY-NEXT: retq
; ;
; HASWELL-LABEL: v16f32_one_step2: ; HASWELL-LABEL: v16f32_one_step2:
; HASWELL: # %bb.0: ; HASWELL: # %bb.0:
; HASWELL-NEXT: vrcpps %ymm0, %ymm2 ; HASWELL-NEXT: vrcpps %ymm0, %ymm2
; HASWELL-NEXT: vmovaps {{.*#+}} ymm3 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0,5.0E+0,6.0E+0,7.0E+0,8.0E+0] ; HASWELL-NEXT: vmovaps {{.*#+}} ymm3 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0,5.0E+0,6.0E+0,7.0E+0,8.0E+0]
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; BTVER2-NEXT: vmulps {{.*}}(%rip), %ymm1, %ymm2 ; BTVER2-NEXT: vmulps {{.*}}(%rip), %ymm1, %ymm2
; BTVER2-NEXT: vmulps %ymm0, %ymm3, %ymm0 ; BTVER2-NEXT: vmulps %ymm0, %ymm3, %ymm0
; BTVER2-NEXT: vmulps %ymm1, %ymm2, %ymm1 ; BTVER2-NEXT: vmulps %ymm1, %ymm2, %ymm1
; BTVER2-NEXT: retq ; BTVER2-NEXT: retq
; ;
; SANDY-LABEL: v16f32_one_step_2_divs: ; SANDY-LABEL: v16f32_one_step_2_divs:
; SANDY: # %bb.0: ; SANDY: # %bb.0:
; SANDY-NEXT: vrcpps %ymm0, %ymm2 ; SANDY-NEXT: vrcpps %ymm0, %ymm2
; SANDY-NEXT: vmulps %ymm2, %ymm0, %ymm0
; SANDY-NEXT: vmovaps {{.*#+}} ymm3 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]
; SANDY-NEXT: vsubps %ymm0, %ymm3, %ymm0
; SANDY-NEXT: vrcpps %ymm1, %ymm4 ; SANDY-NEXT: vrcpps %ymm1, %ymm4
; SANDY-NEXT: vmulps %ymm0, %ymm2, %ymm0 ; SANDY-NEXT: vmovaps {{.*#+}} ymm3 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]
; SANDY-NEXT: vaddps %ymm0, %ymm2, %ymm0 ; SANDY-NEXT: vmulps %ymm2, %ymm0, %ymm0
; SANDY-NEXT: vmulps %ymm4, %ymm1, %ymm1 ; SANDY-NEXT: vmulps %ymm4, %ymm1, %ymm1
; SANDY-NEXT: vsubps %ymm0, %ymm3, %ymm0
; SANDY-NEXT: vsubps %ymm1, %ymm3, %ymm1 ; SANDY-NEXT: vsubps %ymm1, %ymm3, %ymm1
; SANDY-NEXT: vmulps %ymm0, %ymm2, %ymm0
; SANDY-NEXT: vmulps %ymm1, %ymm4, %ymm1 ; SANDY-NEXT: vmulps %ymm1, %ymm4, %ymm1
; SANDY-NEXT: vaddps %ymm0, %ymm2, %ymm0
; SANDY-NEXT: vmulps {{.*}}(%rip), %ymm0, %ymm3
; SANDY-NEXT: vaddps %ymm1, %ymm4, %ymm1 ; SANDY-NEXT: vaddps %ymm1, %ymm4, %ymm1
; SANDY-NEXT: vmulps {{.*}}(%rip), %ymm1, %ymm2 ; SANDY-NEXT: vmulps {{.*}}(%rip), %ymm1, %ymm2
; SANDY-NEXT: vmulps {{.*}}(%rip), %ymm0, %ymm3
; SANDY-NEXT: vmulps %ymm0, %ymm3, %ymm0 ; SANDY-NEXT: vmulps %ymm0, %ymm3, %ymm0
; SANDY-NEXT: vmulps %ymm1, %ymm2, %ymm1 ; SANDY-NEXT: vmulps %ymm1, %ymm2, %ymm1
; SANDY-NEXT: retq ; SANDY-NEXT: retq
; ;
; HASWELL-LABEL: v16f32_one_step_2_divs: ; HASWELL-LABEL: v16f32_one_step_2_divs:
; HASWELL: # %bb.0: ; HASWELL: # %bb.0:
; HASWELL-NEXT: vrcpps %ymm0, %ymm2 ; HASWELL-NEXT: vrcpps %ymm0, %ymm2
; HASWELL-NEXT: vbroadcastss {{.*#+}} ymm3 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0] ; HASWELL-NEXT: vbroadcastss {{.*#+}} ymm3 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]
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; BTVER2-NEXT: vsubps %ymm1, %ymm5, %ymm1 ; BTVER2-NEXT: vsubps %ymm1, %ymm5, %ymm1
; BTVER2-NEXT: vmulps %ymm1, %ymm2, %ymm1 ; BTVER2-NEXT: vmulps %ymm1, %ymm2, %ymm1
; BTVER2-NEXT: vaddps %ymm1, %ymm4, %ymm1 ; BTVER2-NEXT: vaddps %ymm1, %ymm4, %ymm1
; BTVER2-NEXT: retq ; BTVER2-NEXT: retq
; ;
; SANDY-LABEL: v16f32_two_step2: ; SANDY-LABEL: v16f32_two_step2:
; SANDY: # %bb.0: ; SANDY: # %bb.0:
; SANDY-NEXT: vrcpps %ymm0, %ymm2 ; SANDY-NEXT: vrcpps %ymm0, %ymm2
; SANDY-NEXT: vmulps %ymm2, %ymm0, %ymm3
; SANDY-NEXT: vmovaps {{.*#+}} ymm4 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0] ; SANDY-NEXT: vmovaps {{.*#+}} ymm4 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]
; SANDY-NEXT: vmovaps {{.*#+}} ymm7 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0,5.0E+0,6.0E+0,7.0E+0,8.0E+0]
; SANDY-NEXT: vrcpps %ymm1, %ymm6
; SANDY-NEXT: vmulps %ymm2, %ymm0, %ymm3
; SANDY-NEXT: vsubps %ymm3, %ymm4, %ymm3 ; SANDY-NEXT: vsubps %ymm3, %ymm4, %ymm3
; SANDY-NEXT: vmulps %ymm3, %ymm2, %ymm3 ; SANDY-NEXT: vmulps %ymm3, %ymm2, %ymm3
; SANDY-NEXT: vaddps %ymm3, %ymm2, %ymm2 ; SANDY-NEXT: vaddps %ymm3, %ymm2, %ymm2
; SANDY-NEXT: vmovaps {{.*#+}} ymm3 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0,5.0E+0,6.0E+0,7.0E+0,8.0E+0] ; SANDY-NEXT: vmulps %ymm7, %ymm2, %ymm5
; SANDY-NEXT: vmulps %ymm3, %ymm2, %ymm5
; SANDY-NEXT: vmulps %ymm5, %ymm0, %ymm0 ; SANDY-NEXT: vmulps %ymm5, %ymm0, %ymm0
; SANDY-NEXT: vsubps %ymm0, %ymm3, %ymm0 ; SANDY-NEXT: vsubps %ymm0, %ymm7, %ymm0
; SANDY-NEXT: vrcpps %ymm1, %ymm3
; SANDY-NEXT: vmulps %ymm0, %ymm2, %ymm0 ; SANDY-NEXT: vmulps %ymm0, %ymm2, %ymm0
; SANDY-NEXT: vaddps %ymm0, %ymm5, %ymm0 ; SANDY-NEXT: vmulps %ymm6, %ymm1, %ymm2
; SANDY-NEXT: vmulps %ymm3, %ymm1, %ymm2
; SANDY-NEXT: vsubps %ymm2, %ymm4, %ymm2 ; SANDY-NEXT: vsubps %ymm2, %ymm4, %ymm2
; SANDY-NEXT: vmulps %ymm2, %ymm3, %ymm2 ; SANDY-NEXT: vaddps %ymm0, %ymm5, %ymm0
; SANDY-NEXT: vaddps %ymm2, %ymm3, %ymm2 ; SANDY-NEXT: vmovaps {{.*#+}} ymm5 = [9.0E+0,1.0E+1,1.1E+1,1.2E+1,1.3E+1,1.4E+1,1.5E+1,1.6E+1]
; SANDY-NEXT: vmovaps {{.*#+}} ymm3 = [9.0E+0,1.0E+1,1.1E+1,1.2E+1,1.3E+1,1.4E+1,1.5E+1,1.6E+1] ; SANDY-NEXT: vmulps %ymm2, %ymm6, %ymm2
; SANDY-NEXT: vmulps %ymm3, %ymm2, %ymm4 ; SANDY-NEXT: vaddps %ymm2, %ymm6, %ymm2
; SANDY-NEXT: vmulps %ymm5, %ymm2, %ymm4
; SANDY-NEXT: vmulps %ymm4, %ymm1, %ymm1 ; SANDY-NEXT: vmulps %ymm4, %ymm1, %ymm1
; SANDY-NEXT: vsubps %ymm1, %ymm3, %ymm1 ; SANDY-NEXT: vsubps %ymm1, %ymm5, %ymm1
; SANDY-NEXT: vmulps %ymm1, %ymm2, %ymm1 ; SANDY-NEXT: vmulps %ymm1, %ymm2, %ymm1
; SANDY-NEXT: vaddps %ymm1, %ymm4, %ymm1 ; SANDY-NEXT: vaddps %ymm1, %ymm4, %ymm1
; SANDY-NEXT: retq ; SANDY-NEXT: retq
; ;
; HASWELL-LABEL: v16f32_two_step2: ; HASWELL-LABEL: v16f32_two_step2:
; HASWELL: # %bb.0: ; HASWELL: # %bb.0:
; HASWELL-NEXT: vrcpps %ymm0, %ymm2 ; HASWELL-NEXT: vrcpps %ymm0, %ymm2
; HASWELL-NEXT: vbroadcastss {{.*#+}} ymm3 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0] ; HASWELL-NEXT: vbroadcastss {{.*#+}} ymm3 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]
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llvm/test/CodeGen/X86/rot32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- -mcpu=corei7 | FileCheck %s --check-prefix=CHECK32 --check-prefix=X86 ; RUN: llc < %s -mtriple=i686-- -mcpu=corei7 | FileCheck %s --check-prefix=CHECK32 --check-prefix=X86
; RUN: llc < %s -mtriple=i686-- -mcpu=corei7-avx | FileCheck %s --check-prefix=CHECK32 --check-prefix=SHLD ; RUN: llc < %s -mtriple=i686-- -mcpu=corei7-avx | FileCheck %s --check-prefix=CHECK32 --check-prefix=SHLD
; RUN: llc < %s -mtriple=i686-- -mcpu=core-avx2 | FileCheck %s --check-prefix=CHECK32 --check-prefix=BMI2 ; RUN: llc < %s -mtriple=i686-- -mcpu=core-avx2 | FileCheck %s --check-prefix=CHECK32 --check-prefix=BMI2
; RUN: llc < %s -mtriple=x86_64-- -mcpu=corei7 | FileCheck %s --check-prefix=CHECK64 --check-prefix=X64 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=corei7 | FileCheck %s --check-prefix=CHECK64 --check-prefix=X64
; RUN: llc < %s -mtriple=x86_64-- -mcpu=corei7-avx | FileCheck %s --check-prefix=CHECK64 --check-prefix=SHLD64 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=corei7-avx | FileCheck %s --check-prefix=CHECK64 --check-prefix=SHLD64
; RUN: llc < %s -mtriple=x86_64-- -mcpu=core-avx2 | FileCheck %s --check-prefix=CHECK64 --check-prefix=BMI264 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=core-avx2 | FileCheck %s --check-prefix=CHECK64 --check-prefix=BMI264
define i32 @foo(i32 %x, i32 %y, i32 %z) nounwind readnone { define i32 @foo(i32 %x, i32 %y, i32 %z) nounwind readnone {
; CHECK32-LABEL: foo: ; CHECK32-LABEL: foo:
; CHECK32: # %bb.0: # %entry ; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: movb {{[0-9]+}}(%esp), %cl ; CHECK32-NEXT: movb {{[0-9]+}}(%esp), %cl
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: roll %cl, %eax ; CHECK32-NEXT: roll %cl, %eax
; CHECK32-NEXT: retl ; CHECK32-NEXT: retl
; ;
; CHECK64-LABEL: foo: ; X64-LABEL: foo:
; CHECK64: # %bb.0: # %entry ; X64: # %bb.0: # %entry
; CHECK64-NEXT: movl %edx, %ecx ; X64-NEXT: movl %edi, %eax
; CHECK64-NEXT: movl %edi, %eax ; X64-NEXT: movl %edx, %ecx
; CHECK64-NEXT: # kill: def $cl killed $cl killed $ecx ; X64-NEXT: # kill: def $cl killed $cl killed $ecx
; CHECK64-NEXT: roll %cl, %eax ; X64-NEXT: roll %cl, %eax
; CHECK64-NEXT: retq ; X64-NEXT: retq
;
; SHLD64-LABEL: foo:
; SHLD64: # %bb.0: # %entry
; SHLD64-NEXT: movl %edi, %eax
; SHLD64-NEXT: movl %edx, %ecx
; SHLD64-NEXT: # kill: def $cl killed $cl killed $ecx
; SHLD64-NEXT: roll %cl, %eax
; SHLD64-NEXT: retq
;
; BMI264-LABEL: foo:
; BMI264: # %bb.0: # %entry
; BMI264-NEXT: movl %edx, %ecx
; BMI264-NEXT: movl %edi, %eax
; BMI264-NEXT: # kill: def $cl killed $cl killed $ecx
; BMI264-NEXT: roll %cl, %eax
; BMI264-NEXT: retq
entry: entry:
%0 = shl i32 %x, %z %0 = shl i32 %x, %z
%1 = sub i32 32, %z %1 = sub i32 32, %z
%2 = lshr i32 %x, %1 %2 = lshr i32 %x, %1
%3 = or i32 %2, %0 %3 = or i32 %2, %0
ret i32 %3 ret i32 %3
} }
define i32 @bar(i32 %x, i32 %y, i32 %z) nounwind readnone { define i32 @bar(i32 %x, i32 %y, i32 %z) nounwind readnone {
; CHECK32-LABEL: bar: ; CHECK32-LABEL: bar:
; CHECK32: # %bb.0: # %entry ; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: movb {{[0-9]+}}(%esp), %cl ; CHECK32-NEXT: movb {{[0-9]+}}(%esp), %cl
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edx ; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: shldl %cl, %edx, %eax ; CHECK32-NEXT: shldl %cl, %edx, %eax
; CHECK32-NEXT: retl ; CHECK32-NEXT: retl
; ;
; CHECK64-LABEL: bar: ; X64-LABEL: bar:
; CHECK64: # %bb.0: # %entry ; X64: # %bb.0: # %entry
; CHECK64-NEXT: movl %edx, %ecx ; X64-NEXT: movl %esi, %eax
; CHECK64-NEXT: movl %esi, %eax ; X64-NEXT: movl %edx, %ecx
; CHECK64-NEXT: # kill: def $cl killed $cl killed $ecx ; X64-NEXT: # kill: def $cl killed $cl killed $ecx
; CHECK64-NEXT: shldl %cl, %edi, %eax ; X64-NEXT: shldl %cl, %edi, %eax
; CHECK64-NEXT: retq ; X64-NEXT: retq
;
; SHLD64-LABEL: bar:
; SHLD64: # %bb.0: # %entry
; SHLD64-NEXT: movl %esi, %eax
; SHLD64-NEXT: movl %edx, %ecx
; SHLD64-NEXT: # kill: def $cl killed $cl killed $ecx
; SHLD64-NEXT: shldl %cl, %edi, %eax
; SHLD64-NEXT: retq
;
; BMI264-LABEL: bar:
; BMI264: # %bb.0: # %entry
; BMI264-NEXT: movl %edx, %ecx
; BMI264-NEXT: movl %esi, %eax
; BMI264-NEXT: # kill: def $cl killed $cl killed $ecx
; BMI264-NEXT: shldl %cl, %edi, %eax
; BMI264-NEXT: retq
entry: entry:
%0 = shl i32 %y, %z %0 = shl i32 %y, %z
%1 = sub i32 32, %z %1 = sub i32 32, %z
%2 = lshr i32 %x, %1 %2 = lshr i32 %x, %1
%3 = or i32 %2, %0 %3 = or i32 %2, %0
ret i32 %3 ret i32 %3
} }
define i32 @un(i32 %x, i32 %y, i32 %z) nounwind readnone { define i32 @un(i32 %x, i32 %y, i32 %z) nounwind readnone {
; CHECK32-LABEL: un: ; CHECK32-LABEL: un:
; CHECK32: # %bb.0: # %entry ; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: movb {{[0-9]+}}(%esp), %cl ; CHECK32-NEXT: movb {{[0-9]+}}(%esp), %cl
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: rorl %cl, %eax ; CHECK32-NEXT: rorl %cl, %eax
; CHECK32-NEXT: retl ; CHECK32-NEXT: retl
; ;
; CHECK64-LABEL: un: ; X64-LABEL: un:
; CHECK64: # %bb.0: # %entry ; X64: # %bb.0: # %entry
; CHECK64-NEXT: movl %edx, %ecx ; X64-NEXT: movl %edi, %eax
; CHECK64-NEXT: movl %edi, %eax ; X64-NEXT: movl %edx, %ecx
; CHECK64-NEXT: # kill: def $cl killed $cl killed $ecx ; X64-NEXT: # kill: def $cl killed $cl killed $ecx
; CHECK64-NEXT: rorl %cl, %eax ; X64-NEXT: rorl %cl, %eax
; CHECK64-NEXT: retq ; X64-NEXT: retq
;
; SHLD64-LABEL: un:
; SHLD64: # %bb.0: # %entry
; SHLD64-NEXT: movl %edi, %eax
; SHLD64-NEXT: movl %edx, %ecx
; SHLD64-NEXT: # kill: def $cl killed $cl killed $ecx
; SHLD64-NEXT: rorl %cl, %eax
; SHLD64-NEXT: retq
;
; BMI264-LABEL: un:
; BMI264: # %bb.0: # %entry
; BMI264-NEXT: movl %edx, %ecx
; BMI264-NEXT: movl %edi, %eax
; BMI264-NEXT: # kill: def $cl killed $cl killed $ecx
; BMI264-NEXT: rorl %cl, %eax
; BMI264-NEXT: retq
entry: entry:
%0 = lshr i32 %x, %z %0 = lshr i32 %x, %z
%1 = sub i32 32, %z %1 = sub i32 32, %z
%2 = shl i32 %x, %1 %2 = shl i32 %x, %1
%3 = or i32 %2, %0 %3 = or i32 %2, %0
ret i32 %3 ret i32 %3
} }
define i32 @bu(i32 %x, i32 %y, i32 %z) nounwind readnone { define i32 @bu(i32 %x, i32 %y, i32 %z) nounwind readnone {
; CHECK32-LABEL: bu: ; CHECK32-LABEL: bu:
; CHECK32: # %bb.0: # %entry ; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: movb {{[0-9]+}}(%esp), %cl ; CHECK32-NEXT: movb {{[0-9]+}}(%esp), %cl
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edx ; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: shrdl %cl, %edx, %eax ; CHECK32-NEXT: shrdl %cl, %edx, %eax
; CHECK32-NEXT: retl ; CHECK32-NEXT: retl
; ;
; CHECK64-LABEL: bu: ; X64-LABEL: bu:
; CHECK64: # %bb.0: # %entry ; X64: # %bb.0: # %entry
; CHECK64-NEXT: movl %edx, %ecx ; X64-NEXT: movl %esi, %eax
; CHECK64-NEXT: movl %esi, %eax ; X64-NEXT: movl %edx, %ecx
; CHECK64-NEXT: # kill: def $cl killed $cl killed $ecx ; X64-NEXT: # kill: def $cl killed $cl killed $ecx
; CHECK64-NEXT: shrdl %cl, %edi, %eax ; X64-NEXT: shrdl %cl, %edi, %eax
; CHECK64-NEXT: retq ; X64-NEXT: retq
;
; SHLD64-LABEL: bu:
; SHLD64: # %bb.0: # %entry
; SHLD64-NEXT: movl %esi, %eax
; SHLD64-NEXT: movl %edx, %ecx
; SHLD64-NEXT: # kill: def $cl killed $cl killed $ecx
; SHLD64-NEXT: shrdl %cl, %edi, %eax
; SHLD64-NEXT: retq
;
; BMI264-LABEL: bu:
; BMI264: # %bb.0: # %entry
; BMI264-NEXT: movl %edx, %ecx
; BMI264-NEXT: movl %esi, %eax
; BMI264-NEXT: # kill: def $cl killed $cl killed $ecx
; BMI264-NEXT: shrdl %cl, %edi, %eax
; BMI264-NEXT: retq
entry: entry:
%0 = lshr i32 %y, %z %0 = lshr i32 %y, %z
%1 = sub i32 32, %z %1 = sub i32 32, %z
%2 = shl i32 %x, %1 %2 = shl i32 %x, %1
%3 = or i32 %2, %0 %3 = or i32 %2, %0
ret i32 %3 ret i32 %3
} }
▲ Show 20 Lines • Show All 527 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/rot64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- -mcpu=corei7 | FileCheck %s --check-prefix=ALL --check-prefix=X64 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=corei7 | FileCheck %s --check-prefix=ALL --check-prefix=X64
; RUN: llc < %s -mtriple=x86_64-- -mcpu=corei7-avx | FileCheck %s --check-prefix=ALL --check-prefix=SHLD ; RUN: llc < %s -mtriple=x86_64-- -mcpu=corei7-avx | FileCheck %s --check-prefix=ALL --check-prefix=SHLD
; RUN: llc < %s -mtriple=x86_64-- -mcpu=core-avx2 | FileCheck %s --check-prefix=ALL --check-prefix=BMI2 ; RUN: llc < %s -mtriple=x86_64-- -mcpu=core-avx2 | FileCheck %s --check-prefix=ALL --check-prefix=BMI2
define i64 @foo(i64 %x, i64 %y, i64 %z) nounwind readnone { define i64 @foo(i64 %x, i64 %y, i64 %z) nounwind readnone {
; ALL-LABEL: foo: ; X64-LABEL: foo:
; ALL: # %bb.0: # %entry ; X64: # %bb.0: # %entry
; ALL-NEXT: movq %rdx, %rcx ; X64-NEXT: movq %rdi, %rax
; ALL-NEXT: movq %rdi, %rax ; X64-NEXT: movq %rdx, %rcx
; ALL-NEXT: # kill: def $cl killed $cl killed $rcx ; X64-NEXT: # kill: def $cl killed $cl killed $rcx
; ALL-NEXT: rolq %cl, %rax ; X64-NEXT: rolq %cl, %rax
; ALL-NEXT: retq ; X64-NEXT: retq
;
; SHLD-LABEL: foo:
; SHLD: # %bb.0: # %entry
; SHLD-NEXT: movq %rdi, %rax
; SHLD-NEXT: movq %rdx, %rcx
; SHLD-NEXT: # kill: def $cl killed $cl killed $rcx
; SHLD-NEXT: rolq %cl, %rax
; SHLD-NEXT: retq
;
; BMI2-LABEL: foo:
; BMI2: # %bb.0: # %entry
; BMI2-NEXT: movq %rdx, %rcx
; BMI2-NEXT: movq %rdi, %rax
; BMI2-NEXT: # kill: def $cl killed $cl killed $rcx
; BMI2-NEXT: rolq %cl, %rax
; BMI2-NEXT: retq
entry: entry:
%0 = shl i64 %x, %z %0 = shl i64 %x, %z
%1 = sub i64 64, %z %1 = sub i64 64, %z
%2 = lshr i64 %x, %1 %2 = lshr i64 %x, %1
%3 = or i64 %2, %0 %3 = or i64 %2, %0
ret i64 %3 ret i64 %3
} }
define i64 @bar(i64 %x, i64 %y, i64 %z) nounwind readnone { define i64 @bar(i64 %x, i64 %y, i64 %z) nounwind readnone {
; ALL-LABEL: bar: ; X64-LABEL: bar:
; ALL: # %bb.0: # %entry ; X64: # %bb.0: # %entry
; ALL-NEXT: movq %rdx, %rcx ; X64-NEXT: movq %rsi, %rax
; ALL-NEXT: movq %rsi, %rax ; X64-NEXT: movq %rdx, %rcx
; ALL-NEXT: # kill: def $cl killed $cl killed $rcx ; X64-NEXT: # kill: def $cl killed $cl killed $rcx
; ALL-NEXT: shldq %cl, %rdi, %rax ; X64-NEXT: shldq %cl, %rdi, %rax
; ALL-NEXT: retq ; X64-NEXT: retq
;
; SHLD-LABEL: bar:
; SHLD: # %bb.0: # %entry
; SHLD-NEXT: movq %rsi, %rax
; SHLD-NEXT: movq %rdx, %rcx
; SHLD-NEXT: # kill: def $cl killed $cl killed $rcx
; SHLD-NEXT: shldq %cl, %rdi, %rax
; SHLD-NEXT: retq
;
; BMI2-LABEL: bar:
; BMI2: # %bb.0: # %entry
; BMI2-NEXT: movq %rdx, %rcx
; BMI2-NEXT: movq %rsi, %rax
; BMI2-NEXT: # kill: def $cl killed $cl killed $rcx
; BMI2-NEXT: shldq %cl, %rdi, %rax
; BMI2-NEXT: retq
entry: entry:
%0 = shl i64 %y, %z %0 = shl i64 %y, %z
%1 = sub i64 64, %z %1 = sub i64 64, %z
%2 = lshr i64 %x, %1 %2 = lshr i64 %x, %1
%3 = or i64 %2, %0 %3 = or i64 %2, %0
ret i64 %3 ret i64 %3
} }
define i64 @un(i64 %x, i64 %y, i64 %z) nounwind readnone { define i64 @un(i64 %x, i64 %y, i64 %z) nounwind readnone {
; ALL-LABEL: un: ; X64-LABEL: un:
; ALL: # %bb.0: # %entry ; X64: # %bb.0: # %entry
; ALL-NEXT: movq %rdx, %rcx ; X64-NEXT: movq %rdi, %rax
; ALL-NEXT: movq %rdi, %rax ; X64-NEXT: movq %rdx, %rcx
; ALL-NEXT: # kill: def $cl killed $cl killed $rcx ; X64-NEXT: # kill: def $cl killed $cl killed $rcx
; ALL-NEXT: rorq %cl, %rax ; X64-NEXT: rorq %cl, %rax
; ALL-NEXT: retq ; X64-NEXT: retq
;
; SHLD-LABEL: un:
; SHLD: # %bb.0: # %entry
; SHLD-NEXT: movq %rdi, %rax
; SHLD-NEXT: movq %rdx, %rcx
; SHLD-NEXT: # kill: def $cl killed $cl killed $rcx
; SHLD-NEXT: rorq %cl, %rax
; SHLD-NEXT: retq
;
; BMI2-LABEL: un:
; BMI2: # %bb.0: # %entry
; BMI2-NEXT: movq %rdx, %rcx
; BMI2-NEXT: movq %rdi, %rax
; BMI2-NEXT: # kill: def $cl killed $cl killed $rcx
; BMI2-NEXT: rorq %cl, %rax
; BMI2-NEXT: retq
entry: entry:
%0 = lshr i64 %x, %z %0 = lshr i64 %x, %z
%1 = sub i64 64, %z %1 = sub i64 64, %z
%2 = shl i64 %x, %1 %2 = shl i64 %x, %1
%3 = or i64 %2, %0 %3 = or i64 %2, %0
ret i64 %3 ret i64 %3
} }
define i64 @bu(i64 %x, i64 %y, i64 %z) nounwind readnone { define i64 @bu(i64 %x, i64 %y, i64 %z) nounwind readnone {
; ALL-LABEL: bu: ; X64-LABEL: bu:
; ALL: # %bb.0: # %entry ; X64: # %bb.0: # %entry
; ALL-NEXT: movq %rdx, %rcx ; X64-NEXT: movq %rsi, %rax
; ALL-NEXT: movq %rsi, %rax ; X64-NEXT: movq %rdx, %rcx
; ALL-NEXT: # kill: def $cl killed $cl killed $rcx ; X64-NEXT: # kill: def $cl killed $cl killed $rcx
; ALL-NEXT: shrdq %cl, %rdi, %rax ; X64-NEXT: shrdq %cl, %rdi, %rax
; ALL-NEXT: retq ; X64-NEXT: retq
;
; SHLD-LABEL: bu:
; SHLD: # %bb.0: # %entry
; SHLD-NEXT: movq %rsi, %rax
; SHLD-NEXT: movq %rdx, %rcx
; SHLD-NEXT: # kill: def $cl killed $cl killed $rcx
; SHLD-NEXT: shrdq %cl, %rdi, %rax
; SHLD-NEXT: retq
;
; BMI2-LABEL: bu:
; BMI2: # %bb.0: # %entry
; BMI2-NEXT: movq %rdx, %rcx
; BMI2-NEXT: movq %rsi, %rax
; BMI2-NEXT: # kill: def $cl killed $cl killed $rcx
; BMI2-NEXT: shrdq %cl, %rdi, %rax
; BMI2-NEXT: retq
entry: entry:
%0 = lshr i64 %y, %z %0 = lshr i64 %y, %z
%1 = sub i64 64, %z %1 = sub i64 64, %z
%2 = shl i64 %x, %1 %2 = shl i64 %x, %1
%3 = or i64 %2, %0 %3 = or i64 %2, %0
ret i64 %3 ret i64 %3
} }
▲ Show 20 Lines • Show All 295 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/sandybridge-loads.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=corei7-avx | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=corei7-avx | FileCheck %s
define void @wideloads(<8 x float>* %a, <8 x float>* %b, <8 x float>* %c) nounwind { define void @wideloads(<8 x float>* %a, <8 x float>* %b, <8 x float>* %c) nounwind {
; CHECK-LABEL: wideloads: ; CHECK-LABEL: wideloads:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmovaps (%rdi), %xmm0 ; CHECK-NEXT: vmovaps (%rdi), %xmm0
; CHECK-NEXT: vinsertf128 $1, 16(%rdi), %ymm0, %ymm0
; CHECK-NEXT: vmovaps (%rsi), %ymm1 ; CHECK-NEXT: vmovaps (%rsi), %ymm1
; CHECK-NEXT: vcmpltps %ymm0, %ymm1, %ymm1
; CHECK-NEXT: vmovaps (%rdx), %ymm2 ; CHECK-NEXT: vmovaps (%rdx), %ymm2
; CHECK-NEXT: vinsertf128 $1, 16(%rdi), %ymm0, %ymm0
; CHECK-NEXT: vcmpltps %ymm0, %ymm1, %ymm1
; CHECK-NEXT: vcmpltps %ymm0, %ymm2, %ymm0 ; CHECK-NEXT: vcmpltps %ymm0, %ymm2, %ymm0
; CHECK-NEXT: vandps %ymm1, %ymm0, %ymm0 ; CHECK-NEXT: vandps %ymm1, %ymm0, %ymm0
; CHECK-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0 ; CHECK-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
; CHECK-NEXT: vmovaps %ymm0, (%rax) ; CHECK-NEXT: vmovaps %ymm0, (%rax)
; CHECK-NEXT: vzeroupper ; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%v0 = load <8 x float>, <8 x float>* %a, align 16 ; <---- unaligned! %v0 = load <8 x float>, <8 x float>* %a, align 16 ; <---- unaligned!
%v1 = load <8 x float>, <8 x float>* %b, align 32 ; <---- aligned! %v1 = load <8 x float>, <8 x float>* %b, align 32 ; <---- aligned!
▲ Show 20 Lines • Show All 43 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/sibcall.ll

Show First 20 Lines • Show All 356 Lines • ▼ Show 20 Lines
define %struct.ns* @t13(%struct.cp* %yy) nounwind ssp { define %struct.ns* @t13(%struct.cp* %yy) nounwind ssp {
; X86-LABEL: t13: ; X86-LABEL: t13:
; X86: # %bb.0: # %entry ; X86: # %bb.0: # %entry
; X86-NEXT: subl $28, %esp ; X86-NEXT: subl $28, %esp
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl 16(%eax), %ecx ; X86-NEXT: movl 16(%eax), %ecx
; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) ; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp)
; X86-NEXT: xorl %ecx, %ecx
; X86-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; X86-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; X86-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero ; X86-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; X86-NEXT: movsd %xmm1, {{[0-9]+}}(%esp) ; X86-NEXT: movsd %xmm1, {{[0-9]+}}(%esp)
; X86-NEXT: movsd %xmm0, (%esp) ; X86-NEXT: movsd %xmm0, (%esp)
; X86-NEXT: xorl %ecx, %ecx
; X86-NEXT: calll foo7 ; X86-NEXT: calll foo7
; X86-NEXT: addl $28, %esp ; X86-NEXT: addl $28, %esp
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: t13: ; X64-LABEL: t13:
; X64: # %bb.0: # %entry ; X64: # %bb.0: # %entry
; X64-NEXT: pushq %rax ; X64-NEXT: pushq %rax
; X64-NEXT: subq $8, %rsp ; X64-NEXT: subq $8, %rsp
▲ Show 20 Lines • Show All 323 Lines • ▼ Show 20 Lines; X32-NEXT: retq
ret void ret void
} }
define fastcc void @t21_sret_to_sret_more_args(%struct.foo* noalias sret %agg.result, i32 %a, i32 %b) nounwind { define fastcc void @t21_sret_to_sret_more_args(%struct.foo* noalias sret %agg.result, i32 %a, i32 %b) nounwind {
; X86-LABEL: t21_sret_to_sret_more_args: ; X86-LABEL: t21_sret_to_sret_more_args:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: pushl %esi ; X86-NEXT: pushl %esi
; X86-NEXT: subl $8, %esp ; X86-NEXT: subl $8, %esp
; X86-NEXT: movl %ecx, %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl %ecx, %esi
; X86-NEXT: movl %eax, (%esp) ; X86-NEXT: movl %eax, (%esp)
; X86-NEXT: calll f_sret ; X86-NEXT: calll f_sret
; X86-NEXT: movl %esi, %eax ; X86-NEXT: movl %esi, %eax
; X86-NEXT: addl $8, %esp ; X86-NEXT: addl $8, %esp
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: t21_sret_to_sret_more_args: ; X64-LABEL: t21_sret_to_sret_more_args:
Show All 17 Lines; X32-NEXT: retq
ret void ret void
} }
define fastcc void @t21_sret_to_sret_second_arg_sret(%struct.foo* noalias %agg.result, %struct.foo* noalias sret %ret) nounwind { define fastcc void @t21_sret_to_sret_second_arg_sret(%struct.foo* noalias %agg.result, %struct.foo* noalias sret %ret) nounwind {
; X86-LABEL: t21_sret_to_sret_second_arg_sret: ; X86-LABEL: t21_sret_to_sret_second_arg_sret:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: pushl %esi ; X86-NEXT: pushl %esi
; X86-NEXT: subl $8, %esp ; X86-NEXT: subl $8, %esp
; X86-NEXT: movl %edx, %esi
; X86-NEXT: movl %edx, %ecx ; X86-NEXT: movl %edx, %ecx
; X86-NEXT: movl %edx, %esi
; X86-NEXT: calll t21_f_sret ; X86-NEXT: calll t21_f_sret
; X86-NEXT: movl %esi, %eax ; X86-NEXT: movl %esi, %eax
; X86-NEXT: addl $8, %esp ; X86-NEXT: addl $8, %esp
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: t21_sret_to_sret_second_arg_sret: ; X64-LABEL: t21_sret_to_sret_second_arg_sret:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: pushq %rbx ; X64-NEXT: pushq %rbx
; X64-NEXT: movq %rsi, %rbx
; X64-NEXT: movq %rsi, %rdi ; X64-NEXT: movq %rsi, %rdi
; X64-NEXT: movq %rsi, %rbx
; X64-NEXT: callq t21_f_sret ; X64-NEXT: callq t21_f_sret
; X64-NEXT: movq %rbx, %rax ; X64-NEXT: movq %rbx, %rax
; X64-NEXT: popq %rbx ; X64-NEXT: popq %rbx
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X32-LABEL: t21_sret_to_sret_second_arg_sret: ; X32-LABEL: t21_sret_to_sret_second_arg_sret:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: pushq %rbx ; X32-NEXT: pushq %rbx
; X32-NEXT: movl %esi, %ebx
; X32-NEXT: movl %esi, %edi ; X32-NEXT: movl %esi, %edi
; X32-NEXT: movl %esi, %ebx
; X32-NEXT: callq t21_f_sret ; X32-NEXT: callq t21_f_sret
; X32-NEXT: movl %ebx, %eax ; X32-NEXT: movl %ebx, %eax
; X32-NEXT: popq %rbx ; X32-NEXT: popq %rbx
; X32-NEXT: retq ; X32-NEXT: retq
tail call fastcc void @t21_f_sret(%struct.foo* noalias sret %ret) nounwind tail call fastcc void @t21_f_sret(%struct.foo* noalias sret %ret) nounwind
ret void ret void
} }
define fastcc void @t21_sret_to_sret_more_args2(%struct.foo* noalias sret %agg.result, i32 %a, i32 %b) nounwind { define fastcc void @t21_sret_to_sret_more_args2(%struct.foo* noalias sret %agg.result, i32 %a, i32 %b) nounwind {
; X86-LABEL: t21_sret_to_sret_more_args2: ; X86-LABEL: t21_sret_to_sret_more_args2:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: pushl %esi ; X86-NEXT: pushl %esi
; X86-NEXT: subl $8, %esp ; X86-NEXT: subl $8, %esp
; X86-NEXT: movl %ecx, %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl %edx, (%esp) ; X86-NEXT: movl %edx, (%esp)
; X86-NEXT: movl %ecx, %esi
; X86-NEXT: movl %eax, %edx ; X86-NEXT: movl %eax, %edx
; X86-NEXT: calll f_sret ; X86-NEXT: calll f_sret
; X86-NEXT: movl %esi, %eax ; X86-NEXT: movl %esi, %eax
; X86-NEXT: addl $8, %esp ; X86-NEXT: addl $8, %esp
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: t21_sret_to_sret_more_args2: ; X64-LABEL: t21_sret_to_sret_more_args2:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: pushq %rbx ; X64-NEXT: pushq %rbx
; X64-NEXT: movl %esi, %eax ; X64-NEXT: movl %esi, %eax
; X64-NEXT: movq %rdi, %rbx
; X64-NEXT: movl %edx, %esi ; X64-NEXT: movl %edx, %esi
; X64-NEXT: movq %rdi, %rbx
; X64-NEXT: movl %eax, %edx ; X64-NEXT: movl %eax, %edx
; X64-NEXT: callq f_sret ; X64-NEXT: callq f_sret
; X64-NEXT: movq %rbx, %rax ; X64-NEXT: movq %rbx, %rax
; X64-NEXT: popq %rbx ; X64-NEXT: popq %rbx
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X32-LABEL: t21_sret_to_sret_more_args2: ; X32-LABEL: t21_sret_to_sret_more_args2:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: pushq %rbx ; X32-NEXT: pushq %rbx
; X32-NEXT: movl %esi, %eax ; X32-NEXT: movl %esi, %eax
; X32-NEXT: movl %edi, %ebx
; X32-NEXT: movl %edx, %esi ; X32-NEXT: movl %edx, %esi
; X32-NEXT: movl %edi, %ebx
; X32-NEXT: movl %eax, %edx ; X32-NEXT: movl %eax, %edx
; X32-NEXT: callq f_sret ; X32-NEXT: callq f_sret
; X32-NEXT: movl %ebx, %eax ; X32-NEXT: movl %ebx, %eax
; X32-NEXT: popq %rbx ; X32-NEXT: popq %rbx
; X32-NEXT: retq ; X32-NEXT: retq
tail call fastcc void @f_sret(%struct.foo* noalias sret %agg.result, i32 %b, i32 %a) nounwind tail call fastcc void @f_sret(%struct.foo* noalias sret %agg.result, i32 %b, i32 %a) nounwind
ret void ret void
} }
▲ Show 20 Lines • Show All 241 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/sjlj.ll

Show All 20 Linesdefine i32 @sj0() nounwind {
%r = tail call i32 @llvm.eh.sjlj.setjmp(i8* bitcast ([5 x i8*]* @buf to i8*)) %r = tail call i32 @llvm.eh.sjlj.setjmp(i8* bitcast ([5 x i8*]* @buf to i8*))
ret i32 %r ret i32 %r
; X86: sj0 ; X86: sj0
; x86: movl %ebp, buf ; x86: movl %ebp, buf
; X86: movl %esp, buf+8 ; X86: movl %esp, buf+8
; x86: movl ${{.*LBB.*}}, buf+4 ; x86: movl ${{.*LBB.*}}, buf+4
; X86: ret ; X86: ret
; PIC86: sj0 ; PIC86: sj0
; PIC86: movl %ebp, buf@GOTOFF(%[[GOT:.*]]) ; PIC86: leal {{.*LBB.*}}@GOTOFF(%[[GOT:.*]]), %[[LREG:.*]]
; PIC86: movl %ebp, buf@GOTOFF(%[[GOT]])
; PIC86: movl %esp, buf@GOTOFF+8(%[[GOT]]) ; PIC86: movl %esp, buf@GOTOFF+8(%[[GOT]])
; PIC86: leal {{.*LBB.*}}@GOTOFF(%[[GOT]]), %[[LREG:.*]]
; PIC86: movl %[[LREG]], buf@GOTOFF+4 ; PIC86: movl %[[LREG]], buf@GOTOFF+4
; PIC86: ret ; PIC86: ret
; X64: sj0 ; X64: sj0
; x64: movq %rbp, buf(%rip) ; x64: movq %rbp, buf(%rip)
; x64: movq ${{.*LBB.*}}, buf+8(%rip) ; x64: movq ${{.*LBB.*}}, buf+8(%rip)
; X64: movq %rsp, buf+16(%rip) ; X64: movq %rsp, buf+16(%rip)
; X64: ret ; X64: ret
; PIC64: sj0 ; PIC64: sj0
; PIC64: leaq {{.*LBB.*}}(%rip), %[[LREG:.*]]
; PIC64: movq %rbp, buf(%rip) ; PIC64: movq %rbp, buf(%rip)
; PIC64: movq %rsp, buf+16(%rip) ; PIC64: movq %rsp, buf+16(%rip)
; PIC64: leaq {{.*LBB.*}}(%rip), %[[LREG:.*]]
; PIC64: movq %[[LREG]], buf+8(%rip) ; PIC64: movq %[[LREG]], buf+8(%rip)
; PIC64: ret ; PIC64: ret
} }
define void @lj0() nounwind { define void @lj0() nounwind {
tail call void @llvm.eh.sjlj.longjmp(i8* bitcast ([5 x i8*]* @buf to i8*)) tail call void @llvm.eh.sjlj.longjmp(i8* bitcast ([5 x i8*]* @buf to i8*))
unreachable unreachable
; X86: lj0 ; X86: lj0
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llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- -mcpu=nehalem | FileCheck %s --check-prefixes=NHM ; RUN: llc < %s -mtriple=x86_64-- -mcpu=nehalem | FileCheck %s --check-prefixes=NHM
; RUN: llc < %s -mtriple=x86_64-- -mcpu=sandybridge | FileCheck %s --check-prefixes=FAST-SCALAR,SNB ; RUN: llc < %s -mtriple=x86_64-- -mcpu=sandybridge | FileCheck %s --check-prefixes=FAST-SCALAR,SNB
; RUN: llc < %s -mtriple=x86_64-- -mcpu=broadwell | FileCheck %s --check-prefixes=FAST-SCALAR,BDW ; RUN: llc < %s -mtriple=x86_64-- -mcpu=broadwell | FileCheck %s --check-prefixes=FAST-SCALAR,BDW
; RUN: llc < %s -mtriple=x86_64-- -mcpu=skylake | FileCheck %s --check-prefixes=FAST-SCALAR,SKL ; RUN: llc < %s -mtriple=x86_64-- -mcpu=skylake | FileCheck %s --check-prefixes=FAST-SCALAR,SKL
define float @f32_no_daz(float %f) #0 { define float @f32_no_daz(float %f) #0 {
; NHM-LABEL: f32_no_daz: ; NHM-LABEL: f32_no_daz:
; NHM: # %bb.0: ; NHM: # %bb.0:
; NHM-NEXT: rsqrtss %xmm0, %xmm1 ; NHM-NEXT: rsqrtss %xmm0, %xmm1
; NHM-NEXT: movaps %xmm0, %xmm2 ; NHM-NEXT: movaps %xmm0, %xmm2
; NHM-NEXT: mulss %xmm1, %xmm2
; NHM-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero ; NHM-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
; NHM-NEXT: andps {{.*}}(%rip), %xmm0
; NHM-NEXT: cmpltss {{.*}}(%rip), %xmm0
; NHM-NEXT: mulss %xmm1, %xmm2
; NHM-NEXT: mulss %xmm2, %xmm3 ; NHM-NEXT: mulss %xmm2, %xmm3
; NHM-NEXT: mulss %xmm1, %xmm2 ; NHM-NEXT: mulss %xmm1, %xmm2
; NHM-NEXT: addss {{.*}}(%rip), %xmm2 ; NHM-NEXT: addss {{.*}}(%rip), %xmm2
; NHM-NEXT: andps {{.*}}(%rip), %xmm0
; NHM-NEXT: mulss %xmm3, %xmm2 ; NHM-NEXT: mulss %xmm3, %xmm2
; NHM-NEXT: cmpltss {{.*}}(%rip), %xmm0
; NHM-NEXT: andnps %xmm2, %xmm0 ; NHM-NEXT: andnps %xmm2, %xmm0
; NHM-NEXT: retq ; NHM-NEXT: retq
; ;
; FAST-SCALAR-LABEL: f32_no_daz: ; FAST-SCALAR-LABEL: f32_no_daz:
; FAST-SCALAR: # %bb.0: ; FAST-SCALAR: # %bb.0:
; FAST-SCALAR-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 ; FAST-SCALAR-NEXT: vsqrtss %xmm0, %xmm0, %xmm0
; FAST-SCALAR-NEXT: retq ; FAST-SCALAR-NEXT: retq
%call = tail call fast float @llvm.sqrt.f32(float %f) #2 %call = tail call fast float @llvm.sqrt.f32(float %f) #2
ret float %call ret float %call
} }
define <4 x float> @v4f32_no_daz(<4 x float> %f) #0 { define <4 x float> @v4f32_no_daz(<4 x float> %f) #0 {
; NHM-LABEL: v4f32_no_daz: ; NHM-LABEL: v4f32_no_daz:
; NHM: # %bb.0: ; NHM: # %bb.0:
; NHM-NEXT: rsqrtps %xmm0, %xmm2 ; NHM-NEXT: rsqrtps %xmm0, %xmm2
; NHM-NEXT: movaps %xmm0, %xmm1 ; NHM-NEXT: movaps %xmm0, %xmm1
; NHM-NEXT: mulps %xmm2, %xmm1
; NHM-NEXT: movaps {{.*#+}} xmm3 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1] ; NHM-NEXT: movaps {{.*#+}} xmm3 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
; NHM-NEXT: andps {{.*}}(%rip), %xmm0
; NHM-NEXT: mulps %xmm2, %xmm1
; NHM-NEXT: mulps %xmm1, %xmm3 ; NHM-NEXT: mulps %xmm1, %xmm3
; NHM-NEXT: mulps %xmm2, %xmm1 ; NHM-NEXT: mulps %xmm2, %xmm1
; NHM-NEXT: addps {{.*}}(%rip), %xmm1 ; NHM-NEXT: addps {{.*}}(%rip), %xmm1
; NHM-NEXT: andps {{.*}}(%rip), %xmm0
; NHM-NEXT: mulps %xmm3, %xmm1
; NHM-NEXT: movaps {{.*#+}} xmm2 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38] ; NHM-NEXT: movaps {{.*#+}} xmm2 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38]
; NHM-NEXT: cmpleps %xmm0, %xmm2 ; NHM-NEXT: cmpleps %xmm0, %xmm2
; NHM-NEXT: mulps %xmm3, %xmm1
; NHM-NEXT: andps %xmm2, %xmm1 ; NHM-NEXT: andps %xmm2, %xmm1
; NHM-NEXT: movaps %xmm1, %xmm0 ; NHM-NEXT: movaps %xmm1, %xmm0
; NHM-NEXT: retq ; NHM-NEXT: retq
; ;
; SNB-LABEL: v4f32_no_daz: ; SNB-LABEL: v4f32_no_daz:
; SNB: # %bb.0: ; SNB: # %bb.0:
; SNB-NEXT: vrsqrtps %xmm0, %xmm1 ; SNB-NEXT: vrsqrtps %xmm0, %xmm1
; SNB-NEXT: vmulps %xmm1, %xmm0, %xmm2 ; SNB-NEXT: vmulps %xmm1, %xmm0, %xmm2
; SNB-NEXT: vmulps {{.*}}(%rip), %xmm2, %xmm3 ; SNB-NEXT: vmulps {{.*}}(%rip), %xmm2, %xmm3
; SNB-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
; SNB-NEXT: vmulps %xmm1, %xmm2, %xmm1 ; SNB-NEXT: vmulps %xmm1, %xmm2, %xmm1
; SNB-NEXT: vaddps {{.*}}(%rip), %xmm1, %xmm1 ; SNB-NEXT: vaddps {{.*}}(%rip), %xmm1, %xmm1
; SNB-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
; SNB-NEXT: vmulps %xmm1, %xmm3, %xmm1
; SNB-NEXT: vmovaps {{.*#+}} xmm2 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38] ; SNB-NEXT: vmovaps {{.*#+}} xmm2 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38]
; SNB-NEXT: vcmpleps %xmm0, %xmm2, %xmm0 ; SNB-NEXT: vcmpleps %xmm0, %xmm2, %xmm0
; SNB-NEXT: vmulps %xmm1, %xmm3, %xmm1
; SNB-NEXT: vandps %xmm1, %xmm0, %xmm0 ; SNB-NEXT: vandps %xmm1, %xmm0, %xmm0
; SNB-NEXT: retq ; SNB-NEXT: retq
; ;
; BDW-LABEL: v4f32_no_daz: ; BDW-LABEL: v4f32_no_daz:
; BDW: # %bb.0: ; BDW: # %bb.0:
; BDW-NEXT: vrsqrtps %xmm0, %xmm1 ; BDW-NEXT: vrsqrtps %xmm0, %xmm1
; BDW-NEXT: vmulps %xmm1, %xmm0, %xmm2 ; BDW-NEXT: vmulps %xmm1, %xmm0, %xmm2
; BDW-NEXT: vbroadcastss {{.*#+}} xmm3 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0] ; BDW-NEXT: vbroadcastss {{.*#+}} xmm3 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0]
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; SKL-NEXT: retq ; SKL-NEXT: retq
%call = tail call fast <4 x float> @llvm.sqrt.v4f32(<4 x float> %f) #2 %call = tail call fast <4 x float> @llvm.sqrt.v4f32(<4 x float> %f) #2
ret <4 x float> %call ret <4 x float> %call
} }
define <8 x float> @v8f32_no_daz(<8 x float> %f) #0 { define <8 x float> @v8f32_no_daz(<8 x float> %f) #0 {
; NHM-LABEL: v8f32_no_daz: ; NHM-LABEL: v8f32_no_daz:
; NHM: # %bb.0: ; NHM: # %bb.0:
; NHM-NEXT: movaps %xmm0, %xmm2 ; NHM-NEXT: movaps {{.*#+}} xmm6 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38]
; NHM-NEXT: movaps {{.*#+}} xmm9 = [NaN,NaN,NaN,NaN]
; NHM-NEXT: rsqrtps %xmm0, %xmm3 ; NHM-NEXT: rsqrtps %xmm0, %xmm3
; NHM-NEXT: mulps %xmm3, %xmm0 ; NHM-NEXT: rsqrtps %xmm1, %xmm8
; NHM-NEXT: movaps %xmm0, %xmm2
; NHM-NEXT: movaps {{.*#+}} xmm4 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1] ; NHM-NEXT: movaps {{.*#+}} xmm4 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
; NHM-NEXT: movaps %xmm0, %xmm5 ; NHM-NEXT: movaps {{.*#+}} xmm10 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0]
; NHM-NEXT: mulps %xmm4, %xmm5
; NHM-NEXT: mulps %xmm3, %xmm0 ; NHM-NEXT: mulps %xmm3, %xmm0
; NHM-NEXT: movaps {{.*#+}} xmm3 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0] ; NHM-NEXT: andps %xmm9, %xmm2
; NHM-NEXT: addps %xmm3, %xmm0
; NHM-NEXT: mulps %xmm5, %xmm0
; NHM-NEXT: movaps {{.*#+}} xmm5 = [NaN,NaN,NaN,NaN]
; NHM-NEXT: andps %xmm5, %xmm2
; NHM-NEXT: movaps {{.*#+}} xmm6 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38]
; NHM-NEXT: movaps %xmm6, %xmm7 ; NHM-NEXT: movaps %xmm6, %xmm7
; NHM-NEXT: cmpleps %xmm2, %xmm7 ; NHM-NEXT: cmpleps %xmm2, %xmm7
; NHM-NEXT: andps %xmm7, %xmm0
; NHM-NEXT: rsqrtps %xmm1, %xmm7
; NHM-NEXT: movaps %xmm1, %xmm2 ; NHM-NEXT: movaps %xmm1, %xmm2
; NHM-NEXT: mulps %xmm7, %xmm2 ; NHM-NEXT: andps %xmm9, %xmm1
; NHM-NEXT: mulps %xmm8, %xmm2
; NHM-NEXT: cmpleps %xmm1, %xmm6
; NHM-NEXT: movaps %xmm0, %xmm5
; NHM-NEXT: mulps %xmm3, %xmm0
; NHM-NEXT: mulps %xmm4, %xmm5
; NHM-NEXT: mulps %xmm2, %xmm4 ; NHM-NEXT: mulps %xmm2, %xmm4
; NHM-NEXT: mulps %xmm7, %xmm2 ; NHM-NEXT: mulps %xmm8, %xmm2
; NHM-NEXT: addps %xmm3, %xmm2 ; NHM-NEXT: addps %xmm10, %xmm0
; NHM-NEXT: addps %xmm10, %xmm2
; NHM-NEXT: mulps %xmm5, %xmm0
; NHM-NEXT: mulps %xmm4, %xmm2 ; NHM-NEXT: mulps %xmm4, %xmm2
; NHM-NEXT: andps %xmm5, %xmm1 ; NHM-NEXT: andps %xmm7, %xmm0
; NHM-NEXT: cmpleps %xmm1, %xmm6
; NHM-NEXT: andps %xmm6, %xmm2 ; NHM-NEXT: andps %xmm6, %xmm2
; NHM-NEXT: movaps %xmm2, %xmm1 ; NHM-NEXT: movaps %xmm2, %xmm1
; NHM-NEXT: retq ; NHM-NEXT: retq
; ;
; SNB-LABEL: v8f32_no_daz: ; SNB-LABEL: v8f32_no_daz:
; SNB: # %bb.0: ; SNB: # %bb.0:
; SNB-NEXT: vrsqrtps %ymm0, %ymm1 ; SNB-NEXT: vrsqrtps %ymm0, %ymm1
; SNB-NEXT: vmulps %ymm1, %ymm0, %ymm2 ; SNB-NEXT: vmulps %ymm1, %ymm0, %ymm2
; SNB-NEXT: vmulps {{.*}}(%rip), %ymm2, %ymm3 ; SNB-NEXT: vmulps {{.*}}(%rip), %ymm2, %ymm3
; SNB-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
; SNB-NEXT: vmulps %ymm1, %ymm2, %ymm1 ; SNB-NEXT: vmulps %ymm1, %ymm2, %ymm1
; SNB-NEXT: vaddps {{.*}}(%rip), %ymm1, %ymm1 ; SNB-NEXT: vaddps {{.*}}(%rip), %ymm1, %ymm1
; SNB-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
; SNB-NEXT: vmulps %ymm1, %ymm3, %ymm1
; SNB-NEXT: vmovaps {{.*#+}} ymm2 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38] ; SNB-NEXT: vmovaps {{.*#+}} ymm2 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38]
; SNB-NEXT: vcmpleps %ymm0, %ymm2, %ymm0 ; SNB-NEXT: vcmpleps %ymm0, %ymm2, %ymm0
; SNB-NEXT: vmulps %ymm1, %ymm3, %ymm1
; SNB-NEXT: vandps %ymm1, %ymm0, %ymm0 ; SNB-NEXT: vandps %ymm1, %ymm0, %ymm0
; SNB-NEXT: retq ; SNB-NEXT: retq
; ;
; BDW-LABEL: v8f32_no_daz: ; BDW-LABEL: v8f32_no_daz:
; BDW: # %bb.0: ; BDW: # %bb.0:
; BDW-NEXT: vrsqrtps %ymm0, %ymm1 ; BDW-NEXT: vrsqrtps %ymm0, %ymm1
; BDW-NEXT: vmulps %ymm1, %ymm0, %ymm2 ; BDW-NEXT: vmulps %ymm1, %ymm0, %ymm2
; BDW-NEXT: vbroadcastss {{.*#+}} ymm3 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0] ; BDW-NEXT: vbroadcastss {{.*#+}} ymm3 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0]
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; Repeat all tests with denorms-as-zero enabled. ; Repeat all tests with denorms-as-zero enabled.
define float @f32_daz(float %f) #1 { define float @f32_daz(float %f) #1 {
; NHM-LABEL: f32_daz: ; NHM-LABEL: f32_daz:
; NHM: # %bb.0: ; NHM: # %bb.0:
; NHM-NEXT: rsqrtss %xmm0, %xmm1 ; NHM-NEXT: rsqrtss %xmm0, %xmm1
; NHM-NEXT: movaps %xmm0, %xmm2 ; NHM-NEXT: movaps %xmm0, %xmm2
; NHM-NEXT: mulss %xmm1, %xmm2
; NHM-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero ; NHM-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
; NHM-NEXT: mulss %xmm1, %xmm2
; NHM-NEXT: mulss %xmm2, %xmm3 ; NHM-NEXT: mulss %xmm2, %xmm3
; NHM-NEXT: mulss %xmm1, %xmm2 ; NHM-NEXT: mulss %xmm1, %xmm2
; NHM-NEXT: addss {{.*}}(%rip), %xmm2 ; NHM-NEXT: addss {{.*}}(%rip), %xmm2
; NHM-NEXT: mulss %xmm3, %xmm2
; NHM-NEXT: xorps %xmm1, %xmm1 ; NHM-NEXT: xorps %xmm1, %xmm1
; NHM-NEXT: cmpeqss %xmm1, %xmm0 ; NHM-NEXT: cmpeqss %xmm1, %xmm0
; NHM-NEXT: mulss %xmm3, %xmm2
; NHM-NEXT: andnps %xmm2, %xmm0 ; NHM-NEXT: andnps %xmm2, %xmm0
; NHM-NEXT: retq ; NHM-NEXT: retq
; ;
; FAST-SCALAR-LABEL: f32_daz: ; FAST-SCALAR-LABEL: f32_daz:
; FAST-SCALAR: # %bb.0: ; FAST-SCALAR: # %bb.0:
; FAST-SCALAR-NEXT: vsqrtss %xmm0, %xmm0, %xmm0 ; FAST-SCALAR-NEXT: vsqrtss %xmm0, %xmm0, %xmm0
; FAST-SCALAR-NEXT: retq ; FAST-SCALAR-NEXT: retq
%call = tail call fast float @llvm.sqrt.f32(float %f) #2 %call = tail call fast float @llvm.sqrt.f32(float %f) #2
ret float %call ret float %call
} }
define <4 x float> @v4f32_daz(<4 x float> %f) #1 { define <4 x float> @v4f32_daz(<4 x float> %f) #1 {
; NHM-LABEL: v4f32_daz: ; NHM-LABEL: v4f32_daz:
; NHM: # %bb.0: ; NHM: # %bb.0:
; NHM-NEXT: rsqrtps %xmm0, %xmm1 ; NHM-NEXT: rsqrtps %xmm0, %xmm1
; NHM-NEXT: movaps %xmm0, %xmm2 ; NHM-NEXT: movaps %xmm0, %xmm2
; NHM-NEXT: mulps %xmm1, %xmm2
; NHM-NEXT: movaps {{.*#+}} xmm3 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1] ; NHM-NEXT: movaps {{.*#+}} xmm3 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
; NHM-NEXT: mulps %xmm1, %xmm2
; NHM-NEXT: mulps %xmm2, %xmm3 ; NHM-NEXT: mulps %xmm2, %xmm3
; NHM-NEXT: mulps %xmm1, %xmm2 ; NHM-NEXT: mulps %xmm1, %xmm2
; NHM-NEXT: addps {{.*}}(%rip), %xmm2 ; NHM-NEXT: addps {{.*}}(%rip), %xmm2
; NHM-NEXT: mulps %xmm3, %xmm2
; NHM-NEXT: xorps %xmm1, %xmm1 ; NHM-NEXT: xorps %xmm1, %xmm1
; NHM-NEXT: cmpneqps %xmm1, %xmm0 ; NHM-NEXT: cmpneqps %xmm1, %xmm0
; NHM-NEXT: mulps %xmm3, %xmm2
; NHM-NEXT: andps %xmm2, %xmm0 ; NHM-NEXT: andps %xmm2, %xmm0
; NHM-NEXT: retq ; NHM-NEXT: retq
; ;
; SNB-LABEL: v4f32_daz: ; SNB-LABEL: v4f32_daz:
; SNB: # %bb.0: ; SNB: # %bb.0:
; SNB-NEXT: vrsqrtps %xmm0, %xmm1 ; SNB-NEXT: vrsqrtps %xmm0, %xmm1
; SNB-NEXT: vmulps %xmm1, %xmm0, %xmm2 ; SNB-NEXT: vmulps %xmm1, %xmm0, %xmm2
; SNB-NEXT: vmulps {{.*}}(%rip), %xmm2, %xmm3 ; SNB-NEXT: vmulps {{.*}}(%rip), %xmm2, %xmm3
; SNB-NEXT: vmulps %xmm1, %xmm2, %xmm1 ; SNB-NEXT: vmulps %xmm1, %xmm2, %xmm1
; SNB-NEXT: vaddps {{.*}}(%rip), %xmm1, %xmm1 ; SNB-NEXT: vaddps {{.*}}(%rip), %xmm1, %xmm1
; SNB-NEXT: vmulps %xmm1, %xmm3, %xmm1
; SNB-NEXT: vxorps %xmm2, %xmm2, %xmm2 ; SNB-NEXT: vxorps %xmm2, %xmm2, %xmm2
; SNB-NEXT: vcmpneqps %xmm2, %xmm0, %xmm0 ; SNB-NEXT: vcmpneqps %xmm2, %xmm0, %xmm0
; SNB-NEXT: vmulps %xmm1, %xmm3, %xmm1
; SNB-NEXT: vandps %xmm1, %xmm0, %xmm0 ; SNB-NEXT: vandps %xmm1, %xmm0, %xmm0
; SNB-NEXT: retq ; SNB-NEXT: retq
; ;
; BDW-LABEL: v4f32_daz: ; BDW-LABEL: v4f32_daz:
; BDW: # %bb.0: ; BDW: # %bb.0:
; BDW-NEXT: vrsqrtps %xmm0, %xmm1 ; BDW-NEXT: vrsqrtps %xmm0, %xmm1
; BDW-NEXT: vmulps %xmm1, %xmm0, %xmm2 ; BDW-NEXT: vmulps %xmm1, %xmm0, %xmm2
; BDW-NEXT: vbroadcastss {{.*#+}} xmm3 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0] ; BDW-NEXT: vbroadcastss {{.*#+}} xmm3 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0]
Show All 13 Lines; SKL-NEXT: retq
%call = tail call fast <4 x float> @llvm.sqrt.v4f32(<4 x float> %f) #2 %call = tail call fast <4 x float> @llvm.sqrt.v4f32(<4 x float> %f) #2
ret <4 x float> %call ret <4 x float> %call
} }
define <8 x float> @v8f32_daz(<8 x float> %f) #1 { define <8 x float> @v8f32_daz(<8 x float> %f) #1 {
; NHM-LABEL: v8f32_daz: ; NHM-LABEL: v8f32_daz:
; NHM: # %bb.0: ; NHM: # %bb.0:
; NHM-NEXT: rsqrtps %xmm0, %xmm2 ; NHM-NEXT: rsqrtps %xmm0, %xmm2
; NHM-NEXT: rsqrtps %xmm1, %xmm7
; NHM-NEXT: movaps %xmm0, %xmm3 ; NHM-NEXT: movaps %xmm0, %xmm3
; NHM-NEXT: mulps %xmm2, %xmm3 ; NHM-NEXT: movaps %xmm1, %xmm6
; NHM-NEXT: movaps {{.*#+}} xmm4 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1] ; NHM-NEXT: movaps {{.*#+}} xmm4 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
; NHM-NEXT: movaps {{.*#+}} xmm8 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0]
; NHM-NEXT: mulps %xmm2, %xmm3
; NHM-NEXT: mulps %xmm7, %xmm6
; NHM-NEXT: movaps %xmm3, %xmm5 ; NHM-NEXT: movaps %xmm3, %xmm5
; NHM-NEXT: mulps %xmm4, %xmm5
; NHM-NEXT: mulps %xmm2, %xmm3 ; NHM-NEXT: mulps %xmm2, %xmm3
; NHM-NEXT: movaps {{.*#+}} xmm2 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0] ; NHM-NEXT: mulps %xmm4, %xmm5
; NHM-NEXT: addps %xmm2, %xmm3 ; NHM-NEXT: mulps %xmm6, %xmm4
; NHM-NEXT: mulps %xmm7, %xmm6
; NHM-NEXT: addps %xmm8, %xmm3
; NHM-NEXT: addps %xmm8, %xmm6
; NHM-NEXT: mulps %xmm5, %xmm3 ; NHM-NEXT: mulps %xmm5, %xmm3
; NHM-NEXT: xorps %xmm5, %xmm5 ; NHM-NEXT: xorps %xmm5, %xmm5
; NHM-NEXT: cmpneqps %xmm5, %xmm0 ; NHM-NEXT: cmpneqps %xmm5, %xmm0
; NHM-NEXT: andps %xmm3, %xmm0
; NHM-NEXT: rsqrtps %xmm1, %xmm3
; NHM-NEXT: movaps %xmm1, %xmm6
; NHM-NEXT: mulps %xmm3, %xmm6
; NHM-NEXT: mulps %xmm6, %xmm4
; NHM-NEXT: mulps %xmm3, %xmm6
; NHM-NEXT: addps %xmm2, %xmm6
; NHM-NEXT: mulps %xmm4, %xmm6
; NHM-NEXT: cmpneqps %xmm5, %xmm1 ; NHM-NEXT: cmpneqps %xmm5, %xmm1
; NHM-NEXT: mulps %xmm4, %xmm6
; NHM-NEXT: andps %xmm3, %xmm0
; NHM-NEXT: andps %xmm6, %xmm1 ; NHM-NEXT: andps %xmm6, %xmm1
; NHM-NEXT: retq ; NHM-NEXT: retq
; ;
; SNB-LABEL: v8f32_daz: ; SNB-LABEL: v8f32_daz:
; SNB: # %bb.0: ; SNB: # %bb.0:
; SNB-NEXT: vrsqrtps %ymm0, %ymm1 ; SNB-NEXT: vrsqrtps %ymm0, %ymm1
; SNB-NEXT: vmulps %ymm1, %ymm0, %ymm2 ; SNB-NEXT: vmulps %ymm1, %ymm0, %ymm2
; SNB-NEXT: vmulps {{.*}}(%rip), %ymm2, %ymm3 ; SNB-NEXT: vmulps {{.*}}(%rip), %ymm2, %ymm3
; SNB-NEXT: vmulps %ymm1, %ymm2, %ymm1 ; SNB-NEXT: vmulps %ymm1, %ymm2, %ymm1
; SNB-NEXT: vaddps {{.*}}(%rip), %ymm1, %ymm1 ; SNB-NEXT: vaddps {{.*}}(%rip), %ymm1, %ymm1
; SNB-NEXT: vmulps %ymm1, %ymm3, %ymm1
; SNB-NEXT: vxorps %xmm2, %xmm2, %xmm2 ; SNB-NEXT: vxorps %xmm2, %xmm2, %xmm2
; SNB-NEXT: vcmpneqps %ymm2, %ymm0, %ymm0 ; SNB-NEXT: vcmpneqps %ymm2, %ymm0, %ymm0
; SNB-NEXT: vmulps %ymm1, %ymm3, %ymm1
; SNB-NEXT: vandps %ymm1, %ymm0, %ymm0 ; SNB-NEXT: vandps %ymm1, %ymm0, %ymm0
; SNB-NEXT: retq ; SNB-NEXT: retq
; ;
; BDW-LABEL: v8f32_daz: ; BDW-LABEL: v8f32_daz:
; BDW: # %bb.0: ; BDW: # %bb.0:
; BDW-NEXT: vrsqrtps %ymm0, %ymm1 ; BDW-NEXT: vrsqrtps %ymm0, %ymm1
; BDW-NEXT: vmulps %ymm1, %ymm0, %ymm2 ; BDW-NEXT: vmulps %ymm1, %ymm0, %ymm2
; BDW-NEXT: vbroadcastss {{.*#+}} ymm3 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0] ; BDW-NEXT: vbroadcastss {{.*#+}} ymm3 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0]
Show All 24 Lines

llvm/test/CodeGen/X86/sqrt-fastmath.ll

Show First 20 Lines • Show All 73 Lines • ▼ Show 20 Lines; AVX-NEXT: retq
ret float %call ret float %call
} }
define float @finite_f32_estimate_ieee_ninf(float %f) #1 { define float @finite_f32_estimate_ieee_ninf(float %f) #1 {
; SSE-LABEL: finite_f32_estimate_ieee_ninf: ; SSE-LABEL: finite_f32_estimate_ieee_ninf:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: rsqrtss %xmm0, %xmm1 ; SSE-NEXT: rsqrtss %xmm0, %xmm1
; SSE-NEXT: movaps %xmm0, %xmm2 ; SSE-NEXT: movaps %xmm0, %xmm2
; SSE-NEXT: mulss %xmm1, %xmm2
; SSE-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero ; SSE-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
; SSE-NEXT: andps {{.*}}(%rip), %xmm0
; SSE-NEXT: cmpltss {{.*}}(%rip), %xmm0
; SSE-NEXT: mulss %xmm1, %xmm2
; SSE-NEXT: mulss %xmm2, %xmm3 ; SSE-NEXT: mulss %xmm2, %xmm3
; SSE-NEXT: mulss %xmm1, %xmm2 ; SSE-NEXT: mulss %xmm1, %xmm2
; SSE-NEXT: addss {{.*}}(%rip), %xmm2 ; SSE-NEXT: addss {{.*}}(%rip), %xmm2
; SSE-NEXT: andps {{.*}}(%rip), %xmm0
; SSE-NEXT: mulss %xmm3, %xmm2 ; SSE-NEXT: mulss %xmm3, %xmm2
; SSE-NEXT: cmpltss {{.*}}(%rip), %xmm0
; SSE-NEXT: andnps %xmm2, %xmm0 ; SSE-NEXT: andnps %xmm2, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: finite_f32_estimate_ieee_ninf: ; AVX1-LABEL: finite_f32_estimate_ieee_ninf:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vrsqrtss %xmm0, %xmm0, %xmm1 ; AVX1-NEXT: vrsqrtss %xmm0, %xmm0, %xmm1
; AVX1-NEXT: vmulss %xmm1, %xmm0, %xmm2 ; AVX1-NEXT: vmulss %xmm1, %xmm0, %xmm2
; AVX1-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vcmpltss {{.*}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vmulss %xmm1, %xmm2, %xmm1 ; AVX1-NEXT: vmulss %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vaddss {{.*}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vmulss {{.*}}(%rip), %xmm2, %xmm2 ; AVX1-NEXT: vmulss {{.*}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0 ; AVX1-NEXT: vaddss {{.*}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vmulss %xmm1, %xmm2, %xmm1 ; AVX1-NEXT: vmulss %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vcmpltss {{.*}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vandnps %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vandnps %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX512-LABEL: finite_f32_estimate_ieee_ninf: ; AVX512-LABEL: finite_f32_estimate_ieee_ninf:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vrsqrtss %xmm0, %xmm0, %xmm1 ; AVX512-NEXT: vrsqrtss %xmm0, %xmm0, %xmm1
; AVX512-NEXT: vbroadcastss {{.*#+}} xmm3 = [NaN,NaN,NaN,NaN]
; AVX512-NEXT: vmulss %xmm1, %xmm0, %xmm2 ; AVX512-NEXT: vmulss %xmm1, %xmm0, %xmm2
; AVX512-NEXT: vandps %xmm3, %xmm0, %xmm0
; AVX512-NEXT: vcmpltss {{.*}}(%rip), %xmm0, %k1
; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX512-NEXT: vfmadd213ss {{.*#+}} xmm1 = (xmm2 * xmm1) + mem ; AVX512-NEXT: vfmadd213ss {{.*#+}} xmm1 = (xmm2 * xmm1) + mem
; AVX512-NEXT: vmulss {{.*}}(%rip), %xmm2, %xmm2 ; AVX512-NEXT: vmulss {{.*}}(%rip), %xmm2, %xmm2
; AVX512-NEXT: vmulss %xmm1, %xmm2, %xmm1 ; AVX512-NEXT: vmulss %xmm1, %xmm2, %xmm1
; AVX512-NEXT: vbroadcastss {{.*#+}} xmm2 = [NaN,NaN,NaN,NaN]
; AVX512-NEXT: vandps %xmm2, %xmm0, %xmm0
; AVX512-NEXT: vcmpltss {{.*}}(%rip), %xmm0, %k1
; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX512-NEXT: vmovss %xmm0, %xmm1, %xmm1 {%k1} ; AVX512-NEXT: vmovss %xmm0, %xmm1, %xmm1 {%k1}
; AVX512-NEXT: vmovaps %xmm1, %xmm0 ; AVX512-NEXT: vmovaps %xmm1, %xmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%call = tail call ninf float @__sqrtf_finite(float %f) #2 %call = tail call ninf float @__sqrtf_finite(float %f) #2
ret float %call ret float %call
} }
define float @finite_f32_estimate_daz(float %f) #4 { define float @finite_f32_estimate_daz(float %f) #4 {
Show All 10 Lines; AVX-NEXT: retq
ret float %call ret float %call
} }
define float @finite_f32_estimate_daz_ninf(float %f) #4 { define float @finite_f32_estimate_daz_ninf(float %f) #4 {
; SSE-LABEL: finite_f32_estimate_daz_ninf: ; SSE-LABEL: finite_f32_estimate_daz_ninf:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: rsqrtss %xmm0, %xmm1 ; SSE-NEXT: rsqrtss %xmm0, %xmm1
; SSE-NEXT: movaps %xmm0, %xmm2 ; SSE-NEXT: movaps %xmm0, %xmm2
; SSE-NEXT: mulss %xmm1, %xmm2
; SSE-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero ; SSE-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
; SSE-NEXT: mulss %xmm1, %xmm2
; SSE-NEXT: mulss %xmm2, %xmm3 ; SSE-NEXT: mulss %xmm2, %xmm3
; SSE-NEXT: mulss %xmm1, %xmm2 ; SSE-NEXT: mulss %xmm1, %xmm2
; SSE-NEXT: addss {{.*}}(%rip), %xmm2 ; SSE-NEXT: addss {{.*}}(%rip), %xmm2
; SSE-NEXT: mulss %xmm3, %xmm2
; SSE-NEXT: xorps %xmm1, %xmm1 ; SSE-NEXT: xorps %xmm1, %xmm1
; SSE-NEXT: cmpeqss %xmm1, %xmm0 ; SSE-NEXT: cmpeqss %xmm1, %xmm0
; SSE-NEXT: mulss %xmm3, %xmm2
; SSE-NEXT: andnps %xmm2, %xmm0 ; SSE-NEXT: andnps %xmm2, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: finite_f32_estimate_daz_ninf: ; AVX1-LABEL: finite_f32_estimate_daz_ninf:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vrsqrtss %xmm0, %xmm0, %xmm1 ; AVX1-NEXT: vrsqrtss %xmm0, %xmm0, %xmm1
; AVX1-NEXT: vmulss %xmm1, %xmm0, %xmm2 ; AVX1-NEXT: vmulss %xmm1, %xmm0, %xmm2
; AVX1-NEXT: vmulss %xmm1, %xmm2, %xmm1 ; AVX1-NEXT: vmulss %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vaddss {{.*}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vmulss {{.*}}(%rip), %xmm2, %xmm2 ; AVX1-NEXT: vmulss {{.*}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vaddss {{.*}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vmulss %xmm1, %xmm2, %xmm1 ; AVX1-NEXT: vmulss %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vxorps %xmm2, %xmm2, %xmm2 ; AVX1-NEXT: vxorps %xmm2, %xmm2, %xmm2
; AVX1-NEXT: vcmpeqss %xmm2, %xmm0, %xmm0 ; AVX1-NEXT: vcmpeqss %xmm2, %xmm0, %xmm0
; AVX1-NEXT: vandnps %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vandnps %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX512-LABEL: finite_f32_estimate_daz_ninf: ; AVX512-LABEL: finite_f32_estimate_daz_ninf:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines; AVX-NEXT: retq
ret float %call ret float %call
} }
define float @sqrtf_check_denorms_ninf(float %x) #3 { define float @sqrtf_check_denorms_ninf(float %x) #3 {
; SSE-LABEL: sqrtf_check_denorms_ninf: ; SSE-LABEL: sqrtf_check_denorms_ninf:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: rsqrtss %xmm0, %xmm1 ; SSE-NEXT: rsqrtss %xmm0, %xmm1
; SSE-NEXT: movaps %xmm0, %xmm2 ; SSE-NEXT: movaps %xmm0, %xmm2
; SSE-NEXT: mulss %xmm1, %xmm2
; SSE-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero ; SSE-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
; SSE-NEXT: andps {{.*}}(%rip), %xmm0
; SSE-NEXT: cmpltss {{.*}}(%rip), %xmm0
; SSE-NEXT: mulss %xmm1, %xmm2
; SSE-NEXT: mulss %xmm2, %xmm3 ; SSE-NEXT: mulss %xmm2, %xmm3
; SSE-NEXT: mulss %xmm1, %xmm2 ; SSE-NEXT: mulss %xmm1, %xmm2
; SSE-NEXT: addss {{.*}}(%rip), %xmm2 ; SSE-NEXT: addss {{.*}}(%rip), %xmm2
; SSE-NEXT: andps {{.*}}(%rip), %xmm0
; SSE-NEXT: mulss %xmm3, %xmm2 ; SSE-NEXT: mulss %xmm3, %xmm2
; SSE-NEXT: cmpltss {{.*}}(%rip), %xmm0
; SSE-NEXT: andnps %xmm2, %xmm0 ; SSE-NEXT: andnps %xmm2, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: sqrtf_check_denorms_ninf: ; AVX1-LABEL: sqrtf_check_denorms_ninf:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vrsqrtss %xmm0, %xmm0, %xmm1 ; AVX1-NEXT: vrsqrtss %xmm0, %xmm0, %xmm1
; AVX1-NEXT: vmulss %xmm1, %xmm0, %xmm2 ; AVX1-NEXT: vmulss %xmm1, %xmm0, %xmm2
; AVX1-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vcmpltss {{.*}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vmulss %xmm1, %xmm2, %xmm1 ; AVX1-NEXT: vmulss %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vaddss {{.*}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vmulss {{.*}}(%rip), %xmm2, %xmm2 ; AVX1-NEXT: vmulss {{.*}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0 ; AVX1-NEXT: vaddss {{.*}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vmulss %xmm1, %xmm2, %xmm1 ; AVX1-NEXT: vmulss %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vcmpltss {{.*}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vandnps %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vandnps %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX512-LABEL: sqrtf_check_denorms_ninf: ; AVX512-LABEL: sqrtf_check_denorms_ninf:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vrsqrtss %xmm0, %xmm0, %xmm1 ; AVX512-NEXT: vrsqrtss %xmm0, %xmm0, %xmm1
; AVX512-NEXT: vbroadcastss {{.*#+}} xmm3 = [NaN,NaN,NaN,NaN]
; AVX512-NEXT: vmulss %xmm1, %xmm0, %xmm2 ; AVX512-NEXT: vmulss %xmm1, %xmm0, %xmm2
; AVX512-NEXT: vandps %xmm3, %xmm0, %xmm0
; AVX512-NEXT: vcmpltss {{.*}}(%rip), %xmm0, %k1
; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX512-NEXT: vfmadd213ss {{.*#+}} xmm1 = (xmm2 * xmm1) + mem ; AVX512-NEXT: vfmadd213ss {{.*#+}} xmm1 = (xmm2 * xmm1) + mem
; AVX512-NEXT: vmulss {{.*}}(%rip), %xmm2, %xmm2 ; AVX512-NEXT: vmulss {{.*}}(%rip), %xmm2, %xmm2
; AVX512-NEXT: vmulss %xmm1, %xmm2, %xmm1 ; AVX512-NEXT: vmulss %xmm1, %xmm2, %xmm1
; AVX512-NEXT: vbroadcastss {{.*#+}} xmm2 = [NaN,NaN,NaN,NaN]
; AVX512-NEXT: vandps %xmm2, %xmm0, %xmm0
; AVX512-NEXT: vcmpltss {{.*}}(%rip), %xmm0, %k1
; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX512-NEXT: vmovss %xmm0, %xmm1, %xmm1 {%k1} ; AVX512-NEXT: vmovss %xmm0, %xmm1, %xmm1 {%k1}
; AVX512-NEXT: vmovaps %xmm1, %xmm0 ; AVX512-NEXT: vmovaps %xmm1, %xmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%call = tail call ninf float @__sqrtf_finite(float %x) #2 %call = tail call ninf float @__sqrtf_finite(float %x) #2
ret float %call ret float %call
} }
define <4 x float> @sqrt_v4f32_check_denorms(<4 x float> %x) #3 { define <4 x float> @sqrt_v4f32_check_denorms(<4 x float> %x) #3 {
Show All 10 Lines; AVX-NEXT: retq
ret <4 x float> %call ret <4 x float> %call
} }
define <4 x float> @sqrt_v4f32_check_denorms_ninf(<4 x float> %x) #3 { define <4 x float> @sqrt_v4f32_check_denorms_ninf(<4 x float> %x) #3 {
; SSE-LABEL: sqrt_v4f32_check_denorms_ninf: ; SSE-LABEL: sqrt_v4f32_check_denorms_ninf:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: rsqrtps %xmm0, %xmm2 ; SSE-NEXT: rsqrtps %xmm0, %xmm2
; SSE-NEXT: movaps %xmm0, %xmm1 ; SSE-NEXT: movaps %xmm0, %xmm1
; SSE-NEXT: mulps %xmm2, %xmm1
; SSE-NEXT: movaps {{.*#+}} xmm3 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1] ; SSE-NEXT: movaps {{.*#+}} xmm3 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
; SSE-NEXT: andps {{.*}}(%rip), %xmm0
; SSE-NEXT: mulps %xmm2, %xmm1
; SSE-NEXT: mulps %xmm1, %xmm3 ; SSE-NEXT: mulps %xmm1, %xmm3
; SSE-NEXT: mulps %xmm2, %xmm1 ; SSE-NEXT: mulps %xmm2, %xmm1
; SSE-NEXT: addps {{.*}}(%rip), %xmm1 ; SSE-NEXT: addps {{.*}}(%rip), %xmm1
; SSE-NEXT: andps {{.*}}(%rip), %xmm0
; SSE-NEXT: mulps %xmm3, %xmm1
; SSE-NEXT: movaps {{.*#+}} xmm2 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38] ; SSE-NEXT: movaps {{.*#+}} xmm2 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38]
; SSE-NEXT: cmpleps %xmm0, %xmm2 ; SSE-NEXT: cmpleps %xmm0, %xmm2
; SSE-NEXT: mulps %xmm3, %xmm1
; SSE-NEXT: andps %xmm2, %xmm1 ; SSE-NEXT: andps %xmm2, %xmm1
; SSE-NEXT: movaps %xmm1, %xmm0 ; SSE-NEXT: movaps %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: sqrt_v4f32_check_denorms_ninf: ; AVX1-LABEL: sqrt_v4f32_check_denorms_ninf:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vrsqrtps %xmm0, %xmm1 ; AVX1-NEXT: vrsqrtps %xmm0, %xmm1
; AVX1-NEXT: vmulps %xmm1, %xmm0, %xmm2 ; AVX1-NEXT: vmulps %xmm1, %xmm0, %xmm2
; AVX1-NEXT: vmulps {{.*}}(%rip), %xmm2, %xmm3 ; AVX1-NEXT: vmulps {{.*}}(%rip), %xmm2, %xmm3
; AVX1-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vmulps %xmm1, %xmm2, %xmm1 ; AVX1-NEXT: vmulps %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vaddps {{.*}}(%rip), %xmm1, %xmm1 ; AVX1-NEXT: vaddps {{.*}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vmulps %xmm1, %xmm3, %xmm1
; AVX1-NEXT: vmovaps {{.*#+}} xmm2 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38] ; AVX1-NEXT: vmovaps {{.*#+}} xmm2 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38]
; AVX1-NEXT: vcmpleps %xmm0, %xmm2, %xmm0 ; AVX1-NEXT: vcmpleps %xmm0, %xmm2, %xmm0
; AVX1-NEXT: vmulps %xmm1, %xmm3, %xmm1
; AVX1-NEXT: vandps %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vandps %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX512-LABEL: sqrt_v4f32_check_denorms_ninf: ; AVX512-LABEL: sqrt_v4f32_check_denorms_ninf:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vrsqrtps %xmm0, %xmm1 ; AVX512-NEXT: vrsqrtps %xmm0, %xmm1
; AVX512-NEXT: vmulps %xmm1, %xmm0, %xmm2
; AVX512-NEXT: vbroadcastss {{.*#+}} xmm3 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0] ; AVX512-NEXT: vbroadcastss {{.*#+}} xmm3 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0]
; AVX512-NEXT: vbroadcastss {{.*#+}} xmm4 = [NaN,NaN,NaN,NaN]
; AVX512-NEXT: vmulps %xmm1, %xmm0, %xmm2
; AVX512-NEXT: vandps %xmm4, %xmm0, %xmm0
; AVX512-NEXT: vfmadd231ps {{.*#+}} xmm3 = (xmm2 * xmm1) + xmm3 ; AVX512-NEXT: vfmadd231ps {{.*#+}} xmm3 = (xmm2 * xmm1) + xmm3
; AVX512-NEXT: vbroadcastss {{.*#+}} xmm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1] ; AVX512-NEXT: vbroadcastss {{.*#+}} xmm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
; AVX512-NEXT: vmulps %xmm1, %xmm2, %xmm1 ; AVX512-NEXT: vmulps %xmm1, %xmm2, %xmm1
; AVX512-NEXT: vmulps %xmm3, %xmm1, %xmm1 ; AVX512-NEXT: vmulps %xmm3, %xmm1, %xmm1
; AVX512-NEXT: vbroadcastss {{.*#+}} xmm2 = [NaN,NaN,NaN,NaN] ; AVX512-NEXT: vbroadcastss {{.*#+}} xmm3 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38]
; AVX512-NEXT: vandps %xmm2, %xmm0, %xmm0 ; AVX512-NEXT: vcmpleps %xmm0, %xmm3, %xmm0
; AVX512-NEXT: vbroadcastss {{.*#+}} xmm2 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38]
; AVX512-NEXT: vcmpleps %xmm0, %xmm2, %xmm0
; AVX512-NEXT: vandps %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vandps %xmm1, %xmm0, %xmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%call = tail call ninf <4 x float> @llvm.sqrt.v4f32(<4 x float> %x) #2 %call = tail call ninf <4 x float> @llvm.sqrt.v4f32(<4 x float> %x) #2
ret <4 x float> %call ret <4 x float> %call
} }
define float @f32_no_estimate(float %x) #0 { define float @f32_no_estimate(float %x) #0 {
; SSE-LABEL: f32_no_estimate: ; SSE-LABEL: f32_no_estimate:
Show All 15 Lines
} }
define float @f32_estimate(float %x) #1 { define float @f32_estimate(float %x) #1 {
; SSE-LABEL: f32_estimate: ; SSE-LABEL: f32_estimate:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: rsqrtss %xmm0, %xmm1 ; SSE-NEXT: rsqrtss %xmm0, %xmm1
; SSE-NEXT: mulss %xmm1, %xmm0 ; SSE-NEXT: mulss %xmm1, %xmm0
; SSE-NEXT: mulss %xmm1, %xmm0 ; SSE-NEXT: mulss %xmm1, %xmm0
; SSE-NEXT: addss {{.*}}(%rip), %xmm0
; SSE-NEXT: mulss {{.*}}(%rip), %xmm1 ; SSE-NEXT: mulss {{.*}}(%rip), %xmm1
; SSE-NEXT: addss {{.*}}(%rip), %xmm0
; SSE-NEXT: mulss %xmm1, %xmm0 ; SSE-NEXT: mulss %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: f32_estimate: ; AVX1-LABEL: f32_estimate:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vrsqrtss %xmm0, %xmm0, %xmm1 ; AVX1-NEXT: vrsqrtss %xmm0, %xmm0, %xmm1
; AVX1-NEXT: vmulss %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vmulss %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vmulss %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vmulss %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vaddss {{.*}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vmulss {{.*}}(%rip), %xmm1, %xmm1 ; AVX1-NEXT: vmulss {{.*}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vaddss {{.*}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vmulss %xmm0, %xmm1, %xmm0 ; AVX1-NEXT: vmulss %xmm0, %xmm1, %xmm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX512-LABEL: f32_estimate: ; AVX512-LABEL: f32_estimate:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vrsqrtss %xmm0, %xmm0, %xmm1 ; AVX512-NEXT: vrsqrtss %xmm0, %xmm0, %xmm1
; AVX512-NEXT: vmulss %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vmulss %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vfmadd213ss {{.*#+}} xmm0 = (xmm1 * xmm0) + mem ; AVX512-NEXT: vfmadd213ss {{.*#+}} xmm0 = (xmm1 * xmm0) + mem
Show All 32 Lines
} }
define <4 x float> @v4f32_estimate(<4 x float> %x) #1 { define <4 x float> @v4f32_estimate(<4 x float> %x) #1 {
; SSE-LABEL: v4f32_estimate: ; SSE-LABEL: v4f32_estimate:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: rsqrtps %xmm0, %xmm1 ; SSE-NEXT: rsqrtps %xmm0, %xmm1
; SSE-NEXT: mulps %xmm1, %xmm0 ; SSE-NEXT: mulps %xmm1, %xmm0
; SSE-NEXT: mulps %xmm1, %xmm0 ; SSE-NEXT: mulps %xmm1, %xmm0
; SSE-NEXT: addps {{.*}}(%rip), %xmm0
; SSE-NEXT: mulps {{.*}}(%rip), %xmm1 ; SSE-NEXT: mulps {{.*}}(%rip), %xmm1
; SSE-NEXT: addps {{.*}}(%rip), %xmm0
; SSE-NEXT: mulps %xmm1, %xmm0 ; SSE-NEXT: mulps %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: v4f32_estimate: ; AVX1-LABEL: v4f32_estimate:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vrsqrtps %xmm0, %xmm1 ; AVX1-NEXT: vrsqrtps %xmm0, %xmm1
; AVX1-NEXT: vmulps %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vmulps %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vmulps %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vmulps %xmm1, %xmm0, %xmm0
; AVX1-NEXT: vaddps {{.*}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vmulps {{.*}}(%rip), %xmm1, %xmm1 ; AVX1-NEXT: vmulps {{.*}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vaddps {{.*}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vmulps %xmm0, %xmm1, %xmm0 ; AVX1-NEXT: vmulps %xmm0, %xmm1, %xmm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX512-LABEL: v4f32_estimate: ; AVX512-LABEL: v4f32_estimate:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vrsqrtps %xmm0, %xmm1 ; AVX512-NEXT: vrsqrtps %xmm0, %xmm1
; AVX512-NEXT: vmulps %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vbroadcastss {{.*#+}} xmm2 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0] ; AVX512-NEXT: vbroadcastss {{.*#+}} xmm2 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0]
; AVX512-NEXT: vmulps %xmm1, %xmm0, %xmm0
; AVX512-NEXT: vfmadd231ps {{.*#+}} xmm2 = (xmm1 * xmm0) + xmm2 ; AVX512-NEXT: vfmadd231ps {{.*#+}} xmm2 = (xmm1 * xmm0) + xmm2
; AVX512-NEXT: vbroadcastss {{.*#+}} xmm0 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1] ; AVX512-NEXT: vbroadcastss {{.*#+}} xmm0 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
; AVX512-NEXT: vmulps %xmm0, %xmm1, %xmm0 ; AVX512-NEXT: vmulps %xmm0, %xmm1, %xmm0
; AVX512-NEXT: vmulps %xmm2, %xmm0, %xmm0 ; AVX512-NEXT: vmulps %xmm2, %xmm0, %xmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%sqrt = tail call <4 x float> @llvm.sqrt.v4f32(<4 x float> %x) %sqrt = tail call <4 x float> @llvm.sqrt.v4f32(<4 x float> %x)
%div = fdiv fast <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, %sqrt %div = fdiv fast <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, %sqrt
ret <4 x float> %div ret <4 x float> %div
Show All 27 Lines; AVX512-NEXT: retq
%div = fdiv fast <8 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>, %sqrt %div = fdiv fast <8 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>, %sqrt
ret <8 x float> %div ret <8 x float> %div
} }
define <8 x float> @v8f32_estimate(<8 x float> %x) #1 { define <8 x float> @v8f32_estimate(<8 x float> %x) #1 {
; SSE-LABEL: v8f32_estimate: ; SSE-LABEL: v8f32_estimate:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: rsqrtps %xmm0, %xmm2 ; SSE-NEXT: rsqrtps %xmm0, %xmm2
; SSE-NEXT: rsqrtps %xmm1, %xmm5
; SSE-NEXT: movaps {{.*#+}} xmm3 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1] ; SSE-NEXT: movaps {{.*#+}} xmm3 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
; SSE-NEXT: movaps {{.*#+}} xmm4 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0]
; SSE-NEXT: mulps %xmm2, %xmm0 ; SSE-NEXT: mulps %xmm2, %xmm0
; SSE-NEXT: mulps %xmm5, %xmm1
; SSE-NEXT: mulps %xmm2, %xmm0 ; SSE-NEXT: mulps %xmm2, %xmm0
; SSE-NEXT: mulps %xmm5, %xmm1
; SSE-NEXT: mulps %xmm3, %xmm2 ; SSE-NEXT: mulps %xmm3, %xmm2
; SSE-NEXT: movaps {{.*#+}} xmm4 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0] ; SSE-NEXT: mulps %xmm5, %xmm3
; SSE-NEXT: addps %xmm4, %xmm0 ; SSE-NEXT: addps %xmm4, %xmm0
; SSE-NEXT: mulps %xmm2, %xmm0
; SSE-NEXT: rsqrtps %xmm1, %xmm2
; SSE-NEXT: mulps %xmm2, %xmm3
; SSE-NEXT: mulps %xmm2, %xmm1
; SSE-NEXT: mulps %xmm2, %xmm1
; SSE-NEXT: addps %xmm4, %xmm1 ; SSE-NEXT: addps %xmm4, %xmm1
; SSE-NEXT: mulps %xmm2, %xmm0
; SSE-NEXT: mulps %xmm3, %xmm1 ; SSE-NEXT: mulps %xmm3, %xmm1
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: v8f32_estimate: ; AVX1-LABEL: v8f32_estimate:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vrsqrtps %ymm0, %ymm1 ; AVX1-NEXT: vrsqrtps %ymm0, %ymm1
; AVX1-NEXT: vmulps %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: vmulps %ymm1, %ymm0, %ymm0
; AVX1-NEXT: vmulps %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: vmulps %ymm1, %ymm0, %ymm0
; AVX1-NEXT: vaddps {{.*}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: vmulps {{.*}}(%rip), %ymm1, %ymm1 ; AVX1-NEXT: vmulps {{.*}}(%rip), %ymm1, %ymm1
; AVX1-NEXT: vaddps {{.*}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: vmulps %ymm0, %ymm1, %ymm0 ; AVX1-NEXT: vmulps %ymm0, %ymm1, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX512-LABEL: v8f32_estimate: ; AVX512-LABEL: v8f32_estimate:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vrsqrtps %ymm0, %ymm1 ; AVX512-NEXT: vrsqrtps %ymm0, %ymm1
; AVX512-NEXT: vmulps %ymm1, %ymm0, %ymm0
; AVX512-NEXT: vbroadcastss {{.*#+}} ymm2 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0] ; AVX512-NEXT: vbroadcastss {{.*#+}} ymm2 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0]
; AVX512-NEXT: vmulps %ymm1, %ymm0, %ymm0
; AVX512-NEXT: vfmadd231ps {{.*#+}} ymm2 = (ymm1 * ymm0) + ymm2 ; AVX512-NEXT: vfmadd231ps {{.*#+}} ymm2 = (ymm1 * ymm0) + ymm2
; AVX512-NEXT: vbroadcastss {{.*#+}} ymm0 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1] ; AVX512-NEXT: vbroadcastss {{.*#+}} ymm0 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
; AVX512-NEXT: vmulps %ymm0, %ymm1, %ymm0 ; AVX512-NEXT: vmulps %ymm0, %ymm1, %ymm0
; AVX512-NEXT: vmulps %ymm2, %ymm0, %ymm0 ; AVX512-NEXT: vmulps %ymm2, %ymm0, %ymm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%sqrt = tail call <8 x float> @llvm.sqrt.v8f32(<8 x float> %x) %sqrt = tail call <8 x float> @llvm.sqrt.v8f32(<8 x float> %x)
%div = fdiv fast <8 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>, %sqrt %div = fdiv fast <8 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>, %sqrt
ret <8 x float> %div ret <8 x float> %div
} }
define <16 x float> @v16f32_no_estimate(<16 x float> %x) #0 { define <16 x float> @v16f32_no_estimate(<16 x float> %x) #0 {
; SSE-LABEL: v16f32_no_estimate: ; SSE-LABEL: v16f32_no_estimate:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: sqrtps %xmm3, %xmm4
; SSE-NEXT: sqrtps %xmm2, %xmm5 ; SSE-NEXT: sqrtps %xmm2, %xmm5
; SSE-NEXT: sqrtps %xmm1, %xmm2 ; SSE-NEXT: sqrtps %xmm1, %xmm2
; SSE-NEXT: sqrtps %xmm0, %xmm1 ; SSE-NEXT: sqrtps %xmm0, %xmm1
; SSE-NEXT: sqrtps %xmm3, %xmm4
; SSE-NEXT: movaps {{.*#+}} xmm3 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0] ; SSE-NEXT: movaps {{.*#+}} xmm3 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0]
; SSE-NEXT: movaps %xmm3, %xmm0 ; SSE-NEXT: movaps %xmm3, %xmm0
; SSE-NEXT: divps %xmm1, %xmm0 ; SSE-NEXT: divps %xmm1, %xmm0
; SSE-NEXT: movaps %xmm3, %xmm1 ; SSE-NEXT: movaps %xmm3, %xmm1
; SSE-NEXT: divps %xmm2, %xmm1 ; SSE-NEXT: divps %xmm2, %xmm1
; SSE-NEXT: movaps %xmm3, %xmm2 ; SSE-NEXT: movaps %xmm3, %xmm2
; SSE-NEXT: divps %xmm5, %xmm2
; SSE-NEXT: divps %xmm4, %xmm3 ; SSE-NEXT: divps %xmm4, %xmm3
; SSE-NEXT: divps %xmm5, %xmm2
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: v16f32_no_estimate: ; AVX1-LABEL: v16f32_no_estimate:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vsqrtps %ymm1, %ymm1 ; AVX1-NEXT: vsqrtps %ymm1, %ymm1
; AVX1-NEXT: vsqrtps %ymm0, %ymm0 ; AVX1-NEXT: vsqrtps %ymm0, %ymm0
; AVX1-NEXT: vmovaps {{.*#+}} ymm2 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0] ; AVX1-NEXT: vmovaps {{.*#+}} ymm2 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]
; AVX1-NEXT: vdivps %ymm0, %ymm2, %ymm0 ; AVX1-NEXT: vdivps %ymm0, %ymm2, %ymm0
Show All 9 Lines; AVX512-NEXT: retq
%sqrt = tail call <16 x float> @llvm.sqrt.v16f32(<16 x float> %x) %sqrt = tail call <16 x float> @llvm.sqrt.v16f32(<16 x float> %x)
%div = fdiv fast <16 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>, %sqrt %div = fdiv fast <16 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>, %sqrt
ret <16 x float> %div ret <16 x float> %div
} }
define <16 x float> @v16f32_estimate(<16 x float> %x) #1 { define <16 x float> @v16f32_estimate(<16 x float> %x) #1 {
; SSE-LABEL: v16f32_estimate: ; SSE-LABEL: v16f32_estimate:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: rsqrtps %xmm0, %xmm5 ; SSE-NEXT: rsqrtps %xmm1, %xmm7
; SSE-NEXT: movaps {{.*#+}} xmm4 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1] ; SSE-NEXT: movaps {{.*#+}} xmm4 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
; SSE-NEXT: movaps {{.*#+}} xmm9 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0]
; SSE-NEXT: rsqrtps %xmm0, %xmm5
; SSE-NEXT: rsqrtps %xmm2, %xmm8
; SSE-NEXT: mulps %xmm7, %xmm1
; SSE-NEXT: mulps %xmm5, %xmm0 ; SSE-NEXT: mulps %xmm5, %xmm0
; SSE-NEXT: mulps %xmm5, %xmm0 ; SSE-NEXT: mulps %xmm8, %xmm2
; SSE-NEXT: movaps %xmm5, %xmm6 ; SSE-NEXT: movaps %xmm5, %xmm6
; SSE-NEXT: mulps %xmm4, %xmm6 ; SSE-NEXT: mulps %xmm4, %xmm6
; SSE-NEXT: movaps {{.*#+}} xmm5 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0] ; SSE-NEXT: mulps %xmm7, %xmm1
; SSE-NEXT: addps %xmm5, %xmm0 ; SSE-NEXT: mulps %xmm4, %xmm7
; SSE-NEXT: mulps %xmm8, %xmm2
; SSE-NEXT: mulps %xmm5, %xmm0
; SSE-NEXT: mulps %xmm4, %xmm8
; SSE-NEXT: addps %xmm9, %xmm1
; SSE-NEXT: addps %xmm9, %xmm0
; SSE-NEXT: addps %xmm9, %xmm2
; SSE-NEXT: mulps %xmm7, %xmm1
; SSE-NEXT: rsqrtps %xmm3, %xmm7
; SSE-NEXT: mulps %xmm6, %xmm0 ; SSE-NEXT: mulps %xmm6, %xmm0
; SSE-NEXT: rsqrtps %xmm1, %xmm6 ; SSE-NEXT: mulps %xmm8, %xmm2
; SSE-NEXT: mulps %xmm6, %xmm1 ; SSE-NEXT: mulps %xmm7, %xmm3
; SSE-NEXT: mulps %xmm6, %xmm1 ; SSE-NEXT: mulps %xmm7, %xmm4
; SSE-NEXT: mulps %xmm4, %xmm6 ; SSE-NEXT: mulps %xmm7, %xmm3
; SSE-NEXT: addps %xmm5, %xmm1 ; SSE-NEXT: addps %xmm9, %xmm3
; SSE-NEXT: mulps %xmm6, %xmm1
; SSE-NEXT: rsqrtps %xmm2, %xmm6
; SSE-NEXT: mulps %xmm6, %xmm2
; SSE-NEXT: mulps %xmm6, %xmm2
; SSE-NEXT: mulps %xmm4, %xmm6
; SSE-NEXT: addps %xmm5, %xmm2
; SSE-NEXT: mulps %xmm6, %xmm2
; SSE-NEXT: rsqrtps %xmm3, %xmm6
; SSE-NEXT: mulps %xmm6, %xmm4
; SSE-NEXT: mulps %xmm6, %xmm3
; SSE-NEXT: mulps %xmm6, %xmm3
; SSE-NEXT: addps %xmm5, %xmm3
; SSE-NEXT: mulps %xmm4, %xmm3 ; SSE-NEXT: mulps %xmm4, %xmm3
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: v16f32_estimate: ; AVX1-LABEL: v16f32_estimate:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vrsqrtps %ymm0, %ymm2 ; AVX1-NEXT: vrsqrtps %ymm0, %ymm2
; AVX1-NEXT: vrsqrtps %ymm1, %ymm5
; AVX1-NEXT: vmovaps {{.*#+}} ymm3 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1] ; AVX1-NEXT: vmovaps {{.*#+}} ymm3 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
; AVX1-NEXT: vmulps %ymm3, %ymm2, %ymm4 ; AVX1-NEXT: vmovaps {{.*#+}} ymm6 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0]
; AVX1-NEXT: vmulps %ymm2, %ymm0, %ymm0 ; AVX1-NEXT: vmulps %ymm2, %ymm0, %ymm0
; AVX1-NEXT: vmulps %ymm5, %ymm1, %ymm1
; AVX1-NEXT: vmulps %ymm3, %ymm2, %ymm4
; AVX1-NEXT: vmulps %ymm3, %ymm5, %ymm3
; AVX1-NEXT: vmulps %ymm2, %ymm0, %ymm0 ; AVX1-NEXT: vmulps %ymm2, %ymm0, %ymm0
; AVX1-NEXT: vmovaps {{.*#+}} ymm2 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0] ; AVX1-NEXT: vmulps %ymm5, %ymm1, %ymm1
; AVX1-NEXT: vaddps %ymm2, %ymm0, %ymm0 ; AVX1-NEXT: vaddps %ymm6, %ymm0, %ymm0
; AVX1-NEXT: vaddps %ymm6, %ymm1, %ymm1
; AVX1-NEXT: vmulps %ymm0, %ymm4, %ymm0 ; AVX1-NEXT: vmulps %ymm0, %ymm4, %ymm0
; AVX1-NEXT: vrsqrtps %ymm1, %ymm4
; AVX1-NEXT: vmulps %ymm3, %ymm4, %ymm3
; AVX1-NEXT: vmulps %ymm4, %ymm1, %ymm1
; AVX1-NEXT: vmulps %ymm4, %ymm1, %ymm1
; AVX1-NEXT: vaddps %ymm2, %ymm1, %ymm1
; AVX1-NEXT: vmulps %ymm1, %ymm3, %ymm1 ; AVX1-NEXT: vmulps %ymm1, %ymm3, %ymm1
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX512-LABEL: v16f32_estimate: ; AVX512-LABEL: v16f32_estimate:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vrsqrt14ps %zmm0, %zmm1 ; AVX512-NEXT: vrsqrt14ps %zmm0, %zmm1
; AVX512-NEXT: vmulps %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: vmulps %zmm1, %zmm0, %zmm0
; AVX512-NEXT: vfmadd213ps {{.*#+}} zmm0 = (zmm1 * zmm0) + mem ; AVX512-NEXT: vfmadd213ps {{.*#+}} zmm0 = (zmm1 * zmm0) + mem
Show All 11 Lines
; SSE-LABEL: div_sqrt_fabs_f32: ; SSE-LABEL: div_sqrt_fabs_f32:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: mulss %xmm1, %xmm1 ; SSE-NEXT: mulss %xmm1, %xmm1
; SSE-NEXT: mulss %xmm2, %xmm1 ; SSE-NEXT: mulss %xmm2, %xmm1
; SSE-NEXT: xorps %xmm2, %xmm2 ; SSE-NEXT: xorps %xmm2, %xmm2
; SSE-NEXT: rsqrtss %xmm1, %xmm2 ; SSE-NEXT: rsqrtss %xmm1, %xmm2
; SSE-NEXT: mulss %xmm2, %xmm1 ; SSE-NEXT: mulss %xmm2, %xmm1
; SSE-NEXT: mulss %xmm2, %xmm1 ; SSE-NEXT: mulss %xmm2, %xmm1
; SSE-NEXT: addss {{.*}}(%rip), %xmm1
; SSE-NEXT: mulss {{.*}}(%rip), %xmm2 ; SSE-NEXT: mulss {{.*}}(%rip), %xmm2
; SSE-NEXT: addss {{.*}}(%rip), %xmm1
; SSE-NEXT: mulss %xmm0, %xmm2 ; SSE-NEXT: mulss %xmm0, %xmm2
; SSE-NEXT: mulss %xmm1, %xmm2 ; SSE-NEXT: mulss %xmm1, %xmm2
; SSE-NEXT: movaps %xmm2, %xmm0 ; SSE-NEXT: movaps %xmm2, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: div_sqrt_fabs_f32: ; AVX1-LABEL: div_sqrt_fabs_f32:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vmulss %xmm1, %xmm1, %xmm1 ; AVX1-NEXT: vmulss %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vmulss %xmm2, %xmm1, %xmm1 ; AVX1-NEXT: vmulss %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vrsqrtss %xmm1, %xmm1, %xmm2 ; AVX1-NEXT: vrsqrtss %xmm1, %xmm1, %xmm2
; AVX1-NEXT: vmulss %xmm2, %xmm1, %xmm1 ; AVX1-NEXT: vmulss %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vmulss %xmm2, %xmm1, %xmm1 ; AVX1-NEXT: vmulss %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vaddss {{.*}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vmulss {{.*}}(%rip), %xmm2, %xmm2 ; AVX1-NEXT: vmulss {{.*}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vaddss {{.*}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vmulss %xmm0, %xmm2, %xmm0 ; AVX1-NEXT: vmulss %xmm0, %xmm2, %xmm0
; AVX1-NEXT: vmulss %xmm0, %xmm1, %xmm0 ; AVX1-NEXT: vmulss %xmm0, %xmm1, %xmm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX512-LABEL: div_sqrt_fabs_f32: ; AVX512-LABEL: div_sqrt_fabs_f32:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vmulss %xmm1, %xmm1, %xmm1 ; AVX512-NEXT: vmulss %xmm1, %xmm1, %xmm1
; AVX512-NEXT: vmulss %xmm2, %xmm1, %xmm1 ; AVX512-NEXT: vmulss %xmm2, %xmm1, %xmm1
Show All 16 Lines
define <4 x float> @div_sqrt_fabs_v4f32(<4 x float> %x, <4 x float> %y, <4 x float> %z) { define <4 x float> @div_sqrt_fabs_v4f32(<4 x float> %x, <4 x float> %y, <4 x float> %z) {
; SSE-LABEL: div_sqrt_fabs_v4f32: ; SSE-LABEL: div_sqrt_fabs_v4f32:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: mulps %xmm1, %xmm1 ; SSE-NEXT: mulps %xmm1, %xmm1
; SSE-NEXT: mulps %xmm2, %xmm1 ; SSE-NEXT: mulps %xmm2, %xmm1
; SSE-NEXT: rsqrtps %xmm1, %xmm2 ; SSE-NEXT: rsqrtps %xmm1, %xmm2
; SSE-NEXT: mulps %xmm2, %xmm1 ; SSE-NEXT: mulps %xmm2, %xmm1
; SSE-NEXT: mulps %xmm2, %xmm1 ; SSE-NEXT: mulps %xmm2, %xmm1
; SSE-NEXT: addps {{.*}}(%rip), %xmm1
; SSE-NEXT: mulps {{.*}}(%rip), %xmm2 ; SSE-NEXT: mulps {{.*}}(%rip), %xmm2
; SSE-NEXT: addps {{.*}}(%rip), %xmm1
; SSE-NEXT: mulps %xmm1, %xmm2 ; SSE-NEXT: mulps %xmm1, %xmm2
; SSE-NEXT: mulps %xmm2, %xmm0 ; SSE-NEXT: mulps %xmm2, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: div_sqrt_fabs_v4f32: ; AVX1-LABEL: div_sqrt_fabs_v4f32:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vmulps %xmm1, %xmm1, %xmm1 ; AVX1-NEXT: vmulps %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vmulps %xmm2, %xmm1, %xmm1 ; AVX1-NEXT: vmulps %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vrsqrtps %xmm1, %xmm2 ; AVX1-NEXT: vrsqrtps %xmm1, %xmm2
; AVX1-NEXT: vmulps %xmm2, %xmm1, %xmm1 ; AVX1-NEXT: vmulps %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vmulps %xmm2, %xmm1, %xmm1 ; AVX1-NEXT: vmulps %xmm2, %xmm1, %xmm1
; AVX1-NEXT: vaddps {{.*}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vmulps {{.*}}(%rip), %xmm2, %xmm2 ; AVX1-NEXT: vmulps {{.*}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vaddps {{.*}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vmulps %xmm1, %xmm2, %xmm1 ; AVX1-NEXT: vmulps %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vmulps %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vmulps %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX512-LABEL: div_sqrt_fabs_v4f32: ; AVX512-LABEL: div_sqrt_fabs_v4f32:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vmulps %xmm1, %xmm1, %xmm1 ; AVX512-NEXT: vmulps %xmm1, %xmm1, %xmm1
; AVX512-NEXT: vbroadcastss {{.*#+}} xmm3 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0]
; AVX512-NEXT: vmulps %xmm2, %xmm1, %xmm1 ; AVX512-NEXT: vmulps %xmm2, %xmm1, %xmm1
; AVX512-NEXT: vrsqrtps %xmm1, %xmm2 ; AVX512-NEXT: vrsqrtps %xmm1, %xmm2
; AVX512-NEXT: vmulps %xmm2, %xmm1, %xmm1 ; AVX512-NEXT: vmulps %xmm2, %xmm1, %xmm1
; AVX512-NEXT: vbroadcastss {{.*#+}} xmm3 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0]
; AVX512-NEXT: vfmadd231ps {{.*#+}} xmm3 = (xmm2 * xmm1) + xmm3 ; AVX512-NEXT: vfmadd231ps {{.*#+}} xmm3 = (xmm2 * xmm1) + xmm3
; AVX512-NEXT: vbroadcastss {{.*#+}} xmm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1] ; AVX512-NEXT: vbroadcastss {{.*#+}} xmm1 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
; AVX512-NEXT: vmulps %xmm1, %xmm2, %xmm1 ; AVX512-NEXT: vmulps %xmm1, %xmm2, %xmm1
; AVX512-NEXT: vmulps %xmm3, %xmm1, %xmm1 ; AVX512-NEXT: vmulps %xmm3, %xmm1, %xmm1
; AVX512-NEXT: vmulps %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vmulps %xmm1, %xmm0, %xmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%s = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %z) %s = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %z)
%a = call <4 x float> @llvm.fabs.v4f32(<4 x float> %y) %a = call <4 x float> @llvm.fabs.v4f32(<4 x float> %y)
%m = fmul reassoc <4 x float> %a, %s %m = fmul reassoc <4 x float> %a, %s
%d = fdiv reassoc arcp <4 x float> %x, %m %d = fdiv reassoc arcp <4 x float> %x, %m
ret <4 x float> %d ret <4 x float> %d
} }
; This has 'arcp' but does not have 'reassoc' FMF. ; This has 'arcp' but does not have 'reassoc' FMF.
; We allow converting the sqrt to an estimate, but ; We allow converting the sqrt to an estimate, but
; do not pull the divisor into the estimate. ; do not pull the divisor into the estimate.
; x / (fabs(y) * sqrt(z)) --> x * rsqrt(z) / fabs(y) ; x / (fabs(y) * sqrt(z)) --> x * rsqrt(z) / fabs(y)
define <4 x float> @div_sqrt_fabs_v4f32_fmf(<4 x float> %x, <4 x float> %y, <4 x float> %z) { define <4 x float> @div_sqrt_fabs_v4f32_fmf(<4 x float> %x, <4 x float> %y, <4 x float> %z) {
; SSE-LABEL: div_sqrt_fabs_v4f32_fmf: ; SSE-LABEL: div_sqrt_fabs_v4f32_fmf:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: rsqrtps %xmm2, %xmm3 ; SSE-NEXT: rsqrtps %xmm2, %xmm3
; SSE-NEXT: andps {{.*}}(%rip), %xmm1
; SSE-NEXT: mulps %xmm3, %xmm2 ; SSE-NEXT: mulps %xmm3, %xmm2
; SSE-NEXT: mulps %xmm3, %xmm2 ; SSE-NEXT: mulps %xmm3, %xmm2
; SSE-NEXT: addps {{.*}}(%rip), %xmm2
; SSE-NEXT: mulps {{.*}}(%rip), %xmm3 ; SSE-NEXT: mulps {{.*}}(%rip), %xmm3
; SSE-NEXT: addps {{.*}}(%rip), %xmm2
; SSE-NEXT: mulps %xmm2, %xmm3 ; SSE-NEXT: mulps %xmm2, %xmm3
; SSE-NEXT: andps {{.*}}(%rip), %xmm1
; SSE-NEXT: divps %xmm1, %xmm3 ; SSE-NEXT: divps %xmm1, %xmm3
; SSE-NEXT: mulps %xmm3, %xmm0 ; SSE-NEXT: mulps %xmm3, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: div_sqrt_fabs_v4f32_fmf: ; AVX1-LABEL: div_sqrt_fabs_v4f32_fmf:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vrsqrtps %xmm2, %xmm3 ; AVX1-NEXT: vrsqrtps %xmm2, %xmm3
; AVX1-NEXT: vandps {{.*}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vmulps %xmm3, %xmm2, %xmm2 ; AVX1-NEXT: vmulps %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vmulps %xmm3, %xmm2, %xmm2 ; AVX1-NEXT: vmulps %xmm3, %xmm2, %xmm2
; AVX1-NEXT: vaddps {{.*}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vmulps {{.*}}(%rip), %xmm3, %xmm3 ; AVX1-NEXT: vmulps {{.*}}(%rip), %xmm3, %xmm3
; AVX1-NEXT: vaddps {{.*}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vmulps %xmm2, %xmm3, %xmm2 ; AVX1-NEXT: vmulps %xmm2, %xmm3, %xmm2
; AVX1-NEXT: vandps {{.*}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vdivps %xmm1, %xmm2, %xmm1 ; AVX1-NEXT: vdivps %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vmulps %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vmulps %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX512-LABEL: div_sqrt_fabs_v4f32_fmf: ; AVX512-LABEL: div_sqrt_fabs_v4f32_fmf:
; AVX512: # %bb.0: ; AVX512: # %bb.0:
; AVX512-NEXT: vrsqrtps %xmm2, %xmm3 ; AVX512-NEXT: vrsqrtps %xmm2, %xmm3
; AVX512-NEXT: vbroadcastss {{.*#+}} xmm4 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1] ; AVX512-NEXT: vbroadcastss {{.*#+}} xmm4 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
; AVX512-NEXT: vmulps %xmm4, %xmm3, %xmm4 ; AVX512-NEXT: vbroadcastss {{.*#+}} xmm6 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0]
; AVX512-NEXT: vbroadcastss {{.*#+}} xmm5 = [NaN,NaN,NaN,NaN]
; AVX512-NEXT: vmulps %xmm3, %xmm2, %xmm2 ; AVX512-NEXT: vmulps %xmm3, %xmm2, %xmm2
; AVX512-NEXT: vmulps %xmm4, %xmm3, %xmm4
; AVX512-NEXT: vandps %xmm5, %xmm1, %xmm1
; AVX512-NEXT: vmulps %xmm3, %xmm2, %xmm2 ; AVX512-NEXT: vmulps %xmm3, %xmm2, %xmm2
; AVX512-NEXT: vbroadcastss {{.*#+}} xmm3 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0] ; AVX512-NEXT: vaddps %xmm6, %xmm2, %xmm2
; AVX512-NEXT: vaddps %xmm3, %xmm2, %xmm2
; AVX512-NEXT: vbroadcastss {{.*#+}} xmm3 = [NaN,NaN,NaN,NaN]
; AVX512-NEXT: vmulps %xmm2, %xmm4, %xmm2 ; AVX512-NEXT: vmulps %xmm2, %xmm4, %xmm2
; AVX512-NEXT: vandps %xmm3, %xmm1, %xmm1
; AVX512-NEXT: vdivps %xmm1, %xmm2, %xmm1 ; AVX512-NEXT: vdivps %xmm1, %xmm2, %xmm1
; AVX512-NEXT: vmulps %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vmulps %xmm1, %xmm0, %xmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%s = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %z) %s = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %z)
%a = call <4 x float> @llvm.fabs.v4f32(<4 x float> %y) %a = call <4 x float> @llvm.fabs.v4f32(<4 x float> %y)
%m = fmul <4 x float> %a, %s %m = fmul <4 x float> %a, %s
%d = fdiv arcp <4 x float> %x, %m %d = fdiv arcp <4 x float> %x, %m
ret <4 x float> %d ret <4 x float> %d
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llvm/test/CodeGen/X86/sse-domains.ll

Show All 11 Lines
; back-edge. Check that everything is still moved into the integer domain. ; back-edge. Check that everything is still moved into the integer domain.
define void @f(<4 x i32>* nocapture %p, i32 %n) nounwind uwtable ssp { define void @f(<4 x i32>* nocapture %p, i32 %n) nounwind uwtable ssp {
entry: entry:
br label %while.body br label %while.body
; Materialize a zeroinitializer and a constant-pool load in the integer domain. ; Materialize a zeroinitializer and a constant-pool load in the integer domain.
; The order is not important. ; The order is not important.
; CHECK: pxor
; CHECK: movdqa ; CHECK: movdqa
; CHECK: pxor
; The instructions in the loop must all be integer domain as well. ; The instructions in the loop must all be integer domain as well.
; CHECK: while.body ; CHECK: while.body
; CHECK: pand ; CHECK: pand
; CHECK: movdqa ; CHECK: movdqa
; CHECK: movdqa ; CHECK: movdqa
; Finally, the controlling integer-only instruction. ; Finally, the controlling integer-only instruction.
; CHECK: paddd ; CHECK: paddd
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llvm/test/CodeGen/X86/sse_partial_update.ll

Show First 20 Lines • Show All 45 Lines • ▼ Show 20 Lines; CHECK-NEXT: jmp _callee ## TAILCALL
ret void ret void
} }
declare <4 x float> @llvm.x86.sse.rcp.ss(<4 x float>) nounwind readnone declare <4 x float> @llvm.x86.sse.rcp.ss(<4 x float>) nounwind readnone
define void @sqrtss(<4 x float> %a) nounwind uwtable ssp { define void @sqrtss(<4 x float> %a) nounwind uwtable ssp {
; CHECK-LABEL: sqrtss: ; CHECK-LABEL: sqrtss:
; CHECK: ## %bb.0: ; CHECK: ## %bb.0:
; CHECK-NEXT: sqrtss %xmm0, %xmm1 ; CHECK-NEXT: sqrtss %xmm0, %xmm1
; CHECK-NEXT: cvtss2sd %xmm1, %xmm2
; CHECK-NEXT: movshdup {{.*#+}} xmm0 = xmm0[1,1,3,3] ; CHECK-NEXT: movshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
; CHECK-NEXT: cvtss2sd %xmm1, %xmm2
; CHECK-NEXT: xorps %xmm1, %xmm1 ; CHECK-NEXT: xorps %xmm1, %xmm1
; CHECK-NEXT: cvtss2sd %xmm0, %xmm1 ; CHECK-NEXT: cvtss2sd %xmm0, %xmm1
; CHECK-NEXT: movaps %xmm2, %xmm0 ; CHECK-NEXT: movaps %xmm2, %xmm0
; CHECK-NEXT: jmp _callee ## TAILCALL ; CHECK-NEXT: jmp _callee ## TAILCALL
%t0 = tail call <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float> %a) nounwind %t0 = tail call <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float> %a) nounwind
%a.addr.0.extract = extractelement <4 x float> %t0, i32 0 %a.addr.0.extract = extractelement <4 x float> %t0, i32 0
%conv = fpext float %a.addr.0.extract to double %conv = fpext float %a.addr.0.extract to double
%a.addr.4.extract = extractelement <4 x float> %t0, i32 1 %a.addr.4.extract = extractelement <4 x float> %t0, i32 1
%conv3 = fpext float %a.addr.4.extract to double %conv3 = fpext float %a.addr.4.extract to double
tail call void @callee(double %conv, double %conv3) nounwind tail call void @callee(double %conv, double %conv3) nounwind
ret void ret void
} }
declare <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float>) nounwind readnone declare <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float>) nounwind readnone
define void @sqrtsd(<2 x double> %a) nounwind uwtable ssp { define void @sqrtsd(<2 x double> %a) nounwind uwtable ssp {
; CHECK-LABEL: sqrtsd: ; CHECK-LABEL: sqrtsd:
; CHECK: ## %bb.0: ; CHECK: ## %bb.0:
; CHECK-NEXT: sqrtsd %xmm0, %xmm1 ; CHECK-NEXT: sqrtsd %xmm0, %xmm1
; CHECK-NEXT: cvtsd2ss %xmm1, %xmm2
; CHECK-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1] ; CHECK-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1,1]
; CHECK-NEXT: cvtsd2ss %xmm1, %xmm2
; CHECK-NEXT: xorps %xmm1, %xmm1 ; CHECK-NEXT: xorps %xmm1, %xmm1
; CHECK-NEXT: cvtsd2ss %xmm0, %xmm1 ; CHECK-NEXT: cvtsd2ss %xmm0, %xmm1
; CHECK-NEXT: movaps %xmm2, %xmm0 ; CHECK-NEXT: movaps %xmm2, %xmm0
; CHECK-NEXT: jmp _callee2 ## TAILCALL ; CHECK-NEXT: jmp _callee2 ## TAILCALL
%t0 = tail call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> %a) nounwind %t0 = tail call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> %a) nounwind
%a0 = extractelement <2 x double> %t0, i32 0 %a0 = extractelement <2 x double> %t0, i32 0
%conv = fptrunc double %a0 to float %conv = fptrunc double %a0 to float
%a1 = extractelement <2 x double> %t0, i32 1 %a1 = extractelement <2 x double> %t0, i32 1
▲ Show 20 Lines • Show All 57 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/statepoint-vector.ll

Show All 24 Lines
; Can we lower the base, derived pairs if both are vectors? ; Can we lower the base, derived pairs if both are vectors?
define <2 x i8 addrspace(1)*> @test2(<2 x i8 addrspace(1)*> %obj, i64 %offset) gc "statepoint-example" { define <2 x i8 addrspace(1)*> @test2(<2 x i8 addrspace(1)*> %obj, i64 %offset) gc "statepoint-example" {
; CHECK-LABEL: test2: ; CHECK-LABEL: test2:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subq $40, %rsp ; CHECK-NEXT: subq $40, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 48 ; CHECK-NEXT: .cfi_def_cfa_offset 48
; CHECK-NEXT: movq %rdi, %xmm1 ; CHECK-NEXT: movq %rdi, %xmm1
; CHECK-NEXT: movdqa %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,1,0,1] ; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,1,0,1]
; CHECK-NEXT: paddq %xmm0, %xmm1 ; CHECK-NEXT: paddq %xmm0, %xmm1
; CHECK-NEXT: movdqa %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: movdqa %xmm1, (%rsp) ; CHECK-NEXT: movdqa %xmm1, (%rsp)
; CHECK-NEXT: callq do_safepoint ; CHECK-NEXT: callq do_safepoint
; CHECK-NEXT: .Ltmp1: ; CHECK-NEXT: .Ltmp1:
; CHECK-NEXT: movaps (%rsp), %xmm0 ; CHECK-NEXT: movaps (%rsp), %xmm0
; CHECK-NEXT: addq $40, %rsp ; CHECK-NEXT: addq $40, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq ; CHECK-NEXT: retq
entry: entry:
Show All 10 Lines
; - We don't remove the testb even though it serves no purpose ; - We don't remove the testb even though it serves no purpose
; - We could in principal reuse the argument memory (%rsi) and do away ; - We could in principal reuse the argument memory (%rsi) and do away
; with stack slots entirely. ; with stack slots entirely.
define <2 x i64 addrspace(1)*> @test3(i1 %cnd, <2 x i64 addrspace(1)*>* %ptr) gc "statepoint-example" { define <2 x i64 addrspace(1)*> @test3(i1 %cnd, <2 x i64 addrspace(1)*>* %ptr) gc "statepoint-example" {
; CHECK-LABEL: test3: ; CHECK-LABEL: test3:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subq $40, %rsp ; CHECK-NEXT: subq $40, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 48 ; CHECK-NEXT: .cfi_def_cfa_offset 48
; CHECK-NEXT: testb $1, %dil
; CHECK-NEXT: movaps (%rsi), %xmm0 ; CHECK-NEXT: movaps (%rsi), %xmm0
; CHECK-NEXT: testb $1, %dil
; CHECK-NEXT: movaps %xmm0, (%rsp) ; CHECK-NEXT: movaps %xmm0, (%rsp)
; CHECK-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp) ; CHECK-NEXT: movaps %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: callq do_safepoint ; CHECK-NEXT: callq do_safepoint
; CHECK-NEXT: .Ltmp2: ; CHECK-NEXT: .Ltmp2:
; CHECK-NEXT: movaps (%rsp), %xmm0 ; CHECK-NEXT: movaps (%rsp), %xmm0
; CHECK-NEXT: addq $40, %rsp ; CHECK-NEXT: addq $40, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq ; CHECK-NEXT: retq
Show All 38 Linesentry:
%safepoint_token = call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @do_safepoint, i32 0, i32 0, i32 0, i32 0) ["gc-live" (<2 x i8 addrspace(1)*> zeroinitializer)] %safepoint_token = call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 0, i32 0, void ()* @do_safepoint, i32 0, i32 0, i32 0, i32 0) ["gc-live" (<2 x i8 addrspace(1)*> zeroinitializer)]
%obj.relocated = call coldcc <2 x i8 addrspace(1)*> @llvm.experimental.gc.relocate.v2p1i8(token %safepoint_token, i32 0, i32 0) %obj.relocated = call coldcc <2 x i8 addrspace(1)*> @llvm.experimental.gc.relocate.v2p1i8(token %safepoint_token, i32 0, i32 0)
ret <2 x i8 addrspace(1)*> %obj.relocated ret <2 x i8 addrspace(1)*> %obj.relocated
} }
; Check that we can lower a constant typed as i128 correctly. We don't have ; Check that we can lower a constant typed as i128 correctly. We don't have
; a representation of larger than 64 bit constant in the StackMap format. At ; a representation of larger than 64 bit constant in the StackMap format. At
; the moment, this simply means spilling them, but there's a potential ; the moment, this simply means spilling them, but there's a potential
; optimization for values representable as sext(Con64). ; optimization for values representable as sext(Con64).
define void @test5() gc "statepoint-example" { define void @test5() gc "statepoint-example" {
; CHECK-LABEL: test5: ; CHECK-LABEL: test5:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subq $40, %rsp ; CHECK-NEXT: subq $40, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 48 ; CHECK-NEXT: .cfi_def_cfa_offset 48
; CHECK-NEXT: xorps %xmm0, %xmm0 ; CHECK-NEXT: xorps %xmm0, %xmm0
; CHECK-NEXT: movups %xmm0, {{[0-9]+}}(%rsp) ; CHECK-NEXT: movups %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: movq $-1, {{[0-9]+}}(%rsp) ; CHECK-NEXT: movq $-1, {{[0-9]+}}(%rsp)
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llvm/test/CodeGen/X86/tailcall-64.ll

Show First 20 Lines • Show All 211 Lines • ▼ Show 20 Lines
%struct.funcs = type { i32 (i8*, i32*, i32)*, i32 (i8*)*, i32 (i8*)*, i32 (i8*, i32)*, i32 } %struct.funcs = type { i32 (i8*, i32*, i32)*, i32 (i8*)*, i32 (i8*)*, i32 (i8*, i32)*, i32 }
@func_table = external global [0 x %struct.funcs] @func_table = external global [0 x %struct.funcs]
; Check that we can fold an indexed load into a tail call instruction. ; Check that we can fold an indexed load into a tail call instruction.
define void @fold_indexed_load(i8* %mbstr, i64 %idxprom) nounwind uwtable ssp { define void @fold_indexed_load(i8* %mbstr, i64 %idxprom) nounwind uwtable ssp {
; CHECK-LABEL: fold_indexed_load: ; CHECK-LABEL: fold_indexed_load:
; CHECK: ## %bb.0: ## %entry ; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: leaq (%rsi,%rsi,4), %rax
; CHECK-NEXT: movq _func_table@{{.*}}(%rip), %rcx ; CHECK-NEXT: movq _func_table@{{.*}}(%rip), %rcx
; CHECK-NEXT: leaq (%rsi,%rsi,4), %rax
; CHECK-NEXT: jmpq *16(%rcx,%rax,8) ## TAILCALL ; CHECK-NEXT: jmpq *16(%rcx,%rax,8) ## TAILCALL
entry: entry:
%dsplen = getelementptr inbounds [0 x %struct.funcs], [0 x %struct.funcs]* @func_table, i64 0, i64 %idxprom, i32 2 %dsplen = getelementptr inbounds [0 x %struct.funcs], [0 x %struct.funcs]* @func_table, i64 0, i64 %idxprom, i32 2
%x1 = load i32 (i8*)*, i32 (i8*)** %dsplen, align 8 %x1 = load i32 (i8*)*, i32 (i8*)** %dsplen, align 8
%call = tail call i32 %x1(i8* %mbstr) nounwind %call = tail call i32 %x1(i8* %mbstr) nounwind
ret void ret void
} }
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; typedef int (*funcptr)(void*, ...); ; typedef int (*funcptr)(void*, ...);
; extern const funcptr funcs[]; ; extern const funcptr funcs[];
; int f(int n) { ; int f(int n) {
; return funcs[n](0, 0, 0, 0, 0, 0); ; return funcs[n](0, 0, 0, 0, 0, 0);
; } ; }
define i32 @rdar12282281(i32 %n) nounwind uwtable ssp { define i32 @rdar12282281(i32 %n) nounwind uwtable ssp {
; CHECK-LABEL: rdar12282281: ; CHECK-LABEL: rdar12282281:
; CHECK: ## %bb.0: ## %entry ; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: movslq %edi, %rax
; CHECK-NEXT: movq _funcs@{{.*}}(%rip), %rcx ; CHECK-NEXT: movq _funcs@{{.*}}(%rip), %rcx
; CHECK-NEXT: movq (%rcx,%rax,8), %r11 ; CHECK-NEXT: movslq %edi, %rax
; CHECK-NEXT: xorl %edi, %edi ; CHECK-NEXT: xorl %edi, %edi
; CHECK-NEXT: xorl %esi, %esi ; CHECK-NEXT: xorl %esi, %esi
; CHECK-NEXT: xorl %edx, %edx ; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: xorl %r8d, %r8d ; CHECK-NEXT: xorl %r8d, %r8d
; CHECK-NEXT: xorl %r9d, %r9d ; CHECK-NEXT: xorl %r9d, %r9d
; CHECK-NEXT: movq (%rcx,%rax,8), %r11
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: jmpq *%r11 ## TAILCALL ; CHECK-NEXT: jmpq *%r11 ## TAILCALL
entry: entry:
%idxprom = sext i32 %n to i64 %idxprom = sext i32 %n to i64
%arrayidx = getelementptr inbounds [0 x i32 (i8*, ...)*], [0 x i32 (i8*, ...)*]* @funcs, i64 0, i64 %idxprom %arrayidx = getelementptr inbounds [0 x i32 (i8*, ...)*], [0 x i32 (i8*, ...)*]* @funcs, i64 0, i64 %idxprom
%0 = load i32 (i8*, ...)*, i32 (i8*, ...)** %arrayidx, align 8 %0 = load i32 (i8*, ...)*, i32 (i8*, ...)** %arrayidx, align 8
%call = tail call i32 (i8*, ...) %0(i8* null, i32 0, i32 0, i32 0, i32 0, i32 0) nounwind %call = tail call i32 (i8*, ...) %0(i8* null, i32 0, i32 0, i32 0, i32 0, i32 0) nounwind
ret i32 %call ret i32 %call
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llvm/test/CodeGen/X86/test-nofold.ll

; RUN: llc < %s -mtriple=i686-- -mcpu=yonah | FileCheck %s ; RUN: llc < %s -mtriple=i686-- -mcpu=yonah | FileCheck %s
; rdar://5752025 ; rdar://5752025
; We want: ; We want:
; CHECK: movl 4(%esp), %ecx ; CHECK: movl 4(%esp), %ecx
; CHECK-NEXT: andl $15, %ecx
; CHECK-NEXT: movl $42, %eax ; CHECK-NEXT: movl $42, %eax
; CHECK-NEXT: andl $15, %ecx
; CHECK-NEXT: cmovel %ecx, %eax ; CHECK-NEXT: cmovel %ecx, %eax
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; We don't want: ; We don't want:
; movl 4(%esp), %eax ; movl 4(%esp), %eax
; movl %eax, %ecx # bad: extra copy ; movl %eax, %ecx # bad: extra copy
; andl $15, %ecx ; andl $15, %ecx
; testl $15, %eax # bad: peep obstructed ; testl $15, %eax # bad: peep obstructed
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llvm/test/CodeGen/X86/unaligned-load.ll

Show First 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
define void @func_aligned() nounwind ssp { define void @func_aligned() nounwind ssp {
; I386-LABEL: func_aligned: ; I386-LABEL: func_aligned:
; I386: ## %bb.0: ## %entry ; I386: ## %bb.0: ## %entry
; I386-NEXT: subl $44, %esp ; I386-NEXT: subl $44, %esp
; I386-NEXT: movaps {{.*#+}} xmm0 = [1498564676,1313821779,1380982853,1095911247] ; I386-NEXT: movaps {{.*#+}} xmm0 = [1498564676,1313821779,1380982853,1095911247]
; I386-NEXT: .p2align 4, 0x90 ; I386-NEXT: .p2align 4, 0x90
; I386-NEXT: LBB1_1: ## %bb ; I386-NEXT: LBB1_1: ## %bb
; I386-NEXT: ## =>This Inner Loop Header: Depth=1 ; I386-NEXT: ## =>This Inner Loop Header: Depth=1
; I386-NEXT: movaps %xmm0, (%esp)
; I386-NEXT: movl $4673097, {{[0-9]+}}(%esp) ## imm = 0x474E49 ; I386-NEXT: movl $4673097, {{[0-9]+}}(%esp) ## imm = 0x474E49
; I386-NEXT: movaps %xmm0, (%esp)
; I386-NEXT: movl $1230132307, {{[0-9]+}}(%esp) ## imm = 0x49525453 ; I386-NEXT: movl $1230132307, {{[0-9]+}}(%esp) ## imm = 0x49525453
; I386-NEXT: movl $541347367, {{[0-9]+}}(%esp) ## imm = 0x20444E27 ; I386-NEXT: movl $541347367, {{[0-9]+}}(%esp) ## imm = 0x20444E27
; I386-NEXT: movl $840969293, {{[0-9]+}}(%esp) ## imm = 0x32202C4D ; I386-NEXT: movl $840969293, {{[0-9]+}}(%esp) ## imm = 0x32202C4D
; I386-NEXT: jmp LBB1_1 ; I386-NEXT: jmp LBB1_1
; ;
; CORE2-LABEL: func_aligned: ; CORE2-LABEL: func_aligned:
; CORE2: ## %bb.0: ## %entry ; CORE2: ## %bb.0: ## %entry
; CORE2-NEXT: movabsq $20070800167293728, %rax ## imm = 0x474E4952545320 ; CORE2-NEXT: movabsq $20070800167293728, %rax ## imm = 0x474E4952545320
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llvm/test/CodeGen/X86/vec_compare.ll

Show First 20 Lines • Show All 73 Lines • ▼ Show 20 Lines; CHECK-NEXT: retl
%D = sext <2 x i1> %C to <2 x i64> %D = sext <2 x i1> %C to <2 x i64>
ret <2 x i64> %D ret <2 x i64> %D
} }
define <2 x i64> @test7(<2 x i64> %A, <2 x i64> %B) nounwind { define <2 x i64> @test7(<2 x i64> %A, <2 x i64> %B) nounwind {
; CHECK-LABEL: test7: ; CHECK-LABEL: test7:
; CHECK: ## %bb.0: ; CHECK: ## %bb.0:
; CHECK-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,0,2147483648,0] ; CHECK-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,0,2147483648,0]
; CHECK-NEXT: pxor %xmm2, %xmm1
; CHECK-NEXT: pxor %xmm2, %xmm0 ; CHECK-NEXT: pxor %xmm2, %xmm0
; CHECK-NEXT: pxor %xmm2, %xmm1
; CHECK-NEXT: movdqa %xmm0, %xmm2 ; CHECK-NEXT: movdqa %xmm0, %xmm2
; CHECK-NEXT: pcmpgtd %xmm1, %xmm2
; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm2[0,0,2,2]
; CHECK-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-NEXT: pcmpgtd %xmm1, %xmm2
; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; CHECK-NEXT: pand %xmm3, %xmm1 ; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm2[0,0,2,2]
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,3,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,3,3]
; CHECK-NEXT: pand %xmm3, %xmm1
; CHECK-NEXT: por %xmm1, %xmm0 ; CHECK-NEXT: por %xmm1, %xmm0
; CHECK-NEXT: retl ; CHECK-NEXT: retl
%C = icmp sgt <2 x i64> %A, %B %C = icmp sgt <2 x i64> %A, %B
%D = sext <2 x i1> %C to <2 x i64> %D = sext <2 x i1> %C to <2 x i64>
ret <2 x i64> %D ret <2 x i64> %D
} }
define <2 x i64> @test8(<2 x i64> %A, <2 x i64> %B) nounwind { define <2 x i64> @test8(<2 x i64> %A, <2 x i64> %B) nounwind {
; CHECK-LABEL: test8: ; CHECK-LABEL: test8:
; CHECK: ## %bb.0: ; CHECK: ## %bb.0:
; CHECK-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,0,2147483648,0] ; CHECK-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,0,2147483648,0]
; CHECK-NEXT: pxor %xmm2, %xmm0
; CHECK-NEXT: pxor %xmm2, %xmm1 ; CHECK-NEXT: pxor %xmm2, %xmm1
; CHECK-NEXT: pxor %xmm2, %xmm0
; CHECK-NEXT: movdqa %xmm1, %xmm2 ; CHECK-NEXT: movdqa %xmm1, %xmm2
; CHECK-NEXT: pcmpgtd %xmm0, %xmm2
; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm2[0,0,2,2]
; CHECK-NEXT: pcmpeqd %xmm0, %xmm1 ; CHECK-NEXT: pcmpeqd %xmm0, %xmm1
; CHECK-NEXT: pcmpgtd %xmm0, %xmm2
; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; CHECK-NEXT: pand %xmm3, %xmm1 ; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm2[0,0,2,2]
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,3,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,3,3]
; CHECK-NEXT: pand %xmm3, %xmm1
; CHECK-NEXT: por %xmm1, %xmm0 ; CHECK-NEXT: por %xmm1, %xmm0
; CHECK-NEXT: retl ; CHECK-NEXT: retl
%C = icmp slt <2 x i64> %A, %B %C = icmp slt <2 x i64> %A, %B
%D = sext <2 x i1> %C to <2 x i64> %D = sext <2 x i1> %C to <2 x i64>
ret <2 x i64> %D ret <2 x i64> %D
} }
define <2 x i64> @test9(<2 x i64> %A, <2 x i64> %B) nounwind { define <2 x i64> @test9(<2 x i64> %A, <2 x i64> %B) nounwind {
; CHECK-LABEL: test9: ; CHECK-LABEL: test9:
; CHECK: ## %bb.0: ; CHECK: ## %bb.0:
; CHECK-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,0,2147483648,0] ; CHECK-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,0,2147483648,0]
; CHECK-NEXT: pxor %xmm2, %xmm0
; CHECK-NEXT: pxor %xmm2, %xmm1 ; CHECK-NEXT: pxor %xmm2, %xmm1
; CHECK-NEXT: pxor %xmm2, %xmm0
; CHECK-NEXT: movdqa %xmm1, %xmm2 ; CHECK-NEXT: movdqa %xmm1, %xmm2
; CHECK-NEXT: pcmpgtd %xmm0, %xmm2
; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm2[0,0,2,2]
; CHECK-NEXT: pcmpeqd %xmm0, %xmm1 ; CHECK-NEXT: pcmpeqd %xmm0, %xmm1
; CHECK-NEXT: pcmpgtd %xmm0, %xmm2
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,3,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,3,3]
; CHECK-NEXT: pand %xmm3, %xmm0 ; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm2[0,0,2,2]
; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3]
; CHECK-NEXT: pand %xmm3, %xmm0
; CHECK-NEXT: por %xmm0, %xmm1 ; CHECK-NEXT: por %xmm0, %xmm1
; CHECK-NEXT: pcmpeqd %xmm0, %xmm0 ; CHECK-NEXT: pcmpeqd %xmm0, %xmm0
; CHECK-NEXT: pxor %xmm1, %xmm0 ; CHECK-NEXT: pxor %xmm1, %xmm0
; CHECK-NEXT: retl ; CHECK-NEXT: retl
%C = icmp sge <2 x i64> %A, %B %C = icmp sge <2 x i64> %A, %B
%D = sext <2 x i1> %C to <2 x i64> %D = sext <2 x i1> %C to <2 x i64>
ret <2 x i64> %D ret <2 x i64> %D
} }
define <2 x i64> @test10(<2 x i64> %A, <2 x i64> %B) nounwind { define <2 x i64> @test10(<2 x i64> %A, <2 x i64> %B) nounwind {
; CHECK-LABEL: test10: ; CHECK-LABEL: test10:
; CHECK: ## %bb.0: ; CHECK: ## %bb.0:
; CHECK-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,0,2147483648,0] ; CHECK-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,0,2147483648,0]
; CHECK-NEXT: pxor %xmm2, %xmm1
; CHECK-NEXT: pxor %xmm2, %xmm0 ; CHECK-NEXT: pxor %xmm2, %xmm0
; CHECK-NEXT: pxor %xmm2, %xmm1
; CHECK-NEXT: movdqa %xmm0, %xmm2 ; CHECK-NEXT: movdqa %xmm0, %xmm2
; CHECK-NEXT: pcmpgtd %xmm1, %xmm2
; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm2[0,0,2,2]
; CHECK-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-NEXT: pcmpgtd %xmm1, %xmm2
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
; CHECK-NEXT: pand %xmm3, %xmm0 ; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm2[0,0,2,2]
; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3]
; CHECK-NEXT: pand %xmm3, %xmm0
; CHECK-NEXT: por %xmm0, %xmm1 ; CHECK-NEXT: por %xmm0, %xmm1
; CHECK-NEXT: pcmpeqd %xmm0, %xmm0 ; CHECK-NEXT: pcmpeqd %xmm0, %xmm0
; CHECK-NEXT: pxor %xmm1, %xmm0 ; CHECK-NEXT: pxor %xmm1, %xmm0
; CHECK-NEXT: retl ; CHECK-NEXT: retl
%C = icmp sle <2 x i64> %A, %B %C = icmp sle <2 x i64> %A, %B
%D = sext <2 x i1> %C to <2 x i64> %D = sext <2 x i1> %C to <2 x i64>
ret <2 x i64> %D ret <2 x i64> %D
} }
define <2 x i64> @test11(<2 x i64> %A, <2 x i64> %B) nounwind { define <2 x i64> @test11(<2 x i64> %A, <2 x i64> %B) nounwind {
; CHECK-LABEL: test11: ; CHECK-LABEL: test11:
; CHECK: ## %bb.0: ; CHECK: ## %bb.0:
; CHECK-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648] ; CHECK-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
; CHECK-NEXT: pxor %xmm2, %xmm1
; CHECK-NEXT: pxor %xmm2, %xmm0 ; CHECK-NEXT: pxor %xmm2, %xmm0
; CHECK-NEXT: pxor %xmm2, %xmm1
; CHECK-NEXT: movdqa %xmm0, %xmm2 ; CHECK-NEXT: movdqa %xmm0, %xmm2
; CHECK-NEXT: pcmpgtd %xmm1, %xmm2
; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm2[0,0,2,2]
; CHECK-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-NEXT: pcmpgtd %xmm1, %xmm2
; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
; CHECK-NEXT: pand %xmm3, %xmm1 ; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm2[0,0,2,2]
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,3,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,3,3]
; CHECK-NEXT: pand %xmm3, %xmm1
; CHECK-NEXT: por %xmm1, %xmm0 ; CHECK-NEXT: por %xmm1, %xmm0
; CHECK-NEXT: retl ; CHECK-NEXT: retl
%C = icmp ugt <2 x i64> %A, %B %C = icmp ugt <2 x i64> %A, %B
%D = sext <2 x i1> %C to <2 x i64> %D = sext <2 x i1> %C to <2 x i64>
ret <2 x i64> %D ret <2 x i64> %D
} }
define <2 x i64> @test12(<2 x i64> %A, <2 x i64> %B) nounwind { define <2 x i64> @test12(<2 x i64> %A, <2 x i64> %B) nounwind {
; CHECK-LABEL: test12: ; CHECK-LABEL: test12:
; CHECK: ## %bb.0: ; CHECK: ## %bb.0:
; CHECK-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648] ; CHECK-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
; CHECK-NEXT: pxor %xmm2, %xmm0
; CHECK-NEXT: pxor %xmm2, %xmm1 ; CHECK-NEXT: pxor %xmm2, %xmm1
; CHECK-NEXT: pxor %xmm2, %xmm0
; CHECK-NEXT: movdqa %xmm1, %xmm2 ; CHECK-NEXT: movdqa %xmm1, %xmm2
; CHECK-NEXT: pcmpgtd %xmm0, %xmm2
; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm2[0,0,2,2]
; CHECK-NEXT: pcmpeqd %xmm0, %xmm1 ; CHECK-NEXT: pcmpeqd %xmm0, %xmm1
; CHECK-NEXT: pcmpgtd %xmm0, %xmm2
; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; CHECK-NEXT: pand %xmm3, %xmm1 ; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm2[0,0,2,2]
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,3,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,3,3]
; CHECK-NEXT: pand %xmm3, %xmm1
; CHECK-NEXT: por %xmm1, %xmm0 ; CHECK-NEXT: por %xmm1, %xmm0
; CHECK-NEXT: retl ; CHECK-NEXT: retl
%C = icmp ult <2 x i64> %A, %B %C = icmp ult <2 x i64> %A, %B
%D = sext <2 x i1> %C to <2 x i64> %D = sext <2 x i1> %C to <2 x i64>
ret <2 x i64> %D ret <2 x i64> %D
} }
define <2 x i64> @test13(<2 x i64> %A, <2 x i64> %B) nounwind { define <2 x i64> @test13(<2 x i64> %A, <2 x i64> %B) nounwind {
; CHECK-LABEL: test13: ; CHECK-LABEL: test13:
; CHECK: ## %bb.0: ; CHECK: ## %bb.0:
; CHECK-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648] ; CHECK-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
; CHECK-NEXT: pxor %xmm2, %xmm0
; CHECK-NEXT: pxor %xmm2, %xmm1 ; CHECK-NEXT: pxor %xmm2, %xmm1
; CHECK-NEXT: pxor %xmm2, %xmm0
; CHECK-NEXT: movdqa %xmm1, %xmm2 ; CHECK-NEXT: movdqa %xmm1, %xmm2
; CHECK-NEXT: pcmpgtd %xmm0, %xmm2
; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm2[0,0,2,2]
; CHECK-NEXT: pcmpeqd %xmm0, %xmm1 ; CHECK-NEXT: pcmpeqd %xmm0, %xmm1
; CHECK-NEXT: pcmpgtd %xmm0, %xmm2
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,3,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,3,3]
; CHECK-NEXT: pand %xmm3, %xmm0 ; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm2[0,0,2,2]
; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3]
; CHECK-NEXT: pand %xmm3, %xmm0
; CHECK-NEXT: por %xmm0, %xmm1 ; CHECK-NEXT: por %xmm0, %xmm1
; CHECK-NEXT: pcmpeqd %xmm0, %xmm0 ; CHECK-NEXT: pcmpeqd %xmm0, %xmm0
; CHECK-NEXT: pxor %xmm1, %xmm0 ; CHECK-NEXT: pxor %xmm1, %xmm0
; CHECK-NEXT: retl ; CHECK-NEXT: retl
%C = icmp uge <2 x i64> %A, %B %C = icmp uge <2 x i64> %A, %B
%D = sext <2 x i1> %C to <2 x i64> %D = sext <2 x i1> %C to <2 x i64>
ret <2 x i64> %D ret <2 x i64> %D
} }
define <2 x i64> @test14(<2 x i64> %A, <2 x i64> %B) nounwind { define <2 x i64> @test14(<2 x i64> %A, <2 x i64> %B) nounwind {
; CHECK-LABEL: test14: ; CHECK-LABEL: test14:
; CHECK: ## %bb.0: ; CHECK: ## %bb.0:
; CHECK-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648] ; CHECK-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
; CHECK-NEXT: pxor %xmm2, %xmm1
; CHECK-NEXT: pxor %xmm2, %xmm0 ; CHECK-NEXT: pxor %xmm2, %xmm0
; CHECK-NEXT: pxor %xmm2, %xmm1
; CHECK-NEXT: movdqa %xmm0, %xmm2 ; CHECK-NEXT: movdqa %xmm0, %xmm2
; CHECK-NEXT: pcmpgtd %xmm1, %xmm2
; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm2[0,0,2,2]
; CHECK-NEXT: pcmpeqd %xmm1, %xmm0 ; CHECK-NEXT: pcmpeqd %xmm1, %xmm0
; CHECK-NEXT: pcmpgtd %xmm1, %xmm2
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
; CHECK-NEXT: pand %xmm3, %xmm0 ; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm2[0,0,2,2]
; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3]
; CHECK-NEXT: pand %xmm3, %xmm0
; CHECK-NEXT: por %xmm0, %xmm1 ; CHECK-NEXT: por %xmm0, %xmm1
; CHECK-NEXT: pcmpeqd %xmm0, %xmm0 ; CHECK-NEXT: pcmpeqd %xmm0, %xmm0
; CHECK-NEXT: pxor %xmm1, %xmm0 ; CHECK-NEXT: pxor %xmm1, %xmm0
; CHECK-NEXT: retl ; CHECK-NEXT: retl
%C = icmp ule <2 x i64> %A, %B %C = icmp ule <2 x i64> %A, %B
%D = sext <2 x i1> %C to <2 x i64> %D = sext <2 x i1> %C to <2 x i64>
ret <2 x i64> %D ret <2 x i64> %D
} }

llvm/test/CodeGen/X86/vector-gep.ll

Show First 20 Lines • Show All 42 Lines • ▼ Show 20 Lines; CHECK-NEXT: retl
ret i32 %v ret i32 %v
} }
define <4 x i32*> @AGEP3(<4 x i32*> %param, <4 x i32> %off) nounwind { define <4 x i32*> @AGEP3(<4 x i32*> %param, <4 x i32> %off) nounwind {
; CHECK-LABEL: AGEP3: ; CHECK-LABEL: AGEP3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: pushl %eax ; CHECK-NEXT: pushl %eax
; CHECK-NEXT: vpslld $2, %xmm1, %xmm1 ; CHECK-NEXT: vpslld $2, %xmm1, %xmm1
; CHECK-NEXT: vpaddd %xmm1, %xmm0, %xmm0
; CHECK-NEXT: movl %esp, %eax ; CHECK-NEXT: movl %esp, %eax
; CHECK-NEXT: vpaddd %xmm1, %xmm0, %xmm0
; CHECK-NEXT: vpinsrd $3, %eax, %xmm0, %xmm0 ; CHECK-NEXT: vpinsrd $3, %eax, %xmm0, %xmm0
; CHECK-NEXT: popl %eax ; CHECK-NEXT: popl %eax
; CHECK-NEXT: retl ; CHECK-NEXT: retl
%A2 = getelementptr i32, <4 x i32*> %param, <4 x i32> %off %A2 = getelementptr i32, <4 x i32*> %param, <4 x i32> %off
%v = alloca i32 %v = alloca i32
%k = insertelement <4 x i32*> %A2, i32* %v, i32 3 %k = insertelement <4 x i32*> %A2, i32* %v, i32 3
ret <4 x i32*> %k ret <4 x i32*> %k
} }
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines; CHECK-NEXT: retl
ret <4 x i8*> %A ret <4 x i8*> %A
} }
define <4 x i16*> @AGEP8(i16* %param, <4 x i32> %off) nounwind { define <4 x i16*> @AGEP8(i16* %param, <4 x i32> %off) nounwind {
; Multiply offset by two (add it to itself). ; Multiply offset by two (add it to itself).
; add the base to the offset ; add the base to the offset
; CHECK-LABEL: AGEP8: ; CHECK-LABEL: AGEP8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vpaddd %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vbroadcastss {{[0-9]+}}(%esp), %xmm1 ; CHECK-NEXT: vbroadcastss {{[0-9]+}}(%esp), %xmm1
; CHECK-NEXT: vpaddd %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retl ; CHECK-NEXT: retl
%A = getelementptr i16, i16* %param, <4 x i32> %off %A = getelementptr i16, i16* %param, <4 x i32> %off
ret <4 x i16*> %A ret <4 x i16*> %A
} }
define <64 x i16*> @AGEP9(i16* %param, <64 x i32> %off) nounwind { define <64 x i16*> @AGEP9(i16* %param, <64 x i32> %off) nounwind {
; CHECK-LABEL: AGEP9: ; CHECK-LABEL: AGEP9:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: pushl %ebp ; CHECK-NEXT: pushl %ebp
; CHECK-NEXT: movl %esp, %ebp ; CHECK-NEXT: movl %esp, %ebp
; CHECK-NEXT: andl $-32, %esp ; CHECK-NEXT: andl $-32, %esp
; CHECK-NEXT: subl $160, %esp ; CHECK-NEXT: subl $160, %esp
; CHECK-NEXT: vpaddd %xmm0, %xmm0, %xmm3
; CHECK-NEXT: vbroadcastss 12(%ebp), %xmm5 ; CHECK-NEXT: vbroadcastss 12(%ebp), %xmm5
; CHECK-NEXT: vpaddd %xmm3, %xmm5, %xmm3 ; CHECK-NEXT: vpaddd %xmm0, %xmm0, %xmm3
; CHECK-NEXT: vmovdqa %xmm3, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0 ; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm0
; CHECK-NEXT: vmovdqa 88(%ebp), %xmm4
; CHECK-NEXT: vmovdqa 120(%ebp), %xmm6
; CHECK-NEXT: vmovdqa 152(%ebp), %xmm7
; CHECK-NEXT: movl 8(%ebp), %eax
; CHECK-NEXT: vpaddd %xmm0, %xmm0, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vpaddd %xmm0, %xmm5, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm5, %xmm0
; CHECK-NEXT: vpaddd %xmm3, %xmm5, %xmm3
; CHECK-NEXT: vpaddd %xmm4, %xmm4, %xmm4
; CHECK-NEXT: vpaddd %xmm6, %xmm6, %xmm6
; CHECK-NEXT: vpaddd %xmm7, %xmm7, %xmm7
; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vpaddd %xmm1, %xmm1, %xmm0 ; CHECK-NEXT: vpaddd %xmm1, %xmm1, %xmm0
; CHECK-NEXT: vmovdqa %xmm3, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vmovdqa 72(%ebp), %xmm3
; CHECK-NEXT: vpaddd %xmm4, %xmm5, %xmm4
; CHECK-NEXT: vpaddd %xmm6, %xmm5, %xmm6
; CHECK-NEXT: vpaddd %xmm7, %xmm5, %xmm7
; CHECK-NEXT: vpaddd %xmm0, %xmm5, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm5, %xmm0
; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vextractf128 $1, %ymm1, %xmm0 ; CHECK-NEXT: vextractf128 $1, %ymm1, %xmm0
; CHECK-NEXT: vmovdqa 104(%ebp), %xmm1
; CHECK-NEXT: vpaddd %xmm0, %xmm0, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vpaddd %xmm0, %xmm5, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm5, %xmm0
; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vpaddd %xmm2, %xmm2, %xmm0 ; CHECK-NEXT: vpaddd %xmm2, %xmm2, %xmm0
; CHECK-NEXT: vpaddd %xmm0, %xmm5, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm5, %xmm0
; CHECK-NEXT: vpaddd %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vextractf128 $1, %ymm2, %xmm0 ; CHECK-NEXT: vextractf128 $1, %ymm2, %xmm0
; CHECK-NEXT: vmovdqa 136(%ebp), %xmm2
; CHECK-NEXT: vpaddd %xmm0, %xmm0, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vpaddd %xmm1, %xmm1, %xmm1
; CHECK-NEXT: vpaddd %xmm0, %xmm5, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm5, %xmm0
; CHECK-NEXT: vpaddd %xmm1, %xmm5, %xmm1
; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vmovdqa 40(%ebp), %xmm0 ; CHECK-NEXT: vmovdqa 40(%ebp), %xmm0
; CHECK-NEXT: vpaddd %xmm2, %xmm2, %xmm2
; CHECK-NEXT: vpaddd %xmm2, %xmm5, %xmm2
; CHECK-NEXT: vpaddd %xmm0, %xmm0, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vpaddd %xmm0, %xmm5, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm5, %xmm0
; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vmovdqa 56(%ebp), %xmm0 ; CHECK-NEXT: vmovdqa 56(%ebp), %xmm0
; CHECK-NEXT: vpaddd %xmm0, %xmm0, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vpaddd %xmm0, %xmm5, %xmm0 ; CHECK-NEXT: vpaddd %xmm0, %xmm5, %xmm0
; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill ; CHECK-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
; CHECK-NEXT: vmovdqa 72(%ebp), %xmm3
; CHECK-NEXT: vpaddd %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vpaddd %xmm3, %xmm5, %xmm0 ; CHECK-NEXT: vpaddd %xmm3, %xmm5, %xmm0
; CHECK-NEXT: vmovdqa 184(%ebp), %xmm3
; CHECK-NEXT: vmovdqa %xmm0, (%esp) # 16-byte Spill ; CHECK-NEXT: vmovdqa %xmm0, (%esp) # 16-byte Spill
; CHECK-NEXT: vmovdqa 88(%ebp), %xmm4
; CHECK-NEXT: vpaddd %xmm4, %xmm4, %xmm4
; CHECK-NEXT: vpaddd %xmm4, %xmm5, %xmm4
; CHECK-NEXT: vmovdqa 104(%ebp), %xmm1
; CHECK-NEXT: vpaddd %xmm1, %xmm1, %xmm1
; CHECK-NEXT: vpaddd %xmm1, %xmm5, %xmm1
; CHECK-NEXT: vmovdqa 120(%ebp), %xmm6
; CHECK-NEXT: vpaddd %xmm6, %xmm6, %xmm6
; CHECK-NEXT: vpaddd %xmm6, %xmm5, %xmm6
; CHECK-NEXT: vmovdqa 136(%ebp), %xmm2
; CHECK-NEXT: vpaddd %xmm2, %xmm2, %xmm2
; CHECK-NEXT: vpaddd %xmm2, %xmm5, %xmm2
; CHECK-NEXT: vmovdqa 152(%ebp), %xmm7
; CHECK-NEXT: vpaddd %xmm7, %xmm7, %xmm7
; CHECK-NEXT: vpaddd %xmm7, %xmm5, %xmm7
; CHECK-NEXT: vmovdqa 168(%ebp), %xmm0 ; CHECK-NEXT: vmovdqa 168(%ebp), %xmm0
; CHECK-NEXT: vpaddd %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vpaddd %xmm0, %xmm5, %xmm0
; CHECK-NEXT: vmovdqa 184(%ebp), %xmm3
; CHECK-NEXT: vpaddd %xmm3, %xmm3, %xmm3 ; CHECK-NEXT: vpaddd %xmm3, %xmm3, %xmm3
; CHECK-NEXT: vpaddd %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vpaddd %xmm3, %xmm5, %xmm3 ; CHECK-NEXT: vpaddd %xmm3, %xmm5, %xmm3
; CHECK-NEXT: movl 8(%ebp), %eax ; CHECK-NEXT: vpaddd %xmm0, %xmm5, %xmm0
; CHECK-NEXT: vmovdqa %xmm3, 240(%eax) ; CHECK-NEXT: vmovdqa %xmm3, 240(%eax)
; CHECK-NEXT: vmovdqa %xmm0, 224(%eax) ; CHECK-NEXT: vmovdqa %xmm0, 224(%eax)
; CHECK-NEXT: vmovdqa %xmm7, 208(%eax) ; CHECK-NEXT: vmovdqa %xmm7, 208(%eax)
; CHECK-NEXT: vmovdqa %xmm2, 192(%eax) ; CHECK-NEXT: vmovdqa %xmm2, 192(%eax)
; CHECK-NEXT: vmovdqa %xmm6, 176(%eax) ; CHECK-NEXT: vmovdqa %xmm6, 176(%eax)
; CHECK-NEXT: vmovdqa %xmm1, 160(%eax) ; CHECK-NEXT: vmovdqa %xmm1, 160(%eax)
; CHECK-NEXT: vmovdqa %xmm4, 144(%eax) ; CHECK-NEXT: vmovdqa %xmm4, 144(%eax)
; CHECK-NEXT: vmovaps (%esp), %xmm0 # 16-byte Reload ; CHECK-NEXT: vmovaps (%esp), %xmm0 # 16-byte Reload
Show All 25 Lines

llvm/test/CodeGen/X86/vector-reduce-fadd-fast.ll

Show First 20 Lines • Show All 913 Lines • ▼ Show 20 Lines
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%1 = call fast double @llvm.experimental.vector.reduce.v2.fadd.f64.v8f64(double %a0, <8 x double> %a1) %1 = call fast double @llvm.experimental.vector.reduce.v2.fadd.f64.v8f64(double %a0, <8 x double> %a1)
ret double %1 ret double %1
} }
define double @test_v16f64(double %a0, <16 x double> %a1) { define double @test_v16f64(double %a0, <16 x double> %a1) {
; SSE-LABEL: test_v16f64: ; SSE-LABEL: test_v16f64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: addpd {{[0-9]+}}(%rsp), %xmm4
; SSE-NEXT: addpd %xmm6, %xmm2 ; SSE-NEXT: addpd %xmm6, %xmm2
; SSE-NEXT: addpd %xmm7, %xmm3 ; SSE-NEXT: addpd %xmm7, %xmm3
; SSE-NEXT: addpd %xmm5, %xmm1 ; SSE-NEXT: addpd %xmm5, %xmm1
; SSE-NEXT: addpd %xmm3, %xmm1 ; SSE-NEXT: addpd %xmm3, %xmm1
; SSE-NEXT: addpd {{[0-9]+}}(%rsp), %xmm4
; SSE-NEXT: addpd %xmm2, %xmm4 ; SSE-NEXT: addpd %xmm2, %xmm4
; SSE-NEXT: addpd %xmm1, %xmm4 ; SSE-NEXT: addpd %xmm1, %xmm4
; SSE-NEXT: movapd %xmm4, %xmm1 ; SSE-NEXT: movapd %xmm4, %xmm1
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm4[1] ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm4[1]
; SSE-NEXT: addsd %xmm4, %xmm1 ; SSE-NEXT: addsd %xmm4, %xmm1
; SSE-NEXT: addsd %xmm1, %xmm0 ; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
▲ Show 20 Lines • Show All 193 Lines • ▼ Show 20 Lines; AVX512-NEXT: retq
ret double %1 ret double %1
} }
define double @test_v16f64_zero(<16 x double> %a0) { define double @test_v16f64_zero(<16 x double> %a0) {
; SSE-LABEL: test_v16f64_zero: ; SSE-LABEL: test_v16f64_zero:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: addpd %xmm6, %xmm2 ; SSE-NEXT: addpd %xmm6, %xmm2
; SSE-NEXT: addpd %xmm4, %xmm0 ; SSE-NEXT: addpd %xmm4, %xmm0
; SSE-NEXT: addpd %xmm2, %xmm0
; SSE-NEXT: addpd %xmm7, %xmm3 ; SSE-NEXT: addpd %xmm7, %xmm3
; SSE-NEXT: addpd %xmm5, %xmm1 ; SSE-NEXT: addpd %xmm5, %xmm1
; SSE-NEXT: addpd %xmm2, %xmm0
; SSE-NEXT: addpd %xmm3, %xmm1 ; SSE-NEXT: addpd %xmm3, %xmm1
; SSE-NEXT: addpd %xmm0, %xmm1 ; SSE-NEXT: addpd %xmm0, %xmm1
; SSE-NEXT: movapd %xmm1, %xmm0 ; SSE-NEXT: movapd %xmm1, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1] ; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
; SSE-NEXT: addsd %xmm1, %xmm0 ; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-SLOW-LABEL: test_v16f64_zero: ; AVX1-SLOW-LABEL: test_v16f64_zero:
▲ Show 20 Lines • Show All 188 Lines • ▼ Show 20 Lines; AVX512-NEXT: retq
ret double %1 ret double %1
} }
define double @test_v16f64_undef(<16 x double> %a0) { define double @test_v16f64_undef(<16 x double> %a0) {
; SSE-LABEL: test_v16f64_undef: ; SSE-LABEL: test_v16f64_undef:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: addpd %xmm6, %xmm2 ; SSE-NEXT: addpd %xmm6, %xmm2
; SSE-NEXT: addpd %xmm4, %xmm0 ; SSE-NEXT: addpd %xmm4, %xmm0
; SSE-NEXT: addpd %xmm2, %xmm0
; SSE-NEXT: addpd %xmm7, %xmm3 ; SSE-NEXT: addpd %xmm7, %xmm3
; SSE-NEXT: addpd %xmm5, %xmm1 ; SSE-NEXT: addpd %xmm5, %xmm1
; SSE-NEXT: addpd %xmm2, %xmm0
; SSE-NEXT: addpd %xmm3, %xmm1 ; SSE-NEXT: addpd %xmm3, %xmm1
; SSE-NEXT: addpd %xmm0, %xmm1 ; SSE-NEXT: addpd %xmm0, %xmm1
; SSE-NEXT: movapd %xmm1, %xmm0 ; SSE-NEXT: movapd %xmm1, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1] ; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
; SSE-NEXT: addsd %xmm1, %xmm0 ; SSE-NEXT: addsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-SLOW-LABEL: test_v16f64_undef: ; AVX1-SLOW-LABEL: test_v16f64_undef:
▲ Show 20 Lines • Show All 58 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/vector-reduce-fmul-fast.ll

Show First 20 Lines • Show All 647 Lines • ▼ Show 20 Lines
; AVX512-NEXT: retq ; AVX512-NEXT: retq
%1 = call fast double @llvm.experimental.vector.reduce.v2.fmul.f64.v8f64(double %a0, <8 x double> %a1) %1 = call fast double @llvm.experimental.vector.reduce.v2.fmul.f64.v8f64(double %a0, <8 x double> %a1)
ret double %1 ret double %1
} }
define double @test_v16f64(double %a0, <16 x double> %a1) { define double @test_v16f64(double %a0, <16 x double> %a1) {
; SSE-LABEL: test_v16f64: ; SSE-LABEL: test_v16f64:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: mulpd {{[0-9]+}}(%rsp), %xmm4
; SSE-NEXT: mulpd %xmm6, %xmm2 ; SSE-NEXT: mulpd %xmm6, %xmm2
; SSE-NEXT: mulpd %xmm7, %xmm3 ; SSE-NEXT: mulpd %xmm7, %xmm3
; SSE-NEXT: mulpd %xmm5, %xmm1 ; SSE-NEXT: mulpd %xmm5, %xmm1
; SSE-NEXT: mulpd %xmm3, %xmm1 ; SSE-NEXT: mulpd %xmm3, %xmm1
; SSE-NEXT: mulpd {{[0-9]+}}(%rsp), %xmm4
; SSE-NEXT: mulpd %xmm2, %xmm4 ; SSE-NEXT: mulpd %xmm2, %xmm4
; SSE-NEXT: mulpd %xmm1, %xmm4 ; SSE-NEXT: mulpd %xmm1, %xmm4
; SSE-NEXT: movapd %xmm4, %xmm1 ; SSE-NEXT: movapd %xmm4, %xmm1
; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm4[1] ; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm4[1]
; SSE-NEXT: mulsd %xmm4, %xmm1 ; SSE-NEXT: mulsd %xmm4, %xmm1
; SSE-NEXT: mulsd %xmm1, %xmm0 ; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
▲ Show 20 Lines • Show All 121 Lines • ▼ Show 20 Lines; AVX512-NEXT: retq
ret double %1 ret double %1
} }
define double @test_v16f64_zero(<16 x double> %a0) { define double @test_v16f64_zero(<16 x double> %a0) {
; SSE-LABEL: test_v16f64_zero: ; SSE-LABEL: test_v16f64_zero:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: mulpd %xmm6, %xmm2 ; SSE-NEXT: mulpd %xmm6, %xmm2
; SSE-NEXT: mulpd %xmm4, %xmm0 ; SSE-NEXT: mulpd %xmm4, %xmm0
; SSE-NEXT: mulpd %xmm2, %xmm0
; SSE-NEXT: mulpd %xmm7, %xmm3 ; SSE-NEXT: mulpd %xmm7, %xmm3
; SSE-NEXT: mulpd %xmm5, %xmm1 ; SSE-NEXT: mulpd %xmm5, %xmm1
; SSE-NEXT: mulpd %xmm2, %xmm0
; SSE-NEXT: mulpd %xmm3, %xmm1 ; SSE-NEXT: mulpd %xmm3, %xmm1
; SSE-NEXT: mulpd %xmm0, %xmm1 ; SSE-NEXT: mulpd %xmm0, %xmm1
; SSE-NEXT: movapd %xmm1, %xmm0 ; SSE-NEXT: movapd %xmm1, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1] ; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
; SSE-NEXT: mulsd %xmm1, %xmm0 ; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: test_v16f64_zero: ; AVX-LABEL: test_v16f64_zero:
▲ Show 20 Lines • Show All 118 Lines • ▼ Show 20 Lines; AVX512-NEXT: retq
ret double %1 ret double %1
} }
define double @test_v16f64_undef(<16 x double> %a0) { define double @test_v16f64_undef(<16 x double> %a0) {
; SSE-LABEL: test_v16f64_undef: ; SSE-LABEL: test_v16f64_undef:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: mulpd %xmm6, %xmm2 ; SSE-NEXT: mulpd %xmm6, %xmm2
; SSE-NEXT: mulpd %xmm4, %xmm0 ; SSE-NEXT: mulpd %xmm4, %xmm0
; SSE-NEXT: mulpd %xmm2, %xmm0
; SSE-NEXT: mulpd %xmm7, %xmm3 ; SSE-NEXT: mulpd %xmm7, %xmm3
; SSE-NEXT: mulpd %xmm5, %xmm1 ; SSE-NEXT: mulpd %xmm5, %xmm1
; SSE-NEXT: mulpd %xmm2, %xmm0
; SSE-NEXT: mulpd %xmm3, %xmm1 ; SSE-NEXT: mulpd %xmm3, %xmm1
; SSE-NEXT: mulpd %xmm0, %xmm1 ; SSE-NEXT: mulpd %xmm0, %xmm1
; SSE-NEXT: movapd %xmm1, %xmm0 ; SSE-NEXT: movapd %xmm1, %xmm0
; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1] ; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
; SSE-NEXT: mulsd %xmm1, %xmm0 ; SSE-NEXT: mulsd %xmm1, %xmm0
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: test_v16f64_undef: ; AVX-LABEL: test_v16f64_undef:
Show All 35 Lines

llvm/test/CodeGen/X86/vector-shuffle-combining.ll

Show First 20 Lines • Show All 277 Lines • ▼ Show 20 Lines
; Verify that DAGCombiner moves the shuffle after the xor/and/or even if shuffles ; Verify that DAGCombiner moves the shuffle after the xor/and/or even if shuffles
; are not performing a swizzle operations. ; are not performing a swizzle operations.
define <4 x i32> @combine_bitwise_ops_test1b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { define <4 x i32> @combine_bitwise_ops_test1b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
; SSE2-LABEL: combine_bitwise_ops_test1b: ; SSE2-LABEL: combine_bitwise_ops_test1b:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: pand %xmm1, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,3,2,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,3,2,3]
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-LABEL: combine_bitwise_ops_test1b: ; SSSE3-LABEL: combine_bitwise_ops_test1b:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: pand %xmm1, %xmm0 ; SSSE3-NEXT: pand %xmm1, %xmm0
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,3,2,3] ; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,3,2,3]
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSSE3-NEXT: retq ; SSSE3-NEXT: retq
; ;
; SSE41-LABEL: combine_bitwise_ops_test1b: ; SSE41-LABEL: combine_bitwise_ops_test1b:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: andps %xmm1, %xmm0 ; SSE41-NEXT: andps %xmm1, %xmm0
; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3] ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: combine_bitwise_ops_test1b: ; AVX-LABEL: combine_bitwise_ops_test1b:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vandps %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vandps %xmm1, %xmm0, %xmm0
; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3] ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
; AVX-NEXT: retq ; AVX-NEXT: retq
%shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7> %shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
%shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7> %shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
%and = and <4 x i32> %shuf1, %shuf2 %and = and <4 x i32> %shuf1, %shuf2
ret <4 x i32> %and ret <4 x i32> %and
} }
define <4 x i32> @combine_bitwise_ops_test2b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { define <4 x i32> @combine_bitwise_ops_test2b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
; SSE2-LABEL: combine_bitwise_ops_test2b: ; SSE2-LABEL: combine_bitwise_ops_test2b:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: por %xmm1, %xmm0
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,3,2,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,3,2,3]
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-LABEL: combine_bitwise_ops_test2b: ; SSSE3-LABEL: combine_bitwise_ops_test2b:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: por %xmm1, %xmm0 ; SSSE3-NEXT: por %xmm1, %xmm0
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,3,2,3] ; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,3,2,3]
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSSE3-NEXT: retq ; SSSE3-NEXT: retq
; ;
; SSE41-LABEL: combine_bitwise_ops_test2b: ; SSE41-LABEL: combine_bitwise_ops_test2b:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: orps %xmm1, %xmm0 ; SSE41-NEXT: orps %xmm1, %xmm0
; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3] ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
; SSE41-NEXT: retq ; SSE41-NEXT: retq
▲ Show 20 Lines • Show All 1,210 Lines • ▼ Show 20 Lines; AVX-NEXT: retq
%2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 0, i32 5, i32 2, i32 3> %2 = shufflevector <4 x i32> %1, <4 x i32> %a, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
ret <4 x i32> %2 ret <4 x i32> %2
} }
define <4 x i32> @combine_test21(<8 x i32> %a, <4 x i32>* %ptr) { define <4 x i32> @combine_test21(<8 x i32> %a, <4 x i32>* %ptr) {
; SSE-LABEL: combine_test21: ; SSE-LABEL: combine_test21:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movaps %xmm0, %xmm2 ; SSE-NEXT: movaps %xmm0, %xmm2
; SSE-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm1[0]
; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1] ; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
; SSE-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm1[0]
; SSE-NEXT: movaps %xmm2, (%rdi) ; SSE-NEXT: movaps %xmm2, (%rdi)
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: combine_test21: ; AVX-LABEL: combine_test21:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX-NEXT: vmovlhps {{.*#+}} xmm2 = xmm0[0],xmm1[0] ; AVX-NEXT: vmovlhps {{.*#+}} xmm2 = xmm0[0],xmm1[0]
; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1] ; AVX-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
▲ Show 20 Lines • Show All 1,034 Lines • ▼ Show 20 Lines; AVX-NEXT: retq
%a0 = insertelement <4 x float> undef, float %f, i32 0 %a0 = insertelement <4 x float> undef, float %f, i32 0
%ret = shufflevector <4 x float> %a0, <4 x float> <float undef, float 4.0, float 5.0, float 3.0>, <4 x i32> <i32 0, i32 5, i32 6, i32 7> %ret = shufflevector <4 x float> %a0, <4 x float> <float undef, float 4.0, float 5.0, float 3.0>, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
ret <4 x float> %ret ret <4 x float> %ret
} }
define <4 x i32> @combine_constant_insertion_v4i32(i32 %f) { define <4 x i32> @combine_constant_insertion_v4i32(i32 %f) {
; SSE2-LABEL: combine_constant_insertion_v4i32: ; SSE2-LABEL: combine_constant_insertion_v4i32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movd %edi, %xmm1
; SSE2-NEXT: movaps {{.*#+}} xmm0 = <u,4,5,30> ; SSE2-NEXT: movaps {{.*#+}} xmm0 = <u,4,5,30>
; SSE2-NEXT: movd %edi, %xmm1
; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] ; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-LABEL: combine_constant_insertion_v4i32: ; SSSE3-LABEL: combine_constant_insertion_v4i32:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movd %edi, %xmm1
; SSSE3-NEXT: movaps {{.*#+}} xmm0 = <u,4,5,30> ; SSSE3-NEXT: movaps {{.*#+}} xmm0 = <u,4,5,30>
; SSSE3-NEXT: movd %edi, %xmm1
; SSSE3-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] ; SSSE3-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
; SSSE3-NEXT: retq ; SSSE3-NEXT: retq
; ;
; SSE41-LABEL: combine_constant_insertion_v4i32: ; SSE41-LABEL: combine_constant_insertion_v4i32:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movdqa {{.*#+}} xmm0 = <u,4,5,30> ; SSE41-NEXT: movdqa {{.*#+}} xmm0 = <u,4,5,30>
; SSE41-NEXT: pinsrd $0, %edi, %xmm0 ; SSE41-NEXT: pinsrd $0, %edi, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
▲ Show 20 Lines • Show All 235 Lines • ▼ Show 20 Lines; AVX2-FAST-NEXT: retq
%8 = insertelement <8 x i16> %7, i16 %a7, i32 7 %8 = insertelement <8 x i16> %7, i16 %a7, i32 7
ret <8 x i16> %8 ret <8 x i16> %8
} }
define <8 x i16> @shuffle_extract_insert_double(<8 x i16> %a, <8 x i16> %b) { define <8 x i16> @shuffle_extract_insert_double(<8 x i16> %a, <8 x i16> %b) {
; SSE2-LABEL: shuffle_extract_insert_double: ; SSE2-LABEL: shuffle_extract_insert_double:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,3,2,3,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,3,2,3,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,7,5,6,7]
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,1,3,2,4,5,6,7]
; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,7,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,6,7] ; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,6,7]
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,1,3,2,4,5,6,7]
; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[1,0,3,2,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[1,0,3,2,4,5,6,7]
; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-LABEL: shuffle_extract_insert_double: ; SSSE3-LABEL: shuffle_extract_insert_double:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: pshufb {{.*#+}} xmm1 = xmm1[0,1,6,7,10,11,14,15,u,u,u,u,u,u,u,u] ; SSSE3-NEXT: pshufb {{.*#+}} xmm1 = xmm1[0,1,6,7,10,11,14,15,u,u,u,u,u,u,u,u]
; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[4,5,0,1,12,13,8,9,u,u,u,u,u,u,u,u] ; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[4,5,0,1,12,13,8,9,u,u,u,u,u,u,u,u]
Show All 28 Lines; AVX-NEXT: retq
%7 = insertelement <8 x i16> %6, i16 %b15, i32 7 %7 = insertelement <8 x i16> %6, i16 %b15, i32 7
ret <8 x i16> %7 ret <8 x i16> %7
} }
define <8 x i16> @shuffle_extract_concat_insert(<4 x i16> %lhsa, <4 x i16> %rhsa, <8 x i16> %b) { define <8 x i16> @shuffle_extract_concat_insert(<4 x i16> %lhsa, <4 x i16> %rhsa, <8 x i16> %b) {
; SSE2-LABEL: shuffle_extract_concat_insert: ; SSE2-LABEL: shuffle_extract_concat_insert:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,6,7]
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[1,0,3,2,4,5,6,7]
; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm2[0,3,2,3,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm2[0,3,2,3,4,5,6,7]
; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,7,5,6,7] ; SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,7,5,6,7]
; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,6,7]
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,1,3,2,4,5,6,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,1,3,2,4,5,6,7]
; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[1,0,3,2,4,5,6,7]
; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-LABEL: shuffle_extract_concat_insert: ; SSSE3-LABEL: shuffle_extract_concat_insert:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[4,5,0,1,12,13,8,9,u,u,u,u,u,u,u,u] ; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[4,5,0,1,12,13,8,9,u,u,u,u,u,u,u,u]
; SSSE3-NEXT: pshufb {{.*#+}} xmm2 = xmm2[0,1,6,7,10,11,14,15,u,u,u,u,u,u,u,u] ; SSSE3-NEXT: pshufb {{.*#+}} xmm2 = xmm2[0,1,6,7,10,11,14,15,u,u,u,u,u,u,u,u]
; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3] ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
; SSSE3-NEXT: retq ; SSSE3-NEXT: retq
; ;
; SSE41-LABEL: shuffle_extract_concat_insert: ; SSE41-LABEL: shuffle_extract_concat_insert:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE41-NEXT: pshufb {{.*#+}} xmm0 = xmm0[4,5,0,1,12,13,8,9,u,u,u,u,u,u,u,u] ; SSE41-NEXT: pshufb {{.*#+}} xmm0 = xmm0[4,5,0,1,12,13,8,9,u,u,u,u,u,u,u,u]
; SSE41-NEXT: pshufb {{.*#+}} xmm2 = xmm2[0,1,6,7,10,11,14,15,u,u,u,u,u,u,u,u] ; SSE41-NEXT: pshufb {{.*#+}} xmm2 = xmm2[0,1,6,7,10,11,14,15,u,u,u,u,u,u,u,u]
; SSE41-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3] ; SSE41-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: shuffle_extract_concat_insert: ; AVX-LABEL: shuffle_extract_concat_insert:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[4,5,0,1,12,13,8,9,u,u,u,u,u,u,u,u] ; AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[4,5,0,1,12,13,8,9,u,u,u,u,u,u,u,u]
; AVX-NEXT: vpshufb {{.*#+}} xmm1 = xmm2[0,1,6,7,10,11,14,15,u,u,u,u,u,u,u,u] ; AVX-NEXT: vpshufb {{.*#+}} xmm2 = xmm2[0,1,6,7,10,11,14,15,u,u,u,u,u,u,u,u]
; AVX-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] ; AVX-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
; AVX-NEXT: retq ; AVX-NEXT: retq
%a = shufflevector <4 x i16> %lhsa, <4 x i16> %rhsa, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %a = shufflevector <4 x i16> %lhsa, <4 x i16> %rhsa, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%a0 = extractelement <8 x i16> %a, i32 0 %a0 = extractelement <8 x i16> %a, i32 0
%a4 = extractelement <8 x i16> %a, i32 4 %a4 = extractelement <8 x i16> %a, i32 4
%a6 = extractelement <8 x i16> %a, i32 6 %a6 = extractelement <8 x i16> %a, i32 6
%b11 = extractelement <8 x i16> %b, i32 3 %b11 = extractelement <8 x i16> %b, i32 3
%b13 = extractelement <8 x i16> %b, i32 5 %b13 = extractelement <8 x i16> %b, i32 5
%b15 = extractelement <8 x i16> %b, i32 7 %b15 = extractelement <8 x i16> %b, i32 7
%1 = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 2, i32 8, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> %1 = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 2, i32 8, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%2 = insertelement <8 x i16> %1, i16 %a0, i32 2 %2 = insertelement <8 x i16> %1, i16 %a0, i32 2
%3 = insertelement <8 x i16> %2, i16 %b11, i32 3 %3 = insertelement <8 x i16> %2, i16 %b11, i32 3
%4 = insertelement <8 x i16> %3, i16 %a6, i32 4 %4 = insertelement <8 x i16> %3, i16 %a6, i32 4
%5 = insertelement <8 x i16> %4, i16 %b13, i32 5 %5 = insertelement <8 x i16> %4, i16 %b13, i32 5
%6 = insertelement <8 x i16> %5, i16 %a4, i32 6 %6 = insertelement <8 x i16> %5, i16 %a4, i32 6
%7 = insertelement <8 x i16> %6, i16 %b15, i32 7 %7 = insertelement <8 x i16> %6, i16 %b15, i32 7
ret <8 x i16> %7 ret <8 x i16> %7
} }
define <8 x i16> @shuffle_scalar_to_vector_extract(<8 x i8>* %p0, i8* %p1, i8* %p2) { define <8 x i16> @shuffle_scalar_to_vector_extract(<8 x i8>* %p0, i8* %p1, i8* %p2) {
; SSE2-LABEL: shuffle_scalar_to_vector_extract: ; SSE2-LABEL: shuffle_scalar_to_vector_extract:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movq {{.*#+}} xmm0 = mem[0],zero ; SSE2-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
; SSE2-NEXT: movsbl (%rsi), %esi
; SSE2-NEXT: movsbl (%rdx), %ecx
; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
; SSE2-NEXT: movd %esi, %xmm0
; SSE2-NEXT: psraw $8, %xmm1 ; SSE2-NEXT: psraw $8, %xmm1
; SSE2-NEXT: pextrw $7, %xmm1, %eax ; SSE2-NEXT: pextrw $7, %xmm1, %eax
; SSE2-NEXT: movd %eax, %xmm2 ; SSE2-NEXT: movd %eax, %xmm2
; SSE2-NEXT: movsbl (%rsi), %eax
; SSE2-NEXT: movd %eax, %xmm0
; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
; SSE2-NEXT: movsbl (%rdx), %eax ; SSE2-NEXT: movd %ecx, %xmm0
; SSE2-NEXT: movd %eax, %xmm0
; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
; SSE2-NEXT: pxor %xmm0, %xmm0 ; SSE2-NEXT: pxor %xmm0, %xmm0
; SSE2-NEXT: punpckhwd {{.*#+}} xmm0 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] ; SSE2-NEXT: punpckhwd {{.*#+}} xmm0 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1] ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0] ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-LABEL: shuffle_scalar_to_vector_extract: ; SSSE3-LABEL: shuffle_scalar_to_vector_extract:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movq {{.*#+}} xmm0 = mem[0],zero ; SSSE3-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
; SSSE3-NEXT: movsbl (%rsi), %esi
; SSSE3-NEXT: movsbl (%rdx), %ecx
; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
; SSSE3-NEXT: movd %esi, %xmm0
; SSSE3-NEXT: psraw $8, %xmm1 ; SSSE3-NEXT: psraw $8, %xmm1
; SSSE3-NEXT: pextrw $7, %xmm1, %eax ; SSSE3-NEXT: pextrw $7, %xmm1, %eax
; SSSE3-NEXT: movd %eax, %xmm2 ; SSSE3-NEXT: movd %eax, %xmm2
; SSSE3-NEXT: movsbl (%rsi), %eax
; SSSE3-NEXT: movd %eax, %xmm0
; SSSE3-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3] ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
; SSSE3-NEXT: movsbl (%rdx), %eax ; SSSE3-NEXT: movd %ecx, %xmm0
; SSSE3-NEXT: movd %eax, %xmm0
; SSSE3-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1] ; SSSE3-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
; SSSE3-NEXT: pxor %xmm0, %xmm0 ; SSSE3-NEXT: pxor %xmm0, %xmm0
; SSSE3-NEXT: punpckhwd {{.*#+}} xmm0 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] ; SSSE3-NEXT: punpckhwd {{.*#+}} xmm0 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1] ; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0] ; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; SSSE3-NEXT: retq ; SSSE3-NEXT: retq
; ;
; SSE41-LABEL: shuffle_scalar_to_vector_extract: ; SSE41-LABEL: shuffle_scalar_to_vector_extract:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: pmovsxbw (%rdi), %xmm0 ; SSE41-NEXT: pmovsxbw (%rdi), %xmm0
; SSE41-NEXT: movsbl (%rsi), %esi
; SSE41-NEXT: pextrw $4, %xmm0, %eax ; SSE41-NEXT: pextrw $4, %xmm0, %eax
; SSE41-NEXT: pextrw $7, %xmm0, %ecx ; SSE41-NEXT: pextrw $7, %xmm0, %ecx
; SSE41-NEXT: pxor %xmm0, %xmm0 ; SSE41-NEXT: pxor %xmm0, %xmm0
; SSE41-NEXT: pinsrw $1, %eax, %xmm0 ; SSE41-NEXT: pinsrw $1, %eax, %xmm0
; SSE41-NEXT: movl $65531, %eax # imm = 0xFFFB ; SSE41-NEXT: movl $65531, %eax # imm = 0xFFFB
; SSE41-NEXT: pinsrw $2, %eax, %xmm0 ; SSE41-NEXT: pinsrw $2, %eax, %xmm0
; SSE41-NEXT: pinsrw $4, %ecx, %xmm0 ; SSE41-NEXT: pinsrw $4, %ecx, %xmm0
; SSE41-NEXT: movsbl (%rsi), %eax ; SSE41-NEXT: movsbl (%rdx), %ecx
; SSE41-NEXT: pinsrw $5, %eax, %xmm0 ; SSE41-NEXT: pinsrw $5, %esi, %xmm0
; SSE41-NEXT: movsbl (%rdx), %eax ; SSE41-NEXT: pinsrw $6, %ecx, %xmm0
; SSE41-NEXT: pinsrw $6, %eax, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: shuffle_scalar_to_vector_extract: ; AVX-LABEL: shuffle_scalar_to_vector_extract:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vpmovsxbw (%rdi), %xmm0 ; AVX-NEXT: vpmovsxbw (%rdi), %xmm0
; AVX-NEXT: movsbl (%rsi), %esi
; AVX-NEXT: vpextrw $4, %xmm0, %eax ; AVX-NEXT: vpextrw $4, %xmm0, %eax
; AVX-NEXT: vpextrw $7, %xmm0, %ecx ; AVX-NEXT: vpextrw $7, %xmm0, %ecx
; AVX-NEXT: vpxor %xmm0, %xmm0, %xmm0 ; AVX-NEXT: vpxor %xmm0, %xmm0, %xmm0
; AVX-NEXT: vpinsrw $1, %eax, %xmm0, %xmm0 ; AVX-NEXT: vpinsrw $1, %eax, %xmm0, %xmm0
; AVX-NEXT: movl $65531, %eax # imm = 0xFFFB ; AVX-NEXT: movl $65531, %eax # imm = 0xFFFB
; AVX-NEXT: vpinsrw $2, %eax, %xmm0, %xmm0 ; AVX-NEXT: vpinsrw $2, %eax, %xmm0, %xmm0
; AVX-NEXT: vpinsrw $4, %ecx, %xmm0, %xmm0 ; AVX-NEXT: vpinsrw $4, %ecx, %xmm0, %xmm0
; AVX-NEXT: movsbl (%rsi), %eax ; AVX-NEXT: movsbl (%rdx), %ecx
; AVX-NEXT: vpinsrw $5, %eax, %xmm0, %xmm0 ; AVX-NEXT: vpinsrw $5, %esi, %xmm0, %xmm0
; AVX-NEXT: movsbl (%rdx), %eax ; AVX-NEXT: vpinsrw $6, %ecx, %xmm0, %xmm0
; AVX-NEXT: vpinsrw $6, %eax, %xmm0, %xmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%tmp = load <8 x i8>, <8 x i8>* %p0, align 1 %tmp = load <8 x i8>, <8 x i8>* %p0, align 1
%tmp1 = sext <8 x i8> %tmp to <8 x i16> %tmp1 = sext <8 x i8> %tmp to <8 x i16>
%tmp2 = load i8, i8* %p1, align 1 %tmp2 = load i8, i8* %p1, align 1
%cvt1 = sext i8 %tmp2 to i16 %cvt1 = sext i8 %tmp2 to i16
%tmp3 = load i8, i8* %p2, align 1 %tmp3 = load i8, i8* %p2, align 1
%cvt2 = sext i8 %tmp3 to i16 %cvt2 = sext i8 %tmp3 to i16
%tmp4 = extractelement <8 x i16> %tmp1, i32 4 %tmp4 = extractelement <8 x i16> %tmp1, i32 4
%tmp5 = extractelement <8 x i16> %tmp1, i32 7 %tmp5 = extractelement <8 x i16> %tmp1, i32 7
%tmp6 = insertelement <8 x i16> <i16 undef, i16 undef, i16 -5, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef>, i16 undef, i32 0 %tmp6 = insertelement <8 x i16> <i16 undef, i16 undef, i16 -5, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef>, i16 undef, i32 0
%tmp7 = insertelement <8 x i16> %tmp6, i16 %tmp4, i32 1 %tmp7 = insertelement <8 x i16> %tmp6, i16 %tmp4, i32 1
%tmp8 = insertelement <8 x i16> %tmp7, i16 undef, i32 3 %tmp8 = insertelement <8 x i16> %tmp7, i16 undef, i32 3
%tmp9 = insertelement <8 x i16> %tmp8, i16 %tmp5, i32 4 %tmp9 = insertelement <8 x i16> %tmp8, i16 %tmp5, i32 4
%tmp10 = insertelement <8 x i16> %tmp9, i16 %cvt1, i32 5 %tmp10 = insertelement <8 x i16> %tmp9, i16 %cvt1, i32 5
%tmp11 = insertelement <8 x i16> %tmp10, i16 %cvt2, i32 6 %tmp11 = insertelement <8 x i16> %tmp10, i16 %cvt2, i32 6
%tmp12 = insertelement <8 x i16> %tmp11, i16 undef, i32 7 %tmp12 = insertelement <8 x i16> %tmp11, i16 undef, i32 7
%tmp13 = shufflevector <8 x i16> %tmp12, <8 x i16> undef, <8 x i32> <i32 0, i32 1, i32 10, i32 3, i32 4, i32 5, i32 6, i32 7> %tmp13 = shufflevector <8 x i16> %tmp12, <8 x i16> undef, <8 x i32> <i32 0, i32 1, i32 10, i32 3, i32 4, i32 5, i32 6, i32 7>
ret <8 x i16> %tmp13 ret <8 x i16> %tmp13
} }
define void @PR43024() { define void @PR43024() {
; SSE2-LABEL: PR43024: ; SSE2-LABEL: PR43024:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movaps {{.*#+}} xmm0 = [NaN,NaN,0.0E+0,0.0E+0] ; SSE2-NEXT: movaps {{.*#+}} xmm0 = [NaN,NaN,0.0E+0,0.0E+0]
; SSE2-NEXT: movaps %xmm0, (%rax)
; SSE2-NEXT: movaps %xmm0, %xmm1 ; SSE2-NEXT: movaps %xmm0, %xmm1
; SSE2-NEXT: movaps %xmm0, (%rax)
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[2,3] ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[2,3]
; SSE2-NEXT: addss %xmm0, %xmm1 ; SSE2-NEXT: addss %xmm0, %xmm1
; SSE2-NEXT: xorps %xmm0, %xmm0 ; SSE2-NEXT: xorps %xmm0, %xmm0
; SSE2-NEXT: addss %xmm0, %xmm1 ; SSE2-NEXT: addss %xmm0, %xmm1
; SSE2-NEXT: addss %xmm0, %xmm1 ; SSE2-NEXT: addss %xmm0, %xmm1
; SSE2-NEXT: movss %xmm1, (%rax) ; SSE2-NEXT: movss %xmm1, (%rax)
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-LABEL: PR43024: ; SSSE3-LABEL: PR43024:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movaps {{.*#+}} xmm0 = [NaN,NaN,0.0E+0,0.0E+0] ; SSSE3-NEXT: movaps {{.*#+}} xmm0 = [NaN,NaN,0.0E+0,0.0E+0]
; SSSE3-NEXT: movaps %xmm0, (%rax)
; SSSE3-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; SSSE3-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSSE3-NEXT: movaps %xmm0, (%rax)
; SSSE3-NEXT: addss %xmm0, %xmm1 ; SSSE3-NEXT: addss %xmm0, %xmm1
; SSSE3-NEXT: xorps %xmm0, %xmm0 ; SSSE3-NEXT: xorps %xmm0, %xmm0
; SSSE3-NEXT: addss %xmm0, %xmm1 ; SSSE3-NEXT: addss %xmm0, %xmm1
; SSSE3-NEXT: addss %xmm0, %xmm1 ; SSSE3-NEXT: addss %xmm0, %xmm1
; SSSE3-NEXT: movss %xmm1, (%rax) ; SSSE3-NEXT: movss %xmm1, (%rax)
; SSSE3-NEXT: retq ; SSSE3-NEXT: retq
; ;
; SSE41-LABEL: PR43024: ; SSE41-LABEL: PR43024:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movaps {{.*#+}} xmm0 = [NaN,NaN,0.0E+0,0.0E+0] ; SSE41-NEXT: movaps {{.*#+}} xmm0 = [NaN,NaN,0.0E+0,0.0E+0]
; SSE41-NEXT: movaps %xmm0, (%rax)
; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] ; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE41-NEXT: movaps %xmm0, (%rax)
; SSE41-NEXT: addss %xmm0, %xmm1 ; SSE41-NEXT: addss %xmm0, %xmm1
; SSE41-NEXT: xorps %xmm0, %xmm0 ; SSE41-NEXT: xorps %xmm0, %xmm0
; SSE41-NEXT: addss %xmm0, %xmm1 ; SSE41-NEXT: addss %xmm0, %xmm1
; SSE41-NEXT: addss %xmm0, %xmm1 ; SSE41-NEXT: addss %xmm0, %xmm1
; SSE41-NEXT: movss %xmm1, (%rax) ; SSE41-NEXT: movss %xmm1, (%rax)
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX-LABEL: PR43024: ; AVX-LABEL: PR43024:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [NaN,NaN,0.0E+0,0.0E+0] ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [NaN,NaN,0.0E+0,0.0E+0]
; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX-NEXT: vmovaps %xmm0, (%rax) ; AVX-NEXT: vmovaps %xmm0, (%rax)
; AVX-NEXT: vaddss {{\.LCPI.*}}+{{.*}}(%rip), %xmm0, %xmm0 ; AVX-NEXT: vaddss {{\.LCPI.*}}+{{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX-NEXT: vaddss %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vaddss %xmm1, %xmm0, %xmm0
; AVX-NEXT: vaddss {{\.LCPI.*}}+{{.*}}(%rip), %xmm0, %xmm0 ; AVX-NEXT: vaddss {{\.LCPI.*}}+{{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vmovss %xmm0, (%rax) ; AVX-NEXT: vmovss %xmm0, (%rax)
; AVX-NEXT: retq ; AVX-NEXT: retq
store <4 x float> <float 0x7FF8000000000000, float 0x7FF8000000000000, float 0x0, float 0x0>, <4 x float>* undef, align 16 store <4 x float> <float 0x7FF8000000000000, float 0x7FF8000000000000, float 0x0, float 0x0>, <4 x float>* undef, align 16
%1 = load <4 x float>, <4 x float>* undef, align 16 %1 = load <4 x float>, <4 x float>* undef, align 16
%2 = fmul <4 x float> %1, <float 0x0, float 0x0, float 0x0, float 0x0> %2 = fmul <4 x float> %1, <float 0x0, float 0x0, float 0x0, float 0x0>
%3 = shufflevector <4 x float> %2, <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef> %3 = shufflevector <4 x float> %2, <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
%4 = fadd <4 x float> %2, %3 %4 = fadd <4 x float> %2, %3
%5 = fadd <4 x float> zeroinitializer, %4 %5 = fadd <4 x float> zeroinitializer, %4
%6 = shufflevector <4 x float> %2, <4 x float> undef, <4 x i32> <i32 3, i32 undef, i32 undef, i32 undef> %6 = shufflevector <4 x float> %2, <4 x float> undef, <4 x i32> <i32 3, i32 undef, i32 undef, i32 undef>
%7 = fadd <4 x float> %6, %5 %7 = fadd <4 x float> %6, %5
%8 = extractelement <4 x float> %7, i32 0 %8 = extractelement <4 x float> %7, i32 0
store float %8, float* undef, align 8 store float %8, float* undef, align 8
ret void ret void
} }
define void @PR45604(<32 x i16>* %dst, <8 x i16>* %src) { define void @PR45604(<32 x i16>* %dst, <8 x i16>* %src) {
; SSE2-LABEL: PR45604: ; SSE2-LABEL: PR45604:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movdqa (%rsi), %xmm1 ; SSE2-NEXT: movdqa (%rsi), %xmm1
; SSE2-NEXT: movl $11, %r8d
; SSE2-NEXT: pextrw $2, %xmm1, %esi
; SSE2-NEXT: pextrw $3, %xmm1, %edx
; SSE2-NEXT: movd %xmm1, %eax ; SSE2-NEXT: movd %xmm1, %eax
; SSE2-NEXT: pextrw $1, %xmm1, %ecx
; SSE2-NEXT: movzwl %ax, %eax ; SSE2-NEXT: movzwl %ax, %eax
; SSE2-NEXT: movd %esi, %xmm2
; SSE2-NEXT: pextrw $4, %xmm1, %esi
; SSE2-NEXT: movd %eax, %xmm0 ; SSE2-NEXT: movd %eax, %xmm0
; SSE2-NEXT: movl $11, %eax ; SSE2-NEXT: pinsrw $2, %r8d, %xmm2
; SSE2-NEXT: pinsrw $2, %eax, %xmm0 ; SSE2-NEXT: pinsrw $2, %r8d, %xmm0
; SSE2-NEXT: pextrw $1, %xmm1, %ecx ; SSE2-NEXT: pinsrw $4, %edx, %xmm2
; SSE2-NEXT: movd %esi, %xmm3
; SSE2-NEXT: pextrw $6, %xmm1, %esi
; SSE2-NEXT: pextrw $5, %xmm1, %edx
; SSE2-NEXT: pinsrw $4, %ecx, %xmm0 ; SSE2-NEXT: pinsrw $4, %ecx, %xmm0
; SSE2-NEXT: pinsrw $6, %eax, %xmm0 ; SSE2-NEXT: pinsrw $2, %r8d, %xmm3
; SSE2-NEXT: pextrw $2, %xmm1, %ecx ; SSE2-NEXT: pinsrw $6, %r8d, %xmm0
; SSE2-NEXT: movd %ecx, %xmm2 ; SSE2-NEXT: pinsrw $6, %r8d, %xmm2
; SSE2-NEXT: pinsrw $2, %eax, %xmm2 ; SSE2-NEXT: pinsrw $4, %edx, %xmm3
; SSE2-NEXT: pextrw $3, %xmm1, %ecx ; SSE2-NEXT: movd %esi, %xmm4
; SSE2-NEXT: pinsrw $4, %ecx, %xmm2 ; SSE2-NEXT: pextrw $7, %xmm1, %edx
; SSE2-NEXT: pinsrw $6, %eax, %xmm2 ; SSE2-NEXT: pinsrw $2, %r8d, %xmm4
; SSE2-NEXT: pextrw $4, %xmm1, %ecx
; SSE2-NEXT: movd %ecx, %xmm3
; SSE2-NEXT: pinsrw $2, %eax, %xmm3
; SSE2-NEXT: pextrw $5, %xmm1, %ecx
; SSE2-NEXT: pinsrw $4, %ecx, %xmm3
; SSE2-NEXT: pinsrw $6, %eax, %xmm3
; SSE2-NEXT: pextrw $6, %xmm1, %ecx
; SSE2-NEXT: movd %ecx, %xmm4
; SSE2-NEXT: pinsrw $2, %eax, %xmm4
; SSE2-NEXT: pextrw $7, %xmm1, %ecx
; SSE2-NEXT: pinsrw $4, %ecx, %xmm4
; SSE2-NEXT: pinsrw $6, %eax, %xmm4
; SSE2-NEXT: movdqa %xmm4, 48(%rdi)
; SSE2-NEXT: movdqa %xmm3, 32(%rdi)
; SSE2-NEXT: movdqa %xmm2, 16(%rdi) ; SSE2-NEXT: movdqa %xmm2, 16(%rdi)
; SSE2-NEXT: movdqa %xmm0, (%rdi) ; SSE2-NEXT: movdqa %xmm0, (%rdi)
; SSE2-NEXT: pinsrw $6, %r8d, %xmm3
; SSE2-NEXT: pinsrw $4, %edx, %xmm4
; SSE2-NEXT: movdqa %xmm3, 32(%rdi)
; SSE2-NEXT: pinsrw $6, %r8d, %xmm4
; SSE2-NEXT: movdqa %xmm4, 48(%rdi)
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-LABEL: PR45604: ; SSSE3-LABEL: PR45604:
; SSSE3: # %bb.0: ; SSSE3: # %bb.0:
; SSSE3-NEXT: movdqa (%rsi), %xmm1 ; SSSE3-NEXT: movdqa (%rsi), %xmm1
; SSSE3-NEXT: movl $11, %r8d
; SSSE3-NEXT: pextrw $2, %xmm1, %esi
; SSSE3-NEXT: pextrw $3, %xmm1, %edx
; SSSE3-NEXT: movd %xmm1, %eax ; SSSE3-NEXT: movd %xmm1, %eax
; SSSE3-NEXT: pextrw $1, %xmm1, %ecx
; SSSE3-NEXT: movzwl %ax, %eax ; SSSE3-NEXT: movzwl %ax, %eax
; SSSE3-NEXT: movd %esi, %xmm2
; SSSE3-NEXT: pextrw $4, %xmm1, %esi
; SSSE3-NEXT: movd %eax, %xmm0 ; SSSE3-NEXT: movd %eax, %xmm0
; SSSE3-NEXT: movl $11, %eax ; SSSE3-NEXT: pinsrw $2, %r8d, %xmm2
; SSSE3-NEXT: pinsrw $2, %eax, %xmm0 ; SSSE3-NEXT: pinsrw $2, %r8d, %xmm0
; SSSE3-NEXT: pextrw $1, %xmm1, %ecx ; SSSE3-NEXT: pinsrw $4, %edx, %xmm2
; SSSE3-NEXT: movd %esi, %xmm3
; SSSE3-NEXT: pextrw $6, %xmm1, %esi
; SSSE3-NEXT: pextrw $5, %xmm1, %edx
; SSSE3-NEXT: pinsrw $4, %ecx, %xmm0 ; SSSE3-NEXT: pinsrw $4, %ecx, %xmm0
; SSSE3-NEXT: pinsrw $6, %eax, %xmm0 ; SSSE3-NEXT: pinsrw $2, %r8d, %xmm3
; SSSE3-NEXT: pextrw $2, %xmm1, %ecx ; SSSE3-NEXT: pinsrw $6, %r8d, %xmm0
; SSSE3-NEXT: movd %ecx, %xmm2 ; SSSE3-NEXT: pinsrw $6, %r8d, %xmm2
; SSSE3-NEXT: pinsrw $2, %eax, %xmm2 ; SSSE3-NEXT: pinsrw $4, %edx, %xmm3
; SSSE3-NEXT: pextrw $3, %xmm1, %ecx ; SSSE3-NEXT: movd %esi, %xmm4
; SSSE3-NEXT: pinsrw $4, %ecx, %xmm2 ; SSSE3-NEXT: pextrw $7, %xmm1, %edx
; SSSE3-NEXT: pinsrw $6, %eax, %xmm2 ; SSSE3-NEXT: pinsrw $2, %r8d, %xmm4
; SSSE3-NEXT: pextrw $4, %xmm1, %ecx
; SSSE3-NEXT: movd %ecx, %xmm3
; SSSE3-NEXT: pinsrw $2, %eax, %xmm3
; SSSE3-NEXT: pextrw $5, %xmm1, %ecx
; SSSE3-NEXT: pinsrw $4, %ecx, %xmm3
; SSSE3-NEXT: pinsrw $6, %eax, %xmm3
; SSSE3-NEXT: pextrw $6, %xmm1, %ecx
; SSSE3-NEXT: movd %ecx, %xmm4
; SSSE3-NEXT: pinsrw $2, %eax, %xmm4
; SSSE3-NEXT: pextrw $7, %xmm1, %ecx
; SSSE3-NEXT: pinsrw $4, %ecx, %xmm4
; SSSE3-NEXT: pinsrw $6, %eax, %xmm4
; SSSE3-NEXT: movdqa %xmm4, 48(%rdi)
; SSSE3-NEXT: movdqa %xmm3, 32(%rdi)
; SSSE3-NEXT: movdqa %xmm2, 16(%rdi) ; SSSE3-NEXT: movdqa %xmm2, 16(%rdi)
; SSSE3-NEXT: movdqa %xmm0, (%rdi) ; SSSE3-NEXT: movdqa %xmm0, (%rdi)
; SSSE3-NEXT: pinsrw $6, %r8d, %xmm3
; SSSE3-NEXT: pinsrw $4, %edx, %xmm4
; SSSE3-NEXT: movdqa %xmm3, 32(%rdi)
; SSSE3-NEXT: pinsrw $6, %r8d, %xmm4
; SSSE3-NEXT: movdqa %xmm4, 48(%rdi)
; SSSE3-NEXT: retq ; SSSE3-NEXT: retq
; ;
; SSE41-LABEL: PR45604: ; SSE41-LABEL: PR45604:
; SSE41: # %bb.0: ; SSE41: # %bb.0:
; SSE41-NEXT: movdqa (%rsi), %xmm1 ; SSE41-NEXT: movdqa (%rsi), %xmm1
; SSE41-NEXT: movl $11, %r8d
; SSE41-NEXT: pxor %xmm4, %xmm4
; SSE41-NEXT: pextrw $4, %xmm1, %edx
; SSE41-NEXT: pextrw $2, %xmm1, %eax ; SSE41-NEXT: pextrw $2, %xmm1, %eax
; SSE41-NEXT: movd %eax, %xmm0 ; SSE41-NEXT: pextrw $5, %xmm1, %esi
; SSE41-NEXT: movl $11, %eax ; SSE41-NEXT: pblendw {{.*#+}} xmm4 = xmm1[0],xmm4[1,2,3,4,5,6,7]
; SSE41-NEXT: pinsrw $2, %eax, %xmm0
; SSE41-NEXT: pextrw $3, %xmm1, %ecx ; SSE41-NEXT: pextrw $3, %xmm1, %ecx
; SSE41-NEXT: pinsrw $2, %r8d, %xmm4
; SSE41-NEXT: movd %edx, %xmm2
; SSE41-NEXT: pextrw $6, %xmm1, %edx
; SSE41-NEXT: movd %eax, %xmm0
; SSE41-NEXT: pinsrw $2, %r8d, %xmm2
; SSE41-NEXT: pinsrw $2, %r8d, %xmm0
; SSE41-NEXT: pinsrw $4, %esi, %xmm2
; SSE41-NEXT: movd %edx, %xmm3
; SSE41-NEXT: pextrw $1, %xmm1, %edx
; SSE41-NEXT: pextrw $7, %xmm1, %esi
; SSE41-NEXT: pinsrw $4, %ecx, %xmm0 ; SSE41-NEXT: pinsrw $4, %ecx, %xmm0
; SSE41-NEXT: pinsrw $6, %eax, %xmm0 ; SSE41-NEXT: pinsrw $2, %r8d, %xmm3
; SSE41-NEXT: pextrw $4, %xmm1, %ecx ; SSE41-NEXT: pinsrw $6, %r8d, %xmm0
; SSE41-NEXT: movd %ecx, %xmm2 ; SSE41-NEXT: pinsrw $6, %r8d, %xmm2
; SSE41-NEXT: pinsrw $2, %eax, %xmm2 ; SSE41-NEXT: pinsrw $4, %esi, %xmm3
; SSE41-NEXT: pextrw $5, %xmm1, %ecx ; SSE41-NEXT: pinsrw $4, %edx, %xmm4
; SSE41-NEXT: pinsrw $4, %ecx, %xmm2
; SSE41-NEXT: pinsrw $6, %eax, %xmm2
; SSE41-NEXT: pextrw $6, %xmm1, %ecx
; SSE41-NEXT: movd %ecx, %xmm3
; SSE41-NEXT: pinsrw $2, %eax, %xmm3
; SSE41-NEXT: pextrw $7, %xmm1, %ecx
; SSE41-NEXT: pinsrw $4, %ecx, %xmm3
; SSE41-NEXT: pinsrw $6, %eax, %xmm3
; SSE41-NEXT: pxor %xmm4, %xmm4
; SSE41-NEXT: pblendw {{.*#+}} xmm4 = xmm1[0],xmm4[1,2,3,4,5,6,7]
; SSE41-NEXT: pinsrw $2, %eax, %xmm4
; SSE41-NEXT: pextrw $1, %xmm1, %ecx
; SSE41-NEXT: pinsrw $4, %ecx, %xmm4
; SSE41-NEXT: pinsrw $6, %eax, %xmm4
; SSE41-NEXT: movdqa %xmm4, (%rdi)
; SSE41-NEXT: movdqa %xmm3, 48(%rdi)
; SSE41-NEXT: movdqa %xmm2, 32(%rdi) ; SSE41-NEXT: movdqa %xmm2, 32(%rdi)
; SSE41-NEXT: movdqa %xmm0, 16(%rdi) ; SSE41-NEXT: movdqa %xmm0, 16(%rdi)
; SSE41-NEXT: pinsrw $6, %r8d, %xmm3
; SSE41-NEXT: pinsrw $6, %r8d, %xmm4
; SSE41-NEXT: movdqa %xmm4, (%rdi)
; SSE41-NEXT: movdqa %xmm3, 48(%rdi)
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-LABEL: PR45604: ; AVX1-LABEL: PR45604:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vmovdqa (%rsi), %xmm0 ; AVX1-NEXT: vmovdqa (%rsi), %xmm0
; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[3,1,2,3]
; AVX1-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [11,11,11,0,11,11,11,0] ; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [11,11,11,0,11,11,11,0]
; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7] ; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[3,1,2,3]
; AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[2,3,0,1] ; AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[2,3,0,1]
; AVX1-NEXT: vpmovzxwq {{.*#+}} xmm3 = xmm3[0],zero,zero,zero,xmm3[1],zero,zero,zero ; AVX1-NEXT: vpmovzxwq {{.*#+}} xmm3 = xmm3[0],zero,zero,zero,xmm3[1],zero,zero,zero
; AVX1-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
; AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm3[0,1],xmm2[2,3],xmm3[4,5],xmm2[6,7] ; AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm3[0,1],xmm2[2,3],xmm3[4,5],xmm2[6,7]
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm3, %ymm1 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm3, %ymm1
; AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,2,3] ; AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,2,3]
; AVX1-NEXT: vpmovzxwq {{.*#+}} xmm3 = xmm3[0],zero,zero,zero,xmm3[1],zero,zero,zero
; AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm3[0,1],xmm2[2,3],xmm3[4,5],xmm2[6,7]
; AVX1-NEXT: vpmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero ; AVX1-NEXT: vpmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero
; AVX1-NEXT: vpmovzxwq {{.*#+}} xmm3 = xmm3[0],zero,zero,zero,xmm3[1],zero,zero,zero
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7] ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
; AVX1-NEXT: vmovups %ymm1, 32(%rdi)
; AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm3[0,1],xmm2[2,3],xmm3[4,5],xmm2[6,7]
; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0
; AVX1-NEXT: vmovups %ymm0, (%rdi) ; AVX1-NEXT: vmovups %ymm0, (%rdi)
; AVX1-NEXT: vmovups %ymm1, 32(%rdi)
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-SLOW-LABEL: PR45604: ; AVX2-SLOW-LABEL: PR45604:
; AVX2-SLOW: # %bb.0: ; AVX2-SLOW: # %bb.0:
; AVX2-SLOW-NEXT: vmovdqa (%rsi), %xmm0
; AVX2-SLOW-NEXT: vmovdqa {{.*#+}} ymm1 = [11,11,11,11,11,11,11,11,0,0,0,0,0,0,0,0] ; AVX2-SLOW-NEXT: vmovdqa {{.*#+}} ymm1 = [11,11,11,11,11,11,11,11,0,0,0,0,0,0,0,0]
; AVX2-SLOW-NEXT: vpshuflw {{.*#+}} ymm2 = ymm1[0,2,1,3,4,5,6,7,8,10,9,11,12,13,14,15] ; AVX2-SLOW-NEXT: vmovdqa (%rsi), %xmm0
; AVX2-SLOW-NEXT: vpshufd {{.*#+}} ymm2 = ymm2[0,0,2,1,4,4,6,5]
; AVX2-SLOW-NEXT: vmovdqa {{.*#+}} ymm3 = <u,u,u,u,255,255,0,0,u,u,u,u,255,255,0,0,u,u,u,u,0,0,255,255,u,u,u,u,0,0,255,255> ; AVX2-SLOW-NEXT: vmovdqa {{.*#+}} ymm3 = <u,u,u,u,255,255,0,0,u,u,u,u,255,255,0,0,u,u,u,u,0,0,255,255,u,u,u,u,0,0,255,255>
; AVX2-SLOW-NEXT: vmovdqa {{.*#+}} ymm4 = [0,0,0,0,0,0,0,0,11,11,11,11,11,11,11,11] ; AVX2-SLOW-NEXT: vmovdqa {{.*#+}} ymm4 = [0,0,0,0,0,0,0,0,11,11,11,11,11,11,11,11]
; AVX2-SLOW-NEXT: vpblendvb %ymm3, %ymm2, %ymm4, %ymm2
; AVX2-SLOW-NEXT: vpshuflw {{.*#+}} ymm5 = ymm0[0,2,1,3,4,5,6,7,8,10,9,11,12,13,14,15]
; AVX2-SLOW-NEXT: vpshufd {{.*#+}} ymm5 = ymm5[0,1,1,3,4,5,5,7]
; AVX2-SLOW-NEXT: vpermq {{.*#+}} ymm6 = ymm0[2,3,0,1]
; AVX2-SLOW-NEXT: vpshuflw {{.*#+}} ymm7 = ymm6[2,0,3,1,4,5,6,7,10,8,11,9,12,13,14,15]
; AVX2-SLOW-NEXT: vpshufd {{.*#+}} ymm7 = ymm7[0,1,1,3,4,5,5,7]
; AVX2-SLOW-NEXT: vmovdqa {{.*#+}} ymm8 = <255,255,0,0,u,u,u,u,255,255,0,0,u,u,u,u,0,0,255,255,u,u,u,u,0,0,255,255,u,u,u,u> ; AVX2-SLOW-NEXT: vmovdqa {{.*#+}} ymm8 = <255,255,0,0,u,u,u,u,255,255,0,0,u,u,u,u,0,0,255,255,u,u,u,u,0,0,255,255,u,u,u,u>
; AVX2-SLOW-NEXT: vpblendvb %ymm8, %ymm5, %ymm7, %ymm5 ; AVX2-SLOW-NEXT: vpermq {{.*#+}} ymm6 = ymm0[2,3,0,1]
; AVX2-SLOW-NEXT: vpshuflw {{.*#+}} ymm5 = ymm0[0,2,1,3,4,5,6,7,8,10,9,11,12,13,14,15]
; AVX2-SLOW-NEXT: vpshufhw {{.*#+}} ymm0 = ymm0[0,1,2,3,4,6,5,7,8,9,10,11,12,14,13,15]
; AVX2-SLOW-NEXT: vpshuflw {{.*#+}} ymm2 = ymm1[0,2,1,3,4,5,6,7,8,10,9,11,12,13,14,15]
; AVX2-SLOW-NEXT: vpshufhw {{.*#+}} ymm1 = ymm1[0,1,2,3,4,6,5,7,8,9,10,11,12,14,13,15] ; AVX2-SLOW-NEXT: vpshufhw {{.*#+}} ymm1 = ymm1[0,1,2,3,4,6,5,7,8,9,10,11,12,14,13,15]
; AVX2-SLOW-NEXT: vpshuflw {{.*#+}} ymm7 = ymm6[2,0,3,1,4,5,6,7,10,8,11,9,12,13,14,15]
; AVX2-SLOW-NEXT: vpshufd {{.*#+}} ymm5 = ymm5[0,1,1,3,4,5,5,7]
; AVX2-SLOW-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[2,1,3,3,6,5,7,7]
; AVX2-SLOW-NEXT: vpshufd {{.*#+}} ymm2 = ymm2[0,0,2,1,4,4,6,5]
; AVX2-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,2,2,3,4,6,6,7] ; AVX2-SLOW-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,2,2,3,4,6,6,7]
; AVX2-SLOW-NEXT: vpshufd {{.*#+}} ymm7 = ymm7[0,1,1,3,4,5,5,7]
; AVX2-SLOW-NEXT: vpblendvb %ymm3, %ymm2, %ymm4, %ymm2
; AVX2-SLOW-NEXT: vpblendvb %ymm3, %ymm1, %ymm4, %ymm1 ; AVX2-SLOW-NEXT: vpblendvb %ymm3, %ymm1, %ymm4, %ymm1
; AVX2-SLOW-NEXT: vpshufhw {{.*#+}} ymm0 = ymm0[0,1,2,3,4,6,5,7,8,9,10,11,12,14,13,15]
; AVX2-SLOW-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[2,1,3,3,6,5,7,7]
; AVX2-SLOW-NEXT: vpshufhw {{.*#+}} ymm3 = ymm6[0,1,2,3,6,4,7,5,8,9,10,11,14,12,15,13] ; AVX2-SLOW-NEXT: vpshufhw {{.*#+}} ymm3 = ymm6[0,1,2,3,6,4,7,5,8,9,10,11,14,12,15,13]
; AVX2-SLOW-NEXT: vpblendvb %ymm8, %ymm5, %ymm7, %ymm5
; AVX2-SLOW-NEXT: vpshufd {{.*#+}} ymm3 = ymm3[2,1,3,3,6,5,7,7] ; AVX2-SLOW-NEXT: vpshufd {{.*#+}} ymm3 = ymm3[2,1,3,3,6,5,7,7]
; AVX2-SLOW-NEXT: vpblendvb %ymm8, %ymm0, %ymm3, %ymm0 ; AVX2-SLOW-NEXT: vpblendvb %ymm8, %ymm0, %ymm3, %ymm0
; AVX2-SLOW-NEXT: vpblendd {{.*#+}} ymm2 = ymm5[0],ymm2[1],ymm5[2],ymm2[3],ymm5[4],ymm2[5],ymm5[6],ymm2[7] ; AVX2-SLOW-NEXT: vpblendd {{.*#+}} ymm2 = ymm5[0],ymm2[1],ymm5[2],ymm2[3],ymm5[4],ymm2[5],ymm5[6],ymm2[7]
; AVX2-SLOW-NEXT: vmovdqu %ymm2, (%rdi)
; AVX2-SLOW-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7] ; AVX2-SLOW-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7]
; AVX2-SLOW-NEXT: vmovdqu %ymm0, 32(%rdi) ; AVX2-SLOW-NEXT: vmovdqu %ymm0, 32(%rdi)
; AVX2-SLOW-NEXT: vmovdqu %ymm2, (%rdi)
; AVX2-SLOW-NEXT: vzeroupper ; AVX2-SLOW-NEXT: vzeroupper
; AVX2-SLOW-NEXT: retq ; AVX2-SLOW-NEXT: retq
; ;
; AVX2-FAST-LABEL: PR45604: ; AVX2-FAST-LABEL: PR45604:
; AVX2-FAST: # %bb.0: ; AVX2-FAST: # %bb.0:
; AVX2-FAST-NEXT: vmovdqa (%rsi), %xmm0 ; AVX2-FAST-NEXT: vmovdqa (%rsi), %xmm0
; AVX2-FAST-NEXT: vmovdqa {{.*#+}} ymm4 = <u,u,u,u,255,255,0,0,u,u,u,u,255,255,0,0,u,u,u,u,0,0,255,255,u,u,u,u,0,0,255,255>
; AVX2-FAST-NEXT: vpshufb {{.*#+}} ymm1 = ymm0[0,1,4,5,u,u,u,u,2,3,6,7,u,u,u,u,16,17,20,21,u,u,u,u,18,19,22,23,u,u,u,u] ; AVX2-FAST-NEXT: vpshufb {{.*#+}} ymm1 = ymm0[0,1,4,5,u,u,u,u,2,3,6,7,u,u,u,u,16,17,20,21,u,u,u,u,18,19,22,23,u,u,u,u]
; AVX2-FAST-NEXT: vmovdqa {{.*#+}} ymm5 = [0,0,0,0,0,0,0,0,11,11,11,11,11,11,11,11]
; AVX2-FAST-NEXT: vpermq {{.*#+}} ymm2 = ymm0[2,3,0,1] ; AVX2-FAST-NEXT: vpermq {{.*#+}} ymm2 = ymm0[2,3,0,1]
; AVX2-FAST-NEXT: vpshufb {{.*#+}} ymm3 = ymm2[4,5,0,1,u,u,u,u,6,7,2,3,u,u,u,u,20,21,16,17,u,u,u,u,22,23,18,19,u,u,u,u] ; AVX2-FAST-NEXT: vpshufb {{.*#+}} ymm3 = ymm2[4,5,0,1,u,u,u,u,6,7,2,3,u,u,u,u,20,21,16,17,u,u,u,u,22,23,18,19,u,u,u,u]
; AVX2-FAST-NEXT: vmovdqa {{.*#+}} ymm4 = <u,u,u,u,255,255,0,0,u,u,u,u,255,255,0,0,u,u,u,u,0,0,255,255,u,u,u,u,0,0,255,255> ; AVX2-FAST-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[8,9,12,13,u,u,u,u,10,11,14,15,u,u,u,u,24,25,28,29,u,u,u,u,26,27,30,31,u,u,u,u]
; AVX2-FAST-NEXT: vmovdqa {{.*#+}} ymm5 = [0,0,0,0,0,0,0,0,11,11,11,11,11,11,11,11] ; AVX2-FAST-NEXT: vpshufb {{.*#+}} ymm2 = ymm2[12,13,8,9,u,u,u,u,14,15,10,11,u,u,u,u,28,29,24,25,u,u,u,u,30,31,26,27,u,u,u,u]
; AVX2-FAST-NEXT: vpblendvb %ymm4, {{.*}}(%rip), %ymm5, %ymm4 ; AVX2-FAST-NEXT: vpblendvb %ymm4, {{.*}}(%rip), %ymm5, %ymm4
; AVX2-FAST-NEXT: vmovdqa {{.*#+}} ymm5 = <255,255,0,0,u,u,u,u,255,255,0,0,u,u,u,u,0,0,255,255,u,u,u,u,0,0,255,255,u,u,u,u> ; AVX2-FAST-NEXT: vmovdqa {{.*#+}} ymm5 = <255,255,0,0,u,u,u,u,255,255,0,0,u,u,u,u,0,0,255,255,u,u,u,u,0,0,255,255,u,u,u,u>
; AVX2-FAST-NEXT: vpblendvb %ymm5, %ymm1, %ymm3, %ymm1 ; AVX2-FAST-NEXT: vpblendvb %ymm5, %ymm1, %ymm3, %ymm1
; AVX2-FAST-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[8,9,12,13,u,u,u,u,10,11,14,15,u,u,u,u,24,25,28,29,u,u,u,u,26,27,30,31,u,u,u,u]
; AVX2-FAST-NEXT: vpshufb {{.*#+}} ymm2 = ymm2[12,13,8,9,u,u,u,u,14,15,10,11,u,u,u,u,28,29,24,25,u,u,u,u,30,31,26,27,u,u,u,u]
; AVX2-FAST-NEXT: vpblendvb %ymm5, %ymm0, %ymm2, %ymm0 ; AVX2-FAST-NEXT: vpblendvb %ymm5, %ymm0, %ymm2, %ymm0
; AVX2-FAST-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0],ymm4[1],ymm1[2],ymm4[3],ymm1[4],ymm4[5],ymm1[6],ymm4[7] ; AVX2-FAST-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0],ymm4[1],ymm1[2],ymm4[3],ymm1[4],ymm4[5],ymm1[6],ymm4[7]
; AVX2-FAST-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0],ymm4[1],ymm0[2],ymm4[3],ymm0[4],ymm4[5],ymm0[6],ymm4[7] ; AVX2-FAST-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0],ymm4[1],ymm0[2],ymm4[3],ymm0[4],ymm4[5],ymm0[6],ymm4[7]
; AVX2-FAST-NEXT: vmovdqu %ymm0, 32(%rdi) ; AVX2-FAST-NEXT: vmovdqu %ymm0, 32(%rdi)
; AVX2-FAST-NEXT: vmovdqu %ymm1, (%rdi) ; AVX2-FAST-NEXT: vmovdqu %ymm1, (%rdi)
; AVX2-FAST-NEXT: vzeroupper ; AVX2-FAST-NEXT: vzeroupper
; AVX2-FAST-NEXT: retq ; AVX2-FAST-NEXT: retq
%v1 = load <8 x i16>, <8 x i16>* %src, align 16 %v1 = load <8 x i16>, <8 x i16>* %src, align 16
%v2 = shufflevector <8 x i16> %v1, <8 x i16> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %v2 = shufflevector <8 x i16> %v1, <8 x i16> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%v3 = shufflevector <16 x i16> %v2, <16 x i16> <i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, <32 x i32> <i32 0, i32 8, i32 16, i32 24, i32 1, i32 9, i32 17, i32 25, i32 2, i32 10, i32 18, i32 26, i32 3, i32 11, i32 19, i32 27, i32 4, i32 12, i32 20, i32 28, i32 5, i32 13, i32 21, i32 29, i32 6, i32 14, i32 22, i32 30, i32 7, i32 15, i32 23, i32 31> %v3 = shufflevector <16 x i16> %v2, <16 x i16> <i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, <32 x i32> <i32 0, i32 8, i32 16, i32 24, i32 1, i32 9, i32 17, i32 25, i32 2, i32 10, i32 18, i32 26, i32 3, i32 11, i32 19, i32 27, i32 4, i32 12, i32 20, i32 28, i32 5, i32 13, i32 21, i32 29, i32 6, i32 14, i32 22, i32 30, i32 7, i32 15, i32 23, i32 31>
store <32 x i16> %v3, <32 x i16>* %dst, align 16 store <32 x i16> %v3, <32 x i16>* %dst, align 16
ret void ret void
} }

llvm/test/CodeGen/X86/volatile-memstores-nooverlapping-load-stores.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i1 immarg) #1 declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i1 immarg) #1
define dso_local void @copy_7_bytes(i8* noalias nocapture, i8* noalias nocapture readonly) nounwind #0 { define dso_local void @copy_7_bytes(i8* noalias nocapture, i8* noalias nocapture readonly) nounwind #0 {
; CHECK-LABEL: copy_7_bytes: ; CHECK-LABEL: copy_7_bytes:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: movl (%rsi), %eax
; CHECK-NEXT: movl 3(%rsi), %ecx ; CHECK-NEXT: movl 3(%rsi), %ecx
; CHECK-NEXT: movl (%rsi), %eax
; CHECK-NEXT: movl %ecx, 3(%rdi) ; CHECK-NEXT: movl %ecx, 3(%rdi)
; CHECK-NEXT: movl %eax, (%rdi) ; CHECK-NEXT: movl %eax, (%rdi)
; CHECK-NEXT: retq ; CHECK-NEXT: retq
tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 1 %0, i8* align 1 %1, i64 7, i1 false) tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 1 %0, i8* align 1 %1, i64 7, i1 false)
ret void ret void
} }
define dso_local void @copy_7_bytes_volatile(i8* noalias nocapture, i8* noalias nocapture readonly) nounwind #0 { define dso_local void @copy_7_bytes_volatile(i8* noalias nocapture, i8* noalias nocapture readonly) nounwind #0 {
; CHECK-LABEL: copy_7_bytes_volatile: ; CHECK-LABEL: copy_7_bytes_volatile:
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llvm/test/CodeGen/X86/vsplit-and.ll

Show All 17 Lines; CHECK-NEXT: retq
%t2 = sext <2 x i1> %t1 to <2 x i64> %t2 = sext <2 x i1> %t1 to <2 x i64>
store <2 x i64> %t2, <2 x i64>* %dst store <2 x i64> %t2, <2 x i64>* %dst
ret void ret void
} }
define void @t2(<3 x i64>* %dst, <3 x i64> %src1, <3 x i64> %src2) nounwind readonly { define void @t2(<3 x i64>* %dst, <3 x i64> %src1, <3 x i64> %src2) nounwind readonly {
; CHECK-LABEL: t2: ; CHECK-LABEL: t2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: movq {{.*#+}} xmm3 = mem[0],zero
; CHECK-NEXT: movq %r9, %xmm1 ; CHECK-NEXT: movq %r9, %xmm1
; CHECK-NEXT: movq %r8, %xmm0 ; CHECK-NEXT: movq %r8, %xmm0
; CHECK-NEXT: movq %rsi, %xmm2
; CHECK-NEXT: pxor %xmm4, %xmm4
; CHECK-NEXT: pcmpeqd %xmm5, %xmm5
; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; CHECK-NEXT: movq %rdx, %xmm1 ; CHECK-NEXT: movq %rdx, %xmm1
; CHECK-NEXT: movq %rsi, %xmm2
; CHECK-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0] ; CHECK-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
; CHECK-NEXT: movq %rcx, %xmm1 ; CHECK-NEXT: movq %rcx, %xmm1
; CHECK-NEXT: movq {{.*#+}} xmm3 = mem[0],zero ; CHECK-NEXT: pcmpeqq %xmm4, %xmm0
; CHECK-NEXT: pxor %xmm4, %xmm4
; CHECK-NEXT: pcmpeqq %xmm4, %xmm1 ; CHECK-NEXT: pcmpeqq %xmm4, %xmm1
; CHECK-NEXT: pcmpeqd %xmm5, %xmm5
; CHECK-NEXT: pxor %xmm5, %xmm1
; CHECK-NEXT: pcmpeqq %xmm4, %xmm2 ; CHECK-NEXT: pcmpeqq %xmm4, %xmm2
; CHECK-NEXT: pxor %xmm5, %xmm0
; CHECK-NEXT: pxor %xmm5, %xmm1
; CHECK-NEXT: pxor %xmm5, %xmm2 ; CHECK-NEXT: pxor %xmm5, %xmm2
; CHECK-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm1[0,2] ; CHECK-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm1[0,2]
; CHECK-NEXT: pcmpeqq %xmm4, %xmm3 ; CHECK-NEXT: pcmpeqq %xmm4, %xmm3
; CHECK-NEXT: pxor %xmm5, %xmm3 ; CHECK-NEXT: pxor %xmm5, %xmm3
; CHECK-NEXT: pcmpeqq %xmm4, %xmm0
; CHECK-NEXT: pxor %xmm5, %xmm0
; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm3[0,2] ; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm3[0,2]
; CHECK-NEXT: andps %xmm2, %xmm0 ; CHECK-NEXT: andps %xmm2, %xmm0
; CHECK-NEXT: pmovzxdq {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero ; CHECK-NEXT: pmovzxdq {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero
; CHECK-NEXT: psllq $63, %xmm1
; CHECK-NEXT: psrad $31, %xmm1
; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,2,3,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
; CHECK-NEXT: psllq $63, %xmm1
; CHECK-NEXT: psllq $63, %xmm0 ; CHECK-NEXT: psllq $63, %xmm0
; CHECK-NEXT: psrad $31, %xmm1
; CHECK-NEXT: psrad $31, %xmm0 ; CHECK-NEXT: psrad $31, %xmm0
; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
; CHECK-NEXT: movq %xmm0, 16(%rdi) ; CHECK-NEXT: movq %xmm0, 16(%rdi)
; CHECK-NEXT: movdqa %xmm1, (%rdi) ; CHECK-NEXT: movdqa %xmm1, (%rdi)
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%cmp1 = icmp ne <3 x i64> %src1, zeroinitializer %cmp1 = icmp ne <3 x i64> %src1, zeroinitializer
%cmp2 = icmp ne <3 x i64> %src2, zeroinitializer %cmp2 = icmp ne <3 x i64> %src2, zeroinitializer
%t1 = and <3 x i1> %cmp1, %cmp2 %t1 = and <3 x i1> %cmp1, %cmp2
%t2 = sext <3 x i1> %t1 to <3 x i64> %t2 = sext <3 x i1> %t1 to <3 x i64>
store <3 x i64> %t2, <3 x i64>* %dst store <3 x i64> %t2, <3 x i64>* %dst
ret void ret void
} }

llvm/test/CodeGen/X86/x86-cmov-converter.ll

Show First 20 Lines • Show All 283 Lines • ▼ Show 20 Lines
;; %v2 = phi[%f1, %FalseMBB], [%f2, %MBB] ; For CMOV with OppCC switch ;; %v2 = phi[%f1, %FalseMBB], [%f2, %MBB] ; For CMOV with OppCC switch
;; ; true-value with false-value ;; ; true-value with false-value
;; ; Phi instruction cannot use ;; ; Phi instruction cannot use
;; ; previous Phi instruction result ;; ; previous Phi instruction result
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; CHECK-LABEL: Transform ; CHECK-LABEL: Transform
; CHECK-NOT: cmov ; CHECK-NOT: cmov
; CHECK: divl [[a:%[0-9a-z]*]] ; CHECK: movl %r8d, [[s2:%[0-9a-z]*]]
; CHECK: divl %r8d
; CHECK: movl $11, [[s1:%[0-9a-z]*]] ; CHECK: movl $11, [[s1:%[0-9a-z]*]]
; CHECK: movl [[a]], [[s2:%[0-9a-z]*]] ; CHECK: cmpl %r8d, %edx
; CHECK: cmpl [[a]], %edx
; CHECK: ja [[SinkBB:.*]] ; CHECK: ja [[SinkBB:.*]]
; CHECK: [[FalseBB:.*]]: ; CHECK: [[FalseBB:.*]]:
; CHECK: movl $22, [[s1]] ; CHECK: movl $22, [[s1]]
; CHECK: movl $22, [[s2]] ; CHECK: movl $22, [[s2]]
; CHECK: [[SinkBB]]: ; CHECK: [[SinkBB]]:
; CHECK: ja ; CHECK: ja
define void @Transform(i32 *%arr, i32 *%arr2, i32 %a, i32 %b, i32 %c, i32 %n) #0 { define void @Transform(i32 *%arr, i32 *%arr2, i32 %a, i32 %b, i32 %c, i32 %n) #0 {
▲ Show 20 Lines • Show All 183 Lines • Show Last 20 Lines

llvm/test/DebugInfo/COFF/fpo-stack-protect.ll

Show All 9 Lines
; CHECK: _ssp: # @ssp ; CHECK: _ssp: # @ssp
; CHECK: .cv_fpo_proc _ssp 4 ; CHECK: .cv_fpo_proc _ssp 4
; CHECK: pushl %esi ; CHECK: pushl %esi
; CHECK: .cv_fpo_pushreg %esi ; CHECK: .cv_fpo_pushreg %esi
; CHECK: subl $20, %esp ; CHECK: subl $20, %esp
; CHECK: .cv_fpo_stackalloc 20 ; CHECK: .cv_fpo_stackalloc 20
; CHECK: .cv_fpo_endprologue ; CHECK: .cv_fpo_endprologue
; CHECK: movl 28(%esp), %esi
; CHECK: ___security_cookie ; CHECK: ___security_cookie
; CHECK: movl 28(%esp), %esi
; CHECK: movl %esi, {{[0-9]*}}(%esp) ; CHECK: movl %esi, {{[0-9]*}}(%esp)
; CHECK: movl %esi, {{[0-9]*}}(%esp) ; CHECK: movl %esi, {{[0-9]*}}(%esp)
; CHECK: movl %esi, {{[0-9]*}}(%esp) ; CHECK: movl %esi, {{[0-9]*}}(%esp)
; CHECK: movl %esi, {{[0-9]*}}(%esp) ; CHECK: movl %esi, {{[0-9]*}}(%esp)
; CHECK: calll _escape ; CHECK: calll _escape
; CHECK: calll @__security_check_cookie@4 ; CHECK: calll @__security_check_cookie@4
; CHECK: movl %esi, %eax ; CHECK: movl %esi, %eax
; CHECK: addl $20, %esp ; CHECK: addl $20, %esp
; CHECK: popl %esi ; CHECK: popl %esi
; CHECK: retl ; CHECK: retl
; CHECK: Ltmp2: ; CHECK: Ltmp3:
; CHECK: .cv_fpo_endproc ; CHECK: .cv_fpo_endproc
; ModuleID = 't.c' ; ModuleID = 't.c'
source_filename = "t.c" source_filename = "t.c"
target datalayout = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" target datalayout = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"
target triple = "i386-pc-windows-msvc19.11.25508" target triple = "i386-pc-windows-msvc19.11.25508"
; Function Attrs: nounwind sspstrong ; Function Attrs: nounwind sspstrong
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llvm/test/DebugInfo/COFF/inlining.ll

Show First 20 Lines • Show All 164 Lines • ▼ Show 20 Lines
; OBJ: DisplayName: baz ; OBJ: DisplayName: baz
; OBJ: LinkageName: ?baz@@YAXXZ ; OBJ: LinkageName: ?baz@@YAXXZ
; OBJ: } ; OBJ: }
; OBJ: InlineSiteSym { ; OBJ: InlineSiteSym {
; OBJ: PtrParent: 0x0 ; OBJ: PtrParent: 0x0
; OBJ: PtrEnd: 0x0 ; OBJ: PtrEnd: 0x0
; OBJ: Inlinee: bar (0x1002) ; OBJ: Inlinee: bar (0x1002)
; OBJ: BinaryAnnotations [ ; OBJ: BinaryAnnotations [
; OBJ-NEXT: ChangeCodeOffsetAndLineOffset: {CodeOffset: 0x8, LineOffset: 1} ; OBJ-NEXT: ChangeCodeOffsetAndLineOffset: {CodeOffset: 0xA, LineOffset: 1}
; OBJ-NEXT: ChangeCodeOffsetAndLineOffset: {CodeOffset: 0x9, LineOffset: 1} ; OBJ-NEXT: ChangeCodeOffsetAndLineOffset: {CodeOffset: 0x7, LineOffset: 1}
; OBJ-NEXT: ChangeLineOffset: 1 ; OBJ-NEXT: ChangeLineOffset: 1
; OBJ-NEXT: ChangeCodeOffset: 0x14 ; OBJ-NEXT: ChangeCodeOffset: 0x14
; OBJ-NEXT: ChangeCodeLength: 0x7 ; OBJ-NEXT: ChangeCodeLength: 0x7
; OBJ: ] ; OBJ: ]
; OBJ: } ; OBJ: }
; OBJ: InlineSiteSym { ; OBJ: InlineSiteSym {
; OBJ: PtrParent: 0x0 ; OBJ: PtrParent: 0x0
; OBJ: PtrEnd: 0x0 ; OBJ: PtrEnd: 0x0
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llvm/test/DebugInfo/COFF/local-variables.ll

Show All 28 Lines
; ASM: # %bb.0: # %entry ; ASM: # %bb.0: # %entry
; ASM: subq $56, %rsp ; ASM: subq $56, %rsp
; ASM: movl %ecx, 52(%rsp) ; ASM: movl %ecx, 52(%rsp)
; ASM: [[prologue_end:\.Ltmp.*]]: ; ASM: [[prologue_end:\.Ltmp.*]]:
; ASM: .cv_loc 0 1 8 7 # t.cpp:8:7 ; ASM: .cv_loc 0 1 8 7 # t.cpp:8:7
; ASM: testl %ecx, %ecx ; ASM: testl %ecx, %ecx
; ASM: je .LBB0_2 ; ASM: je .LBB0_2
; ASM: # %bb.1: # %if.then ; ASM: # %bb.1: # %if.then
; ASM: [[if_start:\.Ltmp.*]]:
; ASM: .cv_loc 0 1 9 9 # t.cpp:9:9 ; ASM: .cv_loc 0 1 9 9 # t.cpp:9:9
; ASM: leaq 44(%rsp), %rcx
; ASM: [[if_start:\.Ltmp.*]]:
; ASM: movl $42, 40(%rsp) ; ASM: movl $42, 40(%rsp)
; ASM: [[inline_site1:\.Ltmp.*]]: ; ASM: [[inline_site1:\.Ltmp.*]]:
; ASM: .cv_inline_site_id 1 within 0 inlined_at 1 10 5 ; ASM: .cv_inline_site_id 1 within 0 inlined_at 1 10 5
; ASM: .cv_loc 1 1 4 7 # t.cpp:4:7 ; ASM: .cv_loc 1 1 4 7 # t.cpp:4:7
; ASM: movl $3, 44(%rsp) ; ASM: movl $3, 44(%rsp)
; ASM: leaq 44(%rsp), %rcx
; ASM: .cv_loc 1 1 5 3 # t.cpp:5:3 ; ASM: .cv_loc 1 1 5 3 # t.cpp:5:3
; ASM: callq capture ; ASM: callq capture
; ASM: leaq 40(%rsp), %rcx ; ASM: leaq 40(%rsp), %rcx
; ASM: jmp .LBB0_3 ; ASM: jmp .LBB0_3
; ASM: [[else_start:\.Ltmp.*]]: ; ASM: [[else_start:\.Ltmp.*]]:
; ASM: .LBB0_2: # %if.else ; ASM: .LBB0_2: # %if.else
; ASM: .cv_loc 0 1 13 9 # t.cpp:13:9 ; ASM: .cv_loc 0 1 13 9 # t.cpp:13:9
; ASM: leaq 48(%rsp), %rcx
; ASM: [[movl:\.Ltmp.*]]:
; ASM: movl $42, 36(%rsp) ; ASM: movl $42, 36(%rsp)
; ASM: [[inline_site2:\.Ltmp.*]]: ; ASM: [[inline_site2:\.Ltmp.*]]:
; ASM: .cv_inline_site_id 2 within 0 inlined_at 1 14 5 ; ASM: .cv_inline_site_id 2 within 0 inlined_at 1 14 5
; ASM: .cv_loc 2 1 4 7 # t.cpp:4:7 ; ASM: .cv_loc 2 1 4 7 # t.cpp:4:7
; ASM: movl $3, 48(%rsp) ; ASM: movl $3, 48(%rsp)
; ASM: leaq 48(%rsp), %rcx
; ASM: .cv_loc 2 1 5 3 # t.cpp:5:3 ; ASM: .cv_loc 2 1 5 3 # t.cpp:5:3
; ASM: callq capture ; ASM: callq capture
; ASM: leaq 36(%rsp), %rcx ; ASM: leaq 36(%rsp), %rcx
; ASM: [[else_end:\.Ltmp.*]]: ; ASM: [[else_end:\.Ltmp.*]]:
; ASM: .LBB0_3: # %if.end ; ASM: .LBB0_3: # %if.end
; ASM: .cv_loc 0 1 17 1 # t.cpp:17:1 ; ASM: .cv_loc 0 1 17 1 # t.cpp:17:1
; ASM: callq capture ; ASM: callq capture
; ASM: nop ; ASM: nop
Show All 10 Lines
; ASM: .long 116 # TypeIndex ; ASM: .long 116 # TypeIndex
; ASM: .short 0 # Flags ; ASM: .short 0 # Flags
; ASM: .asciz "a" ; ASM: .asciz "a"
; ASM: .cv_def_range [[if_start]] [[else_start]], frame_ptr_rel, 40 ; ASM: .cv_def_range [[if_start]] [[else_start]], frame_ptr_rel, 40
; ASM: .short 4414 # Record kind: S_LOCAL ; ASM: .short 4414 # Record kind: S_LOCAL
; ASM: .long 116 # TypeIndex ; ASM: .long 116 # TypeIndex
; ASM: .short 0 # Flags ; ASM: .short 0 # Flags
; ASM: .asciz "b" ; ASM: .asciz "b"
; ASM: .cv_def_range [[else_start]] [[else_end]], frame_ptr_rel, 36 ; ASM: .cv_def_range [[movl]] [[else_end]], frame_ptr_rel, 36
; ASM: .short 4429 # Record kind: S_INLINESITE ; ASM: .short 4429 # Record kind: S_INLINESITE
; ASM: .short 4414 # Record kind: S_LOCAL ; ASM: .short 4414 # Record kind: S_LOCAL
; ASM: .long 116 # TypeIndex ; ASM: .long 116 # TypeIndex
; ASM: .short 0 # Flags ; ASM: .short 0 # Flags
; ASM: .asciz "v" ; ASM: .asciz "v"
; ASM: .cv_def_range [[inline_site1]] [[else_start]], frame_ptr_rel, 44 ; ASM: .cv_def_range [[inline_site1]] [[else_start]], frame_ptr_rel, 44
; ASM: .short 4430 # Record kind: S_INLINESITE_END ; ASM: .short 4430 # Record kind: S_INLINESITE_END
; ASM: .short 4429 # Record kind: S_INLINESITE ; ASM: .short 4429 # Record kind: S_INLINESITE
Show All 29 Lines
; OBJ: Type: int (0x74) ; OBJ: Type: int (0x74)
; OBJ: Flags [ (0x0) ; OBJ: Flags [ (0x0)
; OBJ: ] ; OBJ: ]
; OBJ: VarName: a ; OBJ: VarName: a
; OBJ: } ; OBJ: }
; OBJ: DefRangeFramePointerRelSym { ; OBJ: DefRangeFramePointerRelSym {
; OBJ: Offset: 40 ; OBJ: Offset: 40
; OBJ: LocalVariableAddrRange { ; OBJ: LocalVariableAddrRange {
; OBJ: OffsetStart: .text+0xC ; OBJ: OffsetStart: .text+0x11
; OBJ: ISectStart: 0x0 ; OBJ: ISectStart: 0x0
; OBJ: Range: 0x21 ; OBJ: Range: 0x1C
; OBJ: } ; OBJ: }
; OBJ: } ; OBJ: }
; OBJ: LocalSym { ; OBJ: LocalSym {
; OBJ: Type: int (0x74) ; OBJ: Type: int (0x74)
; OBJ: Flags [ (0x0) ; OBJ: Flags [ (0x0)
; OBJ: ] ; OBJ: ]
; OBJ: VarName: b ; OBJ: VarName: b
; OBJ: } ; OBJ: }
; OBJ: DefRangeFramePointerRelSym { ; OBJ: DefRangeFramePointerRelSym {
; OBJ: Offset: 36 ; OBJ: Offset: 36
; OBJ: LocalVariableAddrRange { ; OBJ: LocalVariableAddrRange {
; OBJ: OffsetStart: .text+0x2D ; OBJ: OffsetStart: .text+0x32
; OBJ: ISectStart: 0x0 ; OBJ: ISectStart: 0x0
; OBJ: Range: 0x1F ; OBJ: Range: 0x1A
; OBJ: } ; OBJ: }
; OBJ: } ; OBJ: }
; OBJ: InlineSiteSym { ; OBJ: InlineSiteSym {
; OBJ: PtrParent: 0x0 ; OBJ: PtrParent: 0x0
; OBJ: PtrEnd: 0x0 ; OBJ: PtrEnd: 0x0
; OBJ: Inlinee: will_be_inlined (0x1002) ; OBJ: Inlinee: will_be_inlined (0x1002)
; OBJ: BinaryAnnotations [ ; OBJ: BinaryAnnotations [
; OBJ: ChangeLineOffset: 1 ; OBJ: ChangeLineOffset: 1
; OBJ: ChangeCodeOffset: 0x14 ; OBJ: ChangeCodeOffset: 0x19
; OBJ: ChangeCodeOffsetAndLineOffset: {CodeOffset: 0xD, LineOffset: 1} ; OBJ: ChangeCodeOffsetAndLineOffset: {CodeOffset: 0x8, LineOffset: 1}
; OBJ: ChangeCodeLength: 0xC ; OBJ: ChangeCodeLength: 0xC
; OBJ: ] ; OBJ: ]
; OBJ: } ; OBJ: }
; OBJ: LocalSym { ; OBJ: LocalSym {
; OBJ: Type: int (0x74) ; OBJ: Type: int (0x74)
; OBJ: Flags [ (0x0) ; OBJ: Flags [ (0x0)
; OBJ: ] ; OBJ: ]
; OBJ: VarName: v ; OBJ: VarName: v
; OBJ: } ; OBJ: }
; OBJ: DefRangeFramePointerRelSym { ; OBJ: DefRangeFramePointerRelSym {
; OBJ: Offset: 44 ; OBJ: Offset: 44
; OBJ: LocalVariableAddrRange { ; OBJ: LocalVariableAddrRange {
; OBJ: OffsetStart: .text+0x14 ; OBJ: OffsetStart: .text+0x19
; OBJ: ISectStart: 0x0 ; OBJ: ISectStart: 0x0
; OBJ: Range: 0x19 ; OBJ: Range: 0x14
; OBJ: } ; OBJ: }
; OBJ: } ; OBJ: }
; OBJ: InlineSiteEnd { ; OBJ: InlineSiteEnd {
; OBJ: } ; OBJ: }
; OBJ: InlineSiteSym { ; OBJ: InlineSiteSym {
; OBJ: PtrParent: 0x0 ; OBJ: PtrParent: 0x0
; OBJ: PtrEnd: 0x0 ; OBJ: PtrEnd: 0x0
; OBJ: Inlinee: will_be_inlined (0x1002) ; OBJ: Inlinee: will_be_inlined (0x1002)
; OBJ: BinaryAnnotations [ ; OBJ: BinaryAnnotations [
; OBJ: ChangeLineOffset: 1 ; OBJ: ChangeLineOffset: 1
; OBJ: ChangeCodeOffset: 0x35 ; OBJ: ChangeCodeOffset: 0x3A
; OBJ: ChangeCodeOffsetAndLineOffset: {CodeOffset: 0xD, LineOffset: 1} ; OBJ: ChangeCodeOffsetAndLineOffset: {CodeOffset: 0x8, LineOffset: 1}
; OBJ: ChangeCodeLength: 0xA ; OBJ: ChangeCodeLength: 0xA
; OBJ: ] ; OBJ: ]
; OBJ: } ; OBJ: }
; OBJ: LocalSym { ; OBJ: LocalSym {
; OBJ: Type: int (0x74) ; OBJ: Type: int (0x74)
; OBJ: Flags [ (0x0) ; OBJ: Flags [ (0x0)
; OBJ: ] ; OBJ: ]
; OBJ: VarName: v ; OBJ: VarName: v
; OBJ: } ; OBJ: }
; OBJ: DefRangeFramePointerRelSym { ; OBJ: DefRangeFramePointerRelSym {
; OBJ: Offset: 48 ; OBJ: Offset: 48
; OBJ: LocalVariableAddrRange { ; OBJ: LocalVariableAddrRange {
; OBJ: OffsetStart: .text+0x35 ; OBJ: OffsetStart: .text+0x3A
; OBJ: ISectStart: 0x0 ; OBJ: ISectStart: 0x0
; OBJ: Range: 0x17 ; OBJ: Range: 0x12
; OBJ: } ; OBJ: }
; OBJ: } ; OBJ: }
; OBJ: InlineSiteEnd { ; OBJ: InlineSiteEnd {
; OBJ: } ; OBJ: }
; OBJ: ProcEnd ; OBJ: ProcEnd
; OBJ: ] ; OBJ: ]
; ModuleID = 't.cpp' ; ModuleID = 't.cpp'
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llvm/test/DebugInfo/COFF/pieces.ll

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; ASM: [[oy_ox_start:\.Ltmp[0-9]+]]: ; ASM: [[oy_ox_start:\.Ltmp[0-9]+]]:
; ASM: .p2align 4, 0x90 ; ASM: .p2align 4, 0x90
; ASM: .LBB0_3: # %for.body ; ASM: .LBB0_3: # %for.body
; ASM: #DEBUG_VALUE: loop_csr:o <- [DW_OP_LLVM_fragment 0 32] $edi ; ASM: #DEBUG_VALUE: loop_csr:o <- [DW_OP_LLVM_fragment 0 32] $edi
; ASM: #DEBUG_VALUE: loop_csr:o <- [DW_OP_LLVM_fragment 32 32] $esi ; ASM: #DEBUG_VALUE: loop_csr:o <- [DW_OP_LLVM_fragment 32 32] $esi
; ASM: .cv_loc 0 1 13 11 # t.c:13:11 ; ASM: .cv_loc 0 1 13 11 # t.c:13:11
; ASM: movl %edi, %ecx ; ASM: movl %edi, %ecx
; ASM: callq g ; ASM: callq g
; ASM: movl %esi, %ecx
; ASM: movl %eax, %edi ; ASM: movl %eax, %edi
; ASM: [[ox_start:\.Ltmp[0-9]+]]: ; ASM: [[ox_start:\.Ltmp[0-9]+]]:
; ASM: #DEBUG_VALUE: loop_csr:o <- [DW_OP_LLVM_fragment 0 32] $edi ; ASM: #DEBUG_VALUE: loop_csr:o <- [DW_OP_LLVM_fragment 0 32] $edi
; ASM: .cv_loc 0 1 14 11 # t.c:14:11 ; ASM: .cv_loc 0 1 14 11 # t.c:14:11
; ASM: movl %esi, %ecx
; ASM: callq g ; ASM: callq g
; ASM: movl %eax, %esi ; ASM: movl %eax, %esi
; ASM: [[oy_start:\.Ltmp[0-9]+]]: ; ASM: [[oy_start:\.Ltmp[0-9]+]]:
; ASM: #DEBUG_VALUE: loop_csr:o <- [DW_OP_LLVM_fragment 32 32] $esi ; ASM: #DEBUG_VALUE: loop_csr:o <- [DW_OP_LLVM_fragment 32 32] $esi
; ASM: cmpl n(%rip), %eax ; ASM: cmpl n(%rip), %ecx
; ASM: jl .LBB0_3 ; ASM: jl .LBB0_3
; ASM: [[loopskip_start:\.Ltmp[0-9]+]]: ; ASM: [[loopskip_start:\.Ltmp[0-9]+]]:
; ASM: #DEBUG_VALUE: loop_csr:o <- [DW_OP_LLVM_fragment 0 32] 0 ; ASM: #DEBUG_VALUE: loop_csr:o <- [DW_OP_LLVM_fragment 0 32] 0
; ASM: xorl %esi, %esi ; ASM: xorl %esi, %esi
; ASM: xorl %edi, %edi ; ASM: xorl %edi, %edi
; ASM: [[oy_end:\.Ltmp[0-9]+]]: ; ASM: [[oy_end:\.Ltmp[0-9]+]]:
; ASM: addl %edi, %esi ; ASM: addl %edi, %esi
; ASM: movl %esi, %eax ; ASM: movl %esi, %eax
Show All 22 Lines
; ASM-LABEL: nested: # @nested ; ASM-LABEL: nested: # @nested
; ASM: #DEBUG_VALUE: nested:o <- [DW_OP_deref] [$rcx+0] ; ASM: #DEBUG_VALUE: nested:o <- [DW_OP_deref] [$rcx+0]
; ASM: movl 12(%rcx), %eax ; ASM: movl 12(%rcx), %eax
; ASM: [[p_start:\.Ltmp[0-9]+]]: ; ASM: [[p_start:\.Ltmp[0-9]+]]:
; ASM: #DEBUG_VALUE: nested:p <- [DW_OP_LLVM_fragment 32 32] $eax ; ASM: #DEBUG_VALUE: nested:p <- [DW_OP_LLVM_fragment 32 32] $eax
; ASM: retq ; ASM: retq
; ASM-LABEL: bitpiece_spill: # @bitpiece_spill ; ASM-LABEL: bitpiece_spill: # @bitpiece_spill
; ASM: #DEBUG_VALUE: bitpiece_spill:o <- [DW_OP_LLVM_fragment 0 32] 0
; ASM: xorl %ecx, %ecx ; ASM: xorl %ecx, %ecx
; ASM: #DEBUG_VALUE: bitpiece_spill:o <- [DW_OP_LLVM_fragment 0 32] 0
; ASM: callq g ; ASM: callq g
; ASM: movl %eax, [[offset_o_x:[0-9]+]](%rsp) # 4-byte Spill ; ASM: movl %eax, [[offset_o_x:[0-9]+]](%rsp) # 4-byte Spill
; ASM: [[spill_o_x_start:\.Ltmp[0-9]+]]: ; ASM: [[spill_o_x_start:\.Ltmp[0-9]+]]:
; ASM: #DEBUG_VALUE: bitpiece_spill:o <- [DW_OP_plus_uconst [[offset_o_x]], DW_OP_LLVM_fragment 32 32] [$rsp+0] ; ASM: #DEBUG_VALUE: bitpiece_spill:o <- [DW_OP_plus_uconst [[offset_o_x]], DW_OP_LLVM_fragment 32 32] [$rsp+0]
; ASM: #APP ; ASM: #APP
; ASM: #NO_APP ; ASM: #NO_APP
; ASM: movl [[offset_o_x]](%rsp), %eax # 4-byte Reload ; ASM: movl [[offset_o_x]](%rsp), %eax # 4-byte Reload
; ASM: retq ; ASM: retq
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llvm/test/DebugInfo/COFF/register-variables.ll

Show All 30 Lines
; ASM: [[p_ecx_esi:\.Ltmp.*]]: ; ASM: [[p_ecx_esi:\.Ltmp.*]]:
; ASM: #DEBUG_VALUE: f:p <- $esi ; ASM: #DEBUG_VALUE: f:p <- $esi
; ASM: callq getint ; ASM: callq getint
; ASM: [[after_getint:\.Ltmp.*]]: ; ASM: [[after_getint:\.Ltmp.*]]:
; ASM: testl %esi, %esi ; ASM: testl %esi, %esi
; ASM: je .LBB0_2 ; ASM: je .LBB0_2
; ASM: [[after_je:\.Ltmp.*]]: ; ASM: [[after_je:\.Ltmp.*]]:
; ASM: # %bb.1: # %if.then ; ASM: # %bb.1: # %if.then
; ASM-DAG: #DEBUG_VALUE: inlineinc:a <- $eax ; ASM: #DEBUG_VALUE: f:p <- $esi
; ASM-DAG: #DEBUG_VALUE: a <- $eax ; ASM: #DEBUG_VALUE: a <- $eax
; ASM-DAG: #DEBUG_VALUE: f:p <- $esi ; ASM: #DEBUG_VALUE: inlineinc:a <- $eax
; ASM: addl $1, %eax
; ASM: [[after_inc_eax:\.Ltmp.*]]:
; ASM: #DEBUG_VALUE: inlineinc:b <- $eax
; ASM: addl $1, x(%rip) ; ASM: addl $1, x(%rip)
; ASM: [[after_inc_eax:\.Ltmp.*]]:
; ASM: addl $1, %eax
; ASM: [[after_if:\.Ltmp.*]]: ; ASM: [[after_if:\.Ltmp.*]]:
; ASM: #DEBUG_VALUE: inlineinc:b <- $eax
; ASM: .LBB0_2: # %if.else ; ASM: .LBB0_2: # %if.else
; ASM: #DEBUG_VALUE: f:p <- $esi ; ASM: #DEBUG_VALUE: f:p <- $esi
; ASM: #DEBUG_VALUE: c <- $eax ; ASM: #DEBUG_VALUE: c <- $eax
; ASM: movl %eax, %ecx ; ASM: movl %eax, %ecx
; ASM: addq $32, %rsp ; ASM: addq $32, %rsp
; ASM: popq %rsi ; ASM: popq %rsi
; ASM: [[func_end:\.Ltmp.*]]: ; ASM: [[func_end:\.Ltmp.*]]:
; ASM: jmp putint # TAILCALL ; ASM: jmp putint # TAILCALL
; ASM: [[func_finished:\.Ltmp.*]]: ; ASM: [[func_finished:\.Ltmp.*]]:
; ASM: .short 4414 # Record kind: S_LOCAL ; ASM: .short 4414 # Record kind: S_LOCAL
; ASM: .asciz "p" ; ASM: .asciz "p"
; ASM: .cv_def_range .Lfunc_begin0 [[p_ecx_esi]], reg, 18 ; ASM: .cv_def_range .Lfunc_begin0 [[p_ecx_esi]], reg, 18
; ASM: .cv_def_range [[p_ecx_esi]] [[func_end]], reg, 23 ; ASM: .cv_def_range [[p_ecx_esi]] [[func_end]], reg, 23
; ASM: .short 4414 # Record kind: S_LOCAL ; ASM: .short 4414 # Record kind: S_LOCAL
; ASM: .asciz "c" ; ASM: .asciz "c"
; ASM: .cv_def_range [[after_if]] [[func_finished]], reg, 17 ; ASM: .cv_def_range [[after_if]] [[func_finished]], reg, 17
; ASM: .short 4414 # Record kind: S_LOCAL ; ASM: .short 4414 # Record kind: S_LOCAL
; ASM: .asciz "a" ; ASM: .asciz "a"
; ASM: .cv_def_range [[after_je]] [[after_inc_eax]], reg, 17 ; ASM: .cv_def_range [[after_je]] [[after_if]], reg, 17
; ASM: .short 4414 # Record kind: S_LOCAL ; ASM: .short 4414 # Record kind: S_LOCAL
; ASM: .asciz "b" ; ASM: .asciz "b"
; ASM: .cv_def_range [[after_if]] [[after_if]], reg, 17 ; ASM: .cv_def_range [[after_inc_eax]] [[after_if]], reg, 17
; Note: "b" is a victim of tail de-duplication / branch folding. ; Note: "b" is a victim of tail de-duplication / branch folding.
; ASM: .short 4429 # Record kind: S_INLINESITE ; ASM: .short 4429 # Record kind: S_INLINESITE
; ASM: .short 4414 # Record kind: S_LOCAL ; ASM: .short 4414 # Record kind: S_LOCAL
; ASM: .asciz "a" ; ASM: .asciz "a"
; ASM: .cv_def_range [[after_je]] [[after_inc_eax]], reg, 17 ; ASM: .cv_def_range [[after_je]] [[after_if]], reg, 17
; ASM: .short 4414 # Record kind: S_LOCAL ; ASM: .short 4414 # Record kind: S_LOCAL
; ASM: .asciz "b" ; ASM: .asciz "b"
; ASM: .cv_def_range [[after_inc_eax]] [[after_if]], reg, 17 ; ASM: .cv_def_range [[after_if]] [[after_if]], reg, 17
; ASM: .short 4430 # Record kind: S_INLINESITE_END ; ASM: .short 4430 # Record kind: S_INLINESITE_END
; OBJ: Subsection [ ; OBJ: Subsection [
; OBJ: SubSectionType: Symbols (0xF1) ; OBJ: SubSectionType: Symbols (0xF1)
; OBJ: {{.*}}Proc{{.*}}Sym { ; OBJ: {{.*}}Proc{{.*}}Sym {
; OBJ: DisplayName: f ; OBJ: DisplayName: f
; OBJ: } ; OBJ: }
; OBJ: LocalSym { ; OBJ: LocalSym {
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; OBJ: ] ; OBJ: ]
; OBJ: VarName: a ; OBJ: VarName: a
; OBJ: } ; OBJ: }
; OBJ: DefRangeRegisterSym { ; OBJ: DefRangeRegisterSym {
; OBJ: Register: EAX (0x11) ; OBJ: Register: EAX (0x11)
; OBJ: LocalVariableAddrRange { ; OBJ: LocalVariableAddrRange {
; OBJ: OffsetStart: .text+0x10 ; OBJ: OffsetStart: .text+0x10
; OBJ: ISectStart: 0x0 ; OBJ: ISectStart: 0x0
; OBJ: Range: 0x3 ; OBJ: Range: 0xA
; OBJ: } ; OBJ: }
; OBJ: } ; OBJ: }
; OBJ: LocalSym { ; OBJ: LocalSym {
; OBJ: Type: int (0x74) ; OBJ: Type: int (0x74)
; OBJ: Flags [ (0x0) ; OBJ: Flags [ (0x0)
; OBJ: ] ; OBJ: ]
; OBJ: VarName: b ; OBJ: VarName: b
; OBJ: } ; OBJ: }
; OBJ: DefRangeRegisterSym { ; OBJ: DefRangeRegisterSym {
; OBJ: Register: EAX (0x11) ; OBJ: Register: EAX (0x11)
; OBJ: LocalVariableAddrRange { ; OBJ: LocalVariableAddrRange {
; OBJ: OffsetStart: .text+0x13 ; OBJ: OffsetStart: .text+0x1A
; OBJ: ISectStart: 0x0 ; OBJ: ISectStart: 0x0
; OBJ: Range: 0x7 ; OBJ: Range: 0x0
; OBJ: } ; OBJ: }
; OBJ: } ; OBJ: }
; OBJ: InlineSiteEnd { ; OBJ: InlineSiteEnd {
; OBJ: } ; OBJ: }
; OBJ: ProcEnd ; OBJ: ProcEnd
; OBJ: ] ; OBJ: ]
; ModuleID = 't.cpp' ; ModuleID = 't.cpp'
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llvm/test/DebugInfo/X86/spill-nospill.ll

Show All 22 Lines
; CHECK-LABEL: f: # @f ; CHECK-LABEL: f: # @f
; CHECK: callq g ; CHECK: callq g
; CHECK: movl %eax, [[X_OFFS:[0-9]+]](%rsp) # 4-byte Spill ; CHECK: movl %eax, [[X_OFFS:[0-9]+]](%rsp) # 4-byte Spill
; CHECK: #DEBUG_VALUE: f:x <- [DW_OP_plus_uconst [[X_OFFS]]] [$rsp+0] ; CHECK: #DEBUG_VALUE: f:x <- [DW_OP_plus_uconst [[X_OFFS]]] [$rsp+0]
; CHECK: #APP ; CHECK: #APP
; CHECK: #NO_APP ; CHECK: #NO_APP
; CHECK: callq g ; CHECK: callq g
; CHECK: movl %eax, %ecx
; CHECK: movl %eax, %[[CSR:[^ ]*]] ; CHECK: movl %eax, %[[CSR:[^ ]*]]
; CHECK: #DEBUG_VALUE: f:y <- $esi ; CHECK: #DEBUG_VALUE: f:y <- $esi
; CHECK: movl %eax, %ecx
; CHECK: callq g ; CHECK: callq g
; CHECK: movl %[[CSR]], %ecx ; CHECK: movl %[[CSR]], %ecx
; CHECK: callq g ; CHECK: callq g
; CHECK: movl %[[CSR]], %ecx ; CHECK: movl %[[CSR]], %ecx
; CHECK: callq g ; CHECK: callq g
; CHECK: movl [[X_OFFS]](%rsp), %eax # 4-byte Reload ; CHECK: movl [[X_OFFS]](%rsp), %eax # 4-byte Reload
; CHECK: #DEBUG_VALUE: f:x <- $eax ; CHECK: #DEBUG_VALUE: f:x <- $eax
; CHECK: addl %[[CSR]], %eax ; CHECK: addl %[[CSR]], %eax
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llvm/test/Transforms/LoopStrengthReduce/X86/ivchain-X86.ll

Show All 11 Lines
; ;
; no expensive address computation in the preheader ; no expensive address computation in the preheader
; no complex address modes ; no complex address modes
define i32 @simple(i32* %a, i32* %b, i32 %x) nounwind { define i32 @simple(i32* %a, i32* %b, i32 %x) nounwind {
; X64-LABEL: simple: ; X64-LABEL: simple:
; X64: # %bb.0: # %entry ; X64: # %bb.0: # %entry
; X64-NEXT: movslq %edx, %rcx ; X64-NEXT: movslq %edx, %rcx
; X64-NEXT: shlq $2, %rcx
; X64-NEXT: xorl %eax, %eax ; X64-NEXT: xorl %eax, %eax
; X64-NEXT: shlq $2, %rcx
; X64-NEXT: .p2align 4, 0x90 ; X64-NEXT: .p2align 4, 0x90
; X64-NEXT: .LBB0_1: # %loop ; X64-NEXT: .LBB0_1: # %loop
; X64-NEXT: # =>This Inner Loop Header: Depth=1 ; X64-NEXT: # =>This Inner Loop Header: Depth=1
; X64-NEXT: addl (%rdi), %eax ; X64-NEXT: addl (%rdi), %eax
; X64-NEXT: leaq (%rdi,%rcx), %r8 ; X64-NEXT: leaq (%rdi,%rcx), %r8
; X64-NEXT: addl (%rdi,%rcx), %eax ; X64-NEXT: addl (%rdi,%rcx), %eax
; X64-NEXT: leaq (%r8,%rcx), %rdx ; X64-NEXT: leaq (%r8,%rcx), %rdx
; X64-NEXT: addl (%rcx,%r8), %eax ; X64-NEXT: addl (%rcx,%r8), %eax
; X64-NEXT: addl (%rcx,%rdx), %eax ; X64-NEXT: addl (%rcx,%rdx), %eax
; X64-NEXT: addq %rcx, %rdx ; X64-NEXT: addq %rcx, %rdx
; X64-NEXT: addq %rcx, %rdx ; X64-NEXT: addq %rcx, %rdx
; X64-NEXT: movq %rdx, %rdi ; X64-NEXT: movq %rdx, %rdi
; X64-NEXT: cmpq %rsi, %rdx ; X64-NEXT: cmpq %rsi, %rdx
; X64-NEXT: jne .LBB0_1 ; X64-NEXT: jne .LBB0_1
; X64-NEXT: # %bb.2: # %exit ; X64-NEXT: # %bb.2: # %exit
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X32-LABEL: simple: ; X32-LABEL: simple:
; X32: # %bb.0: # %entry ; X32: # %bb.0: # %entry
; X32-NEXT: pushl %ebx ; X32-NEXT: pushl %ebx
; X32-NEXT: pushl %edi ; X32-NEXT: pushl %edi
; X32-NEXT: pushl %esi ; X32-NEXT: pushl %esi
; X32-NEXT: movl {{[0-9]+}}(%esp), %edx
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: movl {{[0-9]+}}(%esp), %esi ; X32-NEXT: movl {{[0-9]+}}(%esp), %esi
; X32-NEXT: movl {{[0-9]+}}(%esp), %edx
; X32-NEXT: shll $2, %edx
; X32-NEXT: xorl %eax, %eax ; X32-NEXT: xorl %eax, %eax
; X32-NEXT: shll $2, %edx
; X32-NEXT: .p2align 4, 0x90 ; X32-NEXT: .p2align 4, 0x90
; X32-NEXT: .LBB0_1: # %loop ; X32-NEXT: .LBB0_1: # %loop
; X32-NEXT: # =>This Inner Loop Header: Depth=1 ; X32-NEXT: # =>This Inner Loop Header: Depth=1
; X32-NEXT: addl (%esi), %eax ; X32-NEXT: addl (%esi), %eax
; X32-NEXT: leal (%esi,%edx), %edi ; X32-NEXT: leal (%esi,%edx), %edi
; X32-NEXT: addl (%esi,%edx), %eax ; X32-NEXT: addl (%esi,%edx), %eax
; X32-NEXT: leal (%edi,%edx), %ebx ; X32-NEXT: leal (%edi,%edx), %ebx
; X32-NEXT: addl (%edx,%edi), %eax ; X32-NEXT: addl (%edx,%edi), %eax
Show All 35 Lines
; ;
; expensive address computation in the preheader ; expensive address computation in the preheader
; complex address modes ; complex address modes
define i32 @user(i32* %a, i32* %b, i32 %x) nounwind { define i32 @user(i32* %a, i32* %b, i32 %x) nounwind {
; X64-LABEL: user: ; X64-LABEL: user:
; X64: # %bb.0: # %entry ; X64: # %bb.0: # %entry
; X64-NEXT: movslq %edx, %rcx ; X64-NEXT: movslq %edx, %rcx
; X64-NEXT: movq %rcx, %rdx ; X64-NEXT: movq %rcx, %rdx
; X64-NEXT: shlq $4, %rdx
; X64-NEXT: leaq (,%rcx,4), %rax ; X64-NEXT: leaq (,%rcx,4), %rax
; X64-NEXT: leaq (%rax,%rax,2), %r8 ; X64-NEXT: leaq (%rax,%rax,2), %r8
; X64-NEXT: shlq $4, %rdx
; X64-NEXT: xorl %eax, %eax ; X64-NEXT: xorl %eax, %eax
; X64-NEXT: .p2align 4, 0x90 ; X64-NEXT: .p2align 4, 0x90
; X64-NEXT: .LBB1_1: # %loop ; X64-NEXT: .LBB1_1: # %loop
; X64-NEXT: # =>This Inner Loop Header: Depth=1 ; X64-NEXT: # =>This Inner Loop Header: Depth=1
; X64-NEXT: addl (%rdi), %eax ; X64-NEXT: addl (%rdi), %eax
; X64-NEXT: addl (%rdi,%rcx,4), %eax ; X64-NEXT: addl (%rdi,%rcx,4), %eax
; X64-NEXT: addl (%rdi,%rcx,8), %eax ; X64-NEXT: addl (%rdi,%rcx,8), %eax
; X64-NEXT: addl (%rdi,%r8), %eax ; X64-NEXT: addl (%rdi,%r8), %eax
; X64-NEXT: movl %eax, (%rdi) ; X64-NEXT: movl %eax, (%rdi)
; X64-NEXT: addq %rdx, %rdi ; X64-NEXT: addq %rdx, %rdi
; X64-NEXT: cmpq %rdi, %rsi ; X64-NEXT: cmpq %rdi, %rsi
; X64-NEXT: jne .LBB1_1 ; X64-NEXT: jne .LBB1_1
; X64-NEXT: # %bb.2: # %exit ; X64-NEXT: # %bb.2: # %exit
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X32-LABEL: user: ; X32-LABEL: user:
; X32: # %bb.0: # %entry ; X32: # %bb.0: # %entry
; X32-NEXT: pushl %ebx ; X32-NEXT: pushl %ebx
; X32-NEXT: pushl %edi ; X32-NEXT: pushl %edi
; X32-NEXT: pushl %esi ; X32-NEXT: pushl %esi
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: movl {{[0-9]+}}(%esp), %edx ; X32-NEXT: movl {{[0-9]+}}(%esp), %edx
; X32-NEXT: movl {{[0-9]+}}(%esp), %esi ; X32-NEXT: movl {{[0-9]+}}(%esp), %esi
; X32-NEXT: movl %ecx, %edi ; X32-NEXT: movl %ecx, %edi
; X32-NEXT: shll $4, %edi
; X32-NEXT: leal (,%ecx,4), %eax ; X32-NEXT: leal (,%ecx,4), %eax
; X32-NEXT: leal (%eax,%eax,2), %ebx ; X32-NEXT: leal (%eax,%eax,2), %ebx
; X32-NEXT: shll $4, %edi
; X32-NEXT: xorl %eax, %eax ; X32-NEXT: xorl %eax, %eax
; X32-NEXT: .p2align 4, 0x90 ; X32-NEXT: .p2align 4, 0x90
; X32-NEXT: .LBB1_1: # %loop ; X32-NEXT: .LBB1_1: # %loop
; X32-NEXT: # =>This Inner Loop Header: Depth=1 ; X32-NEXT: # =>This Inner Loop Header: Depth=1
; X32-NEXT: addl (%esi), %eax ; X32-NEXT: addl (%esi), %eax
; X32-NEXT: addl (%esi,%ecx,4), %eax ; X32-NEXT: addl (%esi,%ecx,4), %eax
; X32-NEXT: addl (%esi,%ecx,8), %eax ; X32-NEXT: addl (%esi,%ecx,8), %eax
; X32-NEXT: addl (%esi,%ebx), %eax ; X32-NEXT: addl (%esi,%ebx), %eax
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
; X64-NEXT: pushq %rbp ; X64-NEXT: pushq %rbp
; X64-NEXT: pushq %r14 ; X64-NEXT: pushq %r14
; X64-NEXT: pushq %rbx ; X64-NEXT: pushq %rbx
; X64-NEXT: # kill: def $ecx killed $ecx def $rcx ; X64-NEXT: # kill: def $ecx killed $ecx def $rcx
; X64-NEXT: # kill: def $esi killed $esi def $rsi ; X64-NEXT: # kill: def $esi killed $esi def $rsi
; X64-NEXT: testl %r9d, %r9d ; X64-NEXT: testl %r9d, %r9d
; X64-NEXT: je .LBB2_3 ; X64-NEXT: je .LBB2_3
; X64-NEXT: # %bb.1: # %for.body.lr.ph ; X64-NEXT: # %bb.1: # %for.body.lr.ph
; X64-NEXT: leal (%rsi,%rsi), %r14d
; X64-NEXT: leal (%rsi,%rsi,2), %ebx
; X64-NEXT: addl %esi, %ecx ; X64-NEXT: addl %esi, %ecx
; X64-NEXT: leal (%rsi,%rsi,2), %ebx
; X64-NEXT: leal (,%rsi,4), %eax ; X64-NEXT: leal (,%rsi,4), %eax
; X64-NEXT: leal (%rsi,%rsi), %r14d
; X64-NEXT: leal (%rcx,%rsi,4), %ebp ; X64-NEXT: leal (%rcx,%rsi,4), %ebp
; X64-NEXT: movslq %r8d, %rcx
; X64-NEXT: movslq %eax, %r10 ; X64-NEXT: movslq %eax, %r10
; X64-NEXT: movslq %ebx, %r11 ; X64-NEXT: movslq %ebx, %r11
; X64-NEXT: movslq %r14d, %rbx ; X64-NEXT: movslq %r14d, %rbx
; X64-NEXT: movslq %esi, %rsi ; X64-NEXT: movslq %esi, %rsi
; X64-NEXT: movslq %r8d, %rcx
; X64-NEXT: shlq $2, %rcx ; X64-NEXT: shlq $2, %rcx
; X64-NEXT: movslq %ebp, %rax ; X64-NEXT: movslq %ebp, %rax
; X64-NEXT: .p2align 4, 0x90 ; X64-NEXT: .p2align 4, 0x90
; X64-NEXT: .LBB2_2: # %for.body ; X64-NEXT: .LBB2_2: # %for.body
; X64-NEXT: # =>This Inner Loop Header: Depth=1 ; X64-NEXT: # =>This Inner Loop Header: Depth=1
; X64-NEXT: movl (%rdi,%rsi), %ebp ; X64-NEXT: movl (%rdi,%rsi), %ebp
; X64-NEXT: addl (%rdi), %ebp ; X64-NEXT: addl (%rdi), %ebp
; X64-NEXT: addl (%rdi,%rbx), %ebp ; X64-NEXT: addl (%rdi,%rbx), %ebp
; X64-NEXT: addl (%rdi,%r11), %ebp ; X64-NEXT: addl (%rdi,%r11), %ebp
; X64-NEXT: addl (%rdi,%r10), %ebp ; X64-NEXT: addl (%rdi,%r10), %ebp
; X64-NEXT: movl %ebp, (%rdx)
; X64-NEXT: addq %rax, %rdi ; X64-NEXT: addq %rax, %rdi
; X64-NEXT: movl %ebp, (%rdx)
; X64-NEXT: addq %rcx, %rdx ; X64-NEXT: addq %rcx, %rdx
; X64-NEXT: decl %r9d ; X64-NEXT: decl %r9d
; X64-NEXT: jne .LBB2_2 ; X64-NEXT: jne .LBB2_2
; X64-NEXT: .LBB2_3: # %for.end ; X64-NEXT: .LBB2_3: # %for.end
; X64-NEXT: popq %rbx ; X64-NEXT: popq %rbx
; X64-NEXT: popq %r14 ; X64-NEXT: popq %r14
; X64-NEXT: popq %rbp ; X64-NEXT: popq %rbp
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X32-LABEL: extrastride: ; X32-LABEL: extrastride:
; X32: # %bb.0: # %entry ; X32: # %bb.0: # %entry
; X32-NEXT: pushl %ebp ; X32-NEXT: pushl %ebp
; X32-NEXT: pushl %ebx ; X32-NEXT: pushl %ebx
; X32-NEXT: pushl %edi ; X32-NEXT: pushl %edi
; X32-NEXT: pushl %esi ; X32-NEXT: pushl %esi
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: testl %eax, %eax ; X32-NEXT: testl %eax, %eax
; X32-NEXT: je .LBB2_3 ; X32-NEXT: je .LBB2_3
; X32-NEXT: # %bb.1: # %for.body.lr.ph ; X32-NEXT: # %bb.1: # %for.body.lr.ph
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: movl {{[0-9]+}}(%esp), %edx
; X32-NEXT: movl {{[0-9]+}}(%esp), %esi ; X32-NEXT: movl {{[0-9]+}}(%esp), %esi
; X32-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X32-NEXT: movl {{[0-9]+}}(%esp), %edi ; X32-NEXT: movl {{[0-9]+}}(%esp), %edi
; X32-NEXT: movl {{[0-9]+}}(%esp), %edx
; X32-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X32-NEXT: addl %esi, %edi ; X32-NEXT: addl %esi, %edi
; X32-NEXT: shll $2, %ecx ; X32-NEXT: shll $2, %ecx
; X32-NEXT: .p2align 4, 0x90 ; X32-NEXT: .p2align 4, 0x90
; X32-NEXT: .LBB2_2: # %for.body ; X32-NEXT: .LBB2_2: # %for.body
; X32-NEXT: # =>This Inner Loop Header: Depth=1 ; X32-NEXT: # =>This Inner Loop Header: Depth=1
; X32-NEXT: movl (%ebx,%esi), %ebp ; X32-NEXT: movl (%ebx,%esi), %ebp
; X32-NEXT: addl (%ebx), %ebp ; X32-NEXT: addl (%ebx), %ebp
; X32-NEXT: addl %esi, %ebx ; X32-NEXT: addl %esi, %ebx
; X32-NEXT: addl (%esi,%ebx), %ebp ; X32-NEXT: addl (%esi,%ebx), %ebp
; X32-NEXT: addl %esi, %ebx ; X32-NEXT: addl %esi, %ebx
; X32-NEXT: addl (%esi,%ebx), %ebp ; X32-NEXT: addl (%esi,%ebx), %ebp
; X32-NEXT: addl %esi, %ebx ; X32-NEXT: addl %esi, %ebx
; X32-NEXT: addl (%esi,%ebx), %ebp ; X32-NEXT: addl (%esi,%ebx), %ebp
; X32-NEXT: movl %ebp, (%edx)
; X32-NEXT: addl %esi, %ebx ; X32-NEXT: addl %esi, %ebx
; X32-NEXT: addl %edi, %ebx ; X32-NEXT: addl %edi, %ebx
; X32-NEXT: movl %ebp, (%edx)
; X32-NEXT: addl %ecx, %edx ; X32-NEXT: addl %ecx, %edx
; X32-NEXT: decl %eax ; X32-NEXT: decl %eax
; X32-NEXT: jne .LBB2_2 ; X32-NEXT: jne .LBB2_2
; X32-NEXT: .LBB2_3: # %for.end ; X32-NEXT: .LBB2_3: # %for.end
; X32-NEXT: popl %esi ; X32-NEXT: popl %esi
; X32-NEXT: popl %edi ; X32-NEXT: popl %edi
; X32-NEXT: popl %ebx ; X32-NEXT: popl %ebx
; X32-NEXT: popl %ebp ; X32-NEXT: popl %ebp
▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines
; X64-NEXT: # %bb.2: # %for.end ; X64-NEXT: # %bb.2: # %for.end
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X32-LABEL: foldedidx: ; X32-LABEL: foldedidx:
; X32: # %bb.0: # %entry ; X32: # %bb.0: # %entry
; X32-NEXT: pushl %ebx ; X32-NEXT: pushl %ebx
; X32-NEXT: pushl %edi ; X32-NEXT: pushl %edi
; X32-NEXT: pushl %esi ; X32-NEXT: pushl %esi
; X32-NEXT: movl $3, %eax
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: movl {{[0-9]+}}(%esp), %edx ; X32-NEXT: movl {{[0-9]+}}(%esp), %edx
; X32-NEXT: movl {{[0-9]+}}(%esp), %esi ; X32-NEXT: movl {{[0-9]+}}(%esp), %esi
; X32-NEXT: movl $3, %eax
; X32-NEXT: .p2align 4, 0x90 ; X32-NEXT: .p2align 4, 0x90
; X32-NEXT: .LBB3_1: # %for.body ; X32-NEXT: .LBB3_1: # %for.body
; X32-NEXT: # =>This Inner Loop Header: Depth=1 ; X32-NEXT: # =>This Inner Loop Header: Depth=1
; X32-NEXT: movzbl -3(%esi,%eax), %edi ; X32-NEXT: movzbl -3(%esi,%eax), %edi
; X32-NEXT: movzbl -3(%edx,%eax), %ebx ; X32-NEXT: movzbl -3(%edx,%eax), %ebx
; X32-NEXT: addl %edi, %ebx ; X32-NEXT: addl %edi, %ebx
; X32-NEXT: movb %bl, -3(%ecx,%eax) ; X32-NEXT: movb %bl, -3(%ecx,%eax)
; X32-NEXT: movzbl -2(%esi,%eax), %edi ; X32-NEXT: movzbl -2(%esi,%eax), %edi
▲ Show 20 Lines • Show All 77 Lines • ▼ Show 20 Lines
define void @multioper(i32* %a, i32 %n) nounwind { define void @multioper(i32* %a, i32 %n) nounwind {
; X64-LABEL: multioper: ; X64-LABEL: multioper:
; X64: # %bb.0: # %entry ; X64: # %bb.0: # %entry
; X64-NEXT: xorl %eax, %eax ; X64-NEXT: xorl %eax, %eax
; X64-NEXT: .p2align 4, 0x90 ; X64-NEXT: .p2align 4, 0x90
; X64-NEXT: .LBB4_1: # %for.body ; X64-NEXT: .LBB4_1: # %for.body
; X64-NEXT: # =>This Inner Loop Header: Depth=1 ; X64-NEXT: # =>This Inner Loop Header: Depth=1
; X64-NEXT: movl %eax, (%rdi,%rax,4)
; X64-NEXT: leal 1(%rax), %ecx ; X64-NEXT: leal 1(%rax), %ecx
; X64-NEXT: leal 2(%rax), %r8d
; X64-NEXT: leal 3(%rax), %edx
; X64-NEXT: movl %eax, (%rdi,%rax,4)
; X64-NEXT: movl %ecx, 4(%rdi,%rax,4) ; X64-NEXT: movl %ecx, 4(%rdi,%rax,4)
; X64-NEXT: leal 2(%rax), %ecx ; X64-NEXT: movl %r8d, 8(%rdi,%rax,4)
; X64-NEXT: movl %ecx, 8(%rdi,%rax,4) ; X64-NEXT: movl %edx, 12(%rdi,%rax,4)
; X64-NEXT: leal 3(%rax), %ecx
; X64-NEXT: movl %ecx, 12(%rdi,%rax,4)
; X64-NEXT: addq $4, %rax ; X64-NEXT: addq $4, %rax
; X64-NEXT: cmpl %esi, %eax ; X64-NEXT: cmpl %esi, %eax
; X64-NEXT: jl .LBB4_1 ; X64-NEXT: jl .LBB4_1
; X64-NEXT: # %bb.2: # %exit ; X64-NEXT: # %bb.2: # %exit
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X32-LABEL: multioper: ; X32-LABEL: multioper:
; X32: # %bb.0: # %entry ; X32: # %bb.0: # %entry
; X32-NEXT: pushl %esi ; X32-NEXT: pushl %esi
; X32-NEXT: xorl %eax, %eax
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: movl {{[0-9]+}}(%esp), %edx ; X32-NEXT: movl {{[0-9]+}}(%esp), %edx
; X32-NEXT: xorl %eax, %eax
; X32-NEXT: .p2align 4, 0x90 ; X32-NEXT: .p2align 4, 0x90
; X32-NEXT: .LBB4_1: # %for.body ; X32-NEXT: .LBB4_1: # %for.body
; X32-NEXT: # =>This Inner Loop Header: Depth=1 ; X32-NEXT: # =>This Inner Loop Header: Depth=1
; X32-NEXT: movl %eax, (%edx,%eax,4)
; X32-NEXT: leal 1(%eax), %esi ; X32-NEXT: leal 1(%eax), %esi
; X32-NEXT: movl %eax, (%edx,%eax,4)
; X32-NEXT: movl %esi, 4(%edx,%eax,4) ; X32-NEXT: movl %esi, 4(%edx,%eax,4)
; X32-NEXT: leal 2(%eax), %esi ; X32-NEXT: leal 2(%eax), %esi
; X32-NEXT: movl %esi, 8(%edx,%eax,4) ; X32-NEXT: movl %esi, 8(%edx,%eax,4)
; X32-NEXT: leal 3(%eax), %esi ; X32-NEXT: leal 3(%eax), %esi
; X32-NEXT: movl %esi, 12(%edx,%eax,4) ; X32-NEXT: movl %esi, 12(%edx,%eax,4)
; X32-NEXT: addl $4, %eax ; X32-NEXT: addl $4, %eax
; X32-NEXT: cmpl %ecx, %eax ; X32-NEXT: cmpl %ecx, %eax
; X32-NEXT: jl .LBB4_1 ; X32-NEXT: jl .LBB4_1
Show All 28 Lines
; @testCmpZero has a ICmpZero LSR use that should not be hidden from ; @testCmpZero has a ICmpZero LSR use that should not be hidden from
; LSR. Profitable chains should have more than one nonzero increment ; LSR. Profitable chains should have more than one nonzero increment
; anyway. ; anyway.
define void @testCmpZero(i8* %src, i8* %dst, i32 %srcidx, i32 %dstidx, i32 %len) nounwind ssp { define void @testCmpZero(i8* %src, i8* %dst, i32 %srcidx, i32 %dstidx, i32 %len) nounwind ssp {
; X64-LABEL: testCmpZero: ; X64-LABEL: testCmpZero:
; X64: # %bb.0: # %entry ; X64: # %bb.0: # %entry
; X64-NEXT: movslq %edx, %rdx ; X64-NEXT: movslq %edx, %rdx
; X64-NEXT: addq %rdx, %rdi
; X64-NEXT: movslq %ecx, %r9 ; X64-NEXT: movslq %ecx, %r9
; X64-NEXT: addq %rsi, %r9
; X64-NEXT: addl %edx, %r8d ; X64-NEXT: addl %edx, %r8d
; X64-NEXT: addq %rdx, %rdi
; X64-NEXT: addq %rsi, %r9
; X64-NEXT: movslq %r8d, %rcx ; X64-NEXT: movslq %r8d, %rcx
; X64-NEXT: subq %rdx, %rcx ; X64-NEXT: subq %rdx, %rcx
; X64-NEXT: xorl %edx, %edx ; X64-NEXT: xorl %edx, %edx
; X64-NEXT: .p2align 4, 0x90 ; X64-NEXT: .p2align 4, 0x90
; X64-NEXT: .LBB5_1: # %for.body82.us ; X64-NEXT: .LBB5_1: # %for.body82.us
; X64-NEXT: # =>This Inner Loop Header: Depth=1 ; X64-NEXT: # =>This Inner Loop Header: Depth=1
; X64-NEXT: movzbl (%r9,%rdx,4), %eax ; X64-NEXT: movzbl (%r9,%rdx,4), %eax
; X64-NEXT: movb %al, (%rdi,%rdx) ; X64-NEXT: movb %al, (%rdi,%rdx)
; X64-NEXT: incq %rdx ; X64-NEXT: incq %rdx
; X64-NEXT: cmpq %rdx, %rcx ; X64-NEXT: cmpq %rdx, %rcx
; X64-NEXT: jne .LBB5_1 ; X64-NEXT: jne .LBB5_1
; X64-NEXT: # %bb.2: # %return ; X64-NEXT: # %bb.2: # %return
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X32-LABEL: testCmpZero: ; X32-LABEL: testCmpZero:
; X32: # %bb.0: # %entry ; X32: # %bb.0: # %entry
; X32-NEXT: pushl %ebx ; X32-NEXT: pushl %ebx
; X32-NEXT: pushl %esi ; X32-NEXT: pushl %esi
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: addl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: movl {{[0-9]+}}(%esp), %edx ; X32-NEXT: movl {{[0-9]+}}(%esp), %edx
; X32-NEXT: addl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: addl {{[0-9]+}}(%esp), %edx ; X32-NEXT: addl {{[0-9]+}}(%esp), %edx
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: xorl %esi, %esi ; X32-NEXT: xorl %esi, %esi
; X32-NEXT: .p2align 4, 0x90 ; X32-NEXT: .p2align 4, 0x90
; X32-NEXT: .LBB5_1: # %for.body82.us ; X32-NEXT: .LBB5_1: # %for.body82.us
; X32-NEXT: # =>This Inner Loop Header: Depth=1 ; X32-NEXT: # =>This Inner Loop Header: Depth=1
; X32-NEXT: movzbl (%edx,%esi,4), %ebx ; X32-NEXT: movzbl (%edx,%esi,4), %ebx
; X32-NEXT: movb %bl, (%ecx,%esi) ; X32-NEXT: movb %bl, (%ecx,%esi)
; X32-NEXT: incl %esi ; X32-NEXT: incl %esi
; X32-NEXT: cmpl %esi, %eax ; X32-NEXT: cmpl %esi, %eax
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