This is an archive of the discontinued LLVM Phabricator instance.

[ARM] Add predicated mla reduction patterns
ClosedPublic

Authored by dmgreen on Jul 18 2020, 7:58 AM.

Details

Summary

Similar to D84101 but this time for MLA patterns, this selects predicated vmlav/vmlava/vmlalv/vmlava instructions from vecreduce.add(select(p, mul(x, y), 0) nodes.

Diff Detail

Event Timeline

dmgreen created this revision.Jul 18 2020, 7:58 AM
simon_tatham added inline comments.Jul 20 2020, 5:20 AM
llvm/lib/Target/ARM/ARMInstrMVE.td
1340

I don't see any lowering code that generates the ARMVMLALVAps node, but these pattern match it. Did I miss it somewhere?

dmgreen marked an inline comment as done.Jul 20 2020, 5:53 AM
dmgreen added inline comments.
llvm/lib/Target/ARM/ARMInstrMVE.td
1340

Oh yeah. I missed a bit in my diffing...

dmgreen updated this revision to Diff 279210.Jul 20 2020, 5:56 AM

Add extra VMLALVps + add -> VMLALVAps folds.

simon_tatham accepted this revision.Jul 20 2020, 6:11 AM
This revision is now accepted and ready to land.Jul 20 2020, 6:11 AM
This revision was automatically updated to reflect the committed changes.