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Differential D83364

[PowerPC][Power10] Implement Instruction definition and MC Tests for Load and Store VSX Vector with Zero or Sign Extend
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Authored by Conanap on Jul 7 2020, 6:04 PM.

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power-llvm-team
saghir
nemanjai
hfinkel
amyk
kamaub
lei
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rG5ffec4672028: [PowerPC][Power10] Add Instruction definition/MC Tests for Load/Store Rightmost…
Summary

Includes instruction defintion and MC Tests for above instructions.

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Unit TestsFailed
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TimeTest
620 mswindows > Clang.CodeGen/arm-mve-intrinsics::Unknown Unit Message ("")
Script: -- : 'RUN: at line 2'; c:\ws\w2\llvm-project\premerge-checks\build\bin\clang.exe -cc1 -internal-isystem c:\ws\w2\llvm-project\premerge-checks\build\lib\clang\11.0.0\include -nostdsysteminc -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - C:\ws\w2\llvm-project\premerge-checks\clang\test\CodeGen\arm-mve-intrinsics\dup.c | c:\ws\w2\llvm-project\premerge-checks\build\bin\opt.exe -S -mem2reg -sroa -early-cse | c:\ws\w2\llvm-project\premerge-checks\build\bin\filecheck.exe C:\ws\w2\llvm-project\premerge-checks\clang\test\CodeGen\arm-mve-intrinsics\dup.c

Event Timeline

Conanap created this revision.Jul 7 2020, 6:04 PM
Harbormaster failed remote builds in B63348: Diff 276282!Jul 7 2020, 8:27 PM
amyk accepted this revision as: amyk.Jul 8 2020, 7:46 AM
amyk added a subscriber: amyk.

This LGTM.

This revision is now accepted and ready to land.Jul 8 2020, 7:46 AM
kamaub accepted this revision.Jul 8 2020, 8:14 AM
kamaub added a subscriber: kamaub.

LGTM

lei added a subscriber: lei.Jul 8 2020, 9:12 AM
lei added inline comments.
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
431

Instead of creating a new section like this, why not add to the existing one on line 469? I realize that does not have Predicates = [IsISA3_1], but I think that is an oversight from previous patch and it should be added as those instructions are also part of ISA3.1.

439

same.

Conanap updated this revision to Diff 276564.Jul 8 2020, 2:58 PM

Relocated some of the instructions to a more appropriate place.

Conanap marked 2 inline comments as done.Jul 8 2020, 2:58 PM

Relocated the isntr definitions to a more appropriate place.

Harbormaster completed remote builds in B63498: Diff 276564.Jul 8 2020, 3:34 PM
lei accepted this revision.Jul 9 2020, 11:15 AM

LGTM thx.

Conanap mentioned this in D82502: [PowerPC] Implement Load VSX Vector and Sign Extend and Zero Extend.Jul 9 2020, 11:25 AM
bsaleil added a subscriber: bsaleil.Jul 9 2020, 12:05 PM
bsaleil added inline comments.
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
963

Shouldn't mayStore be 0 instead of 1 here ?

Conanap marked an inline comment as done.Jul 9 2020, 1:33 PM
Conanap added inline comments.
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
963

yes, thanks; will fix on the commit

Closed by commit rG5ffec4672028: [PowerPC][Power10] Add Instruction definition/MC Tests for Load/Store Rightmost… (authored by Conanap, committed by amyk). · Explain WhyJul 9 2020, 3:06 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents
Changeset List

PathSize
llvm/
lib/
Target/
PowerPC/
16 lines
test/
MC/
Disassembler/
PowerPC/
24 lines
PowerPC/
24 lines

Diff 276282

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llvm/lib/Target/PowerPC/PPCInstrPrefix.td

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llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt

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llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s

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