This is an archive of the discontinued LLVM Phabricator instance.

Differential D82747

[PowerPC] Support constrained int/fp conversion in SPE targets
ClosedPublic

Authored by qiucf on Jun 29 2020, 2:39 AM.

Details

Reviewers
jhibbits
chmeee
uweigand
Group Reviewers
Restricted Project
Commits
rGb6912c879ed8: [PowerPC] Support constrained conversion in SPE target
Summary

This revision derives from D81537 and D81669, but does NOT depend on them since such conversion is naturally legal on SPE. Split this out for easier review.

Diff Detail

Event Timeline

qiucf created this revision.Jun 29 2020, 2:39 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 29 2020, 2:39 AM
Herald added subscribers: llvm-commits, shchenz, kbarton and 2 others. · View Herald Transcript
qiucf mentioned this in D81537: [PowerPC] Support constrained fp operation for scalar fptosi/fptoui.Jun 29 2020, 2:41 AM
Harbormaster failed remote builds in B62110: Diff 274021!Jun 29 2020, 3:12 AM
Herald added a subscriber: • wuzish. · View Herald TranscriptJun 29 2020, 3:12 AM
jhibbits accepted this revision.Jul 10 2020, 5:58 PM

Looks fine to me.

This revision is now accepted and ready to land.Jul 10 2020, 5:58 PM
Closed by commit rGb6912c879ed8: [PowerPC] Support constrained conversion in SPE target (authored by qiucf). · Explain WhyJul 12 2020, 9:34 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
PowerPC/
8 lines
16 lines
test/
CodeGen/
PowerPC/
274 lines

Diff 277322

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 417 Lines • ▼ Show 20 LinesPPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
// PowerPC does not have BRCOND which requires SetCC // PowerPC does not have BRCOND which requires SetCC
if (!Subtarget.useCRBits()) if (!Subtarget.useCRBits())
setOperationAction(ISD::BRCOND, MVT::Other, Expand); setOperationAction(ISD::BRCOND, MVT::Other, Expand);
setOperationAction(ISD::BR_JT, MVT::Other, Expand); setOperationAction(ISD::BR_JT, MVT::Other, Expand);
if (Subtarget.hasSPE()) { if (Subtarget.hasSPE()) {
// SPE has built-in conversions // SPE has built-in conversions
setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Legal);
setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i32, Legal);
setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i32, Legal);
setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal); setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal); setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal); setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
} else { } else {
// PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores. // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
// PowerPC does not have [U|S]INT_TO_FP // PowerPC does not have [U|S]INT_TO_FP
▲ Show 20 Lines • Show All 133 Lines • ▼ Show 20 Lines if (Subtarget.has64BitSupport()) {
// This is just the low 32 bits of a (signed) fp->i64 conversion. // This is just the low 32 bits of a (signed) fp->i64 conversion.
// We cannot do this with Promote because i64 is not a legal type. // We cannot do this with Promote because i64 is not a legal type.
setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
if (Subtarget.hasLFIWAX() || Subtarget.isPPC64()) if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
} else { } else {
// PowerPC does not have FP_TO_UINT on 32-bit implementations. // PowerPC does not have FP_TO_UINT on 32-bit implementations.
if (Subtarget.hasSPE()) if (Subtarget.hasSPE()) {
setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Legal);
setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal); setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
else } else
setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
} }
// With the instructions enabled under FPCVT, we can do everything. // With the instructions enabled under FPCVT, we can do everything.
if (Subtarget.hasFPCVT()) { if (Subtarget.hasFPCVT()) {
if (Subtarget.has64BitSupport()) { if (Subtarget.has64BitSupport()) {
setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom); setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
▲ Show 20 Lines • Show All 16,555 Lines • Show Last 20 Lines

llvm/lib/Target/PowerPC/PPCInstrSPE.td

Show First 20 Lines • Show All 152 Lines • ▼ Show 20 Linesdef EFDCFS : EFXForm_2a<751, (outs sperc:$RT), (ins spe4rc:$RB),
"efdcfs $RT, $RB", IIC_FPDGeneral, "efdcfs $RT, $RB", IIC_FPDGeneral,
[(set f64:$RT, (fpextend f32:$RB))]>; [(set f64:$RT, (fpextend f32:$RB))]>;
def EFDCFSF : EFXForm_2a<755, (outs sperc:$RT), (ins spe4rc:$RB), def EFDCFSF : EFXForm_2a<755, (outs sperc:$RT), (ins spe4rc:$RB),
"efdcfsf $RT, $RB", IIC_FPDGeneral, []>; "efdcfsf $RT, $RB", IIC_FPDGeneral, []>;
def EFDCFSI : EFXForm_2a<753, (outs sperc:$RT), (ins gprc:$RB), def EFDCFSI : EFXForm_2a<753, (outs sperc:$RT), (ins gprc:$RB),
"efdcfsi $RT, $RB", IIC_FPDGeneral, "efdcfsi $RT, $RB", IIC_FPDGeneral,
[(set f64:$RT, (sint_to_fp i32:$RB))]>; [(set f64:$RT, (any_sint_to_fp i32:$RB))]>;
def EFDCFSID : EFXForm_2a<739, (outs sperc:$RT), (ins gprc:$RB), def EFDCFSID : EFXForm_2a<739, (outs sperc:$RT), (ins gprc:$RB),
"efdcfsid $RT, $RB", IIC_FPDGeneral, "efdcfsid $RT, $RB", IIC_FPDGeneral,
[]>; []>;
def EFDCFUF : EFXForm_2a<754, (outs sperc:$RT), (ins spe4rc:$RB), def EFDCFUF : EFXForm_2a<754, (outs sperc:$RT), (ins spe4rc:$RB),
"efdcfuf $RT, $RB", IIC_FPDGeneral, []>; "efdcfuf $RT, $RB", IIC_FPDGeneral, []>;
def EFDCFUI : EFXForm_2a<752, (outs sperc:$RT), (ins gprc:$RB), def EFDCFUI : EFXForm_2a<752, (outs sperc:$RT), (ins gprc:$RB),
"efdcfui $RT, $RB", IIC_FPDGeneral, "efdcfui $RT, $RB", IIC_FPDGeneral,
[(set f64:$RT, (uint_to_fp i32:$RB))]>; [(set f64:$RT, (any_uint_to_fp i32:$RB))]>;
def EFDCFUID : EFXForm_2a<738, (outs sperc:$RT), (ins gprc:$RB), def EFDCFUID : EFXForm_2a<738, (outs sperc:$RT), (ins gprc:$RB),
"efdcfuid $RT, $RB", IIC_FPDGeneral, "efdcfuid $RT, $RB", IIC_FPDGeneral,
[]>; []>;
let isCompare = 1 in { let isCompare = 1 in {
def EFDCMPEQ : EFXForm_3<750, (outs crrc:$crD), (ins sperc:$RA, sperc:$RB), def EFDCMPEQ : EFXForm_3<750, (outs crrc:$crD), (ins sperc:$RA, sperc:$RB),
"efdcmpeq $crD, $RA, $RB", IIC_FPDGeneral>; "efdcmpeq $crD, $RA, $RB", IIC_FPDGeneral>;
Show All 11 Linesdef EFDCTSI : EFXForm_2a<757, (outs gprc:$RT), (ins sperc:$RB),
[]>; []>;
def EFDCTSIDZ : EFXForm_2a<747, (outs gprc:$RT), (ins sperc:$RB), def EFDCTSIDZ : EFXForm_2a<747, (outs gprc:$RT), (ins sperc:$RB),
"efdctsidz $RT, $RB", IIC_FPDGeneral, "efdctsidz $RT, $RB", IIC_FPDGeneral,
[]>; []>;
def EFDCTSIZ : EFXForm_2a<762, (outs gprc:$RT), (ins sperc:$RB), def EFDCTSIZ : EFXForm_2a<762, (outs gprc:$RT), (ins sperc:$RB),
"efdctsiz $RT, $RB", IIC_FPDGeneral, "efdctsiz $RT, $RB", IIC_FPDGeneral,
[(set i32:$RT, (fp_to_sint f64:$RB))]>; [(set i32:$RT, (any_fp_to_sint f64:$RB))]>;
def EFDCTUF : EFXForm_2a<758, (outs sperc:$RT), (ins spe4rc:$RB), def EFDCTUF : EFXForm_2a<758, (outs sperc:$RT), (ins spe4rc:$RB),
"efdctuf $RT, $RB", IIC_FPDGeneral, []>; "efdctuf $RT, $RB", IIC_FPDGeneral, []>;
def EFDCTUI : EFXForm_2a<756, (outs gprc:$RT), (ins sperc:$RB), def EFDCTUI : EFXForm_2a<756, (outs gprc:$RT), (ins sperc:$RB),
"efdctui $RT, $RB", IIC_FPDGeneral, "efdctui $RT, $RB", IIC_FPDGeneral,
[]>; []>;
def EFDCTUIDZ : EFXForm_2a<746, (outs gprc:$RT), (ins sperc:$RB), def EFDCTUIDZ : EFXForm_2a<746, (outs gprc:$RT), (ins sperc:$RB),
"efdctuidz $RT, $RB", IIC_FPDGeneral, "efdctuidz $RT, $RB", IIC_FPDGeneral,
[]>; []>;
def EFDCTUIZ : EFXForm_2a<760, (outs gprc:$RT), (ins sperc:$RB), def EFDCTUIZ : EFXForm_2a<760, (outs gprc:$RT), (ins sperc:$RB),
"efdctuiz $RT, $RB", IIC_FPDGeneral, "efdctuiz $RT, $RB", IIC_FPDGeneral,
[(set i32:$RT, (fp_to_uint f64:$RB))]>; [(set i32:$RT, (any_fp_to_uint f64:$RB))]>;
def EFDDIV : EFXForm_1<745, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB), def EFDDIV : EFXForm_1<745, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"efddiv $RT, $RA, $RB", IIC_FPDivD, "efddiv $RT, $RA, $RB", IIC_FPDivD,
[(set f64:$RT, (fdiv f64:$RA, f64:$RB))]>; [(set f64:$RT, (fdiv f64:$RA, f64:$RB))]>;
def EFDMUL : EFXForm_1<744, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB), def EFDMUL : EFXForm_1<744, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
"efdmul $RT, $RA, $RB", IIC_FPDGeneral, "efdmul $RT, $RA, $RB", IIC_FPDGeneral,
[(set f64:$RT, (fmul f64:$RA, f64:$RB))]>; [(set f64:$RT, (fmul f64:$RA, f64:$RB))]>;
Show All 32 Linesdef EFSCFD : EFXForm_2a<719, (outs spe4rc:$RT), (ins sperc:$RB),
"efscfd $RT, $RB", IIC_FPSGeneral, "efscfd $RT, $RB", IIC_FPSGeneral,
[(set f32:$RT, (fpround f64:$RB))]>; [(set f32:$RT, (fpround f64:$RB))]>;
def EFSCFSF : EFXForm_2a<723, (outs spe4rc:$RT), (ins spe4rc:$RB), def EFSCFSF : EFXForm_2a<723, (outs spe4rc:$RT), (ins spe4rc:$RB),
"efscfsf $RT, $RB", IIC_FPSGeneral, []>; "efscfsf $RT, $RB", IIC_FPSGeneral, []>;
def EFSCFSI : EFXForm_2a<721, (outs spe4rc:$RT), (ins gprc:$RB), def EFSCFSI : EFXForm_2a<721, (outs spe4rc:$RT), (ins gprc:$RB),
"efscfsi $RT, $RB", IIC_FPSGeneral, "efscfsi $RT, $RB", IIC_FPSGeneral,
[(set f32:$RT, (sint_to_fp i32:$RB))]>; [(set f32:$RT, (any_sint_to_fp i32:$RB))]>;
def EFSCFUF : EFXForm_2a<722, (outs spe4rc:$RT), (ins spe4rc:$RB), def EFSCFUF : EFXForm_2a<722, (outs spe4rc:$RT), (ins spe4rc:$RB),
"efscfuf $RT, $RB", IIC_FPSGeneral, []>; "efscfuf $RT, $RB", IIC_FPSGeneral, []>;
def EFSCFUI : EFXForm_2a<720, (outs spe4rc:$RT), (ins gprc:$RB), def EFSCFUI : EFXForm_2a<720, (outs spe4rc:$RT), (ins gprc:$RB),
"efscfui $RT, $RB", IIC_FPSGeneral, "efscfui $RT, $RB", IIC_FPSGeneral,
[(set f32:$RT, (uint_to_fp i32:$RB))]>; [(set f32:$RT, (any_uint_to_fp i32:$RB))]>;
let isCompare = 1 in { let isCompare = 1 in {
def EFSCMPEQ : EFXForm_3<718, (outs crrc:$crD), (ins spe4rc:$RA, spe4rc:$RB), def EFSCMPEQ : EFXForm_3<718, (outs crrc:$crD), (ins spe4rc:$RA, spe4rc:$RB),
"efscmpeq $crD, $RA, $RB", IIC_FPCompare>; "efscmpeq $crD, $RA, $RB", IIC_FPCompare>;
def EFSCMPGT : EFXForm_3<716, (outs crrc:$crD), (ins spe4rc:$RA, spe4rc:$RB), def EFSCMPGT : EFXForm_3<716, (outs crrc:$crD), (ins spe4rc:$RA, spe4rc:$RB),
"efscmpgt $crD, $RA, $RB", IIC_FPCompare>; "efscmpgt $crD, $RA, $RB", IIC_FPCompare>;
def EFSCMPLT : EFXForm_3<717, (outs crrc:$crD), (ins spe4rc:$RA, spe4rc:$RB), def EFSCMPLT : EFXForm_3<717, (outs crrc:$crD), (ins spe4rc:$RA, spe4rc:$RB),
"efscmplt $crD, $RA, $RB", IIC_FPCompare>; "efscmplt $crD, $RA, $RB", IIC_FPCompare>;
} }
def EFSCTSF : EFXForm_2a<727, (outs spe4rc:$RT), (ins spe4rc:$RB), def EFSCTSF : EFXForm_2a<727, (outs spe4rc:$RT), (ins spe4rc:$RB),
"efsctsf $RT, $RB", IIC_FPSGeneral, []>; "efsctsf $RT, $RB", IIC_FPSGeneral, []>;
def EFSCTSI : EFXForm_2a<725, (outs gprc:$RT), (ins spe4rc:$RB), def EFSCTSI : EFXForm_2a<725, (outs gprc:$RT), (ins spe4rc:$RB),
"efsctsi $RT, $RB", IIC_FPSGeneral, "efsctsi $RT, $RB", IIC_FPSGeneral,
[]>; []>;
def EFSCTSIZ : EFXForm_2a<730, (outs gprc:$RT), (ins spe4rc:$RB), def EFSCTSIZ : EFXForm_2a<730, (outs gprc:$RT), (ins spe4rc:$RB),
"efsctsiz $RT, $RB", IIC_FPSGeneral, "efsctsiz $RT, $RB", IIC_FPSGeneral,
[(set i32:$RT, (fp_to_sint f32:$RB))]>; [(set i32:$RT, (any_fp_to_sint f32:$RB))]>;
def EFSCTUF : EFXForm_2a<726, (outs sperc:$RT), (ins spe4rc:$RB), def EFSCTUF : EFXForm_2a<726, (outs sperc:$RT), (ins spe4rc:$RB),
"efsctuf $RT, $RB", IIC_FPSGeneral, []>; "efsctuf $RT, $RB", IIC_FPSGeneral, []>;
def EFSCTUI : EFXForm_2a<724, (outs gprc:$RT), (ins spe4rc:$RB), def EFSCTUI : EFXForm_2a<724, (outs gprc:$RT), (ins spe4rc:$RB),
"efsctui $RT, $RB", IIC_FPSGeneral, "efsctui $RT, $RB", IIC_FPSGeneral,
[]>; []>;
def EFSCTUIZ : EFXForm_2a<728, (outs gprc:$RT), (ins spe4rc:$RB), def EFSCTUIZ : EFXForm_2a<728, (outs gprc:$RT), (ins spe4rc:$RB),
"efsctuiz $RT, $RB", IIC_FPSGeneral, "efsctuiz $RT, $RB", IIC_FPSGeneral,
[(set i32:$RT, (fp_to_uint f32:$RB))]>; [(set i32:$RT, (any_fp_to_uint f32:$RB))]>;
def EFSDIV : EFXForm_1<713, (outs spe4rc:$RT), (ins spe4rc:$RA, spe4rc:$RB), def EFSDIV : EFXForm_1<713, (outs spe4rc:$RT), (ins spe4rc:$RA, spe4rc:$RB),
"efsdiv $RT, $RA, $RB", IIC_FPDivD, "efsdiv $RT, $RA, $RB", IIC_FPDivD,
[(set f32:$RT, (fdiv f32:$RA, f32:$RB))]>; [(set f32:$RT, (fdiv f32:$RA, f32:$RB))]>;
def EFSMUL : EFXForm_1<712, (outs spe4rc:$RT), (ins spe4rc:$RA, spe4rc:$RB), def EFSMUL : EFXForm_1<712, (outs spe4rc:$RT), (ins spe4rc:$RA, spe4rc:$RB),
"efsmul $RT, $RA, $RB", IIC_FPGeneral, "efsmul $RT, $RA, $RB", IIC_FPGeneral,
[(set f32:$RT, (fmul f32:$RA, f32:$RB))]>; [(set f32:$RT, (fmul f32:$RA, f32:$RB))]>;
▲ Show 20 Lines • Show All 589 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/fp-strict-conv.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names < %s -mcpu=e500 \
; RUN: -mtriple=powerpc-unknown-linux-gnu -mattr=spe | FileCheck %s \
; RUN: -check-prefix=SPE
declare i32 @llvm.experimental.constrained.fptosi.i32.f64(double, metadata)
declare i64 @llvm.experimental.constrained.fptosi.i64.f64(double, metadata)
declare i64 @llvm.experimental.constrained.fptoui.i64.f64(double, metadata)
declare i32 @llvm.experimental.constrained.fptoui.i32.f64(double, metadata)
declare i32 @llvm.experimental.constrained.fptosi.i32.f32(float, metadata)
declare i64 @llvm.experimental.constrained.fptosi.i64.f32(float, metadata)
declare i64 @llvm.experimental.constrained.fptoui.i64.f32(float, metadata)
declare i32 @llvm.experimental.constrained.fptoui.i32.f32(float, metadata)
declare double @llvm.experimental.constrained.sitofp.f64.i32(i32, metadata, metadata)
declare double @llvm.experimental.constrained.sitofp.f64.i64(i64, metadata, metadata)
declare double @llvm.experimental.constrained.uitofp.f64.i32(i32, metadata, metadata)
declare double @llvm.experimental.constrained.uitofp.f64.i64(i64, metadata, metadata)
declare float @llvm.experimental.constrained.sitofp.f32.i64(i64, metadata, metadata)
declare float @llvm.experimental.constrained.sitofp.f32.i32(i32, metadata, metadata)
declare float @llvm.experimental.constrained.uitofp.f32.i32(i32, metadata, metadata)
declare float @llvm.experimental.constrained.uitofp.f32.i64(i64, metadata, metadata)
define i32 @d_to_i32(double %m) #0 {
; SPE-LABEL: d_to_i32:
; SPE: # %bb.0: # %entry
; SPE-NEXT: evmergelo r3, r3, r4
; SPE-NEXT: efdctsiz r3, r3
; SPE-NEXT: blr
entry:
%conv = call i32 @llvm.experimental.constrained.fptosi.i32.f64(double %m, metadata !"fpexcept.strict") #0
ret i32 %conv
}
define i64 @d_to_i64(double %m) #0 {
; SPE-LABEL: d_to_i64:
; SPE: # %bb.0: # %entry
; SPE-NEXT: mflr r0
; SPE-NEXT: stw r0, 4(r1)
; SPE-NEXT: stwu r1, -16(r1)
; SPE-NEXT: .cfi_def_cfa_offset 16
; SPE-NEXT: .cfi_offset lr, 4
; SPE-NEXT: evmergelo r4, r3, r4
; SPE-NEXT: evmergehi r3, r4, r4
; SPE-NEXT: # kill: def $r4 killed $r4 killed $s4
; SPE-NEXT: # kill: def $r3 killed $r3 killed $s3
; SPE-NEXT: bl __fixdfdi
; SPE-NEXT: lwz r0, 20(r1)
; SPE-NEXT: addi r1, r1, 16
; SPE-NEXT: mtlr r0
; SPE-NEXT: blr
entry:
%conv = call i64 @llvm.experimental.constrained.fptosi.i64.f64(double %m, metadata !"fpexcept.strict") #0
ret i64 %conv
}
define i64 @d_to_u64(double %m) #0 {
; SPE-LABEL: d_to_u64:
; SPE: # %bb.0: # %entry
; SPE-NEXT: mflr r0
; SPE-NEXT: stw r0, 4(r1)
; SPE-NEXT: stwu r1, -16(r1)
; SPE-NEXT: .cfi_def_cfa_offset 16
; SPE-NEXT: .cfi_offset lr, 4
; SPE-NEXT: evmergelo r4, r3, r4
; SPE-NEXT: evmergehi r3, r4, r4
; SPE-NEXT: # kill: def $r4 killed $r4 killed $s4
; SPE-NEXT: # kill: def $r3 killed $r3 killed $s3
; SPE-NEXT: bl __fixunsdfdi
; SPE-NEXT: lwz r0, 20(r1)
; SPE-NEXT: addi r1, r1, 16
; SPE-NEXT: mtlr r0
; SPE-NEXT: blr
entry:
%conv = call i64 @llvm.experimental.constrained.fptoui.i64.f64(double %m, metadata !"fpexcept.strict") #0
ret i64 %conv
}
define zeroext i32 @d_to_u32(double %m) #0 {
; SPE-LABEL: d_to_u32:
; SPE: # %bb.0: # %entry
; SPE-NEXT: evmergelo r3, r3, r4
; SPE-NEXT: efdctuiz r3, r3
; SPE-NEXT: blr
entry:
%conv = call i32 @llvm.experimental.constrained.fptoui.i32.f64(double %m, metadata !"fpexcept.strict") #0
ret i32 %conv
}
define signext i32 @f_to_i32(float %m) #0 {
; SPE-LABEL: f_to_i32:
; SPE: # %bb.0: # %entry
; SPE-NEXT: efsctsiz r3, r3
; SPE-NEXT: blr
entry:
%conv = call i32 @llvm.experimental.constrained.fptosi.i32.f32(float %m, metadata !"fpexcept.strict") #0
ret i32 %conv
}
define i64 @f_to_i64(float %m) #0 {
; SPE-LABEL: f_to_i64:
; SPE: # %bb.0: # %entry
; SPE-NEXT: mflr r0
; SPE-NEXT: stw r0, 4(r1)
; SPE-NEXT: stwu r1, -16(r1)
; SPE-NEXT: .cfi_def_cfa_offset 16
; SPE-NEXT: .cfi_offset lr, 4
; SPE-NEXT: bl __fixsfdi
; SPE-NEXT: lwz r0, 20(r1)
; SPE-NEXT: addi r1, r1, 16
; SPE-NEXT: mtlr r0
; SPE-NEXT: blr
entry:
%conv = call i64 @llvm.experimental.constrained.fptosi.i64.f32(float %m, metadata !"fpexcept.strict") #0
ret i64 %conv
}
define i64 @f_to_u64(float %m) #0 {
; SPE-LABEL: f_to_u64:
; SPE: # %bb.0: # %entry
; SPE-NEXT: mflr r0
; SPE-NEXT: stw r0, 4(r1)
; SPE-NEXT: stwu r1, -16(r1)
; SPE-NEXT: .cfi_def_cfa_offset 16
; SPE-NEXT: .cfi_offset lr, 4
; SPE-NEXT: bl __fixunssfdi
; SPE-NEXT: lwz r0, 20(r1)
; SPE-NEXT: addi r1, r1, 16
; SPE-NEXT: mtlr r0
; SPE-NEXT: blr
entry:
%conv = call i64 @llvm.experimental.constrained.fptoui.i64.f32(float %m, metadata !"fpexcept.strict") #0
ret i64 %conv
}
define zeroext i32 @f_to_u32(float %m) #0 {
; SPE-LABEL: f_to_u32:
; SPE: # %bb.0: # %entry
; SPE-NEXT: efsctuiz r3, r3
; SPE-NEXT: blr
entry:
%conv = call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %m, metadata !"fpexcept.strict") #0
ret i32 %conv
}
define double @i32_to_d(i32 signext %m) #0 {
; SPE-LABEL: i32_to_d:
; SPE: # %bb.0: # %entry
; SPE-NEXT: efdcfsi r4, r3
; SPE-NEXT: evmergehi r3, r4, r4
; SPE-NEXT: # kill: def $r4 killed $r4 killed $s4
; SPE-NEXT: # kill: def $r3 killed $r3 killed $s3
; SPE-NEXT: blr
entry:
%conv = tail call double @llvm.experimental.constrained.sitofp.f64.i32(i32 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
ret double %conv
}
define double @i64_to_d(i64 %m) #0 {
; SPE-LABEL: i64_to_d:
; SPE: # %bb.0: # %entry
; SPE-NEXT: mflr r0
; SPE-NEXT: stw r0, 4(r1)
; SPE-NEXT: stwu r1, -16(r1)
; SPE-NEXT: .cfi_def_cfa_offset 16
; SPE-NEXT: .cfi_offset lr, 4
; SPE-NEXT: bl __floatdidf
; SPE-NEXT: evmergelo r4, r3, r4
; SPE-NEXT: evmergehi r3, r4, r4
; SPE-NEXT: lwz r0, 20(r1)
; SPE-NEXT: # kill: def $r3 killed $r3 killed $s3
; SPE-NEXT: # kill: def $r4 killed $r4 killed $s4
; SPE-NEXT: addi r1, r1, 16
; SPE-NEXT: mtlr r0
; SPE-NEXT: blr
entry:
%conv = tail call double @llvm.experimental.constrained.sitofp.f64.i64(i64 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
ret double %conv
}
define double @u32_to_d(i32 zeroext %m) #0 {
; SPE-LABEL: u32_to_d:
; SPE: # %bb.0: # %entry
; SPE-NEXT: efdcfui r4, r3
; SPE-NEXT: evmergehi r3, r4, r4
; SPE-NEXT: # kill: def $r4 killed $r4 killed $s4
; SPE-NEXT: # kill: def $r3 killed $r3 killed $s3
; SPE-NEXT: blr
entry:
%conv = tail call double @llvm.experimental.constrained.uitofp.f64.i32(i32 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
ret double %conv
}
define double @u64_to_d(i64 %m) #0 {
; SPE-LABEL: u64_to_d:
; SPE: # %bb.0: # %entry
; SPE-NEXT: mflr r0
; SPE-NEXT: stw r0, 4(r1)
; SPE-NEXT: stwu r1, -16(r1)
; SPE-NEXT: .cfi_def_cfa_offset 16
; SPE-NEXT: .cfi_offset lr, 4
; SPE-NEXT: bl __floatundidf
; SPE-NEXT: evmergelo r4, r3, r4
; SPE-NEXT: evmergehi r3, r4, r4
; SPE-NEXT: lwz r0, 20(r1)
; SPE-NEXT: # kill: def $r3 killed $r3 killed $s3
; SPE-NEXT: # kill: def $r4 killed $r4 killed $s4
; SPE-NEXT: addi r1, r1, 16
; SPE-NEXT: mtlr r0
; SPE-NEXT: blr
entry:
%conv = tail call double @llvm.experimental.constrained.uitofp.f64.i64(i64 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
ret double %conv
}
define float @i32_to_f(i32 signext %m) #0 {
; SPE-LABEL: i32_to_f:
; SPE: # %bb.0: # %entry
; SPE-NEXT: efscfsi r3, r3
; SPE-NEXT: blr
entry:
%conv = tail call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
ret float %conv
}
define float @i64_to_f(i64 %m) #0 {
; SPE-LABEL: i64_to_f:
; SPE: # %bb.0: # %entry
; SPE-NEXT: mflr r0
; SPE-NEXT: stw r0, 4(r1)
; SPE-NEXT: stwu r1, -16(r1)
; SPE-NEXT: .cfi_def_cfa_offset 16
; SPE-NEXT: .cfi_offset lr, 4
; SPE-NEXT: bl __floatdisf
; SPE-NEXT: lwz r0, 20(r1)
; SPE-NEXT: addi r1, r1, 16
; SPE-NEXT: mtlr r0
; SPE-NEXT: blr
entry:
%conv = tail call float @llvm.experimental.constrained.sitofp.f32.i64(i64 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
ret float %conv
}
define float @u32_to_f(i32 zeroext %m) #0 {
; SPE-LABEL: u32_to_f:
; SPE: # %bb.0: # %entry
; SPE-NEXT: efscfui r3, r3
; SPE-NEXT: blr
entry:
%conv = tail call float @llvm.experimental.constrained.uitofp.f32.i32(i32 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
ret float %conv
}
define float @u64_to_f(i64 %m) #0 {
; SPE-LABEL: u64_to_f:
; SPE: # %bb.0: # %entry
; SPE-NEXT: mflr r0
; SPE-NEXT: stw r0, 4(r1)
; SPE-NEXT: stwu r1, -16(r1)
; SPE-NEXT: .cfi_def_cfa_offset 16
; SPE-NEXT: .cfi_offset lr, 4
; SPE-NEXT: bl __floatundisf
; SPE-NEXT: lwz r0, 20(r1)
; SPE-NEXT: addi r1, r1, 16
; SPE-NEXT: mtlr r0
; SPE-NEXT: blr
entry:
%conv = tail call float @llvm.experimental.constrained.uitofp.f32.i64(i64 %m, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
ret float %conv
}
attributes #0 = { strictfp }