[CodeGen] Have CodeGen for fixed-point unsigned with padding emit signed operations.

[ebevhan]

Summary

The design of unsigned fixed-point with padding did not really
work as originally intended downstream.

The issue with the design is that the concept of the unsigned
padding bit disappears in the transition to IR. On the LLVM
level, there is no padding bit and anything goes with the
operations. This has the unfortunate effect of generating
invalid operations during ISel for operations that a target
should be perfectly capable of selecting for.

For example, for an unsigned saturating _Fract division of
width 16, we emit IR for an i15 udiv.fix.sat. In the legalization
of this operation in ISel, the operand and result are promoted
to i16, and to preserve the saturating behavior, the LHS is
shifted left by 1.

However... This means that we now have a division operation
with a significant value in the LHS MSB. If the target could
select this, there would be no meaning to the padding bit.
Considering that ISel will always promote this due to type
illegality, there's no way around the production of illegal
operations.

This patch changes CodeGen to emit signed operations when
emitting code for unsigned with padding. At least for us
downstream, being able to reuse the signed instructions is
the one of the points of having the padding bit, so this
design seems to align better.

[ebevhan]

Fixed some broken CHECK lines.

[rjmccall]

Why not legalize to the signed operation?

[ebevhan]

In D82663#2117451, @rjmccall wrote:

Why not legalize to the signed operation?

My feeling was that it wasn't right do so in LLVM, because LLVM has no notion of the padding bit and therefore doesn't really care about Clang's rationale for doing the legalization that way.
If an illegal udiv.fix.sat needs to be legalized via promotion, it makes more sense to legalize it to another unsigned operation rather than arbitrarily doing it as a signed one.

I guess it could be done in cases where the resulting signed operation was legal and the unsigned one was not, but that isn't testable upstream since none of the operations are legal on upstream targets.

[ebevhan]

Another point is, if we for example have an i16 umul.fix in legalization, we have no way of knowing in the general case that it is safe to replace it with an smul.fix, since the information that the MSB is not significant does not exist on IR level. This is the 'loss of padding bit' that I'm referring to.

[rjmccall]

Can the missing bit just be added? It seems to me that frontends ought to be able to emit the obvious intrinsic for the semantic operation here rather than having to second-guess the backend.

[ebevhan]

Well, it's not so much as adding the bit, but adding the information that the bit exists. That means either new intrinsics for all of the operations, or adding flags to the existing ones. That's a fair bit of added complexity. Also, <signed operation> + <clamp to zero> would do virtually the exact same thing as the new unsigned-with-padding operations, so the utility of adding all of it is a bit questionable.

[ebevhan]

Rebased.

[leonardchan]

In D82663#2130355, @ebevhan wrote:

Well, it's not so much as adding the bit, but adding the information that the bit exists. That means either new intrinsics for all of the operations, or adding flags to the existing ones. That's a fair bit of added complexity. Also, <signed operation> + <clamp to zero> would do virtually the exact same thing as the new unsigned-with-padding operations, so the utility of adding all of it is a bit questionable.

Could the work involved just be adding the flags, then in llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp for unsigned operations, choosing between the signed/unsigned underlying ISD when lowering intrinsics to DAG? I think you could just pass the padding bit to FixedPointIntrinsicToOpcode and handle it from there. This is just off the top of my head so I could be missing other things.

I don't think this is necessarily the same as "legalizing" the intrinsic, but this would at least prevent frontends from second-guessing.

clang/include/clang/Basic/FixedPoint.h

66

Is -> If

clang/lib/Basic/FixedPoint.cpp

143–158

If this is exclusively for codegen purposes with binary operations, would it be clearer to move this to EmitFixedPointBinOp? If UnsignedPaddingIsSigned doesn't need to be used for stuff like constant evaluation, it might be clearer not to provide it for everyone.

clang/test/Frontend/fixed_point_add.c

290–294

If this is a workaround for not being able to convey the padding bit to LLVM intrinsics, I think we should only limit changes to instances we would use intrinsics.

[ebevhan]

In D82663#2140507, @leonardchan wrote:

In D82663#2130355, @ebevhan wrote:

Well, it's not so much as adding the bit, but adding the information that the bit exists. That means either new intrinsics for all of the operations, or adding flags to the existing ones. That's a fair bit of added complexity. Also, <signed operation> + <clamp to zero> would do virtually the exact same thing as the new unsigned-with-padding operations, so the utility of adding all of it is a bit questionable.

Could the work involved just be adding the flags, then in llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp for unsigned operations, choosing between the signed/unsigned underlying ISD when lowering intrinsics to DAG? I think you could just pass the padding bit to FixedPointIntrinsicToOpcode and handle it from there. This is just off the top of my head so I could be missing other things.

It wouldn't just be restricted to fixed-point intrinsics, though. It would have to be added to intrinsics like uadd.sat and usub.sat as well, which aren't really tied to fixed-point at all. Changing the semantics of those intrinsics would be unfortunate for targets that have started using them for their own instructions. I don't really think it's an option to move the padding semantic info into the IR; the intrinsic interface is fairly lean, and I think keeping it that way is a good idea.

I could change the emission to not be so heavy-handed and only use signed operations for the intrinsics, rather than everything. That makes EmitFixedPointBinOp a bit messier, though.

clang/lib/Basic/FixedPoint.cpp

143–158

FixedPointSemantics is immutable except for saturation, unfortunately. I'd end up having to reconstruct the semantics object from scratch immediately after calling getCommonSemantics.

clang/test/Frontend/fixed_point_add.c

290–294

I suppose this makes sense, but the logic will be a bit more convoluted in that case.

It is true that in most cases, the clamp-to-zero resulting from the signed->unsigned conversion at the end isn't even necessary. For addition, multiplication, division and shift, the result of positive operands can never become negative, so there's no point to the clamp.

It just felt more general to do it for all of them instead of littering EmitFixedPointBinOp with special cases. But perhaps it would be better to deal with each case individually instead. Still feels like that would make the implementation less clean.

[leonardchan]

It wouldn't just be restricted to fixed-point intrinsics, though. It would have to be added to intrinsics like uadd.sat and usub.sat as well, which aren't really tied to fixed-point at all.

Oh wait, sorry. I think I'm starting to understand now. You're saying that if you're using the padding bit in the first place, ISel shouldn't need to perform the underlying shift during integral promotions, but we do it anyway still. Yeah it seems a lot of this could be addressed simply by just using the corresponding signed intrinsics.

I guess I'd be ok with purely making this a clang change for now, but if other frontends see interest in the unsigned padding bit then we could migrate this to LLVM down the line.

clang/lib/Basic/FixedPoint.cpp

143–158

Fair.

Minor nit: Could you rename the parameter to UnsignedPaddingIsSignedForCG? Just want to make it clearer that this should specifically be used for codegen only.

[rjmccall]

Would it be sensible to use a technical design more like what the matrix folks are doing, where LLVM provides a small interface for emitting operations with various semantics? FixedPointSemantics would move to that header, and Clang would just call into it. That way you get a lot more flexibility in how you generate code, and the Clang IRGen logic is still transparently correct. If you want to add intrinsics or otherwise change the IR patterns used for various operations, you don't have to rewrite a bunch of Clang IRGen logic every time, you just have to update the tests. It'd then be pretty straightforward to have internal helper functions in that interface for computing things like whether you should use signed or unsigned intrinsics given the desired FixedPointSemantics.

My interest here is mainly in (1) keeping IRGen's logic as obviously correct as possible, (2) not hard-coding a bunch of things that really feel like workarounds for backend limitations, and (3) not complicating core abstractions like FixedPointSemantics with unnecessary extra rules for appropriate use, like having to pass an extra "for codegen" flag to get optimal codegen. If IRGen can just pass down the high-level semantics it wants to some library that will make intelligent decisions about how to emit IR, that seems best.

[ebevhan]

In D82663#2142426, @rjmccall wrote:

Would it be sensible to use a technical design more like what the matrix folks are doing, where LLVM provides a small interface for emitting operations with various semantics? FixedPointSemantics would move to that header, and Clang would just call into it. That way you get a lot more flexibility in how you generate code, and the Clang IRGen logic is still transparently correct. If you want to add intrinsics or otherwise change the IR patterns used for various operations, you don't have to rewrite a bunch of Clang IRGen logic every time, you just have to update the tests. It'd then be pretty straightforward to have internal helper functions in that interface for computing things like whether you should use signed or unsigned intrinsics given the desired FixedPointSemantics.

This seems like a reasonable thing to do for other reasons as well. Also moving the actual APFixedPoint class to LLVM would make it easier to reuse the fixedpoint calculation code for constant folding in LLVM, for example.

My interest here is mainly in (1) keeping IRGen's logic as obviously correct as possible, (2) not hard-coding a bunch of things that really feel like workarounds for backend limitations, and (3) not complicating core abstractions like FixedPointSemantics with unnecessary extra rules for appropriate use, like having to pass an extra "for codegen" flag to get optimal codegen. If IRGen can just pass down the high-level semantics it wants to some library that will make intelligent decisions about how to emit IR, that seems best.

Just to clarify something here; would the interface in LLVM still emit signed operations for unsigned with padding? If so, why does dealing with the padding bit detail in LLVM rather than Clang make more sense? The regular IRBuilder is relatively straightforward in its behavior. I suspect that if anything, LLVM would be equally unwilling to take to take IRBuilder patches that emitted signed intrinsics for certain unsigned operations only due to a detail in Embedded-C's implementation of fixedpoint support.

I could remove the special behavior from FixedPointSemantics and only deal with it in EmitFixedPointBinOp instead. I agree that the FixedPointSemantics interface is muddied by the extra parameter.
Unless I alter the semantics object it might make EmitFixedPointBinOp rather messy, though.

---

Regarding backend limitations, I guess I could propose an alternate solution. If we change FixedPointSemantics to strip the padding bit for both saturating and nonsaturating operations, it may be possible to detect in isel that the corresponding signed operation could be used instead when we promote the type of an unsigned one. For example, if we emit i15 umul.fix scale 15, we could tell in lowering that i16 smul.fix scale 15 is legal and use that instead. Same for all the other intrinsics, including the non-fixedpoint uadd.sat/usub.sat.

The issue with this approach (which is why I didn't really want to do it) is that it's not testable. No upstream target has these intrinsics marked as legal. I doubt anyone would accept a patch with no tests.
It may also be less efficient than just emitting the signed operations in the first place, because we are forced to trunc and zext in IR before and after every operation.

[rjmccall]

In D82663#2144219, @ebevhan wrote:

In D82663#2142426, @rjmccall wrote:

Would it be sensible to use a technical design more like what the matrix folks are doing, where LLVM provides a small interface for emitting operations with various semantics? FixedPointSemantics would move to that header, and Clang would just call into it. That way you get a lot more flexibility in how you generate code, and the Clang IRGen logic is still transparently correct. If you want to add intrinsics or otherwise change the IR patterns used for various operations, you don't have to rewrite a bunch of Clang IRGen logic every time, you just have to update the tests. It'd then be pretty straightforward to have internal helper functions in that interface for computing things like whether you should use signed or unsigned intrinsics given the desired FixedPointSemantics.

This seems like a reasonable thing to do for other reasons as well. Also moving the actual APFixedPoint class to LLVM would make it easier to reuse the fixedpoint calculation code for constant folding in LLVM, for example.

Just to say "I told you so", I'm pretty sure I told people this would happen. :)

My interest here is mainly in (1) keeping IRGen's logic as obviously correct as possible, (2) not hard-coding a bunch of things that really feel like workarounds for backend limitations, and (3) not complicating core abstractions like FixedPointSemantics with unnecessary extra rules for appropriate use, like having to pass an extra "for codegen" flag to get optimal codegen. If IRGen can just pass down the high-level semantics it wants to some library that will make intelligent decisions about how to emit IR, that seems best.

Just to clarify something here; would the interface in LLVM still emit signed operations for unsigned with padding?

If that's the best IR pattern to emit, yes.

If so, why does dealing with the padding bit detail in LLVM rather than Clang make more sense?

Because frontends should be able to just say "I have a value of a type with these semantics, I need you to do these operations, go do them". The whole purpose of this interface would be to go down a level of abstraction by picking the best IR to represent those operations.

Maybe we're not in agreement about what this interface looks like — I'm imagining something like

struct FixedPointEmitter {
  IRBuilder &B;
  FixedPointEmitter(IRBuilder &B) : B(B) {}

  Value *convert(Value *src, FixedPointSemantics srcSemantics, FixedPointSemantics destSemantics);
  Value *add(Value *lhs, FixedPointSemantics lhsSemantics, Value *rhs, FixedPointSemantics rhsSemantics)
};

The regular IRBuilder is relatively straightforward in its behavior. I suspect that if anything, LLVM would be equally unwilling to take to take IRBuilder patches that emitted signed intrinsics for certain unsigned operations only due to a detail in Embedded-C's implementation of fixedpoint support.

Most things in IRBuilder don't have variant representations beyond what's expressed by the value type. The fact that we've chosen to do so here necessitates a more complex interface.

Regarding backend limitations, I guess I could propose an alternate solution. If we change FixedPointSemantics to strip the padding bit for both saturating and nonsaturating operations, it may be possible to detect in isel that the corresponding signed operation could be used instead when we promote the type of an unsigned one. For example, if we emit i15 umul.fix scale 15, we could tell in lowering that i16 smul.fix scale 15 is legal and use that instead. Same for all the other intrinsics, including the non-fixedpoint uadd.sat/usub.sat.

The issue with this approach (which is why I didn't really want to do it) is that it's not testable. No upstream target has these intrinsics marked as legal. I doubt anyone would accept a patch with no tests.
It may also be less efficient than just emitting the signed operations in the first place, because we are forced to trunc and zext in IR before and after every operation.

I don't want to tell you the best IR to use to get good code; I just want frontends to have a reasonably canonical interface to use that matches up well with the information we have.

[ebevhan]

In D82663#2144551, @rjmccall wrote:

In D82663#2144219, @ebevhan wrote:

In D82663#2142426, @rjmccall wrote:

Would it be sensible to use a technical design more like what the matrix folks are doing, where LLVM provides a small interface for emitting operations with various semantics? FixedPointSemantics would move to that header, and Clang would just call into it. That way you get a lot more flexibility in how you generate code, and the Clang IRGen logic is still transparently correct. If you want to add intrinsics or otherwise change the IR patterns used for various operations, you don't have to rewrite a bunch of Clang IRGen logic every time, you just have to update the tests. It'd then be pretty straightforward to have internal helper functions in that interface for computing things like whether you should use signed or unsigned intrinsics given the desired FixedPointSemantics.

This seems like a reasonable thing to do for other reasons as well. Also moving the actual APFixedPoint class to LLVM would make it easier to reuse the fixedpoint calculation code for constant folding in LLVM, for example.

Just to say "I told you so", I'm pretty sure I told people this would happen. :)

Well, transferring the fixed point concept over to LLVM felt like it would happen sooner or later, for the reasons we've discussed here as well as for other reasons. I'm not sure that the discrepancies between the Clang and LLVM semantics were predicted to be the driving factor behind the move, though.

My interest here is mainly in (1) keeping IRGen's logic as obviously correct as possible, (2) not hard-coding a bunch of things that really feel like workarounds for backend limitations, and (3) not complicating core abstractions like FixedPointSemantics with unnecessary extra rules for appropriate use, like having to pass an extra "for codegen" flag to get optimal codegen. If IRGen can just pass down the high-level semantics it wants to some library that will make intelligent decisions about how to emit IR, that seems best.

Just to clarify something here; would the interface in LLVM still emit signed operations for unsigned with padding?

If that's the best IR pattern to emit, yes.

If so, why does dealing with the padding bit detail in LLVM rather than Clang make more sense?

Because frontends should be able to just say "I have a value of a type with these semantics, I need you to do these operations, go do them". The whole purpose of this interface would be to go down a level of abstraction by picking the best IR to represent those operations.

Maybe we're not in agreement about what this interface looks like — I'm imagining something like

struct FixedPointEmitter {
  IRBuilder &B;
  FixedPointEmitter(IRBuilder &B) : B(B) {}

  Value *convert(Value *src, FixedPointSemantics srcSemantics, FixedPointSemantics destSemantics);
  Value *add(Value *lhs, FixedPointSemantics lhsSemantics, Value *rhs, FixedPointSemantics rhsSemantics)
};

I've spent some time going over this and trying to figure out how it would work. I think the interface seems fine on the surface, but I don't see how it directly solves the issues at hand. Regardless of whether this is factored out to LLVM, we still have the issue that we have to massage the semantic somewhere in order to get different behavior for certain kinds of semantics during binop codegen.

Since the binop functions take two different semantics, it must perform conversions internally to get the values to match up before the operation. This would probably just be to the common semantic between the two, and it would then return the Value in the common semantic (since we don't know what to convert back to).

In order for the binop functions to have special behavior for padded unsigned, they would need to modify the common semantic internally in order to get the conversion right. This means that the semantic of the returned Value will not be what you would normally get from getCommonSemantic, so the caller of the function will have no idea what the semantic of the returned value is.

Even if we only treat it as an internal detail of the binop functions and never expose this 'modified' semantic externally, this means we might end up with superfluous operations since (for padded saturating unsigned) we will be forced to trunc the result by one bit to match the real common semantic before we return.

The only solution I can think of is to also return the semantic of the result Value, which feels like it makes the interface pretty bulky.

I can start off by moving APFixedPoint and FixedPointSemantic to ADT, though. Perhaps I should send an RFC.

[rjmccall]

In D82663#2153176, @ebevhan wrote:

In D82663#2144551, @rjmccall wrote:

In D82663#2144219, @ebevhan wrote:

In D82663#2142426, @rjmccall wrote:

Would it be sensible to use a technical design more like what the matrix folks are doing, where LLVM provides a small interface for emitting operations with various semantics? FixedPointSemantics would move to that header, and Clang would just call into it. That way you get a lot more flexibility in how you generate code, and the Clang IRGen logic is still transparently correct. If you want to add intrinsics or otherwise change the IR patterns used for various operations, you don't have to rewrite a bunch of Clang IRGen logic every time, you just have to update the tests. It'd then be pretty straightforward to have internal helper functions in that interface for computing things like whether you should use signed or unsigned intrinsics given the desired FixedPointSemantics.

This seems like a reasonable thing to do for other reasons as well. Also moving the actual APFixedPoint class to LLVM would make it easier to reuse the fixedpoint calculation code for constant folding in LLVM, for example.

Just to say "I told you so", I'm pretty sure I told people this would happen. :)

Well, transferring the fixed point concept over to LLVM felt like it would happen sooner or later, for the reasons we've discussed here as well as for other reasons. I'm not sure that the discrepancies between the Clang and LLVM semantics were predicted to be the driving factor behind the move, though.

My interest here is mainly in (1) keeping IRGen's logic as obviously correct as possible, (2) not hard-coding a bunch of things that really feel like workarounds for backend limitations, and (3) not complicating core abstractions like FixedPointSemantics with unnecessary extra rules for appropriate use, like having to pass an extra "for codegen" flag to get optimal codegen. If IRGen can just pass down the high-level semantics it wants to some library that will make intelligent decisions about how to emit IR, that seems best.

Just to clarify something here; would the interface in LLVM still emit signed operations for unsigned with padding?

If that's the best IR pattern to emit, yes.

If so, why does dealing with the padding bit detail in LLVM rather than Clang make more sense?

Because frontends should be able to just say "I have a value of a type with these semantics, I need you to do these operations, go do them". The whole purpose of this interface would be to go down a level of abstraction by picking the best IR to represent those operations.

Maybe we're not in agreement about what this interface looks like — I'm imagining something like

struct FixedPointEmitter {
  IRBuilder &B;
  FixedPointEmitter(IRBuilder &B) : B(B) {}

  Value *convert(Value *src, FixedPointSemantics srcSemantics, FixedPointSemantics destSemantics);
  Value *add(Value *lhs, FixedPointSemantics lhsSemantics, Value *rhs, FixedPointSemantics rhsSemantics)
};

I've spent some time going over this and trying to figure out how it would work. I think the interface seems fine on the surface, but I don't see how it directly solves the issues at hand. Regardless of whether this is factored out to LLVM, we still have the issue that we have to massage the semantic somewhere in order to get different behavior for certain kinds of semantics during binop codegen.

Since the binop functions take two different semantics, it must perform conversions internally to get the values to match up before the operation. This would probably just be to the common semantic between the two, and it would then return the Value in the common semantic (since we don't know what to convert back to).

In order for the binop functions to have special behavior for padded unsigned, they would need to modify the common semantic internally in order to get the conversion right. This means that the semantic of the returned Value will not be what you would normally get from getCommonSemantic, so the caller of the function will have no idea what the semantic of the returned value is.

Even if we only treat it as an internal detail of the binop functions and never expose this 'modified' semantic externally, this means we might end up with superfluous operations since (for padded saturating unsigned) we will be forced to trunc the result by one bit to match the real common semantic before we return.

The only solution I can think of is to also return the semantic of the result Value, which feels like it makes the interface pretty bulky.

I don't understand. The problem statement as I understood it is that using unsigned intrinsics to do unsigned-with-padding operations is leading to poor code-gen, so you want to start using signed intrinsics, which you can safely do because unsigned-with-padding types are intended to be exactly signed types with a dynamic range restriction to non-negative values. The result of that operation is still logically an unsigned-with-padding value; there's no need to return back a modified semantic that says that the result is really a signed value because it's *not* really a signed value, you're just computing it a different way. I also don't understand why you think need a modified semantics value in the first place as opposed to just using a more complex condition when deciding which intrinsics to use.

[ebevhan]

In D82663#2153834, @rjmccall wrote:

I don't understand. The problem statement as I understood it is that using unsigned intrinsics to do unsigned-with-padding operations is leading to poor code-gen, so you want to start using signed intrinsics, which you can safely do because unsigned-with-padding types are intended to be exactly signed types with a dynamic range restriction to non-negative values. The result of that operation is still logically an unsigned-with-padding value; there's no need to return back a modified semantic that says that the result is really a signed value because it's *not* really a signed value, you're just computing it a different way. I also don't understand why you think need a modified semantics value in the first place as opposed to just using a more complex condition when deciding which intrinsics to use.

Well, it's not just about intrinsics. For saturating operations, the common semantic width is currently narrowed by one bit to get the correct saturating behavior on the operation afterwards. This affects the conversion to the common semantic, since the type will be one bit narrower.

But I realize now that it probably doesn't matter if we simply don't do that narrowing when constructing the common semantic. That way it will always have the right width and we can just do as you say and select the right intrinsic based on the padding bit information. Alright, that should probably work.

EDIT: Ah, but this breaks constant evaluation, which expects the common semantic to be narrower to get the right saturation behavior. So then these special cases for codegen also need to be added to the constant evaluation.

[ebevhan]

clang/include/clang/Basic/FixedPoint.h

unsigned getIntegralBits() const {
     else
       return Width - Scale;
   }
 
   /// Return the FixedPointSemantics that allows for calculating the full
   /// precision semantic that can precisely represent the precision and ranges
   /// of both input values. This does not compute the resulting semantics for a
   /// given binary operation.
+  /// Is UnsignedPaddingIsSigned is true, unsigned semantics which would
+  /// otherwise have been unsigned will be signed instead. This is for codegen
+  /// purposes.
   FixedPointSemantics
-  getCommonSemantics(const FixedPointSemantics &Other) const;
+  getCommonSemantics(const FixedPointSemantics &Other,
+                     bool UnsignedPaddingIsSigned = false) const;
 
   /// Return the FixedPointSemantics for an integer type.
   static FixedPointSemantics GetIntegerSemantics(unsigned Width,
                                                  bool IsSigned) {
     return FixedPointSemantics(Width, /*Scale=*/0, IsSigned,
                                /*IsSaturated=*/false,
                                /*HasUnsignedPadding=*/false);
   }

clang/lib/Basic/FixedPoint.cpp

APFixedPoint APFixedPoint::getMax(const FixedPointSemantics &Sema) {
   return APFixedPoint(Val, Sema);
 }
 
 APFixedPoint APFixedPoint::getMin(const FixedPointSemantics &Sema) {
   auto Val = llvm::APSInt::getMinValue(Sema.getWidth(), !Sema.isSigned());
   return APFixedPoint(Val, Sema);
 }
 
-FixedPointSemantics FixedPointSemantics::getCommonSemantics(
-    const FixedPointSemantics &Other) const {
+FixedPointSemantics
+FixedPointSemantics::getCommonSemantics(const FixedPointSemantics &Other,
+                                        bool UnsignedPaddingIsSigned) const {
   unsigned CommonScale = std::max(getScale(), Other.getScale());
   unsigned CommonWidth =
       std::max(getIntegralBits(), Other.getIntegralBits()) + CommonScale;
 
   bool ResultIsSigned = isSigned() || Other.isSigned();
   bool ResultIsSaturated = isSaturated() || Other.isSaturated();
   bool ResultHasUnsignedPadding = false;
   if (!ResultIsSigned) {
     // Both are unsigned.
     ResultHasUnsignedPadding = hasUnsignedPadding() &&
                                Other.hasUnsignedPadding() && !ResultIsSaturated;
   }
 
+  // For codegen purposes, make unsigned with padding semantics signed instead.
+  // This means that we will generate signed operations. The result from these
+  // operations is defined, since ending up with a negative result is undefined
+  // for nonsaturating semantics, and for saturating semantics we will
+  // perform a clamp-to-zero in the last conversion to result semantics (since
+  // we are going from saturating signed to saturating unsigned).
+  //
+  // This codegen is beneficial for targets which want to use unsigned padding,
+  // since such targets likely do not have native instructions which can
+  // implement the wider scale of unpadded unsigned and would prefer to reuse
+  // their signed operations for this.
+  if (UnsignedPaddingIsSigned && !ResultIsSigned &&
+      (hasUnsignedPadding() || Other.hasUnsignedPadding())) {
+    ResultIsSigned = true;
+    ResultHasUnsignedPadding = false;
+  }
+
   // If the result is signed, add an extra bit for the sign. Otherwise, if it is
   // unsigned and has unsigned padding, we only need to add the extra padding
   // bit back if we are not saturating.
   if (ResultIsSigned || ResultHasUnsignedPadding)
     CommonWidth++;
 
   return FixedPointSemantics(CommonWidth, CommonScale, ResultIsSigned,
                              ResultIsSaturated, ResultHasUnsignedPadding);

clang/lib/CodeGen/CGExprScalar.cpp

Value *ScalarExprEmitter::EmitFixedPointBinOp(const BinOpInfo &op) {
   }
   ASTContext &Ctx = CGF.getContext();
   Value *LHS = op.LHS;
   Value *RHS = op.RHS;
 
   auto LHSFixedSema = Ctx.getFixedPointSemantics(LHSTy);
   auto RHSFixedSema = Ctx.getFixedPointSemantics(RHSTy);
   auto ResultFixedSema = Ctx.getFixedPointSemantics(ResultTy);
-  auto CommonFixedSema = LHSFixedSema.getCommonSemantics(RHSFixedSema);
+  auto CommonFixedSema = LHSFixedSema.getCommonSemantics(RHSFixedSema, true);
 
   // Convert the operands to the full precision type.
   Value *FullLHS = EmitFixedPointConversion(LHS, LHSFixedSema, CommonFixedSema,
                                             op.E->getExprLoc());
   Value *FullRHS = EmitFixedPointConversion(RHS, RHSFixedSema, CommonFixedSema,
                                             op.E->getExprLoc());
 
   // Perform the actual operation.

clang/test/Frontend/fixed_point_add.c

void UnsignedAddition() {
   usa = usa + usf;
 
   // CHECK:      [[USA:%[0-9]+]] = load i16, i16* %usa, align 2
   // CHECK-NEXT: [[UF:%[0-9]+]] = load i16, i16* %uf, align 2
   // CHECK-NEXT: [[USA_EXT:%[a-z0-9]+]] = zext i16 [[USA]] to i24
   // CHECK-NEXT: [[USA:%[a-z0-9]+]] = shl i24 [[USA_EXT]], 8
   // CHECK-NEXT: [[UF_EXT:%[a-z0-9]+]] = zext i16 [[UF]] to i24
   // CHECK-NEXT: [[SUM:%[0-9]+]] = add i24 [[USA]], [[UF_EXT]]
-  // CHECK-NEXT: [[RES:%[a-z0-9]+]] = lshr i24 [[SUM]], 8
+  // SIGNED-NEXT: [[RES:%[a-z0-9]+]] = lshr i24 [[SUM]], 8
+  // UNSIGNED-NEXT: [[RES:%[a-z0-9]+]] = ashr i24 [[SUM]], 8
   // CHECK-NEXT: [[RES_TRUNC:%[a-z0-9]+]] = trunc i24 [[RES]] to i16
   // CHECK-NEXT: store i16 [[RES_TRUNC]], i16* %usa, align 2
   usa = usa + uf;
 }
 
 void IntAddition() {
   // CHECK-LABEL: IntAddition
   short _Accum sa;
void IntAddition() {
 
   // CHECK:      [[USA:%[0-9]+]] = load i16, i16* %usa, align 2
   // CHECK-NEXT: [[I:%[0-9]+]] = load i32, i32* %ui, align 4
   // SIGNED-NEXT: [[USA_EXT:%[a-z0-9]+]] = zext i16 [[USA]] to i40
   // SIGNED-NEXT: [[I_EXT:%[a-z0-9]+]] = zext i32 [[I]] to i40
   // SIGNED-NEXT: [[I:%[a-z0-9]+]] = shl i40 [[I_EXT]], 8
   // SIGNED-NEXT: [[SUM:%[0-9]+]] = add i40 [[USA_EXT]], [[I]]
   // SIGNED-NEXT: [[RES:%[a-z0-9]+]] = trunc i40 [[SUM]] to i16
-  // UNSIGNED-NEXT: [[USA_EXT:%[a-z0-9]+]] = zext i16 [[USA]] to i39
-  // UNSIGNED-NEXT: [[I_EXT:%[a-z0-9]+]] = zext i32 [[I]] to i39
-  // UNSIGNED-NEXT: [[I:%[a-z0-9]+]] = shl i39 [[I_EXT]], 7
-  // UNSIGNED-NEXT: [[SUM:%[0-9]+]] = add i39 [[USA_EXT]], [[I]]
-  // UNSIGNED-NEXT: [[RES:%[a-z0-9]+]] = trunc i39 [[SUM]] to i16
+  // UNSIGNED-NEXT: [[USA_EXT:%[a-z0-9]+]] = zext i16 [[USA]] to i40
+  // UNSIGNED-NEXT: [[I_EXT:%[a-z0-9]+]] = zext i32 [[I]] to i40
+  // UNSIGNED-NEXT: [[I:%[a-z0-9]+]] = shl i40 [[I_EXT]], 7
+  // UNSIGNED-NEXT: [[SUM:%[0-9]+]] = add i40 [[USA_EXT]], [[I]]
+  // UNSIGNED-NEXT: [[RES:%[a-z0-9]+]] = trunc i40 [[SUM]] to i16
   // CHECK-NEXT: store i16 [[RES]], i16* %usa, align 2
   usa = usa + ui;
 
   // CHECK:      [[LF:%[0-9]+]] = load i32, i32* %lf, align 4
   // CHECK-NEXT: [[UI:%[0-9]+]] = load i32, i32* %ui, align 4
   // CHECK-NEXT: [[LF_EXT:%[a-z0-9]+]] = sext i32 [[LF]] to i64
   // CHECK-NEXT: [[UI_EXT:%[a-z0-9]+]] = zext i32 [[UI]] to i64
   // CHECK-NEXT: [[UI:%[a-z0-9]+]] = shl i64 [[UI_EXT]], 31
void SaturatedAddition() {
   // [[SA_SAT]])
   // CHECK-NEXT: store i16 [[SUM]], i16* %sa_sat, align 2
   sa_sat = sa + sa_sat;
 
   // CHECK:      [[USA:%[0-9]+]] = load i16, i16* %usa, align 2
   // CHECK-NEXT: [[USA_SAT:%[0-9]+]] = load i16, i16* %usa_sat, align 2
   // SIGNED-NEXT: [[SUM:%[0-9]+]] = call i16 @llvm.uadd.sat.i16(i16 [[USA]], i16 [[USA_SAT]])
   // SIGNED-NEXT: store i16 [[SUM]], i16* %usa_sat, align 2
-  // UNSIGNED-NEXT: [[USA_TRUNC:%[a-z0-9]+]] = trunc i16 [[USA]] to i15
-  // UNSIGNED-NEXT: [[USA_SAT_TRUNC:%[a-z0-9]+]] = trunc i16 [[USA_SAT]] to i15
-  // UNSIGNED-NEXT: [[SUM:%[0-9]+]] = call i15 @llvm.uadd.sat.i15(i15 [[USA_TRUNC]], i15 [[USA_SAT_TRUNC]])
-  // UNSIGNED-NEXT: [[SUM_EXT:%[a-z0-9]+]] = zext i15 [[SUM]] to i16
-  // UNSIGNED-NEXT: store i16 [[SUM_EXT]], i16* %usa_sat, align 2
+  // UNSIGNED-NEXT: [[SUM:%.*]] = call i16 @llvm.sadd.sat.i16(i16 [[USA]], i16 [[USA_SAT]])
+  // UNSIGNED-NEXT: [[USE_MIN:%.*]] = icmp slt i16 [[SUM]], 0
+  // UNSIGNED-NEXT: [[SATMIN:%.*]] = select i1 [[USE_MIN]], i16 0, i16 [[SUM]]
+  // UNSIGNED-NEXT: store i16 [[SATMIN]], i16* %usa_sat, align 2
   usa_sat = usa + usa_sat;
 
   // CHECK:      [[UA:%[0-9]+]] = load i32, i32* %ua, align 4
   // CHECK-NEXT: [[USA:%[0-9]+]] = load i16, i16* %usa_sat, align 2
   // SIGNED-NEXT: [[USA_EXT:%[a-z0-9]+]] = zext i16 [[USA]] to i32
   // SIGNED-NEXT: [[USA:%[a-z0-9]+]] = shl i32 [[USA_EXT]], 8
   // SIGNED-NEXT: [[SUM:%[0-9]+]] = call i32 @llvm.uadd.sat.i32(i32 [[UA]], i32 [[USA]])
   // SIGNED-NEXT: store i32 [[SUM]], i32* %ua_sat, align 4
-  // UNSIGNED-NEXT: [[UA_TRUNC:%[a-z0-9]+]] = trunc i32 [[UA]] to i31
-  // UNSIGNED-NEXT: [[USA_EXT:%[a-z0-9]+]] = zext i16 [[USA]] to i31
-  // UNSIGNED-NEXT: [[USA:%[a-z0-9]+]] = shl i31 [[USA_EXT]], 8
-  // UNSIGNED-NEXT: [[SUM:%[0-9]+]] = call i31 @llvm.uadd.sat.i31(i31 [[UA_TRUNC]], i31 [[USA]])
-  // UNSIGNED-NEXT: [[SUM_EXT:%[a-z0-9]+]] = zext i31 [[SUM]] to i32
-  // UNSIGNED-NEXT: store i32 [[SUM_EXT]], i32* %ua_sat, align 4
+  // UNSIGNED-NEXT:    [[RESIZE:%.*]] = zext i16 [[USA]] to i32
+  // UNSIGNED-NEXT:    [[UPSCALE:%.*]] = shl i32 [[RESIZE]], 8
+  // UNSIGNED-NEXT:    [[TMP9:%.*]] = call i32 @llvm.sadd.sat.i32(i32 [[UA]], i32 [[UPSCALE]])
+  // UNSIGNED-NEXT:    [[TMP10:%.*]] = icmp slt i32 [[TMP9]], 0
+  // UNSIGNED-NEXT:    [[SATMIN1:%.*]] = select i1 [[TMP10]], i32 0, i32 [[TMP9]]
+  // UNSIGNED-NEXT:    store i32 [[SATMIN1]], i32* %ua_sat, align 4
   ua_sat = ua + usa_sat;
 
   // CHECK:      [[SA_SAT:%[0-9]+]] = load i16, i16* %sa_sat, align 2
   // CHECK-NEXT: [[I:%[0-9]+]] = load i32, i32* %i, align 4
   // CHECK-NEXT: [[SA_SAT_EXT:%[a-z0-9]+]] = sext i16 [[SA_SAT]] to i39
   // CHECK-NEXT: [[I_EXT:%[a-z0-9]+]] = sext i32 [[I]] to i39
   // CHECK-NEXT: [[I:%[a-z0-9]+]] = shl i39 [[I_EXT]], 7
   // CHECK-NEXT: [[SUM:%[0-9]+]] = call i39 @llvm.sadd.sat.i39(i39 [[SA_SAT_EXT]], i39 [[I]])
void SaturatedAddition() {
   // CHECK-NEXT: [[RES3:%[a-z0-9]+]] = trunc i40 [[RES2]] to i16
   // CHECK-NEXT: store i16 [[RES3]], i16* %sa_sat, align 2
   sa_sat = sa_sat + ui;
 
   // CHECK:      [[UF_SAT:%[0-9]+]] = load i16, i16* %uf_sat, align 2
   // CHECK-NEXT: [[UF_SAT2:%[0-9]+]] = load i16, i16* %uf_sat, align 2
   // SIGNED-NEXT: [[SUM:%[0-9]+]] = call i16 @llvm.uadd.sat.i16(i16 [[UF_SAT]], i16 [[UF_SAT2]])
   // SIGNED-NEXT: store i16 [[SUM]], i16* %uf_sat, align 2
-  // UNSIGNED-NEXT: [[UF_SAT_TRUNC:%[a-z0-9]+]] = trunc i16 [[UF_SAT]] to i15
-  // UNSIGNED-NEXT: [[UF_SAT_TRUNC2:%[a-z0-9]+]] = trunc i16 [[UF_SAT2]] to i15
-  // UNSIGNED-NEXT: [[SUM:%[0-9]+]] = call i15 @llvm.uadd.sat.i15(i15 [[UF_SAT_TRUNC]], i15 [[UF_SAT_TRUNC2]])
-  // UNSIGNED-NEXT: [[SUM_EXT:%[a-z0-9]+]] = zext i15 [[SUM]] to i16
-  // UNSIGNED-NEXT: store i16 [[SUM_EXT]], i16* %uf_sat, align 2
+  // UNSIGNED-NEXT:    [[SUM:%.*]] = call i16 @llvm.sadd.sat.i16(i16 [[UF_SAT]], i16 [[UF_SAT2]])
+  // UNSIGNED-NEXT:    [[USE_MIN:%.*]] = icmp slt i16 [[SUM]], 0
+  // UNSIGNED-NEXT:    [[SATMIN:%.*]] = select i1 [[USE_MIN]], i16 0, i16 [[SUM]]
+  // UNSIGNED-NEXT:    store i16 [[SATMIN]], i16* %uf_sat, align 2
   uf_sat = uf_sat + uf_sat;
 
   // CHECK:      [[USA_SAT:%[0-9]+]] = load i16, i16* %usa_sat, align 2
   // CHECK-NEXT: [[I:%[0-9]+]] = load i32, i32* %i, align 4
   // SIGNED-NEXT: [[USA_SAT_RESIZE:%[a-z0-9]+]] = zext i16 [[USA_SAT]] to i40
   // SIGNED-NEXT: [[I_RESIZE:%[a-z0-9]+]] = sext i32 [[I]] to i40
   // SIGNED-NEXT: [[I_UPSCALE:%[a-z0-9]+]] = shl i40 [[I_RESIZE]], 8
   // SIGNED-NEXT: [[SUM:%[0-9]+]] = call i40 @llvm.sadd.sat.i40(i40 [[USA_SAT_RESIZE]], i40 [[I_UPSCALE]])

clang/test/Frontend/fixed_point_comparisons.c

void TestComparisons() {
   // CHECK-NEXT: [[UPSCALE_A:%[a-z0-9]+]] = shl i32 [[RESIZE_A]], 8
   // CHECK-NEXT: {{.*}} = icmp sle i32 [[UPSCALE_A]], [[A2]]
 
   usa > ua;
   // CHECK:      [[A:%[0-9]+]] = load i16, i16* %usa, align 2
   // CHECK-NEXT: [[A2:%[0-9]+]] = load i32, i32* %ua, align 4
   // CHECK-NEXT: [[RESIZE_A:%[a-z0-9]+]] = zext i16 [[A]] to i32
   // CHECK-NEXT: [[UPSCALE_A:%[a-z0-9]+]] = shl i32 [[RESIZE_A]], 8
-  // CHECK-NEXT: {{.*}} = icmp ugt i32 [[UPSCALE_A]], [[A2]]
+  // UNPADDED-NEXT: {{.*}} = icmp ugt i32 [[UPSCALE_A]], [[A2]]
+  // PADDED-NEXT: {{.*}} = icmp sgt i32 [[UPSCALE_A]], [[A2]]
 
   usa >= ua;
   // CHECK:      [[A:%[0-9]+]] = load i16, i16* %usa, align 2
   // CHECK-NEXT: [[A2:%[0-9]+]] = load i32, i32* %ua, align 4
   // CHECK-NEXT: [[RESIZE_A:%[a-z0-9]+]] = zext i16 [[A]] to i32
   // CHECK-NEXT: [[UPSCALE_A:%[a-z0-9]+]] = shl i32 [[RESIZE_A]], 8
-  // CHECK-NEXT: {{.*}} = icmp uge i32 [[UPSCALE_A]], [[A2]]
+  // UNPADDED-NEXT: {{.*}} = icmp uge i32 [[UPSCALE_A]], [[A2]]
+  // PADDED-NEXT: {{.*}} = icmp sge i32 [[UPSCALE_A]], [[A2]]
 
   usa < ua;
   // CHECK:      [[A:%[0-9]+]] = load i16, i16* %usa, align 2
   // CHECK-NEXT: [[A2:%[0-9]+]] = load i32, i32* %ua, align 4
   // CHECK-NEXT: [[RESIZE_A:%[a-z0-9]+]] = zext i16 [[A]] to i32
   // CHECK-NEXT: [[UPSCALE_A:%[a-z0-9]+]] = shl i32 [[RESIZE_A]], 8
-  // CHECK-NEXT: {{.*}} = icmp ult i32 [[UPSCALE_A]], [[A2]]
+  // UNPADDED-NEXT: {{.*}} = icmp ult i32 [[UPSCALE_A]], [[A2]]
+  // PADDED-NEXT: {{.*}} = icmp slt i32 [[UPSCALE_A]], [[A2]]
 
   usa <= ua;
   // CHECK:      [[A:%[0-9]+]] = load i16, i16* %usa, align 2
   // CHECK-NEXT: [[A2:%[0-9]+]] = load i32, i32* %ua, align 4
   // CHECK-NEXT: [[RESIZE_A:%[a-z0-9]+]] = zext i16 [[A]] to i32
   // CHECK-NEXT: [[UPSCALE_A:%[a-z0-9]+]] = shl i32 [[RESIZE_A]], 8
-  // CHECK-NEXT: {{.*}} = icmp ule i32 [[UPSCALE_A]], [[A2]]
+  // UNPADDED-NEXT: {{.*}} = icmp ule i32 [[UPSCALE_A]], [[A2]]
+  // PADDED-NEXT: {{.*}} = icmp sle i32 [[UPSCALE_A]], [[A2]]
 }
 
 void TestIntComparisons() {
   short _Accum sa;
   unsigned short _Accum usa;
 
   int i;
   unsigned int ui;
void TestIntComparisons() {
 
   usa > ui;
   // CHECK:      [[A:%[0-9]+]] = load i16, i16* %usa, align 2
   // CHECK-NEXT: [[I:%[0-9]+]] = load i32, i32* %ui, align 4
   // UNPADDED-NEXT: [[RESIZE_A:%[a-z0-9]+]] = zext i16 [[A]] to i40
   // UNPADDED-NEXT: [[RESIZE_I:%[a-z0-9]+]] = zext i32 [[I]] to i40
   // UNPADDED-NEXT: [[UPSCALE_I:%[a-z0-9]+]] = shl i40 [[RESIZE_I]], 8
   // UNPADDED-NEXT: {{.*}} = icmp ugt i40 [[RESIZE_A]], [[UPSCALE_I]]
-  // PADDED-NEXT: [[RESIZE_A:%[a-z0-9]+]] = zext i16 [[A]] to i39
-  // PADDED-NEXT: [[RESIZE_I:%[a-z0-9]+]] = zext i32 [[I]] to i39
-  // PADDED-NEXT: [[UPSCALE_I:%[a-z0-9]+]] = shl i39 [[RESIZE_I]], 7
-  // PADDED-NEXT: {{.*}} = icmp ugt i39 [[RESIZE_A]], [[UPSCALE_I]]
+  // PADDED-NEXT: [[RESIZE_A:%[a-z0-9]+]] = zext i16 [[A]] to i40
+  // PADDED-NEXT: [[RESIZE_I:%[a-z0-9]+]] = zext i32 [[I]] to i40
+  // PADDED-NEXT: [[UPSCALE_I:%[a-z0-9]+]] = shl i40 [[RESIZE_I]], 7
+  // PADDED-NEXT: {{.*}} = icmp sgt i40 [[RESIZE_A]], [[UPSCALE_I]]
 
   usa >= ui;
   // CHECK:      [[A:%[0-9]+]] = load i16, i16* %usa, align 2
   // CHECK-NEXT: [[I:%[0-9]+]] = load i32, i32* %ui, align 4
   // UNPADDED-NEXT: [[RESIZE_A:%[a-z0-9]+]] = zext i16 [[A]] to i40
   // UNPADDED-NEXT: [[RESIZE_I:%[a-z0-9]+]] = zext i32 [[I]] to i40
   // UNPADDED-NEXT: [[UPSCALE_I:%[a-z0-9]+]] = shl i40 [[RESIZE_I]], 8
   // UNPADDED-NEXT: {{.*}} = icmp uge i40 [[RESIZE_A]], [[UPSCALE_I]]
-  // PADDED-NEXT: [[RESIZE_A:%[a-z0-9]+]] = zext i16 [[A]] to i39
-  // PADDED-NEXT: [[RESIZE_I:%[a-z0-9]+]] = zext i32 [[I]] to i39
-  // PADDED-NEXT: [[UPSCALE_I:%[a-z0-9]+]] = shl i39 [[RESIZE_I]], 7
-  // PADDED-NEXT: {{.*}} = icmp uge i39 [[RESIZE_A]], [[UPSCALE_I]]
+  // PADDED-NEXT: [[RESIZE_A:%[a-z0-9]+]] = zext i16 [[A]] to i40
+  // PADDED-NEXT: [[RESIZE_I:%[a-z0-9]+]] = zext i32 [[I]] to i40
+  // PADDED-NEXT: [[UPSCALE_I:%[a-z0-9]+]] = shl i40 [[RESIZE_I]], 7
+  // PADDED-NEXT: {{.*}} = icmp sge i40 [[RESIZE_A]], [[UPSCALE_I]]
 
   usa < ui;
   // CHECK:      [[A:%[0-9]+]] = load i16, i16* %usa, align 2
   // CHECK-NEXT: [[I:%[0-9]+]] = load i32, i32* %ui, align 4
   // UNPADDED-NEXT: [[RESIZE_A:%[a-z0-9]+]] = zext i16 [[A]] to i40
   // UNPADDED-NEXT: [[RESIZE_I:%[a-z0-9]+]] = zext i32 [[I]] to i40
   // UNPADDED-NEXT: [[UPSCALE_I:%[a-z0-9]+]] = shl i40 [[RESIZE_I]], 8
   // UNPADDED-NEXT: {{.*}} = icmp ult i40 [[RESIZE_A]], [[UPSCALE_I]]
-  // PADDED-NEXT: [[RESIZE_A:%[a-z0-9]+]] = zext i16 [[A]] to i39
-  // PADDED-NEXT: [[RESIZE_I:%[a-z0-9]+]] = zext i32 [[I]] to i39
-  // PADDED-NEXT: [[UPSCALE_I:%[a-z0-9]+]] = shl i39 [[RESIZE_I]], 7
-  // PADDED-NEXT: {{.*}} = icmp ult i39 [[RESIZE_A]], [[UPSCALE_I]]
+  // PADDED-NEXT: [[RESIZE_A:%[a-z0-9]+]] = zext i16 [[A]] to i40
+  // PADDED-NEXT: [[RESIZE_I:%[a-z0-9]+]] = zext i32 [[I]] to i40
+  // PADDED-NEXT: [[UPSCALE_I:%[a-z0-9]+]] = shl i40 [[RESIZE_I]], 7
+  // PADDED-NEXT: {{.*}} = icmp slt i40 [[RESIZE_A]], [[UPSCALE_I]]
 
   usa <= ui;
   // CHECK:      [[A:%[0-9]+]] = load i16, i16* %usa, align 2
   // CHECK-NEXT: [[I:%[0-9]+]] = load i32, i32* %ui, align 4
   // UNPADDED-NEXT: [[RESIZE_A:%[a-z0-9]+]] = zext i16 [[A]] to i40
   // UNPADDED-NEXT: [[RESIZE_I:%[a-z0-9]+]] = zext i32 [[I]] to i40
   // UNPADDED-NEXT: [[UPSCALE_I:%[a-z0-9]+]] = shl i40 [[RESIZE_I]], 8
   // UNPADDED-NEXT: {{.*}} = icmp ule i40 [[RESIZE_A]], [[UPSCALE_I]]
-  // PADDED-NEXT: [[RESIZE_A:%[a-z0-9]+]] = zext i16 [[A]] to i39
-  // PADDED-NEXT: [[RESIZE_I:%[a-z0-9]+]] = zext i32 [[I]] to i39
-  // PADDED-NEXT: [[UPSCALE_I:%[a-z0-9]+]] = shl i39 [[RESIZE_I]], 7
-  // PADDED-NEXT: {{.*}} = icmp ule i39 [[RESIZE_A]], [[UPSCALE_I]]
+  // PADDED-NEXT: [[RESIZE_A:%[a-z0-9]+]] = zext i16 [[A]] to i40
+  // PADDED-NEXT: [[RESIZE_I:%[a-z0-9]+]] = zext i32 [[I]] to i40
+  // PADDED-NEXT: [[UPSCALE_I:%[a-z0-9]+]] = shl i40 [[RESIZE_I]], 7
+  // PADDED-NEXT: {{.*}} = icmp sle i40 [[RESIZE_A]], [[UPSCALE_I]]
 
   // Allow for comparisons with other int like types. These are no different
   // from comparing to an int other than varying sizes. The integer types are
   // still converted to ints or unsigned ints from UsualUnaryConversions().
   sa == b;
   // CHECK:      [[A:%[0-9]+]] = load i16, i16* %sa, align 2
   // CHECK-NEXT: [[B:%[0-9]+]] = load i8, i8* %b, align 1
   // CHECK-NEXT: %tobool = trunc i8 [[B]] to i1
void TestIntComparisons() {
   // An enum value is IntegralCast to an unsigned int.
   usa == e;
   // CHECK:      [[A:%[0-9]+]] = load i16, i16* %usa, align 2
   // CHECK-NEXT: [[I:%[0-9]+]] = load i32, i32* %e, align 4
   // UNPADDED-NEXT: [[RESIZE_A:%[a-z0-9]+]] = zext i16 [[A]] to i40
   // UNPADDED-NEXT: [[RESIZE_I:%[a-z0-9]+]] = zext i32 [[I]] to i40
   // UNPADDED-NEXT: [[UPSCALE_I:%[a-z0-9]+]] = shl i40 [[RESIZE_I]], 8
   // UNPADDED-NEXT: {{.*}} = icmp eq i40 [[RESIZE_A]], [[UPSCALE_I]]
-  // PADDED-NEXT: [[RESIZE_A:%[a-z0-9]+]] = zext i16 [[A]] to i39
-  // PADDED-NEXT: [[RESIZE_I:%[a-z0-9]+]] = zext i32 [[I]] to i39
-  // PADDED-NEXT: [[UPSCALE_I:%[a-z0-9]+]] = shl i39 [[RESIZE_I]], 7
-  // PADDED-NEXT: {{.*}} = icmp eq i39 [[RESIZE_A]], [[UPSCALE_I]]
+  // PADDED-NEXT: [[RESIZE_A:%[a-z0-9]+]] = zext i16 [[A]] to i40
+  // PADDED-NEXT: [[RESIZE_I:%[a-z0-9]+]] = zext i32 [[I]] to i40
+  // PADDED-NEXT: [[UPSCALE_I:%[a-z0-9]+]] = shl i40 [[RESIZE_I]], 7
+  // PADDED-NEXT: {{.*}} = icmp eq i40 [[RESIZE_A]], [[UPSCALE_I]]
 }
 
 void TestComparisonSignage() {
   short _Accum sa;
   unsigned short _Accum usa;
   int i;
   unsigned int ui;
 

clang/test/Frontend/fixed_point_compound.c

 // CHECK-NEXT:    [[TMP46:%.*]] = icmp slt i32 [[RESIZE59]], 0
 // CHECK-NEXT:    [[TMP47:%.*]] = add i32 [[RESIZE59]], 32767
 // CHECK-NEXT:    [[TMP48:%.*]] = select i1 [[TMP46]], i32 [[TMP47]], i32 [[RESIZE59]]
 // CHECK-NEXT:    [[DOWNSCALE60:%.*]] = ashr i32 [[TMP48]], 15
 // CHECK-NEXT:    [[RESIZE61:%.*]] = trunc i32 [[DOWNSCALE60]] to i8
 // CHECK-NEXT:    store i8 [[RESIZE61]], i8* @c, align 1
   c += sa;
 
 // CHECK:         [[TMP47:%.*]] = load i32, i32* @u, align 4
 // CHECK-NEXT:    [[TMP48:%.*]] = load i64, i64* @sula, align 8
 // SIGNED-NEXT:   [[RESIZE55:%.*]] = zext i32 [[TMP47]] to i64
 // SIGNED-NEXT:   [[UPSCALE56:%.*]] = shl i64 [[RESIZE55]], 32
 // SIGNED-NEXT:   [[TMP49:%.*]] = call i64 @llvm.uadd.sat.i64(i64 [[TMP48]], i64 [[UPSCALE56]])
 // SIGNED-NEXT:   store i64 [[TMP49]], i64* @sula, align 8
-// UNSIGNED-NEXT: [[RESIZE39:%.*]] = trunc i64 [[TMP48]] to i63
-// UNSIGNED-NEXT: [[RESIZE40:%.*]] = zext i32 [[TMP47]] to i63
-// UNSIGNED-NEXT: [[UPSCALE41:%.*]] = shl i63 [[RESIZE40]], 31
-// UNSIGNED-NEXT: [[TMP49:%.*]] = call i63 @llvm.uadd.sat.i63(i63 [[RESIZE39]], i63 [[UPSCALE41]])
-// UNSIGNED-NEXT: [[RESIZE42:%.*]] = zext i63 [[TMP49]] to i64
-// UNSIGNED-NEXT: store i64 [[RESIZE42]], i64* @sula, align 8
+// UNSIGNED-NEXT: [[RESIZE40:%.*]] = zext i32 [[TMP47]] to i64
+// UNSIGNED-NEXT: [[UPSCALE41:%.*]] = shl i64 [[RESIZE40]], 31
+// UNSIGNED-NEXT: [[TMP49:%.*]] = call i64 @llvm.sadd.sat.i64(i64 [[TMP48]], i64 [[UPSCALE41]])
+// UNSIGNED-NEXT: [[TMP52:%.*]] = icmp slt i64 [[TMP49]], 0
+// UNSIGNED-NEXT: [[SATMIN48:%.*]] = select i1 [[TMP52]], i64 0, i64 [[TMP49]]
+// UNSIGNED-NEXT: store i64 [[SATMIN48]], i64* @sula, align 8
   sula += u;
 
 // CHECK:         [[TMP50:%.*]] = load i16, i16* @suf, align 2
 // CHECK-NEXT:    [[TMP51:%.*]] = load i8, i8* @sshf, align 1
 // SIGNED-NEXT:   [[RESIZE57:%.*]] = sext i8 [[TMP51]] to i17
 // SIGNED-NEXT:   [[UPSCALE58:%.*]] = shl i17 [[RESIZE57]], 9
 // SIGNED-NEXT:   [[RESIZE59:%.*]] = zext i16 [[TMP50]] to i17
 // SIGNED-NEXT:   [[TMP52:%.*]] = call i17 @llvm.sadd.sat.i17(i17 [[UPSCALE58]], i17 [[RESIZE59]])

clang/test/Frontend/fixed_point_div.c

void UnsignedDivision() {
 
   unsigned short _Fract usf;
   unsigned _Fract uf;
   unsigned long _Fract ulf;
 
   // CHECK:         [[TMP0:%.*]] = load i16, i16* %usa, align 2
   // CHECK-NEXT:    [[TMP1:%.*]] = load i16, i16* %usa, align 2
   // SIGNED-NEXT:   [[TMP2:%.*]] = call i16 @llvm.udiv.fix.i16(i16 [[TMP0]], i16 [[TMP1]], i32 8)
-  // UNSIGNED-NEXT: [[TMP2:%.*]] = call i16 @llvm.udiv.fix.i16(i16 [[TMP0]], i16 [[TMP1]], i32 7)
+  // UNSIGNED-NEXT: [[TMP2:%.*]] = call i16 @llvm.sdiv.fix.i16(i16 [[TMP0]], i16 [[TMP1]], i32 7)
   // CHECK-NEXT:    store i16 [[TMP2]], i16* %usa, align 2
   usa = usa / usa;
 
   // CHECK:         [[TMP3:%.*]] = load i16, i16* %usa, align 2
   // CHECK-NEXT:    [[TMP4:%.*]] = load i32, i32* %ua, align 4
   // CHECK-NEXT:    [[RESIZE:%.*]] = zext i16 [[TMP3]] to i32
   // CHECK-NEXT:    [[UPSCALE:%.*]] = shl i32 [[RESIZE]], 8
   // SIGNED-NEXT:   [[TMP5:%.*]] = call i32 @llvm.udiv.fix.i32(i32 [[UPSCALE]], i32 [[TMP4]], i32 16)
-  // UNSIGNED-NEXT: [[TMP5:%.*]] = call i32 @llvm.udiv.fix.i32(i32 [[UPSCALE]], i32 [[TMP4]], i32 15)
+  // UNSIGNED-NEXT: [[TMP5:%.*]] = call i32 @llvm.sdiv.fix.i32(i32 [[UPSCALE]], i32 [[TMP4]], i32 15)
   // CHECK-NEXT:    store i32 [[TMP5]], i32* %ua, align 4
   ua = usa / ua;
 
   // CHECK:         [[TMP6:%.*]] = load i16, i16* %usa, align 2
   // CHECK-NEXT:    [[TMP7:%.*]] = load i8, i8* %usf, align 1
   // CHECK-NEXT:    [[RESIZE1:%.*]] = zext i8 [[TMP7]] to i16
   // SIGNED-NEXT:   [[TMP8:%.*]] = call i16 @llvm.udiv.fix.i16(i16 [[TMP6]], i16 [[RESIZE1]], i32 8)
-  // UNSIGNED-NEXT: [[TMP8:%.*]] = call i16 @llvm.udiv.fix.i16(i16 [[TMP6]], i16 [[RESIZE1]], i32 7)
+  // UNSIGNED-NEXT: [[TMP8:%.*]] = call i16 @llvm.sdiv.fix.i16(i16 [[TMP6]], i16 [[RESIZE1]], i32 7)
   // CHECK-NEXT:    store i16 [[TMP8]], i16* %usa, align 2
   usa = usa / usf;
 
   // CHECK:         [[TMP9:%.*]] = load i16, i16* %usa, align 2
   // CHECK-NEXT:    [[TMP10:%.*]] = load i16, i16* %uf, align 2
   // CHECK-NEXT:    [[RESIZE2:%.*]] = zext i16 [[TMP9]] to i24
   // CHECK-NEXT:    [[UPSCALE3:%.*]] = shl i24 [[RESIZE2]], 8
   // CHECK-NEXT:    [[RESIZE4:%.*]] = zext i16 [[TMP10]] to i24
   // SIGNED-NEXT:   [[TMP11:%.*]] = call i24 @llvm.udiv.fix.i24(i24 [[UPSCALE3]], i24 [[RESIZE4]], i32 16)
-  // UNSIGNED-NEXT: [[TMP11:%.*]] = call i24 @llvm.udiv.fix.i24(i24 [[UPSCALE3]], i24 [[RESIZE4]], i32 15)
-  // CHECK-NEXT:    [[DOWNSCALE:%.*]] = lshr i24 [[TMP11]], 8
+  // SIGNED-NEXT:   [[DOWNSCALE:%.*]] = lshr i24 [[TMP11]], 8
+  // UNSIGNED-NEXT: [[TMP11:%.*]] = call i24 @llvm.sdiv.fix.i24(i24 [[UPSCALE3]], i24 [[RESIZE4]], i32 15)
+  // UNSIGNED-NEXT: [[DOWNSCALE:%.*]] = ashr i24 [[TMP11]], 8
   // CHECK-NEXT:    [[RESIZE5:%.*]] = trunc i24 [[DOWNSCALE]] to i16
   // CHECK-NEXT:    store i16 [[RESIZE5]], i16* %usa, align 2
   usa = usa / uf;
 }
 
 void IntDivision() {
   // CHECK-LABEL: IntDivision
   short _Accum sa;
void IntDivision() {
 
   // CHECK:         [[TMP9:%.*]] = load i16, i16* %usa, align 2
   // CHECK-NEXT:    [[TMP10:%.*]] = load i32, i32* %ui, align 4
   // SIGNED-NEXT:   [[RESIZE11:%.*]] = zext i16 [[TMP9]] to i40
   // SIGNED-NEXT:   [[RESIZE12:%.*]] = zext i32 [[TMP10]] to i40
   // SIGNED-NEXT:   [[UPSCALE13:%.*]] = shl i40 [[RESIZE12]], 8
   // SIGNED-NEXT:   [[TMP11:%.*]] = call i40 @llvm.udiv.fix.i40(i40 [[RESIZE11]], i40 [[UPSCALE13]], i32 8)
   // SIGNED-NEXT:   [[RESIZE14:%.*]] = trunc i40 [[TMP11]] to i16
-  // UNSIGNED-NEXT: [[RESIZE11:%.*]] = zext i16 [[TMP9]] to i39
-  // UNSIGNED-NEXT: [[RESIZE12:%.*]] = zext i32 [[TMP10]] to i39
-  // UNSIGNED-NEXT: [[UPSCALE13:%.*]] = shl i39 [[RESIZE12]], 7
-  // UNSIGNED-NEXT: [[TMP11:%.*]] = call i39 @llvm.udiv.fix.i39(i39 [[RESIZE11]], i39 [[UPSCALE13]], i32 7)
-  // UNSIGNED-NEXT: [[RESIZE14:%.*]] = trunc i39 [[TMP11]] to i16
+  // UNSIGNED-NEXT: [[RESIZE11:%.*]] = zext i16 [[TMP9]] to i40
+  // UNSIGNED-NEXT: [[RESIZE12:%.*]] = zext i32 [[TMP10]] to i40
+  // UNSIGNED-NEXT: [[UPSCALE13:%.*]] = shl i40 [[RESIZE12]], 7
+  // UNSIGNED-NEXT: [[TMP11:%.*]] = call i40 @llvm.sdiv.fix.i40(i40 [[RESIZE11]], i40 [[UPSCALE13]], i32 7)
+  // UNSIGNED-NEXT: [[RESIZE14:%.*]] = trunc i40 [[TMP11]] to i16
   // CHECK-NEXT:    store i16 [[RESIZE14]], i16* %usa, align 2
   usa = usa / ui;
 
   // CHECK:         [[TMP12:%.*]] = load i32, i32* %lf, align 4
   // CHECK-NEXT:    [[TMP13:%.*]] = load i32, i32* %ui, align 4
   // CHECK-NEXT:    [[RESIZE15:%.*]] = sext i32 [[TMP12]] to i64
   // CHECK-NEXT:    [[RESIZE16:%.*]] = zext i32 [[TMP13]] to i64
   // CHECK-NEXT:    [[UPSCALE17:%.*]] = shl i64 [[RESIZE16]], 31
void IntDivision() {
 
   // CHECK:         [[TMP21:%.*]] = load i32, i32* %ui, align 4
   // CHECK-NEXT:    [[TMP22:%.*]] = load i16, i16* %usa, align 2
   // SIGNED-NEXT:   [[RESIZE27:%.*]] = zext i32 [[TMP21]] to i40
   // SIGNED-NEXT:   [[UPSCALE28:%.*]] = shl i40 [[RESIZE27]], 8
   // SIGNED-NEXT:   [[RESIZE29:%.*]] = zext i16 [[TMP22]] to i40
   // SIGNED-NEXT:   [[TMP23:%.*]] = call i40 @llvm.udiv.fix.i40(i40 [[UPSCALE28]], i40 [[RESIZE29]], i32 8)
   // SIGNED-NEXT:   [[RESIZE30:%.*]] = trunc i40 [[TMP23]] to i16
-  // UNSIGNED-NEXT: [[RESIZE27:%.*]] = zext i32 [[TMP21]] to i39
-  // UNSIGNED-NEXT: [[UPSCALE28:%.*]] = shl i39 [[RESIZE27]], 7
-  // UNSIGNED-NEXT: [[RESIZE29:%.*]] = zext i16 [[TMP22]] to i39
-  // UNSIGNED-NEXT: [[TMP23:%.*]] = call i39 @llvm.udiv.fix.i39(i39 [[UPSCALE28]], i39 [[RESIZE29]], i32 7)
-  // UNSIGNED-NEXT: [[RESIZE30:%.*]] = trunc i39 [[TMP23]] to i16
+  // UNSIGNED-NEXT: [[RESIZE27:%.*]] = zext i32 [[TMP21]] to i40
+  // UNSIGNED-NEXT: [[UPSCALE28:%.*]] = shl i40 [[RESIZE27]], 7
+  // UNSIGNED-NEXT: [[RESIZE29:%.*]] = zext i16 [[TMP22]] to i40
+  // UNSIGNED-NEXT: [[TMP23:%.*]] = call i40 @llvm.sdiv.fix.i40(i40 [[UPSCALE28]], i40 [[RESIZE29]], i32 7)
+  // UNSIGNED-NEXT: [[RESIZE30:%.*]] = trunc i40 [[TMP23]] to i16
   // CHECK-NEXT:    store i16 [[RESIZE30]], i16* %usa, align 2
   usa = ui / usa;
 
   // CHECK:         [[TMP27:%.*]] = load i32, i32* %ui, align 4
   // CHECK-NEXT:    [[TMP28:%.*]] = load i16, i16* %sa, align 2
   // CHECK-NEXT:    [[RESIZE33:%.*]] = zext i32 [[TMP27]] to i40
   // CHECK-NEXT:    [[UPSCALE34:%.*]] = shl i40 [[RESIZE33]], 7
   // CHECK-NEXT:    [[RESIZE35:%.*]] = sext i16 [[TMP28]] to i40
void SaturatedDivision() {
   // CHECK-NEXT: [[SUM:%[0-9]+]] = call i16 @llvm.sdiv.fix.sat.i16(i16 [[SA]], i16 [[SA_SAT]], i32 7)
   // CHECK-NEXT: store i16 [[SUM]], i16* %sa_sat, align 2
   sa_sat = sa / sa_sat;
 
   // CHECK:      [[USA:%[0-9]+]] = load i16, i16* %usa, align 2
   // CHECK-NEXT: [[USA_SAT:%[0-9]+]] = load i16, i16* %usa_sat, align 2
   // SIGNED-NEXT: [[SUM:%[0-9]+]] = call i16 @llvm.udiv.fix.sat.i16(i16 [[USA]], i16 [[USA_SAT]], i32 8)
   // SIGNED-NEXT: store i16 [[SUM]], i16* %usa_sat, align 2
-  // UNSIGNED-NEXT: [[USA_TRUNC:%[a-z0-9]+]] = trunc i16 [[USA]] to i15
-  // UNSIGNED-NEXT: [[USA_SAT_TRUNC:%[a-z0-9]+]] = trunc i16 [[USA_SAT]] to i15
-  // UNSIGNED-NEXT: [[SUM:%[0-9]+]] = call i15 @llvm.udiv.fix.sat.i15(i15 [[USA_TRUNC]], i15 [[USA_SAT_TRUNC]], i32 7)
-  // UNSIGNED-NEXT: [[SUM_EXT:%[a-z0-9]+]] = zext i15 [[SUM]] to i16
-  // UNSIGNED-NEXT: store i16 [[SUM_EXT]], i16* %usa_sat, align 2
+  // UNSIGNED-NEXT:    [[SUM:%.*]] = call i16 @llvm.sdiv.fix.sat.i16(i16 [[USA]], i16 [[USA_SAT]], i32 7)
+  // UNSIGNED-NEXT:    [[USE_MIN:%.*]] = icmp slt i16 [[SUM]], 0
+  // UNSIGNED-NEXT:    [[SATMIN:%.*]] = select i1 [[USE_MIN]], i16 0, i16 [[SUM]]
+  // UNSIGNED-NEXT:    store i16 [[SATMIN]], i16* %usa_sat, align 2
   usa_sat = usa / usa_sat;
 
   // CHECK:      [[UA:%[0-9]+]] = load i32, i32* %ua, align 4
   // CHECK-NEXT: [[USA:%[0-9]+]] = load i16, i16* %usa_sat, align 2
   // SIGNED-NEXT: [[USA_EXT:%[a-z0-9]+]] = zext i16 [[USA]] to i32
   // SIGNED-NEXT: [[USA:%[a-z0-9]+]] = shl i32 [[USA_EXT]], 8
   // SIGNED-NEXT: [[SUM:%[0-9]+]] = call i32 @llvm.udiv.fix.sat.i32(i32 [[UA]], i32 [[USA]], i32 16)
   // SIGNED-NEXT: store i32 [[SUM]], i32* %ua_sat, align 4
-  // UNSIGNED-NEXT: [[UA_TRUNC:%[a-z0-9]+]] = trunc i32 [[UA]] to i31
-  // UNSIGNED-NEXT: [[USA_EXT:%[a-z0-9]+]] = zext i16 [[USA]] to i31
-  // UNSIGNED-NEXT: [[USA:%[a-z0-9]+]] = shl i31 [[USA_EXT]], 8
-  // UNSIGNED-NEXT: [[SUM:%[0-9]+]] = call i31 @llvm.udiv.fix.sat.i31(i31 [[UA_TRUNC]], i31 [[USA]], i32 15)
-  // UNSIGNED-NEXT: [[SUM_EXT:%[a-z0-9]+]] = zext i31 [[SUM]] to i32
-  // UNSIGNED-NEXT: store i32 [[SUM_EXT]], i32* %ua_sat, align 4
+  // UNSIGNED-NEXT:    [[USA_EXT:%.*]] = zext i16 [[USA]] to i32
+  // UNSIGNED-NEXT:    [[USA:%.*]] = shl i32 [[USA_EXT]], 8
+  // UNSIGNED-NEXT:    [[SUM:%.*]] = call i32 @llvm.sdiv.fix.sat.i32(i32 [[UA]], i32 [[USA]], i32 15)
+  // UNSIGNED-NEXT:    [[USE_MIN:%.*]] = icmp slt i32 [[SUM]], 0
+  // UNSIGNED-NEXT:    [[SATMIN:%.*]] = select i1 [[USE_MIN]], i32 0, i32 [[SUM]]
+  // UNSIGNED-NEXT:    store i32 [[SATMIN]], i32* %ua_sat, align 4
   ua_sat = ua / usa_sat;
 
   // CHECK:      [[SA_SAT:%[0-9]+]] = load i16, i16* %sa_sat, align 2
   // CHECK-NEXT: [[I:%[0-9]+]] = load i32, i32* %i, align 4
   // CHECK-NEXT: [[SA_SAT_EXT:%[a-z0-9]+]] = sext i16 [[SA_SAT]] to i39
   // CHECK-NEXT: [[I_EXT:%[a-z0-9]+]] = sext i32 [[I]] to i39
   // CHECK-NEXT: [[I:%[a-z0-9]+]] = shl i39 [[I_EXT]], 7
   // CHECK-NEXT: [[SUM:%[0-9]+]] = call i39 @llvm.sdiv.fix.sat.i39(i39 [[SA_SAT_EXT]], i39 [[I]], i32 7)
void SaturatedDivision() {
   // CHECK-NEXT: [[RES3:%[a-z0-9]+]] = trunc i40 [[RES2]] to i16
   // CHECK-NEXT: store i16 [[RES3]], i16* %sa_sat, align 2
   sa_sat = sa_sat / ui;
 
   // CHECK:      [[UF_SAT:%[0-9]+]] = load i16, i16* %uf_sat, align 2
   // CHECK-NEXT: [[UF_SAT2:%[0-9]+]] = load i16, i16* %uf_sat, align 2
   // SIGNED-NEXT: [[SUM:%[0-9]+]] = call i16 @llvm.udiv.fix.sat.i16(i16 [[UF_SAT]], i16 [[UF_SAT2]], i32 16)
   // SIGNED-NEXT: store i16 [[SUM]], i16* %uf_sat, align 2
-  // UNSIGNED-NEXT: [[UF_SAT_TRUNC:%[a-z0-9]+]] = trunc i16 [[UF_SAT]] to i15
-  // UNSIGNED-NEXT: [[UF_SAT_TRUNC2:%[a-z0-9]+]] = trunc i16 [[UF_SAT2]] to i15
-  // UNSIGNED-NEXT: [[SUM:%[0-9]+]] = call i15 @llvm.udiv.fix.sat.i15(i15 [[UF_SAT_TRUNC]], i15 [[UF_SAT_TRUNC2]], i32 15)
-  // UNSIGNED-NEXT: [[SUM_EXT:%[a-z0-9]+]] = zext i15 [[SUM]] to i16
-  // UNSIGNED-NEXT: store i16 [[SUM_EXT]], i16* %uf_sat, align 2
+  // UNSIGNED-NEXT:    [[SUM:%.*]] = call i16 @llvm.sdiv.fix.sat.i16(i16 [[UF_SAT]], i16 [[UF_SAT2]], i32 15)
+  // UNSIGNED-NEXT:    [[USE_MIN:%.*]] = icmp slt i16 [[SUM]], 0
+  // UNSIGNED-NEXT:    [[SATMIN:%.*]] = select i1 [[USE_MIN]], i16 0, i16 [[SUM]]
+  // UNSIGNED-NEXT:    store i16 [[SATMIN]], i16* %uf_sat, align 2
   uf_sat = uf_sat / uf_sat;
 
   // CHECK:      [[USA_SAT:%[0-9]+]] = load i16, i16* %usa_sat, align 2
   // CHECK-NEXT: [[I:%[0-9]+]] = load i32, i32* %i, align 4
   // SIGNED-NEXT: [[USA_SAT_RESIZE:%[a-z0-9]+]] = zext i16 [[USA_SAT]] to i40
   // SIGNED-NEXT: [[I_RESIZE:%[a-z0-9]+]] = sext i32 [[I]] to i40
   // SIGNED-NEXT: [[I_UPSCALE:%[a-z0-9]+]] = shl i40 [[I_RESIZE]], 8
   // SIGNED-NEXT: [[SUM:%[0-9]+]] = call i40 @llvm.sdiv.fix.sat.i40(i40 [[USA_SAT_RESIZE]], i40 [[I_UPSCALE]], i32 8)

clang/test/Frontend/fixed_point_mul.c

void UnsignedMultiplication() {
 
   unsigned short _Fract usf;
   unsigned _Fract uf;
   unsigned long _Fract ulf;
 
   // CHECK:         [[TMP0:%.*]] = load i16, i16* %usa, align 2
   // CHECK-NEXT:    [[TMP1:%.*]] = load i16, i16* %usa, align 2
   // SIGNED-NEXT:   [[TMP2:%.*]] = call i16 @llvm.umul.fix.i16(i16 [[TMP0]], i16 [[TMP1]], i32 8)
-  // UNSIGNED-NEXT: [[TMP2:%.*]] = call i16 @llvm.umul.fix.i16(i16 [[TMP0]], i16 [[TMP1]], i32 7)
+  // UNSIGNED-NEXT: [[TMP2:%.*]] = call i16 @llvm.smul.fix.i16(i16 [[TMP0]], i16 [[TMP1]], i32 7)
   // CHECK-NEXT:    store i16 [[TMP2]], i16* %usa, align 2
   usa = usa * usa;
 
   // CHECK:         [[TMP3:%.*]] = load i16, i16* %usa, align 2
   // CHECK-NEXT:    [[TMP4:%.*]] = load i32, i32* %ua, align 4
   // CHECK-NEXT:    [[RESIZE:%.*]] = zext i16 [[TMP3]] to i32
   // CHECK-NEXT:    [[UPSCALE:%.*]] = shl i32 [[RESIZE]], 8
   // SIGNED-NEXT:   [[TMP5:%.*]] = call i32 @llvm.umul.fix.i32(i32 [[UPSCALE]], i32 [[TMP4]], i32 16)
-  // UNSIGNED-NEXT: [[TMP5:%.*]] = call i32 @llvm.umul.fix.i32(i32 [[UPSCALE]], i32 [[TMP4]], i32 15)
+  // UNSIGNED-NEXT: [[TMP5:%.*]] = call i32 @llvm.smul.fix.i32(i32 [[UPSCALE]], i32 [[TMP4]], i32 15)
   // CHECK-NEXT:    store i32 [[TMP5]], i32* %ua, align 4
   ua = usa * ua;
 
   // CHECK:         [[TMP6:%.*]] = load i16, i16* %usa, align 2
   // CHECK-NEXT:    [[TMP7:%.*]] = load i8, i8* %usf, align 1
   // CHECK-NEXT:    [[RESIZE1:%.*]] = zext i8 [[TMP7]] to i16
   // SIGNED-NEXT:   [[TMP8:%.*]] = call i16 @llvm.umul.fix.i16(i16 [[TMP6]], i16 [[RESIZE1]], i32 8)
-  // UNSIGNED-NEXT: [[TMP8:%.*]] = call i16 @llvm.umul.fix.i16(i16 [[TMP6]], i16 [[RESIZE1]], i32 7)
+  // UNSIGNED-NEXT: [[TMP8:%.*]] = call i16 @llvm.smul.fix.i16(i16 [[TMP6]], i16 [[RESIZE1]], i32 7)
   // CHECK-NEXT:    store i16 [[TMP8]], i16* %usa, align 2
   usa = usa * usf;
 
   // CHECK:         [[TMP9:%.*]] = load i16, i16* %usa, align 2
   // CHECK-NEXT:    [[TMP10:%.*]] = load i16, i16* %uf, align 2
   // CHECK-NEXT:    [[RESIZE2:%.*]] = zext i16 [[TMP9]] to i24
   // CHECK-NEXT:    [[UPSCALE3:%.*]] = shl i24 [[RESIZE2]], 8
   // CHECK-NEXT:    [[RESIZE4:%.*]] = zext i16 [[TMP10]] to i24
   // SIGNED-NEXT:   [[TMP11:%.*]] = call i24 @llvm.umul.fix.i24(i24 [[UPSCALE3]], i24 [[RESIZE4]], i32 16)
-  // UNSIGNED-NEXT: [[TMP11:%.*]] = call i24 @llvm.umul.fix.i24(i24 [[UPSCALE3]], i24 [[RESIZE4]], i32 15)
-  // CHECK-NEXT:    [[DOWNSCALE:%.*]] = lshr i24 [[TMP11]], 8
+  // SIGNED-NEXT:   [[DOWNSCALE:%.*]] = lshr i24 [[TMP11]], 8
+  // UNSIGNED-NEXT: [[TMP11:%.*]] = call i24 @llvm.smul.fix.i24(i24 [[UPSCALE3]], i24 [[RESIZE4]], i32 15)
+  // UNSIGNED-NEXT: [[DOWNSCALE:%.*]] = ashr i24 [[TMP11]], 8
   // CHECK-NEXT:    [[RESIZE5:%.*]] = trunc i24 [[DOWNSCALE]] to i16
   // CHECK-NEXT:    store i16 [[RESIZE5]], i16* %usa, align 2
   usa = usa * uf;
 }
 
 void IntMultiplication() {
   // CHECK-LABEL: IntMultiplication
   short _Accum sa;
void IntMultiplication() {
 
   // CHECK:         [[TMP9:%.*]] = load i16, i16* %usa, align 2
   // CHECK-NEXT:    [[TMP10:%.*]] = load i32, i32* %ui, align 4
   // SIGNED-NEXT:   [[RESIZE11:%.*]] = zext i16 [[TMP9]] to i40
   // SIGNED-NEXT:   [[RESIZE12:%.*]] = zext i32 [[TMP10]] to i40
   // SIGNED-NEXT:   [[UPSCALE13:%.*]] = shl i40 [[RESIZE12]], 8
   // SIGNED-NEXT:   [[TMP11:%.*]] = call i40 @llvm.umul.fix.i40(i40 [[RESIZE11]], i40 [[UPSCALE13]], i32 8)
   // SIGNED-NEXT:   [[RESIZE14:%.*]] = trunc i40 [[TMP11]] to i16
-  // UNSIGNED-NEXT: [[RESIZE11:%.*]] = zext i16 [[TMP9]] to i39
-  // UNSIGNED-NEXT: [[RESIZE12:%.*]] = zext i32 [[TMP10]] to i39
-  // UNSIGNED-NEXT: [[UPSCALE13:%.*]] = shl i39 [[RESIZE12]], 7
-  // UNSIGNED-NEXT: [[TMP11:%.*]] = call i39 @llvm.umul.fix.i39(i39 [[RESIZE11]], i39 [[UPSCALE13]], i32 7)
-  // UNSIGNED-NEXT: [[RESIZE14:%.*]] = trunc i39 [[TMP11]] to i16
+  // UNSIGNED-NEXT: [[RESIZE11:%.*]] = zext i16 [[TMP9]] to i40
+  // UNSIGNED-NEXT: [[RESIZE12:%.*]] = zext i32 [[TMP10]] to i40
+  // UNSIGNED-NEXT: [[UPSCALE13:%.*]] = shl i40 [[RESIZE12]], 7
+  // UNSIGNED-NEXT: [[TMP11:%.*]] = call i40 @llvm.smul.fix.i40(i40 [[RESIZE11]], i40 [[UPSCALE13]], i32 7)
+  // UNSIGNED-NEXT: [[RESIZE14:%.*]] = trunc i40 [[TMP11]] to i16
   // CHECK-NEXT:    store i16 [[RESIZE14]], i16* %usa, align 2
   usa = usa * ui;
 
   // CHECK:         [[TMP12:%.*]] = load i32, i32* %lf, align 4
   // CHECK-NEXT:    [[TMP13:%.*]] = load i32, i32* %ui, align 4
   // CHECK-NEXT:    [[RESIZE15:%.*]] = sext i32 [[TMP12]] to i64
   // CHECK-NEXT:    [[RESIZE16:%.*]] = zext i32 [[TMP13]] to i64
   // CHECK-NEXT:    [[UPSCALE17:%.*]] = shl i64 [[RESIZE16]], 31
void IntMultiplication() {
 
   // CHECK:         [[TMP21:%.*]] = load i32, i32* %ui, align 4
   // CHECK-NEXT:    [[TMP22:%.*]] = load i16, i16* %usa, align 2
   // SIGNED-NEXT:   [[RESIZE27:%.*]] = zext i32 [[TMP21]] to i40
   // SIGNED-NEXT:   [[UPSCALE28:%.*]] = shl i40 [[RESIZE27]], 8
   // SIGNED-NEXT:   [[RESIZE29:%.*]] = zext i16 [[TMP22]] to i40
   // SIGNED-NEXT:   [[TMP23:%.*]] = call i40 @llvm.umul.fix.i40(i40 [[UPSCALE28]], i40 [[RESIZE29]], i32 8)
   // SIGNED-NEXT:   [[RESIZE30:%.*]] = trunc i40 [[TMP23]] to i16
-  // UNSIGNED-NEXT: [[RESIZE27:%.*]] = zext i32 [[TMP21]] to i39
-  // UNSIGNED-NEXT: [[UPSCALE28:%.*]] = shl i39 [[RESIZE27]], 7
-  // UNSIGNED-NEXT: [[RESIZE29:%.*]] = zext i16 [[TMP22]] to i39
-  // UNSIGNED-NEXT: [[TMP23:%.*]] = call i39 @llvm.umul.fix.i39(i39 [[UPSCALE28]], i39 [[RESIZE29]], i32 7)
-  // UNSIGNED-NEXT: [[RESIZE30:%.*]] = trunc i39 [[TMP23]] to i16
+  // UNSIGNED-NEXT: [[RESIZE27:%.*]] = zext i32 [[TMP21]] to i40
+  // UNSIGNED-NEXT: [[UPSCALE28:%.*]] = shl i40 [[RESIZE27]], 7
+  // UNSIGNED-NEXT: [[RESIZE29:%.*]] = zext i16 [[TMP22]] to i40
+  // UNSIGNED-NEXT: [[TMP23:%.*]] = call i40 @llvm.smul.fix.i40(i40 [[UPSCALE28]], i40 [[RESIZE29]], i32 7)
+  // UNSIGNED-NEXT: [[RESIZE30:%.*]] = trunc i40 [[TMP23]] to i16
   // CHECK-NEXT:    store i16 [[RESIZE30]], i16* %usa, align 2
   usa = ui * usa;
 
   // CHECK:         [[TMP27:%.*]] = load i32, i32* %ui, align 4
   // CHECK-NEXT:    [[TMP28:%.*]] = load i16, i16* %sa, align 2
   // CHECK-NEXT:    [[RESIZE33:%.*]] = zext i32 [[TMP27]] to i40
   // CHECK-NEXT:    [[UPSCALE34:%.*]] = shl i40 [[RESIZE33]], 7
   // CHECK-NEXT:    [[RESIZE35:%.*]] = sext i16 [[TMP28]] to i40
void SaturatedMultiplication() {
   // CHECK-NEXT: [[SUM:%[0-9]+]] = call i16 @llvm.smul.fix.sat.i16(i16 [[SA]], i16 [[SA_SAT]], i32 7)
   // CHECK-NEXT: store i16 [[SUM]], i16* %sa_sat, align 2
   sa_sat = sa * sa_sat;
 
   // CHECK:      [[USA:%[0-9]+]] = load i16, i16* %usa, align 2
   // CHECK-NEXT: [[USA_SAT:%[0-9]+]] = load i16, i16* %usa_sat, align 2
   // SIGNED-NEXT: [[SUM:%[0-9]+]] = call i16 @llvm.umul.fix.sat.i16(i16 [[USA]], i16 [[USA_SAT]], i32 8)
   // SIGNED-NEXT: store i16 [[SUM]], i16* %usa_sat, align 2
-  // UNSIGNED-NEXT: [[USA_TRUNC:%[a-z0-9]+]] = trunc i16 [[USA]] to i15
-  // UNSIGNED-NEXT: [[USA_SAT_TRUNC:%[a-z0-9]+]] = trunc i16 [[USA_SAT]] to i15
-  // UNSIGNED-NEXT: [[SUM:%[0-9]+]] = call i15 @llvm.umul.fix.sat.i15(i15 [[USA_TRUNC]], i15 [[USA_SAT_TRUNC]], i32 7)
-  // UNSIGNED-NEXT: [[SUM_EXT:%[a-z0-9]+]] = zext i15 [[SUM]] to i16
-  // UNSIGNED-NEXT: store i16 [[SUM_EXT]], i16* %usa_sat, align 2
+  // UNSIGNED-NEXT: [[SUM:%[0-9]+]] = call i16 @llvm.smul.fix.sat.i16(i16 [[USA]], i16 [[USA_SAT]], i32 7)
+  // UNSIGNED-NEXT: [[USE_MIN:%.*]] = icmp slt i16 [[SUM]], 0
+  // UNSIGNED-NEXT: [[SATMIN:%.*]] = select i1 [[USE_MIN]], i16 0, i16 [[SUM]]
+  // UNSIGNED-NEXT: store i16 [[SATMIN]], i16* %usa_sat, align 2
   usa_sat = usa * usa_sat;
 
-  // CHECK:      [[UA:%[0-9]+]] = load i32, i32* %ua, align 4
-  // CHECK-NEXT: [[USA:%[0-9]+]] = load i16, i16* %usa_sat, align 2
-  // SIGNED-NEXT: [[USA_EXT:%[a-z0-9]+]] = zext i16 [[USA]] to i32
-  // SIGNED-NEXT: [[USA:%[a-z0-9]+]] = shl i32 [[USA_EXT]], 8
+  // CHECK:       [[UA:%[0-9]+]] = load i32, i32* %ua, align 4
+  // CHECK-NEXT:  [[USA:%[0-9]+]] = load i16, i16* %usa_sat, align 2
+  // CHECK-NEXT:  [[USA_EXT:%[a-z0-9]+]] = zext i16 [[USA]] to i32
+  // CHECK-NEXT:  [[USA:%[a-z0-9]+]] = shl i32 [[USA_EXT]], 8
   // SIGNED-NEXT: [[SUM:%[0-9]+]] = call i32 @llvm.umul.fix.sat.i32(i32 [[UA]], i32 [[USA]], i32 16)
   // SIGNED-NEXT: store i32 [[SUM]], i32* %ua_sat, align 4
-  // UNSIGNED-NEXT: [[UA_TRUNC:%[a-z0-9]+]] = trunc i32 [[UA]] to i31
-  // UNSIGNED-NEXT: [[USA_EXT:%[a-z0-9]+]] = zext i16 [[USA]] to i31
-  // UNSIGNED-NEXT: [[USA:%[a-z0-9]+]] = shl i31 [[USA_EXT]], 8
-  // UNSIGNED-NEXT: [[SUM:%[0-9]+]] = call i31 @llvm.umul.fix.sat.i31(i31 [[UA_TRUNC]], i31 [[USA]], i32 15)
-  // UNSIGNED-NEXT: [[SUM_EXT:%[a-z0-9]+]] = zext i31 [[SUM]] to i32
-  // UNSIGNED-NEXT: store i32 [[SUM_EXT]], i32* %ua_sat, align 4
+  // UNSIGNED-NEXT:    [[SUM:%.*]] = call i32 @llvm.smul.fix.sat.i32(i32 [[UA]], i32 [[USA]], i32 15)
+  // UNSIGNED-NEXT:    [[USE_MIN:%.*]] = icmp slt i32 [[SUM]], 0
+  // UNSIGNED-NEXT:    [[SATMIN:%.*]] = select i1 [[USE_MIN]], i32 0, i32 [[SUM]]
+  // UNSIGNED-NEXT:    store i32 [[SATMIN]], i32* %ua_sat, align 4
   ua_sat = ua * usa_sat;
 
   // CHECK:      [[SA_SAT:%[0-9]+]] = load i16, i16* %sa_sat, align 2
   // CHECK-NEXT: [[I:%[0-9]+]] = load i32, i32* %i, align 4
   // CHECK-NEXT: [[SA_SAT_EXT:%[a-z0-9]+]] = sext i16 [[SA_SAT]] to i39
   // CHECK-NEXT: [[I_EXT:%[a-z0-9]+]] = sext i32 [[I]] to i39
   // CHECK-NEXT: [[I:%[a-z0-9]+]] = shl i39 [[I_EXT]], 7
   // CHECK-NEXT: [[SUM:%[0-9]+]] = call i39 @llvm.smul.fix.sat.i39(i39 [[SA_SAT_EXT]], i39 [[I]], i32 7)
void SaturatedMultiplication() {
   // CHECK-NEXT: [[RES3:%[a-z0-9]+]] = trunc i40 [[RES2]] to i16
   // CHECK-NEXT: store i16 [[RES3]], i16* %sa_sat, align 2
   sa_sat = sa_sat * ui;
 
   // CHECK:      [[UF_SAT:%[0-9]+]] = load i16, i16* %uf_sat, align 2
   // CHECK-NEXT: [[UF_SAT2:%[0-9]+]] = load i16, i16* %uf_sat, align 2
   // SIGNED-NEXT: [[SUM:%[0-9]+]] = call i16 @llvm.umul.fix.sat.i16(i16 [[UF_SAT]], i16 [[UF_SAT2]], i32 16)
   // SIGNED-NEXT: store i16 [[SUM]], i16* %uf_sat, align 2
-  // UNSIGNED-NEXT: [[UF_SAT_TRUNC:%[a-z0-9]+]] = trunc i16 [[UF_SAT]] to i15
-  // UNSIGNED-NEXT: [[UF_SAT_TRUNC2:%[a-z0-9]+]] = trunc i16 [[UF_SAT2]] to i15
-  // UNSIGNED-NEXT: [[SUM:%[0-9]+]] = call i15 @llvm.umul.fix.sat.i15(i15 [[UF_SAT_TRUNC]], i15 [[UF_SAT_TRUNC2]], i32 15)
-  // UNSIGNED-NEXT: [[SUM_EXT:%[a-z0-9]+]] = zext i15 [[SUM]] to i16
-  // UNSIGNED-NEXT: store i16 [[SUM_EXT]], i16* %uf_sat, align 2
+  // UNSIGNED-NEXT:    [[SUM:%.*]] = call i16 @llvm.smul.fix.sat.i16(i16 [[UF_SAT]], i16 [[UF_SAT2]], i32 15)
+  // UNSIGNED-NEXT:    [[USE_MIN:%.*]] = icmp slt i16 [[SUM]], 0
+  // UNSIGNED-NEXT:    [[SATMIN:%.*]] = select i1 [[USE_MIN]], i16 0, i16 [[SUM]]
+  // UNSIGNED-NEXT:    store i16 [[SATMIN]], i16* %uf_sat, align 2
   uf_sat = uf_sat * uf_sat;
 
   // CHECK:      [[USA_SAT:%[0-9]+]] = load i16, i16* %usa_sat, align 2
   // CHECK-NEXT: [[I:%[0-9]+]] = load i32, i32* %i, align 4
   // SIGNED-NEXT: [[USA_SAT_RESIZE:%[a-z0-9]+]] = zext i16 [[USA_SAT]] to i40
   // SIGNED-NEXT: [[I_RESIZE:%[a-z0-9]+]] = sext i32 [[I]] to i40
   // SIGNED-NEXT: [[I_UPSCALE:%[a-z0-9]+]] = shl i40 [[I_RESIZE]], 8
   // SIGNED-NEXT: [[SUM:%[0-9]+]] = call i40 @llvm.smul.fix.sat.i40(i40 [[USA_SAT_RESIZE]], i40 [[I_UPSCALE]], i32 8)

clang/test/Frontend/fixed_point_sub.c

void UnsignedSubtraction() {
   usa = usa - usf;
 
   // CHECK:      [[USA:%[0-9]+]] = load i16, i16* %usa, align 2
   // CHECK-NEXT: [[UF:%[0-9]+]] = load i16, i16* %uf, align 2
   // CHECK-NEXT: [[USA_EXT:%[a-z0-9]+]] = zext i16 [[USA]] to i24
   // CHECK-NEXT: [[USA:%[a-z0-9]+]] = shl i24 [[USA_EXT]], 8
   // CHECK-NEXT: [[UF_EXT:%[a-z0-9]+]] = zext i16 [[UF]] to i24
   // CHECK-NEXT: [[SUM:%[0-9]+]] = sub i24 [[USA]], [[UF_EXT]]
-  // CHECK-NEXT: [[RES:%[a-z0-9]+]] = lshr i24 [[SUM]], 8
+  // SIGNED-NEXT: [[RES:%[a-z0-9]+]] = lshr i24 [[SUM]], 8
+  // UNSIGNED-NEXT: [[RES:%[a-z0-9]+]] = ashr i24 [[SUM]], 8
   // CHECK-NEXT: [[RES_TRUNC:%[a-z0-9]+]] = trunc i24 [[RES]] to i16
   // CHECK-NEXT: store i16 [[RES_TRUNC]], i16* %usa, align 2
   usa = usa - uf;
 }
 
 void IntSubtraction() {
   // CHECK-LABEL: IntSubtraction
   short _Accum sa;
void IntSubtraction() {
 
   // CHECK:      [[USA:%[0-9]+]] = load i16, i16* %usa, align 2
   // CHECK-NEXT: [[I:%[0-9]+]] = load i32, i32* %ui, align 4
   // SIGNED-NEXT: [[USA_EXT:%[a-z0-9]+]] = zext i16 [[USA]] to i40
   // SIGNED-NEXT: [[I_EXT:%[a-z0-9]+]] = zext i32 [[I]] to i40
   // SIGNED-NEXT: [[I:%[a-z0-9]+]] = shl i40 [[I_EXT]], 8
   // SIGNED-NEXT: [[SUM:%[0-9]+]] = sub i40 [[USA_EXT]], [[I]]
   // SIGNED-NEXT: [[RES:%[a-z0-9]+]] = trunc i40 [[SUM]] to i16
-  // UNSIGNED-NEXT: [[USA_EXT:%[a-z0-9]+]] = zext i16 [[USA]] to i39
-  // UNSIGNED-NEXT: [[I_EXT:%[a-z0-9]+]] = zext i32 [[I]] to i39
-  // UNSIGNED-NEXT: [[I:%[a-z0-9]+]] = shl i39 [[I_EXT]], 7
-  // UNSIGNED-NEXT: [[SUM:%[0-9]+]] = sub i39 [[USA_EXT]], [[I]]
-  // UNSIGNED-NEXT: [[RES:%[a-z0-9]+]] = trunc i39 [[SUM]] to i16
+  // UNSIGNED-NEXT: [[USA_EXT:%[a-z0-9]+]] = zext i16 [[USA]] to i40
+  // UNSIGNED-NEXT: [[I_EXT:%[a-z0-9]+]] = zext i32 [[I]] to i40
+  // UNSIGNED-NEXT: [[I:%[a-z0-9]+]] = shl i40 [[I_EXT]], 7
+  // UNSIGNED-NEXT: [[SUM:%[0-9]+]] = sub i40 [[USA_EXT]], [[I]]
+  // UNSIGNED-NEXT: [[RES:%[a-z0-9]+]] = trunc i40 [[SUM]] to i16
   // CHECK-NEXT: store i16 [[RES]], i16* %usa, align 2
   usa = usa - ui;
 
   // CHECK:      [[LF:%[0-9]+]] = load i32, i32* %lf, align 4
   // CHECK-NEXT: [[UI:%[0-9]+]] = load i32, i32* %ui, align 4
   // CHECK-NEXT: [[LF_EXT:%[a-z0-9]+]] = sext i32 [[LF]] to i64
   // CHECK-NEXT: [[UI_EXT:%[a-z0-9]+]] = zext i32 [[UI]] to i64
   // CHECK-NEXT: [[UI:%[a-z0-9]+]] = shl i64 [[UI_EXT]], 31
void SaturatedSubtraction() {
   // [[SA_SAT]])
   // CHECK-NEXT: store i16 [[SUM]], i16* %sa_sat, align 2
   sa_sat = sa - sa_sat;
 
   // CHECK:      [[USA:%[0-9]+]] = load i16, i16* %usa, align 2
   // CHECK-NEXT: [[USA_SAT:%[0-9]+]] = load i16, i16* %usa_sat, align 2
   // SIGNED-NEXT: [[SUM:%[0-9]+]] = call i16 @llvm.usub.sat.i16(i16 [[USA]], i16 [[USA_SAT]])
   // SIGNED-NEXT: store i16 [[SUM]], i16* %usa_sat, align 2
-  // UNSIGNED-NEXT: [[USA_TRUNC:%[a-z0-9]+]] = trunc i16 [[USA]] to i15
-  // UNSIGNED-NEXT: [[USA_SAT_TRUNC:%[a-z0-9]+]] = trunc i16 [[USA_SAT]] to i15
-  // UNSIGNED-NEXT: [[SUM:%[0-9]+]] = call i15 @llvm.usub.sat.i15(i15 [[USA_TRUNC]], i15 [[USA_SAT_TRUNC]])
-  // UNSIGNED-NEXT: [[SUM_EXT:%[a-z0-9]+]] = zext i15 [[SUM]] to i16
-  // UNSIGNED-NEXT: store i16 [[SUM_EXT]], i16* %usa_sat, align 2
+  // UNSIGNED-NEXT: [[SUM:%.*]] = call i16 @llvm.ssub.sat.i16(i16 [[USA]], i16 [[USA_SAT]])
+  // UNSIGNED-NEXT: [[USE_MIN:%.*]] = icmp slt i16 [[SUM]], 0
+  // UNSIGNED-NEXT: [[SATMIN:%.*]] = select i1 [[USE_MIN]], i16 0, i16 [[SUM]]
+  // UNSIGNED-NEXT: store i16 [[SATMIN]], i16* %usa_sat, align 2
   usa_sat = usa - usa_sat;
 
   // CHECK:      [[UA:%[0-9]+]] = load i32, i32* %ua, align 4
   // CHECK-NEXT: [[USA:%[0-9]+]] = load i16, i16* %usa_sat, align 2
   // SIGNED-NEXT: [[USA_EXT:%[a-z0-9]+]] = zext i16 [[USA]] to i32
   // SIGNED-NEXT: [[USA:%[a-z0-9]+]] = shl i32 [[USA_EXT]], 8
   // SIGNED-NEXT: [[SUM:%[0-9]+]] = call i32 @llvm.usub.sat.i32(i32 [[UA]], i32 [[USA]])
   // SIGNED-NEXT: store i32 [[SUM]], i32* %ua_sat, align 4
-  // UNSIGNED-NEXT: [[UA_TRUNC:%[a-z0-9]+]] = trunc i32 [[UA]] to i31
-  // UNSIGNED-NEXT: [[USA_EXT:%[a-z0-9]+]] = zext i16 [[USA]] to i31
-  // UNSIGNED-NEXT: [[USA:%[a-z0-9]+]] = shl i31 [[USA_EXT]], 8
-  // UNSIGNED-NEXT: [[SUM:%[0-9]+]] = call i31 @llvm.usub.sat.i31(i31 [[UA_TRUNC]], i31 [[USA]])
-  // UNSIGNED-NEXT: [[SUM_EXT:%[a-z0-9]+]] = zext i31 [[SUM]] to i32
-  // UNSIGNED-NEXT: store i32 [[SUM_EXT]], i32* %ua_sat, align 4
+  // UNSIGNED-NEXT:    [[RESIZE:%.*]] = zext i16 [[USA]] to i32
+  // UNSIGNED-NEXT:    [[UPSCALE:%.*]] = shl i32 [[RESIZE]], 8
+  // UNSIGNED-NEXT:    [[TMP9:%.*]] = call i32 @llvm.ssub.sat.i32(i32 [[UA]], i32 [[UPSCALE]])
+  // UNSIGNED-NEXT:    [[TMP10:%.*]] = icmp slt i32 [[TMP9]], 0
+  // UNSIGNED-NEXT:    [[SATMIN1:%.*]] = select i1 [[TMP10]], i32 0, i32 [[TMP9]]
+  // UNSIGNED-NEXT:    store i32 [[SATMIN1]], i32* %ua_sat, align 4
   ua_sat = ua - usa_sat;
 
   // CHECK:      [[SA_SAT:%[0-9]+]] = load i16, i16* %sa_sat, align 2
   // CHECK-NEXT: [[I:%[0-9]+]] = load i32, i32* %i, align 4
   // CHECK-NEXT: [[SA_SAT_EXT:%[a-z0-9]+]] = sext i16 [[SA_SAT]] to i39
   // CHECK-NEXT: [[I_EXT:%[a-z0-9]+]] = sext i32 [[I]] to i39
   // CHECK-NEXT: [[I:%[a-z0-9]+]] = shl i39 [[I_EXT]], 7
   // CHECK-NEXT: [[SUM:%[0-9]+]] = call i39 @llvm.ssub.sat.i39(i39 [[SA_SAT_EXT]], i39 [[I]])
void SaturatedSubtraction() {
   // CHECK-NEXT: [[RES3:%[a-z0-9]+]] = trunc i40 [[RES2]] to i16
   // CHECK-NEXT: store i16 [[RES3]], i16* %sa_sat, align 2
   sa_sat = sa_sat - ui;
 
   // CHECK:      [[UF_SAT:%[0-9]+]] = load i16, i16* %uf_sat, align 2
   // CHECK-NEXT: [[UF_SAT2:%[0-9]+]] = load i16, i16* %uf_sat, align 2
   // SIGNED-NEXT: [[SUM:%[0-9]+]] = call i16 @llvm.usub.sat.i16(i16 [[UF_SAT]], i16 [[UF_SAT2]])
   // SIGNED-NEXT: store i16 [[SUM]], i16* %uf_sat, align 2
-  // UNSIGNED-NEXT: [[UF_SAT_TRUNC:%[a-z0-9]+]] = trunc i16 [[UF_SAT]] to i15
-  // UNSIGNED-NEXT: [[UF_SAT_TRUNC2:%[a-z0-9]+]] = trunc i16 [[UF_SAT2]] to i15
-  // UNSIGNED-NEXT: [[SUM:%[0-9]+]] = call i15 @llvm.usub.sat.i15(i15 [[UF_SAT_TRUNC]], i15 [[UF_SAT_TRUNC2]])
-  // UNSIGNED-NEXT: [[SUM_EXT:%[a-z0-9]+]] = zext i15 [[SUM]] to i16
-  // UNSIGNED-NEXT: store i16 [[SUM_EXT]], i16* %uf_sat, align 2
+  // UNSIGNED-NEXT:    [[SUM:%.*]] = call i16 @llvm.ssub.sat.i16(i16 [[UF_SAT]], i16 [[UF_SAT2]])
+  // UNSIGNED-NEXT:    [[USE_MIN:%.*]] = icmp slt i16 [[SUM]], 0
+  // UNSIGNED-NEXT:    [[SATMIN:%.*]] = select i1 [[USE_MIN]], i16 0, i16 [[SUM]]
+  // UNSIGNED-NEXT:    store i16 [[SATMIN]], i16* %uf_sat, align 2
   uf_sat = uf_sat - uf_sat;
 
   // CHECK:      [[USA_SAT:%[0-9]+]] = load i16, i16* %usa_sat, align 2
   // CHECK-NEXT: [[I:%[0-9]+]] = load i32, i32* %i, align 4
   // SIGNED-NEXT: [[USA_SAT_RESIZE:%[a-z0-9]+]] = zext i16 [[USA_SAT]] to i40
   // SIGNED-NEXT: [[I_RESIZE:%[a-z0-9]+]] = sext i32 [[I]] to i40
   // SIGNED-NEXT: [[I_UPSCALE:%[a-z0-9]+]] = shl i40 [[I_RESIZE]], 8
   // SIGNED-NEXT: [[SUM:%[0-9]+]] = call i40 @llvm.ssub.sat.i40(i40 [[USA_SAT_RESIZE]], i40 [[I_UPSCALE]])

clang/test/Frontend/fixed_point_unary.c

 // CHECK-NEXT:    store i16 [[TMP15]], i16* @sf, align 2
   sf++;
 
 // CHECK:         [[TMP16:%.*]] = load i32, i32* @slf, align 4
 // CHECK-NEXT:    [[TMP17:%.*]] = call i32 @llvm.ssub.sat.i32(i32 [[TMP16]], i32 -2147483648)
 // CHECK-NEXT:    store i32 [[TMP17]], i32* @slf, align 4
   slf++;
 
 // CHECK:         [[TMP18:%.*]] = load i32, i32* @sua, align 4
 // SIGNED-NEXT:   [[TMP19:%.*]] = call i32 @llvm.uadd.sat.i32(i32 [[TMP18]], i32 65536)
 // SIGNED-NEXT:   store i32 [[TMP19]], i32* @sua, align 4
-// UNSIGNED-NEXT: [[RESIZE:%.*]] = trunc i32 [[TMP18]] to i31
-// UNSIGNED-NEXT: [[TMP19:%.*]] = call i31 @llvm.uadd.sat.i31(i31 [[RESIZE]], i31 32768)
-// UNSIGNED-NEXT: [[RESIZE1:%.*]] = zext i31 [[TMP19]] to i32
-// UNSIGNED-NEXT: store i32 [[RESIZE1]], i32* @sua, align 4
+// UNSIGNED-NEXT: [[TMP19:%.*]] = call i32 @llvm.sadd.sat.i32(i32 [[TMP18]], i32 32768)
+// UNSIGNED-NEXT: [[TMP20:%.*]] = icmp slt i32 [[TMP19]], 0
+// UNSIGNED-NEXT: [[SATMIN:%.*]] = select i1 [[TMP20]], i32 0, i32 [[TMP19]]
+// UNSIGNED-NEXT: store i32 [[SATMIN]], i32* @sua, align 4
   sua++;
 
 // CHECK:         [[TMP20:%.*]] = load i16, i16* @susa, align 2
 // SIGNED-NEXT:   [[TMP21:%.*]] = call i16 @llvm.uadd.sat.i16(i16 [[TMP20]], i16 256)
 // SIGNED-NEXT:   store i16 [[TMP21]], i16* @susa, align 2
-// UNSIGNED-NEXT: [[RESIZE2:%.*]] = trunc i16 [[TMP20]] to i15
-// UNSIGNED-NEXT: [[TMP21:%.*]] = call i15 @llvm.uadd.sat.i15(i15 [[RESIZE2]], i15 128)
-// UNSIGNED-NEXT: [[RESIZE3:%.*]] = zext i15 [[TMP21]] to i16
-// UNSIGNED-NEXT: store i16 [[RESIZE3]], i16* @susa, align 2
+// UNSIGNED-NEXT: [[TMP22:%.*]] = call i16 @llvm.sadd.sat.i16(i16 [[TMP20]], i16 128)
+// UNSIGNED-NEXT: [[TMP23:%.*]] = icmp slt i16 [[TMP22]], 0
+// UNSIGNED-NEXT: [[SATMIN1:%.*]] = select i1 [[TMP23]], i16 0, i16 [[TMP22]]
+// UNSIGNED-NEXT: store i16 [[SATMIN1]], i16* @susa, align 2
   susa++;
 
 // CHECK:         [[TMP22:%.*]] = load i16, i16* @suf, align 2
 // SIGNED-NEXT:   [[TMP23:%.*]] = call i16 @llvm.uadd.sat.i16(i16 [[TMP22]], i16 -1)
 // SIGNED-NEXT:   store i16 [[TMP23]], i16* @suf, align 2
-// UNSIGNED-NEXT: [[RESIZE4:%.*]] = trunc i16 [[TMP22]] to i15
-// UNSIGNED-NEXT: [[TMP23:%.*]] = call i15 @llvm.uadd.sat.i15(i15 [[RESIZE4]], i15 -1)
-// UNSIGNED-NEXT: [[RESIZE5:%.*]] = zext i15 [[TMP23]] to i16
-// UNSIGNED-NEXT: store i16 [[RESIZE5]], i16* @suf, align 2
+// UNSIGNED-NEXT: [[TMP25:%.*]] = call i16 @llvm.sadd.sat.i16(i16 [[TMP22]], i16 32767)
+// UNSIGNED-NEXT: [[TMP26:%.*]] = icmp slt i16 [[TMP25]], 0
+// UNSIGNED-NEXT: [[SATMIN2:%.*]] = select i1 [[TMP26]], i16 0, i16 [[TMP25]]
+// UNSIGNED-NEXT: store i16 [[SATMIN2]], i16* @suf, align 2
   suf++;
 }
 
 // CHECK-LABEL: @Decrement(
 void Decrement() {
 // CHECK:         [[TMP0:%.*]] = load i32, i32* @a, align 4
 // CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[TMP0]], -32768
 // CHECK-NEXT:    store i32 [[TMP1]], i32* @a, align 4

 // CHECK-NEXT:    store i16 [[TMP15]], i16* @sf, align 2
   sf--;
 
 // CHECK:         [[TMP16:%.*]] = load i32, i32* @slf, align 4
 // CHECK-NEXT:    [[TMP17:%.*]] = call i32 @llvm.sadd.sat.i32(i32 [[TMP16]], i32 -2147483648)
 // CHECK-NEXT:    store i32 [[TMP17]], i32* @slf, align 4
   slf--;
 
 // CHECK:         [[TMP18:%.*]] = load i32, i32* @sua, align 4
 // SIGNED-NEXT:   [[TMP19:%.*]] = call i32 @llvm.usub.sat.i32(i32 [[TMP18]], i32 65536)
 // SIGNED-NEXT:   store i32 [[TMP19]], i32* @sua, align 4
-// UNSIGNED-NEXT: [[RESIZE:%.*]] = trunc i32 [[TMP18]] to i31
-// UNSIGNED-NEXT: [[TMP19:%.*]] = call i31 @llvm.usub.sat.i31(i31 [[RESIZE]], i31 32768)
-// UNSIGNED-NEXT: [[RESIZE1:%.*]] = zext i31 [[TMP19]] to i32
-// UNSIGNED-NEXT: store i32 [[RESIZE1]], i32* @sua, align 4
+// UNSIGNED-NEXT: [[TMP19:%.*]] = call i32 @llvm.ssub.sat.i32(i32 [[TMP18]], i32 32768)
+// UNSIGNED-NEXT: [[TMP20:%.*]] = icmp slt i32 [[TMP19]], 0
+// UNSIGNED-NEXT: [[SATMIN:%.*]] = select i1 [[TMP20]], i32 0, i32 [[TMP19]]
+// UNSIGNED-NEXT: store i32 [[SATMIN]], i32* @sua, align 4
   sua--;
 
 // CHECK:         [[TMP20:%.*]] = load i16, i16* @susa, align 2
 // SIGNED-NEXT:   [[TMP21:%.*]] = call i16 @llvm.usub.sat.i16(i16 [[TMP20]], i16 256)
 // SIGNED-NEXT:   store i16 [[TMP21]], i16* @susa, align 2
-// UNSIGNED-NEXT: [[RESIZE2:%.*]] = trunc i16 [[TMP20]] to i15
-// UNSIGNED-NEXT: [[TMP21:%.*]] = call i15 @llvm.usub.sat.i15(i15 [[RESIZE2]], i15 128)
-// UNSIGNED-NEXT: [[RESIZE3:%.*]] = zext i15 [[TMP21]] to i16
-// UNSIGNED-NEXT: store i16 [[RESIZE3]], i16* @susa, align 2
+// UNSIGNED-NEXT: [[TMP22:%.*]] = call i16 @llvm.ssub.sat.i16(i16 [[TMP20]], i16 128)
+// UNSIGNED-NEXT: [[TMP23:%.*]] = icmp slt i16 [[TMP22]], 0
+// UNSIGNED-NEXT: [[SATMIN1:%.*]] = select i1 [[TMP23]], i16 0, i16 [[TMP22]]
+// UNSIGNED-NEXT: store i16 [[SATMIN1]], i16* @susa, align 2
   susa--;
 
 // CHECK:         [[TMP22:%.*]] = load i16, i16* @suf, align 2
 // SIGNED-NEXT:   [[TMP23:%.*]] = call i16 @llvm.usub.sat.i16(i16 [[TMP22]], i16 -1)
 // SIGNED-NEXT:   store i16 [[TMP23]], i16* @suf, align 2
-// UNSIGNED-NEXT: [[RESIZE4:%.*]] = trunc i16 [[TMP22]] to i15
-// UNSIGNED-NEXT: [[TMP23:%.*]] = call i15 @llvm.usub.sat.i15(i15 [[RESIZE4]], i15 -1)
-// UNSIGNED-NEXT: [[RESIZE5:%.*]] = zext i15 [[TMP23]] to i16
-// UNSIGNED-NEXT: store i16 [[RESIZE5]], i16* @suf, align 2
+// UNSIGNED-NEXT: [[TMP25:%.*]] = call i16 @llvm.ssub.sat.i16(i16 [[TMP22]], i16 32767)
+// UNSIGNED-NEXT: [[TMP26:%.*]] = icmp slt i16 [[TMP25]], 0
+// UNSIGNED-NEXT: [[SATMIN2:%.*]] = select i1 [[TMP26]], i16 0, i16 [[TMP25]]
+// UNSIGNED-NEXT: store i16 [[SATMIN2]], i16* @suf, align 2
   suf--;
 }
 
 // CHECK-LABEL: @Minus(
 void Minus() {
 // CHECK:         [[TMP0:%.*]] = load i32, i32* @a, align 4
 // CHECK-NEXT:    [[TMP1:%.*]] = sub i32 0, [[TMP0]]
 // CHECK-NEXT:    store i32 [[TMP1]], i32* @a, align 4

 // CHECK-NEXT:    store i32 [[TMP9]], i32* @sa, align 4
   sa = -sa;
 
 // CHECK:         [[TMP10:%.*]] = load i16, i16* @sf, align 2
 // CHECK-NEXT:    [[TMP11:%.*]] = call i16 @llvm.ssub.sat.i16(i16 0, i16 [[TMP10]])
 // CHECK-NEXT:    store i16 [[TMP11]], i16* @sf, align 2
   sf = -sf;
 
 // CHECK:         [[TMP12:%.*]] = load i16, i16* @susa, align 2
 // SIGNED-NEXT:   [[TMP13:%.*]] = call i16 @llvm.usub.sat.i16(i16 0, i16 [[TMP12]])
 // SIGNED-NEXT:   store i16 [[TMP13]], i16* @susa, align 2
-// UNSIGNED-NEXT: [[RESIZE:%.*]] = trunc i16 [[TMP12]] to i15
-// UNSIGNED-NEXT: [[TMP13:%.*]] = call i15 @llvm.usub.sat.i15(i15 0, i15 [[RESIZE]])
-// UNSIGNED-NEXT: [[RESIZE1:%.*]] = zext i15 [[TMP13]] to i16
-// UNSIGNED-NEXT: store i16 [[RESIZE1]], i16* @susa, align 2
+// UNSIGNED-NEXT: [[TMP13:%.*]] = call i16 @llvm.ssub.sat.i16(i16 0, i16 [[TMP12]])
+// UNSIGNED-NEXT: [[TMP14:%.*]] = icmp slt i16 [[TMP13]], 0
+// UNSIGNED-NEXT: [[SATMIN:%.*]] = select i1 [[TMP14]], i16 0, i16 [[TMP13]]
+// UNSIGNED-NEXT: store i16 [[SATMIN]], i16* @susa, align 2
   susa = -susa;
 
 // CHECK:         [[TMP14:%.*]] = load i16, i16* @suf, align 2
 // SIGNED-NEXT:   [[TMP15:%.*]] = call i16 @llvm.usub.sat.i16(i16 0, i16 [[TMP14]])
 // SIGNED-NEXT:   store i16 [[TMP15]], i16* @suf, align 2
-// UNSIGNED-NEXT: [[RESIZE2:%.*]] = trunc i16 [[TMP14]] to i15
-// UNSIGNED-NEXT: [[TMP15:%.*]] = call i15 @llvm.usub.sat.i15(i15 0, i15 [[RESIZE2]])
-// UNSIGNED-NEXT: [[RESIZE3:%.*]] = zext i15 [[TMP15]] to i16
-// UNSIGNED-NEXT: store i16 [[RESIZE3]], i16* @suf, align 2
+// UNSIGNED-NEXT: [[TMP16:%.*]] = call i16 @llvm.ssub.sat.i16(i16 0, i16 [[TMP14]])
+// UNSIGNED-NEXT: [[TMP17:%.*]] = icmp slt i16 [[TMP16]], 0
+// UNSIGNED-NEXT: [[SATMIN1:%.*]] = select i1 [[TMP17]], i16 0, i16 [[TMP16]]
+// UNSIGNED-NEXT: store i16 [[SATMIN1]], i16* @suf, align 2
   suf = -suf;
 }
 
 // CHECK-LABEL: @Plus(
 void Plus() {
 // CHECK:         [[TMP0:%.*]] = load i32, i32* @a, align 4
 // CHECK-NEXT:    store i32 [[TMP0]], i32* @a, align 4
   a = +a;