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Differential D81968

[AVR] Decode single register instructions
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Authored by aykevl on Jun 16 2020, 2:15 PM.

Details

Reviewers
dylanmckay
Commits
rG01c2209d518c: [AVR] Decode single register instructions
Summary

This is a set of instructions that take just a single register as an operand, with no immediates. Because all instructions share the same format, I haven't added exhaustive bit testing to all instructions but just to the inc instruction.

Diff Detail

Event Timeline

aykevl created this revision.Jun 16 2020, 2:15 PM
Herald added subscribers: Jim, hiraditya. · View Herald TranscriptJun 16 2020, 2:15 PM
Harbormaster failed remote builds in B60541: Diff 271194!Jun 16 2020, 2:20 PM
dylanmckay requested changes to this revision.Jun 17 2020, 10:51 PM
dylanmckay added inline comments.
llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
159

Fit to 80 columns (ref)

My own OCD: prefer return on a new line

This revision now requires changes to proceed.Jun 17 2020, 10:51 PM
aykevl updated this revision to Diff 271645.Jun 18 2020, 3:32 AM
  • updated formatting

This isn't exactly 80 chars, but it's a lot better than before. I agree that this style return is more readable. I'm not sure cutting those last two or so characters will make the code more readable.

Harbormaster failed remote builds in B60794: Diff 271645!Jun 18 2020, 5:24 AM
dylanmckay accepted this revision.Jun 18 2020, 10:13 PM
This revision is now accepted and ready to land.Jun 18 2020, 10:14 PM
Closed by commit rG01c2209d518c: [AVR] Decode single register instructions (authored by aykevl). · Explain WhyJun 22 2020, 5:45 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
AVR/
2 lines
Disassembler/
11 lines
test/
MC/
AVR/
6 lines
6 lines
6 lines
12 lines
6 lines
6 lines
6 lines
6 lines
6 lines
6 lines

Diff 272574

llvm/lib/Target/AVR/AVRInstrFormats.td

Show First 20 Lines • Show All 142 Lines • ▼ Show 20 Linesclass FRd<bits<4> opcode, bits<7> f, dag outs, dag ins, string asmstr,
list<dag> pattern> : AVRInst16<outs, ins, asmstr, pattern> list<dag> pattern> : AVRInst16<outs, ins, asmstr, pattern>
{ {
bits<5> d; bits<5> d;
let Inst{15-12} = opcode; let Inst{15-12} = opcode;
let Inst{11-9} = f{6-4}; let Inst{11-9} = f{6-4};
let Inst{8-4} = d; let Inst{8-4} = d;
let Inst{3-0} = f{3-0}; let Inst{3-0} = f{3-0};
let DecoderMethod = "decodeFRd";
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// [STD/LDD] P+q, Rr special encoding: <|10q0|qqtr|rrrr|pqqq> // [STD/LDD] P+q, Rr special encoding: <|10q0|qqtr|rrrr|pqqq>
// t = type (1 for STD, 0 for LDD) // t = type (1 for STD, 0 for LDD)
// q = displacement (6 bits) // q = displacement (6 bits)
// r = register (5 bits) // r = register (5 bits)
// p = pointer register (1 bit) [1 for Y, 0 for Z] // p = pointer register (1 bit) [1 for Y, 0 for Z]
▲ Show 20 Lines • Show All 426 Lines • Show Last 20 Lines

llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp

Show First 20 Lines • Show All 101 Lines • ▼ Show 20 Linesstatic DecodeStatus decodeFIORdA(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus decodeFIOBIT(MCInst &Inst, unsigned Insn, static DecodeStatus decodeFIOBIT(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus decodeCallTarget(MCInst &Inst, unsigned Insn, static DecodeStatus decodeCallTarget(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus decodeFRd(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
#include "AVRGenDisassemblerTables.inc" #include "AVRGenDisassemblerTables.inc"
static DecodeStatus decodeFIOARr(MCInst &Inst, unsigned Insn, static DecodeStatus decodeFIOARr(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
unsigned addr = 0; unsigned addr = 0;
addr |= fieldFromInstruction(Insn, 0, 4); addr |= fieldFromInstruction(Insn, 0, 4);
addr |= fieldFromInstruction(Insn, 9, 2) << 4; addr |= fieldFromInstruction(Insn, 9, 2) << 4;
unsigned reg = fieldFromInstruction(Insn, 4, 5); unsigned reg = fieldFromInstruction(Insn, 4, 5);
Show All 27 Lines
static DecodeStatus decodeCallTarget(MCInst &Inst, unsigned Field, static DecodeStatus decodeCallTarget(MCInst &Inst, unsigned Field,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
// Call targets need to be shifted left by one so this needs a custom // Call targets need to be shifted left by one so this needs a custom
// decoder. // decoder.
Inst.addOperand(MCOperand::createImm(Field << 1)); Inst.addOperand(MCOperand::createImm(Field << 1));
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus decodeFRd(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
unsigned d = fieldFromInstruction(Insn, 4, 5);
if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) == MCDisassembler::Fail)
dylanmckayUnsubmitted
Not Done
ReplyInline Actions

Fit to 80 columns (ref)

My own OCD: prefer return on a new line

dylanmckay: Fit to 80 columns ([ref](https://llvm.org/docs/CodingStandards.html#source-code-width)) My own…
return MCDisassembler::Fail;
return MCDisassembler::Success;
}
static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
uint64_t &Size, uint32_t &Insn) { uint64_t &Size, uint32_t &Insn) {
if (Bytes.size() < 2) { if (Bytes.size() < 2) {
Size = 0; Size = 0;
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
Size = 2; Size = 2;
▲ Show 20 Lines • Show All 70 Lines • Show Last 20 Lines

llvm/test/MC/AVR/inst-asr.s

; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s ; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
foo: foo:
asr r31 asr r31
asr r25 asr r25
asr r5 asr r5
asr r0 asr r0
; CHECK: asr r31 ; encoding: [0xf5,0x95] ; CHECK: asr r31 ; encoding: [0xf5,0x95]
; CHECK: asr r25 ; encoding: [0x95,0x95] ; CHECK: asr r25 ; encoding: [0x95,0x95]
; CHECK: asr r5 ; encoding: [0x55,0x94] ; CHECK: asr r5 ; encoding: [0x55,0x94]
; CHECK: asr r0 ; encoding: [0x05,0x94] ; CHECK: asr r0 ; encoding: [0x05,0x94]
; CHECK-INST: asr r31
; CHECK-INST: asr r25
; CHECK-INST: asr r5
; CHECK-INST: asr r0

llvm/test/MC/AVR/inst-com.s

; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s ; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
foo: foo:
com r30 com r30
com r17 com r17
com r4 com r4
com r0 com r0
; CHECK: com r30 ; encoding: [0xe0,0x95] ; CHECK: com r30 ; encoding: [0xe0,0x95]
; CHECK: com r17 ; encoding: [0x10,0x95] ; CHECK: com r17 ; encoding: [0x10,0x95]
; CHECK: com r4 ; encoding: [0x40,0x94] ; CHECK: com r4 ; encoding: [0x40,0x94]
; CHECK: com r0 ; encoding: [0x00,0x94] ; CHECK: com r0 ; encoding: [0x00,0x94]
; CHECK-INST: com r30
; CHECK-INST: com r17
; CHECK-INST: com r4
; CHECK-INST: com r0

llvm/test/MC/AVR/inst-dec.s

; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s ; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
foo: foo:
dec r26 dec r26
dec r3 dec r3
dec r24 dec r24
dec r20 dec r20
; CHECK: dec r26 ; encoding: [0xaa,0x95] ; CHECK: dec r26 ; encoding: [0xaa,0x95]
; CHECK: dec r3 ; encoding: [0x3a,0x94] ; CHECK: dec r3 ; encoding: [0x3a,0x94]
; CHECK: dec r24 ; encoding: [0x8a,0x95] ; CHECK: dec r24 ; encoding: [0x8a,0x95]
; CHECK: dec r20 ; encoding: [0x4a,0x95] ; CHECK: dec r20 ; encoding: [0x4a,0x95]
; CHECK-INST: dec r26
; CHECK-INST: dec r3
; CHECK-INST: dec r24
; CHECK-INST: dec r20

llvm/test/MC/AVR/inst-inc.s

; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s ; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
foo: foo:
inc r12 inc r12
inc r29 inc r29
inc r6 inc r6
inc r20 inc r20
inc r0
inc r31
; CHECK: inc r12 ; encoding: [0xc3,0x94] ; CHECK: inc r12 ; encoding: [0xc3,0x94]
; CHECK: inc r29 ; encoding: [0xd3,0x95] ; CHECK: inc r29 ; encoding: [0xd3,0x95]
; CHECK: inc r6 ; encoding: [0x63,0x94] ; CHECK: inc r6 ; encoding: [0x63,0x94]
; CHECK: inc r20 ; encoding: [0x43,0x95] ; CHECK: inc r20 ; encoding: [0x43,0x95]
; CHECK: inc r0 ; encoding: [0x03,0x94]
; CHECK: inc r31 ; encoding: [0xf3,0x95]
; CHECK-INST: inc r12
; CHECK-INST: inc r29
; CHECK-INST: inc r6
; CHECK-INST: inc r20
; CHECK-INST: inc r0
; CHECK-INST: inc r31

llvm/test/MC/AVR/inst-lsr.s

; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s ; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
foo: foo:
lsr r31 lsr r31
lsr r25 lsr r25
lsr r5 lsr r5
lsr r0 lsr r0
; CHECK: lsr r31 ; encoding: [0xf6,0x95] ; CHECK: lsr r31 ; encoding: [0xf6,0x95]
; CHECK: lsr r25 ; encoding: [0x96,0x95] ; CHECK: lsr r25 ; encoding: [0x96,0x95]
; CHECK: lsr r5 ; encoding: [0x56,0x94] ; CHECK: lsr r5 ; encoding: [0x56,0x94]
; CHECK: lsr r0 ; encoding: [0x06,0x94] ; CHECK: lsr r0 ; encoding: [0x06,0x94]
; CHECK-INST: lsr r31
; CHECK-INST: lsr r25
; CHECK-INST: lsr r5
; CHECK-INST: lsr r0

llvm/test/MC/AVR/inst-neg.s

; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s ; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
foo: foo:
neg r15 neg r15
neg r1 neg r1
neg r22 neg r22
neg r31 neg r31
; CHECK: neg r15 ; encoding: [0xf1,0x94] ; CHECK: neg r15 ; encoding: [0xf1,0x94]
; CHECK: neg r1 ; encoding: [0x11,0x94] ; CHECK: neg r1 ; encoding: [0x11,0x94]
; CHECK: neg r22 ; encoding: [0x61,0x95] ; CHECK: neg r22 ; encoding: [0x61,0x95]
; CHECK: neg r31 ; encoding: [0xf1,0x95] ; CHECK: neg r31 ; encoding: [0xf1,0x95]
; CHECK-INST: neg r15
; CHECK-INST: neg r1
; CHECK-INST: neg r22
; CHECK-INST: neg r31

llvm/test/MC/AVR/inst-pop.s

; RUN: llvm-mc -triple avr -mattr=sram -show-encoding < %s | FileCheck %s ; RUN: llvm-mc -triple avr -mattr=sram -show-encoding < %s | FileCheck %s
; RUN: llvm-mc -filetype=obj -triple avr -mattr=sram < %s | llvm-objdump -d --mattr=sram - | FileCheck -check-prefix=CHECK-INST %s
foo: foo:
pop r31 pop r31
pop r25 pop r25
pop r5 pop r5
pop r0 pop r0
; CHECK: pop r31 ; encoding: [0xff,0x91] ; CHECK: pop r31 ; encoding: [0xff,0x91]
; CHECK: pop r25 ; encoding: [0x9f,0x91] ; CHECK: pop r25 ; encoding: [0x9f,0x91]
; CHECK: pop r5 ; encoding: [0x5f,0x90] ; CHECK: pop r5 ; encoding: [0x5f,0x90]
; CHECK: pop r0 ; encoding: [0x0f,0x90] ; CHECK: pop r0 ; encoding: [0x0f,0x90]
; CHECK-INST: pop r31
; CHECK-INST: pop r25
; CHECK-INST: pop r5
; CHECK-INST: pop r0

llvm/test/MC/AVR/inst-push.s

; RUN: llvm-mc -triple avr -mattr=sram -show-encoding < %s | FileCheck %s ; RUN: llvm-mc -triple avr -mattr=sram -show-encoding < %s | FileCheck %s
; RUN: llvm-mc -filetype=obj -triple avr -mattr=sram < %s | llvm-objdump -d --mattr=sram - | FileCheck -check-prefix=CHECK-INST %s
foo: foo:
push r31 push r31
push r25 push r25
push r5 push r5
push r0 push r0
; CHECK: push r31 ; encoding: [0xff,0x93] ; CHECK: push r31 ; encoding: [0xff,0x93]
; CHECK: push r25 ; encoding: [0x9f,0x93] ; CHECK: push r25 ; encoding: [0x9f,0x93]
; CHECK: push r5 ; encoding: [0x5f,0x92] ; CHECK: push r5 ; encoding: [0x5f,0x92]
; CHECK: push r0 ; encoding: [0x0f,0x92] ; CHECK: push r0 ; encoding: [0x0f,0x92]
; CHECK-INST: push r31
; CHECK-INST: push r25
; CHECK-INST: push r5
; CHECK-INST: push r0

llvm/test/MC/AVR/inst-ror.s

; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s ; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
foo: foo:
ror r31 ror r31
ror r25 ror r25
ror r5 ror r5
ror r0 ror r0
; CHECK: ror r31 ; encoding: [0xf7,0x95] ; CHECK: ror r31 ; encoding: [0xf7,0x95]
; CHECK: ror r25 ; encoding: [0x97,0x95] ; CHECK: ror r25 ; encoding: [0x97,0x95]
; CHECK: ror r5 ; encoding: [0x57,0x94] ; CHECK: ror r5 ; encoding: [0x57,0x94]
; CHECK: ror r0 ; encoding: [0x07,0x94] ; CHECK: ror r0 ; encoding: [0x07,0x94]
; CHECK-INST: ror r31
; CHECK-INST: ror r25
; CHECK-INST: ror r5
; CHECK-INST: ror r0

llvm/test/MC/AVR/inst-swap.s

; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s ; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
foo: foo:
swap r31 swap r31
swap r25 swap r25
swap r5 swap r5
swap r0 swap r0
; CHECK: swap r31 ; encoding: [0xf2,0x95] ; CHECK: swap r31 ; encoding: [0xf2,0x95]
; CHECK: swap r25 ; encoding: [0x92,0x95] ; CHECK: swap r25 ; encoding: [0x92,0x95]
; CHECK: swap r5 ; encoding: [0x52,0x94] ; CHECK: swap r5 ; encoding: [0x52,0x94]
; CHECK: swap r0 ; encoding: [0x02,0x94] ; CHECK: swap r0 ; encoding: [0x02,0x94]
; CHECK-INST: swap r31
; CHECK-INST: swap r25
; CHECK-INST: swap r5
; CHECK-INST: swap r0