[ARM] Fix crash trying to generate i1 immediates

[dmgreen]

Summary

These code patterns attempt to call isVMOVModifiedImm on a splat of i1 values, leading to an unreachable being hit. I've guarded the call on a more specific set of sizes, as i1 is legal under MVE.

[ostannard]

LGTM

[dmgreen]

Thanks.

[uabelho]

llvm/test/CodeGen/Thumb2/mve-vmovimm.ll

549

Hi!
I've no idea if this might be a real problem or not, but I noticed when I ran this testcase that we end up in this code in BuildVectorSDNode::isConstantSplat (SelectionDAG.cpp line 9660):

// FIXME: This does not work for vectors with elements less than 8 bits.
while (VecWidth > 8) {
  unsigned HalfSize = VecWidth / 2;

with VT being v4i1. VecWidth is 4 so the loop won't do anything in this case.
At least according to the FIXME it doesn't seem good, but perhaps the comment is overly cautious.
(I just thought I'd share this since in our downstream clone we have an assert there that suddenly failed on this testcase.)

[dmgreen]

Thanks for the info! That does sound like something that's worth avoiding. I'll try and change things around so that it never gets called on an i1 vector.

llvm/lib/Target/ARM/ARMISelLowering.cpp

static SDValue PerformANDCombine(SDNode *N,
   if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
     return SDValue();
 
   APInt SplatBits, SplatUndef;
   unsigned SplatBitSize;
   bool HasAnyUndefs;
   if (BVN && (Subtarget->hasNEON() || Subtarget->hasMVEIntegerOps()) &&
       BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
-    if (SplatBitSize <= 64) {
+    if (SplatBitSize == 8 || SplatBitSize == 16 || SplatBitSize == 32 ||
+        SplatBitSize == 64) {
       EVT VbicVT;
       SDValue Val = isVMOVModifiedImm((~SplatBits).getZExtValue(),
                                       SplatUndef.getZExtValue(), SplatBitSize,
                                       DAG, dl, VbicVT, VT, OtherModImm);
       if (Val.getNode()) {
         SDValue Input =
           DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0));
         SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val);
static SDValue PerformORCombine(SDNode *N,
   if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
     return SDValue();
 
   APInt SplatBits, SplatUndef;
   unsigned SplatBitSize;
   bool HasAnyUndefs;
   if (BVN && (Subtarget->hasNEON() || Subtarget->hasMVEIntegerOps()) &&
       BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
-    if (SplatBitSize <= 64) {
+    if (SplatBitSize == 8 || SplatBitSize == 16 || SplatBitSize == 32 ||
+        SplatBitSize == 64) {
       EVT VorrVT;
       SDValue Val =
           isVMOVModifiedImm(SplatBits.getZExtValue(), SplatUndef.getZExtValue(),
                             SplatBitSize, DAG, dl, VorrVT, VT, OtherModImm);
       if (Val.getNode()) {
         SDValue Input =
           DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0));
         SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val);

llvm/test/CodeGen/Thumb2/mve-vmovimm.ll

 ; CHECKBE-NEXT:    vrev64.16 q1, q0
 ; CHECKBE-NEXT:    vorr q1, q1, q2
 ; CHECKBE-NEXT:    vrev64.16 q0, q1
 ; CHECKBE-NEXT:    bx lr
 entry:
   %o = or <8 x i16> %i, <i16 -1, i16 0, i16 -1, i16 -1, i16 -1, i16 0, i16 -1, i16 -1>
   ret <8 x i16> %o
 }
+
+define arm_aapcs_vfpcc <4 x i32> @i1and_vmov(<4 x i32> %a, <4 x i32> %b, i32 %c) {
+; CHECKLE-LABEL: i1and_vmov:
+; CHECKLE:       @ %bb.0: @ %entry
+; CHECKLE-NEXT:    cmp r0, #0
+; CHECKLE-NEXT:    mov.w r1, #15
+; CHECKLE-NEXT:    cset r0, eq
+; CHECKLE-NEXT:    and r0, r0, #1
+; CHECKLE-NEXT:    rsbs r0, r0, #0
+; CHECKLE-NEXT:    ands r0, r1
+; CHECKLE-NEXT:    vmsr p0, r0
+; CHECKLE-NEXT:    vpsel q0, q0, q1
+; CHECKLE-NEXT:    bx lr
+;
+; CHECKBE-LABEL: i1and_vmov:
+; CHECKBE:       @ %bb.0: @ %entry
+; CHECKBE-NEXT:    cmp r0, #0
+; CHECKBE-NEXT:    mov.w r1, #15
+; CHECKBE-NEXT:    cset r0, eq
+; CHECKBE-NEXT:    vrev64.32 q2, q1
+; CHECKBE-NEXT:    and r0, r0, #1
+; CHECKBE-NEXT:    vrev64.32 q1, q0
+; CHECKBE-NEXT:    rsbs r0, r0, #0
+; CHECKBE-NEXT:    ands r0, r1
+; CHECKBE-NEXT:    vmsr p0, r0
+; CHECKBE-NEXT:    vpsel q1, q1, q2
+; CHECKBE-NEXT:    vrev64.32 q0, q1
+; CHECKBE-NEXT:    bx lr
+entry:
+  %c1 = icmp eq i32 %c, zeroinitializer
+  %broadcast.splatinsert1967 = insertelement <4 x i1> undef, i1 %c1, i32 0
+  %broadcast.splat1968 = shufflevector <4 x i1> %broadcast.splatinsert1967, <4 x i1> undef, <4 x i32> zeroinitializer
+  %l699 = and <4 x i1> %broadcast.splat1968, <i1 true, i1 false, i1 false, i1 false>
+  %s = select <4 x i1> %l699, <4 x i32> %a, <4 x i32> %b
+  ret <4 x i32> %s
+}
+
+define arm_aapcs_vfpcc <4 x i32> @i1or_vmov(<4 x i32> %a, <4 x i32> %b, i32 %c) {
+; CHECKLE-LABEL: i1or_vmov:
+; CHECKLE:       @ %bb.0: @ %entry
+; CHECKLE-NEXT:    cmp r0, #0
+; CHECKLE-NEXT:    mov.w r1, #15
+; CHECKLE-NEXT:    cset r0, eq
+; CHECKLE-NEXT:    and r0, r0, #1
+; CHECKLE-NEXT:    rsbs r0, r0, #0
+; CHECKLE-NEXT:    orrs r0, r1
+; CHECKLE-NEXT:    vmsr p0, r0
+; CHECKLE-NEXT:    vpsel q0, q0, q1
+; CHECKLE-NEXT:    bx lr
+;
+; CHECKBE-LABEL: i1or_vmov:
+; CHECKBE:       @ %bb.0: @ %entry
+; CHECKBE-NEXT:    cmp r0, #0
+; CHECKBE-NEXT:    mov.w r1, #15
+; CHECKBE-NEXT:    cset r0, eq
+; CHECKBE-NEXT:    vrev64.32 q2, q1
+; CHECKBE-NEXT:    and r0, r0, #1
+; CHECKBE-NEXT:    vrev64.32 q1, q0
+; CHECKBE-NEXT:    rsbs r0, r0, #0
+; CHECKBE-NEXT:    orrs r0, r1
+; CHECKBE-NEXT:    vmsr p0, r0
+; CHECKBE-NEXT:    vpsel q1, q1, q2
+; CHECKBE-NEXT:    vrev64.32 q0, q1
+; CHECKBE-NEXT:    bx lr
+entry:
+  %c1 = icmp eq i32 %c, zeroinitializer
+  %broadcast.splatinsert1967 = insertelement <4 x i1> undef, i1 %c1, i32 0
+  %broadcast.splat1968 = shufflevector <4 x i1> %broadcast.splatinsert1967, <4 x i1> undef, <4 x i32> zeroinitializer
+  %l699 = or <4 x i1> %broadcast.splat1968, <i1 true, i1 false, i1 false, i1 false>
+  %s = select <4 x i1> %l699, <4 x i32> %a, <4 x i32> %b
+  ret <4 x i32> %s
+}