diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
--- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
+++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
@@ -92,41 +92,241 @@
     return;
   }
 
-  // Check for slwi/srwi mnemonics.
-  if (MI->getOpcode() == PPC::RLWINM) {
+  // Check for RLDIMI mnemonics.
+  if (MI->getOpcode() == PPC::RLDIMI || MI->getOpcode() == PPC::RLDIMI_rec) {
+    unsigned char SH = MI->getOperand(3).getImm();
+    unsigned char MB = MI->getOperand(4).getImm();
+
+    if  (MB + SH < 64) {
+      // Check for insrdi
+      if (MI->getOpcode() == PPC::RLDIMI)
+        O << "\tinsrdi ";
+      else
+        O << "\tinsrdi. ";
+      SH = 64 - MB - SH;
+
+      // Op0 is same with Op1, but Op1 is input, Op0 is output.
+      printOperand(MI, 0, O);
+      O << ", ";
+      printOperand(MI, 2, O);
+      O << ", " << (unsigned int)SH;
+      O << ", " << (unsigned int)MB;
+
+      printAnnotation(O, Annot);
+      return;
+    }
+  }
+
+  // Check for RLWIMI mnemonics.
+  if (MI->getOpcode() == PPC::RLWIMI || MI->getOpcode() == PPC::RLWIMI_rec ||
+      MI->getOpcode() == PPC::RLWIMI8 || MI->getOpcode() == PPC::RLWIMI8_rec) {
+    unsigned char SH = MI->getOperand(3).getImm();
+    unsigned char MB = MI->getOperand(4).getImm();
+    unsigned char ME = MI->getOperand(5).getImm();
+    int Op2 = -1;
+
+    if  (SH && SH < 32 && MB == (32 - SH) && (ME + SH) > 31) {
+      // Check for inslwi
+      if (MI->getOpcode() == PPC::RLWIMI || MI->getOpcode() == PPC::RLWIMI8)
+        O << "\tinslwi ";
+      else
+        O << "\tinslwi. ";
+      Op2 = ME + SH - 31;
+    } else if  (SH <= 31 && ME == (31 - SH) && (MB + SH) < 32) {
+      // Check for insrwi
+      if (MI->getOpcode() == PPC::RLWIMI || MI->getOpcode() == PPC::RLWIMI8)
+        O << "\tinsrwi ";
+      else
+        O << "\tinsrwi. ";
+      Op2 = 32 - MB - SH;
+    }
+
+    if (Op2 > -1) {
+      // Op0 is same with Op1, but Op1 is input, Op0 is output.
+      printOperand(MI, 0, O);
+      O << ", ";
+      printOperand(MI, 2, O);
+      O << ", " << (unsigned int)Op2;
+      O << ", " << (unsigned int)MB;
+
+      printAnnotation(O, Annot);
+      return;
+    }
+  }
+
+  // Check for RLWINM mnemonics.
+  if (MI->getOpcode() == PPC::RLWINM || MI->getOpcode() == PPC::RLWINM_rec ||
+      MI->getOpcode() == PPC::RLWINM8 || MI->getOpcode() == PPC::RLWINM8_rec) {
     unsigned char SH = MI->getOperand(2).getImm();
     unsigned char MB = MI->getOperand(3).getImm();
     unsigned char ME = MI->getOperand(4).getImm();
-    bool useSubstituteMnemonic = false;
-    if (SH <= 31 && MB == 0 && ME == (31-SH)) {
-      O << "\tslwi "; useSubstituteMnemonic = true;
+    int Op2 = -1, Op3 = -1;
+
+    if (SH < 32 && MB == 0 && ME == (31 - SH)) {
+      // Check for slwi
+      if (MI->getOpcode() == PPC::RLWINM || MI->getOpcode() == PPC::RLWINM8)
+        O << "\tslwi ";
+      else
+        O << "\tslwi. ";
+      Op2 = SH;
+    } else if (SH && SH < 32 && MB == (32 - SH) && ME == 31) {
+      // Check for srwi
+      if (MI->getOpcode() == PPC::RLWINM || MI->getOpcode() == PPC::RLWINM8)
+        O << "\tsrwi ";
+      else
+        O << "\tsrwi. ";
+      Op2 = 32 - SH;
+    } else if (SH == 0 && MB == 0 && ME < 32) {
+      // Check for clrrwi
+      if (MI->getOpcode() == PPC::RLWINM || MI->getOpcode() == PPC::RLWINM8)
+        O << "\tclrrwi ";
+      else
+        O << "\tclrrwi. ";
+      Op2 = 31 - ME;
+    } else if (SH && SH < 32 && (SH + ME) == 31 && (SH + MB) < 32) {
+      // Check for clrlslwi
+      if (MI->getOpcode() == PPC::RLWINM || MI->getOpcode() == PPC::RLWINM8)
+        O << "\tclrlslwi ";
+      else
+        O << "\tclrlslwi. ";
+      Op2 = SH + MB;
+      Op3 = SH;
+    } else if (SH < 32 && MB == 0 && ME < 31) {
+      // Check for extlwi
+      if (MI->getOpcode() == PPC::RLWINM || MI->getOpcode() == PPC::RLWINM8)
+        O << "\textlwi ";
+      else
+        O << "\textlwi. ";
+      Op2 = ME + 1;
+      Op3 = SH;
+    } else if (SH < 32 && MB < 32 && ME == 31 && (SH + MB) > 33) {
+      // Check for extrwi
+      if (MI->getOpcode() == PPC::RLWINM || MI->getOpcode() == PPC::RLWINM8)
+        O << "\textrwi ";
+      else
+        O << "\textrwi. ";
+      Op2 = 32 - MB;
+      Op3 = SH + MB - 32;
     }
-    if (SH <= 31 && MB == (32-SH) && ME == 31) {
-      O << "\tsrwi "; useSubstituteMnemonic = true;
-      SH = 32-SH;
+
+    if (Op2 > -1) {
+      printOperand(MI, 0, O);
+      O << ", ";
+      printOperand(MI, 1, O);
+      O << ", " << (unsigned int)Op2;
+      if (Op3 > -1)
+        O << ", " << (unsigned int)Op3;
+
+      printAnnotation(O, Annot);
+      return;
     }
-    if (useSubstituteMnemonic) {
+  }
+
+  // Check for RLDIC mnemonics.
+  if (MI->getOpcode() == PPC::RLDIC || MI->getOpcode() == PPC::RLDIC_rec) {
+    unsigned char SH = MI->getOperand(2).getImm();
+    unsigned char MB = MI->getOperand(3).getImm();
+    if (SH + MB < 64) {
+      // Check for clrlsldi
+      if (MI->getOpcode() == PPC::RLDIC)
+        O << "\tclrlsldi ";
+      else
+        O << "\tclrlsldi. ";
+
       printOperand(MI, 0, O);
       O << ", ";
       printOperand(MI, 1, O);
+      O << ", " << (unsigned int)(SH + MB);
       O << ", " << (unsigned int)SH;
+      printAnnotation(O, Annot);
+      return;
+    }
+  }
 
+  // Check for RLDICL mnemonics.
+  if (MI->getOpcode() == PPC::RLDICL ||
+      MI->getOpcode() == PPC::RLDICL_rec ||
+      MI->getOpcode() == PPC::RLDICL_32 ||
+      MI->getOpcode() == PPC::RLDICL_32_rec ||
+      MI->getOpcode() == PPC::RLDICL_32_64) {
+    unsigned char SH = MI->getOperand(2).getImm();
+    unsigned char MB = MI->getOperand(3).getImm();
+    int Op2 = -1, Op3 = -1;
+
+    if (SH && SH < 64 && SH == (64 - MB)) {
+      // Check for srdi
+      if (MI->getOpcode() == PPC::RLDICL ||
+          MI->getOpcode() == PPC::RLDICL_32 ||
+          MI->getOpcode() == PPC::RLDICL_32_64)
+        O << "\tsrdi ";
+      else
+        O << "\tsrdi. ";
+      Op2 = 64 - SH;
+    } else if (SH && SH < 64 &&  (SH + MB) > 63 && MB < 64) {
+      // Check for extrdi
+      if (MI->getOpcode() == PPC::RLDICL ||
+          MI->getOpcode() == PPC::RLDICL_32 ||
+          MI->getOpcode() == PPC::RLDICL_32_64)
+        O << "\textrdi ";
+      else
+        O << "\textrdi. ";
+      Op2 = 64 - MB;
+      Op3 = SH + MB - 64;
+    }
+
+    if (Op2 > -1) {
+      printOperand(MI, 0, O);
+      O << ", ";
+      printOperand(MI, 1, O);
+      O << ", " << (unsigned int)Op2;
+
+      if (Op3 > -1)
+        O << ", " << (unsigned int)Op3;
       printAnnotation(O, Annot);
       return;
     }
   }
 
+  // Check for RLDICR mnemonics.
   if (MI->getOpcode() == PPC::RLDICR ||
-      MI->getOpcode() == PPC::RLDICR_32) {
+      MI->getOpcode() == PPC::RLDICR_32 ||
+      MI->getOpcode() == PPC::RLDICR_rec) {
     unsigned char SH = MI->getOperand(2).getImm();
     unsigned char ME = MI->getOperand(3).getImm();
-    // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
-    if (63-SH == ME) {
-      O << "\tsldi ";
+    int Op2 = -1, Op3 = -1;
+
+    if (63 - SH == ME) {
+      // Check for sldi
+      if (MI->getOpcode() == PPC::RLDICR || MI->getOpcode() == PPC::RLDICR_32)
+        O << "\tsldi ";
+      else
+        O << "\tsldi. ";
+      Op2 = SH;
+    } else if (SH == 0 && ME < 64) {
+      // Check for clrrdi
+      if (MI->getOpcode() == PPC::RLDICR || MI->getOpcode() == PPC::RLDICR_32)
+        O << "\tclrrdi ";
+      else
+        O << "\tclrrdi. ";
+      Op2 = 63 - ME;
+    } else if (SH < 64 && ME < 63) {
+      // Check for extldi
+      if (MI->getOpcode() == PPC::RLDICR || MI->getOpcode() == PPC::RLDICR_32)
+        O << "\textldi ";
+      else
+        O << "\textldi. ";
+      Op2 = ME + 1;
+      Op3 = SH;
+    }
+
+    if (Op2 > -1) {
       printOperand(MI, 0, O);
       O << ", ";
       printOperand(MI, 1, O);
-      O << ", " << (unsigned int)SH;
+      O << ", " << (unsigned int)Op2;
+
+      if (Op3 > -1)
+        O << ", " << (unsigned int)Op3;
       printAnnotation(O, Annot);
       return;
     }
diff --git a/llvm/test/CodeGen/PowerPC/2006-11-10-DAGCombineMiscompile.ll b/llvm/test/CodeGen/PowerPC/2006-11-10-DAGCombineMiscompile.ll
--- a/llvm/test/CodeGen/PowerPC/2006-11-10-DAGCombineMiscompile.ll
+++ b/llvm/test/CodeGen/PowerPC/2006-11-10-DAGCombineMiscompile.ll
@@ -1,4 +1,4 @@
-; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | grep rlwimi
+; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | grep insrwi
 
 define void @test(i16 %div.0.i.i.i.i, i32 %L_num.0.i.i.i.i, i32 %tmp1.i.i206.i.i, i16* %P) {
         %X = shl i16 %div.0.i.i.i.i, 1          ; <i16> [#uses=1]
diff --git a/llvm/test/CodeGen/PowerPC/CompareEliminationSpillIssue.ll b/llvm/test/CodeGen/PowerPC/CompareEliminationSpillIssue.ll
--- a/llvm/test/CodeGen/PowerPC/CompareEliminationSpillIssue.ll
+++ b/llvm/test/CodeGen/PowerPC/CompareEliminationSpillIssue.ll
@@ -36,7 +36,7 @@
 ; CHECK: extsw r3,
 ; CHECK: bl call
 ; CHECK: sub r3,
-; CHECK: rldicl r3, r3, 1, 63
+; CHECK: srdi r3, r3, 63
 ; CHECK: std r3, [[OFF:[0-9]+]](r1)
 ; CHECK: #APP
 ; CHECK: ld r3, [[OFF]](r1)
diff --git a/llvm/test/CodeGen/PowerPC/Frames-dyn-alloca.ll b/llvm/test/CodeGen/PowerPC/Frames-dyn-alloca.ll
--- a/llvm/test/CodeGen/PowerPC/Frames-dyn-alloca.ll
+++ b/llvm/test/CodeGen/PowerPC/Frames-dyn-alloca.ll
@@ -29,7 +29,7 @@
 ; PPC32-LINUX-NEXT: addi 3, 3, 15
 ; PPC32-LINUX-NEXT: stw 31, 28(1)
 ; PPC32-LINUX-NEXT: mr 31, 1
-; PPC32-LINUX-NEXT: rlwinm 3, 3, 0, 0, 27
+; PPC32-LINUX-NEXT: clrrwi 3, 3, 4
 ; PPC32-LINUX-NEXT: neg 3, 3
 ; PPC32-LINUX-NEXT: addi 4, 31, 32
 ; PPC32-LINUX-NEXT: stwux 4, 1, 3
@@ -43,10 +43,10 @@
 ; PPC64-LINUX-LABEL: f1
 ; PPC64-LINUX:      std 31, -8(1)
 ; PPC64-LINUX-NEXT: stdu 1, -64(1)
-; PPC64-LINUX-NEXT: rldic 3, 3, 2, 30
+; PPC64-LINUX-NEXT: clrlsldi 3, 3, 32, 2
 ; PPC64-LINUX-NEXT: mr 31, 1
 ; PPC64-LINUX-NEXT: addi 3, 3, 15
-; PPC64-LINUX-NEXT: rldicl 3, 3, 60, 4
+; PPC64-LINUX-NEXT: srdi 3, 3, 4
 ; PPC64-LINUX-NEXT: addi 4, 31, 64
 ; PPC64-LINUX-NEXT: rldicl 3, 3, 4, 29
 ; PPC64-LINUX-NEXT: neg 3, 3
@@ -66,7 +66,7 @@
 ; PPC32-AIX-NEXT: mr 31, 1
 ; PPC32-AIX-NEXT: addi 3, 3, 15
 ; PPC32-AIX-NEXT: addi 4, 31, 48
-; PPC32-AIX-NEXT: rlwinm 3, 3, 0, 0, 27
+; PPC32-AIX-NEXT: clrrwi 3, 3, 4
 ; PPC32-AIX-NEXT: neg 3, 3
 ; PPC32-AIX-NEXT: stwux 4, 1, 3
 
@@ -80,11 +80,11 @@
 ; PPC64-AIX-LABEL: f1
 ; PPC64-AIX:      std 31, -8(1)
 ; PPC64-AIX-NEXT: stdu 1, -64(1)
-; PPC64-AIX-NEXT: rldic 3, 3, 2, 30
+; PPC64-AIX-NEXT: clrlsldi 3, 3, 32, 2
 ; PPC64-AIX-NEXT: mr 31, 1
 ; PPC64-AIX-NEXT: addi 3, 3, 15
 ; PPC64-AIX-NEXT: addi 4, 31, 64
-; PPC64-AIX-NEXT: rldicl 3, 3, 60, 4 
+; PPC64-AIX-NEXT: srdi 3, 3, 4
 ; PPC64-AIX-NEXT: rldicl 3, 3, 4, 29
 ; PPC64-AIX-NEXT: neg 3, 3
 ; PPC64-AIX-NEXT: stdux 4, 1, 3
diff --git a/llvm/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll b/llvm/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll
--- a/llvm/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll
+++ b/llvm/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll
@@ -83,7 +83,7 @@
 ; CHECK-P7-NEXT:    slw 6, 6, 3
 ; CHECK-P7-NEXT:    slw 8, 5, 3
 ; CHECK-P7-NEXT:    slw 5, 7, 3
-; CHECK-P7-NEXT:    rldicr 4, 4, 0, 61
+; CHECK-P7-NEXT:    clrrdi 4, 4, 2
 ; CHECK-P7-NEXT:    and 7, 6, 5
 ; CHECK-P7-NEXT:    and 8, 8, 5
 ; CHECK-P7-NEXT:  .LBB0_1: # %L.entry
diff --git a/llvm/test/CodeGen/PowerPC/absol-jump-table-enabled.ll b/llvm/test/CodeGen/PowerPC/absol-jump-table-enabled.ll
--- a/llvm/test/CodeGen/PowerPC/absol-jump-table-enabled.ll
+++ b/llvm/test/CodeGen/PowerPC/absol-jump-table-enabled.ll
@@ -14,7 +14,7 @@
 define zeroext i32 @jumpTableTest(%struct.node* readonly %list) {
 ; CHECK-LE-LABEL: jumpTableTest:
 ; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE:       rldic r[[REG:[0-9]+]], r[[REG]], 3, 29
+; CHECK-LE:       clrlsldi r[[REG:[0-9]+]], r[[REG]], 32, 3
 ; CHECK-LE:       ldx r[[REG]], r[[REG]], r[[REG1:[0-9]+]]
 ; CHECK-LE:       mtctr r[[REG]]
 ; CHECK-LE:       bctr
@@ -22,7 +22,7 @@
 ;
 ; CHECK-BE-LABEL: jumpTableTest:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE:       rldic r[[REG:[0-9]+]], r[[REG]], 2, 30
+; CHECK-BE:       clrlsldi r[[REG:[0-9]+]], r[[REG]], 32, 2
 ; CHECK-BE:       lwax r[[REG]], r[[REG]], r[[REG1:[0-9]+]]
 ; CHECK-BE:       mtctr r[[REG]]
 ; CHECK-BE:       bctr
diff --git a/llvm/test/CodeGen/PowerPC/addegluecrash.ll b/llvm/test/CodeGen/PowerPC/addegluecrash.ll
--- a/llvm/test/CodeGen/PowerPC/addegluecrash.ll
+++ b/llvm/test/CodeGen/PowerPC/addegluecrash.ll
@@ -22,7 +22,7 @@
 ; CHECK-NEXT:    add 4, 5, 4
 ; CHECK-NEXT:    cmpld 7, 4, 5
 ; CHECK-NEXT:    mfocrf 4, 1
-; CHECK-NEXT:    rlwinm 4, 4, 29, 31, 31
+; CHECK-NEXT:    extrwi 4, 4, 1, 28
 ; CHECK-NEXT:    # implicit-def: $x5
 ; CHECK-NEXT:    mr 5, 4
 ; CHECK-NEXT:    clrldi 4, 5, 32
diff --git a/llvm/test/CodeGen/PowerPC/addi-offset-fold.ll b/llvm/test/CodeGen/PowerPC/addi-offset-fold.ll
--- a/llvm/test/CodeGen/PowerPC/addi-offset-fold.ll
+++ b/llvm/test/CodeGen/PowerPC/addi-offset-fold.ll
@@ -28,8 +28,8 @@
 ; CHECK-DAG: std 3, -24(1)
 ; CHECK-DAG: stb 4, -16(1)
 ; CHECK-DAG: lwz [[REG2:[0-9]+]], -20(1)
-; CHECK-DAG: rlwinm 3, [[REG2]], 1, 31, 31
-; CHECK: rlwimi 3, 4, 1, 25, 30
+; CHECK-DAG: srwi 3, [[REG2]], 31
+; CHECK: insrwi 3, 4, 6, 25
 ; CHECK: blr
 }
 
diff --git a/llvm/test/CodeGen/PowerPC/addze.ll b/llvm/test/CodeGen/PowerPC/addze.ll
--- a/llvm/test/CodeGen/PowerPC/addze.ll
+++ b/llvm/test/CodeGen/PowerPC/addze.ll
@@ -101,7 +101,7 @@
 ; CHECK-NEXT: li     [[REG1:r[0-9]+]], -32768
 ; CHECK-NEXT: xor    [[REG2:r[0-9]+]], [[REG2]], [[REG1]]
 ; CHECK-NEXT: cntlzd [[REG2]], [[REG2]]
-; CHECK-NEXT: rldicl [[REG2]], [[REG2]], 58, 63
+; CHECK-NEXT: extrdi [[REG2]], [[REG2]], 1, 57
 ; CHECK-NEXT: add    [[REG3:r[0-9]+]], [[REG2]], [[REG3]]
 ; CHECK-NEXT: blr
   %cmp = icmp eq i64 %Z, -32768
@@ -133,7 +133,7 @@
 ; CHECK-NEXT: ori    [[REG1]], [[REG1]], 32769
 ; CHECK-NEXT: xor    [[REG2:r[0-9]+]], [[REG2]], [[REG1]]
 ; CHECK-NEXT: cntlzd [[REG2]], [[REG2]]
-; CHECK-NEXT: rldicl [[REG2]], [[REG2]], 58, 63
+; CHECK-NEXT: extrdi [[REG2]], [[REG2]], 1, 57
 ; CHECK-NEXT: add    [[REG3:r[0-9]+]], [[REG2]], [[REG3]]
 ; CHECK-NEXT: blr
   %cmp = icmp eq i64 %Z, 32769
@@ -162,7 +162,7 @@
 ; CHECK: # %bb.0:
 ; CHECK-NEXT: xor    [[REG2:r[0-9]+]], [[REG2]], [[REG1:r[0-9]+]]
 ; CHECK-NEXT: cntlzd [[REG2]], [[REG2]]
-; CHECK-NEXT: rldicl [[REG2]], [[REG2]], 58, 63
+; CHECK-NEXT: extrdi [[REG2]], [[REG2]], 1, 57
 ; CHECK-NEXT: add    [[REG3:r[0-9]+]], [[REG2]], [[REG3]]
 ; CHECK-NEXT: blr
   %cmp = icmp eq i64 %Y, %Z
diff --git a/llvm/test/CodeGen/PowerPC/aix-cc-byval-mem.ll b/llvm/test/CodeGen/PowerPC/aix-cc-byval-mem.ll
--- a/llvm/test/CodeGen/PowerPC/aix-cc-byval-mem.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-cc-byval-mem.ll
@@ -376,9 +376,9 @@
 ; ASM64BIT-DAG:   lwz [[REG3:[0-9]+]], 24([[REG2]])
 ; ASM64BIT-DAG:   lhz [[REG4:[0-9]+]], 28([[REG2]])
 ; ASM64BIT-DAG:   lbz 7, 30([[REG2]])
-; ASM64BIT-DAG:   rlwinm 7, 7, 8, 16, 23
-; ASM64BIT-DAG:   rlwimi 7, [[REG4]], 16, 0, 15
-; ASM64BIT-DAG:   rldimi 7, [[REG3]], 32, 0
+; ASM64BIT-DAG:   clrlslwi 7, 7, 24, 8
+; ASM64BIT-DAG:   insrwi 7, [[REG4]], 16, 0
+; ASM64BIT-DAG:   insrdi 7, [[REG3]], 32, 0
 ; ASM64BIT-DAG:   ld 8, 0([[REG1]])
 ; ASM64BIT-DAG:   ld 9, 8([[REG1]])
 ; ASM64BIT-DAG:   ld 10, 16([[REG1]])
diff --git a/llvm/test/CodeGen/PowerPC/aix-cc-byval.ll b/llvm/test/CodeGen/PowerPC/aix-cc-byval.ll
--- a/llvm/test/CodeGen/PowerPC/aix-cc-byval.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-cc-byval.ll
@@ -257,8 +257,8 @@
 ; ASM32-DAG:   lwz [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM32-DAG:   lhz [[REG1:[0-9]+]], 0([[REGADDR]])
 ; ASM32-DAG:   lbz [[REG2:[0-9]+]], 2([[REGADDR]])
-; ASM32-DAG:   rlwinm 10, [[REG2]], 8, 16, 23
-; ASM32-DAG:   rlwimi 10, [[REG1]], 16, 0, 15
+; ASM32-DAG:   clrlslwi 10, [[REG2]], 24, 8
+; ASM32-DAG:   insrwi 10, [[REG1]], 16, 0
 ; ASM32-DAG:   li [[REG3:[0-9]+]], 42
 ; ASM32-DAG:   stw [[REG3]], 56(1)
 ; ASM32-NEXT:  bl .test_byval_3Byte
@@ -295,8 +295,8 @@
 ; ASM64-DAG:   ld [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM64-DAG:   lhz [[REG1:[0-9]+]], 0([[REGADDR]])
 ; ASM64-DAG:   lbz [[REG2:[0-9]+]], 2([[REGADDR]])
-; ASM64-DAG:   rldic 10, [[REG2]], 40, 16
-; ASM64-DAG:   rldimi 10, [[REG1]], 48, 0
+; ASM64-DAG:   clrlsldi 10, 3, 56, 40
+; ASM64-DAG:   insrdi 10, [[REG1]], 16, 0
 ; ASM64-DAG:   li [[REG3:[0-9]+]], 42
 ; ASM64-DAG:   std [[REG3]], 112(1)
 ; ASM64-NEXT:  bl .test_byval_3Byte
@@ -508,8 +508,8 @@
 ; ASM64-NEXT:  ld [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM64-DAG:   lwz [[REG1:[0-9]+]], 0([[REGADDR]])
 ; ASM64-DAG:   lbz [[REG2:[0-9]+]], 4([[REGADDR]])
-; ASM64-DAG:   rlwinm 3, [[REG2]], 24, 0, 7
-; ASM64-DAG:   rldimi 3, [[REG1]], 32, 0
+; ASM64-DAG:   slwi 3, [[REG2]], 24
+; ASM64-DAG:   insrdi 3, [[REG1]], 32, 0
 ; ASM64-NEXT:  bl .test_byval_5Byte
 ; ASM64-NEXT:  nop
 
@@ -563,8 +563,8 @@
 ; ASM64-NEXT:  ld [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM64-DAG:   lwz [[REG1:[0-9]+]], 0([[REGADDR]])
 ; ASM64-DAG:   lhz [[REG2:[0-9]+]], 4([[REGADDR]])
-; ASM64-DAG:   rlwinm 3, [[REG2]], 16, 0, 15
-; ASM64-DAG:   rldimi 3, [[REG1]], 32, 0
+; ASM64-DAG:   slwi 3, [[REG2]], 16
+; ASM64-DAG:   insrdi 3, [[REG1]], 32, 0
 ; ASM64-NEXT:  bl .test_byval_6Byte
 ; ASM64-NEXT:  nop
 
@@ -602,8 +602,8 @@
 ; ASM32-DAG:   lwz 3, 0([[REGADDR]])
 ; ASM32-DAG:   lhz [[REG1:[0-9]+]], 4([[REGADDR]])
 ; ASM32-DAG:   lbz [[REG2:[0-9]+]], 6([[REGADDR]])
-; ASM32-DAG:   rlwinm 4, [[REG2]], 8, 16, 23
-; ASM32-DAG:   rlwimi 4, [[REG1]], 16, 0, 15
+; ASM32-DAG:   clrlslwi 4, [[REG2]], 24, 8
+; ASM32-DAG:   insrwi 4, [[REG1]], 16, 0
 ; ASM32-NEXT:  bl .test_byval_7Byte
 ; ASM32-NEXT:  nop
 
@@ -625,9 +625,9 @@
 ; ASM64-DAG:   lwz [[REG1:[0-9]+]], 0([[REGADDR]])
 ; ASM64-DAG:   lhz [[REG2:[0-9]+]], 4([[REGADDR]])
 ; ASM64-DAG:   lbz [[REG3:[0-9]+]], 6([[REGADDR]])
-; ASM64-DAG:   rlwinm 3, [[REG3]], 8, 16, 23
-; ASM64-DAG:   rlwimi 3, [[REG2]], 16, 0, 15
-; ASM64-DAG:   rldimi 3, [[REG1]], 32, 0
+; ASM64-DAG:   clrlslwi 3, [[REG3]], 24, 8
+; ASM64-DAG:   insrwi 3, [[REG2]], 16, 0
+; ASM64-DAG:   insrdi 3, [[REG1]], 32, 0
 ; ASM64-NEXT:  bl .test_byval_7Byte
 ; ASM64-NEXT:  nop
 
@@ -844,8 +844,8 @@
 ; ASM32-DAG:   lwz 9, 24([[REGADDR]])
 ; ASM32-DAG:   lbz 10, 30([[REGADDR]])
 ; ASM32-DAG:   lhz [[REG:[0-9]+]], 28([[REGADDR]])
-; ASM32-DAG:   rlwinm 10, 10, 8, 16, 23
-; ASM32-DAG:   rlwimi 10, [[REG]], 16, 0, 15
+; ASM32-DAG:   clrlslwi 10, 10, 24, 8
+; ASM32-DAG:   insrwi 10, [[REG]], 16, 0
 ; ASM32-NEXT:  bl .test_byval_31Byte
 ; ASM32-NEXT:  nop
 
@@ -872,9 +872,9 @@
 ; ASM64-DAG:   lwz [[REG1:[0-9]+]], 24([[REGADDR]])
 ; ASM64-DAG:   lhz [[REG2:[0-9]+]], 28([[REGADDR]])
 ; ASM64-DAG:   lbz [[REG3:[0-9]+]], 30([[REGADDR]])
-; ASM64-DAG:   rlwinm 6, [[REG3]], 8, 16, 23
-; ASM64-DAG:   rlwimi 6, [[REG2]], 16, 0, 15
-; ASM64-DAG:   rldimi 6, [[REG1]], 32, 0
+; ASM64-DAG:   clrlslwi 6, [[REG3]], 24, 8
+; ASM64-DAG:   insrwi 6, [[REG2]], 16, 0
+; ASM64-DAG:   insrdi 6, [[REG1]], 32, 0
 ; ASM64-NEXT:  bl .test_byval_31Byte
 ; ASM64-NEXT:  nop
 
diff --git a/llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll b/llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll
--- a/llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll
@@ -137,7 +137,7 @@
 ; 64SMALL-ASM:      cmplwi  3, 3
 ; 64SMALL-ASM:      bgt     0, L..BB0_6
 ; 64SMALL-ASM:      ld 4, L..C0(2)
-; 64SMALL-ASM:      rldic 3, 3, 2, 30
+; 64SMALL-ASM:      clrlsldi 3, 3, 32, 2
 ; 64SMALL-ASM:      lwax 3, 3, 4
 ; 64SMALL-ASM:      add 3, 3, 4
 ; 64SMALL-ASM:      mtctr 3
@@ -163,7 +163,7 @@
 ; 64LARGE-ASM:      cmplwi  3, 3
 ; 64LARGE-ASM:      bgt     0, L..BB0_6
 ; 64LARGE-ASM:      addis 4, L..C0@u(2)
-; 64LARGE-ASM:      rldic 3, 3, 2, 30
+; 64LARGE-ASM:      clrlsldi 3, 3, 32, 2
 ; 64LARGE-ASM:      ld 4, L..C0@l(4)
 ; 64LARGE-ASM:      lwax 3, 3, 4
 ; 64LARGE-ASM:      add 3, 3, 4
diff --git a/llvm/test/CodeGen/PowerPC/and-mask.ll b/llvm/test/CodeGen/PowerPC/and-mask.ll
--- a/llvm/test/CodeGen/PowerPC/and-mask.ll
+++ b/llvm/test/CodeGen/PowerPC/and-mask.ll
@@ -5,7 +5,7 @@
 define i32 @test1(i32 %a) {
 ; CHECK-LABEL: test1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    rlwinm 3, 3, 0, 0, 30
+; CHECK-NEXT:    clrrwi 3, 3, 1
 ; CHECK-NEXT:    blr
   %and = and i32 %a, -2
   ret i32 %and
@@ -26,7 +26,7 @@
 define i64 @test3(i64 %a) {
 ; CHECK-LABEL: test3:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    rldicl 3, 3, 42, 22
+; CHECK-NEXT:    srdi 3, 3, 22
 ; CHECK-NEXT:    rldicl 3, 3, 22, 16
 ; CHECK-NEXT:    blr
   %and = and i64 %a, 281474972516352
diff --git a/llvm/test/CodeGen/PowerPC/andc.ll b/llvm/test/CodeGen/PowerPC/andc.ll
--- a/llvm/test/CodeGen/PowerPC/andc.ll
+++ b/llvm/test/CodeGen/PowerPC/andc.ll
@@ -6,7 +6,7 @@
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    andc 3, 4, 3
 ; CHECK-NEXT:    cntlzw 3, 3
-; CHECK-NEXT:    rlwinm 3, 3, 27, 31, 31
+; CHECK-NEXT:    extrwi 3, 3, 1, 26
 ; CHECK-NEXT:    blr
   %and = and i32 %x, %y
   %cmp = icmp eq i32 %and, %y
@@ -19,7 +19,7 @@
 ; CHECK-NEXT:    li 4, 43
 ; CHECK-NEXT:    andc 3, 4, 3
 ; CHECK-NEXT:    cntlzw 3, 3
-; CHECK-NEXT:    rlwinm 3, 3, 27, 31, 31
+; CHECK-NEXT:    extrwi 3, 3, 1, 26
 ; CHECK-NEXT:    blr
   %and = and i32 %x, 43
   %cmp = icmp eq i32 %and, 43
@@ -33,7 +33,7 @@
 ; CHECK-NEXT:    ori 4, 4, 22136
 ; CHECK-NEXT:    andc 3, 4, 3
 ; CHECK-NEXT:    cntlzw 3, 3
-; CHECK-NEXT:    rlwinm 3, 3, 27, 31, 31
+; CHECK-NEXT:    extrwi 3, 3, 1, 26
 ; CHECK-NEXT:    blr
   %and = and i32 %i, 305419896
   %cmp = icmp eq i32 %and, 305419896
diff --git a/llvm/test/CodeGen/PowerPC/anyext_srl.ll b/llvm/test/CodeGen/PowerPC/anyext_srl.ll
--- a/llvm/test/CodeGen/PowerPC/anyext_srl.ll
+++ b/llvm/test/CodeGen/PowerPC/anyext_srl.ll
@@ -18,7 +18,7 @@
   %cmp = xor i1 %cmp.i, %cmp.i5
   ret i1 %cmp
 ; CHECK-LABEL: @foo
-; CHECK: rldicl  {{[0-9]+}}, {{[0-9]+}}, 61, 63
+; CHECK: extrdi  {{[0-9]+}}, {{[0-9]+}}, 1, 60
 
 }
 
diff --git a/llvm/test/CodeGen/PowerPC/atomic-minmax.ll b/llvm/test/CodeGen/PowerPC/atomic-minmax.ll
--- a/llvm/test/CodeGen/PowerPC/atomic-minmax.ll
+++ b/llvm/test/CodeGen/PowerPC/atomic-minmax.ll
@@ -234,7 +234,7 @@
 ; CHECK-LABEL: @ae16min
 ; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 27
 ; CHECK-DAG: li [[M1:[0-9]+]], 0
-; CHECK-DAG: rldicr 3, 3, 0, 61
+; CHECK-DAG: clrrdi 3, 3, 2
 ; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 16
 ; CHECK-DAG: ori [[M2:[0-9]+]], [[M1]], 65535
 ; CHECK-DAG: slw [[SV:[0-9]+]], 4, [[SA]]
@@ -261,7 +261,7 @@
 ; CHECK-LABEL: @ae16max
 ; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 27
 ; CHECK-DAG: li [[M1:[0-9]+]], 0
-; CHECK-DAG: rldicr 3, 3, 0, 61
+; CHECK-DAG: clrrdi 3, 3, 2
 ; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 16
 ; CHECK-DAG: ori [[M2:[0-9]+]], [[M1]], 65535
 ; CHECK-DAG: slw [[SV:[0-9]+]], 4, [[SA]]
@@ -288,7 +288,7 @@
 ; CHECK-LABEL: @ae16umin
 ; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 27
 ; CHECK-DAG: li [[M1:[0-9]+]], 0
-; CHECK-DAG: rldicr 3, 3, 0, 61
+; CHECK-DAG: clrrdi 3, 3, 2
 ; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 16
 ; CHECK-DAG: ori [[M2:[0-9]+]], [[M1]], 65535
 ; CHECK-DAG: slw [[SV:[0-9]+]], 4, [[SA]]
@@ -313,7 +313,7 @@
 ; CHECK-LABEL: @ae16umax
 ; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 27
 ; CHECK-DAG: li [[M1:[0-9]+]], 0
-; CHECK-DAG: rldicr 3, 3, 0, 61
+; CHECK-DAG: clrrdi 3, 3, 2
 ; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 16
 ; CHECK-DAG: ori [[M2:[0-9]+]], [[M1]], 65535
 ; CHECK-DAG: slw [[SV:[0-9]+]], 4, [[SA]]
@@ -336,9 +336,9 @@
   ret void
 
 ; CHECK-LABEL: @ae8min
-; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 28
+; CHECK-DAG: clrlslwi [[SA1:[0-9]+]], 3, 30, 3
 ; CHECK-DAG: li [[M1:[0-9]+]], 255
-; CHECK-DAG: rldicr 3, 3, 0, 61
+; CHECK-DAG: clrrdi 3, 3, 2
 ; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 24
 ; CHECK-DAG: slw [[SV:[0-9]+]], 4, [[SA]]
 ; CHECK-DAG: slw [[M:[0-9]+]], [[M1]], [[SA]]
@@ -362,9 +362,9 @@
   ret void
 
 ; CHECK-LABEL: @ae8max
-; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 28
+; CHECK-DAG: clrlslwi [[SA1:[0-9]+]], 3, 30, 3
 ; CHECK-DAG: li [[M1:[0-9]+]], 255
-; CHECK-DAG: rldicr 3, 3, 0, 61
+; CHECK-DAG: clrrdi 3, 3, 2
 ; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 24
 ; CHECK-DAG: slw [[SV:[0-9]+]], 4, [[SA]]
 ; CHECK-DAG: slw [[M:[0-9]+]], [[M1]], [[SA]]
@@ -388,9 +388,9 @@
   ret void
 
 ; CHECK-LABEL: @ae8umin
-; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 28
+; CHECK-DAG: clrlslwi [[SA1:[0-9]+]], 3, 30, 3
 ; CHECK-DAG: li [[M1:[0-9]+]], 255
-; CHECK-DAG: rldicr 3, 3, 0, 61
+; CHECK-DAG: clrrdi 3, 3, 2
 ; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 24
 ; CHECK-DAG: slw [[SV:[0-9]+]], 4, [[SA]]
 ; CHECK-DAG: slw [[M:[0-9]+]], [[M1]], [[SA]]
@@ -412,9 +412,9 @@
   ret void
 
 ; CHECK-LABEL: @ae8umax
-; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 28
+; CHECK-DAG: clrlslwi [[SA1:[0-9]+]], 3, 30, 3
 ; CHECK-DAG: li [[M1:[0-9]+]], 255
-; CHECK-DAG: rldicr 3, 3, 0, 61
+; CHECK-DAG: clrrdi 3, 3, 2
 ; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 24
 ; CHECK-DAG: slw [[SV:[0-9]+]], 4, [[SA]]
 ; CHECK-DAG: slw [[M:[0-9]+]], [[M1]], [[SA]]
diff --git a/llvm/test/CodeGen/PowerPC/bitfieldinsert.ll b/llvm/test/CodeGen/PowerPC/bitfieldinsert.ll
--- a/llvm/test/CodeGen/PowerPC/bitfieldinsert.ll
+++ b/llvm/test/CodeGen/PowerPC/bitfieldinsert.ll
@@ -16,7 +16,7 @@
 define void @bitfieldinsert64(%struct.s64* nocapture %p, i16 zeroext %v) {
 ; CHECK-LABEL: @bitfieldinsert64
 ; CHECK: ld [[REG1:[0-9]+]], 0(3)
-; CHECK-NEXT: rlwimi [[REG1]], 4, 5, 11, 26
+; CHECK-NEXT: insrwi [[REG1]], 4, 16, 11
 ; CHECK-NEXT: std [[REG1]], 0(3)
 ; CHECK-NEXT: blr
 entry:
@@ -46,7 +46,7 @@
 define void @bitfieldinsert32(%struct.s32* nocapture %p, i32 zeroext %v) {
 ; CHECK-LABEL: @bitfieldinsert32
 ; CHECK: lwz [[REG1:[0-9]+]], 0(3)
-; CHECK-NEXT: rlwimi [[REG1]], 4, 8, 8, 23
+; CHECK-NEXT: insrwi [[REG1]], 4, 16, 8
 ; CHECK-NEXT: stw [[REG1]], 0(3)
 ; CHECK-NEXT: blr
 entry:
@@ -76,7 +76,7 @@
 define void @bitfieldinsert64b(%struct.s64b* nocapture %p, i8 zeroext %v) {
 ; CHECK-LABEL: @bitfieldinsert64b
 ; CHECK: lwz [[REG1:[0-9]+]], 0(3)
-; CHECK-NEXT: rlwimi [[REG1]], 4, 4, 12, 27
+; CHECK-NEXT: insrwi [[REG1]], 4, 16, 12
 ; CHECK-NEXT: stw [[REG1]], 0(3)
 ; CHECK-NEXT: blr
 entry:
@@ -105,7 +105,7 @@
 define void @bitfieldinsert64c(%struct.s64c* nocapture %p, i16 zeroext %v) {
 ; CHECK-LABEL: @bitfieldinsert64c
 ; CHECK: lwz [[REG1:[0-9]+]], 0(3)
-; CHECK-NEXT: rlwimi [[REG1]], 4, 5, 11, 26
+; CHECK-NEXT: insrwi [[REG1]], 4, 16, 11
 ; CHECK-NEXT: stw [[REG1]], 0(3)
 ; CHECK-NEXT: blr
 entry:
diff --git a/llvm/test/CodeGen/PowerPC/bperm.ll b/llvm/test/CodeGen/PowerPC/bperm.ll
--- a/llvm/test/CodeGen/PowerPC/bperm.ll
+++ b/llvm/test/CodeGen/PowerPC/bperm.ll
@@ -11,7 +11,7 @@
 ; CHECK-LABEL: @bs4
 ; CHECK: rotlwi [[REG1:[0-9]+]], 3, 8
 ; CHECK: rlwimi [[REG1]], 3, 24, 16, 23
-; CHECK: rlwimi [[REG1]], 3, 24, 0, 7
+; CHECK: insrwi [[REG1]], 3, 8, 0
 ; CHECK: mr 3, [[REG1]]
 ; CHECK: blr
 }
@@ -25,15 +25,15 @@
 ; CHECK-DAG: rotldi [[REG1:[0-9]+]], 3, 16
 ; CHECK-DAG: rotldi [[REG2:[0-9]+]], 3, 8
 ; CHECK-DAG: rotldi [[REG3:[0-9]+]], 3, 24
-; CHECK-DAG: rldimi [[REG2]], [[REG1]], 8, 48
+; CHECK-DAG: insrdi [[REG2]], [[REG1]], 8, 48
 ; CHECK-DAG: rotldi [[REG4:[0-9]+]], 3, 32
-; CHECK-DAG: rldimi [[REG2]], [[REG3]], 16, 40
+; CHECK-DAG: insrdi [[REG2]], [[REG3]], 8, 40
 ; CHECK-DAG: rotldi [[REG5:[0-9]+]], 3, 48
-; CHECK-DAG: rldimi [[REG2]], [[REG4]], 24, 32
+; CHECK-DAG: insrdi [[REG2]], [[REG4]], 8, 32
 ; CHECK-DAG: rotldi [[REG6:[0-9]+]], 3, 56
-; CHECK-DAG: rldimi [[REG2]], [[REG5]], 40, 16
-; CHECK-DAG: rldimi [[REG2]], [[REG6]], 48, 8
-; CHECK-DAG: rldimi [[REG2]], 3, 56, 0
+; CHECK-DAG: insrdi [[REG2]], [[REG5]], 8, 16
+; CHECK-DAG: nsrdi [[REG2]], [[REG6]], 8, 8
+; CHECK-DAG: insrdi [[REG2]], 3, 8, 0
 ; CHECK: mr 3, [[REG2]]
 ; CHECK: blr
 }
@@ -121,8 +121,8 @@
   ret i32 %or
 
 ; CHECK-LABEL: @test6
-; CHECK: rlwinm [[REG1:[0-9]+]], 3, 16, 24, 31
-; CHECK: rlwimi [[REG1]], 3, 16, 8, 15
+; CHECK: extrwi [[REG1:[0-9]+]], 3, 8, 8
+; CHECK: insrwi [[REG1]], 3, 8, 8
 ; CHECK: mr 3, [[REG1]]
 ; CHECK: blr
 }
@@ -169,7 +169,7 @@
 ; CHECK-DAG: rotldi [[REG5:[0-9]+]], 4, 62
 ; CHECK-DAG: rotldi [[REG6:[0-9]+]], 4, 50
 ; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 4
-; CHECK-DAG: rldimi [[REG6]], [[REG5]], 53, 0
+; CHECK-DAG: insrdi [[REG6]], [[REG5]], 11, 0
 ; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 32
 ; CHECK-DAG: oris [[REG4:[0-9]+]], [[REG3]], 25464
 ; CHECK: and 3, [[REG6]], [[REG4]]
@@ -249,7 +249,7 @@
   ret i64 %or3
 
 ; CHECK-LABEL: @test14
-; CHECK: rldicr [[REG1:[0-9]+]], 3, 0, 31
+; CHECK: clrrdi [[REG1:[0-9]+]], 3, 32
 ; CHECK: rlwimi [[REG1]], 3, 4, 24, 31
 ; CHECK: mr 3, [[REG1]]
 ; CHECK: blr
@@ -279,7 +279,7 @@
   ret i64 %or
 
 ; CHECK-LABEL: @test16
-; CHECK: rldimi 3, 4, 32, 0
+; CHECK: insrdi 3, 4, 32, 0
 ; CHECK: blr
 }
 
diff --git a/llvm/test/CodeGen/PowerPC/bswap64.ll b/llvm/test/CodeGen/PowerPC/bswap64.ll
--- a/llvm/test/CodeGen/PowerPC/bswap64.ll
+++ b/llvm/test/CodeGen/PowerPC/bswap64.ll
@@ -18,16 +18,16 @@
 ; NO-ALTIVEC:       # %bb.0: # %entry
 ; NO-ALTIVEC-NEXT:    rotldi 5, 3, 16
 ; NO-ALTIVEC-NEXT:    rotldi 4, 3, 8
-; NO-ALTIVEC-NEXT:    rldimi 4, 5, 8, 48
+; NO-ALTIVEC-NEXT:    insrdi 4, 5, 8, 48
 ; NO-ALTIVEC-NEXT:    rotldi 5, 3, 24
-; NO-ALTIVEC-NEXT:    rldimi 4, 5, 16, 40
+; NO-ALTIVEC-NEXT:    insrdi 4, 5, 8, 40
 ; NO-ALTIVEC-NEXT:    rotldi 5, 3, 32
-; NO-ALTIVEC-NEXT:    rldimi 4, 5, 24, 32
+; NO-ALTIVEC-NEXT:    insrdi 4, 5, 8, 32
 ; NO-ALTIVEC-NEXT:    rotldi 5, 3, 48
-; NO-ALTIVEC-NEXT:    rldimi 4, 5, 40, 16
+; NO-ALTIVEC-NEXT:    insrdi 4, 5, 8, 16
 ; NO-ALTIVEC-NEXT:    rotldi 5, 3, 56
-; NO-ALTIVEC-NEXT:    rldimi 4, 5, 48, 8
-; NO-ALTIVEC-NEXT:    rldimi 4, 3, 56, 0
+; NO-ALTIVEC-NEXT:    insrdi 4, 5, 8, 8
+; NO-ALTIVEC-NEXT:    insrdi 4, 3, 8, 0
 ; NO-ALTIVEC-NEXT:    mr 3, 4
 ; NO-ALTIVEC-NEXT:    blr
 entry:
diff --git a/llvm/test/CodeGen/PowerPC/build-vector-tests.ll b/llvm/test/CodeGen/PowerPC/build-vector-tests.ll
--- a/llvm/test/CodeGen/PowerPC/build-vector-tests.ll
+++ b/llvm/test/CodeGen/PowerPC/build-vector-tests.ll
@@ -816,22 +816,22 @@
 define <4 x i32> @fromRegsi(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) {
 ; P9BE-LABEL: fromRegsi:
 ; P9BE:       # %bb.0: # %entry
-; P9BE-NEXT:    rldimi r6, r5, 32, 0
-; P9BE-NEXT:    rldimi r4, r3, 32, 0
+; P9BE-NEXT:    insrdi r6, r5, 32, 0
+; P9BE-NEXT:    insrdi r4, r3, 32, 0
 ; P9BE-NEXT:    mtvsrdd v2, r4, r6
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: fromRegsi:
 ; P9LE:       # %bb.0: # %entry
-; P9LE-NEXT:    rldimi r3, r4, 32, 0
-; P9LE-NEXT:    rldimi r5, r6, 32, 0
+; P9LE-NEXT:    insrdi r3, r4, 32, 0
+; P9LE-NEXT:    insrdi r5, r6, 32, 0
 ; P9LE-NEXT:    mtvsrdd v2, r5, r3
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fromRegsi:
 ; P8BE:       # %bb.0: # %entry
-; P8BE-NEXT:    rldimi r6, r5, 32, 0
-; P8BE-NEXT:    rldimi r4, r3, 32, 0
+; P8BE-NEXT:    insrdi r6, r5, 32, 0
+; P8BE-NEXT:    insrdi r4, r3, 32, 0
 ; P8BE-NEXT:    mtfprd f0, r6
 ; P8BE-NEXT:    mtfprd f1, r4
 ; P8BE-NEXT:    xxmrghd v2, vs1, vs0
@@ -839,8 +839,8 @@
 ;
 ; P8LE-LABEL: fromRegsi:
 ; P8LE:       # %bb.0: # %entry
-; P8LE-NEXT:    rldimi r3, r4, 32, 0
-; P8LE-NEXT:    rldimi r5, r6, 32, 0
+; P8LE-NEXT:    insrdi r3, r4, 32, 0
+; P8LE-NEXT:    insrdi r5, r6, 32, 0
 ; P8LE-NEXT:    mtfprd f0, r3
 ; P8LE-NEXT:    mtfprd f1, r5
 ; P8LE-NEXT:    xxmrghd v2, vs1, vs0
@@ -1096,8 +1096,8 @@
 ; P9BE-NEXT:    lwz r5, 72(r3)
 ; P9BE-NEXT:    lwz r6, 8(r3)
 ; P9BE-NEXT:    lwz r3, 352(r3)
-; P9BE-NEXT:    rldimi r3, r6, 32, 0
-; P9BE-NEXT:    rldimi r5, r4, 32, 0
+; P9BE-NEXT:    insrdi r3, r6, 32, 0
+; P9BE-NEXT:    insrdi r5, r4, 32, 0
 ; P9BE-NEXT:    mtvsrdd v2, r5, r3
 ; P9BE-NEXT:    blr
 ;
@@ -1107,8 +1107,8 @@
 ; P9LE-NEXT:    lwz r5, 72(r3)
 ; P9LE-NEXT:    lwz r6, 8(r3)
 ; P9LE-NEXT:    lwz r3, 352(r3)
-; P9LE-NEXT:    rldimi r4, r5, 32, 0
-; P9LE-NEXT:    rldimi r6, r3, 32, 0
+; P9LE-NEXT:    insrdi r4, r5, 32, 0
+; P9LE-NEXT:    insrdi r6, r3, 32, 0
 ; P9LE-NEXT:    mtvsrdd v2, r6, r4
 ; P9LE-NEXT:    blr
 ;
@@ -1118,8 +1118,8 @@
 ; P8BE-NEXT:    lwz r5, 352(r3)
 ; P8BE-NEXT:    lwz r6, 16(r3)
 ; P8BE-NEXT:    lwz r3, 72(r3)
-; P8BE-NEXT:    rldimi r5, r4, 32, 0
-; P8BE-NEXT:    rldimi r3, r6, 32, 0
+; P8BE-NEXT:    insrdi r5, r4, 32, 0
+; P8BE-NEXT:    insrdi r3, r6, 32, 0
 ; P8BE-NEXT:    mtfprd f0, r5
 ; P8BE-NEXT:    mtfprd f1, r3
 ; P8BE-NEXT:    xxmrghd v2, vs1, vs0
@@ -1131,8 +1131,8 @@
 ; P8LE-NEXT:    lwz r5, 72(r3)
 ; P8LE-NEXT:    lwz r6, 8(r3)
 ; P8LE-NEXT:    lwz r3, 352(r3)
-; P8LE-NEXT:    rldimi r4, r5, 32, 0
-; P8LE-NEXT:    rldimi r6, r3, 32, 0
+; P8LE-NEXT:    insrdi r4, r5, 32, 0
+; P8LE-NEXT:    insrdi r6, r3, 32, 0
 ; P8LE-NEXT:    mtfprd f0, r4
 ; P8LE-NEXT:    mtfprd f1, r6
 ; P8LE-NEXT:    xxmrghd v2, vs1, vs0
@@ -1162,8 +1162,8 @@
 ; P9BE-NEXT:    lwz r5, 4(r3)
 ; P9BE-NEXT:    lwz r6, 8(r3)
 ; P9BE-NEXT:    lwz r3, 32(r3)
-; P9BE-NEXT:    rldimi r3, r6, 32, 0
-; P9BE-NEXT:    rldimi r5, r4, 32, 0
+; P9BE-NEXT:    insrdi r3, r6, 32, 0
+; P9BE-NEXT:    insrdi r5, r4, 32, 0
 ; P9BE-NEXT:    mtvsrdd v2, r5, r3
 ; P9BE-NEXT:    blr
 ;
@@ -1175,8 +1175,8 @@
 ; P9LE-NEXT:    lwz r5, 4(r3)
 ; P9LE-NEXT:    lwz r6, 8(r3)
 ; P9LE-NEXT:    lwz r3, 32(r3)
-; P9LE-NEXT:    rldimi r4, r5, 32, 0
-; P9LE-NEXT:    rldimi r6, r3, 32, 0
+; P9LE-NEXT:    insrdi r4, r5, 32, 0
+; P9LE-NEXT:    insrdi r6, r3, 32, 0
 ; P9LE-NEXT:    mtvsrdd v2, r6, r4
 ; P9LE-NEXT:    blr
 ;
@@ -1188,8 +1188,8 @@
 ; P8BE-NEXT:    lwz r5, 32(r3)
 ; P8BE-NEXT:    lwz r6, 16(r3)
 ; P8BE-NEXT:    lwz r3, 4(r3)
-; P8BE-NEXT:    rldimi r5, r4, 32, 0
-; P8BE-NEXT:    rldimi r3, r6, 32, 0
+; P8BE-NEXT:    insrdi r5, r4, 32, 0
+; P8BE-NEXT:    insrdi r3, r6, 32, 0
 ; P8BE-NEXT:    mtfprd f0, r5
 ; P8BE-NEXT:    mtfprd f1, r3
 ; P8BE-NEXT:    xxmrghd v2, vs1, vs0
@@ -1203,8 +1203,8 @@
 ; P8LE-NEXT:    lwz r5, 4(r3)
 ; P8LE-NEXT:    lwz r6, 8(r3)
 ; P8LE-NEXT:    lwz r3, 32(r3)
-; P8LE-NEXT:    rldimi r4, r5, 32, 0
-; P8LE-NEXT:    rldimi r6, r3, 32, 0
+; P8LE-NEXT:    insrdi r4, r5, 32, 0
+; P8LE-NEXT:    insrdi r6, r3, 32, 0
 ; P8LE-NEXT:    mtfprd f0, r4
 ; P8LE-NEXT:    mtfprd f1, r6
 ; P8LE-NEXT:    xxmrghd v2, vs1, vs0
@@ -2335,22 +2335,22 @@
 define <4 x i32> @fromRegsui(i32 zeroext %a, i32 zeroext %b, i32 zeroext %c, i32 zeroext %d) {
 ; P9BE-LABEL: fromRegsui:
 ; P9BE:       # %bb.0: # %entry
-; P9BE-NEXT:    rldimi r6, r5, 32, 0
-; P9BE-NEXT:    rldimi r4, r3, 32, 0
+; P9BE-NEXT:    insrdi r6, r5, 32, 0
+; P9BE-NEXT:    insrdi r4, r3, 32, 0
 ; P9BE-NEXT:    mtvsrdd v2, r4, r6
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: fromRegsui:
 ; P9LE:       # %bb.0: # %entry
-; P9LE-NEXT:    rldimi r3, r4, 32, 0
-; P9LE-NEXT:    rldimi r5, r6, 32, 0
+; P9LE-NEXT:    insrdi r3, r4, 32, 0
+; P9LE-NEXT:    insrdi r5, r6, 32, 0
 ; P9LE-NEXT:    mtvsrdd v2, r5, r3
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fromRegsui:
 ; P8BE:       # %bb.0: # %entry
-; P8BE-NEXT:    rldimi r6, r5, 32, 0
-; P8BE-NEXT:    rldimi r4, r3, 32, 0
+; P8BE-NEXT:    insrdi r6, r5, 32, 0
+; P8BE-NEXT:    insrdi r4, r3, 32, 0
 ; P8BE-NEXT:    mtfprd f0, r6
 ; P8BE-NEXT:    mtfprd f1, r4
 ; P8BE-NEXT:    xxmrghd v2, vs1, vs0
@@ -2358,8 +2358,8 @@
 ;
 ; P8LE-LABEL: fromRegsui:
 ; P8LE:       # %bb.0: # %entry
-; P8LE-NEXT:    rldimi r3, r4, 32, 0
-; P8LE-NEXT:    rldimi r5, r6, 32, 0
+; P8LE-NEXT:    insrdi r3, r4, 32, 0
+; P8LE-NEXT:    insrdi r5, r6, 32, 0
 ; P8LE-NEXT:    mtfprd f0, r3
 ; P8LE-NEXT:    mtfprd f1, r5
 ; P8LE-NEXT:    xxmrghd v2, vs1, vs0
@@ -2615,8 +2615,8 @@
 ; P9BE-NEXT:    lwz r5, 72(r3)
 ; P9BE-NEXT:    lwz r6, 8(r3)
 ; P9BE-NEXT:    lwz r3, 352(r3)
-; P9BE-NEXT:    rldimi r3, r6, 32, 0
-; P9BE-NEXT:    rldimi r5, r4, 32, 0
+; P9BE-NEXT:    insrdi r3, r6, 32, 0
+; P9BE-NEXT:    insrdi r5, r4, 32, 0
 ; P9BE-NEXT:    mtvsrdd v2, r5, r3
 ; P9BE-NEXT:    blr
 ;
@@ -2626,8 +2626,8 @@
 ; P9LE-NEXT:    lwz r5, 72(r3)
 ; P9LE-NEXT:    lwz r6, 8(r3)
 ; P9LE-NEXT:    lwz r3, 352(r3)
-; P9LE-NEXT:    rldimi r4, r5, 32, 0
-; P9LE-NEXT:    rldimi r6, r3, 32, 0
+; P9LE-NEXT:    insrdi r4, r5, 32, 0
+; P9LE-NEXT:    insrdi r6, r3, 32, 0
 ; P9LE-NEXT:    mtvsrdd v2, r6, r4
 ; P9LE-NEXT:    blr
 ;
@@ -2637,8 +2637,8 @@
 ; P8BE-NEXT:    lwz r5, 352(r3)
 ; P8BE-NEXT:    lwz r6, 16(r3)
 ; P8BE-NEXT:    lwz r3, 72(r3)
-; P8BE-NEXT:    rldimi r5, r4, 32, 0
-; P8BE-NEXT:    rldimi r3, r6, 32, 0
+; P8BE-NEXT:    insrdi r5, r4, 32, 0
+; P8BE-NEXT:    insrdi r3, r6, 32, 0
 ; P8BE-NEXT:    mtfprd f0, r5
 ; P8BE-NEXT:    mtfprd f1, r3
 ; P8BE-NEXT:    xxmrghd v2, vs1, vs0
@@ -2650,8 +2650,8 @@
 ; P8LE-NEXT:    lwz r5, 72(r3)
 ; P8LE-NEXT:    lwz r6, 8(r3)
 ; P8LE-NEXT:    lwz r3, 352(r3)
-; P8LE-NEXT:    rldimi r4, r5, 32, 0
-; P8LE-NEXT:    rldimi r6, r3, 32, 0
+; P8LE-NEXT:    insrdi r4, r5, 32, 0
+; P8LE-NEXT:    insrdi r6, r3, 32, 0
 ; P8LE-NEXT:    mtfprd f0, r4
 ; P8LE-NEXT:    mtfprd f1, r6
 ; P8LE-NEXT:    xxmrghd v2, vs1, vs0
@@ -2681,8 +2681,8 @@
 ; P9BE-NEXT:    lwz r5, 4(r3)
 ; P9BE-NEXT:    lwz r6, 8(r3)
 ; P9BE-NEXT:    lwz r3, 32(r3)
-; P9BE-NEXT:    rldimi r3, r6, 32, 0
-; P9BE-NEXT:    rldimi r5, r4, 32, 0
+; P9BE-NEXT:    insrdi r3, r6, 32, 0
+; P9BE-NEXT:    insrdi r5, r4, 32, 0
 ; P9BE-NEXT:    mtvsrdd v2, r5, r3
 ; P9BE-NEXT:    blr
 ;
@@ -2694,8 +2694,8 @@
 ; P9LE-NEXT:    lwz r5, 4(r3)
 ; P9LE-NEXT:    lwz r6, 8(r3)
 ; P9LE-NEXT:    lwz r3, 32(r3)
-; P9LE-NEXT:    rldimi r4, r5, 32, 0
-; P9LE-NEXT:    rldimi r6, r3, 32, 0
+; P9LE-NEXT:    insrdi r4, r5, 32, 0
+; P9LE-NEXT:    insrdi r6, r3, 32, 0
 ; P9LE-NEXT:    mtvsrdd v2, r6, r4
 ; P9LE-NEXT:    blr
 ;
@@ -2707,8 +2707,8 @@
 ; P8BE-NEXT:    lwz r5, 32(r3)
 ; P8BE-NEXT:    lwz r6, 16(r3)
 ; P8BE-NEXT:    lwz r3, 4(r3)
-; P8BE-NEXT:    rldimi r5, r4, 32, 0
-; P8BE-NEXT:    rldimi r3, r6, 32, 0
+; P8BE-NEXT:    insrdi r5, r4, 32, 0
+; P8BE-NEXT:    insrdi r3, r6, 32, 0
 ; P8BE-NEXT:    mtfprd f0, r5
 ; P8BE-NEXT:    mtfprd f1, r3
 ; P8BE-NEXT:    xxmrghd v2, vs1, vs0
@@ -2722,8 +2722,8 @@
 ; P8LE-NEXT:    lwz r5, 4(r3)
 ; P8LE-NEXT:    lwz r6, 8(r3)
 ; P8LE-NEXT:    lwz r3, 32(r3)
-; P8LE-NEXT:    rldimi r4, r5, 32, 0
-; P8LE-NEXT:    rldimi r6, r3, 32, 0
+; P8LE-NEXT:    insrdi r4, r5, 32, 0
+; P8LE-NEXT:    insrdi r6, r3, 32, 0
 ; P8LE-NEXT:    mtfprd f0, r4
 ; P8LE-NEXT:    mtfprd f1, r6
 ; P8LE-NEXT:    xxmrghd v2, vs1, vs0
diff --git a/llvm/test/CodeGen/PowerPC/collapse-rotates.mir b/llvm/test/CodeGen/PowerPC/collapse-rotates.mir
--- a/llvm/test/CodeGen/PowerPC/collapse-rotates.mir
+++ b/llvm/test/CodeGen/PowerPC/collapse-rotates.mir
@@ -62,4 +62,4 @@
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
-# CHECK: rldic 3, 3, 5, 29
+# CHECK: clrlsldi 3, 3, 34, 5
diff --git a/llvm/test/CodeGen/PowerPC/combine-setcc.ll b/llvm/test/CodeGen/PowerPC/combine-setcc.ll
--- a/llvm/test/CodeGen/PowerPC/combine-setcc.ll
+++ b/llvm/test/CodeGen/PowerPC/combine-setcc.ll
@@ -93,7 +93,7 @@
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    add r3, r4, r3
 ; CHECK-NEXT:    cntlzd r3, r3
-; CHECK-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-NEXT:    extrdi r3, r3, 1, 57
 ; CHECK-NEXT:    blr
   %sub = sub nsw i64 0, %x
   %cmp = icmp eq i64 %sub, %y
@@ -190,7 +190,7 @@
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    add r3, r3, r4
 ; CHECK-NEXT:    cntlzd r3, r3
-; CHECK-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-NEXT:    extrdi r3, r3, 1, 57
 ; CHECK-NEXT:    blr
   %sub = sub nsw i64 0, %y
   %cmp = icmp eq i64 %sub, %x
diff --git a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir
--- a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir
+++ b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir
@@ -364,7 +364,7 @@
     %4 = RLWNM_rec %2, %3, 24, 31, implicit-def $cr0
     ; CHECK: RLWINM_rec %2, 10, 24, 31, implicit-def $cr0
     ; CHECK-LATE: li 3, -22
-    ; CHECK-LATE: rlwinm. 5, 4, 10, 24, 31
+    ; CHECK-LATE: extrwi. 5, 4, 8, 2
     %5 = COPY killed $cr0
     %6 = ISEL %2, %3, %5.sub_eq
     %8 = IMPLICIT_DEF
@@ -946,7 +946,7 @@
     %3 = LI 300
     %4 = RLDCR %0, killed %3, 0
     ; CHECK: RLDICR %0, 44, 0
-    ; CHECK-LATE: rldicr 3, 3, 44, 0
+    ; CHECK-LATE: extldi 3, 3, 1, 44
     $x3 = COPY %4
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
@@ -1001,7 +1001,7 @@
     %3 = LI -18
     %4 = RLDCR_rec %0, killed %3, 0, implicit-def $cr0
     ; CHECK: RLDICR_rec %0, 46, 0, implicit-def $cr0
-    ; CHECK-LATE: rldicr. 5, 3, 46, 0
+    ; CHECK-LATE: extldi. 5, 3, 1, 46
     %5 = COPY killed $cr0
     %6 = ISEL8 %2, %0, %5.sub_eq
     $x3 = COPY %6
@@ -1160,7 +1160,7 @@
     %2 = LI 400
     %3 = SRD %0, killed %2
     ; CHECK: RLDICL %0, 48, 16
-    ; CHECK-LATE: rldicl 3, 3, 48, 16
+    ; CHECK-LATE: srdi 3, 3, 16
     $x3 = COPY %3
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
diff --git a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
--- a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
+++ b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
@@ -3783,7 +3783,7 @@
     %3 = LI 0
     %4 = RLDCR %0, killed %3, 0
     ; CHECK: RLDICR %0, 0, 0
-    ; CHECK-LATE: rldicr 3, 3, 0, 0
+    ; CHECK-LATE: clrrdi 3, 3, 63
     $x3 = COPY %4
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
@@ -3838,7 +3838,7 @@
     %3 = LI 18
     %4 = RLDCR_rec %0, killed %3, 0, implicit-def $cr0
     ; CHECK: RLDICR_rec %0, 18, 0, implicit-def $cr0
-    ; CHECK-LATE: rldicr. 5, 3, 18, 0
+    ; CHECK-LATE: extldi. 5, 3, 1, 18
     %5 = COPY killed $cr0
     %6 = ISEL8 %2, %0, %5.sub_eq
     $x3 = COPY %6
@@ -4589,7 +4589,7 @@
     %2 = LI 17
     %3 = SLD_rec %0, killed %2, implicit-def $cr0
     ; CHECK: RLDICR_rec %0, 17, 46, implicit-def $cr0
-    ; CHECK-LATE: rldicr. 5, 3, 17, 46
+    ; CHECK-LATE: sldi. 5, 3, 17
     %4 = COPY killed $cr0
     %5 = ISEL8 %1, %0, %4.sub_eq
     $x3 = COPY %5
@@ -4642,7 +4642,7 @@
     %2 = LI 4
     %3 = SRD %0, killed %2
     ; CHECK: RLDICL %0, 60, 4
-    ; CHECK-LATE: rldicl 3, 3, 60, 4
+    ; CHECK-LATE: srdi 3, 3, 4
     $x3 = COPY %3
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
@@ -4695,7 +4695,7 @@
     %2 = LI 17
     %3 = SRD_rec %0, killed %2, implicit-def $cr0
     ; CHECK: RLDICL_rec %0, 47, 17, implicit-def $cr0
-    ; CHECK-LATE: rldicl. 5, 3, 47, 17
+    ; CHECK-LATE: srdi. 5, 3, 17
     %4 = COPY killed $cr0
     %5 = ISEL8 %1, %0, %4.sub_eq
     $x3 = COPY %5
@@ -4812,7 +4812,7 @@
     %3 = COPY %0.sub_32
     %4 = SLW_rec %3, %2, implicit-def $cr0
     ; CHECK: RLWINM_rec %3, 11, 0, 20, implicit-def $cr0
-    ; CHECK-LATE: rlwinm. 5, 3, 11, 0, 20
+    ; CHECK-LATE: slwi. 5, 3, 11
     %5 = COPY killed $cr0
     %6 = ISEL %2, %3, %5.sub_eq
     %8 = IMPLICIT_DEF
@@ -4932,7 +4932,7 @@
     %3 = COPY %0.sub_32
     %4 = SRW_rec %3, %2, implicit-def $cr0
     ; CHECK: RLWINM_rec %3, 25, 7, 31
-    ; CHECK-LATE: rlwinm. 5, 3, 25, 7, 31
+    ; CHECK-LATE: srwi. 5, 3, 7
     %5 = COPY killed $cr0
     %6 = ISEL %2, %3, %5.sub_eq
     %8 = IMPLICIT_DEF
diff --git a/llvm/test/CodeGen/PowerPC/expand-isel.ll b/llvm/test/CodeGen/PowerPC/expand-isel.ll
--- a/llvm/test/CodeGen/PowerPC/expand-isel.ll
+++ b/llvm/test/CodeGen/PowerPC/expand-isel.ll
@@ -199,7 +199,7 @@
 ; CHECK: [[TGT]]
 ; CHECK: xor [[XOR:r[0-9]+]]
 ; CHECK: cntlzd [[CZ:r[0-9]+]], [[XOR]]
-; CHECK: rldicl [[SH:r[0-9]+]], [[CZ]], 58, 63
+; CHECK: extrdi [[SH:r[0-9]+]], [[CZ]], 1, 57
 }
 
 !1 = !{!2, !2, i64 0}
diff --git a/llvm/test/CodeGen/PowerPC/extract-and-store.ll b/llvm/test/CodeGen/PowerPC/extract-and-store.ll
--- a/llvm/test/CodeGen/PowerPC/extract-and-store.ll
+++ b/llvm/test/CodeGen/PowerPC/extract-and-store.ll
@@ -643,14 +643,14 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xxswapd vs0, vs34
 ; CHECK-NEXT:    mfvsrd r3, vs34
-; CHECK-NEXT:    rldicl r6, r3, 32, 56
-; CHECK-NEXT:    rldicl r3, r3, 56, 56
+; CHECK-NEXT:    extrdi r6, r3, 8, 24
+; CHECK-NEXT:    extrdi r3, r3, 8, 48
 ; CHECK-NEXT:    mffprd r4, f0
 ; CHECK-NEXT:    stb r6, 1(r5)
 ; CHECK-NEXT:    stb r3, 2(r5)
-; CHECK-NEXT:    rldicl r6, r4, 32, 56
-; CHECK-NEXT:    rldicl r3, r4, 8, 56
-; CHECK-NEXT:    rldicl r4, r4, 16, 56
+; CHECK-NEXT:    extrdi r6, r4, 8, 24
+; CHECK-NEXT:    srdi r3, r4, 56
+; CHECK-NEXT:    extrdi r4, r4, 8, 8
 ; CHECK-NEXT:    stb r6, 0(r5)
 ; CHECK-NEXT:    stb r3, 3(r5)
 ; CHECK-NEXT:    stb r4, 4(r5)
@@ -660,14 +660,14 @@
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    xxswapd vs0, vs34
 ; CHECK-BE-NEXT:    mfvsrd r3, vs34
-; CHECK-BE-NEXT:    rldicl r6, r3, 40, 56
+; CHECK-BE-NEXT:    extrdi r6, r3, 8, 32
 ; CHECK-BE-NEXT:    mffprd r4, f0
 ; CHECK-BE-NEXT:    stb r6, 0(r5)
-; CHECK-BE-NEXT:    rldicl r6, r4, 40, 56
-; CHECK-BE-NEXT:    rldicl r4, r4, 16, 56
+; CHECK-BE-NEXT:    extrdi r6, r4, 8, 32
+; CHECK-BE-NEXT:    extrdi r4, r4, 8, 8
 ; CHECK-BE-NEXT:    stb r6, 1(r5)
 ; CHECK-BE-NEXT:    clrldi r6, r3, 56
-; CHECK-BE-NEXT:    rldicl r3, r3, 56, 56
+; CHECK-BE-NEXT:    extrdi r3, r3, 8, 48
 ; CHECK-BE-NEXT:    stb r4, 2(r5)
 ; CHECK-BE-NEXT:    stb r6, 3(r5)
 ; CHECK-BE-NEXT:    stb r3, 4(r5)
@@ -730,31 +730,31 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xxswapd vs0, vs34
 ; CHECK-NEXT:    mfvsrd r3, vs34
-; CHECK-NEXT:    rldicl r4, r3, 32, 56
-; CHECK-NEXT:    rldicl r6, r3, 56, 56
+; CHECK-NEXT:    extrdi r4, r3, 8, 24
+; CHECK-NEXT:    extrdi r6, r3, 8, 48
 ; CHECK-NEXT:    stb r4, 1(r5)
-; CHECK-NEXT:    rldicl r4, r3, 40, 56
+; CHECK-NEXT:    extrdi r4, r3, 8, 32
 ; CHECK-NEXT:    mffprd r7, f0
 ; CHECK-NEXT:    stb r6, 2(r5)
-; CHECK-NEXT:    rldicl r6, r3, 24, 56
+; CHECK-NEXT:    extrdi r6, r3, 8, 16
 ; CHECK-NEXT:    stb r4, 6(r5)
-; CHECK-NEXT:    rldicl r4, r3, 8, 56
+; CHECK-NEXT:    srdi r4, r3, 56
 ; CHECK-NEXT:    stb r6, 7(r5)
-; CHECK-NEXT:    rldicl r3, r3, 16, 56
+; CHECK-NEXT:    extrdi r3, r3, 8, 8
 ; CHECK-NEXT:    stb r4, 9(r5)
-; CHECK-NEXT:    rldicl r4, r7, 32, 56
-; CHECK-NEXT:    rldicl r6, r7, 8, 56
+; CHECK-NEXT:    extrdi r4, r7, 8, 24
+; CHECK-NEXT:    srdi r6, r7, 56
 ; CHECK-NEXT:    stb r3, 12(r5)
 ; CHECK-NEXT:    stb r4, 0(r5)
-; CHECK-NEXT:    rldicl r4, r7, 16, 56
+; CHECK-NEXT:    extrdi r4, r7, 8, 8
 ; CHECK-NEXT:    stb r6, 3(r5)
 ; CHECK-NEXT:    clrldi r6, r7, 56
 ; CHECK-NEXT:    stb r4, 4(r5)
-; CHECK-NEXT:    rldicl r4, r7, 48, 56
+; CHECK-NEXT:    extrdi r4, r7, 8, 40
 ; CHECK-NEXT:    stb r6, 5(r5)
-; CHECK-NEXT:    rldicl r6, r7, 56, 56
+; CHECK-NEXT:    extrdi r6, r7, 8, 48
 ; CHECK-NEXT:    stb r4, 8(r5)
-; CHECK-NEXT:    rldicl r4, r7, 24, 56
+; CHECK-NEXT:    extrdi r4, r7, 8, 16
 ; CHECK-NEXT:    stb r6, 10(r5)
 ; CHECK-NEXT:    stb r4, 11(r5)
 ; CHECK-NEXT:    blr
@@ -763,30 +763,30 @@
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mfvsrd r3, vs34
 ; CHECK-BE-NEXT:    xxswapd vs0, vs34
-; CHECK-BE-NEXT:    rldicl r4, r3, 40, 56
+; CHECK-BE-NEXT:    extrdi r4, r3, 8, 32
 ; CHECK-BE-NEXT:    clrldi r6, r3, 56
 ; CHECK-BE-NEXT:    stb r4, 0(r5)
-; CHECK-BE-NEXT:    rldicl r4, r3, 56, 56
+; CHECK-BE-NEXT:    extrdi r4, r3, 8, 48
 ; CHECK-BE-NEXT:    mffprd r7, f0
 ; CHECK-BE-NEXT:    stb r6, 3(r5)
-; CHECK-BE-NEXT:    rldicl r6, r3, 8, 56
+; CHECK-BE-NEXT:    srdi r6, r3, 56
 ; CHECK-BE-NEXT:    stb r4, 4(r5)
-; CHECK-BE-NEXT:    rldicl r4, r3, 24, 56
+; CHECK-BE-NEXT:    extrdi r4, r3, 8, 16
 ; CHECK-BE-NEXT:    stb r6, 5(r5)
-; CHECK-BE-NEXT:    rldicl r6, r3, 16, 56
+; CHECK-BE-NEXT:    extrdi r6, r3, 8, 8
 ; CHECK-BE-NEXT:    stb r4, 8(r5)
-; CHECK-BE-NEXT:    rldicl r4, r7, 40, 56
+; CHECK-BE-NEXT:    extrdi r4, r7, 8, 32
 ; CHECK-BE-NEXT:    stb r6, 10(r5)
-; CHECK-BE-NEXT:    rldicl r6, r7, 16, 56
+; CHECK-BE-NEXT:    extrdi r6, r7, 8, 8
 ; CHECK-BE-NEXT:    stb r4, 1(r5)
-; CHECK-BE-NEXT:    rldicl r4, r7, 32, 56
+; CHECK-BE-NEXT:    extrdi r4, r7, 8, 24
 ; CHECK-BE-NEXT:    stb r6, 2(r5)
-; CHECK-BE-NEXT:    rldicl r6, r7, 48, 56
+; CHECK-BE-NEXT:    extrdi r6, r7, 8, 40
 ; CHECK-BE-NEXT:    stb r4, 6(r5)
 ; CHECK-BE-NEXT:    clrldi r4, r7, 56
 ; CHECK-BE-NEXT:    stb r6, 7(r5)
-; CHECK-BE-NEXT:    rldicl r3, r3, 48, 56
-; CHECK-BE-NEXT:    rldicl r6, r7, 56, 56
+; CHECK-BE-NEXT:    extrdi r3, r3, 8, 40
+; CHECK-BE-NEXT:    extrdi r6, r7, 8, 48
 ; CHECK-BE-NEXT:    stb r4, 9(r5)
 ; CHECK-BE-NEXT:    stb r3, 11(r5)
 ; CHECK-BE-NEXT:    stb r6, 12(r5)
diff --git a/llvm/test/CodeGen/PowerPC/fold-rlwinm-1.ll b/llvm/test/CodeGen/PowerPC/fold-rlwinm-1.ll
--- a/llvm/test/CodeGen/PowerPC/fold-rlwinm-1.ll
+++ b/llvm/test/CodeGen/PowerPC/fold-rlwinm-1.ll
@@ -11,7 +11,7 @@
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    addis r4, r2, res@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
-; CHECK-NEXT:    rlwinm r3, r3, 14, 0, 12
+; CHECK-NEXT:    extlwi r3, r3, 13, 14
 ; CHECK-NEXT:    stw r3, res@toc@l(r4)
 ; CHECK-NEXT:    blr
 entry:
@@ -30,7 +30,7 @@
 ; CHECK-NEXT:    addis r6, r2, res@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
 ; CHECK-NEXT:    srwi r5, r3, 5
-; CHECK-NEXT:    rlwinm r3, r3, 14, 0, 12
+; CHECK-NEXT:    extlwi r3, r3, 13, 14
 ; CHECK-NEXT:    stw r5, res2@toc@l(r4)
 ; CHECK-NEXT:    stw r3, res@toc@l(r6)
 ; CHECK-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll b/llvm/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll
--- a/llvm/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll
+++ b/llvm/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll
@@ -11,7 +11,7 @@
 ; PPC64-DAG: stfd 1, [[OFFSET_LO:-?[0-9]+]]([[SP]]) 
 ; PPC64-DAG: ld [[HI:[0-9]+]], [[OFFSET_LO]]([[SP]])
 ; PPC64-DAG: ld [[LO:[0-9]+]], [[OFFSET_HI]]([[SP]])
-; PPC64-DAG: rldicr [[FLIP_BIT:[0-9]+]], [[HI]], 0, 0
+; PPC64-DAG: clrrdi [[FLIP_BIT:[0-9]+]], [[HI]], 63
 ; PPC64-DAG: xor 3, [[HI]], [[FLIP_BIT]]
 ; PPC64-DAG: xor 4, [[LO]], [[FLIP_BIT]]
 ; PPC64: blr
@@ -19,7 +19,7 @@
 ; PPC64-P8-LABEL: test_abs:
 ; PPC64-P8-DAG: mffprd [[LO:[0-9]+]], 2
 ; PPC64-P8-DAG: mffprd [[HI:[0-9]+]], 1
-; PPC64-P8-DAG: rldicr [[FLIP_BIT:[0-9]+]], [[HI]], 0, 0
+; PPC64-P8-DAG: clrrdi [[FLIP_BIT:[0-9]+]], [[HI]], 63
 ; PPC64-P8-DAG: xor 3, [[HI]], [[FLIP_BIT]]
 ; PPC64-P8-DAG: xor 4, [[LO]], [[FLIP_BIT]]
 ; PPC64-P8: blr
@@ -28,7 +28,7 @@
 ; PPC32-DAG: stfd 2, 16(1)
 ; PPC32-DAG: lwz [[HI0:[0-9]+]], 24(1)
 ; PPC32-DAG: lwz [[LO0:[0-9]+]], 16(1)
-; PPC32: rlwinm [[FLIP_BIT:[0-9]+]], [[HI0]], 0, 0, 0
+; PPC32: clrrwi [[FLIP_BIT:[0-9]+]], [[HI0]], 31
 ; PPC32-DAG: lwz [[HI1:[0-9]+]], 28(1)
 ; PPC32-DAG: lwz [[LO1:[0-9]+]], 20(1)
 ; PPC32-DAG: xor [[HI0]], [[HI0]], [[FLIP_BIT]]
@@ -88,7 +88,7 @@
 ; PPC64-DAG: sldi [[CST_HI:[0-9]+]], [[HI_TMP]], 48
 ; PPC64-DAG: sldi [[CST_LO:[0-9]+]], [[LO_TMP]], 52
 ; PPC64-DAG: ld [[X_HI:[0-9]+]], [[OFFSET]](1)
-; PPC64-DAG: rldicr [[NEW_HI_TMP:[0-9]+]], [[X_HI]], 0, 0
+; PPC64-DAG: clrrdi [[NEW_HI_TMP:[0-9]+]], [[X_HI]], 63
 ; PPC64-DAG: or 3, [[NEW_HI_TMP]], [[CST_HI]]
 ; PPC64-DAG: xor 4, [[NEW_HI_TMP]], [[CST_LO]]
 ; PPC64: blr
@@ -100,14 +100,14 @@
 ; PPC64-P8-NOT: BARRIER
 ; PPC64-P8-DAG: sldi [[CST_HI:[0-9]+]], [[HI_TMP]], 48
 ; PPC64-P8-DAG: sldi [[CST_LO:[0-9]+]], [[LO_TMP]], 52
-; PPC64-P8-DAG: rldicr [[NEW_HI_TMP:[0-9]+]], [[X_HI]], 0, 0
+; PPC64-P8-DAG: clrrdi [[NEW_HI_TMP:[0-9]+]], [[X_HI]], 63
 ; PPC64-P8-DAG: or 3, [[NEW_HI_TMP]], [[CST_HI]]
 ; PPC64-P8-DAG: xor 4, [[NEW_HI_TMP]], [[CST_LO]]
 ; PPC64-P8: blr
 
 ; PPC32: stfd 1, [[STACK:[0-9]+]](1)
 ; PPC32: lwz [[HI:[0-9]+]], [[STACK]](1)
-; PPC32: rlwinm [[FLIP_BIT:[0-9]+]], [[HI]], 0, 0, 0
+; PPC32: clrrwi [[FLIP_BIT:[0-9]+]], [[HI]], 31
 ; PPC32-NOT: BARRIER
 ; PPC32-DAG: oris {{[0-9]+}}, [[FLIP_BIT]], 16399
 ; PPC32-DAG: xoris {{[0-9]+}}, [[FLIP_BIT]], 48304
diff --git a/llvm/test/CodeGen/PowerPC/funnel-shift-rot.ll b/llvm/test/CodeGen/PowerPC/funnel-shift-rot.ll
--- a/llvm/test/CodeGen/PowerPC/funnel-shift-rot.ll
+++ b/llvm/test/CodeGen/PowerPC/funnel-shift-rot.ll
@@ -19,7 +19,7 @@
 ; CHECK-LABEL: rotl_i8_const_shift:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    rotlwi 4, 3, 27
-; CHECK-NEXT:    rlwimi 4, 3, 3, 0, 28
+; CHECK-NEXT:    insrwi 4, 3, 29, 0
 ; CHECK-NEXT:    mr 3, 4
 ; CHECK-NEXT:    blr
   %f = call i8 @llvm.fshl.i8(i8 %x, i8 %x, i8 3)
@@ -99,7 +99,7 @@
 ; CHECK-LABEL: rotr_i8_const_shift:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    rotlwi 4, 3, 29
-; CHECK-NEXT:    rlwimi 4, 3, 5, 0, 26
+; CHECK-NEXT:    insrwi 4, 3, 27, 0
 ; CHECK-NEXT:    mr 3, 4
 ; CHECK-NEXT:    blr
   %f = call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 3)
diff --git a/llvm/test/CodeGen/PowerPC/funnel-shift.ll b/llvm/test/CodeGen/PowerPC/funnel-shift.ll
--- a/llvm/test/CodeGen/PowerPC/funnel-shift.ll
+++ b/llvm/test/CodeGen/PowerPC/funnel-shift.ll
@@ -42,7 +42,7 @@
 ; CHECK-NEXT:    oris 6, 6, 3542
 ; CHECK-NEXT:    ori 6, 6, 31883
 ; CHECK-NEXT:    mulhdu 6, 5, 6
-; CHECK-NEXT:    rldicl 6, 6, 59, 5
+; CHECK-NEXT:    srdi 6, 6, 5
 ; CHECK-NEXT:    mulli 6, 6, 37
 ; CHECK-NEXT:    sub. 5, 5, 6
 ; CHECK-NEXT:    subfic 6, 5, 37
@@ -73,7 +73,7 @@
 ; CHECK-LABEL: fshl_i32_const_shift:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    rotlwi 4, 4, 9
-; CHECK-NEXT:    rlwimi 4, 3, 9, 0, 22
+; CHECK-NEXT:    insrwi 4, 3, 23, 0
 ; CHECK-NEXT:    mr 3, 4
 ; CHECK-NEXT:    blr
   %f = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 9)
@@ -86,7 +86,7 @@
 ; CHECK-LABEL: fshl_i32_const_overshift:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    rotlwi 4, 4, 9
-; CHECK-NEXT:    rlwimi 4, 3, 9, 0, 22
+; CHECK-NEXT:    insrwi 4, 3, 23, 0
 ; CHECK-NEXT:    mr 3, 4
 ; CHECK-NEXT:    blr
   %f = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 41)
@@ -99,7 +99,7 @@
 ; CHECK-LABEL: fshl_i64_const_overshift:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    rotldi 4, 4, 41
-; CHECK-NEXT:    rldimi 4, 3, 41, 0
+; CHECK-NEXT:    insrdi 4, 3, 23, 0
 ; CHECK-NEXT:    mr 3, 4
 ; CHECK-NEXT:    blr
   %f = call i64 @llvm.fshl.i64(i64 %x, i64 %y, i64 105)
@@ -147,7 +147,7 @@
 ; CHECK-NEXT:    oris 6, 6, 3542
 ; CHECK-NEXT:    ori 6, 6, 31883
 ; CHECK-NEXT:    mulhdu 6, 5, 6
-; CHECK-NEXT:    rldicl 6, 6, 59, 5
+; CHECK-NEXT:    srdi 6, 6, 5
 ; CHECK-NEXT:    mulli 6, 6, 37
 ; CHECK-NEXT:    sub. 5, 5, 6
 ; CHECK-NEXT:    clrldi 6, 4, 27
@@ -179,7 +179,7 @@
 ; CHECK-LABEL: fshr_i32_const_shift:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    rotlwi 4, 4, 23
-; CHECK-NEXT:    rlwimi 4, 3, 23, 0, 8
+; CHECK-NEXT:    insrwi 4, 3, 9, 0
 ; CHECK-NEXT:    mr 3, 4
 ; CHECK-NEXT:    blr
   %f = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 9)
@@ -192,7 +192,7 @@
 ; CHECK-LABEL: fshr_i32_const_overshift:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    rotlwi 4, 4, 23
-; CHECK-NEXT:    rlwimi 4, 3, 23, 0, 8
+; CHECK-NEXT:    insrwi 4, 3, 9, 0
 ; CHECK-NEXT:    mr 3, 4
 ; CHECK-NEXT:    blr
   %f = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 41)
@@ -205,7 +205,7 @@
 ; CHECK-LABEL: fshr_i64_const_overshift:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    rotldi 4, 4, 23
-; CHECK-NEXT:    rldimi 4, 3, 23, 0
+; CHECK-NEXT:    insrdi 4, 3, 41, 0
 ; CHECK-NEXT:    mr 3, 4
 ; CHECK-NEXT:    blr
   %f = call i64 @llvm.fshr.i64(i64 %x, i64 %y, i64 105)
diff --git a/llvm/test/CodeGen/PowerPC/htm-ttest.ll b/llvm/test/CodeGen/PowerPC/htm-ttest.ll
--- a/llvm/test/CodeGen/PowerPC/htm-ttest.ll
+++ b/llvm/test/CodeGen/PowerPC/htm-ttest.ll
@@ -8,8 +8,8 @@
 ; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    tabortwci. 0, 3, 0
 ; CHECK-NEXT:    mfocrf 3, 128
-; CHECK-NEXT:    rldicl 3, 3, 36, 28
-; CHECK-NEXT:    rlwinm. 3, 3, 31, 30, 31
+; CHECK-NEXT:    srdi 3, 3, 28
+; CHECK-NEXT:    extrwi. 3, 3, 2, 29
 ; CHECK-NEXT:    beqlr+ 0
 ; CHECK-NEXT:  # %bb.1:
   %1 = call i64 @llvm.ppc.ttest() #1
diff --git a/llvm/test/CodeGen/PowerPC/htm.ll b/llvm/test/CodeGen/PowerPC/htm.ll
--- a/llvm/test/CodeGen/PowerPC/htm.ll
+++ b/llvm/test/CodeGen/PowerPC/htm.ll
@@ -10,7 +10,7 @@
 ; CHECK-LABEL: @test1
 ; CHECK: tbegin. 0
 ; CHECK: mfocrf  [[REGISTER1:[0-9]+]], 128
-; CHECK: rlwinm  [[REGISTER2:[0-9]+]], [[REGISTER1]], 3, 31, 31
+; CHECK: extrwi  [[REGISTER2:[0-9]+]], [[REGISTER1]], 1, 2
 ; CHECK: xori    {{[0-9]+}}, [[REGISTER2]], 1
 }
 
diff --git a/llvm/test/CodeGen/PowerPC/i64_fp_round.ll b/llvm/test/CodeGen/PowerPC/i64_fp_round.ll
--- a/llvm/test/CodeGen/PowerPC/i64_fp_round.ll
+++ b/llvm/test/CodeGen/PowerPC/i64_fp_round.ll
@@ -19,7 +19,7 @@
 ; CHECK: addi [[REG2:[0-9]+]], [[REG1]], 1
 ; CHECK: cmpldi [[REG2]], 1
 ; CHECK: iselgt [[REG3:[0-9]+]], {{[0-9]+}}, 3
-; CHECK-NO-ISEL: rldicr [[REG2:[0-9]+]], {{[0-9]+}}, 0, 52
+; CHECK-NO-ISEL: clrrdi [[REG2:[0-9]+]], {{[0-9]+}}, 11
 ; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NO-ISEL: b [[SUCCESSOR:.LBB[0-9]+]]
 ; CHECK-NO-ISEL-NEXT: [[TRUE]]
diff --git a/llvm/test/CodeGen/PowerPC/jump-tables-collapse-rotate-remove-SrcMI.mir b/llvm/test/CodeGen/PowerPC/jump-tables-collapse-rotate-remove-SrcMI.mir
--- a/llvm/test/CodeGen/PowerPC/jump-tables-collapse-rotate-remove-SrcMI.mir
+++ b/llvm/test/CodeGen/PowerPC/jump-tables-collapse-rotate-remove-SrcMI.mir
@@ -46,7 +46,7 @@
 ...
 # CHECK-LABEL: test:
 # CHECK: # %bb.0: # %entry
-# CHECK-NEXT: 	rldic 3, 4, 2, 30
+# CHECK-NEXT: 	clrlsldi 3, 4, 32, 2
 # CHECK-NEXT: 	blr
 #
 # CHECK-PASS-NOT:     %2:g8rc = RLDICL killed %1, 0, 32
diff --git a/llvm/test/CodeGen/PowerPC/jump-tables-collapse-rotate.ll b/llvm/test/CodeGen/PowerPC/jump-tables-collapse-rotate.ll
--- a/llvm/test/CodeGen/PowerPC/jump-tables-collapse-rotate.ll
+++ b/llvm/test/CodeGen/PowerPC/jump-tables-collapse-rotate.ll
@@ -14,7 +14,7 @@
 ; CHECK-NEXT:    bgt cr0, .LBB0_3
 ; CHECK-NEXT:  # %bb.1: # %entry
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
-; CHECK-NEXT:    rldic r3, r3, 2, 30
+; CHECK-NEXT:    clrlsldi r3, r3, 32, 2
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
 ; CHECK-NEXT:    lwax r3, r3, r4
 ; CHECK-NEXT:    add r3, r3, r4
diff --git a/llvm/test/CodeGen/PowerPC/knowCRBitSpill.ll b/llvm/test/CodeGen/PowerPC/knowCRBitSpill.ll
--- a/llvm/test/CodeGen/PowerPC/knowCRBitSpill.ll
+++ b/llvm/test/CodeGen/PowerPC/knowCRBitSpill.ll
@@ -22,13 +22,13 @@
 ; CHECK:        # %bb.2:
 ; CHECK-DAG:    crnot [[CREG:.*]]*cr5+lt, eq
 ; CHECK-DAG:    mfocrf [[REG2:.*]], [[CREG]]
-; CHECK-DAG:    rlwinm [[REG2]], [[REG2]]
+; CHECK-DAG:    extlwi [[REG2]], [[REG2]]
 ; CHECK:        .LBB0_3:
 ; CHECK-NOT:    #UNENCODED_NOP
 ; CHECK:        lis [[REG1:.*]], -32768
 ; CHECK:        .LBB0_4:
 ; CHECK-NOT:    mfocrf [[REG2:.*]], [[CREG]]
-; CHECK-NOT:    rlwinm [[REG2]], [[REG2]]
+; CHECK-NOT:    extlwi [[REG2]], [[REG2]]
 ; CHECK:        stw [[REG1]]
 ; CHECK:        # %bb.5:
 
diff --git a/llvm/test/CodeGen/PowerPC/legalize-vaarg.ll b/llvm/test/CodeGen/PowerPC/legalize-vaarg.ll
--- a/llvm/test/CodeGen/PowerPC/legalize-vaarg.ll
+++ b/llvm/test/CodeGen/PowerPC/legalize-vaarg.ll
@@ -14,11 +14,11 @@
 ; BE-NEXT:    std 9, 96(1)
 ; BE-NEXT:    std 10, 104(1)
 ; BE-NEXT:    addi 3, 3, 15
-; BE-NEXT:    rldicr 3, 3, 0, 59
+; BE-NEXT:    clrrdi 3, 3, 4
 ; BE-NEXT:    addi 4, 3, 16
 ; BE-NEXT:    addi 5, 3, 31
 ; BE-NEXT:    std 4, -8(1)
-; BE-NEXT:    rldicr 4, 5, 0, 59
+; BE-NEXT:    clrrdi 4, 5, 4
 ; BE-NEXT:    lvx 2, 0, 3
 ; BE-NEXT:    addi 3, 4, 16
 ; BE-NEXT:    std 3, -8(1)
@@ -33,13 +33,13 @@
 ; LE-NEXT:    std 6, 56(1)
 ; LE-NEXT:    std 7, 64(1)
 ; LE-NEXT:    addi 3, 3, 15
-; LE-NEXT:    rldicr 3, 3, 0, 59
+; LE-NEXT:    clrrdi 3, 3, 4
 ; LE-NEXT:    std 8, 72(1)
 ; LE-NEXT:    std 9, 80(1)
 ; LE-NEXT:    std 10, 88(1)
 ; LE-NEXT:    addi 4, 3, 31
 ; LE-NEXT:    addi 5, 3, 16
-; LE-NEXT:    rldicr 4, 4, 0, 59
+; LE-NEXT:    clrrdi 4, 4, 4
 ; LE-NEXT:    std 5, -8(1)
 ; LE-NEXT:    addi 5, 4, 16
 ; LE-NEXT:    lvx 2, 0, 3
diff --git a/llvm/test/CodeGen/PowerPC/loop-instr-form-prepare.ll b/llvm/test/CodeGen/PowerPC/loop-instr-form-prepare.ll
--- a/llvm/test/CodeGen/PowerPC/loop-instr-form-prepare.ll
+++ b/llvm/test/CodeGen/PowerPC/loop-instr-form-prepare.ll
@@ -510,7 +510,7 @@
 ; CHECK-NEXT:  .LBB6_4: #
 ; CHECK-NEXT:    lbzu r0, 1(r5)
 ; CHECK-NEXT:    mulhwu r27, r0, r4
-; CHECK-NEXT:    rlwinm r26, r27, 0, 0, 30
+; CHECK-NEXT:    clrrwi r26, r27, 1
 ; CHECK-NEXT:    srwi r27, r27, 1
 ; CHECK-NEXT:    add r27, r27, r26
 ; CHECK-NEXT:    sub r0, r0, r27
diff --git a/llvm/test/CodeGen/PowerPC/machine-pre.ll b/llvm/test/CodeGen/PowerPC/machine-pre.ll
--- a/llvm/test/CodeGen/PowerPC/machine-pre.ll
+++ b/llvm/test/CodeGen/PowerPC/machine-pre.ll
@@ -123,8 +123,8 @@
 ; CHECK-P9-NEXT:    extsw r5, r5
 ; CHECK-P9-NEXT:    sub r3, r4, r3
 ; CHECK-P9-NEXT:    sub r4, r5, r4
-; CHECK-P9-NEXT:    rldicl r3, r3, 1, 63
-; CHECK-P9-NEXT:    rldicl r4, r4, 1, 63
+; CHECK-P9-NEXT:    srdi r3, r3, 63
+; CHECK-P9-NEXT:    srdi r4, r4, 63
 ; CHECK-P9-NEXT:    or r3, r3, r4
 ; CHECK-P9-NEXT:    b .LBB1_10
 ; CHECK-P9-NEXT:  .LBB1_9: # %cleanup20
diff --git a/llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll b/llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
--- a/llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
+++ b/llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
@@ -160,7 +160,7 @@
 ; CHECK-NEXT:    bl memcmp
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    cntlzw 3, 3
-; CHECK-NEXT:    rlwinm 3, 3, 27, 31, 31
+; CHECK-NEXT:    extrwi 3, 3, 1, 26
 ; CHECK-NEXT:    addi 1, 1, 32
 ; CHECK-NEXT:    ld 0, 16(1)
 ; CHECK-NEXT:    mtlr 0
diff --git a/llvm/test/CodeGen/PowerPC/memcmp-mergeexpand.ll b/llvm/test/CodeGen/PowerPC/memcmp-mergeexpand.ll
--- a/llvm/test/CodeGen/PowerPC/memcmp-mergeexpand.ll
+++ b/llvm/test/CodeGen/PowerPC/memcmp-mergeexpand.ll
@@ -12,7 +12,7 @@
 ; PPC64LE-NEXT:    ldx 4, 0, 4
 ; PPC64LE-NEXT:    xor 3, 3, 4
 ; PPC64LE-NEXT:    cntlzd 3, 3
-; PPC64LE-NEXT:    rldicl 3, 3, 58, 63
+; PPC64LE-NEXT:    extrdi 3, 3, 1, 57
 ; PPC64LE-NEXT:    blr
   %"struct.std::pair"* nocapture readonly dereferenceable(8) %a,
   %"struct.std::pair"* nocapture readonly dereferenceable(8) %b) local_unnamed_addr #0 {
diff --git a/llvm/test/CodeGen/PowerPC/memcmp.ll b/llvm/test/CodeGen/PowerPC/memcmp.ll
--- a/llvm/test/CodeGen/PowerPC/memcmp.ll
+++ b/llvm/test/CodeGen/PowerPC/memcmp.ll
@@ -28,8 +28,8 @@
 ; CHECK-NEXT:    lwbrx 4, 0, 4
 ; CHECK-NEXT:    sub 5, 4, 3
 ; CHECK-NEXT:    sub 3, 3, 4
-; CHECK-NEXT:    rldicl 4, 5, 1, 63
-; CHECK-NEXT:    rldicl 3, 3, 1, 63
+; CHECK-NEXT:    srdi 4, 5, 63
+; CHECK-NEXT:    srdi 3, 3, 63
 ; CHECK-NEXT:    sub 3, 4, 3
 ; CHECK-NEXT:    extsw 3, 3
 ; CHECK-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/optcmp.ll b/llvm/test/CodeGen/PowerPC/optcmp.ll
--- a/llvm/test/CodeGen/PowerPC/optcmp.ll
+++ b/llvm/test/CodeGen/PowerPC/optcmp.ll
@@ -204,7 +204,7 @@
 ; CHECK-NEXT:    addi 3, 4, -1
 ; CHECK-NEXT:    std 4, 0(5)
 ; CHECK-NEXT:    nor 3, 3, 4
-; CHECK-NEXT:    rldicl 3, 3, 1, 63
+; CHECK-NEXT:    srdi 3, 3, 63
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NO-ISEL-LABEL: foo2l:
@@ -213,7 +213,7 @@
 ; CHECK-NO-ISEL-NEXT:    addi 3, 4, -1
 ; CHECK-NO-ISEL-NEXT:    std 4, 0(5)
 ; CHECK-NO-ISEL-NEXT:    nor 3, 3, 4
-; CHECK-NO-ISEL-NEXT:    rldicl 3, 3, 1, 63
+; CHECK-NO-ISEL-NEXT:    srdi 3, 3, 63
 ; CHECK-NO-ISEL-NEXT:    blr
 entry:
   %shl = shl i64 %a, %b
@@ -289,11 +289,11 @@
 ; CHECK-NEXT:    ori 6, 6, 21845
 ; CHECK-NEXT:    lis 9, 13107
 ; CHECK-NEXT:    rotldi 8, 7, 63
-; CHECK-NEXT:    rldimi 6, 6, 32, 0
+; CHECK-NEXT:    insrdi 6, 6, 32, 0
 ; CHECK-NEXT:    and 6, 8, 6
 ; CHECK-NEXT:    ori 8, 9, 13107
 ; CHECK-NEXT:    sub 6, 7, 6
-; CHECK-NEXT:    rldimi 8, 8, 32, 0
+; CHECK-NEXT:    insrdi 8, 8, 32, 0
 ; CHECK-NEXT:    lis 9, 257
 ; CHECK-NEXT:    rotldi 7, 6, 62
 ; CHECK-NEXT:    and 6, 6, 8
@@ -302,13 +302,13 @@
 ; CHECK-NEXT:    lis 8, 3855
 ; CHECK-NEXT:    add 6, 6, 7
 ; CHECK-NEXT:    ori 7, 8, 3855
-; CHECK-NEXT:    rldicl 8, 6, 60, 4
-; CHECK-NEXT:    rldimi 7, 7, 32, 0
-; CHECK-NEXT:    rldimi 9, 9, 32, 0
+; CHECK-NEXT:    srdi 8, 6, 4
+; CHECK-NEXT:    insrdi 7, 7, 32, 0
+; CHECK-NEXT:    insrdi 9, 9, 32, 0
 ; CHECK-NEXT:    add 6, 6, 8
 ; CHECK-NEXT:    and 6, 6, 7
 ; CHECK-NEXT:    mulld 6, 6, 9
-; CHECK-NEXT:    rldicl. 6, 6, 8, 56
+; CHECK-NEXT:    srdi. 6, 6, 56
 ; CHECK-NEXT:    iselgt 3, 3, 4
 ; CHECK-NEXT:    std 6, 0(5)
 ; CHECK-NEXT:    blr
@@ -320,11 +320,11 @@
 ; CHECK-NO-ISEL-NEXT:    ori 6, 6, 21845
 ; CHECK-NO-ISEL-NEXT:    lis 9, 13107
 ; CHECK-NO-ISEL-NEXT:    rotldi 8, 7, 63
-; CHECK-NO-ISEL-NEXT:    rldimi 6, 6, 32, 0
+; CHECK-NO-ISEL-NEXT:    insrdi 6, 6, 32, 0
 ; CHECK-NO-ISEL-NEXT:    and 6, 8, 6
 ; CHECK-NO-ISEL-NEXT:    ori 8, 9, 13107
 ; CHECK-NO-ISEL-NEXT:    sub 6, 7, 6
-; CHECK-NO-ISEL-NEXT:    rldimi 8, 8, 32, 0
+; CHECK-NO-ISEL-NEXT:    insrdi 8, 8, 32, 0
 ; CHECK-NO-ISEL-NEXT:    lis 9, 257
 ; CHECK-NO-ISEL-NEXT:    rotldi 7, 6, 62
 ; CHECK-NO-ISEL-NEXT:    and 6, 6, 8
@@ -333,13 +333,13 @@
 ; CHECK-NO-ISEL-NEXT:    lis 8, 3855
 ; CHECK-NO-ISEL-NEXT:    add 6, 6, 7
 ; CHECK-NO-ISEL-NEXT:    ori 7, 8, 3855
-; CHECK-NO-ISEL-NEXT:    rldicl 8, 6, 60, 4
-; CHECK-NO-ISEL-NEXT:    rldimi 7, 7, 32, 0
-; CHECK-NO-ISEL-NEXT:    rldimi 9, 9, 32, 0
+; CHECK-NO-ISEL-NEXT:    srdi 8, 6, 4
+; CHECK-NO-ISEL-NEXT:    insrdi 7, 7, 32, 0
+; CHECK-NO-ISEL-NEXT:    insrdi 9, 9, 32, 0
 ; CHECK-NO-ISEL-NEXT:    add 6, 6, 8
 ; CHECK-NO-ISEL-NEXT:    and 6, 6, 7
 ; CHECK-NO-ISEL-NEXT:    mulld 6, 6, 9
-; CHECK-NO-ISEL-NEXT:    rldicl. 6, 6, 8, 56
+; CHECK-NO-ISEL-NEXT:    srdi. 6, 6, 56
 ; CHECK-NO-ISEL-NEXT:    bc 12, 1, .LBB10_2
 ; CHECK-NO-ISEL-NEXT:  # %bb.1: # %entry
 ; CHECK-NO-ISEL-NEXT:    ori 3, 4, 0
diff --git a/llvm/test/CodeGen/PowerPC/ori_imm32.ll b/llvm/test/CodeGen/PowerPC/ori_imm32.ll
--- a/llvm/test/CodeGen/PowerPC/ori_imm32.ll
+++ b/llvm/test/CodeGen/PowerPC/ori_imm32.ll
@@ -17,7 +17,7 @@
 ; CHECK-LABEL: ori_test_b:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    li 4, -1
-; CHECK-NEXT:    rldimi 3, 4, 32, 31
+; CHECK-NEXT:    insrdi 3, 4, 1, 31
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %a, 4294967296
diff --git a/llvm/test/CodeGen/PowerPC/ori_imm64.ll b/llvm/test/CodeGen/PowerPC/ori_imm64.ll
--- a/llvm/test/CodeGen/PowerPC/ori_imm64.ll
+++ b/llvm/test/CodeGen/PowerPC/ori_imm64.ll
@@ -16,7 +16,7 @@
 ; CHECK-LABEL: ori_test_2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    li 4, -1
-; CHECK-NEXT:    rldimi 3, 4, 29, 15
+; CHECK-NEXT:    insrdi 3, 4, 20, 15
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %a, 562949416550400 ; 0x1ffffe0000000
@@ -27,7 +27,7 @@
 ; CHECK-LABEL: ori_test_3:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    li 4, -1
-; CHECK-NEXT:    rldimi 3, 4, 3, 28
+; CHECK-NEXT:    insrdi 3, 4, 33, 28
 ; CHECK-NEXT:    blr
 entry:
   %or = or i64 %a, 68719476728 ; 0xffffffff8
diff --git a/llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll b/llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
--- a/llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
+++ b/llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
@@ -104,7 +104,7 @@
   ret i8 %vecext
 ; CHECK-LABEL: @getsc0
 ; CHECK: mfvsrd r3, v2
-; CHECK: rldicl r3, r3, 8, 56
+; CHECK: srdi r3, r3, 56
 ; CHECK: extsb r3, r3
 ; CHECK-LE-LABEL: @getsc0
 ; CHECK-LE: mffprd r3, f0
@@ -119,11 +119,11 @@
   ret i8 %vecext
 ; CHECK-LABEL: @getsc1
 ; CHECK: mfvsrd r3, v2
-; CHECK: rldicl r3, r3, 16, 56
+; CHECK: extrdi r3, r3, 8, 8
 ; CHECK: extsb r3, r3
 ; CHECK-LE-LABEL: @getsc1
 ; CHECK-LE: mffprd r3, f0
-; CHECK-LE: rldicl r3, r3, 56, 56
+; CHECK-LE: extrdi r3, r3, 8, 48
 ; CHECK-LE: extsb r3, r3
 }
 
@@ -134,11 +134,11 @@
   ret i8 %vecext
 ; CHECK-LABEL: @getsc2
 ; CHECK: mfvsrd r3, v2
-; CHECK: rldicl r3, r3, 24, 56
+; CHECK: extrdi r3, r3, 8, 16
 ; CHECK: extsb r3, r3
 ; CHECK-LE-LABEL: @getsc2
 ; CHECK-LE: mffprd r3, f0
-; CHECK-LE: rldicl r3, r3, 48, 56
+; CHECK-LE: extrdi r3, r3, 8, 40
 ; CHECK-LE: extsb r3, r3
 }
 
@@ -149,11 +149,11 @@
   ret i8 %vecext
 ; CHECK-LABEL: @getsc3
 ; CHECK: mfvsrd r3, v2
-; CHECK: rldicl r3, r3, 32, 56
+; CHECK: extrdi r3, r3, 8, 24
 ; CHECK: extsb r3, r3
 ; CHECK-LE-LABEL: @getsc3
 ; CHECK-LE: mffprd r3, f0
-; CHECK-LE: rldicl r3, r3, 40, 56
+; CHECK-LE: extrdi r3, r3, 8, 32
 ; CHECK-LE: extsb r3, r3
 }
 
@@ -164,11 +164,11 @@
   ret i8 %vecext
 ; CHECK-LABEL: @getsc4
 ; CHECK: mfvsrd r3, v2
-; CHECK: rldicl r3, r3, 40, 56
+; CHECK: extrdi r3, r3, 8, 32
 ; CHECK: extsb r3, r3
 ; CHECK-LE-LABEL: @getsc4
 ; CHECK-LE: mffprd r3, f0
-; CHECK-LE: rldicl r3, r3, 32, 56
+; CHECK-LE: extrdi r3, r3, 8, 24
 ; CHECK-LE: extsb r3, r3
 }
 
@@ -179,11 +179,11 @@
   ret i8 %vecext
 ; CHECK-LABEL: @getsc5
 ; CHECK: mfvsrd r3, v2
-; CHECK: rldicl r3, r3, 48, 56
+; CHECK: extrdi r3, r3, 8,  40
 ; CHECK: extsb r3, r3
 ; CHECK-LE-LABEL: @getsc5
 ; CHECK-LE: mffprd r3, f0
-; CHECK-LE: rldicl r3, r3, 24, 56
+; CHECK-LE: extrdi r3, r3, 8, 16
 ; CHECK-LE: extsb r3, r3
 }
 
@@ -194,11 +194,11 @@
   ret i8 %vecext
 ; CHECK-LABEL: @getsc6
 ; CHECK: mfvsrd r3, v2
-; CHECK: rldicl r3, r3, 56, 56
+; CHECK: extrdi r3, r3, 8, 48
 ; CHECK: extsb r3, r3
 ; CHECK-LE-LABEL: @getsc6
 ; CHECK-LE: mffprd r3, f0
-; CHECK-LE: rldicl r3, r3, 16, 56
+; CHECK-LE: extrdi r3, r3, 8, 8
 ; CHECK-LE: extsb r3, r3
 }
 
@@ -213,7 +213,7 @@
 ; CHECK: extsb r3, r3
 ; CHECK-LE-LABEL: @getsc7
 ; CHECK-LE: mffprd r3, f0
-; CHECK-LE: rldicl r3, r3, 8, 56
+; CHECK-LE: srdi r3, r3, 56
 ; CHECK-LE: extsb r3, r3
 }
 
@@ -224,7 +224,7 @@
   ret i8 %vecext
 ; CHECK-LABEL: @getsc8
 ; CHECK: mffprd r3, f0
-; CHECK: rldicl r3, r3, 8, 56
+; CHECK: srdi r3, r3, 56
 ; CHECK: extsb r3, r3
 ; CHECK-LE-LABEL: @getsc8
 ; CHECK-LE: mfvsrd r3, v2
@@ -239,11 +239,11 @@
   ret i8 %vecext
 ; CHECK-LABEL: @getsc9
 ; CHECK: mffprd r3, f0
-; CHECK: rldicl r3, r3, 16, 56
+; CHECK: extrdi r3, r3, 8, 8
 ; CHECK: extsb r3, r3
 ; CHECK-LE-LABEL: @getsc9
 ; CHECK-LE: mfvsrd r3, v2
-; CHECK-LE: rldicl r3, r3, 56, 56
+; CHECK-LE: extrdi r3, r3, 8, 48
 ; CHECK-LE: extsb r3, r3
 }
 
@@ -254,11 +254,11 @@
   ret i8 %vecext
 ; CHECK-LABEL: @getsc10
 ; CHECK: mffprd r3, f0
-; CHECK: rldicl r3, r3, 24, 56
+; CHECK: extrdi r3, r3, 8, 16
 ; CHECK: extsb r3, r3
 ; CHECK-LE-LABEL: @getsc10
 ; CHECK-LE: mfvsrd r3, v2
-; CHECK-LE: rldicl r3, r3, 48, 56
+; CHECK-LE: extrdi r3, r3, 8, 40
 ; CHECK-LE: extsb r3, r3
 }
 
@@ -269,11 +269,11 @@
   ret i8 %vecext
 ; CHECK-LABEL: @getsc11
 ; CHECK: mffprd r3, f0
-; CHECK: rldicl r3, r3, 32, 56
+; CHECK: extrdi r3, r3, 8, 24
 ; CHECK: extsb r3, r3
 ; CHECK-LE-LABEL: @getsc11
 ; CHECK-LE: mfvsrd r3, v2
-; CHECK-LE: rldicl r3, r3, 40, 56
+; CHECK-LE: extrdi r3, r3, 8, 32
 ; CHECK-LE: extsb r3, r3
 }
 
@@ -284,11 +284,11 @@
   ret i8 %vecext
 ; CHECK-LABEL: @getsc12
 ; CHECK: mffprd r3, f0
-; CHECK: rldicl r3, r3, 40, 56
+; CHECK: extrdi r3, r3, 8, 32
 ; CHECK: extsb r3, r3
 ; CHECK-LE-LABEL: @getsc12
 ; CHECK-LE: mfvsrd r3, v2
-; CHECK-LE: rldicl r3, r3, 32, 56
+; CHECK-LE: extrdi r3, r3, 8, 24
 ; CHECK-LE: extsb r3, r3
 }
 
@@ -299,11 +299,11 @@
   ret i8 %vecext
 ; CHECK-LABEL: @getsc13
 ; CHECK: mffprd r3, f0
-; CHECK: rldicl r3, r3, 48, 56
+; CHECK: extrdi r3, r3, 8, 40
 ; CHECK: extsb r3, r3
 ; CHECK-LE-LABEL: @getsc13
 ; CHECK-LE: mfvsrd r3, v2
-; CHECK-LE: rldicl r3, r3, 24, 56
+; CHECK-LE: extrdi r3, r3, 8, 16
 ; CHECK-LE: extsb r3, r3
 }
 
@@ -314,11 +314,11 @@
   ret i8 %vecext
 ; CHECK-LABEL: @getsc14
 ; CHECK: mffprd r3, f0
-; CHECK: rldicl r3, r3, 56, 56
+; CHECK: extrdi r3, r3, 8, 48
 ; CHECK: extsb r3, r3
 ; CHECK-LE-LABEL: @getsc14
 ; CHECK-LE: mfvsrd r3, v2
-; CHECK-LE: rldicl r3, r3, 16, 56
+; CHECK-LE: extrdi r3, r3, 8, 8
 ; CHECK-LE: extsb r3, r3
 }
 
@@ -333,7 +333,7 @@
 ; CHECK: extsb r3, r3
 ; CHECK-LE-LABEL: @getsc15
 ; CHECK-LE: mfvsrd r3, v2
-; CHECK-LE: rldicl r3, r3, 8, 56
+; CHECK-LE: srdi r3, r3, 56
 ; CHECK-LE: extsb r3, r3
 }
 
@@ -344,7 +344,7 @@
   ret i8 %vecext
 ; CHECK-LABEL: @getuc0
 ; CHECK: mfvsrd r3, v2
-; CHECK: rldicl r3, r3, 8, 56
+; CHECK: srdi r3, r3, 56
 ; CHECK-LE-LABEL: @getuc0
 ; CHECK-LE: mffprd r3, f0
 ; CHECK-LE: clrldi r3, r3, 56
@@ -357,10 +357,10 @@
   ret i8 %vecext
 ; CHECK-LABEL: @getuc1
 ; CHECK: mfvsrd r3, v2
-; CHECK: rldicl r3, r3, 16, 56
+; CHECK: extrdi r3, r3, 8, 8
 ; CHECK-LE-LABEL: @getuc1
 ; CHECK-LE: mffprd r3, f0
-; CHECK-LE: rldicl r3, r3, 56, 56
+; CHECK-LE: extrdi r3, r3, 8, 48
 }
 
 ; Function Attrs: norecurse nounwind readnone
@@ -370,10 +370,10 @@
   ret i8 %vecext
 ; CHECK-LABEL: @getuc2
 ; CHECK: mfvsrd r3, v2
-; CHECK: rldicl r3, r3, 24, 56
+; CHECK: extrdi r3, r3, 8, 16
 ; CHECK-LE-LABEL: @getuc2
 ; CHECK-LE: mffprd r3, f0
-; CHECK-LE: rldicl r3, r3, 48, 56
+; CHECK-LE: extrdi r3, r3, 8, 40
 }
 
 ; Function Attrs: norecurse nounwind readnone
@@ -383,10 +383,10 @@
   ret i8 %vecext
 ; CHECK-LABEL: @getuc3
 ; CHECK: mfvsrd r3, v2
-; CHECK: rldicl r3, r3, 32, 56
+; CHECK: extrdi r3, r3, 8, 24
 ; CHECK-LE-LABEL: @getuc3
 ; CHECK-LE: mffprd r3, f0
-; CHECK-LE: rldicl r3, r3, 40, 56
+; CHECK-LE: extrdi r3, r3, 8, 32
 }
 
 ; Function Attrs: norecurse nounwind readnone
@@ -396,10 +396,10 @@
   ret i8 %vecext
 ; CHECK-LABEL: @getuc4
 ; CHECK: mfvsrd r3, v2
-; CHECK: rldicl r3, r3, 40, 56
+; CHECK: extrdi r3, r3, 8, 32
 ; CHECK-LE-LABEL: @getuc4
 ; CHECK-LE: mffprd r3, f0
-; CHECK-LE: rldicl r3, r3, 32, 56
+; CHECK-LE: extrdi r3, r3, 8, 24
 }
 
 ; Function Attrs: norecurse nounwind readnone
@@ -409,10 +409,10 @@
   ret i8 %vecext
 ; CHECK-LABEL: @getuc5
 ; CHECK: mfvsrd r3, v2
-; CHECK: rldicl r3, r3, 48, 56
+; CHECK: extrdi r3, r3, 8, 40
 ; CHECK-LE-LABEL: @getuc5
 ; CHECK-LE: mffprd r3, f0
-; CHECK-LE: rldicl r3, r3, 24, 56
+; CHECK-LE: extrdi r3, r3, 8, 16
 }
 
 ; Function Attrs: norecurse nounwind readnone
@@ -422,10 +422,10 @@
   ret i8 %vecext
 ; CHECK-LABEL: @getuc6
 ; CHECK: mfvsrd r3, v2
-; CHECK: rldicl r3, r3, 56, 56
+; CHECK: extrdi r3, r3, 8, 48
 ; CHECK-LE-LABEL: @getuc6
 ; CHECK-LE: mffprd r3, f0
-; CHECK-LE: rldicl r3, r3, 16, 56
+; CHECK-LE: extrdi r3, r3, 8, 8
 }
 
 ; Function Attrs: norecurse nounwind readnone
@@ -438,7 +438,7 @@
 ; CHECK: clrldi   r3, r3, 56
 ; CHECK-LE-LABEL: @getuc7
 ; CHECK-LE: mffprd r3, f0
-; CHECK-LE: rldicl r3, r3, 8, 56
+; CHECK-LE: srdi r3, r3, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
@@ -448,7 +448,7 @@
   ret i8 %vecext
 ; CHECK-LABEL: @getuc8
 ; CHECK: mffprd r3, f0
-; CHECK: rldicl r3, r3, 8, 56
+; CHECK: srdi r3, r3, 56
 ; CHECK-LE-LABEL: @getuc8
 ; CHECK-LE: mfvsrd r3, v2
 ; CHECK-LE: clrldi r3, r3, 56
@@ -461,10 +461,10 @@
   ret i8 %vecext
 ; CHECK-LABEL: @getuc9
 ; CHECK: mffprd r3, f0
-; CHECK: rldicl r3, r3, 16, 56
+; CHECK: extrdi r3, r3, 8, 8
 ; CHECK-LE-LABEL: @getuc9
 ; CHECK-LE: mfvsrd r3, v2
-; CHECK-LE: rldicl r3, r3, 56, 56
+; CHECK-LE: extrdi r3, r3, 8, 48
 }
 
 ; Function Attrs: norecurse nounwind readnone
@@ -474,10 +474,10 @@
   ret i8 %vecext
 ; CHECK-LABEL: @getuc10
 ; CHECK: mffprd r3, f0
-; CHECK: rldicl r3, r3, 24, 56
+; CHECK: extrdi r3, r3, 8, 16
 ; CHECK-LE-LABEL: @getuc10
 ; CHECK-LE: mfvsrd r3, v2
-; CHECK-LE: rldicl r3, r3, 48, 56
+; CHECK-LE: extrdi r3, r3, 8, 40
 }
 
 ; Function Attrs: norecurse nounwind readnone
@@ -487,10 +487,10 @@
   ret i8 %vecext
 ; CHECK-LABEL: @getuc11
 ; CHECK: mffprd r3, f0
-; CHECK: rldicl r3, r3, 32, 56
+; CHECK: extrdi r3, r3, 8, 24
 ; CHECK-LE-LABEL: @getuc11
 ; CHECK-LE: mfvsrd r3, v2
-; CHECK-LE: rldicl r3, r3, 40, 56
+; CHECK-LE: extrdi r3, r3, 8, 32
 }
 
 ; Function Attrs: norecurse nounwind readnone
@@ -500,10 +500,10 @@
   ret i8 %vecext
 ; CHECK-LABEL: @getuc12
 ; CHECK: mffprd r3, f0
-; CHECK: rldicl r3, r3, 40, 56
+; CHECK: extrdi r3, r3, 8, 32
 ; CHECK-LE-LABEL: @getuc12
 ; CHECK-LE: mfvsrd r3, v2
-; CHECK-LE: rldicl r3, r3, 32, 56
+; CHECK-LE: extrdi r3, r3, 8, 24
 }
 
 ; Function Attrs: norecurse nounwind readnone
@@ -513,10 +513,10 @@
   ret i8 %vecext
 ; CHECK-LABEL: @getuc13
 ; CHECK: mffprd r3, f0
-; CHECK: rldicl r3, r3, 48, 56
+; CHECK: extrdi r3, r3, 8, 40
 ; CHECK-LE-LABEL: @getuc13
 ; CHECK-LE: mfvsrd r3, v2
-; CHECK-LE: rldicl r3, r3, 24, 56
+; CHECK-LE: extrdi r3, r3, 8, 16
 }
 
 ; Function Attrs: norecurse nounwind readnone
@@ -526,10 +526,10 @@
   ret i8 %vecext
 ; CHECK-LABEL: @getuc14
 ; CHECK: mffprd r3, f0
-; CHECK: rldicl r3, r3, 56, 56
+; CHECK: extrdi r3, r3, 8, 48
 ; CHECK-LE-LABEL: @getuc14
 ; CHECK-LE: mfvsrd r3, v2
-; CHECK-LE: rldicl r3, r3, 16, 56
+; CHECK-LE: extrdi r3, r3, 8, 8
 }
 
 ; Function Attrs: norecurse nounwind readnone
@@ -542,7 +542,7 @@
 ; CHECK: clrldi   r3, r3, 56
 ; CHECK-LE-LABEL: @getuc15
 ; CHECK-LE: mfvsrd r3, v2
-; CHECK-LE: rldicl r3, r3, 8, 56
+; CHECK-LE: srdi r3, r3, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone
@@ -608,7 +608,7 @@
   ret i16 %vecext
 ; CHECK-LABEL: @getss0
 ; CHECK: mfvsrd r3, v2
-; CHECK: rldicl r3, r3, 16, 48
+; CHECK: srdi r3, r3, 48
 ; CHECK: extsh r3, r3
 ; CHECK-LE-LABEL: @getss0
 ; CHECK-LE: mffprd r3, f0
@@ -623,11 +623,11 @@
   ret i16 %vecext
 ; CHECK-LABEL: @getss1
 ; CHECK: mfvsrd r3, v2
-; CHECK: rldicl r3, r3, 32, 48
+; CHECK: extrdi r3, r3, 16, 16
 ; CHECK: extsh r3, r3
 ; CHECK-LE-LABEL: @getss1
 ; CHECK-LE: mffprd r3, f0
-; CHECK-LE: rldicl r3, r3, 48, 48
+; CHECK-LE: extrdi r3, r3, 16, 32
 ; CHECK-LE: extsh r3, r3
 }
 
@@ -638,11 +638,11 @@
   ret i16 %vecext
 ; CHECK-LABEL: @getss2
 ; CHECK: mfvsrd r3, v2
-; CHECK: rldicl r3, r3, 48, 48
+; CHECK: extrdi r3, r3, 16, 32
 ; CHECK: extsh r3, r3
 ; CHECK-LE-LABEL: @getss2
 ; CHECK-LE: mffprd r3, f0
-; CHECK-LE: rldicl r3, r3, 32, 48
+; CHECK-LE: extrdi r3, r3, 16, 16
 ; CHECK-LE: extsh r3, r3
 }
 
@@ -657,7 +657,7 @@
 ; CHECK: extsh r3, r3
 ; CHECK-LE-LABEL: @getss3
 ; CHECK-LE: mffprd r3, f0
-; CHECK-LE: rldicl r3, r3, 16, 48
+; CHECK-LE: srdi r3, r3, 48
 ; CHECK-LE: extsh r3, r3
 }
 
@@ -668,7 +668,7 @@
   ret i16 %vecext
 ; CHECK-LABEL: @getss4
 ; CHECK: mffprd r3, f0
-; CHECK: rldicl r3, r3, 16, 48
+; CHECK: srdi r3, r3, 48
 ; CHECK: extsh r3, r3
 ; CHECK-LE-LABEL: @getss4
 ; CHECK-LE: mfvsrd r3, v2
@@ -683,11 +683,11 @@
   ret i16 %vecext
 ; CHECK-LABEL: @getss5
 ; CHECK: mffprd r3, f0
-; CHECK: rldicl r3, r3, 32, 48
+; CHECK: extrdi r3, r3, 16, 16
 ; CHECK: extsh r3, r3
 ; CHECK-LE-LABEL: @getss5
 ; CHECK-LE: mfvsrd r3, v2
-; CHECK-LE: rldicl r3, r3, 48, 48
+; CHECK-LE: extrdi r3, r3, 16, 32
 ; CHECK-LE: extsh r3, r3
 }
 
@@ -698,11 +698,11 @@
   ret i16 %vecext
 ; CHECK-LABEL: @getss6
 ; CHECK: mffprd r3, f0
-; CHECK: rldicl r3, r3, 48, 48
+; CHECK: extrdi r3, r3, 16, 32
 ; CHECK: extsh r3, r3
 ; CHECK-LE-LABEL: @getss6
 ; CHECK-LE: mfvsrd r3, v2
-; CHECK-LE: rldicl r3, r3, 32, 48
+; CHECK-LE: extrdi r3, r3, 16, 16
 ; CHECK-LE: extsh r3, r3
 }
 
@@ -717,7 +717,7 @@
 ; CHECK: extsh r3, r3
 ; CHECK-LE-LABEL: @getss7
 ; CHECK-LE: mfvsrd r3, v2
-; CHECK-LE: rldicl r3, r3, 16, 48
+; CHECK-LE: srdi r3, r3, 48
 ; CHECK-LE: extsh r3, r3
 }
 
@@ -728,7 +728,7 @@
   ret i16 %vecext
 ; CHECK-LABEL: @getus0
 ; CHECK: mfvsrd r3, v2
-; CHECK: rldicl r3, r3, 16, 48
+; CHECK: srdi r3, r3, 48
 ; CHECK-LE-LABEL: @getus0
 ; CHECK-LE: mffprd r3, f0
 ; CHECK-LE: clrldi r3, r3, 48
@@ -741,10 +741,10 @@
   ret i16 %vecext
 ; CHECK-LABEL: @getus1
 ; CHECK: mfvsrd r3, v2
-; CHECK: rldicl r3, r3, 32, 48
+; CHECK: extrdi r3, r3, 16, 16
 ; CHECK-LE-LABEL: @getus1
 ; CHECK-LE: mffprd r3, f0
-; CHECK-LE: rldicl r3, r3, 48, 48
+; CHECK-LE: extrdi r3, r3, 16, 32
 }
 
 ; Function Attrs: norecurse nounwind readnone
@@ -754,10 +754,10 @@
   ret i16 %vecext
 ; CHECK-LABEL: @getus2
 ; CHECK: mfvsrd r3, v2
-; CHECK: rldicl r3, r3, 48, 48
+; CHECK: extrdi r3, r3, 16, 32
 ; CHECK-LE-LABEL: @getus2
 ; CHECK-LE: mffprd r3, f0
-; CHECK-LE: rldicl r3, r3, 32, 48
+; CHECK-LE: extrdi r3, r3, 16, 16
 }
 
 ; Function Attrs: norecurse nounwind readnone
@@ -770,7 +770,7 @@
 ; CHECK: clrldi   r3, r3, 48
 ; CHECK-LE-LABEL: @getus3
 ; CHECK-LE: mffprd r3, f0
-; CHECK-LE: rldicl r3, r3, 16, 48
+; CHECK-LE: srdi r3, r3, 48
 }
 
 ; Function Attrs: norecurse nounwind readnone
@@ -780,7 +780,7 @@
   ret i16 %vecext
 ; CHECK-LABEL: @getus4
 ; CHECK: mffprd r3, f0
-; CHECK: rldicl r3, r3, 16, 48
+; CHECK: srdi r3, r3, 48
 ; CHECK-LE-LABEL: @getus4
 ; CHECK-LE: mfvsrd r3, v2
 ; CHECK-LE: clrldi r3, r3, 48
@@ -793,10 +793,10 @@
   ret i16 %vecext
 ; CHECK-LABEL: @getus5
 ; CHECK: mffprd r3, f0
-; CHECK: rldicl r3, r3, 32, 48
+; CHECK: extrdi r3, r3, 16, 16
 ; CHECK-LE-LABEL: @getus5
 ; CHECK-LE: mfvsrd r3, v2
-; CHECK-LE: rldicl r3, r3, 48, 48
+; CHECK-LE: extrdi r3, r3, 16, 32
 }
 
 ; Function Attrs: norecurse nounwind readnone
@@ -806,10 +806,10 @@
   ret i16 %vecext
 ; CHECK-LABEL: @getus6
 ; CHECK: mffprd r3, f0
-; CHECK: rldicl r3, r3, 48, 48
+; CHECK: extrdi r3, r3, 16, 32
 ; CHECK-LE-LABEL: @getus6
 ; CHECK-LE: mfvsrd r3, v2
-; CHECK-LE: rldicl r3, r3, 32, 48
+; CHECK-LE: extrdi r3, r3, 16, 16
 }
 
 ; Function Attrs: norecurse nounwind readnone
@@ -822,7 +822,7 @@
 ; CHECK: clrldi   r3, r3, 48
 ; CHECK-LE-LABEL: @getus7
 ; CHECK-LE: mfvsrd r3, v2
-; CHECK-LE: rldicl r3, r3, 16, 48
+; CHECK-LE: srdi r3, r3, 48
 }
 
 ; Function Attrs: norecurse nounwind readnone
diff --git a/llvm/test/CodeGen/PowerPC/pcrel-jump-table.ll b/llvm/test/CodeGen/PowerPC/pcrel-jump-table.ll
--- a/llvm/test/CodeGen/PowerPC/pcrel-jump-table.ll
+++ b/llvm/test/CodeGen/PowerPC/pcrel-jump-table.ll
@@ -12,7 +12,7 @@
 define dso_local signext i32 @jumptable(i32 signext %param) {
 ; CHECK-R-LABEL: jumptable:
 ; CHECK-R:       # %bb.1: # %entry
-; CHECK-R-NEXT:    rldic r4, r4
+; CHECK-R-NEXT:    clrlsldi r4, r4, 32, 2
 ; CHECK-R-NEXT:    paddi r5, 0, .LJTI0_0@PCREL, 1
 ; CHECK-R-NEXT:    lwax r4, r4, r5
 ; CHECK-R-NEXT:    add r4, r4, r5
@@ -20,7 +20,7 @@
 ; CHECK-R-NEXT:    bctr
 ; CHECK-A-LABEL: jumptable:
 ; CHECK-A:       # %bb.1: # %entry
-; CHECK-A-NEXT:    rldic r4, r4
+; CHECK-A-NEXT:    clrlsldi r4, r4, 32, 3
 ; CHECK-A-NEXT:    paddi r5, 0, .LJTI0_0@PCREL, 1
 ; CHECK-A-NEXT:    ldx r4, r4, r5
 ; CHECK-A-NEXT:    mtctr r4
diff --git a/llvm/test/CodeGen/PowerPC/popcnt-zext.ll b/llvm/test/CodeGen/PowerPC/popcnt-zext.ll
--- a/llvm/test/CodeGen/PowerPC/popcnt-zext.ll
+++ b/llvm/test/CodeGen/PowerPC/popcnt-zext.ll
@@ -67,7 +67,7 @@
 ; SLOW-NEXT:    and 3, 3, 5
 ; SLOW-NEXT:    ori 4, 4, 257
 ; SLOW-NEXT:    mullw 3, 3, 4
-; SLOW-NEXT:    rlwinm 3, 3, 8, 24, 31
+; SLOW-NEXT:    srwi 3, 3, 24
 ; SLOW-NEXT:    blr
   %pop = tail call i8 @llvm.ctpop.i8(i8 %x)
   %z = zext i8 %pop to i16
@@ -139,7 +139,7 @@
 ; SLOW-NEXT:    and 3, 3, 5
 ; SLOW-NEXT:    ori 4, 4, 257
 ; SLOW-NEXT:    mullw 3, 3, 4
-; SLOW-NEXT:    rlwinm 3, 3, 8, 24, 31
+; SLOW-NEXT:    srwi 3, 3, 24
 ; SLOW-NEXT:    blr
   %pop = tail call i8 @llvm.ctpop.i8(i8 %x)
   %z = zext i8 %pop to i32
@@ -211,7 +211,7 @@
 ; SLOW-NEXT:    and 3, 3, 5
 ; SLOW-NEXT:    ori 4, 4, 257
 ; SLOW-NEXT:    mullw 3, 3, 4
-; SLOW-NEXT:    rlwinm 3, 3, 8, 24, 31
+; SLOW-NEXT:    srwi 3, 3, 24
 ; SLOW-NEXT:    blr
   %pop = tail call i16 @llvm.ctpop.i16(i16 %x)
   %z = zext i16 %pop to i32
@@ -234,23 +234,23 @@
 ; SLOW-NEXT:    ori 4, 4, 13107
 ; SLOW-NEXT:    or 5, 5, 6
 ; SLOW-NEXT:    clrldi 3, 3, 32
-; SLOW-NEXT:    rldimi 4, 4, 32, 0
+; SLOW-NEXT:    insrdi 4, 4, 32, 0
 ; SLOW-NEXT:    sub 3, 3, 5
 ; SLOW-NEXT:    and 5, 3, 4
 ; SLOW-NEXT:    rotldi 3, 3, 62
 ; SLOW-NEXT:    and 3, 3, 4
 ; SLOW-NEXT:    add 3, 5, 3
 ; SLOW-NEXT:    lis 4, 3855
-; SLOW-NEXT:    rldicl 5, 3, 60, 4
+; SLOW-NEXT:    srdi 5, 3, 4
 ; SLOW-NEXT:    ori 4, 4, 3855
 ; SLOW-NEXT:    add 3, 3, 5
 ; SLOW-NEXT:    lis 5, 257
-; SLOW-NEXT:    rldimi 4, 4, 32, 0
+; SLOW-NEXT:    insrdi 4, 4, 32, 0
 ; SLOW-NEXT:    ori 5, 5, 257
 ; SLOW-NEXT:    and 3, 3, 4
-; SLOW-NEXT:    rldimi 5, 5, 32, 0
+; SLOW-NEXT:    insrdi 5, 5, 32, 0
 ; SLOW-NEXT:    mulld 3, 3, 5
-; SLOW-NEXT:    rldicl 3, 3, 8, 56
+; SLOW-NEXT:    srdi 3, 3, 56
 ; SLOW-NEXT:    blr
   %z = zext i32 %x to i64
   %pop = tail call i64 @llvm.ctpop.i64(i64 %z)
@@ -287,7 +287,7 @@
 ; SLOW-NEXT:    and 3, 3, 5
 ; SLOW-NEXT:    ori 4, 4, 257
 ; SLOW-NEXT:    mullw 3, 3, 4
-; SLOW-NEXT:    rlwinm 3, 3, 8, 24, 31
+; SLOW-NEXT:    srwi 3, 3, 24
 ; SLOW-NEXT:    blr
   %pop = tail call i32 @llvm.ctpop.i32(i32 %x)
   %z = zext i32 %pop to i64
diff --git a/llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll b/llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll
--- a/llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll
@@ -130,7 +130,7 @@
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setb5
 ; CHECK-PWR8-DAG: sradi
-; CHECK-PWR8-DAG: rldicl
+; CHECK-PWR8-DAG: srdi
 ; CHECK-PWR8-DAG: li
 ; CHECK-PWR8-DAG: cmpd
 ; CHECK-PWR8-DAG: subc
@@ -160,7 +160,7 @@
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setb6
 ; CHECK-PWR8-DAG: sradi
-; CHECK-PWR8-DAG: rldicl
+; CHECK-PWR8-DAG: srdi
 ; CHECK-PWR8-DAG: li
 ; CHECK-PWR8-DAG: cmpd
 ; CHECK-PWR8-DAG: subc
@@ -190,7 +190,7 @@
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setb7
 ; CHECK-PWR8-DAG: sradi
-; CHECK-PWR8-DAG: rldicl
+; CHECK-PWR8-DAG: srdi
 ; CHECK-PWR8-DAG: li
 ; CHECK-PWR8-DAG: cmpd
 ; CHECK-PWR8-DAG: subc
@@ -220,7 +220,7 @@
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setb8
 ; CHECK-PWR8-DAG: sradi
-; CHECK-PWR8-DAG: rldicl
+; CHECK-PWR8-DAG: srdi
 ; CHECK-PWR8-DAG: li
 ; CHECK-PWR8-DAG: cmpd
 ; CHECK-PWR8-DAG: subc
@@ -355,7 +355,7 @@
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setb13
 ; CHECK-PWR8-DAG: sradi
-; CHECK-PWR8-DAG: rldicl
+; CHECK-PWR8-DAG: srdi
 ; CHECK-PWR8-DAG: li
 ; CHECK-PWR8-DAG: cmpd
 ; CHECK-PWR8-DAG: subc
@@ -387,7 +387,7 @@
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setb14
 ; CHECK-PWR8-DAG: sradi
-; CHECK-PWR8-DAG: rldicl
+; CHECK-PWR8-DAG: srdi
 ; CHECK-PWR8-DAG: li
 ; CHECK-PWR8-DAG: cmpd
 ; CHECK-PWR8-DAG: subc
@@ -419,7 +419,7 @@
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setb15
 ; CHECK-PWR8-DAG: sradi
-; CHECK-PWR8-DAG: rldicl
+; CHECK-PWR8-DAG: srdi
 ; CHECK-PWR8-DAG: li
 ; CHECK-PWR8-DAG: cmpd
 ; CHECK-PWR8-DAG: subc
@@ -451,7 +451,7 @@
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setb16
 ; CHECK-PWR8-DAG: sradi
-; CHECK-PWR8-DAG: rldicl
+; CHECK-PWR8-DAG: srdi
 ; CHECK-PWR8-DAG: li
 ; CHECK-PWR8-DAG: cmpd
 ; CHECK-PWR8-DAG: subc
@@ -935,7 +935,7 @@
 ; CHECK-PWR8-DAG: extsw
 ; CHECK-PWR8-DAG: extsw
 ; CHECK-PWR8-DAG: cmpw
-; CHECK-PWR8-DAG: rldicl
+; CHECK-PWR8-DAG: srdi
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
@@ -963,7 +963,7 @@
 ; CHECK-PWR8-DAG: extsw
 ; CHECK-PWR8-DAG: extsw
 ; CHECK-PWR8-DAG: cmpw
-; CHECK-PWR8-DAG: rldicl
+; CHECK-PWR8-DAG: srdi
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
@@ -995,7 +995,7 @@
 ; CHECK-PWR8-DAG: extsw
 ; CHECK-PWR8-DAG: extsw
 ; CHECK-PWR8-DAG: cmpw
-; CHECK-PWR8-DAG: rldicl
+; CHECK-PWR8-DAG: srdi
 ; CHECK-PWR8: isel
 ; CHECK-PWR8: blr
 }
@@ -1151,7 +1151,7 @@
 ; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setbuh
-; CHECK-PWR8: clrlwi
+; CHECK-PWR8: clrlwi 
 ; CHECK-PWR8: clrlwi
 ; CHECK-PWR8-DAG: cmplw
 ; CHECK-PWR8-DAG: cntlzw
@@ -1181,7 +1181,7 @@
 ; CHECK-NOT: isel
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: setbuc
-; CHECK-PWR8: clrlwi
+; CHECK-PWR8: clrlwi 
 ; CHECK-PWR8: clrlwi
 ; CHECK-PWR8-DAG: clrldi
 ; CHECK-PWR8-DAG: clrldi
diff --git a/llvm/test/CodeGen/PowerPC/ppc64-patchpoint.ll b/llvm/test/CodeGen/PowerPC/ppc64-patchpoint.ll
--- a/llvm/test/CodeGen/PowerPC/ppc64-patchpoint.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc64-patchpoint.ll
@@ -12,7 +12,7 @@
 ; CHECK-LABEL: trivial_patchpoint_codegen:
 
 ; CHECK: li 12, -8531
-; CHECK-NEXT: rldic 12, 12, 32, 16
+; CHECK-NEXT: clrlsldi 12, 12, 48, 32
 ; CHECK-NEXT: oris 12, 12, 48879
 ; CHECK-NEXT: ori 12, 12, 51966
 ; CHECK-LE-NEXT: std 2, 24(1)
@@ -25,7 +25,7 @@
 ; CHECK-BE-NEXT: ld 2, 40(1)
 
 ; CHECK: li 12, -8531
-; CHECK-NEXT: rldic 12, 12, 32, 16
+; CHECK-NEXT: clrlsldi 12, 12, 48, 32
 ; CHECK-NEXT: oris 12, 12, 48879
 ; CHECK-NEXT: ori 12, 12, 51967
 ; CHECK-LE-NEXT: std 2, 24(1)
diff --git a/llvm/test/CodeGen/PowerPC/ppc64le-aggregates.ll b/llvm/test/CodeGen/PowerPC/ppc64le-aggregates.ll
--- a/llvm/test/CodeGen/PowerPC/ppc64le-aggregates.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc64le-aggregates.ll
@@ -216,7 +216,7 @@
   ret float %b.extract
 }
 ; CHECK-LABEL: @callee1
-; CHECK: rldicl [[REG:[0-9]+]], 10, 32, 32
+; CHECK: srdi [[REG:[0-9]+]], 10, 32
 ; CHECK: stw [[REG]], [[OFF:.*]](1)
 ; CHECK: lfs 1, [[OFF]](1)
 ; CHECK: blr
@@ -240,8 +240,8 @@
 ; CHECK-DAG: lwz [[REG1:[0-9]+]], [[OFF1]](1)
 ; CHECK-DAG: lwz 10, [[OFF2]](1)
 ; CHECK-DAG: lwz [[REG3:[0-9]+]], [[OFF3]](1)
-; CHECK-DAG: rldimi 9, [[REG1]], 32, 0
-; CHECK-DAG: rldimi 10, [[REG3]], 32, 0
+; CHECK-DAG: insrdi 9, [[REG1]], 32, 0
+; CHECK-DAG: insrdi 10, [[REG3]], 32, 0
 ; CHECK: bl test1
 
 declare void @test1([8 x float], [8 x float])
@@ -252,7 +252,7 @@
   ret float %c.extract
 }
 ; CHECK-LABEL: @callee2
-; CHECK: rldicl [[REG:[0-9]+]], 10, 32, 32
+; CHECK: srdi [[REG:[0-9]+]], 10, 32
 ; CHECK: stw [[REG]], [[OFF:.*]](1)
 ; CHECK: lfs 1, [[OFF]](1)
 ; CHECK: blr
diff --git a/llvm/test/CodeGen/PowerPC/pr30640.ll b/llvm/test/CodeGen/PowerPC/pr30640.ll
--- a/llvm/test/CodeGen/PowerPC/pr30640.ll
+++ b/llvm/test/CodeGen/PowerPC/pr30640.ll
@@ -6,6 +6,6 @@
 
 ; CHECK: lis [[REG1:[0-9]+]], -12851
 ; CHECK: ori [[REG2:[0-9]+]], [[REG1]], 52685
-; CHECK: rldimi 3, 3, 32, 0
+; CHECK: insrdi 3, 3, 32, 0
 }
 
diff --git a/llvm/test/CodeGen/PowerPC/pr32140.ll b/llvm/test/CodeGen/PowerPC/pr32140.ll
--- a/llvm/test/CodeGen/PowerPC/pr32140.ll
+++ b/llvm/test/CodeGen/PowerPC/pr32140.ll
@@ -23,7 +23,7 @@
 ; CHECK-LE-NEXT:    addis 4, 2, bi@toc@ha
 ; CHECK-LE-NEXT:    lwa 3, ai@toc@l(3)
 ; CHECK-LE-NEXT:    addi 4, 4, bi@toc@l
-; CHECK-LE-NEXT:    rldicl 3, 3, 32, 32
+; CHECK-LE-NEXT:    srdi 3, 3, 32
 ; CHECK-LE-NEXT:    stwbrx 3, 0, 4
 ; CHECK-LE-NEXT:    blr
 ;
@@ -34,7 +34,7 @@
 ; CHECK-BE-NEXT:    ld 3, .LC0@toc@l(3)
 ; CHECK-BE-NEXT:    ld 4, .LC1@toc@l(4)
 ; CHECK-BE-NEXT:    lwa 3, 0(3)
-; CHECK-BE-NEXT:    rldicl 3, 3, 32, 32
+; CHECK-BE-NEXT:    srdi 3, 3, 32
 ; CHECK-BE-NEXT:    stwbrx 3, 0, 4
 ; CHECK-BE-NEXT:    blr
 entry:
@@ -101,7 +101,7 @@
 ; CHECK-LE-NEXT:    addis 4, 2, bs@toc@ha
 ; CHECK-LE-NEXT:    lha 3, as@toc@l(3)
 ; CHECK-LE-NEXT:    addi 4, 4, bs@toc@l
-; CHECK-LE-NEXT:    rldicl 3, 3, 16, 48
+; CHECK-LE-NEXT:    srdi 3, 3, 48
 ; CHECK-LE-NEXT:    sthbrx 3, 0, 4
 ; CHECK-LE-NEXT:    blr
 ;
@@ -112,7 +112,7 @@
 ; CHECK-BE-NEXT:    ld 3, .LC2@toc@l(3)
 ; CHECK-BE-NEXT:    ld 4, .LC3@toc@l(4)
 ; CHECK-BE-NEXT:    lha 3, 0(3)
-; CHECK-BE-NEXT:    rldicl 3, 3, 16, 48
+; CHECK-BE-NEXT:    srdi 3, 3, 48
 ; CHECK-BE-NEXT:    sthbrx 3, 0, 4
 ; CHECK-BE-NEXT:    blr
 entry:
diff --git a/llvm/test/CodeGen/PowerPC/pr33093.ll b/llvm/test/CodeGen/PowerPC/pr33093.ll
--- a/llvm/test/CodeGen/PowerPC/pr33093.ll
+++ b/llvm/test/CodeGen/PowerPC/pr33093.ll
@@ -34,7 +34,7 @@
 ; CHECK-NEXT:    or 3, 3, 4
 ; CHECK-NEXT:    rotlwi 4, 3, 24
 ; CHECK-NEXT:    rlwimi 4, 3, 8, 8, 15
-; CHECK-NEXT:    rlwimi 4, 3, 8, 24, 31
+; CHECK-NEXT:    inslwi 4, 3, 8, 24
 ; CHECK-NEXT:    rldicl 3, 4, 0, 32
 ; CHECK-NEXT:    clrldi 3, 3, 32
 ; CHECK-NEXT:    blr
@@ -82,7 +82,7 @@
 ; CHECK-NEXT:    oris 4, 4, 43690
 ; CHECK-NEXT:    oris 5, 5, 21845
 ; CHECK-NEXT:    sldi 6, 3, 1
-; CHECK-NEXT:    rldicl 3, 3, 63, 1
+; CHECK-NEXT:    srdi 3, 3, 1
 ; CHECK-NEXT:    ori 4, 4, 43690
 ; CHECK-NEXT:    ori 5, 5, 21845
 ; CHECK-NEXT:    sldi 7, 7, 32
@@ -99,7 +99,7 @@
 ; CHECK-NEXT:    ori 7, 7, 13107
 ; CHECK-NEXT:    ori 4, 4, 3855
 ; CHECK-NEXT:    sldi 8, 3, 2
-; CHECK-NEXT:    rldicl 3, 3, 62, 2
+; CHECK-NEXT:    srdi 3, 3, 2
 ; CHECK-NEXT:    and 6, 8, 6
 ; CHECK-NEXT:    and 3, 3, 7
 ; CHECK-NEXT:    sldi 5, 5, 32
@@ -110,17 +110,17 @@
 ; CHECK-NEXT:    sldi 6, 3, 4
 ; CHECK-NEXT:    ori 5, 5, 61680
 ; CHECK-NEXT:    ori 4, 4, 3855
-; CHECK-NEXT:    rldicl 3, 3, 60, 4
+; CHECK-NEXT:    srdi 3, 3, 4
 ; CHECK-NEXT:    and 5, 6, 5
 ; CHECK-NEXT:    and 3, 3, 4
 ; CHECK-NEXT:    or 3, 3, 5
-; CHECK-NEXT:    rldicl 4, 3, 32, 32
+; CHECK-NEXT:    srdi 4, 3, 32
 ; CHECK-NEXT:    rotlwi 5, 3, 24
 ; CHECK-NEXT:    rotlwi 6, 4, 24
 ; CHECK-NEXT:    rlwimi 5, 3, 8, 8, 15
-; CHECK-NEXT:    rlwimi 5, 3, 8, 24, 31
+; CHECK-NEXT:    inslwi 5, 3, 8, 24
 ; CHECK-NEXT:    rlwimi 6, 4, 8, 8, 15
-; CHECK-NEXT:    rlwimi 6, 4, 8, 24, 31
+; CHECK-NEXT:    inslwi 6, 4, 8, 24
 ; CHECK-NEXT:    sldi 3, 5, 32
 ; CHECK-NEXT:    or 3, 3, 6
 ; CHECK-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/pr41088.ll b/llvm/test/CodeGen/PowerPC/pr41088.ll
--- a/llvm/test/CodeGen/PowerPC/pr41088.ll
+++ b/llvm/test/CodeGen/PowerPC/pr41088.ll
@@ -50,7 +50,7 @@
 ; CHECK-NEXT:  # %bb.1: # %bb9
 ; CHECK-NEXT:    bl test5
 ; CHECK-NEXT:    nop
-; CHECK-NEXT:    rlwinm r3, r3, 8, 16, 23
+; CHECK-NEXT:    clrlslwi r3, r3, 24, 8
 ; CHECK-NEXT:  # %bb.2: # %bb12
 ; CHECK-NEXT:    clrldi r4, r3, 32
 ; CHECK-NEXT:    bl test3
diff --git a/llvm/test/CodeGen/PowerPC/pr44183.ll b/llvm/test/CodeGen/PowerPC/pr44183.ll
--- a/llvm/test/CodeGen/PowerPC/pr44183.ll
+++ b/llvm/test/CodeGen/PowerPC/pr44183.ll
@@ -14,15 +14,15 @@
 ; CHECK-NEXT:    mr r30, r3
 ; CHECK-NEXT:    ld r4, 8(r30)
 ; CHECK-NEXT:    lwz r5, 36(r30)
-; CHECK-NEXT:    rldicl r4, r4, 60, 4
-; CHECK-NEXT:    rlwinm r3, r4, 31, 0, 0
+; CHECK-NEXT:    srdi r4, r4, 4
+; CHECK-NEXT:    slwi r3, r4, 31
 ; CHECK-NEXT:    clrlwi r4, r5, 31
 ; CHECK-NEXT:    or r4, r4, r3
 ; CHECK-NEXT:    bl _ZN1llsE1d
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    ld r3, 16(r30)
 ; CHECK-NEXT:    ld r4, 8(r30)
-; CHECK-NEXT:    rldicl r4, r4, 60, 4
+; CHECK-NEXT:    srdi r4, r4, 4
 ; CHECK-NEXT:    sldi r3, r3, 60
 ; CHECK-NEXT:    or r3, r4, r3
 ; CHECK-NEXT:    sldi r3, r3, 31
diff --git a/llvm/test/CodeGen/PowerPC/rlwimi-and.ll b/llvm/test/CodeGen/PowerPC/rlwimi-and.ll
--- a/llvm/test/CodeGen/PowerPC/rlwimi-and.ll
+++ b/llvm/test/CodeGen/PowerPC/rlwimi-and.ll
@@ -30,7 +30,7 @@
 
 ; CHECK: @test
 ; CHECK: clrlwi [[R1:[0-9]+]], {{[0-9]+}}, 31
-; CHECK: rlwimi [[R1]], {{[0-9]+}}, 8, 23, 23
+; CHECK: insrwi [[R1]], {{[0-9]+}}, 1, 23
 
 codeRepl29:                                       ; preds = %codeRepl1
   unreachable
diff --git a/llvm/test/CodeGen/PowerPC/rlwimi-dyn-and.ll b/llvm/test/CodeGen/PowerPC/rlwimi-dyn-and.ll
--- a/llvm/test/CodeGen/PowerPC/rlwimi-dyn-and.ll
+++ b/llvm/test/CodeGen/PowerPC/rlwimi-dyn-and.ll
@@ -39,8 +39,8 @@
   ret i32 %conv174
 
 ; CHECK-LABEL: @test2
-; CHECK: rlwinm 3, {{[0-9]+}}, 7, 17, 24
-; CHECK: rlwimi 3, {{[0-9]+}}, 15, 16, 16
+; CHECK: clrlslwi 3, {{[0-9]+}}, 24, 7
+; CHECK: insrwi 3, {{[0-9]+}}, 1, 16
 ; CHECK: blr
 }
 
diff --git a/llvm/test/CodeGen/PowerPC/rlwimi-keep-rsh.ll b/llvm/test/CodeGen/PowerPC/rlwimi-keep-rsh.ll
--- a/llvm/test/CodeGen/PowerPC/rlwimi-keep-rsh.ll
+++ b/llvm/test/CodeGen/PowerPC/rlwimi-keep-rsh.ll
@@ -8,7 +8,7 @@
 ; CHECK: xxx:
 ; CHECK: or
 ; CHECK: and
-; CHECK: rlwimi
+; CHECK: insrwi
 entry:
   %tmp0 = ashr i32 %d, 31
   %tmp1 = and i32 %tmp0, 255
diff --git a/llvm/test/CodeGen/PowerPC/rlwimi.ll b/llvm/test/CodeGen/PowerPC/rlwimi.ll
--- a/llvm/test/CodeGen/PowerPC/rlwimi.ll
+++ b/llvm/test/CodeGen/PowerPC/rlwimi.ll
@@ -1,6 +1,8 @@
 ; All of these ands and shifts should be folded into rlwimi's
 ; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | not grep and
-; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | grep rlwimi | count 8
+; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | grep rlwimi | count 2
+; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | grep inslwi | count 2
+; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | grep insrwi | count 4
 
 define i32 @test1(i32 %x, i32 %y) {
 entry:
diff --git a/llvm/test/CodeGen/PowerPC/rlwinm.ll b/llvm/test/CodeGen/PowerPC/rlwinm.ll
--- a/llvm/test/CodeGen/PowerPC/rlwinm.ll
+++ b/llvm/test/CodeGen/PowerPC/rlwinm.ll
@@ -4,7 +4,9 @@
 ; RUN: not grep srawi %t
 ; RUN: not grep srwi %t
 ; RUN: not grep slwi %t
-; RUN: grep rlwinm %t | count 8
+; RUN: grep extrwi %t | count 4
+; RUN: grep extlwi %t | count 2
+; RUN: grep rlwinm %t | count 2
 
 define i32 @test1(i32 %a) {
 entry:
diff --git a/llvm/test/CodeGen/PowerPC/sched-addi.ll b/llvm/test/CodeGen/PowerPC/sched-addi.ll
--- a/llvm/test/CodeGen/PowerPC/sched-addi.ll
+++ b/llvm/test/CodeGen/PowerPC/sched-addi.ll
@@ -16,9 +16,9 @@
 ; CHECK-P9-NEXT:    addis 6, 2, scalars@toc@ha
 ; CHECK-P9-NEXT:    addi 6, 6, scalars@toc@l
 ; CHECK-P9-NEXT:    addi 6, 6, 16
-; CHECK-P9-NEXT:    rldicr 5, 5, 0, 58
+; CHECK-P9-NEXT:    clrrdi 5, 5, 5
 ; CHECK-P9-NEXT:    addi 5, 5, -32
-; CHECK-P9-NEXT:    rldicl 5, 5, 59, 5
+; CHECK-P9-NEXT:    srdi 5, 5, 5
 ; CHECK-P9-NEXT:    addi 5, 5, 1
 ; CHECK-P9-NEXT:    lxvdsx 0, 0, 6
 ; CHECK-P9-NEXT:    mtctr 5
@@ -54,10 +54,10 @@
 ; CHECK-P9-NO-HEURISTIC-NEXT:    ld 5, 0(5)
 ; CHECK-P9-NO-HEURISTIC-NEXT:    addis 6, 2, scalars@toc@ha
 ; CHECK-P9-NO-HEURISTIC-NEXT:    addi 6, 6, scalars@toc@l
-; CHECK-P9-NO-HEURISTIC-NEXT:    rldicr 5, 5, 0, 58
+; CHECK-P9-NO-HEURISTIC-NEXT:    clrrdi 5, 5, 5
 ; CHECK-P9-NO-HEURISTIC-NEXT:    addi 6, 6, 16
 ; CHECK-P9-NO-HEURISTIC-NEXT:    addi 5, 5, -32
-; CHECK-P9-NO-HEURISTIC-NEXT:    rldicl 5, 5, 59, 5
+; CHECK-P9-NO-HEURISTIC-NEXT:    srdi 5, 5, 5
 ; CHECK-P9-NO-HEURISTIC-NEXT:    addi 5, 5, 1
 ; CHECK-P9-NO-HEURISTIC-NEXT:    lxvdsx 0, 0, 6
 ; CHECK-P9-NO-HEURISTIC-NEXT:    mtctr 5
diff --git a/llvm/test/CodeGen/PowerPC/setcc-logic.ll b/llvm/test/CodeGen/PowerPC/setcc-logic.ll
--- a/llvm/test/CodeGen/PowerPC/setcc-logic.ll
+++ b/llvm/test/CodeGen/PowerPC/setcc-logic.ll
@@ -485,7 +485,7 @@
 ; CHECK-NEXT:    rldicl 3, 3, 61, 1
 ; CHECK-NEXT:    rotldi 3, 3, 3
 ; CHECK-NEXT:    cntlzd 3, 3
-; CHECK-NEXT:    rldicl 3, 3, 58, 63
+; CHECK-NEXT:    extrdi 3, 3, 1, 57
 ; CHECK-NEXT:    blr
   %a = icmp eq i64 %x, 17
   %b = icmp eq i64 %x, 13
@@ -500,7 +500,7 @@
 ; CHECK-NEXT:    rlwinm 3, 3, 0, 28, 26
 ; CHECK-NEXT:    cntlzw 3, 3
 ; CHECK-NEXT:    not 3, 3
-; CHECK-NEXT:    rlwinm 3, 3, 27, 31, 31
+; CHECK-NEXT:    extrwi 3, 3, 1, 26
 ; CHECK-NEXT:    blr
   %a = icmp ne i32 %x, 4625
   %b = icmp ne i32 %x, 4641
diff --git a/llvm/test/CodeGen/PowerPC/setcc-to-sub.ll b/llvm/test/CodeGen/PowerPC/setcc-to-sub.ll
--- a/llvm/test/CodeGen/PowerPC/setcc-to-sub.ll
+++ b/llvm/test/CodeGen/PowerPC/setcc-to-sub.ll
@@ -14,7 +14,7 @@
 ; CHECK-NEXT:    rlwinm 3, 3, 0, 28, 28
 ; CHECK-NEXT:    rlwinm 4, 4, 0, 28, 28
 ; CHECK-NEXT:    sub 3, 3, 4
-; CHECK-NEXT:    rldicl 3, 3, 1, 63
+; CHECK-NEXT:    srdi 3, 3, 63
 ; CHECK-NEXT:    blr
 entry:
   %arrayidx.i6 = bitcast %class.PB2* %s_a to i32*
@@ -37,7 +37,7 @@
 ; CHECK-NEXT:    rlwinm 4, 4, 0, 28, 28
 ; CHECK-NEXT:    sub 3, 4, 3
 ; CHECK-NEXT:    not 3, 3
-; CHECK-NEXT:    rldicl 3, 3, 1, 63
+; CHECK-NEXT:    srdi 3, 3, 63
 ; CHECK-NEXT:    blr
 entry:
   %arrayidx.i6 = bitcast %class.PB2* %s_a to i32*
@@ -59,7 +59,7 @@
 ; CHECK-NEXT:    rlwinm 3, 3, 0, 28, 28
 ; CHECK-NEXT:    rlwinm 4, 4, 0, 28, 28
 ; CHECK-NEXT:    sub 3, 4, 3
-; CHECK-NEXT:    rldicl 3, 3, 1, 63
+; CHECK-NEXT:    srdi 3, 3, 63
 ; CHECK-NEXT:    blr
 entry:
   %arrayidx.i6 = bitcast %class.PB2* %s_a to i32*
@@ -82,7 +82,7 @@
 ; CHECK-NEXT:    rlwinm 4, 4, 0, 28, 28
 ; CHECK-NEXT:    sub 3, 3, 4
 ; CHECK-NEXT:    not 3, 3
-; CHECK-NEXT:    rldicl 3, 3, 1, 63
+; CHECK-NEXT:    srdi 3, 3, 63
 ; CHECK-NEXT:    blr
 entry:
   %arrayidx.i6 = bitcast %class.PB2* %s_a to i32*
diff --git a/llvm/test/CodeGen/PowerPC/setcc_no_zext.ll b/llvm/test/CodeGen/PowerPC/setcc_no_zext.ll
--- a/llvm/test/CodeGen/PowerPC/setcc_no_zext.ll
+++ b/llvm/test/CodeGen/PowerPC/setcc_no_zext.ll
@@ -1,4 +1,4 @@
-; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | not grep rlwinm
+; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | not grep extrwi
 
 ; FIXME: This optimization has temporarily regressed with crbits enabled by
 ; default at the default CodeOpt level.
diff --git a/llvm/test/CodeGen/PowerPC/seteq-0.ll b/llvm/test/CodeGen/PowerPC/seteq-0.ll
--- a/llvm/test/CodeGen/PowerPC/seteq-0.ll
+++ b/llvm/test/CodeGen/PowerPC/seteq-0.ll
@@ -6,7 +6,7 @@
         ret i32 %tmp.2
 
 ; CHECK: cntlzw [[REG:[0-9]+]], 3
-; CHECK: rlwinm 3, [[REG]], 27, 31, 31
+; CHECK: extrwi 3, [[REG]], 1, 26
 ; CHECK: blr
 }
 
diff --git a/llvm/test/CodeGen/PowerPC/setrnd.ll b/llvm/test/CodeGen/PowerPC/setrnd.ll
--- a/llvm/test/CodeGen/PowerPC/setrnd.ll
+++ b/llvm/test/CodeGen/PowerPC/setrnd.ll
@@ -46,7 +46,7 @@
 ; CHECK:      # %bb.0:
 ; CHECK-DAG:   mffs 1 
 ; CHECK-DAG:   mffprd [[REG1:[0-9]+]], 1 
-; CHECK-DAG:   rldimi [[REG1]], 3, 0, 62
+; CHECK-DAG:   insrdi [[REG1]], 3, 2, 62
 ; CHECK-DAG:   mtfprd [[REG2:[0-9]+]], [[REG1]]
 ; CHECK-DAG:   mtfsf 255, [[REG2]] 
 ; CHECK:       blr
@@ -56,7 +56,7 @@
 ; CHECK-PWR7-DAG:   mffs 1 
 ; CHECK-PWR7-DAG:   stfd 1, -8(1) 
 ; CHECK-PWR7-DAG:   ld [[REG1:[0-9]+]], -8(1) 
-; CHECK-PWR7-DAG:   rldimi [[REG1]], 3, 0, 62
+; CHECK-PWR7-DAG:   insrdi [[REG1]], 3, 2, 62
 ; CHECK-PWR7-DAG:   std [[REG1]], -16(1)
 ; CHECK-PWR7-DAG:   lfd [[REG2:[0-9]+]], -16(1)
 ; CHECK-PWR7-DAG:   mtfsf 255, [[REG2]] 
diff --git a/llvm/test/CodeGen/PowerPC/sms-phi-5.ll b/llvm/test/CodeGen/PowerPC/sms-phi-5.ll
--- a/llvm/test/CodeGen/PowerPC/sms-phi-5.ll
+++ b/llvm/test/CodeGen/PowerPC/sms-phi-5.ll
@@ -15,9 +15,9 @@
 ; CHECK-NEXT:    lhz 3, 0(3)
 ; CHECK-NEXT:    slwi 3, 3, 15
 ; CHECK-NEXT:    clrlwi 3, 3, 31
-; CHECK-NEXT:    rlwinm 4, 3, 31, 17, 31
+; CHECK-NEXT:    extrwi 4, 3, 15, 16
 ; CHECK-NEXT:    or 3, 3, 4
-; CHECK-NEXT:    rlwimi 3, 3, 15, 0, 16
+; CHECK-NEXT:    insrwi 3, 3, 17, 0
 ; CHECK-NEXT:  # %bb.3:
 ; CHECK-NEXT:    blr
   switch i12 undef, label %21 [
diff --git a/llvm/test/CodeGen/PowerPC/smulfixsat.ll b/llvm/test/CodeGen/PowerPC/smulfixsat.ll
--- a/llvm/test/CodeGen/PowerPC/smulfixsat.ll
+++ b/llvm/test/CodeGen/PowerPC/smulfixsat.ll
@@ -34,7 +34,7 @@
 ; CHECK-NEXT:    mullw 3, 3, 4
 ; CHECK-NEXT:    rotlwi 3, 3, 31
 ; CHECK-NEXT:    ori 4, 5, 65535
-; CHECK-NEXT:    rlwimi 3, 6, 31, 0, 0
+; CHECK-NEXT:    insrwi 3, 6, 1, 0
 ; CHECK-NEXT:    bc 12, 1, .LBB1_1
 ; CHECK-NEXT:    b .LBB1_2
 ; CHECK-NEXT:  .LBB1_1:
diff --git a/llvm/test/CodeGen/PowerPC/spill_p9_setb.ll b/llvm/test/CodeGen/PowerPC/spill_p9_setb.ll
--- a/llvm/test/CodeGen/PowerPC/spill_p9_setb.ll
+++ b/llvm/test/CodeGen/PowerPC/spill_p9_setb.ll
@@ -27,7 +27,7 @@
 ; CHECK-P8:       # %bb.1: # %if.then
 ; CHECK-P8-DAG:    crnot 4*cr[[CREG2:.*]]+lt, eq
 ; CHECK-P8-DAG:    mfocrf [[REG2:.*]],
-; CHECK-P8-DAG:    rlwinm [[REG2]], [[REG2]]
+; CHECK-P8-DAG:    extlwi [[REG2]], [[REG2]]
 ; CHECK-P8-DAG:    stw [[REG2]]
 ; CHECK-P8:        blr
 ; CHECK-P8:        .LBB0_4: # %if.then1
diff --git a/llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll b/llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll
--- a/llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll
+++ b/llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll
@@ -142,10 +142,10 @@
 ; P8LE-NEXT:    ori r9, r9, 37253
 ; P8LE-NEXT:    ori r8, r8, 63249
 ; P8LE-NEXT:    mffprd r4, f0
-; P8LE-NEXT:    rldicl r5, r4, 32, 48
+; P8LE-NEXT:    extrdi r5, r4, 16, 16
 ; P8LE-NEXT:    clrldi r7, r4, 48
-; P8LE-NEXT:    rldicl r6, r4, 16, 48
-; P8LE-NEXT:    rldicl r4, r4, 48, 48
+; P8LE-NEXT:    srdi r6, r4, 48
+; P8LE-NEXT:    extrdi r4, r4, 16, 32
 ; P8LE-NEXT:    extsh r10, r5
 ; P8LE-NEXT:    extsh r0, r7
 ; P8LE-NEXT:    mulhw r3, r10, r3
@@ -202,11 +202,11 @@
 ; P8BE-NEXT:    ori r9, r9, 63421
 ; P8BE-NEXT:    ori r10, r10, 37253
 ; P8BE-NEXT:    clrldi r5, r4, 48
-; P8BE-NEXT:    rldicl r6, r4, 48, 48
-; P8BE-NEXT:    rldicl r7, r4, 32, 48
+; P8BE-NEXT:    extrdi r6, r4, 16, 32
+; P8BE-NEXT:    extrdi r7, r4, 16, 16
 ; P8BE-NEXT:    extsh r5, r5
 ; P8BE-NEXT:    extsh r6, r6
-; P8BE-NEXT:    rldicl r4, r4, 16, 48
+; P8BE-NEXT:    srdi r4, r4, 48
 ; P8BE-NEXT:    extsh r7, r7
 ; P8BE-NEXT:    mulhw r3, r5, r3
 ; P8BE-NEXT:    extsh r4, r4
@@ -374,12 +374,12 @@
 ; P8LE-NEXT:    ori r3, r3, 37253
 ; P8LE-NEXT:    mffprd r4, f0
 ; P8LE-NEXT:    clrldi r5, r4, 48
-; P8LE-NEXT:    rldicl r6, r4, 48, 48
+; P8LE-NEXT:    extrdi r6, r4, 16, 32
 ; P8LE-NEXT:    extsh r8, r5
-; P8LE-NEXT:    rldicl r7, r4, 32, 48
+; P8LE-NEXT:    extrdi r7, r4, 16, 16
 ; P8LE-NEXT:    extsh r9, r6
 ; P8LE-NEXT:    mulhw r10, r8, r3
-; P8LE-NEXT:    rldicl r4, r4, 16, 48
+; P8LE-NEXT:    srdi r4, r4, 48
 ; P8LE-NEXT:    extsh r11, r7
 ; P8LE-NEXT:    mulhw r12, r9, r3
 ; P8LE-NEXT:    extsh r0, r4
@@ -429,12 +429,12 @@
 ; P8BE-NEXT:    lis r3, -21386
 ; P8BE-NEXT:    ori r3, r3, 37253
 ; P8BE-NEXT:    clrldi r5, r4, 48
-; P8BE-NEXT:    rldicl r6, r4, 48, 48
+; P8BE-NEXT:    extrdi r6, r4, 16, 32
 ; P8BE-NEXT:    extsh r5, r5
-; P8BE-NEXT:    rldicl r7, r4, 32, 48
+; P8BE-NEXT:    extrdi r7, r4, 16, 16
 ; P8BE-NEXT:    extsh r6, r6
 ; P8BE-NEXT:    mulhw r8, r5, r3
-; P8BE-NEXT:    rldicl r4, r4, 16, 48
+; P8BE-NEXT:    srdi r4, r4, 48
 ; P8BE-NEXT:    extsh r7, r7
 ; P8BE-NEXT:    mulhw r9, r6, r3
 ; P8BE-NEXT:    extsh r4, r4
@@ -629,13 +629,13 @@
 ; P8LE-NEXT:    ori r4, r4, 37253
 ; P8LE-NEXT:    mffprd r5, f0
 ; P8LE-NEXT:    clrldi r3, r5, 48
-; P8LE-NEXT:    rldicl r6, r5, 48, 48
-; P8LE-NEXT:    rldicl r7, r5, 32, 48
+; P8LE-NEXT:    extrdi r6, r5, 16, 32
+; P8LE-NEXT:    extrdi r7, r5, 16, 16
 ; P8LE-NEXT:    extsh r8, r3
 ; P8LE-NEXT:    extsh r9, r6
 ; P8LE-NEXT:    extsh r10, r7
 ; P8LE-NEXT:    mulhw r11, r8, r4
-; P8LE-NEXT:    rldicl r5, r5, 16, 48
+; P8LE-NEXT:    srdi r5, r5, 48
 ; P8LE-NEXT:    mulhw r12, r9, r4
 ; P8LE-NEXT:    mulhw r0, r10, r4
 ; P8LE-NEXT:    extsh r30, r5
@@ -696,11 +696,11 @@
 ; P8BE-NEXT:    lis r4, -21386
 ; P8BE-NEXT:    ori r4, r4, 37253
 ; P8BE-NEXT:    clrldi r3, r5, 48
-; P8BE-NEXT:    rldicl r6, r5, 48, 48
+; P8BE-NEXT:    extrdi r6, r5, 16, 32
 ; P8BE-NEXT:    extsh r8, r3
-; P8BE-NEXT:    rldicl r7, r5, 32, 48
+; P8BE-NEXT:    extrdi r7, r5, 16, 16
 ; P8BE-NEXT:    extsh r9, r6
-; P8BE-NEXT:    rldicl r5, r5, 16, 48
+; P8BE-NEXT:    srdi r5, r5, 48
 ; P8BE-NEXT:    mulhw r11, r8, r4
 ; P8BE-NEXT:    extsh r10, r7
 ; P8BE-NEXT:    extsh r5, r5
@@ -865,16 +865,16 @@
 ; P8LE-NEXT:    lis r3, -21386
 ; P8LE-NEXT:    ori r3, r3, 37253
 ; P8LE-NEXT:    mffprd r4, f0
-; P8LE-NEXT:    rldicl r5, r4, 16, 48
+; P8LE-NEXT:    srdi r5, r4, 48
 ; P8LE-NEXT:    clrldi r7, r4, 48
 ; P8LE-NEXT:    extsh r6, r5
 ; P8LE-NEXT:    extsh r8, r7
 ; P8LE-NEXT:    mulhw r3, r6, r3
-; P8LE-NEXT:    rldicl r9, r4, 48, 48
+; P8LE-NEXT:    extrdi r9, r4, 16, 32
 ; P8LE-NEXT:    srawi r8, r8, 6
 ; P8LE-NEXT:    extsh r10, r9
 ; P8LE-NEXT:    addze r8, r8
-; P8LE-NEXT:    rldicl r4, r4, 32, 48
+; P8LE-NEXT:    extrdi r4, r4, 16, 16
 ; P8LE-NEXT:    srawi r10, r10, 5
 ; P8LE-NEXT:    slwi r8, r8, 6
 ; P8LE-NEXT:    add r3, r3, r6
@@ -911,15 +911,15 @@
 ; P8BE-NEXT:    lis r3, -21386
 ; P8BE-NEXT:    ori r3, r3, 37253
 ; P8BE-NEXT:    clrldi r5, r4, 48
-; P8BE-NEXT:    rldicl r6, r4, 32, 48
+; P8BE-NEXT:    extrdi r6, r4, 16, 16
 ; P8BE-NEXT:    extsh r5, r5
 ; P8BE-NEXT:    extsh r6, r6
 ; P8BE-NEXT:    mulhw r3, r5, r3
-; P8BE-NEXT:    rldicl r7, r4, 16, 48
+; P8BE-NEXT:    srdi r7, r4, 48
 ; P8BE-NEXT:    srawi r8, r6, 5
 ; P8BE-NEXT:    extsh r7, r7
 ; P8BE-NEXT:    addze r8, r8
-; P8BE-NEXT:    rldicl r4, r4, 48, 48
+; P8BE-NEXT:    extrdi r4, r4, 16, 32
 ; P8BE-NEXT:    srawi r9, r7, 6
 ; P8BE-NEXT:    extsh r4, r4
 ; P8BE-NEXT:    slwi r8, r8, 5
@@ -1065,9 +1065,9 @@
 ; P8LE-NEXT:    ori r3, r3, 47143
 ; P8LE-NEXT:    ori r7, r7, 17097
 ; P8LE-NEXT:    mffprd r4, f0
-; P8LE-NEXT:    rldicl r5, r4, 16, 48
-; P8LE-NEXT:    rldicl r6, r4, 32, 48
-; P8LE-NEXT:    rldicl r4, r4, 48, 48
+; P8LE-NEXT:    srdi r5, r4, 48
+; P8LE-NEXT:    extrdi r6, r4, 16, 16
+; P8LE-NEXT:    extrdi r4, r4, 16, 32
 ; P8LE-NEXT:    extsh r8, r5
 ; P8LE-NEXT:    extsh r10, r6
 ; P8LE-NEXT:    mulhw r3, r8, r3
@@ -1113,8 +1113,8 @@
 ; P8BE-NEXT:    ori r6, r6, 17097
 ; P8BE-NEXT:    ori r8, r8, 30865
 ; P8BE-NEXT:    clrldi r4, r3, 48
-; P8BE-NEXT:    rldicl r7, r3, 48, 48
-; P8BE-NEXT:    rldicl r3, r3, 32, 48
+; P8BE-NEXT:    extrdi r7, r3, 16, 32
+; P8BE-NEXT:    extrdi r3, r3, 16, 16
 ; P8BE-NEXT:    extsh r4, r4
 ; P8BE-NEXT:    extsh r7, r7
 ; P8BE-NEXT:    extsh r3, r3
@@ -1256,13 +1256,13 @@
 ; P8LE-NEXT:    ori r4, r4, 47143
 ; P8LE-NEXT:    ori r5, r5, 17097
 ; P8LE-NEXT:    mffprd r3, f0
-; P8LE-NEXT:    rldicl r6, r3, 16, 48
-; P8LE-NEXT:    rldicl r7, r3, 32, 48
+; P8LE-NEXT:    srdi r6, r3, 48
+; P8LE-NEXT:    extrdi r7, r3, 16, 16
 ; P8LE-NEXT:    extsh r8, r6
 ; P8LE-NEXT:    extsh r9, r7
 ; P8LE-NEXT:    mulhw r4, r8, r4
 ; P8LE-NEXT:    mulhw r5, r9, r5
-; P8LE-NEXT:    rldicl r3, r3, 48, 48
+; P8LE-NEXT:    extrdi r3, r3, 16, 32
 ; P8LE-NEXT:    srwi r8, r4, 31
 ; P8LE-NEXT:    srawi r4, r4, 11
 ; P8LE-NEXT:    add r5, r5, r9
@@ -1298,12 +1298,12 @@
 ; P8BE-NEXT:    ori r4, r4, 47143
 ; P8BE-NEXT:    ori r5, r5, 17097
 ; P8BE-NEXT:    clrldi r6, r3, 48
-; P8BE-NEXT:    rldicl r7, r3, 48, 48
+; P8BE-NEXT:    extrdi r7, r3, 16, 32
 ; P8BE-NEXT:    extsh r6, r6
 ; P8BE-NEXT:    extsh r7, r7
 ; P8BE-NEXT:    mulhw r4, r6, r4
 ; P8BE-NEXT:    mulhw r5, r7, r5
-; P8BE-NEXT:    rldicl r3, r3, 32, 48
+; P8BE-NEXT:    extrdi r3, r3, 16, 16
 ; P8BE-NEXT:    extsh r3, r3
 ; P8BE-NEXT:    srwi r8, r4, 31
 ; P8BE-NEXT:    srawi r4, r4, 11
@@ -1348,7 +1348,7 @@
 ; P9LE-NEXT:    mfvsrd r3, v3
 ; P9LE-NEXT:    ori r4, r4, 6055
 ; P9LE-NEXT:    mulhd r4, r3, r4
-; P9LE-NEXT:    rldicl r5, r4, 1, 63
+; P9LE-NEXT:    srdi r5, r4, 63
 ; P9LE-NEXT:    sradi r4, r4, 11
 ; P9LE-NEXT:    add r4, r4, r5
 ; P9LE-NEXT:    lis r5, -19946
@@ -1361,7 +1361,7 @@
 ; P9LE-NEXT:    ori r5, r5, 8549
 ; P9LE-NEXT:    mulhd r5, r4, r5
 ; P9LE-NEXT:    add r5, r5, r4
-; P9LE-NEXT:    rldicl r6, r5, 1, 63
+; P9LE-NEXT:    srdi r6, r5, 63
 ; P9LE-NEXT:    sradi r5, r5, 4
 ; P9LE-NEXT:    add r5, r5, r6
 ; P9LE-NEXT:    mulli r5, r5, 23
@@ -1374,7 +1374,7 @@
 ; P9LE-NEXT:    mfvsrd r3, v2
 ; P9LE-NEXT:    ori r4, r4, 21445
 ; P9LE-NEXT:    mulhd r4, r3, r4
-; P9LE-NEXT:    rldicl r5, r4, 1, 63
+; P9LE-NEXT:    srdi r5, r4, 63
 ; P9LE-NEXT:    sradi r4, r4, 8
 ; P9LE-NEXT:    add r4, r4, r5
 ; P9LE-NEXT:    mulli r4, r4, 654
@@ -1392,7 +1392,7 @@
 ; P9BE-NEXT:    mfvsrld r3, v3
 ; P9BE-NEXT:    ori r4, r4, 6055
 ; P9BE-NEXT:    mulhd r4, r3, r4
-; P9BE-NEXT:    rldicl r5, r4, 1, 63
+; P9BE-NEXT:    srdi r5, r4, 63
 ; P9BE-NEXT:    sradi r4, r4, 11
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    lis r5, -19946
@@ -1405,7 +1405,7 @@
 ; P9BE-NEXT:    ori r5, r5, 8549
 ; P9BE-NEXT:    mulhd r5, r4, r5
 ; P9BE-NEXT:    add r5, r5, r4
-; P9BE-NEXT:    rldicl r6, r5, 1, 63
+; P9BE-NEXT:    srdi r6, r5, 63
 ; P9BE-NEXT:    sradi r5, r5, 4
 ; P9BE-NEXT:    add r5, r5, r6
 ; P9BE-NEXT:    mulli r5, r5, 23
@@ -1418,7 +1418,7 @@
 ; P9BE-NEXT:    mfvsrld r3, v2
 ; P9BE-NEXT:    ori r4, r4, 21445
 ; P9BE-NEXT:    mulhd r4, r3, r4
-; P9BE-NEXT:    rldicl r5, r4, 1, 63
+; P9BE-NEXT:    srdi r5, r4, 63
 ; P9BE-NEXT:    sradi r4, r4, 8
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, 654
@@ -1450,15 +1450,15 @@
 ; P8LE-NEXT:    mulhd r3, r6, r3
 ; P8LE-NEXT:    mulhd r5, r7, r5
 ; P8LE-NEXT:    mulhd r4, r8, r4
-; P8LE-NEXT:    rldicl r9, r3, 1, 63
+; P8LE-NEXT:    srdi r9, r3, 63
 ; P8LE-NEXT:    sradi r3, r3, 11
 ; P8LE-NEXT:    add r3, r3, r9
-; P8LE-NEXT:    rldicl r9, r5, 1, 63
+; P8LE-NEXT:    srdi r9, r5, 63
 ; P8LE-NEXT:    add r4, r4, r8
 ; P8LE-NEXT:    sradi r5, r5, 8
 ; P8LE-NEXT:    mulli r3, r3, 5423
 ; P8LE-NEXT:    add r5, r5, r9
-; P8LE-NEXT:    rldicl r9, r4, 1, 63
+; P8LE-NEXT:    srdi r9, r4, 63
 ; P8LE-NEXT:    sradi r4, r4, 4
 ; P8LE-NEXT:    mulli r5, r5, 654
 ; P8LE-NEXT:    add r4, r4, r9
@@ -1501,12 +1501,12 @@
 ; P8BE-NEXT:    ori r5, r5, 21445
 ; P8BE-NEXT:    mulhd r5, r8, r5
 ; P8BE-NEXT:    add r4, r4, r6
-; P8BE-NEXT:    rldicl r9, r3, 1, 63
+; P8BE-NEXT:    srdi r9, r3, 63
 ; P8BE-NEXT:    sradi r3, r3, 11
-; P8BE-NEXT:    rldicl r10, r4, 1, 63
+; P8BE-NEXT:    srdi r10, r4, 63
 ; P8BE-NEXT:    sradi r4, r4, 4
 ; P8BE-NEXT:    add r3, r3, r9
-; P8BE-NEXT:    rldicl r9, r5, 1, 63
+; P8BE-NEXT:    srdi r9, r5, 63
 ; P8BE-NEXT:    add r4, r4, r10
 ; P8BE-NEXT:    sradi r5, r5, 8
 ; P8BE-NEXT:    mulli r3, r3, 5423
diff --git a/llvm/test/CodeGen/PowerPC/srl-mask.ll b/llvm/test/CodeGen/PowerPC/srl-mask.ll
--- a/llvm/test/CodeGen/PowerPC/srl-mask.ll
+++ b/llvm/test/CodeGen/PowerPC/srl-mask.ll
@@ -7,7 +7,7 @@
 ; CHECK-LABEL: @foo
   %a = lshr i64 %x, 35
   %b = and i64 %a, 65535
-; CHECK: rldicl 3, 3, 29, 48
+; CHECK: extrdi 3, 3, 16, 13
   ret i64 %b
 ; CHECK: blr
 }
@@ -18,7 +18,7 @@
 entry:
 ; CHECK-LABEL: @bar
   %a = and i64 %x, 18446744073709486080
-; CHECK: rldicr 3, 3, 0, 47
+; CHECK: clrrdi 3, 3, 16
   ret i64 %a
 ; CHECK: blr
 }
diff --git a/llvm/test/CodeGen/PowerPC/testBitReverse.ll b/llvm/test/CodeGen/PowerPC/testBitReverse.ll
--- a/llvm/test/CodeGen/PowerPC/testBitReverse.ll
+++ b/llvm/test/CodeGen/PowerPC/testBitReverse.ll
@@ -35,7 +35,7 @@
 ; PPC32-NEXT:    or 4, 3, 4
 ; PPC32-NEXT:    rotlwi 3, 4, 24
 ; PPC32-NEXT:    rlwimi 3, 4, 8, 8, 15
-; PPC32-NEXT:    rlwimi 3, 4, 8, 24, 31
+; PPC32-NEXT:    inslwi 3, 4, 8, 24
 ; PPC32-NEXT:    blr
 ;
 ; CHECK-LABEL: testBitReverseIntrinsicI32:
@@ -69,7 +69,7 @@
 ; CHECK-NEXT:    or 3, 3, 4
 ; CHECK-NEXT:    rotlwi 4, 3, 24
 ; CHECK-NEXT:    rlwimi 4, 3, 8, 8, 15
-; CHECK-NEXT:    rlwimi 4, 3, 8, 24, 31
+; CHECK-NEXT:    inslwi 4, 3, 8, 24
 ; CHECK-NEXT:    rldicl 3, 4, 0, 32
 ; CHECK-NEXT:    blr
   %res = call i32 @llvm.bitreverse.i32(i32 %arg)
@@ -126,8 +126,8 @@
 ; PPC32-NEXT:    rotlwi 4, 6, 24
 ; PPC32-NEXT:    rlwimi 3, 5, 8, 8, 15
 ; PPC32-NEXT:    rlwimi 4, 6, 8, 8, 15
-; PPC32-NEXT:    rlwimi 3, 5, 8, 24, 31
-; PPC32-NEXT:    rlwimi 4, 6, 8, 24, 31
+; PPC32-NEXT:    inslwi 3, 5, 8, 24
+; PPC32-NEXT:    inslwi 4, 6, 8, 24
 ; PPC32-NEXT:    blr
 ;
 ; CHECK-LABEL: testBitReverseIntrinsicI64:
@@ -145,7 +145,7 @@
 ; CHECK-NEXT:    oris 4, 4, 43690
 ; CHECK-NEXT:    oris 5, 5, 21845
 ; CHECK-NEXT:    sldi 6, 3, 1
-; CHECK-NEXT:    rldicl 3, 3, 63, 1
+; CHECK-NEXT:    srdi 3, 3, 1
 ; CHECK-NEXT:    ori 4, 4, 43690
 ; CHECK-NEXT:    ori 5, 5, 21845
 ; CHECK-NEXT:    sldi 7, 7, 32
@@ -162,7 +162,7 @@
 ; CHECK-NEXT:    ori 7, 7, 13107
 ; CHECK-NEXT:    ori 4, 4, 3855
 ; CHECK-NEXT:    sldi 8, 3, 2
-; CHECK-NEXT:    rldicl 3, 3, 62, 2
+; CHECK-NEXT:    srdi 3, 3, 2
 ; CHECK-NEXT:    and 6, 8, 6
 ; CHECK-NEXT:    and 3, 3, 7
 ; CHECK-NEXT:    sldi 5, 5, 32
@@ -173,17 +173,17 @@
 ; CHECK-NEXT:    sldi 6, 3, 4
 ; CHECK-NEXT:    ori 5, 5, 61680
 ; CHECK-NEXT:    ori 4, 4, 3855
-; CHECK-NEXT:    rldicl 3, 3, 60, 4
+; CHECK-NEXT:    srdi 3, 3, 4
 ; CHECK-NEXT:    and 5, 6, 5
 ; CHECK-NEXT:    and 3, 3, 4
 ; CHECK-NEXT:    or 3, 3, 5
-; CHECK-NEXT:    rldicl 4, 3, 32, 32
+; CHECK-NEXT:    srdi 4, 3, 32
 ; CHECK-NEXT:    rotlwi 5, 3, 24
 ; CHECK-NEXT:    rotlwi 6, 4, 24
 ; CHECK-NEXT:    rlwimi 5, 3, 8, 8, 15
-; CHECK-NEXT:    rlwimi 5, 3, 8, 24, 31
+; CHECK-NEXT:    inslwi 5, 3, 8, 24
 ; CHECK-NEXT:    rlwimi 6, 4, 8, 8, 15
-; CHECK-NEXT:    rlwimi 6, 4, 8, 24, 31
+; CHECK-NEXT:    inslwi 6, 4, 8, 24
 ; CHECK-NEXT:    sldi 3, 5, 32
 ; CHECK-NEXT:    or 3, 3, 6
 ; CHECK-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/testComparesi32gtu.ll b/llvm/test/CodeGen/PowerPC/testComparesi32gtu.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesi32gtu.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesi32gtu.ll
@@ -27,7 +27,7 @@
 ; BE-NEXT:    clrlwi r4, r4, 31
 ; BE-NEXT:    clrldi r4, r4, 32
 ; BE-NEXT:    sub r3, r3, r4
-; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    srdi r3, r3, 63
 ; BE-NEXT:    bl fn2
 ; BE-NEXT:    nop
 ; BE-NEXT:    addi r1, r1, 112
@@ -49,7 +49,7 @@
 ; LE-NEXT:    clrlwi r4, r4, 31
 ; LE-NEXT:    clrldi r4, r4, 32
 ; LE-NEXT:    sub r3, r3, r4
-; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    srdi r3, r3, 63
 ; LE-NEXT:    bl fn2
 ; LE-NEXT:    nop
 ; LE-NEXT:    addi r1, r1, 32
@@ -77,7 +77,7 @@
 ; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    clrldi r4, r4, 32
 ; CHECK-NEXT:    sub r3, r4, r3
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %and = and i32 %a, 1
diff --git a/llvm/test/CodeGen/PowerPC/testComparesi32leu.ll b/llvm/test/CodeGen/PowerPC/testComparesi32leu.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesi32leu.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesi32leu.ll
@@ -14,7 +14,7 @@
 ; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    clrldi r4, r4, 32
 ; CHECK-NEXT:    sub r3, r4, r3
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    blr
 entry:
diff --git a/llvm/test/CodeGen/PowerPC/testComparesi32ltu.ll b/llvm/test/CodeGen/PowerPC/testComparesi32ltu.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesi32ltu.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesi32ltu.ll
@@ -27,7 +27,7 @@
 ; BE-NEXT:    clrlwi r4, r4, 31
 ; BE-NEXT:    clrldi r4, r4, 32
 ; BE-NEXT:    sub r3, r4, r3
-; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    srdi r3, r3, 63
 ; BE-NEXT:    bl fn2
 ; BE-NEXT:    nop
 ; BE-NEXT:    addi r1, r1, 112
@@ -49,7 +49,7 @@
 ; LE-NEXT:    clrlwi r4, r4, 31
 ; LE-NEXT:    clrldi r4, r4, 32
 ; LE-NEXT:    sub r3, r4, r3
-; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    srdi r3, r3, 63
 ; LE-NEXT:    bl fn2
 ; LE-NEXT:    nop
 ; LE-NEXT:    addi r1, r1, 32
@@ -77,7 +77,7 @@
 ; CHECK-NEXT:    clrldi r3, r3, 32
 ; CHECK-NEXT:    clrldi r4, r4, 32
 ; CHECK-NEXT:    sub r3, r3, r4
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %and = and i32 %a, 1
diff --git a/llvm/test/CodeGen/PowerPC/testComparesieqsll.ll b/llvm/test/CodeGen/PowerPC/testComparesieqsll.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesieqsll.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesieqsll.ll
@@ -21,14 +21,14 @@
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    xor r3, r3, r4
 ; CHECK-BE-NEXT:    cntlzd r3, r3
-; CHECK-BE-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-BE-NEXT:    extrdi r3, r3, 1, 57
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_ieqsll:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    xor r3, r3, r4
 ; CHECK-LE-NEXT:    cntlzd r3, r3
-; CHECK-LE-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-LE-NEXT:    extrdi r3, r3, 1, 57
 ; CHECK-LE-NEXT:    blr
 entry:
   %cmp = icmp eq i64 %a, %b
@@ -73,13 +73,13 @@
 ; CHECK-BE-LABEL: test_ieqsll_z:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cntlzd r3, r3
-; CHECK-BE-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-BE-NEXT:    extrdi r3, r3, 1, 57
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_ieqsll_z:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cntlzd r3, r3
-; CHECK-LE-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-LE-NEXT:    extrdi r3, r3, 1, 57
 ; CHECK-LE-NEXT:    blr
 entry:
   %cmp = icmp eq i64 %a, 0
@@ -127,7 +127,7 @@
 ; CHECK-BE-NEXT:    xor r3, r3, r4
 ; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; CHECK-BE-NEXT:    cntlzd r3, r3
-; CHECK-BE-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-BE-NEXT:    extrdi r3, r3, 1, 57
 ; CHECK-BE-NEXT:    std r3, 0(r4)
 ; CHECK-BE-NEXT:    blr
 ;
@@ -136,7 +136,7 @@
 ; CHECK-LE-NEXT:    xor r3, r3, r4
 ; CHECK-LE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-LE-NEXT:    cntlzd r3, r3
-; CHECK-LE-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-LE-NEXT:    extrdi r3, r3, 1, 57
 ; CHECK-LE-NEXT:    std r3, glob@toc@l(r5)
 ; CHECK-LE-NEXT:    blr
 entry:
@@ -195,7 +195,7 @@
 ; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    cntlzd r3, r3
 ; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
-; CHECK-BE-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-BE-NEXT:    extrdi r3, r3, 1, 57
 ; CHECK-BE-NEXT:    std r3, 0(r4)
 ; CHECK-BE-NEXT:    blr
 ;
@@ -203,7 +203,7 @@
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cntlzd r3, r3
 ; CHECK-LE-NEXT:    addis r4, r2, glob@toc@ha
-; CHECK-LE-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-LE-NEXT:    extrdi r3, r3, 1, 57
 ; CHECK-LE-NEXT:    std r3, glob@toc@l(r4)
 ; CHECK-LE-NEXT:    blr
 entry:
diff --git a/llvm/test/CodeGen/PowerPC/testComparesiequll.ll b/llvm/test/CodeGen/PowerPC/testComparesiequll.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesiequll.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesiequll.ll
@@ -21,14 +21,14 @@
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    xor r3, r3, r4
 ; CHECK-BE-NEXT:    cntlzd r3, r3
-; CHECK-BE-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-BE-NEXT:    extrdi r3, r3, 1, 57
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_iequll:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    xor r3, r3, r4
 ; CHECK-LE-NEXT:    cntlzd r3, r3
-; CHECK-LE-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-LE-NEXT:    extrdi r3, r3, 1, 57
 ; CHECK-LE-NEXT:    blr
 entry:
   %cmp = icmp eq i64 %a, %b
@@ -73,13 +73,13 @@
 ; CHECK-BE-LABEL: test_iequll_z:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cntlzd r3, r3
-; CHECK-BE-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-BE-NEXT:    extrdi r3, r3, 1, 57
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_iequll_z:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cntlzd r3, r3
-; CHECK-LE-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-LE-NEXT:    extrdi r3, r3, 1, 57
 ; CHECK-LE-NEXT:    blr
 entry:
   %cmp = icmp eq i64 %a, 0
@@ -127,7 +127,7 @@
 ; CHECK-BE-NEXT:    xor r3, r3, r4
 ; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; CHECK-BE-NEXT:    cntlzd r3, r3
-; CHECK-BE-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-BE-NEXT:    extrdi r3, r3, 1, 57
 ; CHECK-BE-NEXT:    std r3, 0(r4)
 ; CHECK-BE-NEXT:    blr
 ;
@@ -136,7 +136,7 @@
 ; CHECK-LE-NEXT:    xor r3, r3, r4
 ; CHECK-LE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-LE-NEXT:    cntlzd r3, r3
-; CHECK-LE-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-LE-NEXT:    extrdi r3, r3, 1, 57
 ; CHECK-LE-NEXT:    std r3, glob@toc@l(r5)
 ; CHECK-LE-NEXT:    blr
 entry:
@@ -195,7 +195,7 @@
 ; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    cntlzd r3, r3
 ; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
-; CHECK-BE-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-BE-NEXT:    extrdi r3, r3, 1, 57
 ; CHECK-BE-NEXT:    std r3, 0(r4)
 ; CHECK-BE-NEXT:    blr
 ;
@@ -203,7 +203,7 @@
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cntlzd r3, r3
 ; CHECK-LE-NEXT:    addis r4, r2, glob@toc@ha
-; CHECK-LE-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-LE-NEXT:    extrdi r3, r3, 1, 57
 ; CHECK-LE-NEXT:    std r3, glob@toc@l(r4)
 ; CHECK-LE-NEXT:    blr
 entry:
diff --git a/llvm/test/CodeGen/PowerPC/testComparesigesc.ll b/llvm/test/CodeGen/PowerPC/testComparesigesc.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesigesc.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesigesc.ll
@@ -17,14 +17,14 @@
 ; CHECK-BE-LABEL: test_igesc:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    sub r3, r3, r4
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    xori r3, r3, 1
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_igesc:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sub r3, r3, r4
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    xori r3, r3, 1
 ; CHECK-LE-NEXT:    blr
 entry:
@@ -43,14 +43,14 @@
 ; CHECK-BE-LABEL: test_igesc_sext:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    sub r3, r3, r4
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    addi r3, r3, -1
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_igesc_sext:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sub r3, r3, r4
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    addi r3, r3, -1
 ; CHECK-LE-NEXT:    blr
 entry:
@@ -73,7 +73,7 @@
 ; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sub r3, r3, r4
 ; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    xori r3, r3, 1
 ; CHECK-BE-NEXT:    stb r3, 0(r4)
 ; CHECK-BE-NEXT:    blr
@@ -82,7 +82,7 @@
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sub r3, r3, r4
 ; CHECK-LE-NEXT:    addis r5, r2, glob@toc@ha
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    xori r3, r3, 1
 ; CHECK-LE-NEXT:    stb r3, glob@toc@l(r5)
 ; CHECK-LE-NEXT:    blr
@@ -107,7 +107,7 @@
 ; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sub r3, r3, r4
 ; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    addi r3, r3, -1
 ; CHECK-BE-NEXT:    stb r3, 0(r4)
 ; CHECK-BE-NEXT:    blr
@@ -116,7 +116,7 @@
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sub r3, r3, r4
 ; CHECK-LE-NEXT:    addis r5, r2, glob@toc@ha
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    addi r3, r3, -1
 ; CHECK-LE-NEXT:    stb r3, glob@toc@l(r5)
 ; CHECK-LE-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/testComparesigesi.ll b/llvm/test/CodeGen/PowerPC/testComparesigesi.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesigesi.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesigesi.ll
@@ -17,14 +17,14 @@
 ; CHECK-BE-LABEL: test_igesi:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    sub r3, r3, r4
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    xori r3, r3, 1
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_igesi:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sub r3, r3, r4
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    xori r3, r3, 1
 ; CHECK-LE-NEXT:    blr
 entry:
@@ -43,14 +43,14 @@
 ; CHECK-BE-LABEL: test_igesi_sext:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    sub r3, r3, r4
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    addi r3, r3, -1
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_igesi_sext:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sub r3, r3, r4
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    addi r3, r3, -1
 ; CHECK-LE-NEXT:    blr
 entry:
@@ -73,7 +73,7 @@
 ; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sub r3, r3, r4
 ; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    xori r3, r3, 1
 ; CHECK-BE-NEXT:    stw r3, 0(r4)
 ; CHECK-BE-NEXT:    blr
@@ -82,7 +82,7 @@
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sub r3, r3, r4
 ; CHECK-LE-NEXT:    addis r5, r2, glob@toc@ha
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    xori r3, r3, 1
 ; CHECK-LE-NEXT:    stw r3, glob@toc@l(r5)
 ; CHECK-LE-NEXT:    blr
@@ -107,7 +107,7 @@
 ; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sub r3, r3, r4
 ; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    addi r3, r3, -1
 ; CHECK-BE-NEXT:    stw r3, 0(r4)
 ; CHECK-BE-NEXT:    blr
@@ -116,7 +116,7 @@
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sub r3, r3, r4
 ; CHECK-LE-NEXT:    addis r5, r2, glob@toc@ha
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    addi r3, r3, -1
 ; CHECK-LE-NEXT:    stw r3, glob@toc@l(r5)
 ; CHECK-LE-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/testComparesigesll.ll b/llvm/test/CodeGen/PowerPC/testComparesigesll.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesigesll.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesigesll.ll
@@ -18,7 +18,7 @@
 ; CHECK-BE-LABEL: test_igesll:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    sradi r5, r3, 63
-; CHECK-BE-NEXT:    rldicl r6, r4, 1, 63
+; CHECK-BE-NEXT:    srdi r6, r4, 63
 ; CHECK-BE-NEXT:    subc r3, r3, r4
 ; CHECK-BE-NEXT:    adde r3, r5, r6
 ; CHECK-BE-NEXT:    blr
@@ -26,7 +26,7 @@
 ; CHECK-LE-LABEL: test_igesll:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sradi r5, r3, 63
-; CHECK-LE-NEXT:    rldicl r6, r4, 1, 63
+; CHECK-LE-NEXT:    srdi r6, r4, 63
 ; CHECK-LE-NEXT:    subc r3, r3, r4
 ; CHECK-LE-NEXT:    adde r3, r5, r6
 ; CHECK-LE-NEXT:    blr
@@ -48,7 +48,7 @@
 ; CHECK-BE-LABEL: test_igesll_sext:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    sradi r5, r3, 63
-; CHECK-BE-NEXT:    rldicl r6, r4, 1, 63
+; CHECK-BE-NEXT:    srdi r6, r4, 63
 ; CHECK-BE-NEXT:    subc r3, r3, r4
 ; CHECK-BE-NEXT:    adde r3, r5, r6
 ; CHECK-BE-NEXT:    neg r3, r3
@@ -57,7 +57,7 @@
 ; CHECK-LE-LABEL: test_igesll_sext:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sradi r5, r3, 63
-; CHECK-LE-NEXT:    rldicl r6, r4, 1, 63
+; CHECK-LE-NEXT:    srdi r6, r4, 63
 ; CHECK-LE-NEXT:    subc r3, r3, r4
 ; CHECK-LE-NEXT:    adde r3, r5, r6
 ; CHECK-LE-NEXT:    neg r3, r3
@@ -77,13 +77,13 @@
 ; CHECK-BE-LABEL: test_igesll_z:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    not r3, r3
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_igesll_z:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    not r3, r3
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    blr
 entry:
   %cmp = icmp sgt i64 %a, -1
@@ -130,7 +130,7 @@
 ; CHECK-BE-NEXT:    sradi r6, r3, 63
 ; CHECK-BE-NEXT:    ld r5, .LC0@toc@l(r5)
 ; CHECK-BE-NEXT:    subc r3, r3, r4
-; CHECK-BE-NEXT:    rldicl r3, r4, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r4, 63
 ; CHECK-BE-NEXT:    adde r3, r6, r3
 ; CHECK-BE-NEXT:    std r3, 0(r5)
 ; CHECK-BE-NEXT:    blr
@@ -140,7 +140,7 @@
 ; CHECK-LE-NEXT:    sradi r6, r3, 63
 ; CHECK-LE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-LE-NEXT:    subc r3, r3, r4
-; CHECK-LE-NEXT:    rldicl r3, r4, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r4, 63
 ; CHECK-LE-NEXT:    adde r3, r6, r3
 ; CHECK-LE-NEXT:    std r3, glob@toc@l(r5)
 ; CHECK-LE-NEXT:    blr
@@ -167,7 +167,7 @@
 ; CHECK-BE-NEXT:    sradi r6, r3, 63
 ; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    subc r3, r3, r4
-; CHECK-BE-NEXT:    rldicl r3, r4, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r4, 63
 ; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; CHECK-BE-NEXT:    adde r3, r6, r3
 ; CHECK-BE-NEXT:    neg r3, r3
@@ -179,7 +179,7 @@
 ; CHECK-LE-NEXT:    sradi r6, r3, 63
 ; CHECK-LE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-LE-NEXT:    subc r3, r3, r4
-; CHECK-LE-NEXT:    rldicl r3, r4, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r4, 63
 ; CHECK-LE-NEXT:    adde r3, r6, r3
 ; CHECK-LE-NEXT:    neg r3, r3
 ; CHECK-LE-NEXT:    std r3, glob@toc@l(r5)
@@ -204,7 +204,7 @@
 ; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    not r3, r3
 ; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    std r3, 0(r4)
 ; CHECK-BE-NEXT:    blr
 ;
@@ -212,7 +212,7 @@
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    not r3, r3
 ; CHECK-LE-NEXT:    addis r4, r2, glob@toc@ha
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    std r3, glob@toc@l(r4)
 ; CHECK-LE-NEXT:    blr
 entry:
diff --git a/llvm/test/CodeGen/PowerPC/testComparesigess.ll b/llvm/test/CodeGen/PowerPC/testComparesigess.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesigess.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesigess.ll
@@ -17,14 +17,14 @@
 ; CHECK-BE-LABEL: test_igess:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    sub r3, r3, r4
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    xori r3, r3, 1
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_igess:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sub r3, r3, r4
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    xori r3, r3, 1
 ; CHECK-LE-NEXT:    blr
 entry:
@@ -43,14 +43,14 @@
 ; CHECK-BE-LABEL: test_igess_sext:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    sub r3, r3, r4
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    addi r3, r3, -1
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_igess_sext:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sub r3, r3, r4
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    addi r3, r3, -1
 ; CHECK-LE-NEXT:    blr
 entry:
@@ -73,7 +73,7 @@
 ; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sub r3, r3, r4
 ; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    xori r3, r3, 1
 ; CHECK-BE-NEXT:    sth r3, 0(r4)
 ; CHECK-BE-NEXT:    blr
@@ -82,7 +82,7 @@
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sub r3, r3, r4
 ; CHECK-LE-NEXT:    addis r5, r2, glob@toc@ha
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    xori r3, r3, 1
 ; CHECK-LE-NEXT:    sth r3, glob@toc@l(r5)
 ; CHECK-LE-NEXT:    blr
@@ -107,7 +107,7 @@
 ; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sub r3, r3, r4
 ; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    addi r3, r3, -1
 ; CHECK-BE-NEXT:    sth r3, 0(r4)
 ; CHECK-BE-NEXT:    blr
@@ -116,7 +116,7 @@
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sub r3, r3, r4
 ; CHECK-LE-NEXT:    addis r5, r2, glob@toc@ha
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    addi r3, r3, -1
 ; CHECK-LE-NEXT:    sth r3, glob@toc@l(r5)
 ; CHECK-LE-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/testComparesigeuc.ll b/llvm/test/CodeGen/PowerPC/testComparesigeuc.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesigeuc.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesigeuc.ll
@@ -16,7 +16,7 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    not r3, r3
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i8 %a, %b
@@ -29,7 +29,7 @@
 ; CHECK-LABEL: test_igeuc_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    addi r3, r3, -1
 ; CHECK-NEXT:    blr
 entry:
@@ -71,7 +71,7 @@
 ; BE-NEXT:    sub r3, r3, r4
 ; BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; BE-NEXT:    not r3, r3
-; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    srdi r3, r3, 63
 ; BE-NEXT:    stb r3, 0(r4)
 ; BE-NEXT:    blr
 ;
@@ -80,7 +80,7 @@
 ; LE-NEXT:    sub r3, r3, r4
 ; LE-NEXT:    addis r5, r2, glob@toc@ha
 ; LE-NEXT:    not r3, r3
-; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    srdi r3, r3, 63
 ; LE-NEXT:    stb r3, glob@toc@l(r5)
 ; LE-NEXT:    blr
 entry:
@@ -98,7 +98,7 @@
 ; BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; BE-NEXT:    sub r3, r3, r4
 ; BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    srdi r3, r3, 63
 ; BE-NEXT:    addi r3, r3, -1
 ; BE-NEXT:    stb r3, 0(r4)
 ; BE-NEXT:    blr
@@ -107,7 +107,7 @@
 ; LE:       # %bb.0: # %entry
 ; LE-NEXT:    sub r3, r3, r4
 ; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    srdi r3, r3, 63
 ; LE-NEXT:    addi r3, r3, -1
 ; LE-NEXT:    stb r3, glob@toc@l(r5)
 ; LE-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/testComparesigeui.ll b/llvm/test/CodeGen/PowerPC/testComparesigeui.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesigeui.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesigeui.ll
@@ -16,7 +16,7 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    not r3, r3
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i32 %a, %b
@@ -29,7 +29,7 @@
 ; CHECK-LABEL: test_igeui_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    addi r3, r3, -1
 ; CHECK-NEXT:    blr
 entry:
@@ -70,7 +70,7 @@
 ; BE-NEXT:    sub r3, r3, r4
 ; BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; BE-NEXT:    not r3, r3
-; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    srdi r3, r3, 63
 ; BE-NEXT:    stw r3, 0(r4)
 ; BE-NEXT:    blr
 ;
@@ -79,7 +79,7 @@
 ; LE-NEXT:    sub r3, r3, r4
 ; LE-NEXT:    addis r5, r2, glob@toc@ha
 ; LE-NEXT:    not r3, r3
-; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    srdi r3, r3, 63
 ; LE-NEXT:    stw r3, glob@toc@l(r5)
 ; LE-NEXT:    blr
 entry:
@@ -97,7 +97,7 @@
 ; BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; BE-NEXT:    sub r3, r3, r4
 ; BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    srdi r3, r3, 63
 ; BE-NEXT:    addi r3, r3, -1
 ; BE-NEXT:    stw r3, 0(r4)
 ; BE-NEXT:    blr
@@ -106,7 +106,7 @@
 ; LE:       # %bb.0: # %entry
 ; LE-NEXT:    sub r3, r3, r4
 ; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    srdi r3, r3, 63
 ; LE-NEXT:    addi r3, r3, -1
 ; LE-NEXT:    stw r3, glob@toc@l(r5)
 ; LE-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/testComparesigeus.ll b/llvm/test/CodeGen/PowerPC/testComparesigeus.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesigeus.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesigeus.ll
@@ -16,7 +16,7 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    not r3, r3
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i16 %a, %b
@@ -29,7 +29,7 @@
 ; CHECK-LABEL: test_igeus_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    addi r3, r3, -1
 ; CHECK-NEXT:    blr
 entry:
@@ -70,7 +70,7 @@
 ; BE-NEXT:    sub r3, r3, r4
 ; BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; BE-NEXT:    not r3, r3
-; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    srdi r3, r3, 63
 ; BE-NEXT:    sth r3, 0(r4)
 ; BE-NEXT:    blr
 ;
@@ -79,7 +79,7 @@
 ; LE-NEXT:    sub r3, r3, r4
 ; LE-NEXT:    addis r5, r2, glob@toc@ha
 ; LE-NEXT:    not r3, r3
-; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    srdi r3, r3, 63
 ; LE-NEXT:    sth r3, glob@toc@l(r5)
 ; LE-NEXT:    blr
 entry:
@@ -97,7 +97,7 @@
 ; BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; BE-NEXT:    sub r3, r3, r4
 ; BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    srdi r3, r3, 63
 ; BE-NEXT:    addi r3, r3, -1
 ; BE-NEXT:    sth r3, 0(r4)
 ; BE-NEXT:    blr
@@ -106,7 +106,7 @@
 ; LE:       # %bb.0: # %entry
 ; LE-NEXT:    sub r3, r3, r4
 ; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    srdi r3, r3, 63
 ; LE-NEXT:    addi r3, r3, -1
 ; LE-NEXT:    sth r3, glob@toc@l(r5)
 ; LE-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/testComparesigtsc.ll b/llvm/test/CodeGen/PowerPC/testComparesigtsc.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesigtsc.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesigtsc.ll
@@ -13,7 +13,7 @@
 ; CHECK-LABEL: test_igtsc:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i8 %a, %b
@@ -40,7 +40,7 @@
 ; CHECK-LABEL: test_igtsc_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    neg r3, r3
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i8 %a, 0
@@ -68,7 +68,7 @@
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    stb r3, 0(r5)
 ; CHECK-NEXT:    blr
 entry:
@@ -103,7 +103,7 @@
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    stb r3, 0(r4)
 ; CHECK-NEXT:    blr
 entry:
diff --git a/llvm/test/CodeGen/PowerPC/testComparesigtsi.ll b/llvm/test/CodeGen/PowerPC/testComparesigtsi.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesigtsi.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesigtsi.ll
@@ -13,7 +13,7 @@
 ; CHECK-LABEL: test_igtsi:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i32 %a, %b
@@ -40,7 +40,7 @@
 ; CHECK-LABEL: test_igtsi_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    neg r3, r3
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i32 %a, 0
@@ -68,7 +68,7 @@
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    stw r3, 0(r5)
 ; CHECK-NEXT:    blr
 entry:
@@ -103,7 +103,7 @@
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    stw r3, 0(r4)
 ; CHECK-NEXT:    blr
 entry:
diff --git a/llvm/test/CodeGen/PowerPC/testComparesigtsll.ll b/llvm/test/CodeGen/PowerPC/testComparesigtsll.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesigtsll.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesigtsll.ll
@@ -13,7 +13,7 @@
 ; CHECK-LABEL: test_igtsll:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r5, r4, 63
-; CHECK-NEXT:    rldicl r6, r3, 1, 63
+; CHECK-NEXT:    srdi r6, r3, 63
 ; CHECK-NEXT:    subc r3, r4, r3
 ; CHECK-NEXT:    adde r3, r6, r5
 ; CHECK-NEXT:    xori r3, r3, 1
@@ -29,7 +29,7 @@
 ; CHECK-LABEL: test_igtsll_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r5, r4, 63
-; CHECK-NEXT:    rldicl r6, r3, 1, 63
+; CHECK-NEXT:    srdi r6, r3, 63
 ; CHECK-NEXT:    subc r3, r4, r3
 ; CHECK-NEXT:    adde r3, r6, r5
 ; CHECK-NEXT:    xori r3, r3, 1
@@ -48,7 +48,7 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addi r4, r3, -1
 ; CHECK-NEXT:    nor r3, r4, r3
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i64 %a, 0
@@ -77,7 +77,7 @@
 ; CHECK-NEXT:    sradi r6, r4, 63
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    subc r4, r4, r3
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
 ; CHECK-NEXT:    adde r3, r3, r6
 ; CHECK-NEXT:    xori r3, r3, 1
@@ -98,7 +98,7 @@
 ; CHECK-NEXT:    sradi r6, r4, 63
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    subc r4, r4, r3
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    adde r3, r3, r6
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
 ; CHECK-NEXT:    xori r3, r3, 1
@@ -122,7 +122,7 @@
 ; CHECK-NEXT:    addi r5, r3, -1
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
 ; CHECK-NEXT:    nor r3, r5, r3
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    std r3, 0(r4)
 ; CHECK-NEXT:    blr
 entry:
diff --git a/llvm/test/CodeGen/PowerPC/testComparesigtss.ll b/llvm/test/CodeGen/PowerPC/testComparesigtss.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesigtss.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesigtss.ll
@@ -13,7 +13,7 @@
 ; CHECK-LABEL: test_igtss:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i16 %a, %b
@@ -40,7 +40,7 @@
 ; CHECK-LABEL: test_igtss_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    neg r3, r3
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i16 %a, 0
@@ -68,7 +68,7 @@
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    sth r3, 0(r5)
 ; CHECK-NEXT:    blr
 entry:
@@ -103,7 +103,7 @@
 ; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-NEXT:    neg r3, r3
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    sth r3, 0(r4)
 ; CHECK-NEXT:    blr
 entry:
diff --git a/llvm/test/CodeGen/PowerPC/testComparesigtuc.ll b/llvm/test/CodeGen/PowerPC/testComparesigtuc.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesigtuc.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesigtuc.ll
@@ -13,7 +13,7 @@
 ; CHECK-LABEL: test_igtuc:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ugt i8 %a, %b
@@ -70,7 +70,7 @@
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    stb r3, 0(r5)
 ; CHECK-NEXT:    blr
 entry:
diff --git a/llvm/test/CodeGen/PowerPC/testComparesigtui.ll b/llvm/test/CodeGen/PowerPC/testComparesigtui.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesigtui.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesigtui.ll
@@ -13,7 +13,7 @@
 ; CHECK-LABEL: test_igtui:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ugt i32 %a, %b
@@ -70,7 +70,7 @@
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    stw r3, 0(r5)
 ; CHECK-NEXT:    blr
 entry:
diff --git a/llvm/test/CodeGen/PowerPC/testComparesigtus.ll b/llvm/test/CodeGen/PowerPC/testComparesigtus.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesigtus.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesigtus.ll
@@ -13,7 +13,7 @@
 ; CHECK-LABEL: test_igtus:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ugt i16 %a, %b
@@ -70,7 +70,7 @@
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    sth r3, 0(r5)
 ; CHECK-NEXT:    blr
 entry:
diff --git a/llvm/test/CodeGen/PowerPC/testComparesilesc.ll b/llvm/test/CodeGen/PowerPC/testComparesilesc.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesilesc.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesilesc.ll
@@ -17,14 +17,14 @@
 ; CHECK-BE-LABEL: test_ilesc:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    sub r3, r4, r3
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    xori r3, r3, 1
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_ilesc:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sub r3, r4, r3
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    xori r3, r3, 1
 ; CHECK-LE-NEXT:    blr
 entry:
@@ -43,14 +43,14 @@
 ; CHECK-BE-LABEL: test_ilesc_sext:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    sub r3, r4, r3
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    addi r3, r3, -1
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_ilesc_sext:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sub r3, r4, r3
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    addi r3, r3, -1
 ; CHECK-LE-NEXT:    blr
 entry:
@@ -73,7 +73,7 @@
 ; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sub r3, r4, r3
 ; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    xori r3, r3, 1
 ; CHECK-BE-NEXT:    stb r3, 0(r4)
 ; CHECK-BE-NEXT:    blr
@@ -82,7 +82,7 @@
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sub r3, r4, r3
 ; CHECK-LE-NEXT:    addis r5, r2, glob@toc@ha
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    xori r3, r3, 1
 ; CHECK-LE-NEXT:    stb r3, glob@toc@l(r5)
 ; CHECK-LE-NEXT:    blr
@@ -107,7 +107,7 @@
 ; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sub r3, r4, r3
 ; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    addi r3, r3, -1
 ; CHECK-BE-NEXT:    stb r3, 0(r4)
 ; CHECK-BE-NEXT:    blr
@@ -116,7 +116,7 @@
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sub r3, r4, r3
 ; CHECK-LE-NEXT:    addis r5, r2, glob@toc@ha
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    addi r3, r3, -1
 ; CHECK-LE-NEXT:    stb r3, glob@toc@l(r5)
 ; CHECK-LE-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/testComparesilesi.ll b/llvm/test/CodeGen/PowerPC/testComparesilesi.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesilesi.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesilesi.ll
@@ -17,14 +17,14 @@
 ; CHECK-BE-LABEL: test_ilesi:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    sub r3, r4, r3
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    xori r3, r3, 1
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_ilesi:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sub r3, r4, r3
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    xori r3, r3, 1
 ; CHECK-LE-NEXT:    blr
 entry:
@@ -43,14 +43,14 @@
 ; CHECK-BE-LABEL: test_ilesi_sext:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    sub r3, r4, r3
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    addi r3, r3, -1
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_ilesi_sext:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sub r3, r4, r3
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    addi r3, r3, -1
 ; CHECK-LE-NEXT:    blr
 entry:
@@ -73,7 +73,7 @@
 ; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sub r3, r4, r3
 ; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    xori r3, r3, 1
 ; CHECK-BE-NEXT:    stw r3, 0(r4)
 ; CHECK-BE-NEXT:    blr
@@ -82,7 +82,7 @@
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sub r3, r4, r3
 ; CHECK-LE-NEXT:    addis r5, r2, glob@toc@ha
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    xori r3, r3, 1
 ; CHECK-LE-NEXT:    stw r3, glob@toc@l(r5)
 ; CHECK-LE-NEXT:    blr
@@ -107,7 +107,7 @@
 ; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sub r3, r4, r3
 ; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    addi r3, r3, -1
 ; CHECK-BE-NEXT:    stw r3, 0(r4)
 ; CHECK-BE-NEXT:    blr
@@ -116,7 +116,7 @@
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sub r3, r4, r3
 ; CHECK-LE-NEXT:    addis r5, r2, glob@toc@ha
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    addi r3, r3, -1
 ; CHECK-LE-NEXT:    stw r3, glob@toc@l(r5)
 ; CHECK-LE-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/testComparesilesll.ll b/llvm/test/CodeGen/PowerPC/testComparesilesll.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesilesll.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesilesll.ll
@@ -18,7 +18,7 @@
 ; CHECK-BE-LABEL: test_ilesll:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    sradi r5, r4, 63
-; CHECK-BE-NEXT:    rldicl r6, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r6, r3, 63
 ; CHECK-BE-NEXT:    subc r3, r4, r3
 ; CHECK-BE-NEXT:    adde r3, r5, r6
 ; CHECK-BE-NEXT:    blr
@@ -26,7 +26,7 @@
 ; CHECK-LE-LABEL: test_ilesll:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sradi r5, r4, 63
-; CHECK-LE-NEXT:    rldicl r6, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r6, r3, 63
 ; CHECK-LE-NEXT:    subc r3, r4, r3
 ; CHECK-LE-NEXT:    adde r3, r5, r6
 ; CHECK-LE-NEXT:    blr
@@ -48,7 +48,7 @@
 ; CHECK-BE-LABEL: test_ilesll_sext:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    sradi r5, r4, 63
-; CHECK-BE-NEXT:    rldicl r6, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r6, r3, 63
 ; CHECK-BE-NEXT:    subc r3, r4, r3
 ; CHECK-BE-NEXT:    adde r3, r5, r6
 ; CHECK-BE-NEXT:    neg r3, r3
@@ -57,7 +57,7 @@
 ; CHECK-LE-LABEL: test_ilesll_sext:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sradi r5, r4, 63
-; CHECK-LE-NEXT:    rldicl r6, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r6, r3, 63
 ; CHECK-LE-NEXT:    subc r3, r4, r3
 ; CHECK-LE-NEXT:    adde r3, r5, r6
 ; CHECK-LE-NEXT:    neg r3, r3
@@ -79,14 +79,14 @@
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addi r4, r3, -1
 ; CHECK-BE-NEXT:    or r3, r4, r3
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_ilesll_z:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    addi r4, r3, -1
 ; CHECK-LE-NEXT:    or r3, r4, r3
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    blr
 entry:
   %cmp = icmp slt i64 %a, 1
@@ -136,7 +136,7 @@
 ; CHECK-BE-NEXT:    sradi r6, r4, 63
 ; CHECK-BE-NEXT:    ld r5, .LC0@toc@l(r5)
 ; CHECK-BE-NEXT:    subc r4, r4, r3
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    adde r3, r6, r3
 ; CHECK-BE-NEXT:    std r3, 0(r5)
 ; CHECK-BE-NEXT:    blr
@@ -146,7 +146,7 @@
 ; CHECK-LE-NEXT:    sradi r6, r4, 63
 ; CHECK-LE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-LE-NEXT:    subc r4, r4, r3
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    adde r3, r6, r3
 ; CHECK-LE-NEXT:    std r3, glob@toc@l(r5)
 ; CHECK-LE-NEXT:    blr
@@ -173,7 +173,7 @@
 ; CHECK-BE-NEXT:    sradi r6, r4, 63
 ; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    subc r4, r4, r3
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; CHECK-BE-NEXT:    adde r3, r6, r3
 ; CHECK-BE-NEXT:    neg r3, r3
@@ -185,7 +185,7 @@
 ; CHECK-LE-NEXT:    sradi r6, r4, 63
 ; CHECK-LE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-LE-NEXT:    subc r4, r4, r3
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    adde r3, r6, r3
 ; CHECK-LE-NEXT:    neg r3, r3
 ; CHECK-LE-NEXT:    std r3, glob@toc@l(r5)
@@ -212,7 +212,7 @@
 ; CHECK-BE-NEXT:    addi r5, r3, -1
 ; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
 ; CHECK-BE-NEXT:    or r3, r5, r3
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    std r3, 0(r4)
 ; CHECK-BE-NEXT:    blr
 ;
@@ -221,7 +221,7 @@
 ; CHECK-LE-NEXT:    addi r5, r3, -1
 ; CHECK-LE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-LE-NEXT:    or r3, r5, r3
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    std r3, glob@toc@l(r4)
 ; CHECK-LE-NEXT:    blr
 entry:
diff --git a/llvm/test/CodeGen/PowerPC/testComparesiless.ll b/llvm/test/CodeGen/PowerPC/testComparesiless.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesiless.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesiless.ll
@@ -17,14 +17,14 @@
 ; CHECK-BE-LABEL: test_iless:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    sub r3, r4, r3
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    xori r3, r3, 1
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_iless:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sub r3, r4, r3
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    xori r3, r3, 1
 ; CHECK-LE-NEXT:    blr
 entry:
@@ -43,14 +43,14 @@
 ; CHECK-BE-LABEL: test_iless_sext:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    sub r3, r4, r3
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    addi r3, r3, -1
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_iless_sext:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sub r3, r4, r3
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    addi r3, r3, -1
 ; CHECK-LE-NEXT:    blr
 entry:
@@ -73,7 +73,7 @@
 ; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sub r3, r4, r3
 ; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    xori r3, r3, 1
 ; CHECK-BE-NEXT:    sth r3, 0(r4)
 ; CHECK-BE-NEXT:    blr
@@ -82,7 +82,7 @@
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sub r3, r4, r3
 ; CHECK-LE-NEXT:    addis r5, r2, glob@toc@ha
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    xori r3, r3, 1
 ; CHECK-LE-NEXT:    sth r3, glob@toc@l(r5)
 ; CHECK-LE-NEXT:    blr
@@ -107,7 +107,7 @@
 ; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sub r3, r4, r3
 ; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    addi r3, r3, -1
 ; CHECK-BE-NEXT:    sth r3, 0(r4)
 ; CHECK-BE-NEXT:    blr
@@ -116,7 +116,7 @@
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sub r3, r4, r3
 ; CHECK-LE-NEXT:    addis r5, r2, glob@toc@ha
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    addi r3, r3, -1
 ; CHECK-LE-NEXT:    sth r3, glob@toc@l(r5)
 ; CHECK-LE-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/testComparesileuc.ll b/llvm/test/CodeGen/PowerPC/testComparesileuc.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesileuc.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesileuc.ll
@@ -16,7 +16,7 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    not r3, r3
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i8 %a, %b
@@ -29,7 +29,7 @@
 ; CHECK-LABEL: test_ileuc_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    addi r3, r3, -1
 ; CHECK-NEXT:    blr
 entry:
@@ -73,7 +73,7 @@
 ; BE-NEXT:    sub r3, r4, r3
 ; BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; BE-NEXT:    not r3, r3
-; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    srdi r3, r3, 63
 ; BE-NEXT:    stb r3, 0(r4)
 ; BE-NEXT:    blr
 ;
@@ -82,7 +82,7 @@
 ; LE-NEXT:    sub r3, r4, r3
 ; LE-NEXT:    addis r5, r2, glob@toc@ha
 ; LE-NEXT:    not r3, r3
-; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    srdi r3, r3, 63
 ; LE-NEXT:    stb r3, glob@toc@l(r5)
 ; LE-NEXT:    blr
 entry:
@@ -99,7 +99,7 @@
 ; BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; BE-NEXT:    sub r3, r4, r3
 ; BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    srdi r3, r3, 63
 ; BE-NEXT:    addi r3, r3, -1
 ; BE-NEXT:    stb r3, 0(r4)
 ; BE-NEXT:    blr
@@ -108,7 +108,7 @@
 ; LE:       # %bb.0: # %entry
 ; LE-NEXT:    sub r3, r4, r3
 ; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    srdi r3, r3, 63
 ; LE-NEXT:    addi r3, r3, -1
 ; LE-NEXT:    stb r3, glob@toc@l(r5)
 ; LE-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/testComparesileui.ll b/llvm/test/CodeGen/PowerPC/testComparesileui.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesileui.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesileui.ll
@@ -16,7 +16,7 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    not r3, r3
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i32 %a, %b
@@ -29,7 +29,7 @@
 ; CHECK-LABEL: test_ileui_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    addi r3, r3, -1
 ; CHECK-NEXT:    blr
 entry:
@@ -73,7 +73,7 @@
 ; BE-NEXT:    sub r3, r4, r3
 ; BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; BE-NEXT:    not r3, r3
-; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    srdi r3, r3, 63
 ; BE-NEXT:    stw r3, 0(r4)
 ; BE-NEXT:    blr
 ;
@@ -82,7 +82,7 @@
 ; LE-NEXT:    sub r3, r4, r3
 ; LE-NEXT:    addis r5, r2, glob@toc@ha
 ; LE-NEXT:    not r3, r3
-; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    srdi r3, r3, 63
 ; LE-NEXT:    stw r3, glob@toc@l(r5)
 ; LE-NEXT:    blr
 entry:
@@ -99,7 +99,7 @@
 ; BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; BE-NEXT:    sub r3, r4, r3
 ; BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    srdi r3, r3, 63
 ; BE-NEXT:    addi r3, r3, -1
 ; BE-NEXT:    stw r3, 0(r4)
 ; BE-NEXT:    blr
@@ -108,7 +108,7 @@
 ; LE:       # %bb.0: # %entry
 ; LE-NEXT:    sub r3, r4, r3
 ; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    srdi r3, r3, 63
 ; LE-NEXT:    addi r3, r3, -1
 ; LE-NEXT:    stw r3, glob@toc@l(r5)
 ; LE-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/testComparesileull.ll b/llvm/test/CodeGen/PowerPC/testComparesileull.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesileull.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesileull.ll
@@ -43,7 +43,7 @@
 ; CHECK-LABEL: test_ileull_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzd r3, r3
-; CHECK-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-NEXT:    extrdi r3, r3, 1, 57
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i64 %a, 0
@@ -125,7 +125,7 @@
 ; BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; BE-NEXT:    cntlzd r3, r3
 ; BE-NEXT:    ld r4, .LC0@toc@l(r4)
-; BE-NEXT:    rldicl r3, r3, 58, 63
+; BE-NEXT:    extrdi r3, r3, 1, 57
 ; BE-NEXT:    std r3, 0(r4)
 ; BE-NEXT:    blr
 ;
@@ -133,7 +133,7 @@
 ; LE:       # %bb.0: # %entry
 ; LE-NEXT:    cntlzd r3, r3
 ; LE-NEXT:    addis r4, r2, glob@toc@ha
-; LE-NEXT:    rldicl r3, r3, 58, 63
+; LE-NEXT:    extrdi r3, r3, 1, 57
 ; LE-NEXT:    std r3, glob@toc@l(r4)
 ; LE-NEXT:    blr
 entry:
diff --git a/llvm/test/CodeGen/PowerPC/testComparesileus.ll b/llvm/test/CodeGen/PowerPC/testComparesileus.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesileus.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesileus.ll
@@ -16,7 +16,7 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    not r3, r3
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i16 %a, %b
@@ -29,7 +29,7 @@
 ; CHECK-LABEL: test_ileus_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    addi r3, r3, -1
 ; CHECK-NEXT:    blr
 entry:
@@ -73,7 +73,7 @@
 ; BE-NEXT:    sub r3, r4, r3
 ; BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; BE-NEXT:    not r3, r3
-; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    srdi r3, r3, 63
 ; BE-NEXT:    sth r3, 0(r4)
 ; BE-NEXT:    blr
 ;
@@ -82,7 +82,7 @@
 ; LE-NEXT:    sub r3, r4, r3
 ; LE-NEXT:    addis r5, r2, glob@toc@ha
 ; LE-NEXT:    not r3, r3
-; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    srdi r3, r3, 63
 ; LE-NEXT:    sth r3, glob@toc@l(r5)
 ; LE-NEXT:    blr
 entry:
@@ -99,7 +99,7 @@
 ; BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; BE-NEXT:    sub r3, r4, r3
 ; BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    srdi r3, r3, 63
 ; BE-NEXT:    addi r3, r3, -1
 ; BE-NEXT:    sth r3, 0(r4)
 ; BE-NEXT:    blr
@@ -108,7 +108,7 @@
 ; LE:       # %bb.0: # %entry
 ; LE-NEXT:    sub r3, r4, r3
 ; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    srdi r3, r3, 63
 ; LE-NEXT:    addi r3, r3, -1
 ; LE-NEXT:    sth r3, glob@toc@l(r5)
 ; LE-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/testComparesiltsc.ll b/llvm/test/CodeGen/PowerPC/testComparesiltsc.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesiltsc.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesiltsc.ll
@@ -15,7 +15,7 @@
 ; CHECK-LABEL: test_iltsc:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp slt i8 %a, %b
@@ -55,7 +55,7 @@
 ; BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; BE-NEXT:    sub r3, r3, r4
 ; BE-NEXT:    ld r5, .LC0@toc@l(r5)
-; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    srdi r3, r3, 63
 ; BE-NEXT:    stb r3, 0(r5)
 ; BE-NEXT:    blr
 ;
@@ -63,7 +63,7 @@
 ; LE:       # %bb.0: # %entry
 ; LE-NEXT:    sub r3, r3, r4
 ; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    srdi r3, r3, 63
 ; LE-NEXT:    stb r3, glob@toc@l(r5)
 ; LE-NEXT:    blr
 entry:
diff --git a/llvm/test/CodeGen/PowerPC/testComparesiltsi.ll b/llvm/test/CodeGen/PowerPC/testComparesiltsi.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesiltsi.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesiltsi.ll
@@ -15,7 +15,7 @@
 ; CHECK-LABEL: test_iltsi:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp slt i32 %a, %b
@@ -55,7 +55,7 @@
 ; BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; BE-NEXT:    sub r3, r3, r4
 ; BE-NEXT:    ld r5, .LC0@toc@l(r5)
-; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    srdi r3, r3, 63
 ; BE-NEXT:    stw r3, 0(r5)
 ; BE-NEXT:    blr
 ;
@@ -63,7 +63,7 @@
 ; LE:       # %bb.0: # %entry
 ; LE-NEXT:    sub r3, r3, r4
 ; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    srdi r3, r3, 63
 ; LE-NEXT:    stw r3, glob@toc@l(r5)
 ; LE-NEXT:    blr
 entry:
diff --git a/llvm/test/CodeGen/PowerPC/testComparesiltsll.ll b/llvm/test/CodeGen/PowerPC/testComparesiltsll.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesiltsll.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesiltsll.ll
@@ -15,7 +15,7 @@
 ; CHECK-LABEL: test_iltsll:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r5, r3, 63
-; CHECK-NEXT:    rldicl r6, r4, 1, 63
+; CHECK-NEXT:    srdi r6, r4, 63
 ; CHECK-NEXT:    subc r3, r3, r4
 ; CHECK-NEXT:    adde r3, r6, r5
 ; CHECK-NEXT:    xori r3, r3, 1
@@ -31,7 +31,7 @@
 ; CHECK-LABEL: test_iltsll_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r5, r3, 63
-; CHECK-NEXT:    rldicl r6, r4, 1, 63
+; CHECK-NEXT:    srdi r6, r4, 63
 ; CHECK-NEXT:    subc r3, r3, r4
 ; CHECK-NEXT:    adde r3, r6, r5
 ; CHECK-NEXT:    xori r3, r3, 1
@@ -62,7 +62,7 @@
 ; BE-NEXT:    sradi r6, r3, 63
 ; BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; BE-NEXT:    subc r3, r3, r4
-; BE-NEXT:    rldicl r3, r4, 1, 63
+; BE-NEXT:    srdi r3, r4, 63
 ; BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; BE-NEXT:    adde r3, r3, r6
 ; BE-NEXT:    xori r3, r3, 1
@@ -74,7 +74,7 @@
 ; LE-NEXT:    sradi r6, r3, 63
 ; LE-NEXT:    addis r5, r2, glob@toc@ha
 ; LE-NEXT:    subc r3, r3, r4
-; LE-NEXT:    rldicl r3, r4, 1, 63
+; LE-NEXT:    srdi r3, r4, 63
 ; LE-NEXT:    adde r3, r3, r6
 ; LE-NEXT:    xori r3, r3, 1
 ; LE-NEXT:    std r3, glob@toc@l(r5)
@@ -94,7 +94,7 @@
 ; BE-NEXT:    sradi r6, r3, 63
 ; BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; BE-NEXT:    subc r3, r3, r4
-; BE-NEXT:    rldicl r3, r4, 1, 63
+; BE-NEXT:    srdi r3, r4, 63
 ; BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; BE-NEXT:    adde r3, r3, r6
 ; BE-NEXT:    xori r3, r3, 1
@@ -107,7 +107,7 @@
 ; LE-NEXT:    sradi r6, r3, 63
 ; LE-NEXT:    addis r5, r2, glob@toc@ha
 ; LE-NEXT:    subc r3, r3, r4
-; LE-NEXT:    rldicl r3, r4, 1, 63
+; LE-NEXT:    srdi r3, r4, 63
 ; LE-NEXT:    adde r3, r3, r6
 ; LE-NEXT:    xori r3, r3, 1
 ; LE-NEXT:    neg r3, r3
diff --git a/llvm/test/CodeGen/PowerPC/testComparesiltss.ll b/llvm/test/CodeGen/PowerPC/testComparesiltss.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesiltss.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesiltss.ll
@@ -15,7 +15,7 @@
 ; CHECK-LABEL: test_iltss:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp slt i16 %a, %b
@@ -55,7 +55,7 @@
 ; BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; BE-NEXT:    sub r3, r3, r4
 ; BE-NEXT:    ld r5, .LC0@toc@l(r5)
-; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    srdi r3, r3, 63
 ; BE-NEXT:    sth r3, 0(r5)
 ; BE-NEXT:    blr
 ;
@@ -63,7 +63,7 @@
 ; LE:       # %bb.0: # %entry
 ; LE-NEXT:    sub r3, r3, r4
 ; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    srdi r3, r3, 63
 ; LE-NEXT:    sth r3, glob@toc@l(r5)
 ; LE-NEXT:    blr
 entry:
diff --git a/llvm/test/CodeGen/PowerPC/testComparesiltuc.ll b/llvm/test/CodeGen/PowerPC/testComparesiltuc.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesiltuc.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesiltuc.ll
@@ -15,7 +15,7 @@
 ; CHECK-LABEL: test_iltuc:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ult i8 %a, %b
@@ -43,7 +43,7 @@
 ; BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; BE-NEXT:    sub r3, r3, r4
 ; BE-NEXT:    ld r5, .LC0@toc@l(r5)
-; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    srdi r3, r3, 63
 ; BE-NEXT:    stb r3, 0(r5)
 ; BE-NEXT:    blr
 ;
@@ -51,7 +51,7 @@
 ; LE:       # %bb.0: # %entry
 ; LE-NEXT:    sub r3, r3, r4
 ; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    srdi r3, r3, 63
 ; LE-NEXT:    stb r3, glob@toc@l(r5)
 ; LE-NEXT:    blr
 entry:
diff --git a/llvm/test/CodeGen/PowerPC/testComparesiltui.ll b/llvm/test/CodeGen/PowerPC/testComparesiltui.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesiltui.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesiltui.ll
@@ -15,7 +15,7 @@
 ; CHECK-LABEL: test_iltui:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ult i32 %a, %b
@@ -43,7 +43,7 @@
 ; BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; BE-NEXT:    sub r3, r3, r4
 ; BE-NEXT:    ld r5, .LC0@toc@l(r5)
-; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    srdi r3, r3, 63
 ; BE-NEXT:    stw r3, 0(r5)
 ; BE-NEXT:    blr
 ;
@@ -51,7 +51,7 @@
 ; LE:       # %bb.0: # %entry
 ; LE-NEXT:    sub r3, r3, r4
 ; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    srdi r3, r3, 63
 ; LE-NEXT:    stw r3, glob@toc@l(r5)
 ; LE-NEXT:    blr
 entry:
diff --git a/llvm/test/CodeGen/PowerPC/testComparesiltus.ll b/llvm/test/CodeGen/PowerPC/testComparesiltus.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesiltus.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesiltus.ll
@@ -15,7 +15,7 @@
 ; CHECK-LABEL: test_iltus:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ult i16 %a, %b
@@ -43,7 +43,7 @@
 ; BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; BE-NEXT:    sub r3, r3, r4
 ; BE-NEXT:    ld r5, .LC0@toc@l(r5)
-; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    srdi r3, r3, 63
 ; BE-NEXT:    sth r3, 0(r5)
 ; BE-NEXT:    blr
 ;
@@ -51,7 +51,7 @@
 ; LE:       # %bb.0: # %entry
 ; LE-NEXT:    sub r3, r3, r4
 ; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    srdi r3, r3, 63
 ; LE-NEXT:    sth r3, glob@toc@l(r5)
 ; LE-NEXT:    blr
 entry:
diff --git a/llvm/test/CodeGen/PowerPC/testCompareslleqsll.ll b/llvm/test/CodeGen/PowerPC/testCompareslleqsll.ll
--- a/llvm/test/CodeGen/PowerPC/testCompareslleqsll.ll
+++ b/llvm/test/CodeGen/PowerPC/testCompareslleqsll.ll
@@ -20,14 +20,14 @@
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    xor r3, r3, r4
 ; CHECK-BE-NEXT:    cntlzd r3, r3
-; CHECK-BE-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-BE-NEXT:    extrdi r3, r3, 1, 57
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_lleqsll:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    xor r3, r3, r4
 ; CHECK-LE-NEXT:    cntlzd r3, r3
-; CHECK-LE-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-LE-NEXT:    extrdi r3, r3, 1, 57
 ; CHECK-LE-NEXT:    blr
 entry:
   %cmp = icmp eq i64 %a, %b
@@ -72,13 +72,13 @@
 ; CHECK-BE-LABEL: test_lleqsll_z:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cntlzd r3, r3
-; CHECK-BE-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-BE-NEXT:    extrdi r3, r3, 1, 57
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_lleqsll_z:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cntlzd r3, r3
-; CHECK-LE-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-LE-NEXT:    extrdi r3, r3, 1, 57
 ; CHECK-LE-NEXT:    blr
 entry:
   %cmp = icmp eq i64 %a, 0
@@ -126,7 +126,7 @@
 ; CHECK-BE-NEXT:    xor r3, r3, r4
 ; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; CHECK-BE-NEXT:    cntlzd r3, r3
-; CHECK-BE-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-BE-NEXT:    extrdi r3, r3, 1, 57
 ; CHECK-BE-NEXT:    std r3, 0(r4)
 ; CHECK-BE-NEXT:    blr
 ;
@@ -135,7 +135,7 @@
 ; CHECK-LE-NEXT:    xor r3, r3, r4
 ; CHECK-LE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-LE-NEXT:    cntlzd r3, r3
-; CHECK-LE-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-LE-NEXT:    extrdi r3, r3, 1, 57
 ; CHECK-LE-NEXT:    std r3, glob@toc@l(r5)
 ; CHECK-LE-NEXT:    blr
 entry:
@@ -194,7 +194,7 @@
 ; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    cntlzd r3, r3
 ; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
-; CHECK-BE-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-BE-NEXT:    extrdi r3, r3, 1, 57
 ; CHECK-BE-NEXT:    std r3, 0(r4)
 ; CHECK-BE-NEXT:    blr
 ;
@@ -202,7 +202,7 @@
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cntlzd r3, r3
 ; CHECK-LE-NEXT:    addis r4, r2, glob@toc@ha
-; CHECK-LE-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-LE-NEXT:    extrdi r3, r3, 1, 57
 ; CHECK-LE-NEXT:    std r3, glob@toc@l(r4)
 ; CHECK-LE-NEXT:    blr
 entry:
diff --git a/llvm/test/CodeGen/PowerPC/testComparesllequll.ll b/llvm/test/CodeGen/PowerPC/testComparesllequll.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesllequll.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllequll.ll
@@ -20,14 +20,14 @@
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    xor r3, r3, r4
 ; CHECK-BE-NEXT:    cntlzd r3, r3
-; CHECK-BE-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-BE-NEXT:    extrdi r3, r3, 1, 57
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_llequll:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    xor r3, r3, r4
 ; CHECK-LE-NEXT:    cntlzd r3, r3
-; CHECK-LE-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-LE-NEXT:    extrdi r3, r3, 1, 57
 ; CHECK-LE-NEXT:    blr
 entry:
   %cmp = icmp eq i64 %a, %b
@@ -72,13 +72,13 @@
 ; CHECK-BE-LABEL: test_llequll_z:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    cntlzd r3, r3
-; CHECK-BE-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-BE-NEXT:    extrdi r3, r3, 1, 57
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_llequll_z:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cntlzd r3, r3
-; CHECK-LE-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-LE-NEXT:    extrdi r3, r3, 1, 57
 ; CHECK-LE-NEXT:    blr
 entry:
   %cmp = icmp eq i64 %a, 0
@@ -126,7 +126,7 @@
 ; CHECK-BE-NEXT:    xor r3, r3, r4
 ; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; CHECK-BE-NEXT:    cntlzd r3, r3
-; CHECK-BE-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-BE-NEXT:    extrdi r3, r3, 1, 57
 ; CHECK-BE-NEXT:    std r3, 0(r4)
 ; CHECK-BE-NEXT:    blr
 ;
@@ -135,7 +135,7 @@
 ; CHECK-LE-NEXT:    xor r3, r3, r4
 ; CHECK-LE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-LE-NEXT:    cntlzd r3, r3
-; CHECK-LE-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-LE-NEXT:    extrdi r3, r3, 1, 57
 ; CHECK-LE-NEXT:    std r3, glob@toc@l(r5)
 ; CHECK-LE-NEXT:    blr
 entry:
@@ -194,7 +194,7 @@
 ; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    cntlzd r3, r3
 ; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
-; CHECK-BE-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-BE-NEXT:    extrdi r3, r3, 1, 57
 ; CHECK-BE-NEXT:    std r3, 0(r4)
 ; CHECK-BE-NEXT:    blr
 ;
@@ -202,7 +202,7 @@
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    cntlzd r3, r3
 ; CHECK-LE-NEXT:    addis r4, r2, glob@toc@ha
-; CHECK-LE-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-LE-NEXT:    extrdi r3, r3, 1, 57
 ; CHECK-LE-NEXT:    std r3, glob@toc@l(r4)
 ; CHECK-LE-NEXT:    blr
 entry:
diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgesc.ll b/llvm/test/CodeGen/PowerPC/testComparesllgesc.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesllgesc.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllgesc.ll
@@ -17,14 +17,14 @@
 ; CHECK-BE-LABEL: test_llgesc:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    sub r3, r3, r4
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    xori r3, r3, 1
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_llgesc:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sub r3, r3, r4
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    xori r3, r3, 1
 ; CHECK-LE-NEXT:    blr
 entry:
@@ -43,14 +43,14 @@
 ; CHECK-BE-LABEL: test_llgesc_sext:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    sub r3, r3, r4
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    addi r3, r3, -1
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_llgesc_sext:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sub r3, r3, r4
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    addi r3, r3, -1
 ; CHECK-LE-NEXT:    blr
 entry:
@@ -73,7 +73,7 @@
 ; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sub r3, r3, r4
 ; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    xori r3, r3, 1
 ; CHECK-BE-NEXT:    stb r3, 0(r4)
 ; CHECK-BE-NEXT:    blr
@@ -82,7 +82,7 @@
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sub r3, r3, r4
 ; CHECK-LE-NEXT:    addis r5, r2, glob@toc@ha
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    xori r3, r3, 1
 ; CHECK-LE-NEXT:    stb r3, glob@toc@l(r5)
 ; CHECK-LE-NEXT:    blr
@@ -107,7 +107,7 @@
 ; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sub r3, r3, r4
 ; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    addi r3, r3, -1
 ; CHECK-BE-NEXT:    stb r3, 0(r4)
 ; CHECK-BE-NEXT:    blr
@@ -116,7 +116,7 @@
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sub r3, r3, r4
 ; CHECK-LE-NEXT:    addis r5, r2, glob@toc@ha
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    addi r3, r3, -1
 ; CHECK-LE-NEXT:    stb r3, glob@toc@l(r5)
 ; CHECK-LE-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgesi.ll b/llvm/test/CodeGen/PowerPC/testComparesllgesi.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesllgesi.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllgesi.ll
@@ -17,14 +17,14 @@
 ; CHECK-BE-LABEL: test_llgesi:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    sub r3, r3, r4
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    xori r3, r3, 1
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_llgesi:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sub r3, r3, r4
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    xori r3, r3, 1
 ; CHECK-LE-NEXT:    blr
 entry:
@@ -43,14 +43,14 @@
 ; CHECK-BE-LABEL: test_llgesi_sext:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    sub r3, r3, r4
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    addi r3, r3, -1
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_llgesi_sext:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sub r3, r3, r4
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    addi r3, r3, -1
 ; CHECK-LE-NEXT:    blr
 entry:
@@ -73,7 +73,7 @@
 ; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sub r3, r3, r4
 ; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    xori r3, r3, 1
 ; CHECK-BE-NEXT:    stw r3, 0(r4)
 ; CHECK-BE-NEXT:    blr
@@ -82,7 +82,7 @@
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sub r3, r3, r4
 ; CHECK-LE-NEXT:    addis r5, r2, glob@toc@ha
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    xori r3, r3, 1
 ; CHECK-LE-NEXT:    stw r3, glob@toc@l(r5)
 ; CHECK-LE-NEXT:    blr
@@ -107,7 +107,7 @@
 ; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sub r3, r3, r4
 ; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    addi r3, r3, -1
 ; CHECK-BE-NEXT:    stw r3, 0(r4)
 ; CHECK-BE-NEXT:    blr
@@ -116,7 +116,7 @@
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sub r3, r3, r4
 ; CHECK-LE-NEXT:    addis r5, r2, glob@toc@ha
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    addi r3, r3, -1
 ; CHECK-LE-NEXT:    stw r3, glob@toc@l(r5)
 ; CHECK-LE-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgesll.ll b/llvm/test/CodeGen/PowerPC/testComparesllgesll.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesllgesll.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllgesll.ll
@@ -18,7 +18,7 @@
 ; CHECK-BE-LABEL: test_llgesll:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    sradi r5, r3, 63
-; CHECK-BE-NEXT:    rldicl r6, r4, 1, 63
+; CHECK-BE-NEXT:    srdi r6, r4, 63
 ; CHECK-BE-NEXT:    subc r3, r3, r4
 ; CHECK-BE-NEXT:    adde r3, r5, r6
 ; CHECK-BE-NEXT:    blr
@@ -26,7 +26,7 @@
 ; CHECK-LE-LABEL: test_llgesll:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sradi r5, r3, 63
-; CHECK-LE-NEXT:    rldicl r6, r4, 1, 63
+; CHECK-LE-NEXT:    srdi r6, r4, 63
 ; CHECK-LE-NEXT:    subc r3, r3, r4
 ; CHECK-LE-NEXT:    adde r3, r5, r6
 ; CHECK-LE-NEXT:    blr
@@ -48,7 +48,7 @@
 ; CHECK-BE-LABEL: test_llgesll_sext:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    sradi r5, r3, 63
-; CHECK-BE-NEXT:    rldicl r6, r4, 1, 63
+; CHECK-BE-NEXT:    srdi r6, r4, 63
 ; CHECK-BE-NEXT:    subc r3, r3, r4
 ; CHECK-BE-NEXT:    adde r3, r5, r6
 ; CHECK-BE-NEXT:    neg r3, r3
@@ -57,7 +57,7 @@
 ; CHECK-LE-LABEL: test_llgesll_sext:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sradi r5, r3, 63
-; CHECK-LE-NEXT:    rldicl r6, r4, 1, 63
+; CHECK-LE-NEXT:    srdi r6, r4, 63
 ; CHECK-LE-NEXT:    subc r3, r3, r4
 ; CHECK-LE-NEXT:    adde r3, r5, r6
 ; CHECK-LE-NEXT:    neg r3, r3
@@ -77,13 +77,13 @@
 ; CHECK-BE-LABEL: test_llgesll_z:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    not r3, r3
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_llgesll_z:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    not r3, r3
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    blr
 entry:
   %cmp = icmp sgt i64 %a, -1
@@ -130,7 +130,7 @@
 ; CHECK-BE-NEXT:    sradi r6, r3, 63
 ; CHECK-BE-NEXT:    ld r5, .LC0@toc@l(r5)
 ; CHECK-BE-NEXT:    subc r3, r3, r4
-; CHECK-BE-NEXT:    rldicl r3, r4, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r4, 63
 ; CHECK-BE-NEXT:    adde r3, r6, r3
 ; CHECK-BE-NEXT:    std r3, 0(r5)
 ; CHECK-BE-NEXT:    blr
@@ -140,7 +140,7 @@
 ; CHECK-LE-NEXT:    sradi r6, r3, 63
 ; CHECK-LE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-LE-NEXT:    subc r3, r3, r4
-; CHECK-LE-NEXT:    rldicl r3, r4, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r4, 63
 ; CHECK-LE-NEXT:    adde r3, r6, r3
 ; CHECK-LE-NEXT:    std r3, glob@toc@l(r5)
 ; CHECK-LE-NEXT:    blr
@@ -167,7 +167,7 @@
 ; CHECK-BE-NEXT:    sradi r6, r3, 63
 ; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    subc r3, r3, r4
-; CHECK-BE-NEXT:    rldicl r3, r4, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r4, 63
 ; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; CHECK-BE-NEXT:    adde r3, r6, r3
 ; CHECK-BE-NEXT:    neg r3, r3
@@ -179,7 +179,7 @@
 ; CHECK-LE-NEXT:    sradi r6, r3, 63
 ; CHECK-LE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-LE-NEXT:    subc r3, r3, r4
-; CHECK-LE-NEXT:    rldicl r3, r4, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r4, 63
 ; CHECK-LE-NEXT:    adde r3, r6, r3
 ; CHECK-LE-NEXT:    neg r3, r3
 ; CHECK-LE-NEXT:    std r3, glob@toc@l(r5)
@@ -204,7 +204,7 @@
 ; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    not r3, r3
 ; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    std r3, 0(r4)
 ; CHECK-BE-NEXT:    blr
 ;
@@ -212,7 +212,7 @@
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    not r3, r3
 ; CHECK-LE-NEXT:    addis r4, r2, glob@toc@ha
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    std r3, glob@toc@l(r4)
 ; CHECK-LE-NEXT:    blr
 entry:
diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgess.ll b/llvm/test/CodeGen/PowerPC/testComparesllgess.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesllgess.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllgess.ll
@@ -17,14 +17,14 @@
 ; CHECK-BE-LABEL: test_llgess:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    sub r3, r3, r4
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    xori r3, r3, 1
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_llgess:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sub r3, r3, r4
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    xori r3, r3, 1
 ; CHECK-LE-NEXT:    blr
 entry:
@@ -43,14 +43,14 @@
 ; CHECK-BE-LABEL: test_llgess_sext:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    sub r3, r3, r4
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    addi r3, r3, -1
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_llgess_sext:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sub r3, r3, r4
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    addi r3, r3, -1
 ; CHECK-LE-NEXT:    blr
 entry:
@@ -73,7 +73,7 @@
 ; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sub r3, r3, r4
 ; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    xori r3, r3, 1
 ; CHECK-BE-NEXT:    sth r3, 0(r4)
 ; CHECK-BE-NEXT:    blr
@@ -82,7 +82,7 @@
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sub r3, r3, r4
 ; CHECK-LE-NEXT:    addis r5, r2, glob@toc@ha
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    xori r3, r3, 1
 ; CHECK-LE-NEXT:    sth r3, glob@toc@l(r5)
 ; CHECK-LE-NEXT:    blr
@@ -107,7 +107,7 @@
 ; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sub r3, r3, r4
 ; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    addi r3, r3, -1
 ; CHECK-BE-NEXT:    sth r3, 0(r4)
 ; CHECK-BE-NEXT:    blr
@@ -116,7 +116,7 @@
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sub r3, r3, r4
 ; CHECK-LE-NEXT:    addis r5, r2, glob@toc@ha
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    addi r3, r3, -1
 ; CHECK-LE-NEXT:    sth r3, glob@toc@l(r5)
 ; CHECK-LE-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgeuc.ll b/llvm/test/CodeGen/PowerPC/testComparesllgeuc.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesllgeuc.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllgeuc.ll
@@ -16,7 +16,7 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    not r3, r3
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i8 %a, %b
@@ -29,7 +29,7 @@
 ; CHECK-LABEL: test_llgeuc_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    addi r3, r3, -1
 ; CHECK-NEXT:    blr
 entry:
@@ -70,7 +70,7 @@
 ; BE-NEXT:    sub r3, r3, r4
 ; BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; BE-NEXT:    not r3, r3
-; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    srdi r3, r3, 63
 ; BE-NEXT:    stb r3, 0(r4)
 ; BE-NEXT:    blr
 ;
@@ -79,7 +79,7 @@
 ; LE-NEXT:    sub r3, r3, r4
 ; LE-NEXT:    addis r5, r2, glob@toc@ha
 ; LE-NEXT:    not r3, r3
-; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    srdi r3, r3, 63
 ; LE-NEXT:    stb r3, glob@toc@l(r5)
 ; LE-NEXT:    blr
 entry:
@@ -97,7 +97,7 @@
 ; BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; BE-NEXT:    sub r3, r3, r4
 ; BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    srdi r3, r3, 63
 ; BE-NEXT:    addi r3, r3, -1
 ; BE-NEXT:    stb r3, 0(r4)
 ; BE-NEXT:    blr
@@ -106,7 +106,7 @@
 ; LE:       # %bb.0: # %entry
 ; LE-NEXT:    sub r3, r3, r4
 ; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    srdi r3, r3, 63
 ; LE-NEXT:    addi r3, r3, -1
 ; LE-NEXT:    stb r3, glob@toc@l(r5)
 ; LE-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgeui.ll b/llvm/test/CodeGen/PowerPC/testComparesllgeui.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesllgeui.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllgeui.ll
@@ -16,7 +16,7 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    not r3, r3
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i32 %a, %b
@@ -29,7 +29,7 @@
 ; CHECK-LABEL: test_llgeui_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    addi r3, r3, -1
 ; CHECK-NEXT:    blr
 entry:
@@ -70,7 +70,7 @@
 ; BE-NEXT:    sub r3, r3, r4
 ; BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; BE-NEXT:    not r3, r3
-; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    srdi r3, r3, 63
 ; BE-NEXT:    stw r3, 0(r4)
 ; BE-NEXT:    blr
 ;
@@ -79,7 +79,7 @@
 ; LE-NEXT:    sub r3, r3, r4
 ; LE-NEXT:    addis r5, r2, glob@toc@ha
 ; LE-NEXT:    not r3, r3
-; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    srdi r3, r3, 63
 ; LE-NEXT:    stw r3, glob@toc@l(r5)
 ; LE-NEXT:    blr
 entry:
@@ -97,7 +97,7 @@
 ; BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; BE-NEXT:    sub r3, r3, r4
 ; BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    srdi r3, r3, 63
 ; BE-NEXT:    addi r3, r3, -1
 ; BE-NEXT:    stw r3, 0(r4)
 ; BE-NEXT:    blr
@@ -106,7 +106,7 @@
 ; LE:       # %bb.0: # %entry
 ; LE-NEXT:    sub r3, r3, r4
 ; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    srdi r3, r3, 63
 ; LE-NEXT:    addi r3, r3, -1
 ; LE-NEXT:    stw r3, glob@toc@l(r5)
 ; LE-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgeus.ll b/llvm/test/CodeGen/PowerPC/testComparesllgeus.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesllgeus.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllgeus.ll
@@ -16,7 +16,7 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    not r3, r3
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp uge i16 %a, %b
@@ -29,7 +29,7 @@
 ; CHECK-LABEL: test_llgeus_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    addi r3, r3, -1
 ; CHECK-NEXT:    blr
 entry:
@@ -70,7 +70,7 @@
 ; BE-NEXT:    sub r3, r3, r4
 ; BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; BE-NEXT:    not r3, r3
-; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    srdi r3, r3, 63
 ; BE-NEXT:    sth r3, 0(r4)
 ; BE-NEXT:    blr
 ;
@@ -79,7 +79,7 @@
 ; LE-NEXT:    sub r3, r3, r4
 ; LE-NEXT:    addis r5, r2, glob@toc@ha
 ; LE-NEXT:    not r3, r3
-; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    srdi r3, r3, 63
 ; LE-NEXT:    sth r3, glob@toc@l(r5)
 ; LE-NEXT:    blr
 entry:
@@ -97,7 +97,7 @@
 ; BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; BE-NEXT:    sub r3, r3, r4
 ; BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    srdi r3, r3, 63
 ; BE-NEXT:    addi r3, r3, -1
 ; BE-NEXT:    sth r3, 0(r4)
 ; BE-NEXT:    blr
@@ -106,7 +106,7 @@
 ; LE:       # %bb.0: # %entry
 ; LE-NEXT:    sub r3, r3, r4
 ; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    srdi r3, r3, 63
 ; LE-NEXT:    addi r3, r3, -1
 ; LE-NEXT:    sth r3, glob@toc@l(r5)
 ; LE-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgtsll.ll b/llvm/test/CodeGen/PowerPC/testComparesllgtsll.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesllgtsll.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllgtsll.ll
@@ -13,7 +13,7 @@
 ; CHECK-LABEL: test_llgtsll:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r5, r4, 63
-; CHECK-NEXT:    rldicl r6, r3, 1, 63
+; CHECK-NEXT:    srdi r6, r3, 63
 ; CHECK-NEXT:    subc r3, r4, r3
 ; CHECK-NEXT:    adde r3, r6, r5
 ; CHECK-NEXT:    xori r3, r3, 1
@@ -29,7 +29,7 @@
 ; CHECK-LABEL: test_llgtsll_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r5, r4, 63
-; CHECK-NEXT:    rldicl r6, r3, 1, 63
+; CHECK-NEXT:    srdi r6, r3, 63
 ; CHECK-NEXT:    subc r3, r4, r3
 ; CHECK-NEXT:    adde r3, r6, r5
 ; CHECK-NEXT:    xori r3, r3, 1
@@ -48,7 +48,7 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addi r4, r3, -1
 ; CHECK-NEXT:    nor r3, r4, r3
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i64 %a, 0
@@ -77,7 +77,7 @@
 ; CHECK-NEXT:    sradi r6, r4, 63
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    subc r4, r4, r3
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
 ; CHECK-NEXT:    adde r3, r3, r6
 ; CHECK-NEXT:    xori r3, r3, 1
@@ -98,7 +98,7 @@
 ; CHECK-NEXT:    sradi r6, r4, 63
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    subc r4, r4, r3
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    adde r3, r3, r6
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
 ; CHECK-NEXT:    xori r3, r3, 1
@@ -122,7 +122,7 @@
 ; CHECK-NEXT:    addi r5, r3, -1
 ; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
 ; CHECK-NEXT:    nor r3, r5, r3
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    std r3, 0(r4)
 ; CHECK-NEXT:    blr
 entry:
diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgtuc.ll b/llvm/test/CodeGen/PowerPC/testComparesllgtuc.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesllgtuc.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllgtuc.ll
@@ -13,7 +13,7 @@
 ; CHECK-LABEL: test_llgtuc:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ugt i8 %a, %b
@@ -70,7 +70,7 @@
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    stb r3, 0(r5)
 ; CHECK-NEXT:    blr
 entry:
diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgtui.ll b/llvm/test/CodeGen/PowerPC/testComparesllgtui.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesllgtui.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllgtui.ll
@@ -13,7 +13,7 @@
 ; CHECK-LABEL: test_llgtui:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ugt i32 %a, %b
@@ -70,7 +70,7 @@
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    stw r3, 0(r5)
 ; CHECK-NEXT:    blr
 entry:
diff --git a/llvm/test/CodeGen/PowerPC/testComparesllgtus.ll b/llvm/test/CodeGen/PowerPC/testComparesllgtus.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesllgtus.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllgtus.ll
@@ -13,7 +13,7 @@
 ; CHECK-LABEL: test_llgtus:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ugt i16 %a, %b
@@ -70,7 +70,7 @@
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    sth r3, 0(r5)
 ; CHECK-NEXT:    blr
 entry:
diff --git a/llvm/test/CodeGen/PowerPC/testCompareslllesc.ll b/llvm/test/CodeGen/PowerPC/testCompareslllesc.ll
--- a/llvm/test/CodeGen/PowerPC/testCompareslllesc.ll
+++ b/llvm/test/CodeGen/PowerPC/testCompareslllesc.ll
@@ -18,14 +18,14 @@
 ; CHECK-BE-LABEL: test_lllesc:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    sub r3, r4, r3
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    xori r3, r3, 1
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_lllesc:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sub r3, r4, r3
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    xori r3, r3, 1
 ; CHECK-LE-NEXT:    blr
 entry:
@@ -44,14 +44,14 @@
 ; CHECK-BE-LABEL: test_lllesc_sext:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    sub r3, r4, r3
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    addi r3, r3, -1
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_lllesc_sext:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sub r3, r4, r3
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    addi r3, r3, -1
 ; CHECK-LE-NEXT:    blr
 entry:
@@ -74,7 +74,7 @@
 ; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sub r3, r4, r3
 ; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    xori r3, r3, 1
 ; CHECK-BE-NEXT:    stb r3, 0(r4)
 ; CHECK-BE-NEXT:    blr
@@ -83,7 +83,7 @@
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sub r3, r4, r3
 ; CHECK-LE-NEXT:    addis r5, r2, glob@toc@ha
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    xori r3, r3, 1
 ; CHECK-LE-NEXT:    stb r3, glob@toc@l(r5)
 ; CHECK-LE-NEXT:    blr
@@ -108,7 +108,7 @@
 ; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sub r3, r4, r3
 ; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    addi r3, r3, -1
 ; CHECK-BE-NEXT:    stb r3, 0(r4)
 ; CHECK-BE-NEXT:    blr
@@ -117,7 +117,7 @@
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sub r3, r4, r3
 ; CHECK-LE-NEXT:    addis r5, r2, glob@toc@ha
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    addi r3, r3, -1
 ; CHECK-LE-NEXT:    stb r3, glob@toc@l(r5)
 ; CHECK-LE-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/testCompareslllesi.ll b/llvm/test/CodeGen/PowerPC/testCompareslllesi.ll
--- a/llvm/test/CodeGen/PowerPC/testCompareslllesi.ll
+++ b/llvm/test/CodeGen/PowerPC/testCompareslllesi.ll
@@ -18,14 +18,14 @@
 ; CHECK-BE-LABEL: test_lllesi:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    sub r3, r4, r3
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    xori r3, r3, 1
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_lllesi:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sub r3, r4, r3
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    xori r3, r3, 1
 ; CHECK-LE-NEXT:    blr
 entry:
@@ -44,14 +44,14 @@
 ; CHECK-BE-LABEL: test_lllesi_sext:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    sub r3, r4, r3
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    addi r3, r3, -1
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_lllesi_sext:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sub r3, r4, r3
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    addi r3, r3, -1
 ; CHECK-LE-NEXT:    blr
 entry:
@@ -74,7 +74,7 @@
 ; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sub r3, r4, r3
 ; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    xori r3, r3, 1
 ; CHECK-BE-NEXT:    stw r3, 0(r4)
 ; CHECK-BE-NEXT:    blr
@@ -83,7 +83,7 @@
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sub r3, r4, r3
 ; CHECK-LE-NEXT:    addis r5, r2, glob@toc@ha
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    xori r3, r3, 1
 ; CHECK-LE-NEXT:    stw r3, glob@toc@l(r5)
 ; CHECK-LE-NEXT:    blr
@@ -108,7 +108,7 @@
 ; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sub r3, r4, r3
 ; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    addi r3, r3, -1
 ; CHECK-BE-NEXT:    stw r3, 0(r4)
 ; CHECK-BE-NEXT:    blr
@@ -117,7 +117,7 @@
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sub r3, r4, r3
 ; CHECK-LE-NEXT:    addis r5, r2, glob@toc@ha
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    addi r3, r3, -1
 ; CHECK-LE-NEXT:    stw r3, glob@toc@l(r5)
 ; CHECK-LE-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/testCompareslllesll.ll b/llvm/test/CodeGen/PowerPC/testCompareslllesll.ll
--- a/llvm/test/CodeGen/PowerPC/testCompareslllesll.ll
+++ b/llvm/test/CodeGen/PowerPC/testCompareslllesll.ll
@@ -19,7 +19,7 @@
 ; CHECK-BE-LABEL: test_lllesll:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    sradi r5, r4, 63
-; CHECK-BE-NEXT:    rldicl r6, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r6, r3, 63
 ; CHECK-BE-NEXT:    subc r3, r4, r3
 ; CHECK-BE-NEXT:    adde r3, r5, r6
 ; CHECK-BE-NEXT:    blr
@@ -27,7 +27,7 @@
 ; CHECK-LE-LABEL: test_lllesll:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sradi r5, r4, 63
-; CHECK-LE-NEXT:    rldicl r6, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r6, r3, 63
 ; CHECK-LE-NEXT:    subc r3, r4, r3
 ; CHECK-LE-NEXT:    adde r3, r5, r6
 ; CHECK-LE-NEXT:    blr
@@ -50,7 +50,7 @@
 ; CHECK-BE-LABEL: test_lllesll_sext:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    sradi r5, r4, 63
-; CHECK-BE-NEXT:    rldicl r6, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r6, r3, 63
 ; CHECK-BE-NEXT:    subc r3, r4, r3
 ; CHECK-BE-NEXT:    adde r3, r5, r6
 ; CHECK-BE-NEXT:    neg r3, r3
@@ -59,7 +59,7 @@
 ; CHECK-LE-LABEL: test_lllesll_sext:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sradi r5, r4, 63
-; CHECK-LE-NEXT:    rldicl r6, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r6, r3, 63
 ; CHECK-LE-NEXT:    subc r3, r4, r3
 ; CHECK-LE-NEXT:    adde r3, r5, r6
 ; CHECK-LE-NEXT:    neg r3, r3
@@ -82,14 +82,14 @@
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addi r4, r3, -1
 ; CHECK-BE-NEXT:    or r3, r4, r3
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_lllesll_z:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    addi r4, r3, -1
 ; CHECK-LE-NEXT:    or r3, r4, r3
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    blr
 entry:
   %cmp = icmp slt i64 %a, 1
@@ -141,7 +141,7 @@
 ; CHECK-BE-NEXT:    sradi r6, r4, 63
 ; CHECK-BE-NEXT:    ld r5, .LC0@toc@l(r5)
 ; CHECK-BE-NEXT:    subc r4, r4, r3
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    adde r3, r6, r3
 ; CHECK-BE-NEXT:    std r3, 0(r5)
 ; CHECK-BE-NEXT:    blr
@@ -151,7 +151,7 @@
 ; CHECK-LE-NEXT:    sradi r6, r4, 63
 ; CHECK-LE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-LE-NEXT:    subc r4, r4, r3
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    adde r3, r6, r3
 ; CHECK-LE-NEXT:    std r3, glob@toc@l(r5)
 ; CHECK-LE-NEXT:    blr
@@ -179,7 +179,7 @@
 ; CHECK-BE-NEXT:    sradi r6, r4, 63
 ; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    subc r4, r4, r3
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; CHECK-BE-NEXT:    adde r3, r6, r3
 ; CHECK-BE-NEXT:    neg r3, r3
@@ -191,7 +191,7 @@
 ; CHECK-LE-NEXT:    sradi r6, r4, 63
 ; CHECK-LE-NEXT:    addis r5, r2, glob@toc@ha
 ; CHECK-LE-NEXT:    subc r4, r4, r3
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    adde r3, r6, r3
 ; CHECK-LE-NEXT:    neg r3, r3
 ; CHECK-LE-NEXT:    std r3, glob@toc@l(r5)
@@ -219,7 +219,7 @@
 ; CHECK-BE-NEXT:    addi r5, r3, -1
 ; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
 ; CHECK-BE-NEXT:    or r3, r5, r3
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    std r3, 0(r4)
 ; CHECK-BE-NEXT:    blr
 ;
@@ -228,7 +228,7 @@
 ; CHECK-LE-NEXT:    addi r5, r3, -1
 ; CHECK-LE-NEXT:    addis r4, r2, glob@toc@ha
 ; CHECK-LE-NEXT:    or r3, r5, r3
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    std r3, glob@toc@l(r4)
 ; CHECK-LE-NEXT:    blr
 entry:
diff --git a/llvm/test/CodeGen/PowerPC/testComparesllless.ll b/llvm/test/CodeGen/PowerPC/testComparesllless.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesllless.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllless.ll
@@ -18,14 +18,14 @@
 ; CHECK-BE-LABEL: test_llless:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    sub r3, r4, r3
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    xori r3, r3, 1
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_llless:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sub r3, r4, r3
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    xori r3, r3, 1
 ; CHECK-LE-NEXT:    blr
 entry:
@@ -44,14 +44,14 @@
 ; CHECK-BE-LABEL: test_llless_sext:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    sub r3, r4, r3
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    addi r3, r3, -1
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test_llless_sext:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sub r3, r4, r3
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    addi r3, r3, -1
 ; CHECK-LE-NEXT:    blr
 entry:
@@ -74,7 +74,7 @@
 ; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sub r3, r4, r3
 ; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    xori r3, r3, 1
 ; CHECK-BE-NEXT:    sth r3, 0(r4)
 ; CHECK-BE-NEXT:    blr
@@ -83,7 +83,7 @@
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sub r3, r4, r3
 ; CHECK-LE-NEXT:    addis r5, r2, glob@toc@ha
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    xori r3, r3, 1
 ; CHECK-LE-NEXT:    sth r3, glob@toc@l(r5)
 ; CHECK-LE-NEXT:    blr
@@ -108,7 +108,7 @@
 ; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    sub r3, r4, r3
 ; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-BE-NEXT:    srdi r3, r3, 63
 ; CHECK-BE-NEXT:    addi r3, r3, -1
 ; CHECK-BE-NEXT:    sth r3, 0(r4)
 ; CHECK-BE-NEXT:    blr
@@ -117,7 +117,7 @@
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    sub r3, r4, r3
 ; CHECK-LE-NEXT:    addis r5, r2, glob@toc@ha
-; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-LE-NEXT:    srdi r3, r3, 63
 ; CHECK-LE-NEXT:    addi r3, r3, -1
 ; CHECK-LE-NEXT:    sth r3, glob@toc@l(r5)
 ; CHECK-LE-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/testComparesllleuc.ll b/llvm/test/CodeGen/PowerPC/testComparesllleuc.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesllleuc.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllleuc.ll
@@ -16,7 +16,7 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    not r3, r3
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i8 %a, %b
@@ -29,7 +29,7 @@
 ; CHECK-LABEL: test_llleuc_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    addi r3, r3, -1
 ; CHECK-NEXT:    blr
 entry:
@@ -73,7 +73,7 @@
 ; BE-NEXT:    sub r3, r4, r3
 ; BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; BE-NEXT:    not r3, r3
-; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    srdi r3, r3, 63
 ; BE-NEXT:    stb r3, 0(r4)
 ; BE-NEXT:    blr
 ;
@@ -82,7 +82,7 @@
 ; LE-NEXT:    sub r3, r4, r3
 ; LE-NEXT:    addis r5, r2, glob@toc@ha
 ; LE-NEXT:    not r3, r3
-; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    srdi r3, r3, 63
 ; LE-NEXT:    stb r3, glob@toc@l(r5)
 ; LE-NEXT:    blr
 entry:
@@ -99,7 +99,7 @@
 ; BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; BE-NEXT:    sub r3, r4, r3
 ; BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    srdi r3, r3, 63
 ; BE-NEXT:    addi r3, r3, -1
 ; BE-NEXT:    stb r3, 0(r4)
 ; BE-NEXT:    blr
@@ -108,7 +108,7 @@
 ; LE:       # %bb.0: # %entry
 ; LE-NEXT:    sub r3, r4, r3
 ; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    srdi r3, r3, 63
 ; LE-NEXT:    addi r3, r3, -1
 ; LE-NEXT:    stb r3, glob@toc@l(r5)
 ; LE-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/testComparesllleui.ll b/llvm/test/CodeGen/PowerPC/testComparesllleui.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesllleui.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllleui.ll
@@ -16,7 +16,7 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    not r3, r3
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i32 %a, %b
@@ -29,7 +29,7 @@
 ; CHECK-LABEL: test_llleui_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    addi r3, r3, -1
 ; CHECK-NEXT:    blr
 entry:
@@ -73,7 +73,7 @@
 ; BE-NEXT:    sub r3, r4, r3
 ; BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; BE-NEXT:    not r3, r3
-; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    srdi r3, r3, 63
 ; BE-NEXT:    stw r3, 0(r4)
 ; BE-NEXT:    blr
 ;
@@ -82,7 +82,7 @@
 ; LE-NEXT:    sub r3, r4, r3
 ; LE-NEXT:    addis r5, r2, glob@toc@ha
 ; LE-NEXT:    not r3, r3
-; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    srdi r3, r3, 63
 ; LE-NEXT:    stw r3, glob@toc@l(r5)
 ; LE-NEXT:    blr
 entry:
@@ -99,7 +99,7 @@
 ; BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; BE-NEXT:    sub r3, r4, r3
 ; BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    srdi r3, r3, 63
 ; BE-NEXT:    addi r3, r3, -1
 ; BE-NEXT:    stw r3, 0(r4)
 ; BE-NEXT:    blr
@@ -108,7 +108,7 @@
 ; LE:       # %bb.0: # %entry
 ; LE-NEXT:    sub r3, r4, r3
 ; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    srdi r3, r3, 63
 ; LE-NEXT:    addi r3, r3, -1
 ; LE-NEXT:    stw r3, glob@toc@l(r5)
 ; LE-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/testComparesllleull.ll b/llvm/test/CodeGen/PowerPC/testComparesllleull.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesllleull.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllleull.ll
@@ -43,7 +43,7 @@
 ; CHECK-LABEL: test_llleull_z:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cntlzd r3, r3
-; CHECK-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-NEXT:    extrdi r3, r3, 1, 57
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i64 %a, 0
@@ -125,7 +125,7 @@
 ; BE-NEXT:    addis r4, r2, .LC0@toc@ha
 ; BE-NEXT:    cntlzd r3, r3
 ; BE-NEXT:    ld r4, .LC0@toc@l(r4)
-; BE-NEXT:    rldicl r3, r3, 58, 63
+; BE-NEXT:    extrdi r3, r3, 1, 57
 ; BE-NEXT:    std r3, 0(r4)
 ; BE-NEXT:    blr
 ;
@@ -133,7 +133,7 @@
 ; LE:       # %bb.0: # %entry
 ; LE-NEXT:    cntlzd r3, r3
 ; LE-NEXT:    addis r4, r2, glob@toc@ha
-; LE-NEXT:    rldicl r3, r3, 58, 63
+; LE-NEXT:    extrdi r3, r3, 1, 57
 ; LE-NEXT:    std r3, glob@toc@l(r4)
 ; LE-NEXT:    blr
 entry:
diff --git a/llvm/test/CodeGen/PowerPC/testComparesllleus.ll b/llvm/test/CodeGen/PowerPC/testComparesllleus.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesllleus.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllleus.ll
@@ -16,7 +16,7 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
 ; CHECK-NEXT:    not r3, r3
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ule i16 %a, %b
@@ -29,7 +29,7 @@
 ; CHECK-LABEL: test_llleus_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r4, r3
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    addi r3, r3, -1
 ; CHECK-NEXT:    blr
 entry:
@@ -73,7 +73,7 @@
 ; BE-NEXT:    sub r3, r4, r3
 ; BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; BE-NEXT:    not r3, r3
-; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    srdi r3, r3, 63
 ; BE-NEXT:    sth r3, 0(r4)
 ; BE-NEXT:    blr
 ;
@@ -82,7 +82,7 @@
 ; LE-NEXT:    sub r3, r4, r3
 ; LE-NEXT:    addis r5, r2, glob@toc@ha
 ; LE-NEXT:    not r3, r3
-; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    srdi r3, r3, 63
 ; LE-NEXT:    sth r3, glob@toc@l(r5)
 ; LE-NEXT:    blr
 entry:
@@ -99,7 +99,7 @@
 ; BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; BE-NEXT:    sub r3, r4, r3
 ; BE-NEXT:    ld r4, .LC0@toc@l(r5)
-; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    srdi r3, r3, 63
 ; BE-NEXT:    addi r3, r3, -1
 ; BE-NEXT:    sth r3, 0(r4)
 ; BE-NEXT:    blr
@@ -108,7 +108,7 @@
 ; LE:       # %bb.0: # %entry
 ; LE-NEXT:    sub r3, r4, r3
 ; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    srdi r3, r3, 63
 ; LE-NEXT:    addi r3, r3, -1
 ; LE-NEXT:    sth r3, glob@toc@l(r5)
 ; LE-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/testComparesllltsll.ll b/llvm/test/CodeGen/PowerPC/testComparesllltsll.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesllltsll.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllltsll.ll
@@ -15,7 +15,7 @@
 ; CHECK-LABEL: test_llltsll:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r5, r3, 63
-; CHECK-NEXT:    rldicl r6, r4, 1, 63
+; CHECK-NEXT:    srdi r6, r4, 63
 ; CHECK-NEXT:    subc r3, r3, r4
 ; CHECK-NEXT:    adde r3, r6, r5
 ; CHECK-NEXT:    xori r3, r3, 1
@@ -31,7 +31,7 @@
 ; CHECK-LABEL: test_llltsll_sext:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sradi r5, r3, 63
-; CHECK-NEXT:    rldicl r6, r4, 1, 63
+; CHECK-NEXT:    srdi r6, r4, 63
 ; CHECK-NEXT:    subc r3, r3, r4
 ; CHECK-NEXT:    adde r3, r6, r5
 ; CHECK-NEXT:    xori r3, r3, 1
@@ -62,7 +62,7 @@
 ; BE-NEXT:    sradi r6, r3, 63
 ; BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; BE-NEXT:    subc r3, r3, r4
-; BE-NEXT:    rldicl r3, r4, 1, 63
+; BE-NEXT:    srdi r3, r4, 63
 ; BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; BE-NEXT:    adde r3, r3, r6
 ; BE-NEXT:    xori r3, r3, 1
@@ -74,7 +74,7 @@
 ; LE-NEXT:    sradi r6, r3, 63
 ; LE-NEXT:    addis r5, r2, glob@toc@ha
 ; LE-NEXT:    subc r3, r3, r4
-; LE-NEXT:    rldicl r3, r4, 1, 63
+; LE-NEXT:    srdi r3, r4, 63
 ; LE-NEXT:    adde r3, r3, r6
 ; LE-NEXT:    xori r3, r3, 1
 ; LE-NEXT:    std r3, glob@toc@l(r5)
@@ -94,7 +94,7 @@
 ; BE-NEXT:    sradi r6, r3, 63
 ; BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; BE-NEXT:    subc r3, r3, r4
-; BE-NEXT:    rldicl r3, r4, 1, 63
+; BE-NEXT:    srdi r3, r4, 63
 ; BE-NEXT:    ld r4, .LC0@toc@l(r5)
 ; BE-NEXT:    adde r3, r3, r6
 ; BE-NEXT:    xori r3, r3, 1
@@ -107,7 +107,7 @@
 ; LE-NEXT:    sradi r6, r3, 63
 ; LE-NEXT:    addis r5, r2, glob@toc@ha
 ; LE-NEXT:    subc r3, r3, r4
-; LE-NEXT:    rldicl r3, r4, 1, 63
+; LE-NEXT:    srdi r3, r4, 63
 ; LE-NEXT:    adde r3, r3, r6
 ; LE-NEXT:    xori r3, r3, 1
 ; LE-NEXT:    neg r3, r3
diff --git a/llvm/test/CodeGen/PowerPC/testComparesllltuc.ll b/llvm/test/CodeGen/PowerPC/testComparesllltuc.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesllltuc.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllltuc.ll
@@ -15,7 +15,7 @@
 ; CHECK-LABEL: test_llltuc:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ult i8 %a, %b
@@ -43,7 +43,7 @@
 ; BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; BE-NEXT:    sub r3, r3, r4
 ; BE-NEXT:    ld r5, .LC0@toc@l(r5)
-; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    srdi r3, r3, 63
 ; BE-NEXT:    stb r3, 0(r5)
 ; BE-NEXT:    blr
 ;
@@ -51,7 +51,7 @@
 ; LE:       # %bb.0: # %entry
 ; LE-NEXT:    sub r3, r3, r4
 ; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    srdi r3, r3, 63
 ; LE-NEXT:    stb r3, glob@toc@l(r5)
 ; LE-NEXT:    blr
 entry:
diff --git a/llvm/test/CodeGen/PowerPC/testComparesllltui.ll b/llvm/test/CodeGen/PowerPC/testComparesllltui.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesllltui.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllltui.ll
@@ -13,7 +13,7 @@
 ; CHECK-LABEL: test_llltui:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ult i32 %a, %b
@@ -61,7 +61,7 @@
 ; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
 ; CHECK-NEXT:    sub r3, r3, r4
 ; CHECK-NEXT:    ld r5, .LC0@toc@l(r5)
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    stw r3, 0(r5)
 ; CHECK-NEXT:    blr
 entry:
diff --git a/llvm/test/CodeGen/PowerPC/testComparesllltus.ll b/llvm/test/CodeGen/PowerPC/testComparesllltus.ll
--- a/llvm/test/CodeGen/PowerPC/testComparesllltus.ll
+++ b/llvm/test/CodeGen/PowerPC/testComparesllltus.ll
@@ -15,7 +15,7 @@
 ; CHECK-LABEL: test_llltus:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub r3, r3, r4
-; CHECK-NEXT:    rldicl r3, r3, 1, 63
+; CHECK-NEXT:    srdi r3, r3, 63
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp ult i16 %a, %b
@@ -43,7 +43,7 @@
 ; BE-NEXT:    addis r5, r2, .LC0@toc@ha
 ; BE-NEXT:    sub r3, r3, r4
 ; BE-NEXT:    ld r5, .LC0@toc@l(r5)
-; BE-NEXT:    rldicl r3, r3, 1, 63
+; BE-NEXT:    srdi r3, r3, 63
 ; BE-NEXT:    sth r3, 0(r5)
 ; BE-NEXT:    blr
 ;
@@ -51,7 +51,7 @@
 ; LE:       # %bb.0: # %entry
 ; LE-NEXT:    sub r3, r3, r4
 ; LE-NEXT:    addis r5, r2, glob@toc@ha
-; LE-NEXT:    rldicl r3, r3, 1, 63
+; LE-NEXT:    srdi r3, r3, 63
 ; LE-NEXT:    sth r3, glob@toc@l(r5)
 ; LE-NEXT:    blr
 entry:
diff --git a/llvm/test/CodeGen/PowerPC/trunc-srl-load.ll b/llvm/test/CodeGen/PowerPC/trunc-srl-load.ll
--- a/llvm/test/CodeGen/PowerPC/trunc-srl-load.ll
+++ b/llvm/test/CodeGen/PowerPC/trunc-srl-load.ll
@@ -25,7 +25,7 @@
 define i32 @sh_trunc_sh(i64 %x) {
 ; CHECK-LABEL: sh_trunc_sh:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    rldicl 3, 3, 47, 36
+; CHECK-NEXT:    extrdi 3, 3, 28, 19
 ; CHECK-NEXT:    blr
   %s = lshr i64 %x, 13
   %t = trunc i64 %s to i32
diff --git a/llvm/test/CodeGen/PowerPC/uint-to-fp-v4i32.ll b/llvm/test/CodeGen/PowerPC/uint-to-fp-v4i32.ll
--- a/llvm/test/CodeGen/PowerPC/uint-to-fp-v4i32.ll
+++ b/llvm/test/CodeGen/PowerPC/uint-to-fp-v4i32.ll
@@ -45,8 +45,8 @@
 ; P8BE-LABEL: test1:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    mfvsrd r3, v2
-; P8BE-NEXT:    rldicl r4, r3, 16, 48
-; P8BE-NEXT:    rldicl r3, r3, 32, 48
+; P8BE-NEXT:    srdi r4, r3, 48
+; P8BE-NEXT:    extrdi r3, r3, 16, 16
 ; P8BE-NEXT:    clrlwi r4, r4, 16
 ; P8BE-NEXT:    clrlwi r3, r3, 16
 ; P8BE-NEXT:    mtfprwz f0, r4
@@ -61,7 +61,7 @@
 ; P8LE-NEXT:    xxswapd vs0, v2
 ; P8LE-NEXT:    mffprd r3, f0
 ; P8LE-NEXT:    clrldi r4, r3, 48
-; P8LE-NEXT:    rldicl r3, r3, 48, 48
+; P8LE-NEXT:    extrdi r3, r3, 16, 32
 ; P8LE-NEXT:    clrlwi r4, r4, 16
 ; P8LE-NEXT:    clrlwi r3, r3, 16
 ; P8LE-NEXT:    mtfprwz f0, r4
diff --git a/llvm/test/CodeGen/PowerPC/umulfixsat.ll b/llvm/test/CodeGen/PowerPC/umulfixsat.ll
--- a/llvm/test/CodeGen/PowerPC/umulfixsat.ll
+++ b/llvm/test/CodeGen/PowerPC/umulfixsat.ll
@@ -25,7 +25,7 @@
 ; CHECK-NEXT:    cmplwi 6, 1
 ; CHECK-NEXT:    mullw 3, 3, 4
 ; CHECK-NEXT:    rotlwi 3, 3, 31
-; CHECK-NEXT:    rlwimi 3, 6, 31, 0, 0
+; CHECK-NEXT:    insrwi 3, 6, 1, 0
 ; CHECK-NEXT:    bc 12, 1, .LBB1_1
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB1_1:
diff --git a/llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll b/llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll
--- a/llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll
+++ b/llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll
@@ -36,7 +36,7 @@
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 2
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
-; P9LE-NEXT:    rlwinm r4, r3, 30, 18, 31
+; P9LE-NEXT:    extrwi r4, r3, 14, 16
 ; P9LE-NEXT:    mulhwu r4, r4, r5
 ; P9LE-NEXT:    lis r5, 22765
 ; P9LE-NEXT:    ori r5, r5, 8969
@@ -93,7 +93,7 @@
 ; P9BE-NEXT:    ori r5, r5, 16913
 ; P9BE-NEXT:    vmrghh v3, v4, v3
 ; P9BE-NEXT:    clrlwi r4, r3, 16
-; P9BE-NEXT:    rlwinm r3, r3, 30, 18, 31
+; P9BE-NEXT:    extrwi r3, r3, 14, 16
 ; P9BE-NEXT:    mulhwu r3, r3, r5
 ; P9BE-NEXT:    srwi r3, r3, 2
 ; P9BE-NEXT:    mulli r3, r3, 124
@@ -129,18 +129,18 @@
 ; P8LE-NEXT:    ori r10, r10, 2287
 ; P8LE-NEXT:    mffprd r4, f0
 ; P8LE-NEXT:    clrldi r6, r4, 48
-; P8LE-NEXT:    rldicl r5, r4, 32, 48
+; P8LE-NEXT:    extrdi r5, r4, 16, 16
 ; P8LE-NEXT:    clrlwi r9, r6, 16
-; P8LE-NEXT:    rldicl r8, r4, 16, 48
+; P8LE-NEXT:    srdi r8, r4, 48
 ; P8LE-NEXT:    clrlwi r11, r5, 16
 ; P8LE-NEXT:    mulhwu r3, r9, r3
 ; P8LE-NEXT:    clrlwi r12, r8, 16
 ; P8LE-NEXT:    mulhwu r7, r11, r7
 ; P8LE-NEXT:    lis r11, 8456
-; P8LE-NEXT:    rldicl r4, r4, 48, 48
+; P8LE-NEXT:    extrdi r4, r4, 16, 32
 ; P8LE-NEXT:    mulhwu r10, r12, r10
 ; P8LE-NEXT:    ori r11, r11, 16913
-; P8LE-NEXT:    rlwinm r12, r4, 30, 18, 31
+; P8LE-NEXT:    extrwi r12, r4, 14, 16
 ; P8LE-NEXT:    mulhwu r11, r12, r11
 ; P8LE-NEXT:    sub r9, r9, r3
 ; P8LE-NEXT:    srwi r9, r9, 1
@@ -181,16 +181,16 @@
 ; P8BE-NEXT:    ori r7, r7, 2287
 ; P8BE-NEXT:    ori r9, r9, 33437
 ; P8BE-NEXT:    ori r10, r10, 16913
-; P8BE-NEXT:    rldicl r6, r4, 16, 48
+; P8BE-NEXT:    srdi r6, r4, 48
 ; P8BE-NEXT:    clrldi r5, r4, 48
 ; P8BE-NEXT:    clrlwi r6, r6, 16
-; P8BE-NEXT:    rldicl r8, r4, 48, 48
+; P8BE-NEXT:    extrdi r8, r4, 16, 32
 ; P8BE-NEXT:    clrlwi r5, r5, 16
 ; P8BE-NEXT:    mulhwu r3, r6, r3
-; P8BE-NEXT:    rldicl r4, r4, 32, 48
+; P8BE-NEXT:    extrdi r4, r4, 16, 16
 ; P8BE-NEXT:    clrlwi r8, r8, 16
 ; P8BE-NEXT:    mulhwu r7, r5, r7
-; P8BE-NEXT:    rlwinm r11, r4, 30, 18, 31
+; P8BE-NEXT:    extrwi r11, r4, 14, 16
 ; P8BE-NEXT:    clrlwi r4, r4, 16
 ; P8BE-NEXT:    mulhwu r9, r8, r9
 ; P8BE-NEXT:    mulhwu r10, r11, r10
@@ -348,11 +348,11 @@
 ; P8LE-NEXT:    ori r3, r3, 8969
 ; P8LE-NEXT:    mffprd r4, f0
 ; P8LE-NEXT:    clrldi r5, r4, 48
-; P8LE-NEXT:    rldicl r6, r4, 48, 48
+; P8LE-NEXT:    extrdi r6, r4, 16, 32
 ; P8LE-NEXT:    clrlwi r8, r5, 16
-; P8LE-NEXT:    rldicl r7, r4, 32, 48
+; P8LE-NEXT:    extrdi r7, r4, 16, 16
 ; P8LE-NEXT:    clrlwi r9, r6, 16
-; P8LE-NEXT:    rldicl r4, r4, 16, 48
+; P8LE-NEXT:    srdi r4, r4, 48
 ; P8LE-NEXT:    mulhwu r10, r8, r3
 ; P8LE-NEXT:    clrlwi r11, r7, 16
 ; P8LE-NEXT:    clrlwi r0, r4, 16
@@ -403,12 +403,12 @@
 ; P8BE-NEXT:    lis r3, 22765
 ; P8BE-NEXT:    ori r3, r3, 8969
 ; P8BE-NEXT:    clrldi r5, r4, 48
-; P8BE-NEXT:    rldicl r6, r4, 48, 48
+; P8BE-NEXT:    extrdi r6, r4, 16, 32
 ; P8BE-NEXT:    clrlwi r5, r5, 16
-; P8BE-NEXT:    rldicl r7, r4, 32, 48
+; P8BE-NEXT:    extrdi r7, r4, 16, 16
 ; P8BE-NEXT:    clrlwi r6, r6, 16
 ; P8BE-NEXT:    mulhwu r8, r5, r3
-; P8BE-NEXT:    rldicl r4, r4, 16, 48
+; P8BE-NEXT:    srdi r4, r4, 48
 ; P8BE-NEXT:    clrlwi r7, r7, 16
 ; P8BE-NEXT:    mulhwu r9, r6, r3
 ; P8BE-NEXT:    clrlwi r4, r4, 16
@@ -603,13 +603,13 @@
 ; P8LE-NEXT:    ori r4, r4, 8969
 ; P8LE-NEXT:    mffprd r5, f0
 ; P8LE-NEXT:    clrldi r3, r5, 48
-; P8LE-NEXT:    rldicl r6, r5, 48, 48
+; P8LE-NEXT:    extrdi r6, r5, 16, 32
 ; P8LE-NEXT:    clrlwi r8, r3, 16
-; P8LE-NEXT:    rldicl r7, r5, 32, 48
+; P8LE-NEXT:    extrdi r7, r5, 16, 16
 ; P8LE-NEXT:    clrlwi r9, r6, 16
 ; P8LE-NEXT:    mulhwu r10, r8, r4
 ; P8LE-NEXT:    clrlwi r11, r7, 16
-; P8LE-NEXT:    rldicl r5, r5, 16, 48
+; P8LE-NEXT:    srdi r5, r5, 48
 ; P8LE-NEXT:    mulhwu r12, r9, r4
 ; P8LE-NEXT:    mulhwu r0, r11, r4
 ; P8LE-NEXT:    clrlwi r30, r5, 16
@@ -670,11 +670,11 @@
 ; P8BE-NEXT:    lis r4, 22765
 ; P8BE-NEXT:    ori r4, r4, 8969
 ; P8BE-NEXT:    clrldi r3, r5, 48
-; P8BE-NEXT:    rldicl r6, r5, 48, 48
+; P8BE-NEXT:    extrdi r6, r5, 16, 32
 ; P8BE-NEXT:    clrlwi r8, r3, 16
-; P8BE-NEXT:    rldicl r7, r5, 32, 48
+; P8BE-NEXT:    extrdi r7, r5, 16, 16
 ; P8BE-NEXT:    clrlwi r9, r6, 16
-; P8BE-NEXT:    rldicl r5, r5, 16, 48
+; P8BE-NEXT:    srdi r5, r5, 48
 ; P8BE-NEXT:    mulhwu r10, r8, r4
 ; P8BE-NEXT:    clrlwi r11, r7, 16
 ; P8BE-NEXT:    mulhwu r12, r9, r4
@@ -815,8 +815,8 @@
 ; P8LE-NEXT:    lis r3, 22765
 ; P8LE-NEXT:    ori r3, r3, 8969
 ; P8LE-NEXT:    mffprd r4, f0
-; P8LE-NEXT:    rldicl r5, r4, 16, 48
-; P8LE-NEXT:    rldicl r7, r4, 48, 48
+; P8LE-NEXT:    srdi r5, r4, 48
+; P8LE-NEXT:    extrdi r7, r4, 16, 32
 ; P8LE-NEXT:    clrlwi r6, r5, 16
 ; P8LE-NEXT:    mulhwu r3, r6, r3
 ; P8LE-NEXT:    sub r6, r6, r3
@@ -826,7 +826,7 @@
 ; P8LE-NEXT:    srwi r3, r3, 6
 ; P8LE-NEXT:    clrlwi r6, r6, 26
 ; P8LE-NEXT:    mulli r3, r3, 95
-; P8LE-NEXT:    rldicl r4, r4, 32, 48
+; P8LE-NEXT:    extrdi r4, r4, 16, 16
 ; P8LE-NEXT:    mtfprd f0, r6
 ; P8LE-NEXT:    clrlwi r6, r7, 27
 ; P8LE-NEXT:    clrlwi r4, r4, 29
@@ -849,16 +849,16 @@
 ; P8BE-NEXT:    lis r3, 22765
 ; P8BE-NEXT:    ori r3, r3, 8969
 ; P8BE-NEXT:    clrldi r5, r4, 48
-; P8BE-NEXT:    rldicl r7, r4, 16, 48
+; P8BE-NEXT:    srdi r7, r4, 48
 ; P8BE-NEXT:    clrlwi r5, r5, 16
 ; P8BE-NEXT:    clrlwi r7, r7, 26
 ; P8BE-NEXT:    mulhwu r3, r5, r3
 ; P8BE-NEXT:    sub r6, r5, r3
 ; P8BE-NEXT:    srwi r6, r6, 1
 ; P8BE-NEXT:    add r3, r6, r3
-; P8BE-NEXT:    rldicl r6, r4, 32, 48
+; P8BE-NEXT:    extrdi r6, r4, 16, 16
 ; P8BE-NEXT:    srwi r3, r3, 6
-; P8BE-NEXT:    rldicl r4, r4, 48, 48
+; P8BE-NEXT:    extrdi r4, r4, 16, 32
 ; P8BE-NEXT:    clrlwi r6, r6, 27
 ; P8BE-NEXT:    mulli r3, r3, 95
 ; P8BE-NEXT:    sldi r6, r6, 48
@@ -908,7 +908,7 @@
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 2
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
-; P9LE-NEXT:    rlwinm r4, r3, 31, 17, 31
+; P9LE-NEXT:    extrwi r4, r3, 15, 16
 ; P9LE-NEXT:    mulhwu r4, r4, r5
 ; P9LE-NEXT:    srwi r4, r4, 8
 ; P9LE-NEXT:    mulli r4, r4, 654
@@ -952,7 +952,7 @@
 ; P9BE-NEXT:    ori r5, r5, 30865
 ; P9BE-NEXT:    vmrghh v3, v4, v3
 ; P9BE-NEXT:    clrlwi r4, r3, 16
-; P9BE-NEXT:    rlwinm r3, r3, 31, 17, 31
+; P9BE-NEXT:    extrwi r3, r3, 15, 16
 ; P9BE-NEXT:    mulhwu r3, r3, r5
 ; P9BE-NEXT:    srwi r3, r3, 8
 ; P9BE-NEXT:    mulli r3, r3, 654
@@ -977,14 +977,14 @@
 ; P8LE-NEXT:    ori r7, r7, 47143
 ; P8LE-NEXT:    ori r9, r9, 30865
 ; P8LE-NEXT:    mffprd r4, f0
-; P8LE-NEXT:    rldicl r5, r4, 32, 48
-; P8LE-NEXT:    rldicl r6, r4, 16, 48
+; P8LE-NEXT:    extrdi r5, r4, 16, 16
+; P8LE-NEXT:    srdi r6, r4, 48
 ; P8LE-NEXT:    clrlwi r8, r5, 16
-; P8LE-NEXT:    rldicl r4, r4, 48, 48
+; P8LE-NEXT:    extrdi r4, r4, 16, 32
 ; P8LE-NEXT:    mulhwu r3, r8, r3
 ; P8LE-NEXT:    clrlwi r8, r6, 16
 ; P8LE-NEXT:    mulhwu r7, r8, r7
-; P8LE-NEXT:    rlwinm r8, r4, 31, 17, 31
+; P8LE-NEXT:    extrwi r8, r4, 15, 16
 ; P8LE-NEXT:    mulhwu r8, r8, r9
 ; P8LE-NEXT:    srwi r3, r3, 4
 ; P8LE-NEXT:    srwi r7, r7, 11
@@ -1016,12 +1016,12 @@
 ; P8BE-NEXT:    ori r7, r7, 17097
 ; P8BE-NEXT:    ori r8, r8, 30865
 ; P8BE-NEXT:    clrldi r5, r4, 48
-; P8BE-NEXT:    rldicl r6, r4, 48, 48
-; P8BE-NEXT:    rldicl r4, r4, 32, 48
+; P8BE-NEXT:    extrdi r6, r4, 16, 32
+; P8BE-NEXT:    extrdi r4, r4, 16, 16
 ; P8BE-NEXT:    clrlwi r5, r5, 16
 ; P8BE-NEXT:    clrlwi r6, r6, 16
 ; P8BE-NEXT:    mulhwu r3, r5, r3
-; P8BE-NEXT:    rlwinm r9, r4, 31, 17, 31
+; P8BE-NEXT:    extrwi r9, r4, 15, 16
 ; P8BE-NEXT:    clrlwi r4, r4, 16
 ; P8BE-NEXT:    mulhwu r7, r6, r7
 ; P8BE-NEXT:    mulhwu r8, r9, r8
@@ -1072,10 +1072,10 @@
 ; P9LE-NEXT:    ori r4, r4, 17097
 ; P9LE-NEXT:    mulhdu r4, r3, r4
 ; P9LE-NEXT:    sub r5, r3, r4
-; P9LE-NEXT:    rldicl r5, r5, 63, 1
+; P9LE-NEXT:    srdi r5, r5, 1
 ; P9LE-NEXT:    add r4, r5, r4
 ; P9LE-NEXT:    lis r5, -16037
-; P9LE-NEXT:    rldicl r4, r4, 60, 4
+; P9LE-NEXT:    srdi r4, r4, 4
 ; P9LE-NEXT:    ori r5, r5, 28749
 ; P9LE-NEXT:    mulli r4, r4, 23
 ; P9LE-NEXT:    sldi r5, r5, 32
@@ -1084,7 +1084,7 @@
 ; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    mfvsrd r4, v3
 ; P9LE-NEXT:    mulhdu r5, r4, r5
-; P9LE-NEXT:    rldicl r5, r5, 52, 12
+; P9LE-NEXT:    srdi r5, r5, 12
 ; P9LE-NEXT:    mulli r5, r5, 5423
 ; P9LE-NEXT:    sub r4, r4, r5
 ; P9LE-NEXT:    lis r5, 25653
@@ -1092,11 +1092,11 @@
 ; P9LE-NEXT:    sldi r5, r5, 32
 ; P9LE-NEXT:    mtvsrdd v3, r4, r3
 ; P9LE-NEXT:    mfvsrd r3, v2
-; P9LE-NEXT:    rldicl r4, r3, 63, 1
+; P9LE-NEXT:    srdi r4, r3, 1
 ; P9LE-NEXT:    oris r5, r5, 1603
 ; P9LE-NEXT:    ori r5, r5, 21445
 ; P9LE-NEXT:    mulhdu r4, r4, r5
-; P9LE-NEXT:    rldicl r4, r4, 57, 7
+; P9LE-NEXT:    srdi r4, r4, 7
 ; P9LE-NEXT:    mulli r4, r4, 654
 ; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    li r4, 0
@@ -1113,10 +1113,10 @@
 ; P9BE-NEXT:    ori r4, r4, 17097
 ; P9BE-NEXT:    mulhdu r4, r3, r4
 ; P9BE-NEXT:    sub r5, r3, r4
-; P9BE-NEXT:    rldicl r5, r5, 63, 1
+; P9BE-NEXT:    srdi r5, r5, 1
 ; P9BE-NEXT:    add r4, r5, r4
 ; P9BE-NEXT:    lis r5, -16037
-; P9BE-NEXT:    rldicl r4, r4, 60, 4
+; P9BE-NEXT:    srdi r4, r4, 4
 ; P9BE-NEXT:    mulli r4, r4, 23
 ; P9BE-NEXT:    ori r5, r5, 28749
 ; P9BE-NEXT:    sldi r5, r5, 32
@@ -1125,7 +1125,7 @@
 ; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    mfvsrld r4, v3
 ; P9BE-NEXT:    mulhdu r5, r4, r5
-; P9BE-NEXT:    rldicl r5, r5, 52, 12
+; P9BE-NEXT:    srdi r5, r5, 12
 ; P9BE-NEXT:    mulli r5, r5, 5423
 ; P9BE-NEXT:    sub r4, r4, r5
 ; P9BE-NEXT:    lis r5, 25653
@@ -1133,11 +1133,11 @@
 ; P9BE-NEXT:    sldi r5, r5, 32
 ; P9BE-NEXT:    mtvsrdd v3, r3, r4
 ; P9BE-NEXT:    mfvsrld r3, v2
-; P9BE-NEXT:    rldicl r4, r3, 63, 1
+; P9BE-NEXT:    srdi r4, r3, 1
 ; P9BE-NEXT:    oris r5, r5, 1603
 ; P9BE-NEXT:    ori r5, r5, 21445
 ; P9BE-NEXT:    mulhdu r4, r4, r5
-; P9BE-NEXT:    rldicl r4, r4, 57, 7
+; P9BE-NEXT:    srdi r4, r4, 7
 ; P9BE-NEXT:    mulli r4, r4, 654
 ; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    mtvsrdd v2, 0, r3
@@ -1164,17 +1164,17 @@
 ; P8LE-NEXT:    oris r5, r5, 1603
 ; P8LE-NEXT:    ori r4, r4, 12109
 ; P8LE-NEXT:    mulhdu r3, r7, r3
-; P8LE-NEXT:    rldicl r9, r6, 63, 1
+; P8LE-NEXT:    srdi r9, r6, 1
 ; P8LE-NEXT:    ori r5, r5, 21445
 ; P8LE-NEXT:    mulhdu r4, r8, r4
 ; P8LE-NEXT:    mulhdu r5, r9, r5
 ; P8LE-NEXT:    sub r9, r7, r3
-; P8LE-NEXT:    rldicl r9, r9, 63, 1
-; P8LE-NEXT:    rldicl r4, r4, 52, 12
+; P8LE-NEXT:    srdi r9, r9, 1
+; P8LE-NEXT:    srdi r4, r4, 12
 ; P8LE-NEXT:    add r3, r9, r3
-; P8LE-NEXT:    rldicl r5, r5, 57, 7
+; P8LE-NEXT:    srdi r5, r5, 7
 ; P8LE-NEXT:    mulli r4, r4, 5423
-; P8LE-NEXT:    rldicl r3, r3, 60, 4
+; P8LE-NEXT:    srdi r3, r3, 4
 ; P8LE-NEXT:    mulli r5, r5, 654
 ; P8LE-NEXT:    mulli r3, r3, 23
 ; P8LE-NEXT:    sub r4, r8, r4
@@ -1213,15 +1213,15 @@
 ; P8BE-NEXT:    mulhdu r3, r6, r3
 ; P8BE-NEXT:    ori r5, r5, 21445
 ; P8BE-NEXT:    mulhdu r4, r7, r4
-; P8BE-NEXT:    rldicl r9, r8, 63, 1
+; P8BE-NEXT:    srdi r9, r8, 1
 ; P8BE-NEXT:    mulhdu r5, r9, r5
 ; P8BE-NEXT:    sub r9, r6, r3
-; P8BE-NEXT:    rldicl r9, r9, 63, 1
-; P8BE-NEXT:    rldicl r4, r4, 52, 12
+; P8BE-NEXT:    srdi r9, r9, 1
+; P8BE-NEXT:    srdi r4, r4, 12
 ; P8BE-NEXT:    add r3, r9, r3
 ; P8BE-NEXT:    mulli r4, r4, 5423
-; P8BE-NEXT:    rldicl r5, r5, 57, 7
-; P8BE-NEXT:    rldicl r3, r3, 60, 4
+; P8BE-NEXT:    srdi r5, r5, 7
+; P8BE-NEXT:    srdi r3, r3, 4
 ; P8BE-NEXT:    mulli r5, r5, 654
 ; P8BE-NEXT:    mulli r3, r3, 23
 ; P8BE-NEXT:    sub r4, r7, r4
diff --git a/llvm/test/CodeGen/PowerPC/variable_elem_vec_extracts.ll b/llvm/test/CodeGen/PowerPC/variable_elem_vec_extracts.ll
--- a/llvm/test/CodeGen/PowerPC/variable_elem_vec_extracts.ll
+++ b/llvm/test/CodeGen/PowerPC/variable_elem_vec_extracts.ll
@@ -23,7 +23,7 @@
 ; CHECK: mfvsrd [[TOGPR:[0-9]+]],
 ; CHECK: srd [[RSHREG:[0-9]+]], [[TOGPR]], [[SHAMREG]]
 ; CHECK: extsw 3, [[RSHREG]]
-; CHECK-P7-DAG: rlwinm [[ELEMOFFREG:[0-9]+]], 5, 2, 28, 29
+; CHECK-P7-DAG: clrlslwi [[ELEMOFFREG:[0-9]+]], 5, 30, 2
 ; CHECK-P7-DAG: stxvw4x 34,
 ; CHECK-P7: lwax 3, 3, [[ELEMOFFREG]]
 ; CHECK-BE-DAG: andi. [[ANDREG:[0-9]+]], 5, 2
@@ -52,7 +52,7 @@
 ; CHECK-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]]
 ; CHECK-DAG: vperm [[PERMVEC:[0-9]+]], 2, 2, [[SHMSKREG]]
 ; CHECK: mfvsrd 3,
-; CHECK-P7-DAG: rlwinm [[ELEMOFFREG:[0-9]+]], 5, 3, 28, 28
+; CHECK-P7-DAG: clrlslwi [[ELEMOFFREG:[0-9]+]], 5, 31
 ; CHECK-P7-DAG: stxvd2x 34,
 ; CHECK-P7: ldx 3, 3, [[ELEMOFFREG]]
 ; CHECK-BE-DAG: andi. [[ANDREG:[0-9]+]], 5, 1
@@ -75,7 +75,7 @@
 ; CHECK: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]]
 ; CHECK: vperm {{[0-9]+}}, 2, 2, [[SHMSKREG]]
 ; CHECK: xscvspdpn 1,
-; CHECK-P7-DAG: rlwinm [[ELEMOFFREG:[0-9]+]], 5, 2, 28, 29
+; CHECK-P7-DAG: clrlslwi [[ELEMOFFREG:[0-9]+]], 5, 30, 2
 ; CHECK-P7-DAG: stxvw4x 34,
 ; CHECK-P7: lfsx 1, 3, [[ELEMOFFREG]]
 ; CHECK-BE: sldi [[ELNOREG:[0-9]+]], 5, 2
diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll
--- a/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll
+++ b/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll
@@ -15,7 +15,7 @@
 ; CHECK-P8-NEXT:    mtfprd f0, r3
 ; CHECK-P8-NEXT:    mffprd r3, f0
 ; CHECK-P8-NEXT:    clrldi r4, r3, 48
-; CHECK-P8-NEXT:    rldicl r3, r3, 48, 48
+; CHECK-P8-NEXT:    extrdi r3, r3, 16, 32
 ; CHECK-P8-NEXT:    clrlwi r4, r4, 16
 ; CHECK-P8-NEXT:    clrlwi r3, r3, 16
 ; CHECK-P8-NEXT:    mtfprwz f0, r4
@@ -267,7 +267,7 @@
 ; CHECK-P8-NEXT:    mtfprd f0, r3
 ; CHECK-P8-NEXT:    mffprd r3, f0
 ; CHECK-P8-NEXT:    clrldi r4, r3, 48
-; CHECK-P8-NEXT:    rldicl r3, r3, 48, 48
+; CHECK-P8-NEXT:    extrdi r3, r3, 16, 32
 ; CHECK-P8-NEXT:    extsh r4, r4
 ; CHECK-P8-NEXT:    extsh r3, r3
 ; CHECK-P8-NEXT:    mtfprwa f0, r4
diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll
--- a/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll
+++ b/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll
@@ -15,7 +15,7 @@
 ; CHECK-P8-NEXT:    mtfprd f0, r3
 ; CHECK-P8-NEXT:    mffprd r3, f0
 ; CHECK-P8-NEXT:    clrldi r4, r3, 56
-; CHECK-P8-NEXT:    rldicl r3, r3, 56, 56
+; CHECK-P8-NEXT:    extrdi r3, r3, 8, 48
 ; CHECK-P8-NEXT:    clrlwi r4, r4, 24
 ; CHECK-P8-NEXT:    clrlwi r3, r3, 24
 ; CHECK-P8-NEXT:    mtfprwz f0, r4
@@ -283,7 +283,7 @@
 ; CHECK-P8-NEXT:    mtfprd f0, r3
 ; CHECK-P8-NEXT:    mffprd r3, f0
 ; CHECK-P8-NEXT:    clrldi r4, r3, 56
-; CHECK-P8-NEXT:    rldicl r3, r3, 56, 56
+; CHECK-P8-NEXT:    extrdi r3, r3, 8, 48
 ; CHECK-P8-NEXT:    extsb r4, r4
 ; CHECK-P8-NEXT:    extsb r3, r3
 ; CHECK-P8-NEXT:    mtfprwa f0, r4
diff --git a/llvm/test/CodeGen/PowerPC/vec_extract_p9.ll b/llvm/test/CodeGen/PowerPC/vec_extract_p9.ll
--- a/llvm/test/CodeGen/PowerPC/vec_extract_p9.ll
+++ b/llvm/test/CodeGen/PowerPC/vec_extract_p9.ll
@@ -8,6 +8,7 @@
 ; CHECK-LE-NEXT:    vextubrx 3, 5, 2
 ; CHECK-LE-NEXT:    clrldi 3, 3, 56
 ; CHECK-LE-NEXT:    blr
+;
 ; CHECK-BE-LABEL: test1:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vextublx 3, 5, 2
@@ -25,6 +26,7 @@
 ; CHECK-LE-NEXT:    vextubrx 3, 5, 2
 ; CHECK-LE-NEXT:    extsb 3, 3
 ; CHECK-LE-NEXT:    blr
+;
 ; CHECK-BE-LABEL: test2:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vextublx 3, 5, 2
@@ -39,13 +41,14 @@
 define zeroext i16 @test3(<8 x i16> %a, i32 signext %index) {
 ; CHECK-LE-LABEL: test3:
 ; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    rlwinm 3, 5, 1, 28, 30
+; CHECK-LE-NEXT:    clrlslwi 3, 5, 29, 1
 ; CHECK-LE-NEXT:    vextuhrx 3, 3, 2
 ; CHECK-LE-NEXT:    clrldi 3, 3, 48
 ; CHECK-LE-NEXT:    blr
+;
 ; CHECK-BE-LABEL: test3:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    rlwinm 3, 5, 1, 28, 30
+; CHECK-BE-NEXT:    clrlslwi 3, 5, 29, 1
 ; CHECK-BE-NEXT:    vextuhlx 3, 3, 2
 ; CHECK-BE-NEXT:    clrldi 3, 3, 48
 ; CHECK-BE-NEXT:    blr
@@ -58,13 +61,14 @@
 define signext i16 @test4(<8 x i16> %a, i32 signext %index) {
 ; CHECK-LE-LABEL: test4:
 ; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    rlwinm 3, 5, 1, 28, 30
+; CHECK-LE-NEXT:    clrlslwi 3, 5, 29, 1
 ; CHECK-LE-NEXT:    vextuhrx 3, 3, 2
 ; CHECK-LE-NEXT:    extsh 3, 3
 ; CHECK-LE-NEXT:    blr
+;
 ; CHECK-BE-LABEL: test4:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    rlwinm 3, 5, 1, 28, 30
+; CHECK-BE-NEXT:    clrlslwi 3, 5, 29, 1
 ; CHECK-BE-NEXT:    vextuhlx 3, 3, 2
 ; CHECK-BE-NEXT:    extsh 3, 3
 ; CHECK-BE-NEXT:    blr
@@ -77,12 +81,13 @@
 define zeroext i32 @test5(<4 x i32> %a, i32 signext %index) {
 ; CHECK-LE-LABEL: test5:
 ; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    rlwinm 3, 5, 2, 28, 29
+; CHECK-LE-NEXT:    clrlslwi 3, 5, 30, 2
 ; CHECK-LE-NEXT:    vextuwrx 3, 3, 2
 ; CHECK-LE-NEXT:    blr
+;
 ; CHECK-BE-LABEL: test5:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    rlwinm 3, 5, 2, 28, 29
+; CHECK-BE-NEXT:    clrlslwi 3, 5, 30, 2
 ; CHECK-BE-NEXT:    vextuwlx 3, 3, 2
 ; CHECK-BE-NEXT:    blr
 
@@ -94,13 +99,14 @@
 define signext i32 @test6(<4 x i32> %a, i32 signext %index) {
 ; CHECK-LE-LABEL: test6:
 ; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    rlwinm 3, 5, 2, 28, 29
+; CHECK-LE-NEXT:    clrlslwi 3, 5, 30, 2
 ; CHECK-LE-NEXT:    vextuwrx 3, 3, 2
 ; CHECK-LE-NEXT:    extsw 3, 3
 ; CHECK-LE-NEXT:    blr
+;
 ; CHECK-BE-LABEL: test6:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    rlwinm 3, 5, 2, 28, 29
+; CHECK-BE-NEXT:    clrlslwi 3, 5, 30, 2
 ; CHECK-BE-NEXT:    vextuwlx 3, 3, 2
 ; CHECK-BE-NEXT:    extsw 3, 3
 ; CHECK-BE-NEXT:    blr
@@ -118,6 +124,7 @@
 ; CHECK-LE-NEXT:    vextubrx 3, 3, 2
 ; CHECK-LE-NEXT:    clrldi 3, 3, 56
 ; CHECK-LE-NEXT:    blr
+;
 ; CHECK-BE-LABEL: test7:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    li 3, 1
@@ -137,6 +144,7 @@
 ; CHECK-LE-NEXT:    vextuhrx 3, 3, 2
 ; CHECK-LE-NEXT:    clrldi 3, 3, 48
 ; CHECK-LE-NEXT:    blr
+;
 ; CHECK-BE-LABEL: test8:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    li 3, 2
@@ -155,6 +163,7 @@
 ; CHECK-LE-NEXT:    li 3, 12
 ; CHECK-LE-NEXT:    vextuwrx 3, 3, 2
 ; CHECK-LE-NEXT:    blr
+;
 ; CHECK-BE-LABEL: test9:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    li 3, 12
diff --git a/llvm/test/CodeGen/PowerPC/vec_extract_p9_2.ll b/llvm/test/CodeGen/PowerPC/vec_extract_p9_2.ll
--- a/llvm/test/CodeGen/PowerPC/vec_extract_p9_2.ll
+++ b/llvm/test/CodeGen/PowerPC/vec_extract_p9_2.ll
@@ -49,14 +49,14 @@
 define zeroext i16 @test_add3(<8 x i16> %a, i32 signext %index, i16 zeroext %c) {
 ; CHECK-LE-LABEL: test_add3:
 ; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    rlwinm 3, 5, 1, 28, 30
+; CHECK-LE-NEXT:    clrlslwi 3, 5, 29, 1
 ; CHECK-LE-NEXT:    vextuhrx 3, 3, 2
 ; CHECK-LE-NEXT:    add 3, 3, 6
 ; CHECK-LE-NEXT:    clrldi 3, 3, 48
 ; CHECK-LE-NEXT:    blr
 ; CHECK-BE-LABEL: test_add3:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    rlwinm 3, 5, 1, 28, 30
+; CHECK-BE-NEXT:    clrlslwi 3, 5, 29, 1
 ; CHECK-BE-NEXT:    vextuhlx 3, 3, 2
 ; CHECK-BE-NEXT:    add 3, 3, 6
 ; CHECK-BE-NEXT:    clrldi 3, 3, 48
@@ -73,14 +73,14 @@
 define signext i16 @test_add4(<8 x i16> %a, i32 signext %index, i16 signext %c) {
 ; CHECK-LE-LABEL: test_add4:
 ; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    rlwinm 3, 5, 1, 28, 30
+; CHECK-LE-NEXT:    clrlslwi 3, 5, 29, 1
 ; CHECK-LE-NEXT:    vextuhrx 3, 3, 2
 ; CHECK-LE-NEXT:    add 3, 3, 6
 ; CHECK-LE-NEXT:    extsh 3, 3
 ; CHECK-LE-NEXT:    blr
 ; CHECK-BE-LABEL: test_add4:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    rlwinm 3, 5, 1, 28, 30
+; CHECK-BE-NEXT:    clrlslwi 3, 5, 29, 1
 ; CHECK-BE-NEXT:    vextuhlx 3, 3, 2
 ; CHECK-BE-NEXT:    add 3, 3, 6
 ; CHECK-BE-NEXT:    extsh 3, 3
@@ -97,14 +97,14 @@
 define zeroext i32 @test_add5(<4 x i32> %a, i32 signext %index, i32 zeroext %c) {
 ; CHECK-LE-LABEL: test_add5:
 ; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    rlwinm 3, 5, 2, 28, 29
+; CHECK-LE-NEXT:    clrlslwi 3, 5, 30, 2
 ; CHECK-LE-NEXT:    vextuwrx 3, 3, 2
 ; CHECK-LE-NEXT:    add 3, 3, 6
 ; CHECK-LE-NEXT:    clrldi 3, 3, 32
 ; CHECK-LE-NEXT:    blr
 ; CHECK-BE-LABEL: test_add5:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    rlwinm 3, 5, 2, 28, 29
+; CHECK-BE-NEXT:    clrlslwi 3, 5, 30, 2
 ; CHECK-BE-NEXT:    vextuwlx 3, 3, 2
 ; CHECK-BE-NEXT:    add 3, 3, 6
 ; CHECK-BE-NEXT:    clrldi 3, 3, 32
@@ -118,14 +118,14 @@
 define signext i32 @test_add6(<4 x i32> %a, i32 signext %index, i32 signext %c) {
 ; CHECK-LE-LABEL: test_add6:
 ; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    rlwinm 3, 5, 2, 28, 29
+; CHECK-LE-NEXT:    clrlslwi 3, 5, 30, 2
 ; CHECK-LE-NEXT:    vextuwrx 3, 3, 2
 ; CHECK-LE-NEXT:    add 3, 3, 6
 ; CHECK-LE-NEXT:    extsw 3, 3
 ; CHECK-LE-NEXT:    blr
 ; CHECK-BE-LABEL: test_add6:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    rlwinm 3, 5, 2, 28, 29
+; CHECK-BE-NEXT:    clrlslwi 3, 5, 30, 2
 ; CHECK-BE-NEXT:    vextuwlx 3, 3, 2
 ; CHECK-BE-NEXT:    add 3, 3, 6
 ; CHECK-BE-NEXT:    extsw 3, 3
diff --git a/llvm/test/CodeGen/PowerPC/vector-rotates.ll b/llvm/test/CodeGen/PowerPC/vector-rotates.ll
--- a/llvm/test/CodeGen/PowerPC/vector-rotates.ll
+++ b/llvm/test/CodeGen/PowerPC/vector-rotates.ll
@@ -114,11 +114,11 @@
 ; CHECK-P7-NEXT:    stxvd2x vs34, 0, r3
 ; CHECK-P7-NEXT:    ld r3, -40(r1)
 ; CHECK-P7-NEXT:    sldi r4, r3, 53
-; CHECK-P7-NEXT:    rldicl r3, r3, 53, 11
+; CHECK-P7-NEXT:    srdi r3, r3, 11
 ; CHECK-P7-NEXT:    std r4, -8(r1)
 ; CHECK-P7-NEXT:    ld r4, -48(r1)
 ; CHECK-P7-NEXT:    sldi r5, r4, 41
-; CHECK-P7-NEXT:    rldicl r4, r4, 41, 23
+; CHECK-P7-NEXT:    srdi r4, r4, 23
 ; CHECK-P7-NEXT:    std r5, -16(r1)
 ; CHECK-P7-NEXT:    addi r5, r1, -16
 ; CHECK-P7-NEXT:    lxvw4x vs0, 0, r5
diff --git a/llvm/test/CodeGen/PowerPC/zext-bitperm.ll b/llvm/test/CodeGen/PowerPC/zext-bitperm.ll
--- a/llvm/test/CodeGen/PowerPC/zext-bitperm.ll
+++ b/llvm/test/CodeGen/PowerPC/zext-bitperm.ll
@@ -8,7 +8,7 @@
 define zeroext i32 @func(i32* %p, i32 zeroext %i) {
 ; CHECK-LABEL: @func
 ; CHECK: addi [[REG1:[0-9]+]], 4, 1
-; CHECK: rlwinm [[REG2:[0-9]+]], [[REG1]], 2, 22, 29
+; CHECK: clrlslwi [[REG2:[0-9]+]], [[REG1]], 24, 2
 ; CHECK-NOT: sldi
 ; CHECK: lwzx 3, 3, [[REG2]]
 ; CHECK: blr
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt
--- a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt
@@ -2068,22 +2068,22 @@
 # CHECK: trap
 0x7f 0xe0 0x00 0x08
 
-# CHECK: rldicr 2, 3, 5, 3
+# CHECK: extldi 2, 3, 4, 5
 0x78 0x62 0x28 0xc4
 
-# CHECK: rldicr. 2, 3, 5, 3
+# CHECK: extldi. 2, 3, 4, 5
 0x78 0x62 0x28 0xc5
 
-# CHECK: rldicl 2, 3, 9, 60
+# CHECK: extrdi 2, 3, 4, 5
 0x78 0x62 0x4f 0x20
 
-# CHECK: rldicl. 2, 3, 9, 60
+# CHECK: extrdi. 2, 3, 4, 5
 0x78 0x62 0x4f 0x21
 
-# CHECK: rldimi 2, 3, 55, 5
+# CHECK: insrdi 2, 3, 4, 5
 0x78 0x62 0xb9 0x4e
 
-# CHECK: rldimi. 2, 3, 55, 5
+# CHECK: insrdi. 2, 3, 4, 5
 0x78 0x62 0xb9 0x4f
 
 # CHECK: rotldi 2, 3, 4
@@ -2107,13 +2107,13 @@
 # CHECK: sldi 2, 3, 4
 0x78 0x62 0x26 0xe4
 
-# CHECK: rldicr. 2, 3, 4, 59
+# CHECK: sldi. 2, 3, 4
 0x78 0x62 0x26 0xe5
 
-# CHECK: rldicl 2, 3, 60, 4
+# CHECK: srdi 2, 3, 4
 0x78 0x62 0xe1 0x02
 
-# CHECK: rldicl. 2, 3, 60, 4
+# CHECK: srdi. 2, 3, 4
 0x78 0x62 0xe1 0x03
 
 # CHECK: clrldi 2, 3, 4
@@ -2122,40 +2122,40 @@
 # CHECK: clrldi. 2, 3, 4
 0x78 0x62 0x01 0x01
 
-# CHECK: rldicr 2, 3, 0, 59
+# CHECK: clrrdi 2, 3, 4
 0x78 0x62 0x06 0xe4
 
-# CHECK: rldicr. 2, 3, 0, 59
+# CHECK: clrrdi. 2, 3, 4
 0x78 0x62 0x06 0xe5
 
-# CHECK: rldic 2, 3, 4, 1
+# CHECK: clrlsldi 2, 3, 5, 4
 0x78 0x62 0x20 0x48
 
-# CHECK: rldic. 2, 3, 4, 1
+# CHECK: clrlsldi. 2, 3, 5, 4
 0x78 0x62 0x20 0x49
 
-# CHECK: rlwinm 2, 3, 5, 0, 3
+# CHECK: extlwi 2, 3, 4, 5
 0x54 0x62 0x28 0x06
 
-# CHECK: rlwinm. 2, 3, 5, 0, 3
+# CHECK: extlwi. 2, 3, 4, 5
 0x54 0x62 0x28 0x07
 
-# CHECK: rlwinm 2, 3, 9, 28, 31
+# CHECK: extrwi 2, 3, 4, 5
 0x54 0x62 0x4f 0x3e
 
-# CHECK: rlwinm. 2, 3, 9, 28, 31
+# CHECK: extrwi. 2, 3, 4, 5
 0x54 0x62 0x4f 0x3f
 
-# CHECK: rlwimi 2, 3, 27, 5, 8
+# CHECK: inslwi 2, 3, 4, 5
 0x50 0x62 0xd9 0x50
 
-# CHECK: rlwimi. 2, 3, 27, 5, 8
+# CHECK: inslwi. 2, 3, 4, 5
 0x50 0x62 0xd9 0x51
 
-# CHECK: rlwimi 2, 3, 23, 5, 8
+# CHECK: insrwi 2, 3, 4, 5
 0x50 0x62 0xb9 0x50
 
-# CHECK: rlwimi. 2, 3, 23, 5, 8
+# CHECK: insrwi. 2, 3, 4, 5
 0x50 0x62 0xb9 0x51
 
 # CHECK: rotlwi 2, 3, 4
@@ -2179,13 +2179,13 @@
 # CHECK: slwi 2, 3, 4
 0x54 0x62 0x20 0x36
 
-# CHECK: rlwinm. 2, 3, 4, 0, 27
+# CHECK: slwi. 2, 3, 4
 0x54 0x62 0x20 0x37
 
 # CHECK: srwi 2, 3, 4
 0x54 0x62 0xe1 0x3e
 
-# CHECK: rlwinm. 2, 3, 28, 4, 31
+# CHECK: srwi. 2, 3, 4
 0x54 0x62 0xe1 0x3f
 
 # CHECK: clrlwi 2, 3, 4
@@ -2194,16 +2194,16 @@
 # CHECK: clrlwi. 2, 3, 4
 0x54 0x62 0x01 0x3f
 
-# CHECK: rlwinm 2, 3, 0, 0, 27
+# CHECK: clrrwi 2, 3, 4
 0x54 0x62 0x00 0x36
 
-# CHECK: rlwinm. 2, 3, 0, 0, 27
+# CHECK: clrrwi. 2, 3, 4
 0x54 0x62 0x00 0x37
 
-# CHECK: rlwinm 2, 3, 4, 1, 27
+# CHECK: clrlslwi 2, 3, 5, 4
 0x54 0x62 0x20 0x76
 
-# CHECK: rlwinm. 2, 3, 4, 1, 27
+# CHECK: clrlslwi. 2, 3, 5, 4
 0x54 0x62 0x20 0x77
 
 # CHECK: mtxer 2
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt
--- a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt
@@ -745,16 +745,16 @@
 # CHECK: rldicl. 2, 3, 4, 5              
 0x78 0x62 0x21 0x41
 
-# CHECK: rldicr 2, 3, 4, 5               
+# CHECK: extldi 2, 3, 6, 4               
 0x78 0x62 0x21 0x44
 
-# CHECK: rldicr. 2, 3, 4, 5              
+# CHECK: extldi. 2, 3, 6, 4              
 0x78 0x62 0x21 0x45
 
-# CHECK: rldic 2, 3, 4, 5                
+# CHECK: clrlsldi 2, 3, 9, 4             
 0x78 0x62 0x21 0x48
 
-# CHECK: rldic. 2, 3, 4, 5               
+# CHECK: clrlsldi. 2, 3, 9, 4            
 0x78 0x62 0x21 0x49
 
 # CHECK: rldcl 2, 3, 4, 5                
@@ -769,10 +769,10 @@
 # CHECK: rldcr. 2, 3, 4, 5               
 0x78 0x62 0x21 0x53
 
-# CHECK: rldimi 2, 3, 4, 5               
+# CHECK: insrdi 2, 3, 55, 5              
 0x78 0x62 0x21 0x4c
 
-# CHECK: rldimi. 2, 3, 4, 5              
+# CHECK: insrdi. 2, 3, 55, 5              
 0x78 0x62 0x21 0x4d
 
 # CHECK: slw 2, 3, 4                     
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt
--- a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt
@@ -700,16 +700,16 @@
 # CHECK: rldicl. 2, 3, 4, 5
 0x41 0x21 0x62 0x78
 
-# CHECK: rldicr 2, 3, 4, 5
+# CHECK: extldi 2, 3, 6, 4
 0x44 0x21 0x62 0x78
 
-# CHECK: rldicr. 2, 3, 4, 5
+# CHECK: extldi. 2, 3, 6, 4
 0x45 0x21 0x62 0x78
 
-# CHECK: rldic 2, 3, 4, 5
+# CHECK: clrlsldi 2, 3, 9, 4
 0x48 0x21 0x62 0x78
 
-# CHECK: rldic. 2, 3, 4, 5
+# CHECK: clrlsldi. 2, 3, 9, 4
 0x49 0x21 0x62 0x78
 
 # CHECK: rldcl 2, 3, 4, 5
@@ -724,10 +724,10 @@
 # CHECK: rldcr. 2, 3, 4, 5
 0x53 0x21 0x62 0x78
 
-# CHECK: rldimi 2, 3, 4, 5
+# CHECK: insrdi 2, 3, 55, 5
 0x4c 0x21 0x62 0x78
 
-# CHECK: rldimi. 2, 3, 4, 5
+# CHECK: insrdi. 2, 3, 55, 5
 0x4d 0x21 0x62 0x78
 
 # CHECK: slw 2, 3, 4
diff --git a/llvm/test/MC/PowerPC/ppc64-encoding-ext.s b/llvm/test/MC/PowerPC/ppc64-encoding-ext.s
--- a/llvm/test/MC/PowerPC/ppc64-encoding-ext.s
+++ b/llvm/test/MC/PowerPC/ppc64-encoding-ext.s
@@ -3271,23 +3271,23 @@
 
 # Rotate and shift mnemonics
 
-# CHECK-BE: rldicr 2, 3, 5, 3               # encoding: [0x78,0x62,0x28,0xc4]
-# CHECK-LE: rldicr 2, 3, 5, 3               # encoding: [0xc4,0x28,0x62,0x78]
+# CHECK-BE: extldi 2, 3, 4, 5               # encoding: [0x78,0x62,0x28,0xc4]
+# CHECK-LE: extldi 2, 3, 4, 5               # encoding: [0xc4,0x28,0x62,0x78]
             extldi 2, 3, 4, 5
-# CHECK-BE: rldicr. 2, 3, 5, 3              # encoding: [0x78,0x62,0x28,0xc5]
-# CHECK-LE: rldicr. 2, 3, 5, 3              # encoding: [0xc5,0x28,0x62,0x78]
+# CHECK-BE: extldi. 2, 3, 4, 5              # encoding: [0x78,0x62,0x28,0xc5]
+# CHECK-LE: extldi. 2, 3, 4, 5              # encoding: [0xc5,0x28,0x62,0x78]
             extldi. 2, 3, 4, 5
-# CHECK-BE: rldicl 2, 3, 9, 60              # encoding: [0x78,0x62,0x4f,0x20]
-# CHECK-LE: rldicl 2, 3, 9, 60              # encoding: [0x20,0x4f,0x62,0x78]
+# CHECK-BE: extrdi 2, 3, 4, 5               # encoding: [0x78,0x62,0x4f,0x20]
+# CHECK-LE: extrdi 2, 3, 4, 5               # encoding: [0x20,0x4f,0x62,0x78]
             extrdi 2, 3, 4, 5
-# CHECK-BE: rldicl. 2, 3, 9, 60             # encoding: [0x78,0x62,0x4f,0x21]
-# CHECK-LE: rldicl. 2, 3, 9, 60             # encoding: [0x21,0x4f,0x62,0x78]
+# CHECK-BE: extrdi. 2, 3, 4, 5              # encoding: [0x78,0x62,0x4f,0x21]
+# CHECK-LE: extrdi. 2, 3, 4, 5              # encoding: [0x21,0x4f,0x62,0x78]
             extrdi. 2, 3, 4, 5
-# CHECK-BE: rldimi 2, 3, 55, 5              # encoding: [0x78,0x62,0xb9,0x4e]
-# CHECK-LE: rldimi 2, 3, 55, 5              # encoding: [0x4e,0xb9,0x62,0x78]
+# CHECK-BE: insrdi 2, 3, 4, 5               # encoding: [0x78,0x62,0xb9,0x4e]
+# CHECK-LE: insrdi 2, 3, 4, 5               # encoding: [0x4e,0xb9,0x62,0x78]
             insrdi 2, 3, 4, 5
-# CHECK-BE: rldimi. 2, 3, 55, 5             # encoding: [0x78,0x62,0xb9,0x4f]
-# CHECK-LE: rldimi. 2, 3, 55, 5             # encoding: [0x4f,0xb9,0x62,0x78]
+# CHECK-BE: insrdi. 2, 3, 4, 5              # encoding: [0x78,0x62,0xb9,0x4f]
+# CHECK-LE: insrdi. 2, 3, 4, 5              # encoding: [0x4f,0xb9,0x62,0x78]
             insrdi. 2, 3, 4, 5
 # CHECK-BE: rotldi 2, 3, 4                  # encoding: [0x78,0x62,0x20,0x00]
 # CHECK-LE: rotldi 2, 3, 4                  # encoding: [0x00,0x20,0x62,0x78]
@@ -3310,14 +3310,14 @@
 # CHECK-BE: sldi 2, 3, 4                    # encoding: [0x78,0x62,0x26,0xe4]
 # CHECK-LE: sldi 2, 3, 4                    # encoding: [0xe4,0x26,0x62,0x78]
             sldi 2, 3, 4
-# CHECK-BE: rldicr. 2, 3, 4, 59             # encoding: [0x78,0x62,0x26,0xe5]
-# CHECK-LE: rldicr. 2, 3, 4, 59             # encoding: [0xe5,0x26,0x62,0x78]
+# CHECK-BE: sldi. 2, 3, 4                   # encoding: [0x78,0x62,0x26,0xe5]
+# CHECK-LE: sldi. 2, 3, 4                   # encoding: [0xe5,0x26,0x62,0x78]
             sldi. 2, 3, 4
-# CHECK-BE: rldicl 2, 3, 60, 4              # encoding: [0x78,0x62,0xe1,0x02]
-# CHECK-LE: rldicl 2, 3, 60, 4              # encoding: [0x02,0xe1,0x62,0x78]
+# CHECK-BE: srdi 2, 3, 4                    # encoding: [0x78,0x62,0xe1,0x02]
+# CHECK-LE: srdi 2, 3, 4                    # encoding: [0x02,0xe1,0x62,0x78]
             srdi 2, 3, 4
-# CHECK-BE: rldicl. 2, 3, 60, 4             # encoding: [0x78,0x62,0xe1,0x03]
-# CHECK-LE: rldicl. 2, 3, 60, 4             # encoding: [0x03,0xe1,0x62,0x78]
+# CHECK-BE: srdi. 2, 3, 4                   # encoding: [0x78,0x62,0xe1,0x03]
+# CHECK-LE: srdi. 2, 3, 4                   # encoding: [0x03,0xe1,0x62,0x78]
             srdi. 2, 3, 4
 # CHECK-BE: clrldi 2, 3, 4                  # encoding: [0x78,0x62,0x01,0x00]
 # CHECK-LE: clrldi 2, 3, 4                  # encoding: [0x00,0x01,0x62,0x78]
@@ -3325,42 +3325,42 @@
 # CHECK-BE: clrldi. 2, 3, 4                 # encoding: [0x78,0x62,0x01,0x01]
 # CHECK-LE: clrldi. 2, 3, 4                 # encoding: [0x01,0x01,0x62,0x78]
             clrldi. 2, 3, 4
-# CHECK-BE: rldicr 2, 3, 0, 59              # encoding: [0x78,0x62,0x06,0xe4]
-# CHECK-LE: rldicr 2, 3, 0, 59              # encoding: [0xe4,0x06,0x62,0x78]
+# CHECK-BE: clrrdi 2, 3, 4                  # encoding: [0x78,0x62,0x06,0xe4]
+# CHECK-LE: clrrdi 2, 3, 4                  # encoding: [0xe4,0x06,0x62,0x78]
             clrrdi 2, 3, 4
-# CHECK-BE: rldicr. 2, 3, 0, 59             # encoding: [0x78,0x62,0x06,0xe5]
-# CHECK-LE: rldicr. 2, 3, 0, 59             # encoding: [0xe5,0x06,0x62,0x78]
+# CHECK-BE: clrrdi. 2, 3, 4                 # encoding: [0x78,0x62,0x06,0xe5]
+# CHECK-LE: clrrdi. 2, 3, 4                 # encoding: [0xe5,0x06,0x62,0x78]
             clrrdi. 2, 3, 4
-# CHECK-BE: rldic 2, 3, 4, 1                # encoding: [0x78,0x62,0x20,0x48]
-# CHECK-LE: rldic 2, 3, 4, 1                # encoding: [0x48,0x20,0x62,0x78]
+# CHECK-BE: clrlsldi 2, 3, 5, 4             # encoding: [0x78,0x62,0x20,0x48]
+# CHECK-LE: clrlsldi 2, 3, 5, 4             # encoding: [0x48,0x20,0x62,0x78]
             clrlsldi 2, 3, 5, 4
-# CHECK-BE: rldic. 2, 3, 4, 1               # encoding: [0x78,0x62,0x20,0x49]
-# CHECK-LE: rldic. 2, 3, 4, 1               # encoding: [0x49,0x20,0x62,0x78]
+# CHECK-BE: clrlsldi. 2, 3, 5, 4            # encoding: [0x78,0x62,0x20,0x49]
+# CHECK-LE: clrlsldi. 2, 3, 5, 4            # encoding: [0x49,0x20,0x62,0x78]
             clrlsldi. 2, 3, 5, 4
 
-# CHECK-BE: rlwinm 2, 3, 5, 0, 3            # encoding: [0x54,0x62,0x28,0x06]
-# CHECK-LE: rlwinm 2, 3, 5, 0, 3            # encoding: [0x06,0x28,0x62,0x54]
+# CHECK-BE: extlwi 2, 3, 4, 5               # encoding: [0x54,0x62,0x28,0x06]
+# CHECK-LE: extlwi 2, 3, 4, 5               # encoding: [0x06,0x28,0x62,0x54]
             extlwi 2, 3, 4, 5
-# CHECK-BE: rlwinm. 2, 3, 5, 0, 3           # encoding: [0x54,0x62,0x28,0x07]
-# CHECK-LE: rlwinm. 2, 3, 5, 0, 3           # encoding: [0x07,0x28,0x62,0x54]
+# CHECK-BE: extlwi. 2, 3, 4, 5              # encoding: [0x54,0x62,0x28,0x07]
+# CHECK-LE: extlwi. 2, 3, 4, 5              # encoding: [0x07,0x28,0x62,0x54]
             extlwi. 2, 3, 4, 5
-# CHECK-BE: rlwinm 2, 3, 9, 28, 31          # encoding: [0x54,0x62,0x4f,0x3e]
-# CHECK-LE: rlwinm 2, 3, 9, 28, 31          # encoding: [0x3e,0x4f,0x62,0x54]
+# CHECK-BE: extrwi 2, 3, 4, 5               # encoding: [0x54,0x62,0x4f,0x3e]
+# CHECK-LE: extrwi 2, 3, 4, 5               # encoding: [0x3e,0x4f,0x62,0x54]
             extrwi 2, 3, 4, 5
-# CHECK-BE: rlwinm. 2, 3, 9, 28, 31         # encoding: [0x54,0x62,0x4f,0x3f]
-# CHECK-LE: rlwinm. 2, 3, 9, 28, 31         # encoding: [0x3f,0x4f,0x62,0x54]
+# CHECK-BE: extrwi. 2, 3, 4, 5              # encoding: [0x54,0x62,0x4f,0x3f]
+# CHECK-LE: extrwi. 2, 3, 4, 5              # encoding: [0x3f,0x4f,0x62,0x54]
             extrwi. 2, 3, 4, 5
-# CHECK-BE: rlwimi 2, 3, 27, 5, 8           # encoding: [0x50,0x62,0xd9,0x50]
-# CHECK-LE: rlwimi 2, 3, 27, 5, 8           # encoding: [0x50,0xd9,0x62,0x50]
+# CHECK-BE: inslwi 2, 3, 4, 5               # encoding: [0x50,0x62,0xd9,0x50]
+# CHECK-LE: inslwi 2, 3, 4, 5               # encoding: [0x50,0xd9,0x62,0x50]
             inslwi 2, 3, 4, 5
-# CHECK-BE: rlwimi. 2, 3, 27, 5, 8          # encoding: [0x50,0x62,0xd9,0x51]
-# CHECK-LE: rlwimi. 2, 3, 27, 5, 8          # encoding: [0x51,0xd9,0x62,0x50]
+# CHECK-BE: inslwi. 2, 3, 4, 5              # encoding: [0x50,0x62,0xd9,0x51]
+# CHECK-LE: inslwi. 2, 3, 4, 5              # encoding: [0x51,0xd9,0x62,0x50]
             inslwi. 2, 3, 4, 5
-# CHECK-BE: rlwimi 2, 3, 23, 5, 8           # encoding: [0x50,0x62,0xb9,0x50]
-# CHECK-LE: rlwimi 2, 3, 23, 5, 8           # encoding: [0x50,0xb9,0x62,0x50]
+# CHECK-BE: insrwi 2, 3, 4, 5               # encoding: [0x50,0x62,0xb9,0x50]
+# CHECK-LE: insrwi 2, 3, 4, 5               # encoding: [0x50,0xb9,0x62,0x50]
             insrwi 2, 3, 4, 5
-# CHECK-BE: rlwimi. 2, 3, 23, 5, 8          # encoding: [0x50,0x62,0xb9,0x51]
-# CHECK-LE: rlwimi. 2, 3, 23, 5, 8          # encoding: [0x51,0xb9,0x62,0x50]
+# CHECK-BE: insrwi. 2, 3, 4, 5              # encoding: [0x50,0x62,0xb9,0x51]
+# CHECK-LE: insrwi. 2, 3, 4, 5              # encoding: [0x51,0xb9,0x62,0x50]
             insrwi. 2, 3, 4, 5
 # CHECK-BE: rotlwi 2, 3, 4                  # encoding: [0x54,0x62,0x20,0x3e]
 # CHECK-LE: rotlwi 2, 3, 4                  # encoding: [0x3e,0x20,0x62,0x54]
@@ -3383,14 +3383,14 @@
 # CHECK-BE: slwi 2, 3, 4                    # encoding: [0x54,0x62,0x20,0x36]
 # CHECK-LE: slwi 2, 3, 4                    # encoding: [0x36,0x20,0x62,0x54]
             slwi 2, 3, 4
-# CHECK-BE: rlwinm. 2, 3, 4, 0, 27          # encoding: [0x54,0x62,0x20,0x37]
-# CHECK-LE: rlwinm. 2, 3, 4, 0, 27          # encoding: [0x37,0x20,0x62,0x54]
+# CHECK-BE: slwi. 2, 3, 4                   # encoding: [0x54,0x62,0x20,0x37]
+# CHECK-LE: slwi. 2, 3, 4                   # encoding: [0x37,0x20,0x62,0x54]
             slwi. 2, 3, 4
 # CHECK-BE: srwi 2, 3, 4                    # encoding: [0x54,0x62,0xe1,0x3e]
 # CHECK-LE: srwi 2, 3, 4                    # encoding: [0x3e,0xe1,0x62,0x54]
             srwi 2, 3, 4
-# CHECK-BE: rlwinm. 2, 3, 28, 4, 31         # encoding: [0x54,0x62,0xe1,0x3f]
-# CHECK-LE: rlwinm. 2, 3, 28, 4, 31         # encoding: [0x3f,0xe1,0x62,0x54]
+# CHECK-BE: srwi. 2, 3, 4                   # encoding: [0x54,0x62,0xe1,0x3f]
+# CHECK-LE: srwi. 2, 3, 4                   # encoding: [0x3f,0xe1,0x62,0x54]
             srwi. 2, 3, 4
 # CHECK-BE: clrlwi 2, 3, 4                  # encoding: [0x54,0x62,0x01,0x3e]
 # CHECK-LE: clrlwi 2, 3, 4                  # encoding: [0x3e,0x01,0x62,0x54]
@@ -3398,17 +3398,17 @@
 # CHECK-BE: clrlwi. 2, 3, 4                 # encoding: [0x54,0x62,0x01,0x3f]
 # CHECK-LE: clrlwi. 2, 3, 4                 # encoding: [0x3f,0x01,0x62,0x54]
             clrlwi. 2, 3, 4
-# CHECK-BE: rlwinm 2, 3, 0, 0, 27           # encoding: [0x54,0x62,0x00,0x36]
-# CHECK-LE: rlwinm 2, 3, 0, 0, 27           # encoding: [0x36,0x00,0x62,0x54]
+# CHECK-BE: clrrwi 2, 3, 4                  # encoding: [0x54,0x62,0x00,0x36]
+# CHECK-LE: clrrwi 2, 3, 4                  # encoding: [0x36,0x00,0x62,0x54]
             clrrwi 2, 3, 4
-# CHECK-BE: rlwinm. 2, 3, 0, 0, 27          # encoding: [0x54,0x62,0x00,0x37]
-# CHECK-LE: rlwinm. 2, 3, 0, 0, 27          # encoding: [0x37,0x00,0x62,0x54]
+# CHECK-BE: clrrwi. 2, 3, 4                 # encoding: [0x54,0x62,0x00,0x37]
+# CHECK-LE: clrrwi. 2, 3, 4                 # encoding: [0x37,0x00,0x62,0x54]
             clrrwi. 2, 3, 4
-# CHECK-BE: rlwinm 2, 3, 4, 1, 27           # encoding: [0x54,0x62,0x20,0x76]
-# CHECK-LE: rlwinm 2, 3, 4, 1, 27           # encoding: [0x76,0x20,0x62,0x54]
+# CHECK-BE: clrlslwi 2, 3, 5, 4             # encoding: [0x54,0x62,0x20,0x76]
+# CHECK-LE: clrlslwi 2, 3, 5, 4             # encoding: [0x76,0x20,0x62,0x54]
             clrlslwi 2, 3, 5, 4
-# CHECK-BE: rlwinm. 2, 3, 4, 1, 27          # encoding: [0x54,0x62,0x20,0x77]
-# CHECK-LE: rlwinm. 2, 3, 4, 1, 27          # encoding: [0x77,0x20,0x62,0x54]
+# CHECK-BE: clrlslwi. 2, 3, 5, 4            # encoding: [0x54,0x62,0x20,0x77]
+# CHECK-LE: clrlslwi. 2, 3, 5, 4            # encoding: [0x77,0x20,0x62,0x54]
             clrlslwi. 2, 3, 5, 4
 
 # Move to/from special purpose register mnemonics
diff --git a/llvm/test/MC/PowerPC/ppc64-encoding.s b/llvm/test/MC/PowerPC/ppc64-encoding.s
--- a/llvm/test/MC/PowerPC/ppc64-encoding.s
+++ b/llvm/test/MC/PowerPC/ppc64-encoding.s
@@ -897,17 +897,17 @@
 # CHECK-BE: rldicl. 2, 3, 4, 5              # encoding: [0x78,0x62,0x21,0x41]
 # CHECK-LE: rldicl. 2, 3, 4, 5              # encoding: [0x41,0x21,0x62,0x78]
             rldicl. 2, 3, 4, 5
-# CHECK-BE: rldicr 2, 3, 4, 5               # encoding: [0x78,0x62,0x21,0x44]
-# CHECK-LE: rldicr 2, 3, 4, 5               # encoding: [0x44,0x21,0x62,0x78]
+# CHECK-BE: extldi 2, 3, 6, 4               # encoding: [0x78,0x62,0x21,0x44]
+# CHECK-LE: extldi 2, 3, 6, 4               # encoding: [0x44,0x21,0x62,0x78]
             rldicr 2, 3, 4, 5
-# CHECK-BE: rldicr. 2, 3, 4, 5              # encoding: [0x78,0x62,0x21,0x45]
-# CHECK-LE: rldicr. 2, 3, 4, 5              # encoding: [0x45,0x21,0x62,0x78]
+# CHECK-BE: extldi. 2, 3, 6, 4              # encoding: [0x78,0x62,0x21,0x45]
+# CHECK-LE: extldi. 2, 3, 6, 4              # encoding: [0x45,0x21,0x62,0x78]
             rldicr. 2, 3, 4, 5
-# CHECK-BE: rldic 2, 3, 4, 5                # encoding: [0x78,0x62,0x21,0x48]
-# CHECK-LE: rldic 2, 3, 4, 5                # encoding: [0x48,0x21,0x62,0x78]
+# CHECK-BE: clrlsldi 2, 3, 9, 4             # encoding: [0x78,0x62,0x21,0x48]
+# CHECK-LE: clrlsldi 2, 3, 9, 4             # encoding: [0x48,0x21,0x62,0x78]
             rldic 2, 3, 4, 5
-# CHECK-BE: rldic. 2, 3, 4, 5               # encoding: [0x78,0x62,0x21,0x49]
-# CHECK-LE: rldic. 2, 3, 4, 5               # encoding: [0x49,0x21,0x62,0x78]
+# CHECK-BE: clrlsldi. 2, 3, 9, 4            # encoding: [0x78,0x62,0x21,0x49]
+# CHECK-LE: clrlsldi. 2, 3, 9, 4            # encoding: [0x49,0x21,0x62,0x78]
             rldic. 2, 3, 4, 5
 # CHECK-BE: rldcl 2, 3, 4, 5                # encoding: [0x78,0x62,0x21,0x50]
 # CHECK-LE: rldcl 2, 3, 4, 5                # encoding: [0x50,0x21,0x62,0x78]
@@ -921,18 +921,18 @@
 # CHECK-BE: rldcr. 2, 3, 4, 5               # encoding: [0x78,0x62,0x21,0x53]
 # CHECK-LE: rldcr. 2, 3, 4, 5               # encoding: [0x53,0x21,0x62,0x78]
             rldcr. 2, 3, 4, 5
-# CHECK-BE: rldimi 2, 3, 4, 5               # encoding: [0x78,0x62,0x21,0x4c]
-# CHECK-LE: rldimi 2, 3, 4, 5               # encoding: [0x4c,0x21,0x62,0x78]
+# CHECK-BE: insrdi 2, 3, 55, 5              # encoding: [0x78,0x62,0x21,0x4c]
+# CHECK-LE: insrdi 2, 3, 55, 5              # encoding: [0x4c,0x21,0x62,0x78]
             rldimi 2, 3, 4, 5
-# CHECK-BE: rldimi. 2, 3, 4, 5              # encoding: [0x78,0x62,0x21,0x4d]
-# CHECK-LE: rldimi. 2, 3, 4, 5              # encoding: [0x4d,0x21,0x62,0x78]
+# CHECK-BE: insrdi. 2, 3, 55, 5             # encoding: [0x78,0x62,0x21,0x4d]
+# CHECK-LE: insrdi. 2, 3, 55, 5             # encoding: [0x4d,0x21,0x62,0x78]
             rldimi. 2, 3, 4, 5
 
 # Aliases that take bit masks...
 
-# CHECK-BE: rlwinm  0, 0, 30, 31, 31        # encoding: [0x54,0x00,0xf7,0xfe]
+# CHECK-BE: extrwi  0, 0, 1, 29             # encoding: [0x54,0x00,0xf7,0xfe]
             rlwinm  0, 0, 30, 1
-# CHECK-BE: rlwinm. 0, 0, 30, 31, 31        # encoding: [0x54,0x00,0xf7,0xff]
+# CHECK-BE: extrwi. 0, 0, 1, 29             # encoding: [0x54,0x00,0xf7,0xff]
             rlwinm. 0, 0, 30, 1
 # CHECK-BE: rlwinm  0, 0, 30, 31, 0         # encoding: [0x54,0x00,0xf7,0xc0]
             rlwinm  0, 0, 30, 2147483649