AMDGPU/AMDHSA: Implement new target ID support in AMDGPU backend

[kzhuravl]

Summary

Target ID format is a list of strings delimited by ':', e.g.
amdgcn-amd-amdhsa--gfx908:xnack+:sramecc-. The first string
is an id string which could be triple-cpu but may not be
necessarily so. The other strings are called feature string
which may or may not be target features. Except for the id
string, all feature strings end with '+' or '-'.

  - Add --amdgcn-new-target-id option that enables new
    target ID in the backend (off by default)
  - ELF Header changes
    - Per code object features are now recorded in e_flags
      - xnack, values: default, off, on
        - EF_AMDGPU_FEATURE_XNACK (mask)
        - EF_AMDGPU_FEATURE_XNACK_DEFAULT (1)
        - EF_AMDGPU_FEATURE_XNACK_OFF (2)
        - EF_AMDGPU_FEATURE_XNACK_ON (3)
      - sramecc, values: default, off, on
        - EF_AMDGPU_FEATURE_SRAMECC (mask)
        - EF_AMDGPU_FEATURE_SRAMECC_DEFAULT (1)
        - EF_AMDGPU_FEATURE_SRAMECC_OFF (2)
        - EF_AMDGPU_FEATURE_SRAMECC_ON (3)
    - e_ident[EI_ABIVERSION] is bumped up to 2
  - Metadata
    - Add root metadata with key "amdhsa.target" and value
      being new target id
  - Assembler
    - Parse and emit new target id
  - Tools
    - Relevant update to elf tools

[kzhuravl]

Changes to AMDGPUUsage are WIP.

[MaskRay]

lib/ObjectYAML/ELFYAML.cpp and tools/llvm-readobj/ELFDumper.cpp changes can be made to a separate patch. They are not tightly coupled with the MC/CodeGen changes. A group of binary format focused people will be interested to review that part.

[kzhuravl]

In D81780#2091280, @MaskRay wrote:

lib/ObjectYAML/ELFYAML.cpp and tools/llvm-readobj/ELFDumper.cpp changes can be made to a separate patch. They are not tightly coupled with the MC/CodeGen changes. A group of binary format focused people will be interested to review that part.

Sure, I will move that part to a different change.

[kzhuravl]

In D81780#2091213, @kzhuravl wrote:

Changes to AMDGPUUsage are WIP.

Since Sam is updating the docs with the overall target id concept, I think these docs are sufficient for this review.

[scott.linder]

llvm/docs/AMDGPUUsage.rst

657

Why do we enumerate ELFABIVERSION_* if they can have multiple actual values? It seems like the only other place we mention these is to say that they describe the version of their corresponding ELFOSABI_*. Could we just replace those places with the literal values that are possible for each ELFOSABI_*?

726

Are these shared between all ELFOSABI_*? Other places seem to also mention the EI_OSABI field when specifying where these values are legal.

778

Nit: I would prefer the value in parenthesis be written in hex to be consistent with the Value column.

llvm/include/llvm/BinaryFormat/ELF.h

718

Can you update these comments to explicitly state they are applicable to EI_ABIVERSION<2 ?

726

Same question as above; are these really only under the specified EI_OSABI and if so can that be reflected in AMDGPUUsage?

729

Is there a reason for this to be non-zero? Maybe it would make sense to have four values:

• 0b00: Not an applicable feature for the given MACH
• 0b01: Default
• 0b10: Off
• 0b11: On

But from my original reading of the proposal my understanding was we would instead use:

• 0b00: If applicable, Default. Otherwise, the only legal value for a non-applicable target feature.
• 0b01: Off
• 0b10: On

In effect the context of the ARCH tells you if you even need to consider the feature bits for a given feature, so differentiating the case isn't useful. I guess we don't save any bits this way though?

The original proposal also mentions "makes using a mask to check for a match easier as value & test will be 0 if exact match or matching against default", although I'm not actually clear what it means to say.

llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

136

I think I need some help to understand what case this intends to diagnose. Is the GlobalSTI a property of the module? Where is it derived from if the subtarget is a per-function concept?

llvm/lib/Target/AMDGPU/AMDGPUMachineModuleInfo.cpp

46

It seems like the condition/assertion here should be flipped. We should identify the metadata by the key, then assert it has the required merge behavior. Is it just inverted to avoid repeated string comparisons, and because we can be certain there won't be other uses of the merge behavior for AMDGPU IR?

53

Do we really want to have this "fallback"? It seems like we should just define the "target-id" metadata entry as required, and fail here instead.

I can't remember exactly, but my understanding is that the Target you get from MMI is essentially incorrect, and is only there for legacy purposes. We have had bugs in the past, some of which led us to the whole TargetID proposal in the first place, when we used the MMI instead of per-function Subtargets. Not AMDGPU, but see http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20150316/266041.html for an example.

I am worried that this behavior will just lead to more bugs. Is it here to avoid updating tests or something similar?

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

3764

Nit: Can this condition be inverted, i.e. the new case first.

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp

181

Why is TargetID ignored, but passed in by AMDGPUAsmParser::ParseDirectiveAMDGCNTarget for this case, and constructed in the same way?

432

Same question as above about the bit-pattern for the Default case; is there a need to differentiate the non-supported-feature case from the supported-and-Default case? If not, can we just change the bitpatterns of the three values and delete these bitwise-ORs?

[kzhuravl]

llvm/docs/AMDGPUUsage.rst

657

doc update in separate review.

726

doc update in separate review.

778

doc update in separate review.

llvm/include/llvm/BinaryFormat/ELF.h

726

yes.

729

discussed offline. docs have been updated to match this implementation.

llvm/lib/Target/AMDGPU/AMDGPUMachineModuleInfo.cpp

46

yes, avoiding string comparisons. also implementation of MergeTargetID implies there won't be other uses of the merge behavior.

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp

432

no, according to latest docs.

llvm/docs/AMDGPUUsage.rst

``e_ident[EI_OSABI]``      - ``ELFOSABI_NONE``
                                 - ``ELFOSABI_AMDGPU_MESA3D``
      ``e_ident[EI_ABIVERSION]`` - ``ELFABIVERSION_AMDGPU_HSA``
                                 - ``ELFABIVERSION_AMDGPU_PAL``
                                 - ``ELFABIVERSION_AMDGPU_MESA3D``
      ``e_type``                 - ``ET_REL``
                                 - ``ET_DYN``
      ``e_machine``              ``EM_AMDGPU``
      ``e_entry``                0
-     ``e_flags``                See :ref:`amdgpu-elf-header-e_flags-table`
+     ``e_flags``                See :ref:`amdgpu-elf-header-e_flags-table-01`
+                                and :ref:`amdgpu-elf-header-e_flags-table-2`
      ========================== ===============================
 
 ..
 
   .. table:: AMDGPU ELF Header Enumeration Values
      :name: amdgpu-elf-header-enumeration-values-table
 
-     =============================== =====
+     =============================== ======
      Name                            Value
-     =============================== =====
+     =============================== ======
      ``EM_AMDGPU``                   224
      ``ELFOSABI_NONE``               0
      ``ELFOSABI_AMDGPU_HSA``         64
      ``ELFOSABI_AMDGPU_PAL``         65
      ``ELFOSABI_AMDGPU_MESA3D``      66
-     ``ELFABIVERSION_AMDGPU_HSA``    1
+     ``ELFABIVERSION_AMDGPU_HSA``    1 or 2
      ``ELFABIVERSION_AMDGPU_PAL``    0
      ``ELFABIVERSION_AMDGPU_MESA3D`` 0
-     =============================== =====
+     =============================== ======
 
 ``e_ident[EI_CLASS]``
   The ELF class is:
 
   * ``ELFCLASS32`` for ``r600`` architecture.
 
   * ``ELFCLASS64`` for ``amdgcn`` architecture which only supports 64-bit
     process address space applications.
``e_type``
 
   The AMD HSA runtime loader requires a ``ET_DYN`` code object.
 
 ``e_machine``
   The value ``EM_AMDGPU`` is used for the machine for all processors supported
   by the ``r600`` and ``amdgcn`` architectures (see
   :ref:`amdgpu-processor-table`). The specific processor is specified in the
   ``EF_AMDGPU_MACH`` bit field of the ``e_flags`` (see
-  :ref:`amdgpu-elf-header-e_flags-table`).
+  :ref:`amdgpu-elf-header-e_flags-table-01` and
+  :ref:`amdgpu-elf-header-e_flags-table-2`).
 
 ``e_entry``
   The entry point is 0 as the entry points for individual kernels must be
   selected in order to invoke them through AQL packets.
 
 ``e_flags``
   The AMDGPU backend uses the following ELF header flags:
 
-  .. table:: AMDGPU ELF Header ``e_flags``
-     :name: amdgpu-elf-header-e_flags-table
+  .. table:: AMDGPU ELF Header ``e_flags`` (``EI_ABIVERSION=0`` and ``EI_ABIVERSION=1``)
+     :name: amdgpu-elf-header-e_flags-table-01
 
      ================================= ========== =============================
      Name                              Value      Description
      ================================= ========== =============================
      **AMDGPU Processor Flag**                    See :ref:`amdgpu-processor-table`.
      -------------------------------------------- -----------------------------
      ``EF_AMDGPU_MACH``                0x000000ff AMDGPU processor selection
                                                   mask for
``EF_AMDGPU_SRAM_ECC``            0x00000200 Indicates if the ``sram-ecc``
                                                   does not support the
                                                   ``sram-ecc`` target
                                                   feature then must
                                                   be 0.
                                                   See
                                                   :ref:`amdgpu-target-features`.
      ================================= ========== =============================
 
+  .. table:: AMDGPU ELF Header ``e_flags`` (``EI_ABIVERSION=2``)
+     :name: amdgpu-elf-header-e_flags-table-2
+
+     ================================= ========== ==========================================
+     Name                              Value      Description
+     ================================= ========== ==========================================
+     **AMDGPU Processor Flag**                    See :ref:`amdgpu-processor-table`.
+     -------------------------------------------- ------------------------------------------
+     ``EF_AMDGPU_MACH``                0x000000ff AMDGPU processor selection
+                                                  mask for
+                                                  ``EF_AMDGPU_MACH_xxx`` values
+                                                  defined in
+                                                  :ref:`amdgpu-ef-amdgpu-mach-table`.
+     ``EF_AMDGPU_FEATURE_XNACK``       0x00000300 XNACK selection mask for
+                                                  representing 3 values:
+                                                  ``EF_AMDGPU_FEATURE_XNACK_DEFAULT`` (1),
+                                                  ``EF_AMDGPU_FEATURE_XNACK_OFF`` (2),
+                                                  ``EF_AMDGPU_FEATURE_XNACK_ON`` (3).
+     ``EF_AMDGPU_FEATURE_SRAMECC``     0x00000c00 SRAMECC selection mask for
+                                                  representing 3 values:
+                                                  ``EF_AMDGPU_FEATURE_SRAMECC_DEFAULT`` (1),
+                                                  ``EF_AMDGPU_FEATURE_SRAMECC_OFF`` (2),
+                                                  ``EF_AMDGPU_FEATURE_SRAMECC_ON`` (3).
+     ================================= ========== ==========================================
+
   .. table:: AMDGPU ``EF_AMDGPU_MACH`` Values
      :name: amdgpu-ef-amdgpu-mach-table
 
      ================================= ========== =============================
      Name                              Value      Description (see
                                                   :ref:`amdgpu-processor-table`)
      ================================= ========== =============================
      ``EF_AMDGPU_MACH_NONE``           0x000      *not specified*

llvm/include/llvm/BinaryFormat/ELF.h

enum : unsigned {
   // Reserved for AMDGCN-based processors.
   EF_AMDGPU_MACH_AMDGCN_RESERVED0 = 0x027,
   EF_AMDGPU_MACH_AMDGCN_RESERVED1 = 0x032,
 
   // First/last AMDGCN-based processors.
   EF_AMDGPU_MACH_AMDGCN_FIRST = EF_AMDGPU_MACH_AMDGCN_GFX600,
   EF_AMDGPU_MACH_AMDGCN_LAST = EF_AMDGPU_MACH_AMDGCN_GFX1012,
 
   // Indicates if the "xnack" target feature is enabled for all code contained
   // in the object.
   EF_AMDGPU_XNACK = 0x100,
   // Indicates if the "sram-ecc" target feature is enabled for all code
   // contained in the object.
   EF_AMDGPU_SRAM_ECC = 0x200,
+
+  // XNACK selection mask for EF_AMDGPU_FEATURE_XNACK_* values. Applicable
+  // to EI_OSABI=ELFOSABI_AMDGPU_HSA and EI_ABIVERSION=2.
+  EF_AMDGPU_FEATURE_XNACK = 0x300,
+  // XNACK is any/default.
+  EF_AMDGPU_FEATURE_XNACK_DEFAULT=0x100,
+  // XNACK is off.
+  EF_AMDGPU_FEATURE_XNACK_OFF=0x200,
+  // XNACK is on.
+  EF_AMDGPU_FEATURE_XNACK_ON=0x300,
+
+  // SRAMECC selection mask for EF_AMDGPU_FEATURE_SRAMECC_* values. Applicable
+  // to EI_OSABI=ELFOSABI_AMDGPU_HSA and EI_ABIVERSION=2.
+  EF_AMDGPU_FEATURE_SRAMECC = 0xc00,
+  // SRAMECC is any/default.
+  EF_AMDGPU_FEATURE_SRAMECC_DEFAULT = 0x400,
+  // SRAMECC is off.
+  EF_AMDGPU_FEATURE_SRAMECC_OFF = 0x800,
+  // SRAMECC is on.
+  EF_AMDGPU_FEATURE_SRAMECC_ON = 0xc00,
 };
 
 // ELF Relocation types for AMDGPU
 enum {
 #include "ELFRelocs/AMDGPU.def"
 };
 
 // ELF Relocation types for BPF

llvm/lib/ObjectYAML/ELFYAML.cpp

case ELF::EM_AMDGPU:
     BCaseMask(EF_AMDGPU_MACH_AMDGCN_GFX902, EF_AMDGPU_MACH);
     BCaseMask(EF_AMDGPU_MACH_AMDGCN_GFX904, EF_AMDGPU_MACH);
     BCaseMask(EF_AMDGPU_MACH_AMDGCN_GFX906, EF_AMDGPU_MACH);
     BCaseMask(EF_AMDGPU_MACH_AMDGCN_GFX908, EF_AMDGPU_MACH);
     BCaseMask(EF_AMDGPU_MACH_AMDGCN_GFX909, EF_AMDGPU_MACH);
     BCaseMask(EF_AMDGPU_MACH_AMDGCN_GFX1010, EF_AMDGPU_MACH);
     BCaseMask(EF_AMDGPU_MACH_AMDGCN_GFX1011, EF_AMDGPU_MACH);
     BCaseMask(EF_AMDGPU_MACH_AMDGCN_GFX1012, EF_AMDGPU_MACH);
+    switch (Object->Header.ABIVersion) {
+    case 0:
+    case 1:
       BCase(EF_AMDGPU_XNACK);
       BCase(EF_AMDGPU_SRAM_ECC);
       break;
+    case 2:
+      BCaseMask(EF_AMDGPU_FEATURE_XNACK_DEFAULT, EF_AMDGPU_FEATURE_XNACK);
+      BCaseMask(EF_AMDGPU_FEATURE_XNACK_OFF, EF_AMDGPU_FEATURE_XNACK);
+      BCaseMask(EF_AMDGPU_FEATURE_XNACK_ON, EF_AMDGPU_FEATURE_XNACK);
+      BCaseMask(EF_AMDGPU_FEATURE_SRAMECC_DEFAULT, EF_AMDGPU_FEATURE_SRAMECC);
+      BCaseMask(EF_AMDGPU_FEATURE_SRAMECC_OFF, EF_AMDGPU_FEATURE_SRAMECC);
+      BCaseMask(EF_AMDGPU_FEATURE_SRAMECC_ON, EF_AMDGPU_FEATURE_SRAMECC);
+      break;
+    default:
+      llvm_unreachable("Unsupported ABI Version");
+    }
+    break;
   case ELF::EM_X86_64:
     break;
   default:
     llvm_unreachable("Unsupported architecture");
   }
 #undef BCase
 #undef BCaseMask
 }

llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

 /// code.  When passed an MCAsmStreamer it prints assembly and when passed
 /// an MCObjectStreamer it outputs binary code.
 //
 //===----------------------------------------------------------------------===//
 //
 
 #include "AMDGPUAsmPrinter.h"
 #include "AMDGPU.h"
+#include "AMDGPUMachineModuleInfo.h"
 #include "AMDGPUSubtarget.h"
 #include "AMDGPUTargetMachine.h"
 #include "MCTargetDesc/AMDGPUInstPrinter.h"
 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
 #include "MCTargetDesc/AMDGPUTargetStreamer.h"
 #include "R600AsmPrinter.h"
 #include "R600Defines.h"
 #include "R600MachineFunctionInfo.h"

 
 AMDGPUTargetStreamer* AMDGPUAsmPrinter::getTargetStreamer() const {
   if (!OutStreamer)
     return nullptr;
   return static_cast<AMDGPUTargetStreamer*>(OutStreamer->getTargetStreamer());
 }
 
 void AMDGPUAsmPrinter::emitStartOfAsmFile(Module &M) {
-  if (IsaInfo::hasCodeObjectV3(getGlobalSTI())) {
-    std::string ExpectedTarget;
-    raw_string_ostream ExpectedTargetOS(ExpectedTarget);
-    IsaInfo::streamIsaVersion(getGlobalSTI(), ExpectedTargetOS);
-
-    getTargetStreamer()->EmitDirectiveAMDGCNTarget(ExpectedTarget);
+  StringRef TargetID =
+      MMI->getObjFileInfo<AMDGPUMachineModuleInfo>().getTargetID();
+  if (enableNewTargetID()) {
+    if (!isSubtargetInfoEquivalentToTargetID(getGlobalSTI(), TargetID)) {
+      report_fatal_error("Subtarget info does not match TargetID");
+    }
   }
+  getTargetStreamer()->EmitDirectiveAMDGCNTarget(*getGlobalSTI(), TargetID);
 
   if (TM.getTargetTriple().getOS() != Triple::AMDHSA &&
       TM.getTargetTriple().getOS() != Triple::AMDPAL)
     return;
 
   if (TM.getTargetTriple().getOS() == Triple::AMDHSA)
-    HSAMetadataStream->begin(M);
+    HSAMetadataStream->begin(M, TargetID);
 
   if (TM.getTargetTriple().getOS() == Triple::AMDPAL)
     getTargetStreamer()->getPALMetadata()->readFromIR(M);
 
   if (IsaInfo::hasCodeObjectV3(getGlobalSTI()))
     return;
 
   // HSA emits NT_AMDGPU_HSA_CODE_OBJECT_VERSION for code objects v2.

llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.h

 namespace HSAMD {
 
 class MetadataStreamer {
 public:
   virtual ~MetadataStreamer(){};
 
   virtual bool emitTo(AMDGPUTargetStreamer &TargetStreamer) = 0;
 
-  virtual void begin(const Module &Mod) = 0;
+  virtual void begin(const Module &Mod, StringRef TargetID) = 0;
 
   virtual void end() = 0;
 
   virtual void emitKernel(const MachineFunction &MF,
                           const SIProgramInfo &ProgramInfo) = 0;
 };
 
 class MetadataStreamerV3 final : public MetadataStreamer {
private:
 
   msgpack::ArrayDocNode getWorkGroupDimensions(MDNode *Node) const;
 
   msgpack::MapDocNode getHSAKernelProps(const MachineFunction &MF,
                                         const SIProgramInfo &ProgramInfo) const;
 
   void emitVersion();
 
+  void emitTargetID(StringRef TargetID);
+
   void emitPrintf(const Module &Mod);
 
   void emitKernelLanguage(const Function &Func, msgpack::MapDocNode Kern);
 
   void emitKernelAttrs(const Function &Func, msgpack::MapDocNode Kern);
 
   void emitKernelArgs(const Function &Func, msgpack::MapDocNode Kern);
 
private:
   }
 
 public:
   MetadataStreamerV3() = default;
   ~MetadataStreamerV3() = default;
 
   bool emitTo(AMDGPUTargetStreamer &TargetStreamer) override;
 
-  void begin(const Module &Mod) override;
+  void begin(const Module &Mod, StringRef TargetID) override;
 
   void end() override;
 
   void emitKernel(const MachineFunction &MF,
                   const SIProgramInfo &ProgramInfo) override;
 };
 
 class MetadataStreamerV2 final : public MetadataStreamer {
private:
   }
 
 public:
   MetadataStreamerV2() = default;
   ~MetadataStreamerV2() = default;
 
   bool emitTo(AMDGPUTargetStreamer &TargetStreamer) override;
 
-  void begin(const Module &Mod) override;
+  void begin(const Module &Mod, StringRef TargetID) override;
 
   void end() override;
 
   void emitKernel(const MachineFunction &MF,
                   const SIProgramInfo &ProgramInfo) override;
 };
 
 } // end namespace HSAMD
 } // end namespace AMDGPU
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUHSAMETADATASTREAMER_H

llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp

void MetadataStreamerV2::emitHiddenKernelArgs(const Function &Func) {
   if (HiddenArgNumBytes >= 56)
     emitKernelArg(DL, Int8PtrTy, ValueKind::HiddenMultiGridSyncArg);
 }
 
 bool MetadataStreamerV2::emitTo(AMDGPUTargetStreamer &TargetStreamer) {
   return TargetStreamer.EmitHSAMetadata(getHSAMetadata());
 }
 
-void MetadataStreamerV2::begin(const Module &Mod) {
+void MetadataStreamerV2::begin(const Module &Mod, StringRef TargetID) {
   emitVersion();
   emitPrintf(Mod);
 }
 
 void MetadataStreamerV2::end() {
   std::string HSAMetadataString;
   if (toString(HSAMetadata, HSAMetadataString))
     return;

 
 void MetadataStreamerV3::emitVersion() {
   auto Version = HSAMetadataDoc->getArrayNode();
   Version.push_back(Version.getDocument()->getNode(VersionMajor));
   Version.push_back(Version.getDocument()->getNode(VersionMinor));
   getRootMetadata("amdhsa.version") = Version;
 }
 
+void MetadataStreamerV3::emitTargetID(StringRef TargetID) {
+  getRootMetadata("amdhsa.target") =
+      HSAMetadataDoc->getNode(TargetID, /*Copy=*/true);
+}
+
 void MetadataStreamerV3::emitPrintf(const Module &Mod) {
   auto Node = Mod.getNamedMetadata("llvm.printf.fmts");
   if (!Node)
     return;
 
   auto Printf = HSAMetadataDoc->getArrayNode();
   for (auto Op : Node->operands())
     if (Op->getNumOperands())
MetadataStreamerV3::getHSAKernelProps(const MachineFunction &MF,
 
   return Kern;
 }
 
 bool MetadataStreamerV3::emitTo(AMDGPUTargetStreamer &TargetStreamer) {
   return TargetStreamer.EmitHSAMetadata(*HSAMetadataDoc, true);
 }
 
-void MetadataStreamerV3::begin(const Module &Mod) {
+void MetadataStreamerV3::begin(const Module &Mod, StringRef TargetID) {
   emitVersion();
+  if (enableNewTargetID())
+    emitTargetID(TargetID);
   emitPrintf(Mod);
   getRootMetadata("amdhsa.kernels") = HSAMetadataDoc->getArrayNode();
 }
 
 void MetadataStreamerV3::end() {
   std::string HSAMetadataString;
   raw_string_ostream StrOS(HSAMetadataString);
   HSAMetadataDoc->toYAML(StrOS);

llvm/lib/Target/AMDGPU/AMDGPUMachineModuleInfo.h

private:
   SyncScope::ID AgentOneAddressSpaceSSID;
   /// Workgroup synchronization scope ID (single address space).
   SyncScope::ID WorkgroupOneAddressSpaceSSID;
   /// Wavefront synchronization scope ID (single address space).
   SyncScope::ID WavefrontOneAddressSpaceSSID;
   /// Single thread synchronization scope ID (single address space).
   SyncScope::ID SingleThreadOneAddressSpaceSSID;
 
+  // Target identification string syntax can be found here:
+  //   https://llvm.org/docs/AMDGPUUsage.html#code-object-target-identification
+
+  /// Target identification string.
+  std::string TargetID;
+
   /// In AMDGPU target synchronization scopes are inclusive, meaning a
   /// larger synchronization scope is inclusive of a smaller synchronization
   /// scope.
   ///
   /// \returns \p SSID's inclusion ordering, or "None" if \p SSID is not
   /// supported by the AMDGPU target.
   Optional<uint8_t> getSyncScopeInclusionOrdering(SyncScope::ID SSID) const {
     if (SSID == SyncScope::SingleThread ||
if (!AIO || !BIO)
       return None;
 
     bool IsAOneAddressSpace = isOneAddressSpace(A);
     bool IsBOneAddressSpace = isOneAddressSpace(B);
 
     return AIO.getValue() >= BIO.getValue() &&
         (IsAOneAddressSpace == IsBOneAddressSpace || !IsAOneAddressSpace);
   }
+
+  /// \returns Target identification string.
+  StringRef getTargetID() const {
+    return TargetID;
+  }
 };
 
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINEMODULEINFO_H

llvm/lib/Target/AMDGPU/AMDGPUMachineModuleInfo.cpp

 //===--- AMDGPUMachineModuleInfo.cpp ----------------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 /// \file
 /// AMDGPU Machine Module Info.
 ///
 //
 //===----------------------------------------------------------------------===//
 
 #include "AMDGPUMachineModuleInfo.h"
 #include "llvm/IR/Module.h"
+#include "llvm/Target/TargetMachine.h"
+#include "llvm/Support/TargetParser.h"
 
 namespace llvm {
 
 AMDGPUMachineModuleInfo::AMDGPUMachineModuleInfo(const MachineModuleInfo &MMI)
     : MachineModuleInfoELF(MMI) {
   LLVMContext &CTX = MMI.getModule()->getContext();
   AgentSSID = CTX.getOrInsertSyncScopeID("agent");
   WorkgroupSSID = CTX.getOrInsertSyncScopeID("workgroup");
   WavefrontSSID = CTX.getOrInsertSyncScopeID("wavefront");
   SystemOneAddressSpaceSSID =
       CTX.getOrInsertSyncScopeID("one-as");
   AgentOneAddressSpaceSSID =
       CTX.getOrInsertSyncScopeID("agent-one-as");
   WorkgroupOneAddressSpaceSSID =
       CTX.getOrInsertSyncScopeID("workgroup-one-as");
   WavefrontOneAddressSpaceSSID =
       CTX.getOrInsertSyncScopeID("wavefront-one-as");
   SingleThreadOneAddressSpaceSSID =
       CTX.getOrInsertSyncScopeID("singlethread-one-as");
+
+  if (MMI.getTarget().getTargetTriple().getArch() != Triple::amdgcn) {
+    return;
+  }
+
+  SmallVector<Module::ModuleFlagEntry, 8> ModuleFlags;
+  MMI.getModule()->getModuleFlagsMetadata(ModuleFlags);
+  for (const auto &MFE : ModuleFlags) {
+    if (MFE.Behavior != Module::MergeTargetId) {
+      continue;
+    }
+
+    assert(MFE.Key->getString().equals("target-id"));
+    TargetID = cast<MDString>(MFE.Val)->getString().str();
+  }
+  if (TargetID.empty()) {
+    auto TargetTriple = MMI.getTarget().getTargetTriple();
+    auto CPU = MMI.getTarget().getTargetCPU();
+    auto Version = AMDGPU::getIsaVersion(CPU);
+
+    raw_string_ostream ConstructedTargetIDOStr(TargetID);
+    ConstructedTargetIDOStr << TargetTriple.getArchName() << '-'
+                            << TargetTriple.getVendorName() << '-'
+                            << TargetTriple.getOSName() << '-'
+                            << TargetTriple.getEnvironmentName() << '-';
+    if (Version.Major >= 9) {
+      ConstructedTargetIDOStr << CPU;
+    } else {
+      ConstructedTargetIDOStr << "gfx" << Version.Major << Version.Minor
+                              << Version.Stepping;
+    }
+    ConstructedTargetIDOStr.flush();
+  }
 }
 
 } // end namespace llvm

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

bool AMDGPUAsmParser::ParseDirectiveMajorMinor(uint32_t &Major,
 
   return false;
 }
 
 bool AMDGPUAsmParser::ParseDirectiveAMDGCNTarget() {
   if (getSTI().getTargetTriple().getArch() != Triple::amdgcn)
     return TokError("directive only supported for amdgcn architecture");
 
-  std::string Target;
+  std::string TargetID;
 
   SMLoc TargetStart = getTok().getLoc();
-  if (getParser().parseEscapedString(Target))
+  if (getParser().parseEscapedString(TargetID))
     return true;
   SMRange TargetRange = SMRange(TargetStart, getTok().getLoc());
 
-  std::string ExpectedTarget;
-  raw_string_ostream ExpectedTargetOS(ExpectedTarget);
-  IsaInfo::streamIsaVersion(&getSTI(), ExpectedTargetOS);
+  if (!enableNewTargetID()) {
+    std::string ExpectedTargetIDStr;
+    raw_string_ostream ExpectedTargetIDOStr(ExpectedTargetIDStr);
+    IsaInfo::streamIsaVersion(&getSTI(), ExpectedTargetIDOStr);
 
-  if (Target != ExpectedTargetOS.str())
+    if (TargetID != ExpectedTargetIDOStr.str())
       return getParser().Error(TargetRange.Start, "target must match options",
                                TargetRange);
+  } else {
+    if (!isSubtargetInfoEquivalentToTargetID(&getSTI(), TargetID))
+      return getParser().Error(TargetRange.Start, "target must match options",
+                               TargetRange);
+  }
 
-  getTargetStreamer().EmitDirectiveAMDGCNTarget(Target);
+  getTargetStreamer().EmitDirectiveAMDGCNTarget(getSTI(), TargetID);
   return false;
 }
 
 bool AMDGPUAsmParser::OutOfRangeError(SMRange Range) {
   return getParser().Error(Range.Start, "value out of range", Range);
 }
 
 bool AMDGPUAsmParser::calculateGPRBlocks(

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp

 };
 
 } // end anonymous namespace
 
 MCAsmBackend *llvm::createAMDGPUAsmBackend(const Target &T,
                                            const MCSubtargetInfo &STI,
                                            const MCRegisterInfo &MRI,
                                            const MCTargetOptions &Options) {
+  uint8_t ABIVersion = 0;
+  if (IsaInfo::hasCodeObjectV3(&STI)) {
+    ABIVersion = enableNewTargetID() ? 2 : 1;
+  }
+
   // Use 64-bit ELF for amdgcn
-  return new ELFAMDGPUAsmBackend(T, STI.getTargetTriple(),
-                                 IsaInfo::hasCodeObjectV3(&STI) ? 1 : 0);
+  return new ELFAMDGPUAsmBackend(T, STI.getTargetTriple(), ABIVersion);
 }

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h

 protected:
   MCContext &getContext() const { return Streamer.getContext(); }
 
 public:
   AMDGPUTargetStreamer(MCStreamer &S) : MCTargetStreamer(S) {}
 
   AMDGPUPALMetadata *getPALMetadata() { return &PALMetadata; }
 
-  virtual void EmitDirectiveAMDGCNTarget(StringRef Target) = 0;
+  virtual void EmitDirectiveAMDGCNTarget(const MCSubtargetInfo &STI,
+                                         StringRef TargetID = "") = 0;
 
   virtual void EmitDirectiveHSACodeObjectVersion(uint32_t Major,
                                                  uint32_t Minor) = 0;
 
   virtual void EmitDirectiveHSACodeObjectISA(uint32_t Major, uint32_t Minor,
                                              uint32_t Stepping,
                                              StringRef VendorName,
                                              StringRef ArchName) = 0;

 
 class AMDGPUTargetAsmStreamer final : public AMDGPUTargetStreamer {
   formatted_raw_ostream &OS;
 public:
   AMDGPUTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS);
 
   void finish() override;
 
-  void EmitDirectiveAMDGCNTarget(StringRef Target) override;
+  void EmitDirectiveAMDGCNTarget(const MCSubtargetInfo &STI,
+                                 StringRef TargetID = "") override;
 
   void EmitDirectiveHSACodeObjectVersion(uint32_t Major,
                                          uint32_t Minor) override;
 
   void EmitDirectiveHSACodeObjectISA(uint32_t Major, uint32_t Minor,
                                      uint32_t Stepping, StringRef VendorName,
                                      StringRef ArchName) override;
 
void EmitAmdhsaKernelDescriptor(
       const MCSubtargetInfo &STI, StringRef KernelName,
       const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR,
       uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr,
       bool ReserveXNACK) override;
 };
 
 class AMDGPUTargetELFStreamer final : public AMDGPUTargetStreamer {
   MCStreamer &Streamer;
-  Triple::OSType Os;
+  const MCSubtargetInfo &STI;
 
   void EmitNote(StringRef Name, const MCExpr *DescSize, unsigned NoteType,
                 function_ref<void(MCELFStreamer &)> EmitDesc);
 
 public:
   AMDGPUTargetELFStreamer(MCStreamer &S, const MCSubtargetInfo &STI);
 
   MCELFStreamer &getStreamer();
 
   void finish() override;
 
-  void EmitDirectiveAMDGCNTarget(StringRef Target) override;
+  void EmitDirectiveAMDGCNTarget(const MCSubtargetInfo &STI,
+                                 StringRef TargetID = "") override;
 
   void EmitDirectiveHSACodeObjectVersion(uint32_t Major,
                                          uint32_t Minor) override;
 
   void EmitDirectiveHSACodeObjectISA(uint32_t Major, uint32_t Minor,
                                      uint32_t Stepping, StringRef VendorName,
                                      StringRef ArchName) override;
 

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp

 // A hook for emitting stuff at the end.
 // We use it for emitting the accumulated PAL metadata as directives.
 void AMDGPUTargetAsmStreamer::finish() {
   std::string S;
   getPALMetadata()->toString(S);
   OS << S;
 }
 
-void AMDGPUTargetAsmStreamer::EmitDirectiveAMDGCNTarget(StringRef Target) {
-  OS << "\t.amdgcn_target \"" << Target << "\"\n";
+void AMDGPUTargetAsmStreamer::EmitDirectiveAMDGCNTarget(
+    const MCSubtargetInfo &STI, StringRef TargetID) {
+  if (!IsaInfo::hasCodeObjectV3(&STI)) {
+    // V2 does not have TargetID concept.
+    return;
+  }
+  if (!enableNewTargetID()) {
+    // V3 + Original TargetID.
+    std::string ConstructedTargetIDStr;
+    raw_string_ostream ConstructedTargetIDOStr(ConstructedTargetIDStr);
+    IsaInfo::streamIsaVersion(&STI, ConstructedTargetIDOStr);
+    OS << "\t.amdgcn_target \"" << ConstructedTargetIDStr << "\"\n";
+    return;
+  }
+
+  // V3 + New TargetID.
+  OS << "\t.amdgcn_target \"" << TargetID << "\"\n";
 }
 
 void AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectVersion(
     uint32_t Major, uint32_t Minor) {
   OS << "\t.hsa_code_object_version " <<
         Twine(Major) << "," << Twine(Minor) << '\n';
 }
 

 }
 
 //===----------------------------------------------------------------------===//
 // AMDGPUTargetELFStreamer
 //===----------------------------------------------------------------------===//
 
 AMDGPUTargetELFStreamer::AMDGPUTargetELFStreamer(MCStreamer &S,
                                                  const MCSubtargetInfo &STI)
-    : AMDGPUTargetStreamer(S), Streamer(S), Os(STI.getTargetTriple().getOS()) {
+    : AMDGPUTargetStreamer(S), Streamer(S), STI(STI) {
   MCAssembler &MCA = getStreamer().getAssembler();
   unsigned EFlags = MCA.getELFHeaderEFlags();
 
   EFlags &= ~ELF::EF_AMDGPU_MACH;
   EFlags |= getElfMach(STI.getCPU());
 
+  if (!enableNewTargetID()) {
+    // V2, V3 + Original TargetID.
     EFlags &= ~ELF::EF_AMDGPU_XNACK;
     if (AMDGPU::hasXNACK(STI))
       EFlags |= ELF::EF_AMDGPU_XNACK;
 
     EFlags &= ~ELF::EF_AMDGPU_SRAM_ECC;
     if (AMDGPU::hasSRAMECC(STI))
       EFlags |= ELF::EF_AMDGPU_SRAM_ECC;
+  } else {
+    // V3 + New TargetID.
+    EFlags &= ~ELF::EF_AMDGPU_FEATURE_XNACK;
+    EFlags |= ELF::EF_AMDGPU_FEATURE_XNACK_DEFAULT;
+
+    EFlags &= ~ELF::EF_AMDGPU_FEATURE_SRAMECC;
+    EFlags |= ELF::EF_AMDGPU_FEATURE_SRAMECC_DEFAULT;
+  }
 
   MCA.setELFHeaderEFlags(EFlags);
 }
 
 MCELFStreamer &AMDGPUTargetELFStreamer::getStreamer() {
   return static_cast<MCELFStreamer &>(Streamer);
 }
 
void AMDGPUTargetELFStreamer::EmitNote(
   auto &S = getStreamer();
   auto &Context = S.getContext();
 
   auto NameSZ = Name.size() + 1;
 
   unsigned NoteFlags = 0;
   // TODO Apparently, this is currently needed for OpenCL as mentioned in
   // https://reviews.llvm.org/D74995
-  if (Os == Triple::AMDHSA)
+  if (STI.getTargetTriple().getOS() == Triple::AMDHSA)
     NoteFlags = ELF::SHF_ALLOC;
 
   S.PushSection();
   S.SwitchSection(
       Context.getELFSection(ElfNote::SectionName, ELF::SHT_NOTE, NoteFlags));
   S.emitInt32(NameSZ);                                        // namesz
   S.emitValue(DescSZ, 4);                                     // descz
   S.emitInt32(NoteType);                                      // type
   S.emitBytes(Name);                                          // name
   S.emitValueToAlignment(4, 0, 1, 0);                         // padding 0
   EmitDesc(S);                                                // desc
   S.emitValueToAlignment(4, 0, 1, 0);                         // padding 0
   S.PopSection();
 }
 
-void AMDGPUTargetELFStreamer::EmitDirectiveAMDGCNTarget(StringRef Target) {}
+void AMDGPUTargetELFStreamer::EmitDirectiveAMDGCNTarget(
+    const MCSubtargetInfo &STI, StringRef TargetID) {
+  if (!IsaInfo::hasCodeObjectV3(&STI)) {
+    // V2 is setup in the constructor.
+    return;
+  }
+  if (!enableNewTargetID()) {
+    // V3 + Original TargetID is setup in the constructor.
+    return;
+  }
+
+  MCAssembler &MCA = getStreamer().getAssembler();
+  unsigned EFlags = MCA.getELFHeaderEFlags();
+
+  // V3 + New TargetID (default is already setup in the constructor).
+  if (auto XNACK = getXnackFromTargetID(TargetID)) {
+    EFlags &= ~ELF::EF_AMDGPU_FEATURE_XNACK;
+    EFlags |= XNACK.getValue() ? ELF::EF_AMDGPU_FEATURE_XNACK_ON
+                               : ELF::EF_AMDGPU_FEATURE_XNACK_OFF;
+  }
+  if (auto SRAMECC = getSramEccFromTargetID(TargetID)) {
+    EFlags &= ~ELF::EF_AMDGPU_FEATURE_SRAMECC;
+    EFlags |= SRAMECC.getValue() ? ELF::EF_AMDGPU_FEATURE_SRAMECC_ON
+                                 : ELF::EF_AMDGPU_FEATURE_SRAMECC_OFF;
+  }
+
+  MCA.setELFHeaderEFlags(EFlags);
+}
 
 void AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectVersion(
     uint32_t Major, uint32_t Minor) {
 
   EmitNote(ElfNote::NoteNameV2, MCConstantExpr::create(8, getContext()),
            ElfNote::NT_AMDGPU_HSA_CODE_OBJECT_VERSION, [&](MCELFStreamer &OS) {
              OS.emitInt32(Major);
              OS.emitInt32(Minor);

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h

 class MCRegisterClass;
 class MCRegisterInfo;
 class MCSubtargetInfo;
 class StringRef;
 class Triple;
 
 namespace AMDGPU {
 
+/// \returns True if new target identification string is enabled, false
+/// otherwise.
+bool enableNewTargetID();
+
+/// \returns None for "default", false for "off", true for "on".
+Optional<bool> getFeatureFromTargetID(StringRef TargetID, StringRef Feature);
+
+/// \returns None for "default", false for "off", true for "on".
+Optional<bool> getXnackFromTargetID(StringRef TargetID);
+
+/// \returns None for "default", false for "off", true for "on".
+Optional<bool> getSramEccFromTargetID(StringRef TargetID);
+
+/// \returns True if \p STI is equivalent to \p TargetID, false otherwise.
+bool isSubtargetInfoEquivalentToTargetID(const MCSubtargetInfo *STI,
+                                         StringRef TargetID);
+
 struct GcnBufferFormatInfo {
   unsigned Format;
   unsigned BitsPerComp;
   unsigned NumComponents;
   unsigned NumFormat;
   unsigned DataFormat;
 };
 

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCInstrDesc.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSectionELF.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/MC/SubtargetFeature.h"
 #include "llvm/Support/Casting.h"
+#include "llvm/Support/CommandLine.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/MathExtras.h"
 #include <algorithm>
 #include <cassert>
 #include <cstdint>
 #include <cstring>
 #include <utility>
 
 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
 
 #define GET_INSTRINFO_NAMED_OPS
 #define GET_INSTRMAP_INFO
 #include "AMDGPUGenInstrInfo.inc"
 #undef GET_INSTRMAP_INFO
 #undef GET_INSTRINFO_NAMED_OPS
 
+static llvm::cl::opt<bool> EnableNewTargetID(
+  "amdgcn-new-target-id",
+  llvm::cl::desc("Use New Target ID"),
+  llvm::cl::init(false));
+
 namespace {
 
 /// \returns Bit mask for given bit \p Shift and bit \p Width.
 unsigned getBitMask(unsigned Shift, unsigned Width) {
   return ((1 << Width) - 1) << Shift;
 }
 
 /// Packs \p Src into \p Dst for given bit \p Shift and bit \p Width.

 unsigned getVmcntBitWidthHi() { return 2; }
 
 } // end namespace anonymous
 
 namespace llvm {
 
 namespace AMDGPU {
 
+bool enableNewTargetID() {
+  return EnableNewTargetID;
+}
+
+Optional<bool> getFeatureFromTargetID(StringRef TargetID, StringRef Feature) {
+  SmallVector<StringRef, 3> TargetIDSplit;
+  TargetID.split(TargetIDSplit, ':');
+
+  Optional<bool> FeatureStatus;
+  for (const auto &FeatureString : TargetIDSplit) {
+    if (FeatureString.startswith(Feature)) {
+      if (FeatureString.endswith("+")) {
+        FeatureStatus = true;
+      } else if (FeatureString.endswith("-")) {
+        FeatureStatus = false;
+      } else {
+        llvm_unreachable("Malformed feature string");
+      }
+    }
+  }
+  return FeatureStatus;
+}
+
+Optional<bool> getXnackFromTargetID(StringRef TargetID) {
+  return getFeatureFromTargetID(TargetID, "xnack");
+}
+
+Optional<bool> getSramEccFromTargetID(StringRef TargetID) {
+  return getFeatureFromTargetID(TargetID, "sramecc");
+}
+
+bool isSubtargetInfoEquivalentToTargetID(const MCSubtargetInfo *STI,
+                                         StringRef TargetID) {
+  auto TargetTriple = STI->getTargetTriple();
+  auto CPU = STI->getCPU();
+  auto Version = AMDGPU::getIsaVersion(CPU);
+
+  std::string ConstructedTargetIDStr;
+  raw_string_ostream ConstructedTargetIDOStr(ConstructedTargetIDStr);
+  ConstructedTargetIDOStr << TargetTriple.getArchName() << '-'
+                          << TargetTriple.getVendorName() << '-'
+                          << TargetTriple.getOSName() << '-'
+                          << TargetTriple.getEnvironmentName() << '-';
+  if (Version.Major >= 9) {
+    ConstructedTargetIDOStr << CPU;
+  } else {
+    ConstructedTargetIDOStr << "gfx" << Version.Major << Version.Minor
+                            << Version.Stepping;
+  }
+  ConstructedTargetIDOStr.flush();
+
+  if (!TargetID.startswith(ConstructedTargetIDStr)) {
+    return false;
+  }
+  if (auto XNACK = getXnackFromTargetID(TargetID)) {
+    if (XNACK.getValue() != hasXNACK(*STI)) {
+      return false;
+    }
+  }
+  if (auto SRAMECC = getSramEccFromTargetID(TargetID)) {
+    if (SRAMECC.getValue() != hasSRAMECC(*STI)) {
+      return false;
+    }
+  }
+  return true;
+}
+
 #define GET_MIMGBaseOpcodesTable_IMPL
 #define GET_MIMGDimInfoTable_IMPL
 #define GET_MIMGInfoTable_IMPL
 #define GET_MIMGLZMappingTable_IMPL
 #define GET_MIMGMIPMappingTable_IMPL
 #include "AMDGPUGenSearchableTables.inc"
 
 int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,

llvm/test/CodeGen/AMDGPU/tid-incompatible-sti-1.ll

+; RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdgcn-new-target-id < %s 2>&1 | FileCheck %s
+
+; CHECK: Subtarget info does not match TargetID
+
+define amdgpu_kernel void @empty() {
+entry:
+  ret void
+}
+
+!0 = !{ i32 8, !"target-id", !"amdgcn-amd-amdhsa--gfx803" }
+!llvm.module.flags = !{ !0 }

llvm/test/CodeGen/AMDGPU/tid-incompatible-sti-2.ll

+; RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdgcn-new-target-id < %s 2>&1 | FileCheck %s
+
+; CHECK: Subtarget info does not match TargetID
+
+define amdgpu_kernel void @empty() {
+entry:
+  ret void
+}
+
+!0 = !{ i32 8, !"target-id", !"amdgcn-amd-amdhsa--gfx900:xnack+:sramecc+" }
+!llvm.module.flags = !{ !0 }

llvm/test/CodeGen/AMDGPU/tid-none.ll

+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdgcn-new-target-id < %s | FileCheck --check-prefixes=ASM %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdgcn-new-target-id -filetype=obj < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=ELF %s
+
+; ASM: .amdgcn_target "amdgcn-amd-amdhsa--gfx900"
+; ASM: amdhsa.target: amdgcn-amd-amdhsa--gfx900
+; ELF: Flags [ (0x52C)
+; ELF:   EF_AMDGPU_FEATURE_SRAMECC_DEFAULT (0x400)
+; ELF:   EF_AMDGPU_FEATURE_XNACK_DEFAULT (0x100)
+; ELF:   EF_AMDGPU_MACH_AMDGCN_GFX900 (0x2C)
+; ELF: ]
+
+define amdgpu_kernel void @empty() {
+entry:
+  ret void
+}

llvm/test/CodeGen/AMDGPU/tid-xnack-default-sramecc-default.ll

+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdgcn-new-target-id < %s | FileCheck --check-prefixes=ASM %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdgcn-new-target-id -filetype=obj < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=ELF %s
+
+; ASM: .amdgcn_target "amdgcn-amd-amdhsa--gfx900"
+; ASM: amdhsa.target: amdgcn-amd-amdhsa--gfx900
+; ELF: Flags [ (0x52C)
+; ELF:   EF_AMDGPU_FEATURE_SRAMECC_DEFAULT (0x400)
+; ELF:   EF_AMDGPU_FEATURE_XNACK_DEFAULT (0x100)
+; ELF:   EF_AMDGPU_MACH_AMDGCN_GFX900 (0x2C)
+; ELF: ]
+
+define amdgpu_kernel void @empty() {
+entry:
+  ret void
+}
+
+!0 = !{ i32 8, !"target-id", !"amdgcn-amd-amdhsa--gfx900" }
+!llvm.module.flags = !{ !0 }

llvm/test/CodeGen/AMDGPU/tid-xnack-default-sramecc-off.ll

+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-sram-ecc --amdgcn-new-target-id < %s | FileCheck --check-prefixes=ASM %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-sram-ecc --amdgcn-new-target-id -filetype=obj < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=ELF %s
+
+; ASM: .amdgcn_target "amdgcn-amd-amdhsa--gfx900:sramecc-"
+; ASM: amdhsa.target: 'amdgcn-amd-amdhsa--gfx900:sramecc-'
+; ELF: Flags [ (0x92C)
+; ELF:   EF_AMDGPU_FEATURE_SRAMECC_OFF (0x800)
+; ELF:   EF_AMDGPU_FEATURE_XNACK_DEFAULT (0x100)
+; ELF:   EF_AMDGPU_MACH_AMDGCN_GFX900 (0x2C)
+; ELF: ]
+
+define amdgpu_kernel void @empty() {
+entry:
+  ret void
+}
+
+!0 = !{ i32 8, !"target-id", !"amdgcn-amd-amdhsa--gfx900:sramecc-" }
+!llvm.module.flags = !{ !0 }

llvm/test/CodeGen/AMDGPU/tid-xnack-default-sramecc-on.ll

+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=+sram-ecc --amdgcn-new-target-id < %s | FileCheck --check-prefixes=ASM %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=+sram-ecc --amdgcn-new-target-id -filetype=obj < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=ELF %s
+
+; ASM: .amdgcn_target "amdgcn-amd-amdhsa--gfx900:sramecc+"
+; ASM: amdhsa.target: 'amdgcn-amd-amdhsa--gfx900:sramecc+'
+; ELF: Flags [ (0xD2C)
+; ELF:   EF_AMDGPU_FEATURE_SRAMECC_ON (0xC00)
+; ELF:   EF_AMDGPU_FEATURE_XNACK_DEFAULT (0x100)
+; ELF:   EF_AMDGPU_MACH_AMDGCN_GFX900 (0x2C)
+; ELF: ]
+
+define amdgpu_kernel void @empty() {
+entry:
+  ret void
+}
+
+!0 = !{ i32 8, !"target-id", !"amdgcn-amd-amdhsa--gfx900:sramecc+" }
+!llvm.module.flags = !{ !0 }

llvm/test/CodeGen/AMDGPU/tid-xnack-off-sramecc-default.ll

+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-xnack --amdgcn-new-target-id < %s | FileCheck --check-prefixes=ASM %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-xnack --amdgcn-new-target-id -filetype=obj < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=ELF %s
+
+; ASM: .amdgcn_target "amdgcn-amd-amdhsa--gfx900:xnack-"
+; ASM: amdhsa.target: 'amdgcn-amd-amdhsa--gfx900:xnack-'
+; ELF: Flags [ (0x62C)
+; ELF:   EF_AMDGPU_FEATURE_SRAMECC_DEFAULT (0x400)
+; ELF:   EF_AMDGPU_FEATURE_XNACK_OFF (0x200)
+; ELF:   EF_AMDGPU_MACH_AMDGCN_GFX900 (0x2C)
+; ELF: ]
+
+define amdgpu_kernel void @empty() {
+entry:
+  ret void
+}
+
+!0 = !{ i32 8, !"target-id", !"amdgcn-amd-amdhsa--gfx900:xnack-" }
+!llvm.module.flags = !{ !0 }

llvm/test/CodeGen/AMDGPU/tid-xnack-off-sramecc-off.ll

+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-xnack,-sram-ecc --amdgcn-new-target-id < %s | FileCheck --check-prefixes=ASM %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-xnack,-sram-ecc --amdgcn-new-target-id -filetype=obj < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=ELF %s
+
+; ASM: .amdgcn_target "amdgcn-amd-amdhsa--gfx900:xnack-:sramecc-"
+; ASM: amdhsa.target: 'amdgcn-amd-amdhsa--gfx900:xnack-:sramecc-'
+; ELF: Flags [ (0xA2C)
+; ELF:   EF_AMDGPU_FEATURE_SRAMECC_OFF (0x800)
+; ELF:   EF_AMDGPU_FEATURE_XNACK_OFF (0x200)
+; ELF:   EF_AMDGPU_MACH_AMDGCN_GFX900 (0x2C)
+; ELF: ]
+
+define amdgpu_kernel void @empty() {
+entry:
+  ret void
+}
+
+!0 = !{ i32 8, !"target-id", !"amdgcn-amd-amdhsa--gfx900:xnack-:sramecc-" }
+!llvm.module.flags = !{ !0 }

llvm/test/CodeGen/AMDGPU/tid-xnack-off-sramecc-on.ll

+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-xnack,+sram-ecc --amdgcn-new-target-id < %s | FileCheck --check-prefixes=ASM %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-xnack,+sram-ecc --amdgcn-new-target-id -filetype=obj < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=ELF %s
+
+; ASM: .amdgcn_target "amdgcn-amd-amdhsa--gfx900:xnack-:sramecc+"
+; ASM: amdhsa.target: 'amdgcn-amd-amdhsa--gfx900:xnack-:sramecc+'
+; ELF: Flags [ (0xE2C)
+; ELF:   EF_AMDGPU_FEATURE_SRAMECC_ON (0xC00)
+; ELF:   EF_AMDGPU_FEATURE_XNACK_OFF (0x200)
+; ELF:   EF_AMDGPU_MACH_AMDGCN_GFX900 (0x2C)
+; ELF: ]
+
+define amdgpu_kernel void @empty() {
+entry:
+  ret void
+}
+
+!0 = !{ i32 8, !"target-id", !"amdgcn-amd-amdhsa--gfx900:xnack-:sramecc+" }
+!llvm.module.flags = !{ !0 }

llvm/test/CodeGen/AMDGPU/tid-xnack-on-sramecc-default.ll

+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=+xnack --amdgcn-new-target-id < %s | FileCheck --check-prefixes=ASM %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=+xnack --amdgcn-new-target-id -filetype=obj < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=ELF %s
+
+; ASM: .amdgcn_target "amdgcn-amd-amdhsa--gfx900:xnack+"
+; ASM: amdhsa.target: 'amdgcn-amd-amdhsa--gfx900:xnack+'
+; ELF: Flags [ (0x72C)
+; ELF:   EF_AMDGPU_FEATURE_SRAMECC_DEFAULT (0x400)
+; ELF:   EF_AMDGPU_FEATURE_XNACK_ON (0x300)
+; ELF:   EF_AMDGPU_MACH_AMDGCN_GFX900 (0x2C)
+; ELF: ]
+
+define amdgpu_kernel void @empty() {
+entry:
+  ret void
+}
+
+!0 = !{ i32 8, !"target-id", !"amdgcn-amd-amdhsa--gfx900:xnack+" }
+!llvm.module.flags = !{ !0 }

llvm/test/CodeGen/AMDGPU/tid-xnack-on-sramecc-off.ll

+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=+xnack,-sram-ecc --amdgcn-new-target-id < %s | FileCheck --check-prefixes=ASM %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=+xnack,-sram-ecc --amdgcn-new-target-id -filetype=obj < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=ELF %s
+
+; ASM: .amdgcn_target "amdgcn-amd-amdhsa--gfx900:xnack+:sramecc-"
+; ASM: amdhsa.target: 'amdgcn-amd-amdhsa--gfx900:xnack+:sramecc-'
+; ELF: Flags [ (0xB2C)
+; ELF:   EF_AMDGPU_FEATURE_SRAMECC_OFF (0x800)
+; ELF:   EF_AMDGPU_FEATURE_XNACK_ON (0x300)
+; ELF:   EF_AMDGPU_MACH_AMDGCN_GFX900 (0x2C)
+; ELF: ]
+
+define amdgpu_kernel void @empty() {
+entry:
+  ret void
+}
+
+!0 = !{ i32 8, !"target-id", !"amdgcn-amd-amdhsa--gfx900:xnack+:sramecc-" }
+!llvm.module.flags = !{ !0 }

llvm/test/CodeGen/AMDGPU/tid-xnack-on-sramecc-on.ll

+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=+xnack,+sram-ecc --amdgcn-new-target-id < %s | FileCheck --check-prefixes=ASM %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=+xnack,+sram-ecc --amdgcn-new-target-id -filetype=obj < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=ELF %s
+
+; ASM: .amdgcn_target "amdgcn-amd-amdhsa--gfx900:xnack+:sramecc+"
+; ASM: amdhsa.target: 'amdgcn-amd-amdhsa--gfx900:xnack+:sramecc+'
+; ELF: Flags [ (0xF2C)
+; ELF:   EF_AMDGPU_FEATURE_SRAMECC_ON (0xC00)
+; ELF:   EF_AMDGPU_FEATURE_XNACK_ON (0x300)
+; ELF:   EF_AMDGPU_MACH_AMDGCN_GFX900 (0x2C)
+; ELF: ]
+
+define amdgpu_kernel void @empty() {
+entry:
+  ret void
+}
+
+!0 = !{ i32 8, !"target-id", !"amdgcn-amd-amdhsa--gfx900:xnack+:sramecc+" }
+!llvm.module.flags = !{ !0 }

llvm/test/MC/AMDGPU/tid-incompatible-sti-1.s

+// RUN: not llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdgcn-new-target-id %s 2>&1 | FileCheck %s
+
+// CHECK: error: target must match options
+
+.amdgcn_target "amdgcn-amd-amdhsa--gfx803"
+.text

llvm/test/MC/AMDGPU/tid-incompatible-sti-2.s

+// RUN: not llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdgcn-new-target-id %s 2>&1 | FileCheck %s
+
+// CHECK: error: target must match options
+
+.amdgcn_target "amdgcn-amd-amdhsa--gfx900:xnack+:sramecc+"
+.text

llvm/test/MC/AMDGPU/tid-none.s

+// RUN: llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdgcn-new-target-id %s | FileCheck --check-prefixes=ASM %s
+// RUN: llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdgcn-new-target-id -filetype=obj %s | llvm-readobj --file-headers - |FileCheck --check-prefixes=ELF %s
+
+// ASM-NOT: .amdgcn_target
+// ELF: Flags [ (0x52C)
+// ELF:   EF_AMDGPU_FEATURE_SRAMECC_DEFAULT (0x400)
+// ELF:   EF_AMDGPU_FEATURE_XNACK_DEFAULT (0x100)
+// ELF:   EF_AMDGPU_MACH_AMDGCN_GFX900 (0x2C)
+// ELF: ]
+
+.text

llvm/test/MC/AMDGPU/tid-xnack-default-sramecc-default.s

+// RUN: llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdgcn-new-target-id %s | FileCheck --check-prefixes=ASM %s
+// RUN: llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdgcn-new-target-id -filetype=obj %s | llvm-readobj --file-headers - |FileCheck --check-prefixes=ELF %s
+
+// ASM: .amdgcn_target "amdgcn-amd-amdhsa--gfx900"
+// ELF: Flags [ (0x52C)
+// ELF:   EF_AMDGPU_FEATURE_SRAMECC_DEFAULT (0x400)
+// ELF:   EF_AMDGPU_FEATURE_XNACK_DEFAULT (0x100)
+// ELF:   EF_AMDGPU_MACH_AMDGCN_GFX900 (0x2C)
+// ELF: ]
+
+.amdgcn_target "amdgcn-amd-amdhsa--gfx900"
+.text

llvm/test/MC/AMDGPU/tid-xnack-default-sramecc-off.s

+// RUN: llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx900 --mattr=-sram-ecc --amdgcn-new-target-id %s | FileCheck --check-prefixes=ASM %s
+// RUN: llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx900 --mattr=-sram-ecc --amdgcn-new-target-id -filetype=obj %s | llvm-readobj --file-headers - |FileCheck --check-prefixes=ELF %s
+
+// ASM: .amdgcn_target "amdgcn-amd-amdhsa--gfx900:sramecc-"
+// ELF: Flags [ (0x92C)
+// ELF:   EF_AMDGPU_FEATURE_SRAMECC_OFF (0x800)
+// ELF:   EF_AMDGPU_FEATURE_XNACK_DEFAULT (0x100)
+// ELF:   EF_AMDGPU_MACH_AMDGCN_GFX900 (0x2C)
+// ELF: ]
+
+.amdgcn_target "amdgcn-amd-amdhsa--gfx900:sramecc-"
+.text

llvm/test/MC/AMDGPU/tid-xnack-default-sramecc-on.s

+// RUN: llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx900 --mattr=+sram-ecc --amdgcn-new-target-id %s | FileCheck --check-prefixes=ASM %s
+// RUN: llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx900 --mattr=+sram-ecc --amdgcn-new-target-id -filetype=obj %s | llvm-readobj --file-headers - |FileCheck --check-prefixes=ELF %s
+
+// ASM: .amdgcn_target "amdgcn-amd-amdhsa--gfx900:sramecc+"
+// ELF: Flags [ (0xD2C)
+// ELF:   EF_AMDGPU_FEATURE_SRAMECC_ON (0xC00)
+// ELF:   EF_AMDGPU_FEATURE_XNACK_DEFAULT (0x100)
+// ELF:   EF_AMDGPU_MACH_AMDGCN_GFX900 (0x2C)
+// ELF: ]
+
+.amdgcn_target "amdgcn-amd-amdhsa--gfx900:sramecc+"
+.text

llvm/test/MC/AMDGPU/tid-xnack-off-sramecc-default.s

+// RUN: llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx900 --mattr=-xnack --amdgcn-new-target-id %s | FileCheck --check-prefixes=ASM %s
+// RUN: llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx900 --mattr=-xnack --amdgcn-new-target-id -filetype=obj %s | llvm-readobj --file-headers - |FileCheck --check-prefixes=ELF %s
+
+// ASM: .amdgcn_target "amdgcn-amd-amdhsa--gfx900:xnack-"
+// ELF: Flags [ (0x62C)
+// ELF:   EF_AMDGPU_FEATURE_SRAMECC_DEFAULT (0x400)
+// ELF:   EF_AMDGPU_FEATURE_XNACK_OFF (0x200)
+// ELF:   EF_AMDGPU_MACH_AMDGCN_GFX900 (0x2C)
+// ELF: ]
+
+.amdgcn_target "amdgcn-amd-amdhsa--gfx900:xnack-"
+.text

llvm/test/MC/AMDGPU/tid-xnack-off-sramecc-off.s

+// RUN: llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx900 --mattr=-xnack,-sram-ecc --amdgcn-new-target-id %s | FileCheck --check-prefixes=ASM %s
+// RUN: llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx900 --mattr=-xnack,-sram-ecc --amdgcn-new-target-id -filetype=obj %s | llvm-readobj --file-headers - |FileCheck --check-prefixes=ELF %s
+
+// ASM: .amdgcn_target "amdgcn-amd-amdhsa--gfx900:xnack-:sramecc-"
+// ELF: Flags [ (0xA2C)
+// ELF:   EF_AMDGPU_FEATURE_SRAMECC_OFF (0x800)
+// ELF:   EF_AMDGPU_FEATURE_XNACK_OFF (0x200)
+// ELF:   EF_AMDGPU_MACH_AMDGCN_GFX900 (0x2C)
+// ELF: ]
+
+.amdgcn_target "amdgcn-amd-amdhsa--gfx900:xnack-:sramecc-"
+.text

llvm/test/MC/AMDGPU/tid-xnack-off-sramecc-on.s

+// RUN: llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx900 --mattr=-xnack,+sram-ecc --amdgcn-new-target-id %s | FileCheck --check-prefixes=ASM %s
+// RUN: llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx900 --mattr=-xnack,+sram-ecc --amdgcn-new-target-id -filetype=obj %s | llvm-readobj --file-headers - |FileCheck --check-prefixes=ELF %s
+
+// ASM: .amdgcn_target "amdgcn-amd-amdhsa--gfx900:xnack-:sramecc+"
+// ELF: Flags [ (0xE2C)
+// ELF:   EF_AMDGPU_FEATURE_SRAMECC_ON (0xC00)
+// ELF:   EF_AMDGPU_FEATURE_XNACK_OFF (0x200)
+// ELF:   EF_AMDGPU_MACH_AMDGCN_GFX900 (0x2C)
+// ELF: ]
+
+.amdgcn_target "amdgcn-amd-amdhsa--gfx900:xnack-:sramecc+"
+.text

llvm/test/MC/AMDGPU/tid-xnack-on-sramecc-default.s

+// RUN: llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx900 --mattr=+xnack --amdgcn-new-target-id %s | FileCheck --check-prefixes=ASM %s
+// RUN: llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx900 --mattr=+xnack --amdgcn-new-target-id -filetype=obj %s | llvm-readobj --file-headers - |FileCheck --check-prefixes=ELF %s
+
+// ASM: .amdgcn_target "amdgcn-amd-amdhsa--gfx900:xnack+"
+// ELF: Flags [ (0x72C)
+// ELF:   EF_AMDGPU_FEATURE_SRAMECC_DEFAULT (0x400)
+// ELF:   EF_AMDGPU_FEATURE_XNACK_ON (0x300)
+// ELF:   EF_AMDGPU_MACH_AMDGCN_GFX900 (0x2C)
+// ELF: ]
+
+.amdgcn_target "amdgcn-amd-amdhsa--gfx900:xnack+"
+.text

llvm/test/MC/AMDGPU/tid-xnack-on-sramecc-off.s

+// RUN: llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx900 --mattr=+xnack,-sram-ecc --amdgcn-new-target-id %s | FileCheck --check-prefixes=ASM %s
+// RUN: llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx900 --mattr=+xnack,-sram-ecc --amdgcn-new-target-id -filetype=obj %s | llvm-readobj --file-headers - |FileCheck --check-prefixes=ELF %s
+
+// ASM: .amdgcn_target "amdgcn-amd-amdhsa--gfx900:xnack+:sramecc-"
+// ELF: Flags [ (0xB2C)
+// ELF:   EF_AMDGPU_FEATURE_SRAMECC_OFF (0x800)
+// ELF:   EF_AMDGPU_FEATURE_XNACK_ON (0x300)
+// ELF:   EF_AMDGPU_MACH_AMDGCN_GFX900 (0x2C)
+// ELF: ]
+
+.amdgcn_target "amdgcn-amd-amdhsa--gfx900:xnack+:sramecc-"
+.text

llvm/test/MC/AMDGPU/tid-xnack-on-sramecc-on.s

+// RUN: llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx900 --mattr=+xnack,+sram-ecc --amdgcn-new-target-id %s | FileCheck --check-prefixes=ASM %s
+// RUN: llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx900 --mattr=+xnack,+sram-ecc --amdgcn-new-target-id -filetype=obj %s | llvm-readobj --file-headers - |FileCheck --check-prefixes=ELF %s
+
+// ASM: .amdgcn_target "amdgcn-amd-amdhsa--gfx900:xnack+:sramecc+"
+// ELF: Flags [ (0xF2C)
+// ELF:   EF_AMDGPU_FEATURE_SRAMECC_ON (0xC00)
+// ELF:   EF_AMDGPU_FEATURE_XNACK_ON (0x300)
+// ELF:   EF_AMDGPU_MACH_AMDGCN_GFX900 (0x2C)
+// ELF: ]
+
+.amdgcn_target "amdgcn-amd-amdhsa--gfx900:xnack+:sramecc+"
+.text

llvm/tools/llvm-readobj/ELFDumper.cpp

static const EnumEntry<unsigned> ElfHeaderMipsFlags[] = {
   ENUM_ENT(EF_MIPS_ARCH_32, "mips32"),
   ENUM_ENT(EF_MIPS_ARCH_64, "mips64"),
   ENUM_ENT(EF_MIPS_ARCH_32R2, "mips32r2"),
   ENUM_ENT(EF_MIPS_ARCH_64R2, "mips64r2"),
   ENUM_ENT(EF_MIPS_ARCH_32R6, "mips32r6"),
   ENUM_ENT(EF_MIPS_ARCH_64R6, "mips64r6")
 };
 
-static const EnumEntry<unsigned> ElfHeaderAMDGPUFlags[] = {
+static const EnumEntry<unsigned> ElfHeaderAMDGPUFlagsABIVersion01[] = {
   LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_NONE),
   LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_R600_R600),
   LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_R600_R630),
   LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_R600_RS880),
   LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_R600_RV670),
   LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_R600_RV710),
   LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_R600_RV730),
   LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_R600_RV770),
static const EnumEntry<unsigned> ElfHeaderAMDGPUFlagsABIVersion01[] = {
   LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX909),
   LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX1010),
   LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX1011),
   LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX1012),
   LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_XNACK),
   LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_SRAM_ECC)
 };
 
+static const EnumEntry<unsigned> ElfHeaderAMDGPUFlagsABIVersion2[] = {
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_NONE),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_R600_R600),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_R600_R630),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_R600_RS880),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_R600_RV670),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_R600_RV710),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_R600_RV730),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_R600_RV770),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_R600_CEDAR),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_R600_CYPRESS),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_R600_JUNIPER),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_R600_REDWOOD),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_R600_SUMO),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_R600_BARTS),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_R600_CAICOS),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_R600_CAYMAN),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_R600_TURKS),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX600),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX601),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX700),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX701),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX702),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX703),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX704),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX801),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX802),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX803),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX810),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX900),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX902),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX904),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX906),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX908),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX909),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX1010),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX1011),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX1012),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_FEATURE_XNACK_DEFAULT),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_FEATURE_XNACK_OFF),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_FEATURE_XNACK_ON),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_FEATURE_SRAMECC_DEFAULT),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_FEATURE_SRAMECC_OFF),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_FEATURE_SRAMECC_ON),
+};
+
 static const EnumEntry<unsigned> ElfHeaderRISCVFlags[] = {
   ENUM_ENT(EF_RISCV_RVC, "RVC"),
   ENUM_ENT(EF_RISCV_FLOAT_ABI_SINGLE, "single-float ABI"),
   ENUM_ENT(EF_RISCV_FLOAT_ABI_DOUBLE, "double-float ABI"),
   ENUM_ENT(EF_RISCV_FLOAT_ABI_QUAD, "quad-float ABI"),
   ENUM_ENT(EF_RISCV_RVE, "RVE")
 };
 
const Elf_Ehdr *E = Obj->getHeader();
     W.printNumber("Version", E->e_version);
     W.printHex("Entry", E->e_entry);
     W.printHex("ProgramHeaderOffset", E->e_phoff);
     W.printHex("SectionHeaderOffset", E->e_shoff);
     if (E->e_machine == EM_MIPS)
       W.printFlags("Flags", E->e_flags, makeArrayRef(ElfHeaderMipsFlags),
                    unsigned(ELF::EF_MIPS_ARCH), unsigned(ELF::EF_MIPS_ABI),
                    unsigned(ELF::EF_MIPS_MACH));
-    else if (E->e_machine == EM_AMDGPU)
-      W.printFlags("Flags", E->e_flags, makeArrayRef(ElfHeaderAMDGPUFlags),
+    else if (E->e_machine == EM_AMDGPU) {
+      if (E->e_ident[EI_ABIVERSION] == 0 || E->e_ident[EI_ABIVERSION] == 1) {
+        W.printFlags("Flags", E->e_flags,
+                     makeArrayRef(ElfHeaderAMDGPUFlagsABIVersion01),
                      unsigned(ELF::EF_AMDGPU_MACH));
+      } else if (E->e_ident[EI_ABIVERSION] == 2) {
+        W.printFlags("Flags", E->e_flags,
+                     makeArrayRef(ElfHeaderAMDGPUFlagsABIVersion2),
+                     unsigned(ELF::EF_AMDGPU_MACH),
+                     unsigned(ELF::EF_AMDGPU_FEATURE_XNACK),
+                     unsigned(ELF::EF_AMDGPU_FEATURE_SRAMECC));
+      }
+    }
     else if (E->e_machine == EM_RISCV)
       W.printFlags("Flags", E->e_flags, makeArrayRef(ElfHeaderRISCVFlags));
     else
       W.printFlags("Flags", E->e_flags);
     W.printNumber("HeaderSize", E->e_ehsize);
     W.printNumber("ProgramHeaderEntrySize", E->e_phentsize);
     W.printNumber("ProgramHeaderCount", E->e_phnum);
     W.printNumber("SectionHeaderEntrySize", E->e_shentsize);