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AMDGPU: Fix spill/restore of 192-bit registers
ClosedPublic

Authored by arsenm on Jun 11 2020, 6:41 PM.

Details

Summary

I tried to use an IR inline asm test, but that doesn't work since the
inline asm handling asserts without an MVT to use.

Diff Detail

Event Timeline

arsenm created this revision.Jun 11 2020, 6:41 PM
Herald added a project: Restricted Project. · View Herald TranscriptJun 11 2020, 6:41 PM
arsenm updated this revision to Diff 270285.Jun 11 2020, 6:57 PM
arsenm updated this revision to Diff 270289.Jun 11 2020, 7:14 PM

Fix expansion

critson added inline comments.Jun 12 2020, 8:09 AM
llvm/test/CodeGen/AMDGPU/spill-wide-vgpr.ll
2

At the moment this test seems to fail with an assertion?

arsenm marked an inline comment as done.Jun 12 2020, 8:55 AM
arsenm added inline comments.
llvm/test/CodeGen/AMDGPU/spill-wide-vgpr.ll
2

Yes, this was the first attempt at a test (but the asm will never work as mentioned in the commit). I deleted this test after posting

rampitec added inline comments.Jun 12 2020, 10:52 AM
llvm/test/CodeGen/AMDGPU/spill-wide-vgpr.ll
2

But it is still here?

arsenm marked an inline comment as done.Jun 12 2020, 10:55 AM
arsenm added inline comments.
llvm/test/CodeGen/AMDGPU/spill-wide-vgpr.ll
2

Yes, pretend it's not

rampitec accepted this revision.Jun 12 2020, 11:31 AM

Pretend it is LGTM. Less the test ;)

This revision is now accepted and ready to land.Jun 12 2020, 11:31 AM