[VE] Support host memory access instructions in MC layer

[kaz7]

Summary

Add LHM/SHM instructions. Add regression tests for them of asmparser,
mccodeemitter, and disassembler. In order to add those instructions,
add new decode functions to disassembler, and add new print functions
to instprinter.

llvm/lib/Target/VE/Disassembler/VEDisassembler.cpp

 static DecodeStatus DecodeLoadI64(MCInst &Inst, uint64_t insn, uint64_t Address,
                                   const void *Decoder);
 static DecodeStatus DecodeStoreI64(MCInst &Inst, uint64_t insn,
                                    uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeLoadF32(MCInst &Inst, uint64_t insn, uint64_t Address,
                                   const void *Decoder);
 static DecodeStatus DecodeStoreF32(MCInst &Inst, uint64_t insn,
                                    uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeLoadASI64(MCInst &Inst, uint64_t insn,
+                                    uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeStoreASI64(MCInst &Inst, uint64_t insn,
+                                     uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeTS1AMI64(MCInst &Inst, uint64_t insn,
                                    uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeTS1AMI32(MCInst &Inst, uint64_t insn,
                                    uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeCASI64(MCInst &Inst, uint64_t insn, uint64_t Address,
                                  const void *Decoder);
 static DecodeStatus DecodeCASI32(MCInst &Inst, uint64_t insn, uint64_t Address,
                                  const void *Decoder);
static DecodeStatus DecodeMem(MCInst &MI, uint64_t insn, uint64_t Address,
   if (!isLoad) {
     status = DecodeSX(MI, sx, Address, Decoder);
     if (status != MCDisassembler::Success)
       return status;
   }
   return MCDisassembler::Success;
 }
 
+static DecodeStatus DecodeMemAS(MCInst &MI, uint64_t insn, uint64_t Address,
+                                const void *Decoder, bool isLoad,
+                                DecodeFunc DecodeSX) {
+  unsigned sx = fieldFromInstruction(insn, 48, 7);
+
+  DecodeStatus status;
+  if (isLoad) {
+    status = DecodeSX(MI, sx, Address, Decoder);
+    if (status != MCDisassembler::Success)
+      return status;
+  }
+
+  status = DecodeAS(MI, insn, Address, Decoder);
+  if (status != MCDisassembler::Success)
+    return status;
+
+  if (!isLoad) {
+    status = DecodeSX(MI, sx, Address, Decoder);
+    if (status != MCDisassembler::Success)
+      return status;
+  }
+  return MCDisassembler::Success;
+}
+
 static DecodeStatus DecodeLoadI32(MCInst &Inst, uint64_t insn, uint64_t Address,
                                   const void *Decoder) {
   return DecodeMem(Inst, insn, Address, Decoder, true, DecodeI32RegisterClass);
 }
 
 static DecodeStatus DecodeStoreI32(MCInst &Inst, uint64_t insn,
                                    uint64_t Address, const void *Decoder) {
   return DecodeMem(Inst, insn, Address, Decoder, false, DecodeI32RegisterClass);
static DecodeStatus DecodeLoadF32(MCInst &Inst, uint64_t insn, uint64_t Address,
   return DecodeMem(Inst, insn, Address, Decoder, true, DecodeF32RegisterClass);
 }
 
 static DecodeStatus DecodeStoreF32(MCInst &Inst, uint64_t insn,
                                    uint64_t Address, const void *Decoder) {
   return DecodeMem(Inst, insn, Address, Decoder, false, DecodeF32RegisterClass);
 }
 
+static DecodeStatus DecodeLoadASI64(MCInst &Inst, uint64_t insn,
+                                    uint64_t Address, const void *Decoder) {
+  return DecodeMemAS(Inst, insn, Address, Decoder, true,
+                     DecodeI64RegisterClass);
+}
+
+static DecodeStatus DecodeStoreASI64(MCInst &Inst, uint64_t insn,
+                                     uint64_t Address, const void *Decoder) {
+  return DecodeMemAS(Inst, insn, Address, Decoder, false,
+                     DecodeI64RegisterClass);
+}
+
 static DecodeStatus DecodeCAS(MCInst &MI, uint64_t insn, uint64_t Address,
                               const void *Decoder, bool isImmOnly, bool isUImm,
                               DecodeFunc DecodeSX) {
   unsigned sx = fieldFromInstruction(insn, 48, 7);
   bool cy = fieldFromInstruction(insn, 47, 1);
   unsigned sy = fieldFromInstruction(insn, 40, 7);
 
   // Add $sx.

llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.h

void printMemASXOperand(const MCInst *MI, int OpNum,
                           const MCSubtargetInfo &STI, raw_ostream &OS,
                           const char *Modifier = nullptr);
   void printMemASOperandASX(const MCInst *MI, int OpNum,
                             const MCSubtargetInfo &STI, raw_ostream &OS,
                             const char *Modifier = nullptr);
   void printMemASOperandRRM(const MCInst *MI, int OpNum,
                             const MCSubtargetInfo &STI, raw_ostream &OS,
                             const char *Modifier = nullptr);
-  void printMemASOperand(const MCInst *MI, int OpNum,
+  void printMemASOperandHM(const MCInst *MI, int OpNum,
                            const MCSubtargetInfo &STI, raw_ostream &OS,
                            const char *Modifier = nullptr);
   void printMImmOperand(const MCInst *MI, int OpNum, const MCSubtargetInfo &STI,
                         raw_ostream &OS);
   void printCCOperand(const MCInst *MI, int OpNum, const MCSubtargetInfo &STI,
                       raw_ostream &OS);
   void printRDOperand(const MCInst *MI, int OpNum, const MCSubtargetInfo &STI,
                       raw_ostream &OS);
 };
 } // namespace llvm
 
 #endif

llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.cpp

if (MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) {
     }
   } else {
     O << "(";
     printOperand(MI, OpNum, STI, O);
     O << ")";
   }
 }
 
-void VEInstPrinter::printMemASOperand(const MCInst *MI, int OpNum,
+void VEInstPrinter::printMemASOperandHM(const MCInst *MI, int OpNum,
                                         const MCSubtargetInfo &STI,
                                         raw_ostream &O, const char *Modifier) {
   // If this is an ADD operand, emit it like normal operands.
   if (Modifier && !strcmp(Modifier, "arith")) {
     printOperand(MI, OpNum, STI, O);
     O << ", ";
     printOperand(MI, OpNum + 1, STI, O);
     return;
   }
 
-  const MCOperand &MO = MI->getOperand(OpNum + 1);
-  if (!MO.isImm() || MO.getImm() != 0) {
+  if (MI->getOperand(OpNum + 1).isImm() &&
+      MI->getOperand(OpNum + 1).getImm() == 0) {
+    // don't print "+0"
+  } else {
     printOperand(MI, OpNum + 1, STI, O);
   }
   O << "(";
+  if (MI->getOperand(OpNum).isReg())
     printOperand(MI, OpNum, STI, O);
   O << ")";
 }
 
 void VEInstPrinter::printMImmOperand(const MCInst *MI, int OpNum,
                                      const MCSubtargetInfo &STI,
                                      raw_ostream &O) {
   int MImm = (int)MI->getOperand(OpNum).getImm() & 0x7f;
   if (MImm > 63)

llvm/lib/Target/VE/VEInstrFormats.td

 // RRM type is identical to RM, but the effective address is generated
 // by sz + imm32.  The sy field is used by other purposes.
 //-----------------------------------------------------------------------------
 
 class RRM<bits<8>opVal, dag outs, dag ins, string asmstr,
           list<dag> pattern = []>
    : RM<opVal, outs, ins, asmstr, pattern>;
 
+// RRMHM type is to load/store host memory
+// It is similar to RRM and not use sy.
+class RRMHM<bits<8>opVal, dag outs, dag ins, string asmstr,
+            list<dag> pattern = []>
+   : RRM<opVal, outs, ins, asmstr, pattern> {
+  bits<2> ry = 0;
+  let cy = 0;
+  let sy{6-2} = 0;
+  let sy{1-0} = ry;
+}
+
 //-----------------------------------------------------------------------------
 // Section 5.3 CF Type
 //
 // CF type is used for control flow.
 //-----------------------------------------------------------------------------
 
 class CF<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern = []>
    : InstVE<outs, ins, asmstr, pattern> {

llvm/lib/Target/VE/VEInstrInfo.cpp

BuildMI(BB, dl, TII.get(VE::LDrii), VE::SX61)
       .addImm(0x18);
   BuildMI(BB, dl, TII.get(VE::ORri), VE::SX62)
       .addReg(VE::SX0)
       .addImm(0);
   BuildMI(BB, dl, TII.get(VE::LEAzii), VE::SX63)
       .addImm(0)
       .addImm(0)
       .addImm(0x13b);
-  BuildMI(BB, dl, TII.get(VE::SHMri))
+  BuildMI(BB, dl, TII.get(VE::SHMLri))
       .addReg(VE::SX61)
       .addImm(0)
       .addReg(VE::SX63);
-  BuildMI(BB, dl, TII.get(VE::SHMri))
+  BuildMI(BB, dl, TII.get(VE::SHMLri))
       .addReg(VE::SX61)
       .addImm(8)
       .addReg(VE::SX8);
-  BuildMI(BB, dl, TII.get(VE::SHMri))
+  BuildMI(BB, dl, TII.get(VE::SHMLri))
       .addReg(VE::SX61)
       .addImm(16)
       .addReg(VE::SX11);
   BuildMI(BB, dl, TII.get(VE::MONC));
 
   BuildMI(BB, dl, TII.get(VE::ORri), VE::SX0)
       .addReg(VE::SX62)
       .addImm(0);

llvm/lib/Target/VE/VEInstrInfo.td

def CCUIOp : PatLeaf<(cond), [{
   default:         return true;
   case ISD::SETLT:
   case ISD::SETLE:
   case ISD::SETGT:
   case ISD::SETGE: return false;
   }
 }]>;
 
+//===----------------------------------------------------------------------===//
 // Addressing modes.
 // SX-Aurora has following fields.
 //    sz: register or 0
 //    sy: register or immediate (-64 to 63)
 //    disp: immediate (-2147483648 to 2147483647)
 //
 // There are two kinds of instruction.
 //    ASX format uses sz + sy + disp.

 //
 // We defined them below.
 //
 // ASX format:
 //    MEMrri, MEMrii, MEMzri, MEMzii
 // AS format:
 //    MEMriASX, MEMziASX    : simple AS format
 //    MEMriRRM, MEMziRRM    : AS format in RRM format
-//    well be added later.
+//    MEMriHM, MEMziHM      : AS format in RRM format for host memory access
+//===----------------------------------------------------------------------===//
 
 // DAG selections for both ASX and AS formats.
 def ADDRrri : ComplexPattern<iPTR, 3, "selectADDRrri", [frameindex], []>;
 def ADDRrii : ComplexPattern<iPTR, 3, "selectADDRrii", [frameindex], []>;
 def ADDRzri : ComplexPattern<iPTR, 3, "selectADDRzri", [], []>;
 def ADDRzii : ComplexPattern<iPTR, 3, "selectADDRzii", [], []>;
 def ADDRri : ComplexPattern<iPTR, 2, "selectADDRri", [frameindex], []>;
 def ADDRzi : ComplexPattern<iPTR, 2, "selectADDRzi", [], []>;
def MEMriRRM : Operand<iPTR> {
   let ParserMatchClass = VEMEMriAsmOperand;
 }
 def MEMziRRM : Operand<iPTR> {
   let PrintMethod = "printMemASOperandRRM";
   let MIOperandInfo = (ops i32imm /* = 0 */, i32imm);
   let ParserMatchClass = VEMEMziAsmOperand;
 }
 
-def MEMASri : Operand<iPTR> {
-  let PrintMethod = "printMemASOperand";
+//   3. AS HM style assembly instruction format:
+def MEMriHM : Operand<iPTR> {
+  let PrintMethod = "printMemASOperandHM";
   let MIOperandInfo = (ops ptr_rc, i32imm);
   let ParserMatchClass = VEMEMriAsmOperand;
 }
+def MEMziHM : Operand<iPTR> {
+  let PrintMethod = "printMemASOperandHM";
+  let MIOperandInfo = (ops i32imm /* = 0 */, i32imm);
+  let ParserMatchClass = VEMEMziAsmOperand;
+}
+
+//===----------------------------------------------------------------------===//
+// Other operands.
+//===----------------------------------------------------------------------===//
 
 // Branch targets have OtherVT type.
 def brtarget32 : Operand<OtherVT> {
 }
 
 def calltarget : Operand<i64> {
 }
 

 let cz = 0, hasSideEffects = 1 in
 multiclass FIDCRm<string opcStr, bits<8>opc, RegisterClass RC> {
   def ri : RR<opc, (outs RC:$sx), (ins RC:$sy, uimm3:$sz),
               !strconcat(opcStr, " $sx, $sy, $sz")>;
   let cy = 0 in def ii : RR<opc, (outs RC:$sx), (ins simm7:$sy, uimm3:$sz),
                             !strconcat(opcStr, " $sx, $sy, $sz")>;
 }
 
+// Multiclass for LHM instruction.
+let mayLoad = 1, hasSideEffects = 0 in
+multiclass LHMm<string opcStr, bits<8> opc, RegisterClass RC> {
+  def ri : RRMHM<opc, (outs RC:$dest), (ins MEMriHM:$addr),
+                 !strconcat(opcStr, " $dest, $addr")>;
+  let cz = 0 in
+  def zi : RRMHM<opc, (outs RC:$dest), (ins MEMziHM:$addr),
+                 !strconcat(opcStr, " $dest, $addr")>;
+}
+
+// Multiclass for SHM instruction.
+let mayStore = 1, hasSideEffects = 0 in
+multiclass SHMm<string opcStr, bits<8> opc, RegisterClass RC> {
+  def ri : RRMHM<opc, (outs), (ins MEMriHM:$addr, RC:$sx),
+                 !strconcat(opcStr, " $sx, $addr")>;
+  let cz = 0 in
+  def zi : RRMHM<opc, (outs), (ins MEMziHM:$addr, RC:$sx),
+                 !strconcat(opcStr, " $sx, $addr")>;
+}
+
 //===----------------------------------------------------------------------===//
 // Instructions
 //
 // Define all scalar instructions defined in SX-Aurora TSUBASA Architecture
 // Guide here.  As those mnemonics, we use mnemonics defined in Vector Engine
 // Assembly Language Reference Manual.
 //===----------------------------------------------------------------------===//
 

 defm SCR : STORECRm<"scr", 0x50, I64>;
 
 // Section 8.19.11 - TSCR (Test & Set Communication Register)
 defm TSCR : LOADCRm<"tscr", 0x41, I64>;
 
 // Section 8.19.12 - FIDCR (Fetch & Increment/Decrement CR)
 defm FIDCR : FIDCRm<"fidcr", 0x51, I64>;
 
-let cx = 0, cy = 0, cz = 1, hasSideEffects = 0 in {
-let sy = 3 in
-def SHMri : RM<
-    0x31, (outs), (ins MEMASri:$addr, I64:$sx),
-    "shm.l $sx, $addr">;
-}
+//-----------------------------------------------------------------------------
+// Section 8.20 - Host Memory Access Instructions
+//-----------------------------------------------------------------------------
+
+// Section 8.20.1 - LHM (Load Host Memory)
+let ry = 3, DecoderMethod = "DecodeLoadASI64" in
+defm LHML : LHMm<"lhm.l", 0x21, I64>;
+let ry = 2, DecoderMethod = "DecodeLoadASI64" in
+defm LHMW : LHMm<"lhm.w", 0x21, I64>;
+let ry = 1, DecoderMethod = "DecodeLoadASI64" in
+defm LHMH : LHMm<"lhm.h", 0x21, I64>;
+let ry = 0, DecoderMethod = "DecodeLoadASI64" in
+defm LHMB : LHMm<"lhm.b", 0x21, I64>;
+
+// Section 8.20.2 - SHM (Store Host Memory)
+let ry = 3, DecoderMethod = "DecodeStoreASI64" in
+defm SHML : SHMm<"shm.l", 0x31, I64>;
+let ry = 2, DecoderMethod = "DecodeStoreASI64" in
+defm SHMW : SHMm<"shm.w", 0x31, I64>;
+let ry = 1, DecoderMethod = "DecodeStoreASI64" in
+defm SHMH : SHMm<"shm.h", 0x31, I64>;
+let ry = 0, DecoderMethod = "DecodeStoreASI64" in
+defm SHMB : SHMm<"shm.b", 0x31, I64>;
 
 //===----------------------------------------------------------------------===//
 // Instructions for CodeGenOnly
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
 // Pattern Matchings
 //===----------------------------------------------------------------------===//

llvm/test/MC/VE/LHM.s

+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: lhm.l %s20, 20(%s11)
+# CHECK-ENCODING: encoding: [0x14,0x00,0x00,0x00,0x8b,0x03,0x14,0x21]
+lhm.l %s20, 20(%s11)
+
+# CHECK-INST: lhm.w %s20, 8192()
+# CHECK-ENCODING: encoding: [0x00,0x20,0x00,0x00,0x00,0x02,0x14,0x21]
+lhm.w %s20, 8192()
+
+# CHECK-INST: lhm.h %s20, (%s11)
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x01,0x14,0x21]
+lhm.h %s20, (%s11)
+
+# CHECK-INST: lhm.b %s20, (%s11)
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x00,0x14,0x21]
+lhm.b %s20, %s11

llvm/test/MC/VE/SHM.s

+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: shm.l %s20, 20(%s11)
+# CHECK-ENCODING: encoding: [0x14,0x00,0x00,0x00,0x8b,0x03,0x14,0x31]
+shm.l %s20, 20(%s11)
+
+# CHECK-INST: shm.w %s20, 8192()
+# CHECK-ENCODING: encoding: [0x00,0x20,0x00,0x00,0x00,0x02,0x14,0x31]
+shm.w %s20, 8192()
+
+# CHECK-INST: shm.h %s20, (%s11)
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x01,0x14,0x31]
+shm.h %s20, (%s11)
+
+# CHECK-INST: shm.b %s20, (%s11)
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x00,0x14,0x31]
+shm.b %s20, %s11