Index: llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp =================================================================== --- llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp +++ llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp @@ -100,6 +100,8 @@ LegalizerHelper::legalizeInstrStep(MachineInstr &MI) { LLVM_DEBUG(dbgs() << "Legalizing: " << MI); + MIRBuilder.setInstrAndDebugLoc(MI); + if (MI.getOpcode() == TargetOpcode::G_INTRINSIC || MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS) return LI.legalizeIntrinsic(MI, MIRBuilder, Observer) ? Legalized @@ -634,8 +636,6 @@ unsigned Size = LLTy.getSizeInBits(); auto &Ctx = MIRBuilder.getMF().getFunction().getContext(); - MIRBuilder.setInstrAndDebugLoc(MI); - switch (MI.getOpcode()) { default: return UnableToLegalize; @@ -731,8 +731,6 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy) { - MIRBuilder.setInstrAndDebugLoc(MI); - uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); uint64_t NarrowSize = NarrowTy.getSizeInBits(); @@ -1644,8 +1642,6 @@ LegalizerHelper::LegalizeResult LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) { - MIRBuilder.setInstrAndDebugLoc(MI); - switch (MI.getOpcode()) { default: return UnableToLegalize; @@ -2195,8 +2191,6 @@ LegalizerHelper::LegalizeResult LegalizerHelper::bitcast(MachineInstr &MI, unsigned TypeIdx, LLT CastTy) { - MIRBuilder.setInstr(MI); - switch (MI.getOpcode()) { case TargetOpcode::G_LOAD: { if (TypeIdx != 0) @@ -2251,7 +2245,6 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) { using namespace TargetOpcode; - MIRBuilder.setInstrAndDebugLoc(MI); switch(MI.getOpcode()) { default: @@ -3325,7 +3318,6 @@ LLT NarrowTy) { using namespace TargetOpcode; - MIRBuilder.setInstrAndDebugLoc(MI); switch (MI.getOpcode()) { case G_IMPLICIT_DEF: return fewerElementsVectorImplicitDef(MI, TypeIdx, NarrowTy); @@ -3648,7 +3640,6 @@ LegalizerHelper::LegalizeResult LegalizerHelper::moreElementsVector(MachineInstr &MI, unsigned TypeIdx, LLT MoreTy) { - MIRBuilder.setInstrAndDebugLoc(MI); unsigned Opc = MI.getOpcode(); switch (Opc) { case TargetOpcode::G_IMPLICIT_DEF: Index: llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp =================================================================== --- llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp +++ llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp @@ -661,7 +661,6 @@ if (GV->isThreadLocal()) return true; // Don't want to modify TLS vars. - MIRBuilder.setInstrAndDebugLoc(MI); auto &TM = ST->getTargetLowering()->getTargetMachine(); unsigned OpFlags = ST->ClassifyGlobalReference(GV, TM); @@ -717,7 +716,6 @@ if (Amount > 31) return true; // This will have to remain a register variant. assert(MRI.getType(AmtReg).getSizeInBits() == 32); - MIRBuilder.setInstrAndDebugLoc(MI); auto ExtCst = MIRBuilder.buildZExt(LLT::scalar(64), AmtReg); MI.getOperand(2).setReg(ExtCst.getReg(0)); return true; @@ -746,7 +744,6 @@ return false; } - MIRBuilder.setInstrAndDebugLoc(MI); unsigned PtrSize = ValTy.getElementType().getSizeInBits(); const LLT NewTy = LLT::vector(ValTy.getNumElements(), PtrSize); auto &MMO = **MI.memoperands_begin(); @@ -764,7 +761,6 @@ bool AArch64LegalizerInfo::legalizeVaArg(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &MIRBuilder) const { - MIRBuilder.setInstrAndDebugLoc(MI); MachineFunction &MF = MIRBuilder.getMF(); Align Alignment(MI.getOperand(2).getImm()); Register Dst = MI.getOperand(0).getReg(); Index: llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp +++ llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp @@ -1571,8 +1571,6 @@ MachineIRBuilder &B) const { MachineFunction &MF = B.getMF(); - B.setInstr(MI); - const LLT S32 = LLT::scalar(32); Register Dst = MI.getOperand(0).getReg(); Register Src = MI.getOperand(1).getReg(); @@ -1668,8 +1666,6 @@ bool AMDGPULegalizerInfo::legalizeFrint( MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const { - B.setInstr(MI); - Register Src = MI.getOperand(1).getReg(); LLT Ty = MRI.getType(Src); assert(Ty.isScalar() && Ty.getSizeInBits() == 64); @@ -1695,7 +1691,6 @@ bool AMDGPULegalizerInfo::legalizeFceil( MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const { - B.setInstr(MI); const LLT S1 = LLT::scalar(1); const LLT S64 = LLT::scalar(64); @@ -1740,8 +1735,6 @@ bool AMDGPULegalizerInfo::legalizeIntrinsicTrunc( MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const { - B.setInstr(MI); - const LLT S1 = LLT::scalar(1); const LLT S32 = LLT::scalar(32); const LLT S64 = LLT::scalar(64); @@ -1786,7 +1779,6 @@ bool AMDGPULegalizerInfo::legalizeITOFP( MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, bool Signed) const { - B.setInstr(MI); Register Dst = MI.getOperand(0).getReg(); Register Src = MI.getOperand(1).getReg(); @@ -1820,7 +1812,6 @@ bool AMDGPULegalizerInfo::legalizeFPTOI( MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, bool Signed) const { - B.setInstr(MI); Register Dst = MI.getOperand(0).getReg(); Register Src = MI.getOperand(1).getReg(); @@ -1871,7 +1862,6 @@ MachineIRBuilder HelperBuilder(MI); GISelObserverWrapper DummyObserver; LegalizerHelper Helper(MF, DummyObserver, HelperBuilder); - HelperBuilder.setInstr(MI); return Helper.lowerFMinNumMaxNum(MI) == LegalizerHelper::Legalized; } @@ -1897,8 +1887,6 @@ LLT EltTy = VecTy.getElementType(); assert(EltTy == MRI.getType(Dst)); - B.setInstr(MI); - if (IdxVal->Value < VecTy.getNumElements()) B.buildExtract(Dst, Vec, IdxVal->Value * EltTy.getSizeInBits()); else @@ -1931,8 +1919,6 @@ LLT EltTy = VecTy.getElementType(); assert(EltTy == MRI.getType(Ins)); - B.setInstr(MI); - if (IdxVal->Value < VecTy.getNumElements()) B.buildInsert(Dst, Vec, Ins, IdxVal->Value * EltTy.getSizeInBits()); else @@ -1959,14 +1945,12 @@ MachineIRBuilder HelperBuilder(MI); GISelObserverWrapper DummyObserver; LegalizerHelper Helper(B.getMF(), DummyObserver, HelperBuilder); - HelperBuilder.setInstr(MI); return Helper.lowerShuffleVector(MI) == LegalizerHelper::Legalized; } bool AMDGPULegalizerInfo::legalizeSinCos( MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const { - B.setInstr(MI); Register DstReg = MI.getOperand(0).getReg(); Register SrcReg = MI.getOperand(1).getReg(); @@ -2058,7 +2042,6 @@ const GlobalValue *GV = MI.getOperand(1).getGlobal(); MachineFunction &MF = B.getMF(); SIMachineFunctionInfo *MFI = MF.getInfo(); - B.setInstr(MI); if (AS == AMDGPUAS::LOCAL_ADDRESS || AS == AMDGPUAS::REGION_ADDRESS) { if (!MFI->isEntryFunction()) { @@ -2138,7 +2121,6 @@ bool AMDGPULegalizerInfo::legalizeLoad( MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, GISelChangeObserver &Observer) const { - B.setInstr(MI); LLT ConstPtr = LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64); auto Cast = B.buildAddrSpaceCast(ConstPtr, MI.getOperand(1).getReg()); Observer.changingInstr(MI); @@ -2166,7 +2148,6 @@ MachineIRBuilder HelperBuilder(MI); GISelObserverWrapper DummyObserver; LegalizerHelper Helper(MF, DummyObserver, HelperBuilder); - HelperBuilder.setInstr(MI); return Helper.lowerFMad(MI) == LegalizerHelper::Legalized; } @@ -2184,7 +2165,6 @@ LLT ValTy = MRI.getType(CmpVal); LLT VecTy = LLT::vector(2, ValTy); - B.setInstr(MI); Register PackedVal = B.buildBuildVector(VecTy, { NewVal, CmpVal }).getReg(0); B.buildInstr(AMDGPU::G_AMDGPU_ATOMIC_CMPXCHG) @@ -2203,7 +2183,6 @@ Register Src = MI.getOperand(1).getReg(); LLT Ty = B.getMRI()->getType(Dst); unsigned Flags = MI.getFlags(); - B.setInstr(MI); auto Log2Operand = B.buildFLog2(Ty, Src, Flags); auto Log2BaseInvertedOperand = B.buildFConstant(Ty, Log2BaseInverted); @@ -2219,7 +2198,6 @@ Register Src = MI.getOperand(1).getReg(); unsigned Flags = MI.getFlags(); LLT Ty = B.getMRI()->getType(Dst); - B.setInstr(MI); auto K = B.buildFConstant(Ty, numbers::log2e); auto Mul = B.buildFMul(Ty, Src, K, Flags); @@ -2235,7 +2213,6 @@ Register Src1 = MI.getOperand(2).getReg(); unsigned Flags = MI.getFlags(); LLT Ty = B.getMRI()->getType(Dst); - B.setInstr(MI); const LLT S16 = LLT::scalar(16); const LLT S32 = LLT::scalar(32); @@ -2279,7 +2256,6 @@ bool AMDGPULegalizerInfo::legalizeFFloor(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const { - B.setInstr(MI); const LLT S1 = LLT::scalar(1); const LLT S64 = LLT::scalar(64); @@ -2345,7 +2321,6 @@ Register Src1 = MI.getOperand(2).getReg(); assert(MRI.getType(Src0) == LLT::scalar(16)); - B.setInstr(MI); auto Merge = B.buildMerge(S32, {Src0, Src1}); B.buildBitcast(Dst, Merge); @@ -2483,7 +2458,6 @@ bool AMDGPULegalizerInfo::legalizePreloadedArgIntrin( MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, AMDGPUFunctionArgInfo::PreloadedValue ArgType) const { - B.setInstr(MI); const ArgDescriptor *Arg = getArgDescriptor(B, ArgType); if (!Arg) @@ -2499,7 +2473,6 @@ bool AMDGPULegalizerInfo::legalizeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const { - B.setInstr(MI); Register Dst = MI.getOperand(0).getReg(); LLT DstTy = MRI.getType(Dst); LLT S16 = LLT::scalar(16); @@ -2622,7 +2595,6 @@ bool AMDGPULegalizerInfo::legalizeUDIV_UREM32(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const { - B.setInstr(MI); const bool IsRem = MI.getOpcode() == AMDGPU::G_UREM; Register DstReg = MI.getOperand(0).getReg(); Register Num = MI.getOperand(1).getReg(); @@ -2678,8 +2650,6 @@ bool AMDGPULegalizerInfo::legalizeUDIV_UREM64(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const { - B.setInstr(MI); - const bool IsDiv = MI.getOpcode() == TargetOpcode::G_UDIV; const LLT S32 = LLT::scalar(32); const LLT S64 = LLT::scalar(64); @@ -2808,7 +2778,6 @@ bool AMDGPULegalizerInfo::legalizeSDIV_SREM32(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const { - B.setInstr(MI); const LLT S32 = LLT::scalar(32); const bool IsRem = MI.getOpcode() == AMDGPU::G_SREM; @@ -2915,7 +2884,6 @@ bool AMDGPULegalizerInfo::legalizeFDIV16(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const { - B.setInstr(MI); Register Res = MI.getOperand(0).getReg(); Register LHS = MI.getOperand(1).getReg(); Register RHS = MI.getOperand(2).getReg(); @@ -2978,7 +2946,6 @@ bool AMDGPULegalizerInfo::legalizeFDIV32(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const { - B.setInstr(MI); Register Res = MI.getOperand(0).getReg(); Register LHS = MI.getOperand(1).getReg(); Register RHS = MI.getOperand(2).getReg(); @@ -3045,7 +3012,6 @@ bool AMDGPULegalizerInfo::legalizeFDIV64(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const { - B.setInstr(MI); Register Res = MI.getOperand(0).getReg(); Register LHS = MI.getOperand(1).getReg(); Register RHS = MI.getOperand(2).getReg(); @@ -3124,7 +3090,6 @@ bool AMDGPULegalizerInfo::legalizeFDIVFastIntrin(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const { - B.setInstr(MI); Register Res = MI.getOperand(0).getReg(); Register LHS = MI.getOperand(2).getReg(); Register RHS = MI.getOperand(3).getReg(); @@ -3166,8 +3131,6 @@ AMDGPUFunctionArgInfo::IMPLICIT_ARG_PTR); } - B.setInstr(MI); - uint64_t Offset = ST.getTargetLowering()->getImplicitParameterOffset( B.getMF(), AMDGPUTargetLowering::FIRST_IMPLICIT); @@ -3195,7 +3158,6 @@ MachineRegisterInfo &MRI, MachineIRBuilder &B, unsigned AddrSpace) const { - B.setInstr(MI); Register ApertureReg = getSegmentAperture(AddrSpace, MRI, B); auto Hi32 = B.buildExtract(LLT::scalar(32), MI.getOperand(2).getReg(), 32); B.buildICmp(ICmpInst::ICMP_EQ, MI.getOperand(0), Hi32, ApertureReg); @@ -3303,8 +3265,6 @@ MachineIRBuilder &B, bool IsTyped, bool IsFormat) const { - B.setInstr(MI); - Register VData = MI.getOperand(1).getReg(); LLT Ty = MRI.getType(VData); LLT EltTy = Ty.getScalarType(); @@ -3395,8 +3355,6 @@ MachineIRBuilder &B, bool IsFormat, bool IsTyped) const { - B.setInstr(MI); - // FIXME: Verifier should enforce 1 MMO for these intrinsics. MachineMemOperand *MMO = *MI.memoperands_begin(); const int MemSize = MMO->getSize(); @@ -3515,7 +3473,6 @@ bool AMDGPULegalizerInfo::legalizeAtomicIncDec(MachineInstr &MI, MachineIRBuilder &B, bool IsInc) const { - B.setInstr(MI); unsigned Opc = IsInc ? AMDGPU::G_AMDGPU_ATOMIC_INC : AMDGPU::G_AMDGPU_ATOMIC_DEC; B.buildInstr(Opc) @@ -3576,8 +3533,6 @@ bool AMDGPULegalizerInfo::legalizeBufferAtomic(MachineInstr &MI, MachineIRBuilder &B, Intrinsic::ID IID) const { - B.setInstr(MI); - const bool IsCmpSwap = IID == Intrinsic::amdgcn_raw_buffer_atomic_cmpswap || IID == Intrinsic::amdgcn_struct_buffer_atomic_cmpswap; @@ -3733,7 +3688,6 @@ MachineInstr &MI, MachineIRBuilder &B, GISelChangeObserver &Observer, const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr) const { - B.setInstr(MI); const int NumDefs = MI.getNumExplicitDefs(); bool IsTFE = NumDefs == 2; @@ -3913,8 +3867,6 @@ if (!Ty.isVector() || Ty.getElementType() != S16) return true; - B.setInstr(MI); - Register RepackedReg = handleD16VData(B, *MRI, VData); if (RepackedReg != VData) { MI.getOperand(1).setReg(RepackedReg); @@ -4118,7 +4070,6 @@ // out this needs to be converted to a vector load during RegBankSelect. if (!isPowerOf2_32(Size)) { LegalizerHelper Helper(MF, *this, Observer, B); - B.setInstr(MI); if (Ty.isVector()) Helper.moreElementsVectorDst(MI, getPow2VectorType(Ty), 0); @@ -4133,8 +4084,6 @@ bool AMDGPULegalizerInfo::legalizeTrapIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const { - B.setInstr(MI); - // Is non-HSA path or trap-handler disabled? then, insert s_endpgm instruction if (ST.getTrapHandlerAbi() != GCNSubtarget::TrapHandlerAbiHsa || !ST.isTrapHandlerEnabled()) { @@ -4165,8 +4114,6 @@ bool AMDGPULegalizerInfo::legalizeDebugTrapIntrinsic( MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const { - B.setInstr(MI); - // Is non-HSA path or trap-handler disabled? then, report a warning // accordingly if (ST.getTrapHandlerAbi() != GCNSubtarget::TrapHandlerAbiHsa || @@ -4201,7 +4148,6 @@ const SIRegisterInfo *TRI = static_cast(MRI.getTargetRegisterInfo()); - B.setInstr(*BrCond); Register Def = MI.getOperand(1).getReg(); Register Use = MI.getOperand(3).getReg(); @@ -4244,8 +4190,6 @@ const SIRegisterInfo *TRI = static_cast(MRI.getTargetRegisterInfo()); - B.setInstr(*BrCond); - MachineBasicBlock *CondBrTarget = BrCond->getOperand(1).getMBB(); Register Reg = MI.getOperand(2).getReg(); B.buildInstr(AMDGPU::SI_LOOP) @@ -4267,7 +4211,6 @@ } case Intrinsic::amdgcn_kernarg_segment_ptr: if (!AMDGPU::isKernel(B.getMF().getFunction().getCallingConv())) { - B.setInstr(MI); // This only makes sense to call in a kernel, so just lower to null. B.buildConstant(MI.getOperand(0).getReg(), 0); MI.eraseFromParent(); @@ -4315,7 +4258,6 @@ case Intrinsic::amdgcn_is_private: return legalizeIsAddrSpace(MI, MRI, B, AMDGPUAS::PRIVATE_ADDRESS); case Intrinsic::amdgcn_wavefrontsize: { - B.setInstr(MI); B.buildConstant(MI.getOperand(0), ST.getWavefrontSize()); MI.eraseFromParent(); return true; Index: llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp +++ llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp @@ -2209,7 +2209,8 @@ break; const LLT S32 = LLT::scalar(32); - MachineFunction *MF = MI.getParent()->getParent(); + MachineBasicBlock *MBB = MI.getParent(); + MachineFunction *MF = MBB->getParent(); MachineIRBuilder B(MI); ApplyRegBankMapping ApplySALU(*this, MRI, &AMDGPU::SGPRRegBank); GISelObserverWrapper Observer(&ApplySALU); @@ -2234,9 +2235,10 @@ if (Helper.widenScalar(MI, 0, S32) != LegalizerHelper::Legalized) llvm_unreachable("widen scalar should have succeeded"); - // FIXME: s16 shift amounts should be lgeal. + // FIXME: s16 shift amounts should be legal. if (Opc == AMDGPU::G_SHL || Opc == AMDGPU::G_LSHR || Opc == AMDGPU::G_ASHR) { + B.setInsertPt(*MBB, MI.getIterator()); if (Helper.widenScalar(MI, 1, S32) != LegalizerHelper::Legalized) llvm_unreachable("widen scalar should have succeeded"); } Index: llvm/lib/Target/Mips/MipsLegalizerInfo.cpp =================================================================== --- llvm/lib/Target/Mips/MipsLegalizerInfo.cpp +++ llvm/lib/Target/Mips/MipsLegalizerInfo.cpp @@ -333,7 +333,6 @@ using namespace TargetOpcode; - MIRBuilder.setInstr(MI); const LLT s32 = LLT::scalar(32); const LLT s64 = LLT::scalar(64); @@ -507,7 +506,6 @@ const MipsInstrInfo &TII = *ST.getInstrInfo(); const MipsRegisterInfo &TRI = *ST.getRegisterInfo(); const RegisterBankInfo &RBI = *ST.getRegBankInfo(); - MIRBuilder.setInstr(MI); switch (MI.getIntrinsicID()) { case Intrinsic::memcpy: Index: llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp =================================================================== --- llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp +++ llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp @@ -176,6 +176,8 @@ AInfo Info(MF->getSubtarget()); DummyGISelObserver Observer; LegalizerHelper Helper(*MF, Info, Observer, B); + + B.setInsertPt(*EntryMBB, MIBCTTZ->getIterator()); EXPECT_TRUE(Helper.lower(*MIBCTTZ, 0, LLT::scalar(64)) == LegalizerHelper::LegalizeResult::Legalized); @@ -2583,6 +2585,7 @@ AInfo Info(MF->getSubtarget()); DummyGISelObserver Observer; + B.setInsertPt(*EntryMBB, Load->getIterator()); LegalizerHelper Helper(*MF, Info, Observer, B); EXPECT_EQ(LegalizerHelper::LegalizeResult::Legalized, Helper.bitcast(*Load, 0, S32)); @@ -2618,6 +2621,7 @@ AInfo Info(MF->getSubtarget()); DummyGISelObserver Observer; LegalizerHelper Helper(*MF, Info, Observer, B); + B.setInsertPt(*EntryMBB, Store->getIterator()); EXPECT_EQ(LegalizerHelper::LegalizeResult::Legalized, Helper.bitcast(*Store, 0, S32)); @@ -2651,6 +2655,7 @@ AInfo Info(MF->getSubtarget()); DummyGISelObserver Observer; LegalizerHelper Helper(*MF, Info, Observer, B); + B.setInsertPt(*EntryMBB, Select->getIterator()); EXPECT_EQ(LegalizerHelper::LegalizeResult::Legalized, Helper.bitcast(*Select, 0, S32)); @@ -2669,6 +2674,8 @@ // Doesn't make sense auto VCond = B.buildUndef(LLT::vector(4, 1)); auto VSelect = B.buildSelect(V4S8, VCond, Val0, Val1); + + B.setInsertPt(*EntryMBB, VSelect->getIterator()); EXPECT_EQ(LegalizerHelper::LegalizeResult::UnableToLegalize, Helper.bitcast(*VSelect, 0, S32)); EXPECT_EQ(LegalizerHelper::LegalizeResult::UnableToLegalize, @@ -2694,10 +2701,15 @@ AInfo Info(MF->getSubtarget()); DummyGISelObserver Observer; LegalizerHelper Helper(*MF, Info, Observer, B); + B.setInsertPt(*EntryMBB, And->getIterator()); EXPECT_EQ(LegalizerHelper::LegalizeResult::Legalized, Helper.bitcast(*And, 0, S32)); + + B.setInsertPt(*EntryMBB, Or->getIterator()); EXPECT_EQ(LegalizerHelper::LegalizeResult::Legalized, Helper.bitcast(*Or, 0, S32)); + + B.setInsertPt(*EntryMBB, Xor->getIterator()); EXPECT_EQ(LegalizerHelper::LegalizeResult::Legalized, Helper.bitcast(*Xor, 0, S32)); @@ -2773,12 +2785,20 @@ LegalizerHelper Helper(*MF, Info, Observer, B); // Perform Legalization + + B.setInsertPt(*EntryMBB, Implicit1->getIterator()); EXPECT_EQ(LegalizerHelper::LegalizeResult::Legalized, Helper.narrowScalar(*Implicit1, 0, S48)); + + B.setInsertPt(*EntryMBB, Implicit2->getIterator()); EXPECT_EQ(LegalizerHelper::LegalizeResult::Legalized, Helper.narrowScalar(*Implicit2, 0, S32)); + + B.setInsertPt(*EntryMBB, Implicit3->getIterator()); EXPECT_EQ(LegalizerHelper::LegalizeResult::Legalized, Helper.narrowScalar(*Implicit3, 0, S48)); + + B.setInsertPt(*EntryMBB, Implicit4->getIterator()); EXPECT_EQ(LegalizerHelper::LegalizeResult::Legalized, Helper.narrowScalar(*Implicit4, 0, S32)); @@ -2828,8 +2848,12 @@ LegalizerHelper Helper(*MF, Info, Observer, B); // Perform Legalization + + B.setInsertPt(*EntryMBB, FreezeScalar->getIterator()); EXPECT_EQ(LegalizerHelper::LegalizeResult::Legalized, Helper.widenScalar(*FreezeScalar, 0, S128)); + + B.setInsertPt(*EntryMBB, FreezeVector->getIterator()); EXPECT_EQ(LegalizerHelper::LegalizeResult::Legalized, Helper.widenScalar(*FreezeVector, 0, V2S64)); @@ -2879,12 +2903,20 @@ LegalizerHelper Helper(*MF, Info, Observer, B); // Perform Legalization + + B.setInsertPt(*EntryMBB, FreezeScalar->getIterator()); EXPECT_EQ(LegalizerHelper::LegalizeResult::Legalized, Helper.narrowScalar(*FreezeScalar, 0, S32)); + + B.setInsertPt(*EntryMBB, FreezeOdd->getIterator()); EXPECT_EQ(LegalizerHelper::LegalizeResult::Legalized, Helper.narrowScalar(*FreezeOdd, 0, S32)); + + B.setInsertPt(*EntryMBB, FreezeVector->getIterator()); EXPECT_EQ(LegalizerHelper::LegalizeResult::Legalized, Helper.narrowScalar(*FreezeVector, 0, V2S16)); + + B.setInsertPt(*EntryMBB, FreezeVector1->getIterator()); EXPECT_EQ(LegalizerHelper::LegalizeResult::Legalized, Helper.narrowScalar(*FreezeVector1, 0, S16)); @@ -2954,8 +2986,12 @@ LegalizerHelper Helper(*MF, Info, Observer, B); // Perform Legalization + + B.setInsertPt(*EntryMBB, FreezeVector1->getIterator()); EXPECT_EQ(LegalizerHelper::LegalizeResult::Legalized, Helper.fewerElementsVector(*FreezeVector1, 0, S32)); + + B.setInsertPt(*EntryMBB, FreezeVector2->getIterator()); EXPECT_EQ(LegalizerHelper::LegalizeResult::Legalized, Helper.fewerElementsVector(*FreezeVector2, 0, V2S16)); @@ -2998,6 +3034,7 @@ LegalizerHelper Helper(*MF, Info, Observer, B); // Perform Legalization + B.setInsertPt(*EntryMBB, FreezeVector1->getIterator()); EXPECT_EQ(LegalizerHelper::LegalizeResult::Legalized, Helper.moreElementsVector(*FreezeVector1, 0, V4S32));