[VE] Support floating-point arithmetic instructions in MC layer

[kaz7]

Summary

Add regression tests of asmparser, mccodeemitter, and disassembler for
floating-point arithmetic instructions. Add FADDQ, FSUBQ, FMULQ, and FCMPQ
instructions and F128 register class too.

llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp

static const MCPhysReg F32Regs[64] = {
     VE::SF21, VE::SF22, VE::SF23, VE::SF24, VE::SF25, VE::SF26, VE::SF27,
     VE::SF28, VE::SF29, VE::SF30, VE::SF31, VE::SF32, VE::SF33, VE::SF34,
     VE::SF35, VE::SF36, VE::SF37, VE::SF38, VE::SF39, VE::SF40, VE::SF41,
     VE::SF42, VE::SF43, VE::SF44, VE::SF45, VE::SF46, VE::SF47, VE::SF48,
     VE::SF49, VE::SF50, VE::SF51, VE::SF52, VE::SF53, VE::SF54, VE::SF55,
     VE::SF56, VE::SF57, VE::SF58, VE::SF59, VE::SF60, VE::SF61, VE::SF62,
     VE::SF63};
 
+static const MCPhysReg F128Regs[32] = {
+    VE::Q0,  VE::Q1,  VE::Q2,  VE::Q3,  VE::Q4,  VE::Q5,  VE::Q6,  VE::Q7,
+    VE::Q8,  VE::Q9,  VE::Q10, VE::Q11, VE::Q12, VE::Q13, VE::Q14, VE::Q15,
+    VE::Q16, VE::Q17, VE::Q18, VE::Q19, VE::Q20, VE::Q21, VE::Q22, VE::Q23,
+    VE::Q24, VE::Q25, VE::Q26, VE::Q27, VE::Q28, VE::Q29, VE::Q30, VE::Q31};
+
 static const MCPhysReg MISCRegs[31] = {
     VE::USRCC,      VE::PSW,        VE::SAR,        VE::NoRegister,
     VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::PMMR,
     VE::PMCR0,      VE::PMCR1,      VE::PMCR2,      VE::PMCR3,
     VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::NoRegister,
     VE::PMC0,       VE::PMC1,       VE::PMC2,       VE::PMC3,
     VE::PMC4,       VE::PMC5,       VE::PMC6,       VE::PMC7,
     VE::PMC8,       VE::PMC9,       VE::PMC10,      VE::PMC11,
static bool MorphToF32Reg(VEOperand &Op) {
     unsigned Reg = Op.getReg();
     unsigned regIdx = Reg - VE::SX0;
     if (regIdx > 63)
       return false;
     Op.Reg.RegNum = F32Regs[regIdx];
     return true;
   }
 
+  static bool MorphToF128Reg(VEOperand &Op) {
+    unsigned Reg = Op.getReg();
+    unsigned regIdx = Reg - VE::SX0;
+    if (regIdx % 2 || regIdx > 63)
+      return false;
+    Op.Reg.RegNum = F128Regs[regIdx / 2];
+    return true;
+  }
+
   static bool MorphToMISCReg(VEOperand &Op) {
     const auto *ConstExpr = dyn_cast<MCConstantExpr>(Op.getImm());
     if (!ConstExpr)
       return false;
     unsigned regIdx = ConstExpr->getValue();
     if (regIdx > 31 || MISCRegs[regIdx] == VE::NoRegister)
       return false;
     Op.Kind = k_Register;
unsigned VEAsmParser::validateTargetOperandClass(MCParsedAsmOperand &GOp,
   case MCK_F32:
     if (Op.isReg() && VEOperand::MorphToF32Reg(Op))
       return MCTargetAsmParser::Match_Success;
     break;
   case MCK_I32:
     if (Op.isReg() && VEOperand::MorphToI32Reg(Op))
       return MCTargetAsmParser::Match_Success;
     break;
+  case MCK_F128:
+    if (Op.isReg() && VEOperand::MorphToF128Reg(Op))
+      return MCTargetAsmParser::Match_Success;
+    break;
   case MCK_MISC:
     if (Op.isImm() && VEOperand::MorphToMISCReg(Op))
       return MCTargetAsmParser::Match_Success;
     break;
   }
   return Match_InvalidOperand;
 }

llvm/lib/Target/VE/Disassembler/VEDisassembler.cpp

static const unsigned F32RegDecoderTable[] = {
     VE::SF21, VE::SF22, VE::SF23, VE::SF24, VE::SF25, VE::SF26, VE::SF27,
     VE::SF28, VE::SF29, VE::SF30, VE::SF31, VE::SF32, VE::SF33, VE::SF34,
     VE::SF35, VE::SF36, VE::SF37, VE::SF38, VE::SF39, VE::SF40, VE::SF41,
     VE::SF42, VE::SF43, VE::SF44, VE::SF45, VE::SF46, VE::SF47, VE::SF48,
     VE::SF49, VE::SF50, VE::SF51, VE::SF52, VE::SF53, VE::SF54, VE::SF55,
     VE::SF56, VE::SF57, VE::SF58, VE::SF59, VE::SF60, VE::SF61, VE::SF62,
     VE::SF63};
 
+static const unsigned F128RegDecoderTable[] = {
+    VE::Q0,  VE::Q1,  VE::Q2,  VE::Q3,  VE::Q4,  VE::Q5,  VE::Q6,  VE::Q7,
+    VE::Q8,  VE::Q9,  VE::Q10, VE::Q11, VE::Q12, VE::Q13, VE::Q14, VE::Q15,
+    VE::Q16, VE::Q17, VE::Q18, VE::Q19, VE::Q20, VE::Q21, VE::Q22, VE::Q23,
+    VE::Q24, VE::Q25, VE::Q26, VE::Q27, VE::Q28, VE::Q29, VE::Q30, VE::Q31};
+
 static const unsigned MiscRegDecoderTable[] = {
     VE::USRCC,      VE::PSW,        VE::SAR,        VE::NoRegister,
     VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::PMMR,
     VE::PMCR0,      VE::PMCR1,      VE::PMCR2,      VE::PMCR3,
     VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::NoRegister,
     VE::PMC0,       VE::PMC1,       VE::PMC2,       VE::PMC3,
     VE::PMC4,       VE::PMC5,       VE::PMC6,       VE::PMC7,
     VE::PMC8,       VE::PMC9,       VE::PMC10,      VE::PMC11,
static DecodeStatus DecodeF32RegisterClass(MCInst &Inst, unsigned RegNo,
                                            const void *Decoder) {
   if (RegNo > 63)
     return MCDisassembler::Fail;
   unsigned Reg = F32RegDecoderTable[RegNo];
   Inst.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
+static DecodeStatus DecodeF128RegisterClass(MCInst &Inst, unsigned RegNo,
+                                            uint64_t Address,
+                                            const void *Decoder) {
+  if (RegNo % 2 || RegNo > 63)
+    return MCDisassembler::Fail;
+  unsigned Reg = F128RegDecoderTable[RegNo / 2];
+  Inst.addOperand(MCOperand::createReg(Reg));
+  return MCDisassembler::Success;
+}
+
 static DecodeStatus DecodeMISCRegisterClass(MCInst &Inst, unsigned RegNo,
                                             uint64_t Address,
                                             const void *Decoder) {
   if (RegNo > 30)
     return MCDisassembler::Fail;
   unsigned Reg = MiscRegDecoderTable[RegNo];
   if (Reg == VE::NoRegister)
     return MCDisassembler::Fail;

llvm/lib/Target/VE/VEInstrInfo.td

def mimm : Operand<i32>, PatLeaf<(imm), [{
   let ParserMatchClass = MImmAsmOperand;
   let PrintMethod = "printMImmOperand";
 }
 
 // simm7fp - Generic fp immediate value.
 def simm7fp : Operand<i32>, PatLeaf<(fpimm), [{
     return isInt<7>(getFpImmVal(N));
   }], LO7FP> {
+  let ParserMatchClass = SImm7AsmOperand;
   let DecoderMethod = "DecodeSIMM7";
 }
 
 // mimmfp - Special fp immediate value of sequential bit stream of 0 or 1.
 def mimmfp : Operand<i32>, PatLeaf<(fpimm), [{
     return isMImmVal(getFpImmVal(N)); }], MIMMFP> {
+  let ParserMatchClass = MImmAsmOperand;
   let PrintMethod = "printMImmOperand";
 }
 
 // mimmfp32 - 32 bit width mimmfp
 //   Float value places at higher bits, so ignore lower 32 bits.
 def mimmfp32 : Operand<i32>, PatLeaf<(fpimm), [{
     return isMImm32Val(getFpImmVal(N) >> 32); }], MIMMFP> {
+  let ParserMatchClass = MImmAsmOperand;
   let PrintMethod = "printMImmOperand";
 }
 
 // other generic patterns to use in pattern matchings
 def simm32      : PatLeaf<(imm), [{ return isInt<32>(N->getSExtValue()); }]>;
 def uimm32      : PatLeaf<(imm), [{ return isUInt<32>(N->getZExtValue()); }]>;
 def lomsbzero   : PatLeaf<(imm), [{ return (N->getZExtValue() & 0x80000000)
                                       == 0; }]>;

 let cw = 0, cx = 1 in
 defm FMAXS : RRFm<"fmax.s", 0x3E, F32, f32, fmaxnum, simm7fp, mimmfp32>;
 let cw = 1, cx = 0 in
 defm FMIND : RRFm<"fmin.d", 0x3E, I64, f64, fminnum>;
 let cw = 1, cx = 1 in
 defm FMINS : RRFm<"fmin.s", 0x3E, F32, f32, fminnum, simm7fp, mimmfp32>;
 
 // Section 8.7.7 - FAQ (Floating Add Quadruple)
+defm FADDQ : RRFm<"fadd.q", 0x6C, F128, f128>;
+
 // Section 8.7.8 - FSQ (Floating Subtract Quadruple)
+defm FSUBQ : RRFm<"fsub.q", 0x7C, F128, f128>;
+
 // Section 8.7.9 - FMQ (Floating Subtract Quadruple)
+defm FMULQ : RRFm<"fmul.q", 0x6D, F128, f128>;
+
 // Section 8.7.10 - FCQ (Floating Compare Quadruple)
+defm FCMPQ : RRNCbm<"fcmp.q", 0x7D, I64, f64, F128, f128, null_frag, simm7fp,
+                    mimmfp>;
 
 // Section 8.7.11 - FIX (Convert to Fixed Point)
 // cx: double/float, cw: sx/zx, sz{0-3} = round
 let cx = 0, cw = 0 /* sign extend */ in
 defm CVTWDSX : CVTRDm<"cvt.w.d.sx", 0x4E, I32, i32, I64, f64>;
 let cx = 0, cw = 1 /* zero extend */ in
 defm CVTWDZX : CVTRDm<"cvt.w.d.zx", 0x4E, I32, i32, I64, f64>;
 let cx = 1, cw = 0 /* sign extend */ in

llvm/lib/Target/VE/VERegisterInfo.td

class VEMiscReg<bits<6> enc, string n>: Register<n> {
   let Namespace = "VE";
 }
 
 let Namespace = "VE" in {
   def sub_i8      : SubRegIndex<8, 56>;         // Low 8 bit (56..63)
   def sub_i16     : SubRegIndex<16, 48>;        // Low 16 bit (48..63)
   def sub_i32     : SubRegIndex<32, 32>;        // Low 32 bit (32..63)
   def sub_f32     : SubRegIndex<32>;            // High 32 bit (0..31)
+  def sub_even    : SubRegIndex<64>;            // High 64 bit (0..63)
+  def sub_odd     : SubRegIndex<64, 64>;        // Low 64 bit (64..127)
   def AsmName     : RegAltNameIndex;
 }
 
 //-----------------------------------------------------------------------------
 // Miscellaneous Registers
 //-----------------------------------------------------------------------------
 
 def USRCC : VEMiscReg<0, "usrcc">;      // User clock counter
def SF#I : VEReg<I, "sf"#I, [], ["s"#I], [!cast<VEReg>("SW"#I)]>,
                    DwarfRegNum<[I]>;
 
 // Generic integer registers - 64 bits wide
 let SubRegIndices = [sub_i32, sub_f32], CoveredBySubRegs = 1 in
 foreach I = 0-63 in
   def SX#I : VEReg<I, "s"#I, [!cast<VEReg>("SW"#I), !cast<VEReg>("SF"#I)],
                    ["s"#I]>, DwarfRegNum<[I]>;
 
+// Aliases of the S* registers used to hold 128-bit for values (long doubles).
+// Following foreach represents something like:
+//   def Q0 : VEReg<0, "q0", [SX0, SX1], ["s0"]>;
+//   def Q1 : VEReg<2, "q2", [SX2, SX3], ["s2"]>;
+//   ...
+let SubRegIndices = [sub_even, sub_odd], CoveredBySubRegs = 1 in
+foreach I = 0-31 in
+  def Q#I : VEReg<!shl(I,1), "q"#I,
+                  [!cast<VEReg>("SX"#!shl(I,1)),
+                   !cast<VEReg>("SX"#!add(!shl(I,1),1))],
+                  ["s"#!shl(I,1)]>;
+
 } // RegAltNameIndices = [AsmName]
 
 // Register classes.
 //
 // The register order is defined in terms of the preferred
 // allocation order.
 def I8  : RegisterClass<"VE", [i8], 8,
                         (add (sequence "SB%u", 0, 7),

 def I64 : RegisterClass<"VE", [i64, f64], 64,
                         (add (sequence "SX%u", 0, 7),
                              (sequence "SX%u", 34, 63),
                              (sequence "SX%u", 8, 33))>;
 def F32 : RegisterClass<"VE", [f32], 32,
                         (add (sequence "SF%u", 0, 7),
                              (sequence "SF%u", 34, 63),
                              (sequence "SF%u", 8, 33))>;
+def F128 : RegisterClass<"VE", [f128], 128,
+                        (add (sequence "Q%u", 0, 3),
+                             (sequence "Q%u", 17, 31),
+                             (sequence "Q%u", 4, 16))>;

llvm/test/MC/VE/FADD.s

+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: fadd.d %s11, %s20, %s22
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x94,0x0b,0x4c]
+fadd.d %s11, %s20, %s22
+
+# CHECK-INST: fadd.s %s11, 22, %s22
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x16,0x8b,0x4c]
+fadd.s %s11, 22, %s22
+
+# CHECK-INST: fadd.d %s11, 63, (60)1
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x3c,0x3f,0x0b,0x4c]
+fadd.d %s11, 63, (60)1
+
+# CHECK-INST: fadd.s %s11, -64, (22)0
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x56,0x40,0x8b,0x4c]
+fadd.s %s11, -64, (22)0
+
+# CHECK-INST: fadd.q %s12, %s20, %s22
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x94,0x0c,0x6c]
+fadd.q %s12, %s20, %s22

llvm/test/MC/VE/FCMP.s

+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: fcmp.d %s11, %s20, %s22
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x94,0x0b,0x7e]
+fcmp.d %s11, %s20, %s22
+
+# CHECK-INST: fcmp.s %s11, 22, %s22
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x16,0x8b,0x7e]
+fcmp.s %s11, 22, %s22
+
+# CHECK-INST: fcmp.d %s11, 63, (60)1
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x3c,0x3f,0x0b,0x7e]
+fcmp.d %s11, 63, (60)1
+
+# CHECK-INST: fcmp.s %s11, -64, (22)0
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x56,0x40,0x8b,0x7e]
+fcmp.s %s11, -64, (22)0
+
+# CHECK-INST: fcmp.q %s11, %s20, %s22
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x94,0x0b,0x7d]
+fcmp.q %s11, %s20, %s22

llvm/test/MC/VE/FDIV.s

+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: fdiv.d %s11, %s20, %s22
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x94,0x0b,0x5d]
+fdiv.d %s11, %s20, %s22
+
+# CHECK-INST: fdiv.s %s11, 22, %s22
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x16,0x8b,0x5d]
+fdiv.s %s11, 22, %s22
+
+# CHECK-INST: fdiv.d %s11, 63, (60)1
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x3c,0x3f,0x0b,0x5d]
+fdiv.d %s11, 63, (60)1
+
+# CHECK-INST: fdiv.s %s11, -64, (22)0
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x56,0x40,0x8b,0x5d]
+fdiv.s %s11, -64, (22)0

llvm/test/MC/VE/FMAXMIN.s

+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: fmax.d %s11, %s20, %s22
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x94,0x0b,0x3e]
+fmax.d %s11, %s20, %s22
+
+# CHECK-INST: fmax.s %s11, 22, %s22
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x16,0x8b,0x3e]
+fmax.s %s11, 22, %s22
+
+# CHECK-INST: fmin.d %s11, 63, (63)1
+# CHECK-ENCODING: encoding: [0x80,0x00,0x00,0x00,0x3f,0x3f,0x0b,0x3e]
+fmin.d %s11, 63, (63)1
+
+# CHECK-INST: fmin.s %s11, -64, %s22
+# CHECK-ENCODING: encoding: [0x80,0x00,0x00,0x00,0x96,0x40,0x8b,0x3e]
+fmin.s %s11, -64, %s22

llvm/test/MC/VE/FMUL.s

+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: fmul.d %s11, %s20, %s22
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x94,0x0b,0x4d]
+fmul.d %s11, %s20, %s22
+
+# CHECK-INST: fmul.s %s11, 22, %s22
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x16,0x8b,0x4d]
+fmul.s %s11, 22, %s22
+
+# CHECK-INST: fmul.d %s11, 63, (60)1
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x3c,0x3f,0x0b,0x4d]
+fmul.d %s11, 63, (60)1
+
+# CHECK-INST: fmul.s %s11, -64, (22)0
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x56,0x40,0x8b,0x4d]
+fmul.s %s11, -64, (22)0
+
+# CHECK-INST: fmul.q %s12, %s20, %s22
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x94,0x0c,0x6d]
+fmul.q %s12, %s20, %s22

llvm/test/MC/VE/FSUB.s

+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: fsub.d %s11, %s20, %s22
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x94,0x0b,0x5c]
+fsub.d %s11, %s20, %s22
+
+# CHECK-INST: fsub.s %s11, 22, %s22
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x16,0x8b,0x5c]
+fsub.s %s11, 22, %s22
+
+# CHECK-INST: fsub.d %s11, 63, (60)1
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x3c,0x3f,0x0b,0x5c]
+fsub.d %s11, 63, (60)1
+
+# CHECK-INST: fsub.s %s11, -64, (22)0
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x56,0x40,0x8b,0x5c]
+fsub.s %s11, -64, (22)0
+
+# CHECK-INST: fsub.q %s12, %s20, %s22
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x96,0x94,0x0c,0x7c]
+fsub.q %s12, %s20, %s22