diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -16287,8 +16287,7 @@
   SDLoc Loc(N);
 
   // TODO: QPX subtarget is deprecated. No transformation here.
-  if (Subtarget.hasQPX() || !isOperationLegal(ISD::FMA, VT) ||
-      (VT.isVector() && !Subtarget.hasVSX()))
+  if (Subtarget.hasQPX() || !isOperationLegal(ISD::FMA, VT))
     return SDValue();
 
   // Allowing transformation to FNMSUB may change sign of zeroes when ab-c=0
diff --git a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td
--- a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td
@@ -1024,6 +1024,9 @@
           (VMADDFP $vA, $vB,
              (v4i32 (VSLW (v4i32 (V_SETALLONES)), (v4i32 (V_SETALLONES)))))>; 
 
+def : Pat<(PPCfnmsub v4f32:$A, v4f32:$B, v4f32:$C),
+          (VNMSUBFP $A, $B, $C)>;
+
 def : Pat<(int_ppc_altivec_vmaddfp v4f32:$A, v4f32:$B, v4f32:$C),
           (VMADDFP $A, $B, $C)>;
 def : Pat<(int_ppc_altivec_vnmsubfp v4f32:$A, v4f32:$B, v4f32:$C),
diff --git a/llvm/test/CodeGen/PowerPC/fma-negate.ll b/llvm/test/CodeGen/PowerPC/fma-negate.ll
--- a/llvm/test/CodeGen/PowerPC/fma-negate.ll
+++ b/llvm/test/CodeGen/PowerPC/fma-negate.ll
@@ -304,10 +304,7 @@
 ;
 ; NO-VSX-LABEL: test_fast_neg_fma_v4f32:
 ; NO-VSX:       # %bb.0: # %entry
-; NO-VSX-NEXT:    vspltisb 5, -1
-; NO-VSX-NEXT:    vslw 5, 5, 5
-; NO-VSX-NEXT:    vsubfp 2, 5, 2
-; NO-VSX-NEXT:    vmaddfp 2, 2, 3, 4
+; NO-VSX-NEXT:    vnmsubfp 2, 2, 3, 4
 ; NO-VSX-NEXT:    blr
                                             <4 x float> %c) {
 entry:
diff --git a/llvm/test/CodeGen/PowerPC/recipest.ll b/llvm/test/CodeGen/PowerPC/recipest.ll
--- a/llvm/test/CodeGen/PowerPC/recipest.ll
+++ b/llvm/test/CodeGen/PowerPC/recipest.ll
@@ -679,12 +679,9 @@
 ; CHECK-P7:       # %bb.0:
 ; CHECK-P7-NEXT:    vspltisw 4, -1
 ; CHECK-P7-NEXT:    vrefp 5, 3
-; CHECK-P7-NEXT:    vspltisb 0, -1
-; CHECK-P7-NEXT:    vslw 0, 0, 0
 ; CHECK-P7-NEXT:    vslw 4, 4, 4
-; CHECK-P7-NEXT:    vsubfp 3, 0, 3
 ; CHECK-P7-NEXT:    vmaddfp 4, 2, 5, 4
-; CHECK-P7-NEXT:    vmaddfp 2, 3, 4, 2
+; CHECK-P7-NEXT:    vnmsubfp 2, 3, 4, 2
 ; CHECK-P7-NEXT:    vmaddfp 2, 5, 2, 4
 ; CHECK-P7-NEXT:    blr
 ;