diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -10724,6 +10724,7 @@
     return BB;
   }
 
+  case ARM::VMOVDcc:
   case ARM::tMOVCCr_pseudo: {
     // To "insert" a SELECT_CC instruction, we actually have to insert the
     // diamond control-flow pattern.  The incoming instruction knows the
@@ -10761,7 +10762,8 @@
     BB->addSuccessor(copy0MBB);
     BB->addSuccessor(sinkMBB);
 
-    BuildMI(BB, dl, TII->get(ARM::tBcc))
+
+    BuildMI(BB, dl,Subtarget->isThumb()? TII->get(ARM::tBcc): TII->get(ARM::Bcc))
         .addMBB(sinkMBB)
         .addImm(MI.getOperand(3).getImm())
         .addReg(MI.getOperand(4).getReg());
diff --git a/llvm/lib/Target/ARM/ARMInstrVFP.td b/llvm/lib/Target/ARM/ARMInstrVFP.td
--- a/llvm/lib/Target/ARM/ARMInstrVFP.td
+++ b/llvm/lib/Target/ARM/ARMInstrVFP.td
@@ -2320,11 +2320,13 @@
 //
 
 let hasSideEffects = 0 in {
+let usesCustomInserter = 1 in {
 def VMOVDcc  : PseudoInst<(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm, cmovpred:$p),
                     IIC_fpUNA64,
                     [(set (f64 DPR:$Dd),
                           (ARMcmov DPR:$Dn, DPR:$Dm, cmovpred:$p))]>,
                RegConstraint<"$Dn = $Dd">, Requires<[HasFPRegs64]>;
+}
 
 def VMOVScc  : PseudoInst<(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm, cmovpred:$p),
                     IIC_fpUNA32,
diff --git a/llvm/test/CodeGen/ARM/select.ll b/llvm/test/CodeGen/ARM/select.ll
--- a/llvm/test/CodeGen/ARM/select.ll
+++ b/llvm/test/CodeGen/ARM/select.ll
@@ -65,7 +65,7 @@
 ;CHECK: movmi
 ;CHECK: movpl
 ;CHECK-VFP-LABEL: f7:
-;CHECK-VFP: vmovmi
+;CHECK-VFP: vldrmi
     %tmp = fcmp olt double %a, 1.234e+00
     %tmp1 = select i1 %tmp, double -1.000e+00, double %b
     ret double %tmp1
@@ -153,3 +153,19 @@
 }
 
 declare { i32, i1 } @llvm.smul.with.overflow.i32(i32, i32)
+
+@ff = dso_local local_unnamed_addr global double 0x7FEFFFFFFFFFFFFF, align 8
+@xx = dso_local local_unnamed_addr global i32 16777216, align 4
+
+; CHECK-VFP-LABEL: f13:
+define double @f13() {
+; CHECK-VFP: %bb.1
+; CHECK-VFP-NEXT: vadd
+entry:
+  %0 = load double, double* @ff, align 8
+  %1 = load i32, i32* @xx, align 4
+  %cmp = icmp slt i32 %1, 1048576
+  %mul = fmul double %0, 2.000000e+00
+  %spec.select = select i1 %cmp, double %mul, double %0
+  ret double %spec.select
+}