diff --git a/llvm/docs/GlobalISel/GenericOpcode.rst b/llvm/docs/GlobalISel/GenericOpcode.rst --- a/llvm/docs/GlobalISel/GenericOpcode.rst +++ b/llvm/docs/GlobalISel/GenericOpcode.rst @@ -20,7 +20,7 @@ An undefined value. -.. code-block:: none +.. code-block:: llvm-mir-body %0:_(s32) = G_IMPLICIT_DEF @@ -29,7 +29,7 @@ An integer constant. -.. code-block:: none +.. code-block:: llvm-mir-body %0:_(s32) = G_CONSTANT i32 1 @@ -38,7 +38,7 @@ A floating point constant. -.. code-block:: none +.. code-block:: llvm-mir-body %0:_(s32) = G_FCONSTANT float 1.0 @@ -47,7 +47,7 @@ The address of an object in the stack frame. -.. code-block:: none +.. code-block:: llvm-mir-body %1:_(p0) = G_FRAME_INDEX %stack.0.ptr0 @@ -56,7 +56,7 @@ The address of a global value. -.. code-block:: none +.. code-block:: llvm-mir-body %0(p0) = G_GLOBAL_VALUE @var_local @@ -65,7 +65,7 @@ The address of a basic block. -.. code-block:: none +.. code-block:: llvm-mir-body %0:_(p0) = G_BLOCK_ADDR blockaddress(@test_blockaddress, %ir-block.block) @@ -78,7 +78,7 @@ Extend the underlying scalar type of an operation, leaving the high bits unspecified. -.. code-block:: none +.. code-block:: llvm-mir-body %1:_(s32) = G_ANYEXT %0:_(s16) @@ -88,7 +88,7 @@ Sign extend the underlying scalar type of an operation, copying the sign bit into the newly-created space. -.. code-block:: none +.. code-block:: llvm-mir-body %1:_(s32) = G_SEXT %0:_(s16) @@ -104,7 +104,7 @@ able to make decisions on whether it's better to hang on to the G_SEXT_INREG or to lower it and optimize the individual shifts. -.. code-block:: none +.. code-block:: llvm-mir-body %1:_(s32) = G_SEXT_INREG %0:_(s32), 16 @@ -114,7 +114,7 @@ Zero extend the underlying scalar type of an operation, putting zero bits into the newly-created space. -.. code-block:: none +.. code-block:: llvm-mir-body %1:_(s32) = G_ZEXT %0:_(s16) @@ -124,7 +124,7 @@ Truncate the underlying scalar type of an operation. This is equivalent to G_EXTRACT for scalar types, but acts elementwise on vectors. -.. code-block:: none +.. code-block:: llvm-mir-body %1:_(s16) = G_TRUNC %0:_(s32) @@ -136,7 +136,7 @@ Convert an integer to a pointer. -.. code-block:: none +.. code-block:: llvm-mir-body %1:_(p0) = G_INTTOPTR %0:_(s32) @@ -145,7 +145,7 @@ Convert a pointer to an integer. -.. code-block:: none +.. code-block:: llvm-mir-body %1:_(s32) = G_PTRTOINT %0:_(p0) @@ -156,7 +156,7 @@ bits but this is not always the case due a sublety in the definition of the :ref:`LLVM-IR Bitcast Instruction `. -.. code-block:: none +.. code-block:: llvm-mir-body %1:_(s64) = G_BITCAST %0:_(<2 x s32>) @@ -165,7 +165,7 @@ Convert a pointer to an address space to a pointer to another address space. -.. code-block:: none +.. code-block:: llvm-mir-body %1:_(p1) = G_ADDRSPACE_CAST %0:_(p0) @@ -195,7 +195,7 @@ Concatenate multiple registers of the same size into a wider register. The input operands are always ordered from lowest bits to highest: -.. code-block:: none +.. code-block:: llvm-mir-body %0:(s32) = G_MERGE_VALUES %bits_0_7:(s8), %bits_8_15:(s8), %bits_16_23:(s8), %bits_24_31:(s8) @@ -208,7 +208,7 @@ register banks have been selected. The output operands are always ordered from lowest bits to highest: -.. code-block:: none +.. code-block:: llvm-mir-body %bits_0_7:(s8), %bits_8_15:(s8), %bits_16_23:(s8), %bits_24_31:(s8) = G_UNMERGE_VALUES %0:(s32) @@ -218,7 +218,7 @@ Reverse the order of the bytes in a scalar. -.. code-block:: none +.. code-block:: llvm-mir-body %1:_(s32) = G_BSWAP %0:_(s32) @@ -227,7 +227,7 @@ Reverse the order of the bits in a scalar. -.. code-block:: none +.. code-block:: llvm-mir-body %1:_(s32) = G_BITREVERSE %0:_(s32) @@ -239,7 +239,7 @@ These each perform their respective integer arithmetic on a scalar. -.. code-block:: none +.. code-block:: llvm-mir-body %2:_(s32) = G_ADD %0:_(s32), %1:_(s32) @@ -248,7 +248,7 @@ Signed and unsigned addition and subtraction with saturation. -.. code-block:: none +.. code-block:: llvm-mir-body %2:_(s32) = G_SADDSAT %0:_(s32), %1:_(s32) @@ -268,7 +268,7 @@ Select between two values depending on a zero/non-zero value. -.. code-block:: none +.. code-block:: llvm-mir-body %5:_(s32) = G_SELECT %4(s1), %6, %2 @@ -278,7 +278,7 @@ Add a scalar offset in addressible units to a pointer. Addressible units are typically bytes but this may vary between targets. -.. code-block:: none +.. code-block:: llvm-mir-body %1:_(p0) = G_PTR_ADD %0:_(p0), %1:_(s32) @@ -292,7 +292,7 @@ Zero the least significant N bits of a pointer. -.. code-block:: none +.. code-block:: llvm-mir-body %1:_(p0) = G_PTR_MASK %0, 3 @@ -301,7 +301,7 @@ Take the minimum/maximum of two values. -.. code-block:: none +.. code-block:: llvm-mir-body %5:_(s32) = G_SMIN %6, %2 @@ -311,7 +311,7 @@ Perform the requested arithmetic and produce a carry output in addition to the normal result. -.. code-block:: none +.. code-block:: llvm-mir-body %3:_(s32), %4:_(s1) = G_UADDO %0, %1 @@ -321,7 +321,7 @@ Perform the requested arithmetic and consume a carry input in addition to the normal input. Also produce a carry output in addition to the normal result. -.. code-block:: none +.. code-block:: llvm-mir-body %4:_(s32), %5:_(s1) = G_UADDE %0, %1, %3:_(s1) @@ -331,7 +331,7 @@ Multiply two numbers at twice the incoming bit width (signed) and return the high half of the result. -.. code-block:: none +.. code-block:: llvm-mir-body %3:_(s32) = G_UMULH %0, %1 @@ -340,7 +340,7 @@ Count leading zeros, trailing zeros, or number of set bits. -.. code-block:: none +.. code-block:: llvm-mir-body %2:_(s33) = G_CTLZ_ZERO_UNDEF %1 %2:_(s33) = G_CTTZ_ZERO_UNDEF %1 @@ -352,7 +352,7 @@ Count leading zeros or trailing zeros. If the value is zero then the result is undefined. -.. code-block:: none +.. code-block:: llvm-mir-body %2:_(s33) = G_CTLZ_ZERO_UNDEF %1 %2:_(s33) = G_CTTZ_ZERO_UNDEF %1 @@ -605,7 +605,7 @@ Implement the φ node in the SSA graph representing the function. -.. code-block:: none +.. code-block:: llvm-mir-body %1(s8) = G_PHI %7(s8), %bb.0, %3(s8), %bb.1 @@ -675,6 +675,6 @@ Dynamically realigns the stack pointer to the specified size and alignment. An alignment value of `0` or `1` mean no specific alignment. -.. code-block:: none +.. code-block:: llvm-mir-body %8:_(p0) = G_DYN_STACKALLOC %7(s64), 32 diff --git a/llvm/docs/GlobalISel/IRTranslator.rst b/llvm/docs/GlobalISel/IRTranslator.rst --- a/llvm/docs/GlobalISel/IRTranslator.rst +++ b/llvm/docs/GlobalISel/IRTranslator.rst @@ -16,7 +16,7 @@ becomes: -.. code-block:: none +.. code-block:: llvm-mir-body %2:_(s32) = G_ADD %0:_(s32), %1:_(s32) diff --git a/llvm/docs/GlobalISel/KnownBits.rst b/llvm/docs/GlobalISel/KnownBits.rst --- a/llvm/docs/GlobalISel/KnownBits.rst +++ b/llvm/docs/GlobalISel/KnownBits.rst @@ -22,7 +22,7 @@ Another example is: -.. code-block:: none +.. code-block:: llvm-mir-body %1:(s32) = G_CONSTANT i32 0xFF0 %2:(s32) = G_AND %0, %1 @@ -32,7 +32,7 @@ We can use the constants and the definition of ``G_AND`` to determine the known bits: -.. code-block:: none +.. code-block:: llvm-mir-body ; %0 = 0x???????? %1:(s32) = G_CONSTANT i32 0xFF0 ; %1 = 0x00000FF0 @@ -42,7 +42,7 @@ and then use this to simplify the expression: -.. code-block:: none +.. code-block:: llvm-mir-body ; %0 = 0x???????? %5:(s32) = G_CONSTANT i32 0x0F0 ; %5 = 0x00000FF0 diff --git a/llvm/docs/MIRLangRef.rst b/llvm/docs/MIRLangRef.rst --- a/llvm/docs/MIRLangRef.rst +++ b/llvm/docs/MIRLangRef.rst @@ -184,7 +184,7 @@ The remaining YAML documents contain the machine functions. This is an example of such YAML document: -.. code-block:: text +.. code-block:: llvm-mir --- name: inc @@ -266,7 +266,7 @@ Example: -.. code-block:: llvm +.. code-block:: llvm-mir-body %bb.0 @@ -279,7 +279,7 @@ Example: -.. code-block:: llvm +.. code-block:: llvm-mir-body %bb.1.then @@ -303,7 +303,7 @@ The example below defines a block that has two successors with branch weights of 32 and 16: -.. code-block:: text +.. code-block:: llvm-mir-body bb.0.entry: successors: %bb.1.then(32), %bb.2.else(16) @@ -316,7 +316,7 @@ The machine basic block's live in registers have to be specified before any of the instructions: -.. code-block:: text +.. code-block:: llvm-mir-body bb.0.entry: liveins: $edi, $esi @@ -358,7 +358,7 @@ below shows an instance of the X86 ``RETQ`` instruction with a single machine operand: -.. code-block:: text +.. code-block:: llvm-mir-body RETQ $eax @@ -367,7 +367,7 @@ below shows an instance of the AArch64 ``LDPXpost`` instruction with three defined register operands: -.. code-block:: text +.. code-block:: llvm-mir-body $sp, $fp, $lr = LDPXpost $sp, 2 @@ -384,11 +384,11 @@ The flag ``frame-setup`` or ``frame-destroy`` can be specified before the instruction's name: -.. code-block:: text +.. code-block:: llvm-mir-body $fp = frame-setup ADDXri $sp, 0, 0 -.. code-block:: text +.. code-block:: llvm-mir-body $x21, $x20 = frame-destroy LDPXi $sp @@ -399,7 +399,7 @@ The syntax for bundled instructions is the following: -.. code-block:: text +.. code-block:: llvm-mir-body BUNDLE implicit-def $r0, implicit-def $r1, implicit $r2 { $r0 = SOME_OP $r2 @@ -429,7 +429,7 @@ The example below shows three X86 physical registers: -.. code-block:: text +.. code-block:: llvm-mir-body $eax $r15 @@ -444,7 +444,7 @@ Example: -.. code-block:: text +.. code-block:: llvm-mir-body %0 @@ -467,7 +467,7 @@ example below shows an instance of the X86 ``MOV32ri`` instruction that has an immediate machine operand ``-42``: -.. code-block:: text +.. code-block:: llvm-mir-body $eax = MOV32ri -42 @@ -496,7 +496,7 @@ value), based on the instruction's opcode and the operand's index the operand will be printed as ``%subreg.sub_32``: -.. code-block:: text +.. code-block:: llvm-mir-body %1:gpr64 = SUBREG_TO_REG 0, %0, %subreg.sub_32 @@ -518,14 +518,14 @@ and a reference to the tied register operand. The full syntax of a register operand is shown below: -.. code-block:: text +.. code-block:: llvm-mir-body [] [ : ] [ (tied-def ) ] This example shows an instance of the X86 ``XOR32rr`` instruction that has 5 register operands with different register flags: -.. code-block:: text +.. code-block:: llvm-mir-body dead $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, implicit-def $al @@ -583,7 +583,7 @@ pseudo instruction that uses the X86 ``sub_8bit`` subregister index to copy 8 lower bits from the 32-bit virtual register 0 to the 8-bit virtual register 1: -.. code-block:: text +.. code-block:: llvm-mir-body %1 = COPY %0:sub_8bit @@ -598,13 +598,13 @@ For example, a CPI with the index 1 and offset 8: -.. code-block:: text +.. code-block:: llvm-mir-body %1:gr64 = MOV64ri %const.1 + 8 For a CPI with the index 0 and offset -12: -.. code-block:: text +.. code-block:: llvm-mir-body %1:gr64 = MOV64ri %const.0 - 12 @@ -630,7 +630,7 @@ Example: -.. code-block:: text +.. code-block:: llvm-mir constants: - id: 0 @@ -649,7 +649,7 @@ The example below shows an instance of the X86 ``MOV64rm`` instruction that has a global value operand named ``G``: -.. code-block:: text +.. code-block:: llvm-mir-body $rax = MOV64rm $rip, 1, _, @G, _ @@ -671,7 +671,7 @@ in the AMDGPU backend. So if we have a target index operand with the index 0 and the offset 8: -.. code-block:: text +.. code-block:: llvm-mir-body $sgpr2 = S_ADD_U32 _, target-index(amdgpu-constdata-start) + 8, implicit-def _, implicit-def _ @@ -680,9 +680,9 @@ A jump-table index operand with the index 0 is printed as following: -.. code-block:: text +.. code-block:: llvm-mir-body - tBR_JTr killed $r0, %jump-table.0 + tBR_JTr $r0, %jump-table.0 A machine jump-table entry contains a list of ``MachineBasicBlocks``. When serializing all the function's jump-table entries, the following format is used: @@ -698,7 +698,7 @@ Example: -.. code-block:: text +.. code-block:: llvm-mir-body jumpTable: kind: inline @@ -717,7 +717,7 @@ Example: -.. code-block:: text +.. code-block:: llvm-mir-body CALL64pcrel32 &__stack_chk_fail, csr_64, implicit $rsp, implicit-def $rsp @@ -744,13 +744,13 @@ The syntax is: -.. code-block:: text +.. code-block:: llvm-mir-body CFI_INSTRUCTION offset $w30, -16 which may be emitted later in the MC layer as: -.. code-block:: text +.. code-block:: llvm-mir-body .cfi_offset w30, -16 @@ -761,7 +761,7 @@ The syntax for the ``returnaddress`` intrinsic is: -.. code-block:: text +.. code-block:: llvm-mir-body $x0 = COPY intrinsic(@llvm.returnaddress) @@ -773,7 +773,7 @@ For an int eq predicate ``ICMP_EQ``, the syntax is: -.. code-block:: text +.. code-block:: llvm-mir-body %2:gpr(s32) = G_ICMP intpred(eq), %0, %1