[RISCV] Improve constant materialization

[luismarques]

Summary

This patch adds several tatics for RISCVMatInt::generateInstSeq to try decompose the constant/immediate to materialize, which can find less costly materialization alternatives for RV64 than what we emit with the generic approach. Some of those tactics depend on each other to be effective. This addresses many of the less-than-optimal materializations in the imm.ll test.

[asb]

Thanks, this is a good improvement. Two thoughts, mainly for discussion rather than blocking issues:

1. I don't want to unreasonably expand the scope of this patch, but I do note that at least the srli transformation may be beneficial on RV32 as well for code size (still two instructions, but more compressible). Did you consider adding this or look at other RVC considerations?

2. Although it has the advantage that mistakes in edge cases etc won't lead to regressions in terms of longer instruction sequences, I'm slightly wary of the "generate and see if it's shorter" approach. Though perhaps this is going to come way down the list on any compile-time profiling vs all the other analyses+transformations being done. Any thoughts on this?

[luismarques]

In D79492#2024394, @asb wrote:

1. I don't want to unreasonably expand the scope of this patch, but I do note that at least the srli transformation may be beneficial on RV32 as well for code size (still two instructions, but more compressible). Did you consider adding this or look at other RVC considerations?
2. Although it has the advantage that mistakes in edge cases etc won't lead to regressions in terms of longer instruction sequences, I'm slightly wary of the "generate and see if it's shorter" approach. Though perhaps this is going to come way down the list on any compile-time profiling vs all the other analyses+transformations being done. Any thoughts on this?

Originally I started by writing the optimizations in terms of "If this condition matches, do this", and I was rather please with the results, as the code was quite straightforward, clean and efficient. I was also trying keep the original structure of the materialization code, and just add those tweaks. But as I started trying to cover the last cases it kept getting hairier and hairier. Since that approach didn't backtrack it was very easy for those tweaks to interfere with each other, or to get ever more convoluted preconditions to avoid doing so. Maybe I was just tired and it shouldn't be that difficult. Eventually I decided to cut my losses and move some of the optimizations to the "give it a try" approach, but the other ones kept interfering, so eventually I ended up moving them all to the try approach. I have several ideas on how this could be improved, which would also address compressibility issues, but I wanted to get this baseline improvement merged.

[lenary]

Alex's concerns about the retry-based algorithm seem reasonable to me, but I have been advocating the approach of "this is an improvement, we can make more improvements later", so I think I still err towards landing this patch.

When it comes to improving the implementation approach here, it would be good to ensure that the overhead of getIntMatCost is also reduced, given it has an inefficient implementation based on materialising and then counting, rather than anything else.

llvm/test/CodeGen/RISCV/add-before-shl.ll

42–44

These have been changed from (shift_left (add X, C) C) to (add (shift_left X, C), C).

This isn't an issue per-se, as the sequences are still the same number of instructions - it's likely due to slight changes in the results of getIntMatCost for these examples, and potentially it means we need to change these test cases to maintain coverage of the shift/add hook (which we can do in a follow-up commit).

Having checked the compression (something I know the cost model does not do), it seems the new code does not compress as well as the old code (the lui a0, 4095 is beyond its capabilities). Again, I think this is something to address in a follow-up commit.

[asb]

I'm in favour of merging a patch that is functionally correct and makes incremental improvements. I'd rather avoid any regression in codesize though if possible. How feasible would it to be to avoid that case? It may be worthwhile leaving some of the materialisation improvements for a follow-up patch in order to land the clear wins now.

llvm/lib/Target/RISCV/Utils/RISCVMatInt.cpp

void generateInstSeq(int64_t Val, bool IsRV64, InstSeq &Res) {
   int ShiftAmount = 12 + findFirstSet((uint64_t)Hi52);
   Hi52 = SignExtend64(Hi52 >> (ShiftAmount - 12), 64 - ShiftAmount);
 
   generateInstSeq(Hi52, IsRV64, Res);
 
   Res.push_back(Inst(RISCV::SLLI, ShiftAmount));
   if (Lo12)
     Res.push_back(Inst(RISCV::ADDI, Lo12));
+
+  // Now that we handled the general case, let's check if we can improve on it
+  // in various ways.
+
+  // Try InstSeq(Val) -> InstSeq(Val - Lo12)+ADDI(Lo12).
+  if (Lo12 != 0 && Res.size() > 2) {
+    int64_t AltVal = Val - Lo12;
+    InstSeq AltRes;
+    generateInstSeq(AltVal, IsRV64, AltRes);
+    if (AltRes.size() + 1 < Res.size()) {
+      Res = AltRes;
+      Res.push_back(Inst(RISCV::ADDI, Lo12));
+    }
+  }
+
+  // Try InstSeq(XXX0*) -> InstSeq(XXX)+SLLI.
+  if ((Val & 1) == 0 && Res.size() > 2) {
+    ShiftAmount = findFirstSet((uint64_t)Val);
+    int64_t AltVal = SignExtend64(Val >> ShiftAmount, 64 - ShiftAmount);
+    if (isInt<20>(AltVal) && !isInt<12>(AltVal)) {
+      assert(ShiftAmount > 12);
+      AltVal = AltVal << 12;
+      ShiftAmount -= 12;
+    }
+    InstSeq AltRes;
+    generateInstSeq(AltVal, IsRV64, AltRes);
+    if (AltRes.size() + 1 < Res.size()) {
+      Res = AltRes;
+      Res.push_back(Inst(RISCV::SLLI, ShiftAmount));
+    }
+  }
+
+  if (Val > 0 && Res.size() > 2) {
+    // Try InstSeq(0*XXX) -> InstSeq(XXX1*)+SRLI.
+    int ShiftAmount = countLeadingZeros((uint64_t)Val);
+    int64_t AltVal = (Val << ShiftAmount) | ((1L << ShiftAmount) - 1);
+    InstSeq AltRes;
+    generateInstSeq(AltVal, IsRV64, AltRes);
+    if (AltRes.size() + 1 < Res.size()) {
+      Res = AltRes;
+      Res.push_back(Inst(RISCV::SRLI, ShiftAmount));
+    }
+
+    // Try InstSeq(0*XXX) -> InstSeq(XXX0*)+SRLI.
+    AltVal = (Val << ShiftAmount);
+    AltRes.clear();
+    generateInstSeq(AltVal, IsRV64, AltRes);
+    if (AltRes.size() + 1 < Res.size()) {
+      Res = AltRes;
+      Res.push_back(Inst(RISCV::SRLI, ShiftAmount));
+    }
+  }
 }
 
 int getIntMatCost(const APInt &Val, unsigned Size, bool IsRV64) {
   int PlatRegSize = IsRV64 ? 64 : 32;
 
   // Split the constant into platform register sized chunks, and calculate cost
   // of each chunk.
   int Cost = 0;

llvm/test/CodeGen/RISCV/add-before-shl.ll

 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    lui a1, 65520
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    srai a0, a0, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: add_large_const:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    lui a1, 1
-; RV64I-NEXT:    addiw a1, a1, -1
-; RV64I-NEXT:    add a0, a0, a1
 ; RV64I-NEXT:    slli a0, a0, 48
+; RV64I-NEXT:    lui a1, 4095
+; RV64I-NEXT:    slli a1, a1, 36
+; RV64I-NEXT:    add a0, a0, a1
 ; RV64I-NEXT:    srai a0, a0, 48
 ; RV64I-NEXT:    ret
   %1 = add i32 %a, 4095
   %2 = shl i32 %1, 16
   %3 = ashr i32 %2, 16
   ret i32 %3
 }
 
 define signext i32 @add_huge_const(i32 signext %a) nounwind {
 ; RV32I-LABEL: add_huge_const:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    lui a1, 524272
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    srai a0, a0, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: add_huge_const:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    lui a1, 8
-; RV64I-NEXT:    addiw a1, a1, -1
-; RV64I-NEXT:    add a0, a0, a1
 ; RV64I-NEXT:    slli a0, a0, 48
+; RV64I-NEXT:    lui a1, 32767
+; RV64I-NEXT:    slli a1, a1, 36
+; RV64I-NEXT:    add a0, a0, a1
 ; RV64I-NEXT:    srai a0, a0, 48
 ; RV64I-NEXT:    ret
   %1 = add i32 %a, 32767
   %2 = shl i32 %1, 16
   %3 = ashr i32 %2, 16
   ret i32 %3
 }
 

llvm/test/CodeGen/RISCV/copysign-casts.ll

 ; RV32I-NEXT:    addi a3, a3, -1
 ; RV32I-NEXT:    and a1, a1, a3
 ; RV32I-NEXT:    or a1, a1, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fold_promote:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a2, zero, -1
-; RV64I-NEXT:    slli a2, a2, 63
-; RV64I-NEXT:    addi a2, a2, -1
+; RV64I-NEXT:    srli a2, a2, 1
 ; RV64I-NEXT:    and a0, a0, a2
 ; RV64I-NEXT:    addi a2, zero, 1
 ; RV64I-NEXT:    slli a2, a2, 31
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    slli a1, a1, 32
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;

llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll

 ; RV32IFD-NEXT:    lui a2, 524288
 ; RV32IFD-NEXT:    addi a2, a2, -1
 ; RV32IFD-NEXT:    and a1, a1, a2
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64I-LABEL: fabs:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a1, zero, -1
-; RV64I-NEXT:    slli a1, a1, 63
-; RV64I-NEXT:    addi a1, a1, -1
+; RV64I-NEXT:    srli a1, a1, 1
 ; RV64I-NEXT:    and a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fabs:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    addi a1, zero, -1
-; RV64IFD-NEXT:    slli a1, a1, 63
-; RV64IFD-NEXT:    addi a1, a1, -1
+; RV64IFD-NEXT:    srli a1, a1, 1
 ; RV64IFD-NEXT:    and a0, a0, a1
 ; RV64IFD-NEXT:    ret
   %1 = call double @llvm.fabs.f64(double %a)
   ret double %1
 }
 
 declare double @llvm.copysign.f64(double, double)
 

 ; RV32IFD-NEXT:    lw a1, 12(sp)
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64I-LABEL: fcopysign_fneg:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    not a1, a1
 ; RV64I-NEXT:    addi a2, zero, -1
-; RV64I-NEXT:    slli a2, a2, 63
-; RV64I-NEXT:    and a1, a1, a2
-; RV64I-NEXT:    addi a2, a2, -1
+; RV64I-NEXT:    slli a3, a2, 63
+; RV64I-NEXT:    and a1, a1, a3
+; RV64I-NEXT:    srli a2, a2, 1
 ; RV64I-NEXT:    and a0, a0, a2
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fcopysign_fneg:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    addi a2, zero, -1
 ; RV64IFD-NEXT:    slli a2, a2, 63

llvm/test/CodeGen/RISCV/double-intrinsics.ll

 ; RV32IFD-NEXT:    lui a2, 524288
 ; RV32IFD-NEXT:    addi a2, a2, -1
 ; RV32IFD-NEXT:    and a1, a1, a2
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fabs_f64:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    addi a1, zero, -1
-; RV64IFD-NEXT:    slli a1, a1, 63
-; RV64IFD-NEXT:    addi a1, a1, -1
+; RV64IFD-NEXT:    srli a1, a1, 1
 ; RV64IFD-NEXT:    and a0, a0, a1
 ; RV64IFD-NEXT:    ret
   %1 = call double @llvm.fabs.f64(double %a)
   ret double %1
 }
 
 declare double @llvm.minnum.f64(double, double)
 

llvm/test/CodeGen/RISCV/double-mem.ll

 ; RV32IFD-NEXT:    fsd ft0, 8(sp)
 ; RV32IFD-NEXT:    lw a0, 8(sp)
 ; RV32IFD-NEXT:    lw a1, 12(sp)
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fld_fsd_constant:
 ; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    lui a1, 56
-; RV64IFD-NEXT:    addiw a1, a1, -1353
-; RV64IFD-NEXT:    slli a1, a1, 14
+; RV64IFD-NEXT:    lui a1, 228023
+; RV64IFD-NEXT:    slli a1, a1, 2
 ; RV64IFD-NEXT:    fld ft0, -273(a1)
 ; RV64IFD-NEXT:    fmv.d.x ft1, a0
 ; RV64IFD-NEXT:    fadd.d ft0, ft1, ft0
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    fsd ft0, -273(a1)
 ; RV64IFD-NEXT:    ret
   %1 = inttoptr i32 3735928559 to double*
   %2 = load volatile double, double* %1

llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll

 ; RV64F-LABEL: bitcast_double_and:
 ; RV64F:       # %bb.0:
 ; RV64F-NEXT:    addi sp, sp, -16
 ; RV64F-NEXT:    sd ra, 8(sp)
 ; RV64F-NEXT:    sd s0, 0(sp)
 ; RV64F-NEXT:    mv s0, a0
 ; RV64F-NEXT:    call __adddf3
 ; RV64F-NEXT:    addi a1, zero, -1
-; RV64F-NEXT:    slli a1, a1, 63
-; RV64F-NEXT:    addi a1, a1, -1
+; RV64F-NEXT:    srli a1, a1, 1
 ; RV64F-NEXT:    and a1, a0, a1
 ; RV64F-NEXT:    mv a0, s0
 ; RV64F-NEXT:    call __adddf3
 ; RV64F-NEXT:    ld s0, 0(sp)
 ; RV64F-NEXT:    ld ra, 8(sp)
 ; RV64F-NEXT:    addi sp, sp, 16
 ; RV64F-NEXT:    ret
 ;

llvm/test/CodeGen/RISCV/float-mem.ll

 ; RV32IF-NEXT:    fmv.w.x ft1, a0
 ; RV32IF-NEXT:    fadd.s ft0, ft1, ft0
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    fsw ft0, -273(a1)
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: flw_fsw_constant:
 ; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    lui a1, 56
-; RV64IF-NEXT:    addiw a1, a1, -1353
-; RV64IF-NEXT:    slli a1, a1, 14
+; RV64IF-NEXT:    lui a1, 228023
+; RV64IF-NEXT:    slli a1, a1, 2
 ; RV64IF-NEXT:    flw ft0, -273(a1)
 ; RV64IF-NEXT:    fmv.w.x ft1, a0
 ; RV64IF-NEXT:    fadd.s ft0, ft1, ft0
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    fsw ft0, -273(a1)
 ; RV64IF-NEXT:    ret
   %1 = inttoptr i32 3735928559 to float*
   %2 = load volatile float, float* %1

llvm/test/CodeGen/RISCV/imm.ll

 ; RV64I-LABEL: imm64_1:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a0, zero, 1
 ; RV64I-NEXT:    slli a0, a0, 31
 ; RV64I-NEXT:    ret
   ret i64 2147483648 ; 0x8000_0000
 }
 
-; TODO: This and similar constants with all 0s in the upper bits and all 1s in
-; the lower bits could be lowered to addi a0, zero, -1 followed by a logical
-; right shift.
 define i64 @imm64_2() nounwind {
 ; RV32I-LABEL: imm64_2:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a0, zero, -1
 ; RV32I-NEXT:    mv a1, zero
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: imm64_2:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi a0, zero, 1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    addi a0, a0, -1
+; RV64I-NEXT:    addi a0, zero, -1
+; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
   ret i64 4294967295 ; 0xFFFF_FFFF
 }
 
 define i64 @imm64_3() nounwind {
 ; RV32I-LABEL: imm64_3:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a1, zero, 1

 ; RV32I-LABEL: imm_left_shifted_lui_1:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a0, 524290
 ; RV32I-NEXT:    mv a1, zero
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: imm_left_shifted_lui_1:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    lui a0, 64
-; RV64I-NEXT:    addiw a0, a0, 1
-; RV64I-NEXT:    slli a0, a0, 13
+; RV64I-NEXT:    lui a0, 262145
+; RV64I-NEXT:    slli a0, a0, 1
 ; RV64I-NEXT:    ret
   ret i64 2147491840 ; 0x8000_2000
 }
 
 define i64 @imm_left_shifted_lui_2() nounwind {
 ; RV32I-LABEL: imm_left_shifted_lui_2:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a0, 4
 ; RV32I-NEXT:    addi a1, zero, 1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: imm_left_shifted_lui_2:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    lui a0, 64
-; RV64I-NEXT:    addiw a0, a0, 1
-; RV64I-NEXT:    slli a0, a0, 14
+; RV64I-NEXT:    lui a0, 262145
+; RV64I-NEXT:    slli a0, a0, 2
 ; RV64I-NEXT:    ret
   ret i64 4294983680 ; 0x1_0000_4000
 }
 
 define i64 @imm_left_shifted_lui_3() nounwind {
 ; RV32I-LABEL: imm_left_shifted_lui_3:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a0, 1
 ; RV32I-NEXT:    addi a1, a0, 1
 ; RV32I-NEXT:    mv a0, zero
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: imm_left_shifted_lui_3:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addiw a0, a0, 1
-; RV64I-NEXT:    slli a0, a0, 32
+; RV64I-NEXT:    lui a0, 4097
+; RV64I-NEXT:    slli a0, a0, 20
 ; RV64I-NEXT:    ret
   ret i64 17596481011712 ; 0x1001_0000_0000
 }
 
 ; Various cases where extraneous ADDIs can be inserted where a (right shifted)
 ; LUI suffices, or where multiple ADDIs can be used instead of a single LUI.
 
 define i64 @imm_right_shifted_lui_1() nounwind {
 ; RV32I-LABEL: imm_right_shifted_lui_1:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a0, 1048575
 ; RV32I-NEXT:    addi a0, a0, 1
 ; RV32I-NEXT:    lui a1, 16
 ; RV32I-NEXT:    addi a1, a1, -1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: imm_right_shifted_lui_1:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi a0, zero, 1
-; RV64I-NEXT:    slli a0, a0, 36
-; RV64I-NEXT:    addi a0, a0, -1
-; RV64I-NEXT:    slli a0, a0, 12
-; RV64I-NEXT:    addi a0, a0, 1
+; RV64I-NEXT:    lui a0, 983056
+; RV64I-NEXT:    srli a0, a0, 16
 ; RV64I-NEXT:    ret
   ret i64 281474976706561 ; 0xFFFF_FFFF_F001
 }
 
 define i64 @imm_right_shifted_lui_2() nounwind {
 ; RV32I-LABEL: imm_right_shifted_lui_2:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a0, 1048575
 ; RV32I-NEXT:    addi a0, a0, 1
 ; RV32I-NEXT:    addi a1, zero, 255
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: imm_right_shifted_lui_2:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    lui a0, 65536
-; RV64I-NEXT:    addiw a0, a0, -1
+; RV64I-NEXT:    lui a0, 1044481
 ; RV64I-NEXT:    slli a0, a0, 12
-; RV64I-NEXT:    addi a0, a0, 1
+; RV64I-NEXT:    srli a0, a0, 24
 ; RV64I-NEXT:    ret
   ret i64 1099511623681 ; 0xFF_FFFF_F001
 }
 
 ; We can materialize the upper bits with a single (shifted) LUI, but that option
 ; can be missed due to the lower bits, which aren't just 1s or just 0s.
 
 define i64 @imm_decoupled_lui_addi() nounwind {
 ; RV32I-LABEL: imm_decoupled_lui_addi:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a0, zero, -3
 ; RV32I-NEXT:    lui a1, 1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: imm_decoupled_lui_addi:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addiw a0, a0, 1
-; RV64I-NEXT:    slli a0, a0, 32
+; RV64I-NEXT:    lui a0, 4097
+; RV64I-NEXT:    slli a0, a0, 20
 ; RV64I-NEXT:    addi a0, a0, -3
 ; RV64I-NEXT:    ret
   ret i64 17596481011709 ; 0x1000_FFFF_FFFD
 }
 
 ; This constant can be materialized for RV64 with LUI+SRLI+XORI.
 
 define i64 @imm_end_xori_1() nounwind {

llvm/test/CodeGen/RISCV/rv64-large-stack.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck %s
 ;
 ; The test case check that RV64 could handle the stack adjustment offset exceed
 ; 32-bit.
 
 define void @foo() nounwind {
 ; CHECK-LABEL: foo:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addi sp, sp, -2032
 ; CHECK-NEXT:    sd ra, 2024(sp)
-; CHECK-NEXT:    lui a0, 95
-; CHECK-NEXT:    addiw a0, a0, 1505
-; CHECK-NEXT:    slli a0, a0, 13
+; CHECK-NEXT:    lui a0, 390625
+; CHECK-NEXT:    slli a0, a0, 1
 ; CHECK-NEXT:    addi a0, a0, -2000
 ; CHECK-NEXT:    sub sp, sp, a0
 ; CHECK-NEXT:    addi a0, sp, 16
 ; CHECK-NEXT:    call baz
-; CHECK-NEXT:    lui a0, 95
-; CHECK-NEXT:    addiw a0, a0, 1505
-; CHECK-NEXT:    slli a0, a0, 13
+; CHECK-NEXT:    lui a0, 390625
+; CHECK-NEXT:    slli a0, a0, 1
 ; CHECK-NEXT:    addi a0, a0, -2000
 ; CHECK-NEXT:    add sp, sp, a0
 ; CHECK-NEXT:    ld ra, 2024(sp)
 ; CHECK-NEXT:    addi sp, sp, 2032
 ; CHECK-NEXT:    ret
 entry:
   %w = alloca [100000000 x { fp128, fp128 }], align 16
   %arraydecay = getelementptr inbounds [100000000 x { fp128, fp128 }], [100000000 x { fp128, fp128 }]* %w, i64 0, i64 0
   call void @baz({ fp128, fp128 }* nonnull %arraydecay)
   ret void
 }
 
 declare void @baz({ fp128, fp128 }*)

llvm/test/CodeGen/RISCV/srem-vector-lkk.ll

 ; RV64IM-NEXT:    mulh a5, a1, a5
 ; RV64IM-NEXT:    add a5, a5, a1
 ; RV64IM-NEXT:    srli a2, a5, 63
 ; RV64IM-NEXT:    srli a5, a5, 6
 ; RV64IM-NEXT:    add a2, a5, a2
 ; RV64IM-NEXT:    addi a5, zero, 95
 ; RV64IM-NEXT:    mul a2, a2, a5
 ; RV64IM-NEXT:    sub a1, a1, a2
-; RV64IM-NEXT:    lui a2, 248
+; RV64IM-NEXT:    lui a2, 777976
 ; RV64IM-NEXT:    addiw a2, a2, -1057
-; RV64IM-NEXT:    slli a2, a2, 15
-; RV64IM-NEXT:    addi a2, a2, -1057
-; RV64IM-NEXT:    slli a2, a2, 15
+; RV64IM-NEXT:    slli a2, a2, 29
+; RV64IM-NEXT:    srli a2, a2, 14
 ; RV64IM-NEXT:    addi a2, a2, -1057
 ; RV64IM-NEXT:    slli a2, a2, 13
 ; RV64IM-NEXT:    addi a2, a2, -265
 ; RV64IM-NEXT:    mulh a2, a4, a2
 ; RV64IM-NEXT:    sub a2, a2, a4
 ; RV64IM-NEXT:    srli a5, a2, 63
 ; RV64IM-NEXT:    srli a2, a2, 6
 ; RV64IM-NEXT:    add a2, a2, a5

llvm/test/CodeGen/RISCV/vararg.ll

 ; LP64-LP64F-LP64D-FPELIM-NEXT:    lui a0, 2049
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    addiw a0, a0, -1147
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    slli a0, a0, 13
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    addi a0, a0, 983
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    slli a0, a0, 14
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    addi a0, a0, 655
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    slli a0, a0, 12
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    addi t0, a0, 1475
-; LP64-LP64F-LP64D-FPELIM-NEXT:    lui a0, 1192
-; LP64-LP64F-LP64D-FPELIM-NEXT:    addiw a0, a0, 381
-; LP64-LP64F-LP64D-FPELIM-NEXT:    slli a0, a0, 12
-; LP64-LP64F-LP64D-FPELIM-NEXT:    addi a6, a0, -2048
+; LP64-LP64F-LP64D-FPELIM-NEXT:    lui a0, 2384
+; LP64-LP64F-LP64D-FPELIM-NEXT:    addiw a0, a0, 761
+; LP64-LP64F-LP64D-FPELIM-NEXT:    slli a6, a0, 11
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    lui a0, 1048248
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    addiw a0, a0, 1311
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    slli a0, a0, 12
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    addi a0, a0, -1147
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    slli a0, a0, 13
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    addi a0, a0, 983
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    slli a0, a0, 15
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    addi a2, a0, 1311

 ; LP64-LP64F-LP64D-WITHFP-NEXT:    lui a0, 2049
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addiw a0, a0, -1147
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    slli a0, a0, 13
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi a0, a0, 983
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    slli a0, a0, 14
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi a0, a0, 655
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    slli a0, a0, 12
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi t0, a0, 1475
-; LP64-LP64F-LP64D-WITHFP-NEXT:    lui a0, 1192
-; LP64-LP64F-LP64D-WITHFP-NEXT:    addiw a0, a0, 381
-; LP64-LP64F-LP64D-WITHFP-NEXT:    slli a0, a0, 12
-; LP64-LP64F-LP64D-WITHFP-NEXT:    addi a6, a0, -2048
+; LP64-LP64F-LP64D-WITHFP-NEXT:    lui a0, 2384
+; LP64-LP64F-LP64D-WITHFP-NEXT:    addiw a0, a0, 761
+; LP64-LP64F-LP64D-WITHFP-NEXT:    slli a6, a0, 11
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    lui a0, 1048248
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addiw a0, a0, 1311
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    slli a0, a0, 12
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi a0, a0, -1147
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    slli a0, a0, 13
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi a0, a0, 983
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    slli a0, a0, 15
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi a2, a0, 1311

llvm/test/MC/RISCV/rv64c-aliases-valid.s

 # CHECK-EXPAND: lui a2, 524288
 li x12, -2147483648
 # CHECK-EXPAND: lui a2, 524288
 li x12, -0x80000000
 
 # CHECK-EXPAND: c.li a2, 1
 # CHECK-EXPAND: c.slli a2, 31
 li x12, 0x80000000
-# CHECK-EXPAND: c.li a2, 1
-# CHECK-EXPAND: c.slli a2, 32
-# CHECK-EXPAND: c.addi a2, -1
+# CHECK-EXPAND: c.li a2, -1
+# CHECK-EXPAND: c.srli a2, 32
 li x12, 0xFFFFFFFF
 
 # CHECK-EXPAND: c.li t0, 1
 # CHECK-EXPAND: c.slli t0, 32
 li t0, 0x100000000
 # CHECK-EXPAND: c.li t1, -1
 # CHECK-EXPAND: c.slli t1, 63
 li t1, 0x8000000000000000

llvm/test/MC/RISCV/rv64i-aliases-valid.s

 # CHECK-EXPAND: lui a2, 524288
 li x12, -2147483648
 # CHECK-EXPAND: lui a2, 524288
 li x12, -0x80000000
 
 # CHECK-EXPAND: addi a2, zero, 1
 # CHECK-EXPAND: slli a2, a2, 31
 li x12, 0x80000000
-# CHECK-EXPAND: addi a2, zero, 1
-# CHECK-EXPAND: slli a2, a2, 32
-# CHECK-EXPAND: addi a2, a2, -1
+# CHECK-EXPAND: addi a2, zero, -1
+# CHECK-EXPAND: srli a2, a2, 32
 li x12, 0xFFFFFFFF
 
 # CHECK-EXPAND: addi t0, zero, 1
 # CHECK-EXPAND: slli t0, t0, 32
 li t0, 0x100000000
 # CHECK-EXPAND: addi t1, zero, -1
 # CHECK-EXPAND: slli t1, t1, 63
 li t1, 0x8000000000000000

 # CHECK-EXPAND: addi t4, t4, -947
 # CHECK-EXPAND: slli t4, t4, 12
 # CHECK-EXPAND: addi t4, t4, 1511
 # CHECK-EXPAND: slli t4, t4, 13
 # CHECK-EXPAND: addi t4, t4, -272
 li t4, 0x123456789abcdef0
 # CHECK-EXPAND: addi t5, zero, -1
 li t5, 0xFFFFFFFFFFFFFFFF
-# CHECK-EXPAND: lui t6, 64
-# CHECK-EXPAND: addiw t6, t6, 1
-# CHECK-EXPAND: slli t6, t6, 13
+# CHECK-EXPAND: lui t6, 262145
+# CHECK-EXPAND: slli t6, t6, 1
 li t6, 0x80002000
-# CHECK-EXPAND: lui t0, 64
-# CHECK-EXPAND: addiw t0, t0, 1
-# CHECK-EXPAND: slli t0, t0, 14
+# CHECK-EXPAND: lui t0, 262145
+# CHECK-EXPAND: slli t0, t0, 2
 li x5, 0x100004000
-# CHECK-EXPAND: lui t1, 1
-# CHECK-EXPAND: addiw t1, t1, 1
-# CHECK-EXPAND: slli t1, t1, 32
+# CHECK-EXPAND: lui t1, 4097
+# CHECK-EXPAND: slli t1, t1, 20
 li x6, 0x100100000000
-# CHECK-EXPAND: addi t2, zero, 1
-# CHECK-EXPAND: slli t2, t2, 36
-# CHECK-EXPAND: addi t2, t2, -1
-# CHECK-EXPAND: slli t2, t2, 12
-# CHECK-EXPAND: addi t2, t2, 1
+# CHECK-EXPAND: lui t2, 983056
+# CHECK-EXPAND: srli t2, t2, 16
 li x7, 0xFFFFFFFFF001
-# CHECK-EXPAND: lui s0, 65536
-# CHECK-EXPAND: addiw s0, s0, -1
+# CHECK-EXPAND: lui s0, 1044481
 # CHECK-EXPAND: slli s0, s0, 12
-# CHECK-EXPAND: addi s0, s0, 1
+# CHECK-EXPAND: srli s0, s0, 24
 li x8, 0xFFFFFFF001
-# CHECK-EXPAND: lui s1, 1
-# CHECK-EXPAND: addiw s1, s1, 1
-# CHECK-EXPAND: slli s1, s1, 32
+# CHECK-EXPAND: lui s1, 4097
+# CHECK-EXPAND: slli s1, s1, 20
 # CHECK-EXPAND: addi s1, s1, -3
 li x9, 0x1000FFFFFFFD
 # CHECK-EXPAND: addi a0, zero, -1
 # CHECK-EXPAND: slli a0, a0, 36
 # CHECK-EXPAND: addi a0, a0, 1
 # CHECK-EXPAND: slli a0, a0, 25
 # CHECK-EXPAND: addi a0, a0, -1
 li x10, 0xE000000001FFFFFF