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Differential D79007

[AArch64] Remove inexistent system register ERXTS_EL1
ClosedPublic

Authored by vhscampos on Apr 28 2020, 7:51 AM.

Details

Reviewers
SjoerdMeijer
DavidSpickett
Commits
rGd3dc4c32afb4: [AArch64] Remove inexistent system register ERXTS_EL1
Summary

AArch64's system register ERXTS_EL1 is present in the backend as a
component of the Arm Reliability, Availability and Serviceability (RAS)
extension. However, it has been removed from the specification before
its final release.

This patch removes the register.

Diff Detail

Event Timeline

vhscampos created this revision.Apr 28 2020, 7:51 AM
Herald added a project: Restricted Project. · View Herald TranscriptApr 28 2020, 7:51 AM
Herald added subscribers: llvm-commits, danielkiss, hiraditya, kristof.beyls. · View Herald Transcript
vhscampos added a reviewer: SjoerdMeijer.Apr 28 2020, 7:56 AM
DavidSpickett accepted this revision.Apr 28 2020, 8:00 AM
DavidSpickett added a subscriber: DavidSpickett.

LGTM, no sign of it in the current armarm.

This revision is now accepted and ready to land.Apr 28 2020, 8:00 AM
Harbormaster completed remote builds in B54967: Diff 260633.Apr 28 2020, 8:34 AM
Closed by commit rGd3dc4c32afb4: [AArch64] Remove inexistent system register ERXTS_EL1 (authored by vhscampos). · Explain WhyApr 29 2020, 9:06 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
1 line
test/
MC/
AArch64/
8 lines
Disassembler/
AArch64/
4 lines

Diff 260936

llvm/lib/Target/AArch64/AArch64SystemOperands.td

Show First 20 Lines • Show All 1,325 Lines • ▼ Show 20 Lines
def : RWSysReg<"PMMIR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b110>; def : RWSysReg<"PMMIR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b110>;
} // FeaturePMU } // FeaturePMU
// v8.4a RAS registers // v8.4a RAS registers
// Op0 Op1 CRn CRm Op2 // Op0 Op1 CRn CRm Op2
let Requires = [{ {AArch64::FeatureRASv8_4} }] in { let Requires = [{ {AArch64::FeatureRASv8_4} }] in {
def : RWSysReg<"ERXPFGCTL_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b101>; def : RWSysReg<"ERXPFGCTL_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b101>;
def : RWSysReg<"ERXPFGCDN_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b110>; def : RWSysReg<"ERXPFGCDN_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b110>;
def : RWSysReg<"ERXTS_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b111>;
def : RWSysReg<"ERXMISC2_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b010>; def : RWSysReg<"ERXMISC2_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b010>;
def : RWSysReg<"ERXMISC3_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b011>; def : RWSysReg<"ERXMISC3_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b011>;
def : ROSysReg<"ERXPFGF_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b100>; def : ROSysReg<"ERXPFGF_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b100>;
} // FeatureRASv8_4 } // FeatureRASv8_4
// v8.4a MPAM registers // v8.4a MPAM registers
// Op0 Op1 CRn CRm Op2 // Op0 Op1 CRn CRm Op2
let Requires = [{ {AArch64::FeatureMPAM} }] in { let Requires = [{ {AArch64::FeatureMPAM} }] in {
▲ Show 20 Lines • Show All 187 Lines • Show Last 20 Lines

llvm/test/MC/AArch64/armv8.4a-ras.s

Show All 19 Lines//CHECK-ERROR: error: expected readable system register
msr ERXPFGCDN_EL1, x0 msr ERXPFGCDN_EL1, x0
mrs x0,ERXPFGCDN_EL1 mrs x0,ERXPFGCDN_EL1
//CHECK: msr ERXPFGCDN_EL1, x0 // encoding: [0xc0,0x54,0x18,0xd5] //CHECK: msr ERXPFGCDN_EL1, x0 // encoding: [0xc0,0x54,0x18,0xd5]
//CHECK: mrs x0, ERXPFGCDN_EL1 // encoding: [0xc0,0x54,0x38,0xd5] //CHECK: mrs x0, ERXPFGCDN_EL1 // encoding: [0xc0,0x54,0x38,0xd5]
//CHECK-ERROR: error: expected writable system register or pstate //CHECK-ERROR: error: expected writable system register or pstate
//CHECK-ERROR: error: expected readable system register //CHECK-ERROR: error: expected readable system register
msr ERXTS_EL1, x0
mrs x0,ERXTS_EL1
//CHECK: msr ERXTS_EL1, x0 // encoding: [0xe0,0x55,0x18,0xd5]
//CHECK: mrs x0, ERXTS_EL1 // encoding: [0xe0,0x55,0x38,0xd5]
//CHECK-ERROR: error: expected writable system register or pstate
//CHECK-ERROR: error: expected readable system register
msr ERXMISC2_EL1, x0 msr ERXMISC2_EL1, x0
mrs x0, ERXMISC2_EL1 mrs x0, ERXMISC2_EL1
//CHECK: msr ERXMISC2_EL1, x0 // encoding: [0x40,0x55,0x18,0xd5] //CHECK: msr ERXMISC2_EL1, x0 // encoding: [0x40,0x55,0x18,0xd5]
//CHECK: mrs x0, ERXMISC2_EL1 // encoding: [0x40,0x55,0x38,0xd5] //CHECK: mrs x0, ERXMISC2_EL1 // encoding: [0x40,0x55,0x38,0xd5]
//CHECK-ERROR: error: expected writable system register or pstate //CHECK-ERROR: error: expected writable system register or pstate
//CHECK-ERROR: error: expected readable system register //CHECK-ERROR: error: expected readable system register
Show All 17 Lines

llvm/test/MC/Disassembler/AArch64/armv8.4a-ras.txt

# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.4a --disassemble < %s | FileCheck %s # RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.4a --disassemble < %s | FileCheck %s
0xa0,0x54,0x18,0xd5 0xa0,0x54,0x18,0xd5
0xa0,0x54,0x38,0xd5 0xa0,0x54,0x38,0xd5
0xc0,0x54,0x18,0xd5 0xc0,0x54,0x18,0xd5
0xc0,0x54,0x38,0xd5 0xc0,0x54,0x38,0xd5
0xe0,0x55,0x18,0xd5
0xe0,0x55,0x38,0xd5
0x80,0x54,0x38,0xd5 0x80,0x54,0x38,0xd5
0x40,0x55,0x18,0xd5 0x40,0x55,0x18,0xd5
0x40,0x55,0x38,0xd5 0x40,0x55,0x38,0xd5
0x60,0x55,0x18,0xd5 0x60,0x55,0x18,0xd5
0x60,0x55,0x38,0xd5 0x60,0x55,0x38,0xd5
#CHECK: msr ERXPFGCTL_EL1, x0 #CHECK: msr ERXPFGCTL_EL1, x0
#CHECK: mrs x0, ERXPFGCTL_EL1 #CHECK: mrs x0, ERXPFGCTL_EL1
#CHECK: msr ERXPFGCDN_EL1, x0 #CHECK: msr ERXPFGCDN_EL1, x0
#CHECK: mrs x0, ERXPFGCDN_EL1 #CHECK: mrs x0, ERXPFGCDN_EL1
#CHECK: msr ERXTS_EL1, x0
#CHECK: mrs x0, ERXTS_EL1
#CHECK: mrs x0, ERXPFGF_EL1 #CHECK: mrs x0, ERXPFGF_EL1
#CHECK: msr ERXMISC2_EL1, x0 #CHECK: msr ERXMISC2_EL1, x0
#CHECK: mrs x0, ERXMISC2_EL1 #CHECK: mrs x0, ERXMISC2_EL1
#CHECK: msr ERXMISC3_EL1, x0 #CHECK: msr ERXMISC3_EL1, x0
#CHECK: mrs x0, ERXMISC3_EL1 #CHECK: mrs x0, ERXMISC3_EL1