diff --git a/llvm/lib/Target/PowerPC/PPCInstrQPX.td b/llvm/lib/Target/PowerPC/PPCInstrQPX.td
--- a/llvm/lib/Target/PowerPC/PPCInstrQPX.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrQPX.td
@@ -167,48 +167,48 @@
 
   // Multiply-add instructions
   def QVFMADD : AForm_1<4, 29,
-                      (outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRB, qfrc:$FRC),
+                      (outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRC, qfrc:$FRB),
                       "qvfmadd $FRT, $FRA, $FRC, $FRB", IIC_FPFused,
                       [(set v4f64:$FRT, (fma v4f64:$FRA, v4f64:$FRC, v4f64:$FRB))]>;
   let isCodeGenOnly = 1 in
     def QVFMADDS : QPXA1_Int<0, 29, "qvfmadds", int_ppc_qpx_qvfmadds>;
   def QVFMADDSs : AForm_1<0, 29,
-                        (outs qsrc:$FRT), (ins qsrc:$FRA, qsrc:$FRB, qsrc:$FRC),
+                        (outs qsrc:$FRT), (ins qsrc:$FRA, qsrc:$FRC, qsrc:$FRB),
                         "qvfmadds $FRT, $FRA, $FRC, $FRB", IIC_FPFused,
                         [(set v4f32:$FRT, (fma v4f32:$FRA, v4f32:$FRC, v4f32:$FRB))]>;
   def QVFNMADD : AForm_1<4, 31,
-                      (outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRB, qfrc:$FRC),
+                      (outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRC, qfrc:$FRB),
                       "qvfnmadd $FRT, $FRA, $FRC, $FRB", IIC_FPFused,
                       [(set v4f64:$FRT, (fneg (fma v4f64:$FRA, v4f64:$FRC,
                                                    v4f64:$FRB)))]>;
   let isCodeGenOnly = 1 in
     def QVFNMADDS : QPXA1_Int<0, 31, "qvfnmadds", int_ppc_qpx_qvfnmadds>;
   def QVFNMADDSs : AForm_1<0, 31,
-                        (outs qsrc:$FRT), (ins qsrc:$FRA, qsrc:$FRB, qsrc:$FRC),
+                        (outs qsrc:$FRT), (ins qsrc:$FRA, qsrc:$FRC, qsrc:$FRB),
                         "qvfnmadds $FRT, $FRA, $FRC, $FRB", IIC_FPFused,
                         [(set v4f32:$FRT, (fneg (fma v4f32:$FRA, v4f32:$FRC,
                                                      v4f32:$FRB)))]>;
   def QVFMSUB : AForm_1<4, 28,
-                      (outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRB, qfrc:$FRC),
+                      (outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRC, qfrc:$FRB),
                       "qvfmsub $FRT, $FRA, $FRC, $FRB", IIC_FPFused,
                       [(set v4f64:$FRT, (fma v4f64:$FRA, v4f64:$FRC,
                                              (fneg v4f64:$FRB)))]>;
   let isCodeGenOnly = 1 in
     def QVFMSUBS : QPXA1_Int<0, 28, "qvfmsubs", int_ppc_qpx_qvfmsubs>;
   def QVFMSUBSs : AForm_1<0, 28,
-                      (outs qsrc:$FRT), (ins qsrc:$FRA, qsrc:$FRB, qsrc:$FRC),
+                      (outs qsrc:$FRT), (ins qsrc:$FRA, qsrc:$FRC, qsrc:$FRB),
                       "qvfmsubs $FRT, $FRA, $FRC, $FRB", IIC_FPFused,
                       [(set v4f32:$FRT, (fma v4f32:$FRA, v4f32:$FRC,
                                              (fneg v4f32:$FRB)))]>;
   def QVFNMSUB : AForm_1<4, 30,
-                      (outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRB, qfrc:$FRC),
+                      (outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRC, qfrc:$FRB),
                       "qvfnmsub $FRT, $FRA, $FRC, $FRB", IIC_FPFused,
                       [(set v4f64:$FRT, (fneg (fma v4f64:$FRA, v4f64:$FRC,
                                               (fneg v4f64:$FRB))))]>;
   let isCodeGenOnly = 1 in
     def QVFNMSUBS : QPXA1_Int<0, 30, "qvfnmsubs", int_ppc_qpx_qvfnmsubs>;
   def QVFNMSUBSs : AForm_1<0, 30,
-                      (outs qsrc:$FRT), (ins qsrc:$FRA, qsrc:$FRB, qsrc:$FRC),
+                      (outs qsrc:$FRT), (ins qsrc:$FRA, qsrc:$FRC, qsrc:$FRB),
                       "qvfnmsubs $FRT, $FRA, $FRC, $FRB", IIC_FPFused,
                       [(set v4f32:$FRT, (fneg (fma v4f32:$FRA, v4f32:$FRC,
                                               (fneg v4f32:$FRB))))]>;
@@ -899,13 +899,13 @@
 
 // Additional QVFNMSUB patterns: -a*c + b == -(a*c - b)
 def : Pat<(fma (fneg v4f64:$A), v4f64:$C, v4f64:$B),
-          (QVFNMSUB $A, $B, $C)>;
+          (QVFNMSUB $A, $C, $B)>;
 def : Pat<(fma v4f64:$A, (fneg v4f64:$C), v4f64:$B),
-          (QVFNMSUB $A, $B, $C)>;
+          (QVFNMSUB $A, $C, $B)>;
 def : Pat<(fma (fneg v4f32:$A), v4f32:$C, v4f32:$B),
-          (QVFNMSUBSs $A, $B, $C)>;
+          (QVFNMSUBSs $A, $C, $B)>;
 def : Pat<(fma v4f32:$A, (fneg v4f32:$C), v4f32:$B),
-          (QVFNMSUBSs $A, $B, $C)>;
+          (QVFNMSUBSs $A, $C, $B)>;
 
 def : Pat<(int_ppc_qpx_qvfmadd v4f64:$A, v4f64:$B, v4f64:$C),
           (QVFMADD $A, $B, $C)>;
diff --git a/llvm/test/CodeGen/PowerPC/qpx-qvfmadd.ll b/llvm/test/CodeGen/PowerPC/qpx-qvfmadd.ll
--- a/llvm/test/CodeGen/PowerPC/qpx-qvfmadd.ll
+++ b/llvm/test/CodeGen/PowerPC/qpx-qvfmadd.ll
@@ -3,7 +3,7 @@
 
 define <2 x double> @test_qvfmadd(<2 x double> %0, <2 x double> %1, <2 x double> %2) {
 ; CHECK: test_qvfmadd
-; CHECK: QVFMADD %2, %0, %1, implicit $rm
+; CHECK: QVFMADD %2, %1, %0, implicit $rm
 ;
   %4 = fmul reassoc nsz <2 x double> %2, %1
   %5 = fadd reassoc nsz <2 x double> %4, %0
@@ -12,7 +12,7 @@
 
 define <4 x float> @test_qvfmadds(<4 x float> %0, <4 x float> %1, <4 x float> %2) {
 ; CHECK: test_qvfmadds
-; CHECK: QVFMADDSs %2, %0, %1, implicit $rm
+; CHECK: QVFMADDSs %2, %1, %0, implicit $rm
 ;
   %4 = fmul reassoc nsz <4 x float> %2, %1
   %5 = fadd reassoc nsz <4 x float> %4, %0
@@ -21,7 +21,7 @@
 
 define <2 x double> @test_qvfnmadd(<2 x double> %0, <2 x double> %1, <2 x double> %2) {
 ; CHECK: test_qvfnmadd
-; CHECK: QVFNMADD %2, %0, %1, implicit $rm
+; CHECK: QVFNMADD %2, %1, %0, implicit $rm
 ;
   %4 = fmul reassoc nsz <2 x double> %2, %1
   %5 = fadd reassoc nsz <2 x double> %4, %0
@@ -31,7 +31,7 @@
 
 define <4 x float> @test_qvfnmadds(<4 x float> %0, <4 x float> %1, <4 x float> %2) {
 ; CHECK: test_qvfnmadds
-; CHECK: QVFNMADDSs %2, %0, %1, implicit $rm
+; CHECK: QVFNMADDSs %2, %1, %0, implicit $rm
 ;
   %4 = fmul reassoc nsz <4 x float> %2, %1
   %5 = fadd reassoc nsz <4 x float> %4, %0
@@ -41,7 +41,7 @@
 
 define <2 x double> @test_qvfmsub(<2 x double> %0, <2 x double> %1, <2 x double> %2) {
 ; CHECK: test_qvfmsub
-; CHECK: QVFMSUB %2, %0, %1, implicit $rm
+; CHECK: QVFMSUB %2, %1, %0, implicit $rm
 ;
   %4 = fmul reassoc nsz <2 x double> %2, %1
   %5 = fsub reassoc nsz <2 x double> %4, %0
@@ -50,7 +50,7 @@
 
 define <4 x float> @test_qvfmsubs(<4 x float> %0, <4 x float> %1, <4 x float> %2) {
 ; CHECK: test_qvfmsubs
-; CHECK: QVFMSUBSs %2, %0, %1, implicit $rm
+; CHECK: QVFMSUBSs %2, %1, %0, implicit $rm
 ;
   %4 = fmul reassoc nsz <4 x float> %2, %1
   %5 = fsub reassoc nsz <4 x float> %4, %0
@@ -59,7 +59,7 @@
 
 define <2 x double> @test_qvfnmsub(<2 x double> %0, <2 x double> %1, <2 x double> %2) {
 ; CHECK: test_qvfnmsub
-; CHECK: QVFNMSUB %2, %0, %1, implicit $rm
+; CHECK: QVFNMSUB %2, %1, %0, implicit $rm
 ;
   %4 = fmul reassoc nsz <2 x double> %2, %1
   %5 = fsub reassoc nsz <2 x double> %4, %0
@@ -69,7 +69,7 @@
 
 define <4 x float> @test_qvfnmsubs(<4 x float> %0, <4 x float> %1, <4 x float> %2) {
 ; CHECK: test_qvfnmsubs
-; CHECK: QVFNMSUBSs %2, %0, %1, implicit $rm
+; CHECK: QVFNMSUBSs %2, %1, %0, implicit $rm
 ;
   %4 = fmul reassoc nsz <4 x float> %2, %1
   %5 = fsub reassoc nsz <4 x float> %4, %0