Index: include/llvm/Object/ELFObjectFile.h =================================================================== --- include/llvm/Object/ELFObjectFile.h +++ include/llvm/Object/ELFObjectFile.h @@ -911,13 +911,22 @@ case ELF::EM_HEXAGON: return Triple::hexagon; case ELF::EM_MIPS: - switch (EF.getHeader()->e_ident[ELF::EI_CLASS]) { - case ELF::ELFCLASS32: + switch (EF.getHeader()->e_flags & ELF::EF_MIPS_ARCH) { + case ELF::EF_MIPS_ARCH_32R6: + case ELF::EF_MIPS_ARCH_32R2: + case ELF::EF_MIPS_ARCH_32: + case ELF::EF_MIPS_ARCH_2: + case ELF::EF_MIPS_ARCH_1: return IsLittleEndian ? Triple::mipsel : Triple::mips; - case ELF::ELFCLASS64: + case ELF::EF_MIPS_ARCH_64R6: + case ELF::EF_MIPS_ARCH_64R2: + case ELF::EF_MIPS_ARCH_64: + case ELF::EF_MIPS_ARCH_5: + case ELF::EF_MIPS_ARCH_4: + case ELF::EF_MIPS_ARCH_3: return IsLittleEndian ? Triple::mips64el : Triple::mips64; default: - report_fatal_error("Invalid ELFCLASS!"); + report_fatal_error("Invalid MIPS ARCH!"); } case ELF::EM_PPC: return Triple::ppc; Index: lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h =================================================================== --- lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h +++ lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h @@ -30,12 +30,12 @@ Triple::OSType OSType; bool IsLittle; // Big or little endian bool Is64Bit; // 32 or 64 bit words - + bool IsN64; // Is ABI n64 public: MipsAsmBackend(const Target &T, Triple::OSType _OSType, bool _isLittle, - bool _is64Bit) + bool _is64Bit, bool _isN64) : MCAsmBackend(), OSType(_OSType), IsLittle(_isLittle), - Is64Bit(_is64Bit) {} + Is64Bit(_is64Bit), IsN64(_isN64) {} MCObjectWriter *createObjectWriter(raw_ostream &OS) const override; Index: lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp =================================================================== --- lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp +++ lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp @@ -15,6 +15,7 @@ #include "MCTargetDesc/MipsFixupKinds.h" #include "MCTargetDesc/MipsAsmBackend.h" #include "MCTargetDesc/MipsMCTargetDesc.h" +#include "MCTargetDesc/MipsABIInfo.h" #include "llvm/MC/MCAsmBackend.h" #include "llvm/MC/MCAssembler.h" #include "llvm/MC/MCContext.h" @@ -157,7 +158,7 @@ MCObjectWriter *MipsAsmBackend::createObjectWriter(raw_ostream &OS) const { return createMipsELFObjectWriter(OS, - MCELFObjectTargetWriter::getOSABI(OSType), IsLittle, Is64Bit); + MCELFObjectTargetWriter::getOSABI(OSType), IsLittle, Is64Bit, IsN64); } // Little-endian fixup data byte ordering: @@ -424,8 +425,9 @@ StringRef TT, StringRef CPU, const MCTargetOptions &Options) { + MipsABIInfo ABI = MipsABIInfo::computeTargetABI(Triple(TT), CPU, Options); return new MipsAsmBackend(T, Triple(TT).getOS(), - /*IsLittle*/true, /*Is64Bit*/false); + /*IsLittle*/true, /*Is64Bit*/false, ABI.IsN64()); } MCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T, @@ -433,8 +435,9 @@ StringRef TT, StringRef CPU, const MCTargetOptions &Options) { + MipsABIInfo ABI = MipsABIInfo::computeTargetABI(Triple(TT), CPU, Options); return new MipsAsmBackend(T, Triple(TT).getOS(), - /*IsLittle*/false, /*Is64Bit*/false); + /*IsLittle*/false, /*Is64Bit*/false, ABI.IsN64()); } MCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T, @@ -442,8 +445,9 @@ StringRef TT, StringRef CPU, const MCTargetOptions &Options) { + MipsABIInfo ABI = MipsABIInfo::computeTargetABI(Triple(TT), CPU, Options); return new MipsAsmBackend(T, Triple(TT).getOS(), - /*IsLittle*/true, /*Is64Bit*/true); + /*IsLittle*/true, /*Is64Bit*/true, ABI.IsN64()); } MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T, @@ -451,6 +455,7 @@ StringRef TT, StringRef CPU, const MCTargetOptions &Options) { + MipsABIInfo ABI = MipsABIInfo::computeTargetABI(Triple(TT), CPU, Options); return new MipsAsmBackend(T, Triple(TT).getOS(), - /*IsLittle*/false, /*Is64Bit*/true); + /*IsLittle*/false, /*Is64Bit*/true, ABI.IsN64()); } Index: lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp =================================================================== --- lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp +++ lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp @@ -265,8 +265,9 @@ MCObjectWriter *llvm::createMipsELFObjectWriter(raw_ostream &OS, uint8_t OSABI, bool IsLittleEndian, - bool Is64Bit) { - MCELFObjectTargetWriter *MOTW = new MipsELFObjectWriter(Is64Bit, OSABI, + bool Is64Bit, + bool IsN64) { + MCELFObjectTargetWriter *MOTW = new MipsELFObjectWriter(IsN64, OSABI, (Is64Bit) ? true : false, IsLittleEndian); return createELFObjectWriter(MOTW, OS, IsLittleEndian); Index: lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h =================================================================== --- lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h +++ lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h @@ -61,7 +61,8 @@ const MCTargetOptions &Options); MCObjectWriter *createMipsELFObjectWriter(raw_ostream &OS, uint8_t OSABI, - bool IsLittleEndian, bool Is64Bit); + bool IsLittleEndian, + bool Is64Bit, bool IsN64); namespace MIPS_MC { StringRef selectMipsCPU(StringRef TT, StringRef CPU); Index: test/MC/Mips/cpsetup.s =================================================================== --- test/MC/Mips/cpsetup.s +++ test/MC/Mips/cpsetup.s @@ -33,9 +33,11 @@ # NXX: sd $gp, 8($sp) # NXX: lui $gp, 0 -# NXX: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_HI16 __cerror +# N64: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_HI16 __cerror +# N23: R_MIPS_GPREL16 __cerror # NXX: addiu $gp, $gp, 0 -# NXX: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_LO16 __cerror +# N64: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_LO16 __cerror +# N32: R_MIPS_GPREL16 __cerror # N32: addu $gp, $gp, $25 # N64: daddu $gp, $gp, $25 @@ -53,9 +55,11 @@ # NXX: move $2, $gp # NXX: lui $gp, 0 -# NXX: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_HI16 __cerror +# N64: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_HI16 __cerror +# N32: R_MIPS_GPREL16 __cerror # NXX: addiu $gp, $gp, 0 -# NXX: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_LO16 __cerror +# N64: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_LO16 __cerror +# N32: R_MIPS_GPREL16 __cerror # N32: addu $gp, $gp, $25 # N64: daddu $gp, $gp, $25 @@ -79,9 +83,11 @@ # NXX: move $2, $gp # NXX: lui $gp, 0 -# NXX: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_HI16 $tmp0 +# N64: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_HI16 $tmp0 +# N32: R_MIPS_GPREL16 $tmp0 # NXX: addiu $gp, $gp, 0 -# NXX: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_LO16 $tmp0 +# N32: R_MIPS_GPREL16 $tmp0 +# N64: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_LO16 $tmp0 # N32: addu $gp, $gp, $25 # N64: daddu $gp, $gp, $25 # NXX: nop Index: test/MC/Mips/mips64r6/relocations.s =================================================================== --- test/MC/Mips/mips64r6/relocations.s +++ test/MC/Mips/mips64r6/relocations.s @@ -48,18 +48,18 @@ # Check that the appropriate relocations were created. #------------------------------------------------------------------------------ # CHECK-ELF: Relocations [ -# CHECK-ELF: 0x0 R_MIPS_PC19_S2 bar 0x0 -# CHECK-ELF: 0x4 R_MIPS_PC16 bar 0x0 -# CHECK-ELF: 0x8 R_MIPS_PC16 bar 0x0 -# CHECK-ELF: 0xC R_MIPS_PC21_S2 bar 0x0 -# CHECK-ELF: 0x10 R_MIPS_PC21_S2 bar 0x0 -# CHECK-ELF: 0x14 R_MIPS_PC26_S2 bar 0x0 -# CHECK-ELF: 0x18 R_MIPS_PC26_S2 bar 0x0 -# CHECK-ELF: 0x1C R_MIPS_PCHI16 bar 0x0 -# CHECK-ELF: 0x20 R_MIPS_PCLO16 bar 0x0 -# CHECK-ELF: 0x24 R_MIPS_PC18_S3 bar 0x0 -# CHECK-ELF: 0x28 R_MIPS_PC19_S2 bar 0x0 -# CHECK-ELF: 0x2C R_MIPS_PC19_S2 bar 0x0 +# CHECK-ELF: 0x0 R_MIPS_PC19_S2/R_MIPS_NONE/R_MIPS_NONE bar 0x0 +# CHECK-ELF: 0x4 R_MIPS_PC16/R_MIPS_NONE/R_MIPS_NONE bar 0x0 +# CHECK-ELF: 0x8 R_MIPS_PC16/R_MIPS_NONE/R_MIPS_NONE bar 0x0 +# CHECK-ELF: 0xC R_MIPS_PC21_S2/R_MIPS_NONE/R_MIPS_NONE bar 0x0 +# CHECK-ELF: 0x10 R_MIPS_PC21_S2/R_MIPS_NONE/R_MIPS_NONE bar 0x0 +# CHECK-ELF: 0x14 R_MIPS_PC26_S2/R_MIPS_NONE/R_MIPS_NONE bar 0x0 +# CHECK-ELF: 0x18 R_MIPS_PC26_S2/R_MIPS_NONE/R_MIPS_NONE bar 0x0 +# CHECK-ELF: 0x1C R_MIPS_PCHI16/R_MIPS_NONE/R_MIPS_NONE bar 0x0 +# CHECK-ELF: 0x20 R_MIPS_PCLO16/R_MIPS_NONE/R_MIPS_NONE bar 0x0 +# CHECK-ELF: 0x24 R_MIPS_PC18_S3/R_MIPS_NONE/R_MIPS_NONE bar 0x0 +# CHECK-ELF: 0x28 R_MIPS_PC19_S2/R_MIPS_NONE/R_MIPS_NONE bar 0x0 +# CHECK-ELF: 0x2C R_MIPS_PC19_S2/R_MIPS_NONE/R_MIPS_NONE bar 0x0 # CHECK-ELF: ] addiupc $2,bar