diff --git a/llvm/lib/CodeGen/LiveIntervals.cpp b/llvm/lib/CodeGen/LiveIntervals.cpp
--- a/llvm/lib/CodeGen/LiveIntervals.cpp
+++ b/llvm/lib/CodeGen/LiveIntervals.cpp
@@ -862,6 +862,11 @@
 float LiveIntervals::getSpillWeight(bool isDef, bool isUse,
                                     const MachineBlockFrequencyInfo *MBFI,
                                     const MachineInstr &MI) {
+  // FIXME: Is there place to add the check better than here?
+  // The pass x86-slh attached an post instruction symbol to call instruction.
+  // We don't want its register been spilt out.
+  if (MI.isCall() && MI.getPostInstrSymbol())
+    return huge_valf;
   return getSpillWeight(isDef, isUse, MBFI, MI.getParent());
 }
 
diff --git a/llvm/test/CodeGen/X86/speculative-load-hardening-no-spill.ll b/llvm/test/CodeGen/X86/speculative-load-hardening-no-spill.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/X86/speculative-load-hardening-no-spill.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -x86-speculative-load-hardening | FileCheck %s
+
+define i32 @foo(void ()** %0) {
+; CHECK-LABEL: foo:
+; CHECK:         callq *%rax
+; CHECK-NEXT:  .Lslh_ret_addr0:
+; CHECK-NEXT:    movq %rsp, %rcx
+; CHECK-NEXT:    movq -{{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT:    sarq $63, %rcx
+; CHECK-NEXT:    cmpq $.Lslh_ret_addr0, %rax
+  %2 = load void ()*, void ()** %0
+  call void asm sideeffect "", "~{bx},~{cx},~{dx},~{bp},~{si},~{di},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15},~{dirflag},~{fpsr},~{flags}"()
+  call void %2()
+  ret i32 0
+}