[GIsel][CombinerHelper] Fix for missed ElideBrByInvertingCond/CombineIndexedLoadStore combines [4/10]

[vsk]

Summary

Fix an issue which could result in ElideBrByInvertingCond or
CombineIndexedLoadStore being missed when debug info is present. In both
cases the fix is s/hasOneUse/hasOneNonDbgUse/.

[aemerson]

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

645

This looks like an unrelated fix?

[vsk]

retitle

[vsk]

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

645

Hm, you're right, I don't think it's exercised by the test change. I'll try to find some other way to exercise this.

[vsk]

Add test coverage for change in findPreIndexCandidate. PTAL, thanks.

[aemerson]

LGTM.

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

 #ifndef NDEBUG
   unsigned Opcode = MI.getOpcode();
   assert(Opcode == TargetOpcode::G_LOAD || Opcode == TargetOpcode::G_SEXTLOAD ||
          Opcode == TargetOpcode::G_ZEXTLOAD || Opcode == TargetOpcode::G_STORE);
 #endif
 
   Addr = MI.getOperand(1).getReg();
   MachineInstr *AddrDef = getOpcodeDef(TargetOpcode::G_PTR_ADD, Addr, MRI);
-  if (!AddrDef || MRI.hasOneUse(Addr))
+  if (!AddrDef || MRI.hasOneNonDBGUse(Addr))
     return false;
 
   Base = AddrDef->getOperand(1).getReg();
   Offset = AddrDef->getOperand(2).getReg();
 
   LLVM_DEBUG(dbgs() << "Found potential pre-indexed load_store: " << MI);
 
   if (!ForceLegalIndexing &&
if (BrCond->getOpcode() != TargetOpcode::G_BRCOND)
     return false;
 
   // Check that the next block is the conditional branch target.
   if (!MBB->isLayoutSuccessor(BrCond->getOperand(1).getMBB()))
     return false;
 
   MachineInstr *CmpMI = MRI.getVRegDef(BrCond->getOperand(0).getReg());
   if (!CmpMI || CmpMI->getOpcode() != TargetOpcode::G_ICMP ||
-      !MRI.hasOneUse(CmpMI->getOperand(0).getReg()))
+      !MRI.hasOneNonDBGUse(CmpMI->getOperand(0).getReg()))
     return false;
   return true;
 }
 
 bool CombinerHelper::tryElideBrByInvertingCond(MachineInstr &MI) {
   if (!matchElideBrByInvertingCond(MI))
     return false;
   applyElideBrByInvertingCond(MI);

llvm/test/CodeGen/AArch64/GlobalISel/combiner-load-store-indexing.ll

+; RUN: llc -mtriple=arm64-apple-ios -global-isel -global-isel-abort=1 -verify-machineinstrs -stop-after=aarch64-prelegalizer-combiner -force-legal-indexing %s -o - | FileCheck %s
 ; RUN: llc -debugify-and-strip-all-safe -mtriple=arm64-apple-ios -global-isel -global-isel-abort=1 -verify-machineinstrs -stop-after=aarch64-prelegalizer-combiner -force-legal-indexing %s -o - | FileCheck %s
 
 define i8* @test_simple_load_pre(i8* %ptr) {
 ; CHECK-LABEL: name: test_simple_load_pre
 ; CHECK: [[BASE:%.*]]:_(p0) = COPY $x0
 ; CHECK: [[OFFSET:%.*]]:_(s64) = G_CONSTANT i64 42
 ; CHECK-NOT: G_PTR_ADD
 ; CHECK: {{%.*}}:_(s8), [[NEXT:%.*]]:_(p0) = G_INDEXED_LOAD [[BASE]], [[OFFSET]](s64), 1
 ; CHECK: $x0 = COPY [[NEXT]](p0)
 
   %next = getelementptr i8, i8* %ptr, i32 42
   load volatile i8, i8* %next
   ret i8* %next
 }
 
+define i8* @test_unused_load_pre(i8* %ptr) {
+; CHECK-LABEL: name: test_unused_load_pre
+; CHECK-NOT: G_INDEXED_LOAD
+
+  %next = getelementptr i8, i8* %ptr, i32 42
+  load volatile i8, i8* %next
+  ret i8* null
+}
+
 define void @test_load_multiple_dominated(i8* %ptr, i1 %tst, i1 %tst2) {
 ; CHECK-LABEL: name: test_load_multiple_dominated
 ; CHECK: [[BASE:%.*]]:_(p0) = COPY $x0
 ; CHECK: [[OFFSET:%.*]]:_(s64) = G_CONSTANT i64 42
 ; CHECK-NOT: G_PTR_ADD
 ; CHECK: {{%.*}}:_(s8), [[NEXT:%.*]]:_(p0) = G_INDEXED_LOAD [[BASE]], [[OFFSET]](s64), 1
 ; CHECK: $x0 = COPY [[NEXT]](p0)
   %next = getelementptr i8, i8* %ptr, i32 42

llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-br.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -run-pass=aarch64-prelegalizer-combiner -global-isel -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -debugify-and-strip-all-safe -O0 -run-pass=aarch64-prelegalizer-combiner -global-isel -verify-machineinstrs %s -o - | FileCheck %s
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
   target triple = "arm64-apple-ios5.0.0"
 
   define i32 @foo(i32 %a, i32 %b) {
   entry:
     %cmp = icmp sgt i32 %a, 0
     br i1 %cmp, label %if.then, label %if.end