diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp
--- a/llvm/lib/CodeGen/RegisterCoalescer.cpp
+++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp
@@ -675,6 +675,12 @@
       S.removeSegment(*SS, true);
       continue;
     }
+    // The subrange may have ended before FillerStart. If so, extend it.
+    if (!S.getVNInfoAt(FillerStart)) {
+      SlotIndex BBStart =
+          LIS->getMBBStartIdx(LIS->getMBBFromIndex(FillerStart));
+      S.extendInBlock(BBStart, FillerStart);
+    }
     VNInfo *SubBValNo = S.getVNInfoAt(CopyIdx);
     S.addSegment(LiveInterval::Segment(FillerStart, FillerEnd, SubBValNo));
     VNInfo *SubValSNo = S.getVNInfoAt(AValNo->def.getPrevSlot());
diff --git a/llvm/test/CodeGen/Hexagon/regalloc-coal-extend-short-subrange.mir b/llvm/test/CodeGen/Hexagon/regalloc-coal-extend-short-subrange.mir
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/regalloc-coal-extend-short-subrange.mir
@@ -0,0 +1,97 @@
+# RUN: llc -march=hexagon -run-pass simple-register-coalescing -verify-machineinstrs %s -o - | FileCheck %s
+#
+# Check that this doesn't crash.
+# CHECK: PS_jmpret $r31, implicit-def dead $pc
+
+---
+name: fred
+tracksRegLiveness: true
+liveins:
+  - { reg: '$r1', virtual-reg: '%0' }
+  - { reg: '$v1', virtual-reg: '%1' }
+  - { reg: '$v2', virtual-reg: '%2' }
+  - { reg: '$v3', virtual-reg: '%3' }
+  - { reg: '$v4', virtual-reg: '%4' }
+
+body: |
+  bb.0:
+    successors: %bb.2(0x80000000)
+    liveins: $r1, $v1, $v2, $v3, $v4
+  
+    %4:hvxvr = COPY $v4
+    %3:hvxvr = COPY $v3
+    %2:hvxvr = COPY $v2
+    %1:hvxvr = COPY $v1
+    %0:intregs = COPY $r1
+    %5:hvxvr = V6_vd0
+    %6:hvxwr = PS_vdd0
+    J2_jump %bb.2, implicit-def $pc
+  
+  bb.1:
+    PS_jmpret $r31, implicit-def dead $pc
+  
+  bb.2:
+    successors: %bb.3(0x40000000), %bb.6(0x40000000)
+  
+    %7:hvxvr = V6_vL32b_ai %0, 0
+    %8:hvxwr = COPY %6
+    %8:hvxwr = V6_vmpyhv_acc %8, %7, %7
+    %9:predregs = C2_cmpgtui undef %10:intregs, 1
+    J2_jumpf %9, %bb.6, implicit-def $pc
+    J2_jump %bb.3, implicit-def $pc
+  
+  bb.3:
+    successors: %bb.4(0x40000000), %bb.5(0x40000000)
+  
+    %11:hvxqr = V6_vgtuw %1, %8.vsub_lo
+    %12:hvxvr = COPY %5
+    %12:hvxvr = V6_vaddwq %11, %12, %2
+    %13:hvxqr = V6_vgtuw %6.vsub_hi, %3
+    %14:hvxvr = V6_vL32b_ai %0, 0
+    %15:hvxwr = COPY %8
+    %15:hvxwr = V6_vmpyhv_acc %15, %14, %14
+    %16:predregs = C2_cmpgtui undef %10:intregs, 2
+    %17:intregs = A2_addi undef %10:intregs, -2
+    J2_loop0r %bb.4, %17, implicit-def $lc0, implicit-def $sa0, implicit-def $usr
+    %18:hvxwr = COPY %15
+    %19:hvxwr = COPY %8
+    %20:hvxvr = COPY %12
+    %21:hvxqr = COPY %13
+    J2_jumpf %16, %bb.5, implicit-def $pc
+    J2_jump %bb.4, implicit-def $pc
+  
+  bb.4:
+    successors: %bb.5(0x04000000), %bb.4(0x7c000000)
+  
+    %22:hvxqr = COPY %21
+    %23:hvxvr = COPY %20
+    %24:hvxwr = COPY %18
+    %25:hvxwr = COPY %19
+    %26:hvxwr = COPY %18
+    %27:hvxvr = COPY %23
+    %27:hvxvr = V6_vaddwq %22, %27, %4
+    %28:hvxqr = V6_vgtuw %1, %24.vsub_lo
+    %29:hvxvr = V6_vL32b_ai %0, 0
+    %30:hvxvr = COPY %27
+    %30:hvxvr = V6_vaddwq %28, %30, %2
+    %31:hvxqr = V6_vgtuw %25.vsub_hi, %3
+    %32:hvxwr = COPY %26
+    %33:hvxwr = COPY %32
+    %33:hvxwr = V6_vmpyhv_acc %33, %29, %29
+    %18:hvxwr = COPY %33
+    %19:hvxwr = COPY %26
+    %20:hvxvr = COPY %30
+    %21:hvxqr = COPY %31
+    ENDLOOP0 %bb.4, implicit-def $pc, implicit-def $lc0, implicit $sa0, implicit $lc0
+    J2_jump %bb.5, implicit-def $pc
+  
+  bb.5:
+    successors: %bb.6(0x80000000)
+  
+  
+  bb.6:
+    successors: %bb.1(0x80000000)
+  
+    J2_jump %bb.1, implicit-def $pc
+
+...