[PowerPC] Don't use rldicl when targeting 32bit CPUs

[LemonBoy]

Summary

As reported in the documentation the rldicl instruction should not be used when targeting 32bit CPUs.

Since rldicl is used to clear the upper 32bits of the byteswapped register I've patched the tablegen pattern to avoid emitting it when a 32bit CPU is targeted.

It's my first adventure with TableGen and its DSL so be kind, I also have a few unresolved questions:

• Should the predicate be use64BitRegs instead of In64BitMode ?
• The i64 byteswap is marked as legal but is still expanded, I'd expect that to cause a "failure to select" error but that's not the case. Am I missing something?

[nemanjai]

LGTM. Thanks for fixing this.

llvm/lib/Target/PowerPC/PPCInstrInfo.td

5074

These are the right predicates to use. Using RLDICL in 32-bit mode is at best unnecessary here and at worst not legal.

[LemonBoy]

Can you (or anyone) commit this on my behalf? I don't have commit access.

[MaskRay]

Will commit shortly.

llvm/lib/Target/PowerPC/PPCInstrInfo.td

 def RotateInsertByte3 {
   dag Left = (RLWIMI Rotate.Left3Bytes, Swap4.Bits, 8, 8, 15);
 }
 
 def RotateInsertByte1 {
   dag Left = (RLWIMI RotateInsertByte3.Left, Swap4.Bits, 8, 24, 31);
 }
 
-def : Pat<(i32 (bitreverse i32:$A)),
-  (RLDICL_32 RotateInsertByte1.Left, 0, 32)>;
+// Clear the upper half of the register when in 64-bit mode
+let Predicates = [In64BitMode] in
+def : Pat<(i32 (bitreverse i32:$A)), (RLDICL_32 RotateInsertByte1.Left, 0, 32)>;
+let Predicates = [In32BitMode] in
+def : Pat<(i32 (bitreverse i32:$A)), RotateInsertByte1.Left>;
 
 // Fast 64-bit reverse bits algorithm:
 // Step 1: 1-bit swap (swap odd 1-bit and even 1-bit):
 // n = ((n >> 1) & 0x5555555555555555) | ((n << 1) & 0xAAAAAAAAAAAAAAAA);
 // Step 2: 2-bit swap (swap odd 2-bit and even 2-bit):
 // n = ((n >> 2) & 0x3333333333333333) | ((n << 2) & 0xCCCCCCCCCCCCCCCC);
 // Step 3: 4-bit swap (swap odd 4-bit and even 4-bit):
 // n = ((n >> 4) & 0x0F0F0F0F0F0F0F0F) | ((n << 4) & 0xF0F0F0F0F0F0F0F0);

llvm/test/CodeGen/PowerPC/testBitReverse.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu -mcpu=ppc32 < %s | FileCheck %s --check-prefix=PPC32
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
 declare i32 @llvm.bitreverse.i32(i32)
 define i32 @testBitReverseIntrinsicI32(i32 %arg) {
+; PPC32-LABEL: testBitReverseIntrinsicI32:
+; PPC32:       # %bb.0:
+; PPC32-NEXT:    lis 4, -21846
+; PPC32-NEXT:    ori 4, 4, 43690
+; PPC32-NEXT:    slwi 5, 3, 1
+; PPC32-NEXT:    and 4, 5, 4
+; PPC32-NEXT:    lis 5, 21845
+; PPC32-NEXT:    ori 5, 5, 21845
+; PPC32-NEXT:    srwi 3, 3, 1
+; PPC32-NEXT:    and 3, 3, 5
+; PPC32-NEXT:    lis 5, -13108
+; PPC32-NEXT:    or 3, 3, 4
+; PPC32-NEXT:    ori 5, 5, 52428
+; PPC32-NEXT:    slwi 4, 3, 2
+; PPC32-NEXT:    and 4, 4, 5
+; PPC32-NEXT:    lis 5, 13107
+; PPC32-NEXT:    ori 5, 5, 13107
+; PPC32-NEXT:    srwi 3, 3, 2
+; PPC32-NEXT:    and 3, 3, 5
+; PPC32-NEXT:    lis 5, -3856
+; PPC32-NEXT:    or 3, 3, 4
+; PPC32-NEXT:    ori 5, 5, 61680
+; PPC32-NEXT:    slwi 4, 3, 4
+; PPC32-NEXT:    and 4, 4, 5
+; PPC32-NEXT:    lis 5, 3855
+; PPC32-NEXT:    ori 5, 5, 3855
+; PPC32-NEXT:    srwi 3, 3, 4
+; PPC32-NEXT:    and 3, 3, 5
+; PPC32-NEXT:    or 4, 3, 4
+; PPC32-NEXT:    rotlwi 3, 4, 24
+; PPC32-NEXT:    rlwimi 3, 4, 8, 8, 15
+; PPC32-NEXT:    rlwimi 3, 4, 8, 24, 31
+; PPC32-NEXT:    blr
+;
 ; CHECK-LABEL: testBitReverseIntrinsicI32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lis 4, -21846
 ; CHECK-NEXT:    lis 5, 21845
 ; CHECK-NEXT:    slwi 6, 3, 1
 ; CHECK-NEXT:    srwi 3, 3, 1
 ; CHECK-NEXT:    ori 4, 4, 43690
 ; CHECK-NEXT:    ori 5, 5, 21845

 ; CHECK-NEXT:    rldicl 3, 4, 0, 32
 ; CHECK-NEXT:    blr
   %res = call i32 @llvm.bitreverse.i32(i32 %arg)
   ret i32 %res
 }
 
 declare i64 @llvm.bitreverse.i64(i64)
 define i64 @testBitReverseIntrinsicI64(i64 %arg) {
+; PPC32-LABEL: testBitReverseIntrinsicI64:
+; PPC32:       # %bb.0:
+; PPC32-NEXT:    lis 5, -21846
+; PPC32-NEXT:    lis 6, 21845
+; PPC32-NEXT:    ori 5, 5, 43690
+; PPC32-NEXT:    slwi 10, 4, 1
+; PPC32-NEXT:    slwi 11, 3, 1
+; PPC32-NEXT:    ori 6, 6, 21845
+; PPC32-NEXT:    srwi 4, 4, 1
+; PPC32-NEXT:    srwi 3, 3, 1
+; PPC32-NEXT:    and 10, 10, 5
+; PPC32-NEXT:    and 5, 11, 5
+; PPC32-NEXT:    and 4, 4, 6
+; PPC32-NEXT:    and 3, 3, 6
+; PPC32-NEXT:    lis 7, -13108
+; PPC32-NEXT:    lis 8, 13107
+; PPC32-NEXT:    or 4, 4, 10
+; PPC32-NEXT:    or 3, 3, 5
+; PPC32-NEXT:    ori 7, 7, 52428
+; PPC32-NEXT:    ori 8, 8, 13107
+; PPC32-NEXT:    slwi 5, 4, 2
+; PPC32-NEXT:    srwi 4, 4, 2
+; PPC32-NEXT:    slwi 6, 3, 2
+; PPC32-NEXT:    srwi 3, 3, 2
+; PPC32-NEXT:    and 5, 5, 7
+; PPC32-NEXT:    and 4, 4, 8
+; PPC32-NEXT:    and 6, 6, 7
+; PPC32-NEXT:    and 3, 3, 8
+; PPC32-NEXT:    lis 9, -3856
+; PPC32-NEXT:    lis 11, 3855
+; PPC32-NEXT:    or 4, 4, 5
+; PPC32-NEXT:    or 3, 3, 6
+; PPC32-NEXT:    ori 9, 9, 61680
+; PPC32-NEXT:    ori 11, 11, 3855
+; PPC32-NEXT:    slwi 5, 4, 4
+; PPC32-NEXT:    srwi 4, 4, 4
+; PPC32-NEXT:    slwi 6, 3, 4
+; PPC32-NEXT:    srwi 3, 3, 4
+; PPC32-NEXT:    and 5, 5, 9
+; PPC32-NEXT:    and 4, 4, 11
+; PPC32-NEXT:    and 6, 6, 9
+; PPC32-NEXT:    and 3, 3, 11
+; PPC32-NEXT:    or 5, 4, 5
+; PPC32-NEXT:    or 6, 3, 6
+; PPC32-NEXT:    rotlwi 3, 5, 24
+; PPC32-NEXT:    rotlwi 4, 6, 24
+; PPC32-NEXT:    rlwimi 3, 5, 8, 8, 15
+; PPC32-NEXT:    rlwimi 4, 6, 8, 8, 15
+; PPC32-NEXT:    rlwimi 3, 5, 8, 24, 31
+; PPC32-NEXT:    rlwimi 4, 6, 8, 24, 31
+; PPC32-NEXT:    blr
+;
 ; CHECK-LABEL: testBitReverseIntrinsicI64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lis 4, -21846
 ; CHECK-NEXT:    lis 5, 21845
 ; CHECK-NEXT:    lis 7, -13108
 ; CHECK-NEXT:    lis 8, 13107
 ; CHECK-NEXT:    ori 4, 4, 43690
 ; CHECK-NEXT:    ori 5, 5, 21845