diff --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.h b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.h
--- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.h
+++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.h
@@ -32,6 +32,12 @@
 class RISCVRegisterBankInfo final : public RISCVGenRegisterBankInfo {
 public:
   RISCVRegisterBankInfo(unsigned HwMode);
+
+  const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC,
+                                             LLT Ty) const override;
+
+  const InstructionMapping &
+  getInstrMapping(const MachineInstr &MI) const override;
 };
 } // end namespace llvm
 #endif
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
--- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
@@ -12,6 +12,7 @@
 
 #include "RISCVRegisterBankInfo.h"
 #include "MCTargetDesc/RISCVMCTargetDesc.h"
+#include "RISCVSubtarget.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/RegisterBank.h"
 #include "llvm/CodeGen/RegisterBankInfo.h"
@@ -20,7 +21,134 @@
 #define GET_TARGET_REGBANK_IMPL
 #include "RISCVGenRegisterBank.inc"
 
+namespace llvm {
+namespace RISCV {
+
+RegisterBankInfo::PartialMapping PartMappings[] = {
+    {0, 32, GPRRegBank},
+    {0, 64, GPRRegBank}
+};
+
+enum PartialMappingIdx {
+  PMI_GPR32 = 0,
+  PMI_GPR64 = 1
+};
+
+RegisterBankInfo::ValueMapping ValueMappings[] = {
+    // Invalid value mapping.
+    {nullptr, 0},
+    // Maximum 3 GPR operands; 32 bit.
+    {&PartMappings[PMI_GPR32], 1},
+    {&PartMappings[PMI_GPR32], 1},
+    {&PartMappings[PMI_GPR32], 1},
+    // Maximum 3 GPR operands; 64 bit.
+    {&PartMappings[PMI_GPR64], 1},
+    {&PartMappings[PMI_GPR64], 1},
+    {&PartMappings[PMI_GPR64], 1}
+};
+
+enum ValueMappingsIdx {
+  InvalidIdx = 0,
+  GPR32Idx = 1,
+  GPR64Idx = 4
+};
+} // namespace RISCV
+} // namespace llvm
+
 using namespace llvm;
 
 RISCVRegisterBankInfo::RISCVRegisterBankInfo(unsigned HwMode)
     : RISCVGenRegisterBankInfo(HwMode) {}
+
+const RegisterBank &
+RISCVRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC,
+                                              LLT Ty) const {
+  switch (RC.getID()) {
+  default:
+    llvm_unreachable("Register class not supported");
+  case RISCV::GPRRegClassID:
+  case RISCV::GPRNoX0RegClassID:
+  case RISCV::GPRNoX0X2RegClassID:
+  case RISCV::GPRTCRegClassID:
+  case RISCV::GPRCRegClassID:
+  case RISCV::GPRC_and_GPRTCRegClassID:
+  case RISCV::GPRC_and_SR07RegClassID:
+  case RISCV::GPRX0RegClassID:
+  case RISCV::GPRJALRRegClassID:
+  case RISCV::SPRegClassID:
+  case RISCV::SR07RegClassID:
+    return getRegBank(RISCV::GPRRegBankID);
+  }
+}
+
+const RegisterBankInfo::InstructionMapping &
+RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
+  const unsigned Opc = MI.getOpcode();
+
+  // Try the default logic for non-generic instructions that are either copies
+  // or already have some operands assigned to banks.
+  if (!isPreISelGenericOpcode(Opc) || Opc == TargetOpcode::G_PHI) {
+    const InstructionMapping &Mapping = getInstrMappingImpl(MI);
+    if (Mapping.isValid())
+      return Mapping;
+  }
+
+  const MachineFunction &MF = *MI.getParent()->getParent();
+  bool IsRV64 = MF.getSubtarget<RISCVSubtarget>().is64Bit();
+
+  unsigned NumOperands = MI.getNumOperands();
+  const ValueMapping *GPRValueMapping =
+      &RISCV::ValueMappings[IsRV64 ? RISCV::GPR64Idx : RISCV::GPR32Idx];
+  const ValueMapping *OperandsMapping = GPRValueMapping;
+
+  switch (Opc) {
+  case TargetOpcode::G_ADD:
+  case TargetOpcode::G_SUB:
+  case TargetOpcode::G_SHL:
+  case TargetOpcode::G_ASHR:
+  case TargetOpcode::G_LSHR:
+  case TargetOpcode::G_AND:
+  case TargetOpcode::G_OR:
+  case TargetOpcode::G_XOR:
+  case TargetOpcode::G_MUL:
+  case TargetOpcode::G_SDIV:
+  case TargetOpcode::G_SREM:
+  case TargetOpcode::G_UDIV:
+  case TargetOpcode::G_UREM:
+  case TargetOpcode::G_UMULH:
+  case TargetOpcode::G_PTR_ADD:
+  case TargetOpcode::G_TRUNC:
+  case TargetOpcode::G_ANYEXT:
+  case TargetOpcode::G_SEXT:
+  case TargetOpcode::G_ZEXT:
+  case TargetOpcode::G_LOAD:
+  case TargetOpcode::G_ZEXTLOAD:
+  case TargetOpcode::G_STORE:
+    break;
+  case TargetOpcode::G_CONSTANT:
+  case TargetOpcode::G_GLOBAL_VALUE:
+  case TargetOpcode::G_BRCOND:
+    OperandsMapping = getOperandsMapping({GPRValueMapping, nullptr});
+    break;
+  case TargetOpcode::G_BR:
+    OperandsMapping = getOperandsMapping({nullptr});
+    break;
+  case TargetOpcode::G_ICMP:
+    OperandsMapping = getOperandsMapping(
+        {GPRValueMapping, nullptr, GPRValueMapping, GPRValueMapping});
+    break;
+  case TargetOpcode::G_SEXT_INREG:
+    OperandsMapping =
+        getOperandsMapping({GPRValueMapping, GPRValueMapping, nullptr});
+    break;
+  case TargetOpcode::G_SELECT:
+    OperandsMapping = getOperandsMapping(
+        {GPRValueMapping, GPRValueMapping, GPRValueMapping, GPRValueMapping});
+    break;
+  default:
+    return getInvalidInstructionMapping();
+  }
+
+  return getInstructionMapping(DefaultMappingID, /*Cost=*/1, OperandsMapping,
+                               NumOperands);
+}
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir
@@ -0,0 +1,398 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=riscv32 -mattr=+m -run-pass=regbankselect \
+# RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN:   -o - | FileCheck -check-prefix=RV32I %s
+
+---
+name:            add_i32
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV32I-LABEL: name: add_i32
+    ; RV32I: liveins: $x10, $x11
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
+    ; RV32I-NEXT: [[ADD:%[0-9]+]]:gprb(s32) = G_ADD [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $x10 = COPY [[ADD]](s32)
+    ; RV32I-NEXT: PseudoRET implicit $x10
+    %0:_(s32) = COPY $x10
+    %1:_(s32) = COPY $x11
+    %2:_(s32) = G_ADD %0, %1
+    $x10 = COPY %2(s32)
+    PseudoRET implicit $x10
+
+...
+---
+name:            sub_i32
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV32I-LABEL: name: sub_i32
+    ; RV32I: liveins: $x10, $x11
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
+    ; RV32I-NEXT: [[SUB:%[0-9]+]]:gprb(s32) = G_SUB [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $x10 = COPY [[SUB]](s32)
+    ; RV32I-NEXT: PseudoRET implicit $x10
+    %0:_(s32) = COPY $x10
+    %1:_(s32) = COPY $x11
+    %2:_(s32) = G_SUB %0, %1
+    $x10 = COPY %2(s32)
+    PseudoRET implicit $x10
+
+...
+---
+name:            shl_i32
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV32I-LABEL: name: shl_i32
+    ; RV32I: liveins: $x10, $x11
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
+    ; RV32I-NEXT: [[SHL:%[0-9]+]]:gprb(s32) = G_SHL [[COPY]], [[COPY1]](s32)
+    ; RV32I-NEXT: $x10 = COPY [[SHL]](s32)
+    ; RV32I-NEXT: PseudoRET implicit $x10
+    %0:_(s32) = COPY $x10
+    %1:_(s32) = COPY $x11
+    %2:_(s32) = G_SHL %0, %1
+    $x10 = COPY %2(s32)
+    PseudoRET implicit $x10
+
+...
+---
+name:            ashr_i32
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV32I-LABEL: name: ashr_i32
+    ; RV32I: liveins: $x10, $x11
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
+    ; RV32I-NEXT: [[ASHR:%[0-9]+]]:gprb(s32) = G_ASHR [[COPY]], [[COPY1]](s32)
+    ; RV32I-NEXT: $x10 = COPY [[ASHR]](s32)
+    ; RV32I-NEXT: PseudoRET implicit $x10
+    %0:_(s32) = COPY $x10
+    %1:_(s32) = COPY $x11
+    %2:_(s32) = G_ASHR %0, %1
+    $x10 = COPY %2(s32)
+    PseudoRET implicit $x10
+
+...
+---
+name:            lshr_i32
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV32I-LABEL: name: lshr_i32
+    ; RV32I: liveins: $x10, $x11
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
+    ; RV32I-NEXT: [[LSHR:%[0-9]+]]:gprb(s32) = G_LSHR [[COPY]], [[COPY1]](s32)
+    ; RV32I-NEXT: $x10 = COPY [[LSHR]](s32)
+    ; RV32I-NEXT: PseudoRET implicit $x10
+    %0:_(s32) = COPY $x10
+    %1:_(s32) = COPY $x11
+    %2:_(s32) = G_LSHR %0, %1
+    $x10 = COPY %2(s32)
+    PseudoRET implicit $x10
+
+...
+---
+name:            and_i32
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV32I-LABEL: name: and_i32
+    ; RV32I: liveins: $x10, $x11
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
+    ; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $x10 = COPY [[AND]](s32)
+    ; RV32I-NEXT: PseudoRET implicit $x10
+    %0:_(s32) = COPY $x10
+    %1:_(s32) = COPY $x11
+    %2:_(s32) = G_AND %0, %1
+    $x10 = COPY %2(s32)
+    PseudoRET implicit $x10
+
+...
+---
+name:            or_i32
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV32I-LABEL: name: or_i32
+    ; RV32I: liveins: $x10, $x11
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
+    ; RV32I-NEXT: [[OR:%[0-9]+]]:gprb(s32) = G_OR [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $x10 = COPY [[OR]](s32)
+    ; RV32I-NEXT: PseudoRET implicit $x10
+    %0:_(s32) = COPY $x10
+    %1:_(s32) = COPY $x11
+    %2:_(s32) = G_OR %0, %1
+    $x10 = COPY %2(s32)
+    PseudoRET implicit $x10
+
+...
+---
+name:            xor_i32
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV32I-LABEL: name: xor_i32
+    ; RV32I: liveins: $x10, $x11
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
+    ; RV32I-NEXT: [[XOR:%[0-9]+]]:gprb(s32) = G_XOR [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $x10 = COPY [[XOR]](s32)
+    ; RV32I-NEXT: PseudoRET implicit $x10
+    %0:_(s32) = COPY $x10
+    %1:_(s32) = COPY $x11
+    %2:_(s32) = G_XOR %0, %1
+    $x10 = COPY %2(s32)
+    PseudoRET implicit $x10
+
+...
+---
+name:            mul_i32
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV32I-LABEL: name: mul_i32
+    ; RV32I: liveins: $x10, $x11
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
+    ; RV32I-NEXT: [[MUL:%[0-9]+]]:gprb(s32) = G_MUL [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $x10 = COPY [[MUL]](s32)
+    ; RV32I-NEXT: PseudoRET implicit $x10
+    %0:_(s32) = COPY $x10
+    %1:_(s32) = COPY $x11
+    %2:_(s32) = G_MUL %0, %1
+    $x10 = COPY %2(s32)
+    PseudoRET implicit $x10
+
+...
+---
+name:            sdiv_i32
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV32I-LABEL: name: sdiv_i32
+    ; RV32I: liveins: $x10, $x11
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
+    ; RV32I-NEXT: [[SDIV:%[0-9]+]]:gprb(s32) = G_SDIV [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $x10 = COPY [[SDIV]](s32)
+    ; RV32I-NEXT: PseudoRET implicit $x10
+    %0:_(s32) = COPY $x10
+    %1:_(s32) = COPY $x11
+    %2:_(s32) = G_SDIV %0, %1
+    $x10 = COPY %2(s32)
+    PseudoRET implicit $x10
+
+...
+---
+name:            srem_i32
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV32I-LABEL: name: srem_i32
+    ; RV32I: liveins: $x10, $x11
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
+    ; RV32I-NEXT: [[SREM:%[0-9]+]]:gprb(s32) = G_SREM [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $x10 = COPY [[SREM]](s32)
+    ; RV32I-NEXT: PseudoRET implicit $x10
+    %0:_(s32) = COPY $x10
+    %1:_(s32) = COPY $x11
+    %2:_(s32) = G_SREM %0, %1
+    $x10 = COPY %2(s32)
+    PseudoRET implicit $x10
+
+...
+---
+name:            udiv_i32
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV32I-LABEL: name: udiv_i32
+    ; RV32I: liveins: $x10, $x11
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
+    ; RV32I-NEXT: [[UDIV:%[0-9]+]]:gprb(s32) = G_UDIV [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $x10 = COPY [[UDIV]](s32)
+    ; RV32I-NEXT: PseudoRET implicit $x10
+    %0:_(s32) = COPY $x10
+    %1:_(s32) = COPY $x11
+    %2:_(s32) = G_UDIV %0, %1
+    $x10 = COPY %2(s32)
+    PseudoRET implicit $x10
+
+...
+---
+name:            urem_i32
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV32I-LABEL: name: urem_i32
+    ; RV32I: liveins: $x10, $x11
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
+    ; RV32I-NEXT: [[UREM:%[0-9]+]]:gprb(s32) = G_UREM [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $x10 = COPY [[UREM]](s32)
+    ; RV32I-NEXT: PseudoRET implicit $x10
+    %0:_(s32) = COPY $x10
+    %1:_(s32) = COPY $x11
+    %2:_(s32) = G_UREM %0, %1
+    $x10 = COPY %2(s32)
+    PseudoRET implicit $x10
+
+...
+---
+name:            umulh_i32
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV32I-LABEL: name: umulh_i32
+    ; RV32I: liveins: $x10, $x11
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
+    ; RV32I-NEXT: [[UMULH:%[0-9]+]]:gprb(s32) = G_UMULH [[COPY]], [[COPY1]]
+    ; RV32I-NEXT: $x10 = COPY [[UMULH]](s32)
+    ; RV32I-NEXT: PseudoRET implicit $x10
+    %0:_(s32) = COPY $x10
+    %1:_(s32) = COPY $x11
+    %2:_(s32) = G_UMULH %0, %1
+    $x10 = COPY %2(s32)
+    PseudoRET implicit $x10
+
+...
+---
+name:            icmp_i32
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV32I-LABEL: name: icmp_i32
+    ; RV32I: liveins: $x10, $x11
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
+    ; RV32I-NEXT: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
+    ; RV32I-NEXT: $x10 = COPY [[ICMP]](s32)
+    ; RV32I-NEXT: PseudoRET implicit $x10
+    %0:_(s32) = COPY $x10
+    %1:_(s32) = COPY $x11
+    %2:_(s32) = G_ICMP intpred(eq), %0(s32), %1
+    $x10 = COPY %2(s32)
+    PseudoRET implicit $x10
+
+...
+---
+name:            icmp_ptr
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV32I-LABEL: name: icmp_ptr
+    ; RV32I: liveins: $x10, $x11
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $x11
+    ; RV32I-NEXT: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(eq), [[COPY]](p0), [[COPY1]]
+    ; RV32I-NEXT: $x10 = COPY [[ICMP]](s32)
+    ; RV32I-NEXT: PseudoRET implicit $x10
+    %0:_(p0) = COPY $x10
+    %1:_(p0) = COPY $x11
+    %2:_(s32) = G_ICMP intpred(eq), %0(p0), %1
+    $x10 = COPY %2(s32)
+    PseudoRET implicit $x10
+
+...
+---
+name:            gep
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV32I-LABEL: name: gep
+    ; RV32I: liveins: $x10, $x11
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
+    ; RV32I-NEXT: [[PTR_ADD:%[0-9]+]]:gprb(p0) = G_PTR_ADD [[COPY]], [[COPY1]](s32)
+    ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gprb(p0) = COPY [[PTR_ADD]](p0)
+    ; RV32I-NEXT: $x10 = COPY [[COPY2]](p0)
+    ; RV32I-NEXT: PseudoRET implicit $x10
+    %0:_(p0) = COPY $x10
+    %1:_(s32) = COPY $x11
+    %2:_(p0) = G_PTR_ADD %0, %1(s32)
+    %3:_(p0) = COPY %2(p0)
+    $x10 = COPY %3(p0)
+    PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv64.mir
@@ -0,0 +1,419 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=riscv64 -mattr=+m -run-pass=regbankselect \
+# RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN:   -o - | FileCheck -check-prefix=RV64I %s
+
+---
+name:            add_i64
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV64I-LABEL: name: add_i64
+    ; RV64I: liveins: $x10, $x11
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11
+    ; RV64I-NEXT: [[ADD:%[0-9]+]]:gprb(s64) = G_ADD [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $x10 = COPY [[ADD]](s64)
+    ; RV64I-NEXT: PseudoRET implicit $x10
+    %0:_(s64) = COPY $x10
+    %1:_(s64) = COPY $x11
+    %2:_(s64) = G_ADD %0, %1
+    $x10 = COPY %2(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            sub_i64
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV64I-LABEL: name: sub_i64
+    ; RV64I: liveins: $x10, $x11
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11
+    ; RV64I-NEXT: [[SUB:%[0-9]+]]:gprb(s64) = G_SUB [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $x10 = COPY [[SUB]](s64)
+    ; RV64I-NEXT: PseudoRET implicit $x10
+    %0:_(s64) = COPY $x10
+    %1:_(s64) = COPY $x11
+    %2:_(s64) = G_SUB %0, %1
+    $x10 = COPY %2(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            shl_i64
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV64I-LABEL: name: shl_i64
+    ; RV64I: liveins: $x10, $x11
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11
+    ; RV64I-NEXT: [[SHL:%[0-9]+]]:gprb(s64) = G_SHL [[COPY]], [[COPY1]](s64)
+    ; RV64I-NEXT: $x10 = COPY [[SHL]](s64)
+    ; RV64I-NEXT: PseudoRET implicit $x10
+    %0:_(s64) = COPY $x10
+    %1:_(s64) = COPY $x11
+    %2:_(s64) = G_SHL %0, %1
+    $x10 = COPY %2(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            ashr_i64
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV64I-LABEL: name: ashr_i64
+    ; RV64I: liveins: $x10, $x11
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11
+    ; RV64I-NEXT: [[ASHR:%[0-9]+]]:gprb(s64) = G_ASHR [[COPY]], [[COPY1]](s64)
+    ; RV64I-NEXT: $x10 = COPY [[ASHR]](s64)
+    ; RV64I-NEXT: PseudoRET implicit $x10
+    %0:_(s64) = COPY $x10
+    %1:_(s64) = COPY $x11
+    %2:_(s64) = G_ASHR %0, %1
+    $x10 = COPY %2(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            lshr_i64
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV64I-LABEL: name: lshr_i64
+    ; RV64I: liveins: $x10, $x11
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11
+    ; RV64I-NEXT: [[LSHR:%[0-9]+]]:gprb(s64) = G_LSHR [[COPY]], [[COPY1]](s64)
+    ; RV64I-NEXT: $x10 = COPY [[LSHR]](s64)
+    ; RV64I-NEXT: PseudoRET implicit $x10
+    %0:_(s64) = COPY $x10
+    %1:_(s64) = COPY $x11
+    %2:_(s64) = G_LSHR %0, %1
+    $x10 = COPY %2(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            and_i64
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV64I-LABEL: name: and_i64
+    ; RV64I: liveins: $x10, $x11
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11
+    ; RV64I-NEXT: [[AND:%[0-9]+]]:gprb(s64) = G_AND [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $x10 = COPY [[AND]](s64)
+    ; RV64I-NEXT: PseudoRET implicit $x10
+    %0:_(s64) = COPY $x10
+    %1:_(s64) = COPY $x11
+    %2:_(s64) = G_AND %0, %1
+    $x10 = COPY %2(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            or_i64
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV64I-LABEL: name: or_i64
+    ; RV64I: liveins: $x10, $x11
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11
+    ; RV64I-NEXT: [[OR:%[0-9]+]]:gprb(s64) = G_OR [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $x10 = COPY [[OR]](s64)
+    ; RV64I-NEXT: PseudoRET implicit $x10
+    %0:_(s64) = COPY $x10
+    %1:_(s64) = COPY $x11
+    %2:_(s64) = G_OR %0, %1
+    $x10 = COPY %2(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            xor_i64
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV64I-LABEL: name: xor_i64
+    ; RV64I: liveins: $x10, $x11
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11
+    ; RV64I-NEXT: [[XOR:%[0-9]+]]:gprb(s64) = G_XOR [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $x10 = COPY [[XOR]](s64)
+    ; RV64I-NEXT: PseudoRET implicit $x10
+    %0:_(s64) = COPY $x10
+    %1:_(s64) = COPY $x11
+    %2:_(s64) = G_XOR %0, %1
+    $x10 = COPY %2(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            mul_i64
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV64I-LABEL: name: mul_i64
+    ; RV64I: liveins: $x10, $x11
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11
+    ; RV64I-NEXT: [[MUL:%[0-9]+]]:gprb(s64) = G_MUL [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $x10 = COPY [[MUL]](s64)
+    ; RV64I-NEXT: PseudoRET implicit $x10
+    %0:_(s64) = COPY $x10
+    %1:_(s64) = COPY $x11
+    %2:_(s64) = G_MUL %0, %1
+    $x10 = COPY %2(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            sdiv_i64
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV64I-LABEL: name: sdiv_i64
+    ; RV64I: liveins: $x10, $x11
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11
+    ; RV64I-NEXT: [[SDIV:%[0-9]+]]:gprb(s64) = G_SDIV [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $x10 = COPY [[SDIV]](s64)
+    ; RV64I-NEXT: PseudoRET implicit $x10
+    %0:_(s64) = COPY $x10
+    %1:_(s64) = COPY $x11
+    %2:_(s64) = G_SDIV %0, %1
+    $x10 = COPY %2(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            srem_i64
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV64I-LABEL: name: srem_i64
+    ; RV64I: liveins: $x10, $x11
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11
+    ; RV64I-NEXT: [[SREM:%[0-9]+]]:gprb(s64) = G_SREM [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $x10 = COPY [[SREM]](s64)
+    ; RV64I-NEXT: PseudoRET implicit $x10
+    %0:_(s64) = COPY $x10
+    %1:_(s64) = COPY $x11
+    %2:_(s64) = G_SREM %0, %1
+    $x10 = COPY %2(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            udiv_i64
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV64I-LABEL: name: udiv_i64
+    ; RV64I: liveins: $x10, $x11
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11
+    ; RV64I-NEXT: [[UDIV:%[0-9]+]]:gprb(s64) = G_UDIV [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $x10 = COPY [[UDIV]](s64)
+    ; RV64I-NEXT: PseudoRET implicit $x10
+    %0:_(s64) = COPY $x10
+    %1:_(s64) = COPY $x11
+    %2:_(s64) = G_UDIV %0, %1
+    $x10 = COPY %2(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            urem_i64
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV64I-LABEL: name: urem_i64
+    ; RV64I: liveins: $x10, $x11
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11
+    ; RV64I-NEXT: [[UREM:%[0-9]+]]:gprb(s64) = G_UREM [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $x10 = COPY [[UREM]](s64)
+    ; RV64I-NEXT: PseudoRET implicit $x10
+    %0:_(s64) = COPY $x10
+    %1:_(s64) = COPY $x11
+    %2:_(s64) = G_UREM %0, %1
+    $x10 = COPY %2(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            umulh_i64
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV64I-LABEL: name: umulh_i64
+    ; RV64I: liveins: $x10, $x11
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11
+    ; RV64I-NEXT: [[UMULH:%[0-9]+]]:gprb(s64) = G_UMULH [[COPY]], [[COPY1]]
+    ; RV64I-NEXT: $x10 = COPY [[UMULH]](s64)
+    ; RV64I-NEXT: PseudoRET implicit $x10
+    %0:_(s64) = COPY $x10
+    %1:_(s64) = COPY $x11
+    %2:_(s64) = G_UMULH %0, %1
+    $x10 = COPY %2(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            icmp_i64
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV64I-LABEL: name: icmp_i64
+    ; RV64I: liveins: $x10, $x11
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11
+    ; RV64I-NEXT: [[ICMP:%[0-9]+]]:gprb(s64) = G_ICMP intpred(eq), [[COPY]](s64), [[COPY1]]
+    ; RV64I-NEXT: $x10 = COPY [[ICMP]](s64)
+    ; RV64I-NEXT: PseudoRET implicit $x10
+    %0:_(s64) = COPY $x10
+    %1:_(s64) = COPY $x11
+    %2:_(s64) = G_ICMP intpred(eq), %0(s64), %1
+    $x10 = COPY %2(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            icmp_ptr
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV64I-LABEL: name: icmp_ptr
+    ; RV64I: liveins: $x10, $x11
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $x11
+    ; RV64I-NEXT: [[ICMP:%[0-9]+]]:gprb(s64) = G_ICMP intpred(eq), [[COPY]](p0), [[COPY1]]
+    ; RV64I-NEXT: $x10 = COPY [[ICMP]](s64)
+    ; RV64I-NEXT: PseudoRET implicit $x10
+    %0:_(p0) = COPY $x10
+    %1:_(p0) = COPY $x11
+    %2:_(s64) = G_ICMP intpred(eq), %0(p0), %1
+    $x10 = COPY %2(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            sext_inreg_i64
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10
+
+    ; RV64I-LABEL: name: sext_inreg_i64
+    ; RV64I: liveins: $x10
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+    ; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:gprb(s64) = G_SEXT_INREG [[COPY]], 32
+    ; RV64I-NEXT: $x10 = COPY [[SEXT_INREG]](s64)
+    ; RV64I-NEXT: PseudoRET implicit $x10
+    %0:_(s64) = COPY $x10
+    %1:_(s64) = G_SEXT_INREG %0, 32
+    $x10 = COPY %1(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            gep
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV64I-LABEL: name: gep
+    ; RV64I: liveins: $x10, $x11
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11
+    ; RV64I-NEXT: [[PTR_ADD:%[0-9]+]]:gprb(p0) = G_PTR_ADD [[COPY]], [[COPY1]](s64)
+    ; RV64I-NEXT: [[COPY2:%[0-9]+]]:gprb(p0) = COPY [[PTR_ADD]](p0)
+    ; RV64I-NEXT: $x10 = COPY [[COPY2]](p0)
+    ; RV64I-NEXT: PseudoRET implicit $x10
+    %0:_(p0) = COPY $x10
+    %1:_(s64) = COPY $x11
+    %2:_(p0) = G_PTR_ADD %0, %1(s64)
+    %3:_(p0) = COPY %2(p0)
+    $x10 = COPY %3(p0)
+    PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv32.mir
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv32.mir
@@ -0,0 +1,71 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=riscv32 -run-pass=regbankselect \
+# RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN:   -o - | FileCheck -check-prefix=RV32I %s
+
+---
+name:            virt_to_phys
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+
+    ; RV32I-LABEL: name: virt_to_phys
+    ; RV32I: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
+    ; RV32I-NEXT: $x10 = COPY [[C]](s32)
+    ; RV32I-NEXT: PseudoRET implicit $x10
+    %0:_(s32) = G_CONSTANT i32 1
+    $x10 = COPY %0(s32)
+    PseudoRET implicit $x10
+
+...
+---
+name:            phys_to_phys
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV32I-LABEL: name: phys_to_phys
+    ; RV32I: liveins: $x10, $x11
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: $x10 = COPY $x11
+    ; RV32I-NEXT: PseudoRET implicit $x10
+    $x10 = COPY $x11
+    PseudoRET implicit $x10
+
+...
+---
+name:            virt_to_virt
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+
+    ; RV32I-LABEL: name: virt_to_virt
+    ; RV32I: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY [[C]](s32)
+    ; RV32I-NEXT: PseudoRET
+    %0:_(s32) = G_CONSTANT i32 1
+    %1:_(s32) = COPY %0(s32)
+    PseudoRET
+
+...
+---
+name:            phys_to_virt
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10
+
+    ; RV32I-LABEL: name: phys_to_virt
+    ; RV32I: liveins: $x10
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+    ; RV32I-NEXT: PseudoRET
+    %0:_(s32) = COPY $x10
+    PseudoRET
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv64.mir
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/copy-rv64.mir
@@ -0,0 +1,71 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=riscv64 -run-pass=regbankselect \
+# RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN:   -o - | FileCheck -check-prefix=RV64I %s
+
+---
+name:            virt_to_phys
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+
+    ; RV64I-LABEL: name: virt_to_phys
+    ; RV64I: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 1
+    ; RV64I-NEXT: $x10 = COPY [[C]](s64)
+    ; RV64I-NEXT: PseudoRET implicit $x10
+    %0:_(s64) = G_CONSTANT i64 1
+    $x10 = COPY %0(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            phys_to_phys
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV64I-LABEL: name: phys_to_phys
+    ; RV64I: liveins: $x10, $x11
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: $x10 = COPY $x11
+    ; RV64I-NEXT: PseudoRET implicit $x10
+    $x10 = COPY $x11
+    PseudoRET implicit $x10
+
+...
+---
+name:            virt_to_virt
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+
+    ; RV64I-LABEL: name: virt_to_virt
+    ; RV64I: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 1
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY [[C]](s64)
+    ; RV64I-NEXT: PseudoRET
+    %0:_(s64) = G_CONSTANT i64 1
+    %1:_(s64) = COPY %0(s64)
+    PseudoRET
+
+...
+---
+name:            phys_to_virt
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10
+
+    ; RV64I-LABEL: name: phys_to_virt
+    ; RV64I: liveins: $x10
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+    ; RV64I-NEXT: PseudoRET
+    %0:_(s64) = COPY $x10
+    PseudoRET
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ext-trunc-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ext-trunc-rv64.mir
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/ext-trunc-rv64.mir
@@ -0,0 +1,89 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=riscv64 -run-pass=regbankselect \
+# RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN:   -o - | FileCheck -check-prefix=RV64I %s
+
+---
+name:            anyext_i32_i64
+legalized:       true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV64I-LABEL: name: anyext_i32_i64
+    ; RV64I: liveins: $x10, $x11
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+    ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:gprb(s32) = G_TRUNC [[COPY]](s64)
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11
+    ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:gprb(s32) = G_TRUNC [[COPY1]](s64)
+    ; RV64I-NEXT: [[ADD:%[0-9]+]]:gprb(s32) = G_ADD [[TRUNC]], [[TRUNC1]]
+    ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[ADD]](s32)
+    ; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
+    ; RV64I-NEXT: PseudoRET implicit $x10
+    %2:_(s64) = COPY $x10
+    %0:_(s32) = G_TRUNC %2(s64)
+    %3:_(s64) = COPY $x11
+    %1:_(s32) = G_TRUNC %3(s64)
+    %4:_(s32) = G_ADD %0, %1
+    %5:_(s64) = G_ANYEXT %4(s32)
+    $x10 = COPY %5(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            sext_i32_i64
+legalized:       true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV64I-LABEL: name: sext_i32_i64
+    ; RV64I: liveins: $x10, $x11
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+    ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:gprb(s32) = G_TRUNC [[COPY]](s64)
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11
+    ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:gprb(s32) = G_TRUNC [[COPY1]](s64)
+    ; RV64I-NEXT: [[ADD:%[0-9]+]]:gprb(s32) = G_ADD [[TRUNC]], [[TRUNC1]]
+    ; RV64I-NEXT: [[SEXT:%[0-9]+]]:gprb(s64) = G_SEXT [[ADD]](s32)
+    ; RV64I-NEXT: $x10 = COPY [[SEXT]](s64)
+    ; RV64I-NEXT: PseudoRET implicit $x10
+    %2:_(s64) = COPY $x10
+    %0:_(s32) = G_TRUNC %2(s64)
+    %3:_(s64) = COPY $x11
+    %1:_(s32) = G_TRUNC %3(s64)
+    %4:_(s32) = G_ADD %0, %1
+    %5:_(s64) = G_SEXT %4(s32)
+    $x10 = COPY %5(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            zext_i32_i64
+legalized:       true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; RV64I-LABEL: name: zext_i32_i64
+    ; RV64I: liveins: $x10, $x11
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+    ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:gprb(s32) = G_TRUNC [[COPY]](s64)
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11
+    ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:gprb(s32) = G_TRUNC [[COPY1]](s64)
+    ; RV64I-NEXT: [[ADD:%[0-9]+]]:gprb(s32) = G_ADD [[TRUNC]], [[TRUNC1]]
+    ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:gprb(s64) = G_ZEXT [[ADD]](s32)
+    ; RV64I-NEXT: $x10 = COPY [[ZEXT]](s64)
+    ; RV64I-NEXT: PseudoRET implicit $x10
+    %2:_(s64) = COPY $x10
+    %0:_(s32) = G_TRUNC %2(s64)
+    %3:_(s64) = COPY $x11
+    %1:_(s32) = G_TRUNC %3(s64)
+    %4:_(s32) = G_ADD %0, %1
+    %5:_(s64) = G_ZEXT %4(s32)
+    $x10 = COPY %5(s64)
+    PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv32.mir
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv32.mir
@@ -0,0 +1,28 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=riscv32 -run-pass=regbankselect \
+# RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN:   -o - | FileCheck -check-prefix=RV32I %s
+
+--- |
+  @var = global i32 0
+
+  define ptr @test_global() {
+    ret ptr @var
+  }
+
+...
+---
+name:            test_global
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0 (%ir-block.0):
+    ; RV32I-LABEL: name: test_global
+    ; RV32I: [[GV:%[0-9]+]]:gprb(p0) = G_GLOBAL_VALUE @var
+    ; RV32I-NEXT: $x10 = COPY [[GV]](p0)
+    ; RV32I-NEXT: PseudoRET implicit $x10
+    %0:_(p0) = G_GLOBAL_VALUE @var
+    $x10 = COPY %0(p0)
+    PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv64.mir
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/global-rv64.mir
@@ -0,0 +1,28 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=riscv64 -run-pass=regbankselect \
+# RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN:   -o - | FileCheck -check-prefix=RV64I %s
+
+--- |
+  @var = global i32 0
+
+  define ptr @test_global() {
+    ret ptr @var
+  }
+
+...
+---
+name:            test_global
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0 (%ir-block.0):
+    ; RV64I-LABEL: name: test_global
+    ; RV64I: [[GV:%[0-9]+]]:gprb(p0) = G_GLOBAL_VALUE @var
+    ; RV64I-NEXT: $x10 = COPY [[GV]](p0)
+    ; RV64I-NEXT: PseudoRET implicit $x10
+    %0:_(p0) = G_GLOBAL_VALUE @var
+    $x10 = COPY %0(p0)
+    PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv32.mir
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv32.mir
@@ -0,0 +1,131 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=riscv32 -run-pass=regbankselect \
+# RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN:   -o - | FileCheck -check-prefix=RV32I %s
+
+---
+name:            load_i8
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x10
+
+    ; RV32I-LABEL: name: load_i8
+    ; RV32I: liveins: $x10
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+    ; RV32I-NEXT: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load (s8))
+    ; RV32I-NEXT: $x10 = COPY [[LOAD]](s32)
+    ; RV32I-NEXT: PseudoRET implicit $x10
+    %0:_(p0) = COPY $x10
+    %3:_(s32) = G_LOAD %0(p0) :: (load (s8))
+    $x10 = COPY %3(s32)
+    PseudoRET implicit $x10
+
+...
+---
+name:            load_i16
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x10
+
+    ; RV32I-LABEL: name: load_i16
+    ; RV32I: liveins: $x10
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+    ; RV32I-NEXT: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load (s16))
+    ; RV32I-NEXT: $x10 = COPY [[LOAD]](s32)
+    ; RV32I-NEXT: PseudoRET implicit $x10
+    %0:_(p0) = COPY $x10
+    %3:_(s32) = G_LOAD %0(p0) :: (load (s16))
+    $x10 = COPY %3(s32)
+    PseudoRET implicit $x10
+
+...
+---
+name:            load_i32
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x10
+
+    ; RV32I-LABEL: name: load_i32
+    ; RV32I: liveins: $x10
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+    ; RV32I-NEXT: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
+    ; RV32I-NEXT: $x10 = COPY [[LOAD]](s32)
+    ; RV32I-NEXT: PseudoRET implicit $x10
+    %0:_(p0) = COPY $x10
+    %3:_(s32) = G_LOAD %0(p0) :: (load (s32))
+    $x10 = COPY %3(s32)
+    PseudoRET implicit $x10
+
+...
+---
+name:            load_ptr
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x10
+
+    ; RV32I-LABEL: name: load_ptr
+    ; RV32I: liveins: $x10
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+    ; RV32I-NEXT: [[LOAD:%[0-9]+]]:gprb(p0) = G_LOAD [[COPY]](p0) :: (load (p0))
+    ; RV32I-NEXT: $x10 = COPY [[LOAD]](p0)
+    ; RV32I-NEXT: PseudoRET implicit $x10
+    %0:_(p0) = COPY $x10
+    %3:_(p0) = G_LOAD %0(p0) :: (load (p0))
+    $x10 = COPY %3(p0)
+    PseudoRET implicit $x10
+
+...
+---
+name:            zextload_i8
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x10
+
+    ; RV32I-LABEL: name: zextload_i8
+    ; RV32I: liveins: $x10
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+    ; RV32I-NEXT: [[ZEXTLOAD:%[0-9]+]]:gprb(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
+    ; RV32I-NEXT: $x10 = COPY [[ZEXTLOAD]](s32)
+    ; RV32I-NEXT: PseudoRET implicit $x10
+    %0:_(p0) = COPY $x10
+    %1:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s8))
+    $x10 = COPY %1(s32)
+    PseudoRET implicit $x10
+
+...
+---
+name:            zextload_i16
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x10
+
+    ; RV32I-LABEL: name: zextload_i16
+    ; RV32I: liveins: $x10
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+    ; RV32I-NEXT: [[ZEXTLOAD:%[0-9]+]]:gprb(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16))
+    ; RV32I-NEXT: $x10 = COPY [[ZEXTLOAD]](s32)
+    ; RV32I-NEXT: PseudoRET implicit $x10
+    %0:_(p0) = COPY $x10
+    %1:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s16))
+    $x10 = COPY %1(s32)
+    PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv64.mir
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/load-rv64.mir
@@ -0,0 +1,174 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=riscv64 -run-pass=regbankselect \
+# RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN:   -o - | FileCheck -check-prefix=RV64I %s
+
+---
+name:            load_i8
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x10
+
+    ; RV64I-LABEL: name: load_i8
+    ; RV64I: liveins: $x10
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+    ; RV64I-NEXT: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load (s8))
+    ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[LOAD]](s32)
+    ; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
+    ; RV64I-NEXT: PseudoRET implicit $x10
+    %0:_(p0) = COPY $x10
+    %3:_(s32) = G_LOAD %0(p0) :: (load (s8))
+    %2:_(s64) = G_ANYEXT %3(s32)
+    $x10 = COPY %2(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            load_i16
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x10
+
+    ; RV64I-LABEL: name: load_i16
+    ; RV64I: liveins: $x10
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+    ; RV64I-NEXT: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load (s16))
+    ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[LOAD]](s32)
+    ; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
+    ; RV64I-NEXT: PseudoRET implicit $x10
+    %0:_(p0) = COPY $x10
+    %3:_(s32) = G_LOAD %0(p0) :: (load (s16))
+    %2:_(s64) = G_ANYEXT %3(s32)
+    $x10 = COPY %2(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            load_i32
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x10
+
+    ; RV64I-LABEL: name: load_i32
+    ; RV64I: liveins: $x10
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+    ; RV64I-NEXT: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
+    ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[LOAD]](s32)
+    ; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
+    ; RV64I-NEXT: PseudoRET implicit $x10
+    %0:_(p0) = COPY $x10
+    %1:_(s32) = G_LOAD %0(p0) :: (load (s32))
+    %2:_(s64) = G_ANYEXT %1(s32)
+    $x10 = COPY %2(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            load_i64
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x10
+
+    ; RV64I-LABEL: name: load_i64
+    ; RV64I: liveins: $x10
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+    ; RV64I-NEXT: [[LOAD:%[0-9]+]]:gprb(s64) = G_LOAD [[COPY]](p0) :: (load (s64))
+    ; RV64I-NEXT: $x10 = COPY [[LOAD]](s64)
+    ; RV64I-NEXT: PseudoRET implicit $x10
+    %0:_(p0) = COPY $x10
+    %1:_(s64) = G_LOAD %0(p0) :: (load (s64))
+    $x10 = COPY %1(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            load_ptr
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x10
+
+    ; RV64I-LABEL: name: load_ptr
+    ; RV64I: liveins: $x10
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+    ; RV64I-NEXT: [[LOAD:%[0-9]+]]:gprb(p0) = G_LOAD [[COPY]](p0) :: (load (p0))
+    ; RV64I-NEXT: $x10 = COPY [[LOAD]](p0)
+    ; RV64I-NEXT: PseudoRET implicit $x10
+    %0:_(p0) = COPY $x10
+    %1:_(p0) = G_LOAD %0(p0) :: (load (p0))
+    $x10 = COPY %1(p0)
+    PseudoRET implicit $x10
+
+...
+name:            zextload_i8
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x10
+
+    %0:_(p0) = COPY $x10
+    %3:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s8))
+    %2:_(s64) = G_ANYEXT %3(s32)
+    $x10 = COPY %2(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            zextload_i16
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x10
+
+    ; RV64I-LABEL: name: zextload_i16
+    ; RV64I: liveins: $x10
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+    ; RV64I-NEXT: [[ZEXTLOAD:%[0-9]+]]:gprb(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16))
+    ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[ZEXTLOAD]](s32)
+    ; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
+    ; RV64I-NEXT: PseudoRET implicit $x10
+    %0:_(p0) = COPY $x10
+    %3:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s16))
+    %2:_(s64) = G_ANYEXT %3(s32)
+    $x10 = COPY %2(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            zextload_i32
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x10
+
+    ; RV64I-LABEL: name: zextload_i32
+    ; RV64I: liveins: $x10
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+    ; RV64I-NEXT: [[ZEXTLOAD:%[0-9]+]]:gprb(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load (s32))
+    ; RV64I-NEXT: $x10 = COPY [[ZEXTLOAD]](s64)
+    ; RV64I-NEXT: PseudoRET implicit $x10
+    %0:_(p0) = COPY $x10
+    %1:_(s64) = G_ZEXTLOAD %0(p0) :: (load (s32))
+    $x10 = COPY %1(s64)
+    PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv32.mir
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv32.mir
@@ -0,0 +1,89 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=riscv32 -run-pass=regbankselect \
+# RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN:   -o - | FileCheck -check-prefix=RV32I %s
+
+---
+name:            phi_i32
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  ; RV32I-LABEL: name: phi_i32
+  ; RV32I: bb.0:
+  ; RV32I-NEXT:   liveins: $x10, $x11, $x12
+  ; RV32I-NEXT: {{  $}}
+  ; RV32I-NEXT:   [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+  ; RV32I-NEXT:   [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
+  ; RV32I-NEXT:   [[COPY2:%[0-9]+]]:gprb(s32) = COPY $x12
+  ; RV32I-NEXT:   [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
+  ; RV32I-NEXT:   [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY]], [[C]]
+  ; RV32I-NEXT:   G_BRCOND [[AND]](s32), %bb.2
+  ; RV32I-NEXT:   G_BR %bb.1
+  ; RV32I-NEXT: {{  $}}
+  ; RV32I-NEXT: bb.1:
+  ; RV32I-NEXT: {{  $}}
+  ; RV32I-NEXT: bb.2:
+  ; RV32I-NEXT:   [[PHI:%[0-9]+]]:gprb(s32) = G_PHI [[COPY2]](s32), %bb.1, [[COPY1]](s32), %bb.0
+  ; RV32I-NEXT:   $x10 = COPY [[PHI]](s32)
+  ; RV32I-NEXT:   PseudoRET implicit $x10
+  bb.0:
+    liveins: $x10, $x11, $x12
+
+    %3:_(s32) = COPY $x10
+    %1:_(s32) = COPY $x11
+    %2:_(s32) = COPY $x12
+    %6:_(s32) = G_CONSTANT i32 1
+    %5:_(s32) = G_AND %3, %6
+    G_BRCOND %5(s32), %bb.2
+    G_BR %bb.1
+
+  bb.1:
+
+  bb.2:
+    %4:_(s32) = G_PHI %2(s32), %bb.1, %1(s32), %bb.0
+    $x10 = COPY %4(s32)
+    PseudoRET implicit $x10
+
+...
+---
+name:            phi_ptr
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  ; RV32I-LABEL: name: phi_ptr
+  ; RV32I: bb.0.entry:
+  ; RV32I-NEXT:   liveins: $x10, $x11, $x12
+  ; RV32I-NEXT: {{  $}}
+  ; RV32I-NEXT:   [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+  ; RV32I-NEXT:   [[COPY1:%[0-9]+]]:gprb(p0) = COPY $x11
+  ; RV32I-NEXT:   [[COPY2:%[0-9]+]]:gprb(p0) = COPY $x12
+  ; RV32I-NEXT:   [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
+  ; RV32I-NEXT:   [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY]], [[C]]
+  ; RV32I-NEXT:   G_BRCOND [[AND]](s32), %bb.2
+  ; RV32I-NEXT:   G_BR %bb.1
+  ; RV32I-NEXT: {{  $}}
+  ; RV32I-NEXT: bb.1:
+  ; RV32I-NEXT: {{  $}}
+  ; RV32I-NEXT: bb.2:
+  ; RV32I-NEXT:   [[PHI:%[0-9]+]]:gprb(p0) = G_PHI [[COPY2]](p0), %bb.1, [[COPY1]](p0), %bb.0
+  ; RV32I-NEXT:   $x10 = COPY [[PHI]](p0)
+  ; RV32I-NEXT:   PseudoRET implicit $x10
+  bb.0.entry:
+    liveins: $x10, $x11, $x12
+
+    %3:_(s32) = COPY $x10
+    %1:_(p0) = COPY $x11
+    %2:_(p0) = COPY $x12
+    %6:_(s32) = G_CONSTANT i32 1
+    %5:_(s32) = G_AND %3, %6
+    G_BRCOND %5(s32), %bb.2
+    G_BR %bb.1
+
+  bb.1:
+
+  bb.2:
+    %4:_(p0) = G_PHI %2(p0), %bb.1, %1(p0), %bb.0
+    $x10 = COPY %4(p0)
+    PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv64.mir
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/phi-rv64.mir
@@ -0,0 +1,89 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=riscv64 -run-pass=regbankselect \
+# RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN:   -o - | FileCheck -check-prefix=RV64I %s
+
+---
+name:            phi_i64
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  ; RV64I-LABEL: name: phi_i64
+  ; RV64I: bb.0:
+  ; RV64I-NEXT:   liveins: $x10, $x11, $x12
+  ; RV64I-NEXT: {{  $}}
+  ; RV64I-NEXT:   [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+  ; RV64I-NEXT:   [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11
+  ; RV64I-NEXT:   [[COPY2:%[0-9]+]]:gprb(s64) = COPY $x12
+  ; RV64I-NEXT:   [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 1
+  ; RV64I-NEXT:   [[AND:%[0-9]+]]:gprb(s64) = G_AND [[COPY]], [[C]]
+  ; RV64I-NEXT:   G_BRCOND [[AND]](s64), %bb.2
+  ; RV64I-NEXT:   G_BR %bb.1
+  ; RV64I-NEXT: {{  $}}
+  ; RV64I-NEXT: bb.1:
+  ; RV64I-NEXT: {{  $}}
+  ; RV64I-NEXT: bb.2:
+  ; RV64I-NEXT:   [[PHI:%[0-9]+]]:gprb(s64) = G_PHI [[COPY2]](s64), %bb.1, [[COPY1]](s64), %bb.0
+  ; RV64I-NEXT:   $x10 = COPY [[PHI]](s64)
+  ; RV64I-NEXT:   PseudoRET implicit $x10
+  bb.0:
+    liveins: $x10, $x11, $x12
+
+    %3:_(s64) = COPY $x10
+    %1:_(s64) = COPY $x11
+    %2:_(s64) = COPY $x12
+    %6:_(s64) = G_CONSTANT i64 1
+    %5:_(s64) = G_AND %3, %6
+    G_BRCOND %5(s64), %bb.2
+    G_BR %bb.1
+
+  bb.1:
+
+  bb.2:
+    %4:_(s64) = G_PHI %2(s64), %bb.1, %1(s64), %bb.0
+    $x10 = COPY %4(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            phi_ptr
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  ; RV64I-LABEL: name: phi_ptr
+  ; RV64I: bb.0:
+  ; RV64I-NEXT:   liveins: $x10, $x11, $x12
+  ; RV64I-NEXT: {{  $}}
+  ; RV64I-NEXT:   [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+  ; RV64I-NEXT:   [[COPY1:%[0-9]+]]:gprb(p0) = COPY $x11
+  ; RV64I-NEXT:   [[COPY2:%[0-9]+]]:gprb(p0) = COPY $x12
+  ; RV64I-NEXT:   [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 1
+  ; RV64I-NEXT:   [[AND:%[0-9]+]]:gprb(s64) = G_AND [[COPY]], [[C]]
+  ; RV64I-NEXT:   G_BRCOND [[AND]](s64), %bb.2
+  ; RV64I-NEXT:   G_BR %bb.1
+  ; RV64I-NEXT: {{  $}}
+  ; RV64I-NEXT: bb.1:
+  ; RV64I-NEXT: {{  $}}
+  ; RV64I-NEXT: bb.2:
+  ; RV64I-NEXT:   [[PHI:%[0-9]+]]:gprb(p0) = G_PHI [[COPY2]](p0), %bb.1, [[COPY1]](p0), %bb.0
+  ; RV64I-NEXT:   $x10 = COPY [[PHI]](p0)
+  ; RV64I-NEXT:   PseudoRET implicit $x10
+  bb.0:
+    liveins: $x10, $x11, $x12
+
+    %3:_(s64) = COPY $x10
+    %1:_(p0) = COPY $x11
+    %2:_(p0) = COPY $x12
+    %6:_(s64) = G_CONSTANT i64 1
+    %5:_(s64) = G_AND %3, %6
+    G_BRCOND %5(s64), %bb.2
+    G_BR %bb.1
+
+  bb.1:
+
+  bb.2:
+    %4:_(p0) = G_PHI %2(p0), %bb.1, %1(p0), %bb.0
+    $x10 = COPY %4(p0)
+    PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv32.mir
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv32.mir
@@ -0,0 +1,63 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=riscv32 -run-pass=regbankselect \
+# RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN:   -o - | FileCheck -check-prefix=RV32I %s
+
+---
+name:            select_i32
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11, $x12
+
+    ; RV32I-LABEL: name: select_i32
+    ; RV32I: liveins: $x10, $x11, $x12
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
+    ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $x12
+    ; RV32I-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
+    ; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY]], [[C]]
+    ; RV32I-NEXT: [[SELECT:%[0-9]+]]:gprb(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
+    ; RV32I-NEXT: $x10 = COPY [[SELECT]](s32)
+    ; RV32I-NEXT: PseudoRET implicit $x10
+    %3:_(s32) = COPY $x10
+    %4:_(s32) = COPY $x11
+    %5:_(s32) = COPY $x12
+    %12:_(s32) = G_CONSTANT i32 1
+    %11:_(s32) = G_AND %3, %12
+    %10:_(s32) = G_SELECT %11(s32), %4, %5
+    $x10 = COPY %10(s32)
+    PseudoRET implicit $x10
+
+...
+---
+name:            select_ptr
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11, $x12
+
+    ; RV32I-LABEL: name: select_ptr
+    ; RV32I: liveins: $x10, $x11, $x12
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $x11
+    ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $x12
+    ; RV32I-NEXT: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
+    ; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY]], [[C]]
+    ; RV32I-NEXT: [[SELECT:%[0-9]+]]:gprb(p0) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
+    ; RV32I-NEXT: $x10 = COPY [[SELECT]](p0)
+    ; RV32I-NEXT: PseudoRET implicit $x10
+    %3:_(s32) = COPY $x10
+    %4:_(p0) = COPY $x11
+    %5:_(p0) = COPY $x12
+    %12:_(s32) = G_CONSTANT i32 1
+    %11:_(s32) = G_AND %3, %12
+    %10:_(p0) = G_SELECT %11(s32), %4, %5
+    $x10 = COPY %10(p0)
+    PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv64.mir
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/select-rv64.mir
@@ -0,0 +1,63 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=riscv64 -run-pass=regbankselect \
+# RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN:   -o - | FileCheck -check-prefix=RV64I %s
+
+---
+name:            select_i64
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11, $x12
+
+    ; RV64I-LABEL: name: select_i64
+    ; RV64I: liveins: $x10, $x11, $x12
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11
+    ; RV64I-NEXT: [[COPY2:%[0-9]+]]:gprb(s64) = COPY $x12
+    ; RV64I-NEXT: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 1
+    ; RV64I-NEXT: [[AND:%[0-9]+]]:gprb(s64) = G_AND [[COPY]], [[C]]
+    ; RV64I-NEXT: [[SELECT:%[0-9]+]]:gprb(s64) = G_SELECT [[AND]](s64), [[COPY1]], [[COPY2]]
+    ; RV64I-NEXT: $x10 = COPY [[SELECT]](s64)
+    ; RV64I-NEXT: PseudoRET implicit $x10
+    %3:_(s64) = COPY $x10
+    %4:_(s64) = COPY $x11
+    %5:_(s64) = COPY $x12
+    %12:_(s64) = G_CONSTANT i64 1
+    %11:_(s64) = G_AND %3, %12
+    %10:_(s64) = G_SELECT %11(s64), %4, %5
+    $x10 = COPY %10(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            select_ptr
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11, $x12
+
+    ; RV64I-LABEL: name: select_ptr
+    ; RV64I: liveins: $x10, $x11, $x12
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $x11
+    ; RV64I-NEXT: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $x12
+    ; RV64I-NEXT: [[C:%[0-9]+]]:gprb(s64) = G_CONSTANT i64 1
+    ; RV64I-NEXT: [[AND:%[0-9]+]]:gprb(s64) = G_AND [[COPY]], [[C]]
+    ; RV64I-NEXT: [[SELECT:%[0-9]+]]:gprb(p0) = G_SELECT [[AND]](s64), [[COPY1]], [[COPY2]]
+    ; RV64I-NEXT: $x10 = COPY [[SELECT]](p0)
+    ; RV64I-NEXT: PseudoRET implicit $x10
+    %3:_(s64) = COPY $x10
+    %4:_(p0) = COPY $x11
+    %5:_(p0) = COPY $x12
+    %12:_(s64) = G_CONSTANT i64 1
+    %11:_(s64) = G_AND %3, %12
+    %10:_(p0) = G_SELECT %11(s64), %4, %5
+    $x10 = COPY %10(p0)
+    PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv32.mir
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv32.mir
@@ -0,0 +1,89 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=riscv32 -run-pass=regbankselect \
+# RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN:   -o - | FileCheck -check-prefix=RV32I %s
+
+---
+name:            store_i8
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x10, $x11
+
+    ; RV32I-LABEL: name: store_i8
+    ; RV32I: liveins: $x10, $x11
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $x11
+    ; RV32I-NEXT: G_STORE [[COPY]](s32), [[COPY1]](p0) :: (store (s8))
+    ; RV32I-NEXT: PseudoRET
+    %2:_(s32) = COPY $x10
+    %1:_(p0) = COPY $x11
+    G_STORE %2(s32), %1(p0) :: (store (s8))
+    PseudoRET
+
+...
+---
+name:            store_i16
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x10, $x11
+
+    ; RV32I-LABEL: name: store_i16
+    ; RV32I: liveins: $x10, $x11
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $x11
+    ; RV32I-NEXT: G_STORE [[COPY]](s32), [[COPY1]](p0) :: (store (s16))
+    ; RV32I-NEXT: PseudoRET
+    %2:_(s32) = COPY $x10
+    %1:_(p0) = COPY $x11
+    G_STORE %2(s32), %1(p0) :: (store (s16))
+    PseudoRET
+
+...
+---
+name:            store_i32
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x10, $x11
+
+    ; RV32I-LABEL: name: store_i32
+    ; RV32I: liveins: $x10, $x11
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $x11
+    ; RV32I-NEXT: G_STORE [[COPY]](s32), [[COPY1]](p0) :: (store (s32))
+    ; RV32I-NEXT: PseudoRET
+    %0:_(s32) = COPY $x10
+    %1:_(p0) = COPY $x11
+    G_STORE %0(s32), %1(p0) :: (store (s32))
+    PseudoRET
+
+...
+---
+name:            store_ptr
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x10, $x11
+
+    ; RV32I-LABEL: name: store_ptr
+    ; RV32I: liveins: $x10, $x11
+    ; RV32I-NEXT: {{  $}}
+    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $x11
+    ; RV32I-NEXT: G_STORE [[COPY]](p0), [[COPY1]](p0) :: (store (p0), align 8)
+    ; RV32I-NEXT: PseudoRET
+    %0:_(p0) = COPY $x10
+    %1:_(p0) = COPY $x11
+    G_STORE %0(p0), %1(p0) :: (store (p0), align 8)
+    PseudoRET
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv64.mir
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/store-rv64.mir
@@ -0,0 +1,113 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=riscv64 -run-pass=regbankselect \
+# RUN:   -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
+# RUN:   -o - | FileCheck -check-prefix=RV64I %s
+
+---
+name:            store_i8
+legalized:       true
+body:             |
+  bb.0:
+    liveins: $x10, $x11
+
+    ; RV64I-LABEL: name: store_i8
+    ; RV64I: liveins: $x10, $x11
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $x11
+    ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:gprb(s32) = G_TRUNC [[COPY]](s64)
+    ; RV64I-NEXT: G_STORE [[TRUNC]](s32), [[COPY1]](p0) :: (store (s8))
+    ; RV64I-NEXT: PseudoRET
+    %2:_(s64) = COPY $x10
+    %1:_(p0) = COPY $x11
+    %3:_(s32) = G_TRUNC %2(s64)
+    G_STORE %3(s32), %1(p0) :: (store (s8))
+    PseudoRET
+
+...
+---
+name:            store_i16
+legalized:       true
+body:             |
+  bb.0:
+    liveins: $x10, $x11
+
+    ; RV64I-LABEL: name: store_i16
+    ; RV64I: liveins: $x10, $x11
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $x11
+    ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:gprb(s32) = G_TRUNC [[COPY]](s64)
+    ; RV64I-NEXT: G_STORE [[TRUNC]](s32), [[COPY1]](p0) :: (store (s16))
+    ; RV64I-NEXT: PseudoRET
+    %2:_(s64) = COPY $x10
+    %1:_(p0) = COPY $x11
+    %3:_(s32) = G_TRUNC %2(s64)
+    G_STORE %3(s32), %1(p0) :: (store (s16))
+    PseudoRET
+
+...
+---
+name:            store_i32
+legalized:       true
+body:             |
+  bb.0:
+    liveins: $x10, $x11
+
+    ; RV64I-LABEL: name: store_i32
+    ; RV64I: liveins: $x10, $x11
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $x11
+    ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:gprb(s32) = G_TRUNC [[COPY]](s64)
+    ; RV64I-NEXT: G_STORE [[TRUNC]](s32), [[COPY1]](p0) :: (store (s32))
+    ; RV64I-NEXT: PseudoRET
+    %2:_(s64) = COPY $x10
+    %1:_(p0) = COPY $x11
+    %3:_(s32) = G_TRUNC %2(s64)
+    G_STORE %3(s32), %1(p0) :: (store (s32))
+    PseudoRET
+
+...
+---
+name:            store_i64
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x10, $x11
+
+    ; RV64I-LABEL: name: store_i64
+    ; RV64I: liveins: $x10, $x11
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $x11
+    ; RV64I-NEXT: G_STORE [[COPY]](s64), [[COPY1]](p0) :: (store (s64))
+    ; RV64I-NEXT: PseudoRET
+    %0:_(s64) = COPY $x10
+    %1:_(p0) = COPY $x11
+    G_STORE %0(s64), %1(p0) :: (store (s64))
+    PseudoRET
+
+...
+---
+name:            store_ptr
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x10, $x11
+
+    ; RV64I-LABEL: name: store_ptr
+    ; RV64I: liveins: $x10, $x11
+    ; RV64I-NEXT: {{  $}}
+    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
+    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $x11
+    ; RV64I-NEXT: G_STORE [[COPY]](p0), [[COPY1]](p0) :: (store (p0))
+    ; RV64I-NEXT: PseudoRET
+    %0:_(p0) = COPY $x10
+    %1:_(p0) = COPY $x11
+    G_STORE %0(p0), %1(p0) :: (store (p0))
+    PseudoRET
+
+...