diff --git a/llvm/lib/Target/AMDGPU/SISchedule.td b/llvm/lib/Target/AMDGPU/SISchedule.td
--- a/llvm/lib/Target/AMDGPU/SISchedule.td
+++ b/llvm/lib/Target/AMDGPU/SISchedule.td
@@ -27,8 +27,10 @@
 def MIVGPRRead  : SchedRead;
 def MIMFMARead  : SchedRead;
 
-// Normal 16 or 32 bit VALU instructions
+// Normal 16 or 32 bit VALU instructions. "Aux" forms are used for the second
+// and subsequent def operands of instructions with multiple results.
 def Write32Bit         : SchedWrite;
+def Write32BitAux      : SchedWrite;
 // Conversion to or from F32 (but not converting F64 to or from F32)
 def WriteFloatCvt      : SchedWrite;
 // F16 or F32 transcendental instructions (these are quarter rate)
@@ -36,10 +38,12 @@
 // Other quarter rate VALU instructions
 def WriteQuarterRate32 : SchedWrite;
 
-def WriteFloatFMA   : SchedWrite;
+def WriteFloatFMA    : SchedWrite;
+def WriteFloatFMAAux : SchedWrite;
 
 // Slow quarter rate f64 instruction.
-def WriteDouble : SchedWrite;
+def WriteDouble    : SchedWrite;
+def WriteDoubleAux : SchedWrite;
 
 // half rate f64 instruction (same as v_add_f64)
 def WriteDoubleAdd  : SchedWrite;
@@ -52,10 +56,12 @@
 def WriteTrans64    : SchedWrite;
 
 // Half rate 64-bit instructions.
-def Write64Bit : SchedWrite;
+def Write64Bit    : SchedWrite;
+def Write64BitAux : SchedWrite;
 
 // Integer multiplications.
-def WriteIntMul : SchedWrite;
+def WriteIntMul    : SchedWrite;
+def WriteIntMulAux : SchedWrite;
 
 // mAI multipass instructions.
 def Write2PassMAI  : SchedWrite;
@@ -114,14 +120,22 @@
   let BufferSize = 0;
 }
 
+// Define the resources and latency of a SchedWrite.
 class HWWriteRes<SchedWrite write, list<ProcResourceKind> resources,
                  int latency> : WriteRes<write, resources> {
   let Latency = latency;
+  // If no resources are specifed then assume that this is for the second or
+  // subsequent operand of an instruction, which we don't want to consume any
+  // additional issue resource.
+  let NumMicroOps = !if(!empty(resources), 0, 1);
 }
 
 class HWVALUWriteRes<SchedWrite write, int latency> :
   HWWriteRes<write, [HWVALU], latency>;
 
+class HWAuxWriteRes<SchedWrite write, int latency> :
+  HWWriteRes<write, [], latency>;
+
 def PredMIReadVGPR : SchedPredicate<[{TII->hasVGPRUses(*MI)}]>;
 
 def MIReadVGPR : SchedReadVariant<[
@@ -143,6 +157,7 @@
   def : HWWriteRes<WriteBarrier, [HWBranch], 500>; // XXX: Guessed ???
 
   def : HWVALUWriteRes<Write32Bit,         1>;
+  def : HWAuxWriteRes<Write32BitAux,       1>;
   def : HWVALUWriteRes<WriteFloatCvt,      4>;
   def : HWVALUWriteRes<WriteTrans32,       4>;
   def : HWVALUWriteRes<WriteQuarterRate32, 4>;
@@ -180,9 +195,13 @@
 defm : SICommonWriteRes;
 
 def : HWVALUWriteRes<Write64Bit,       2>;
+def : HWAuxWriteRes<Write64BitAux,     2>;
 def : HWVALUWriteRes<WriteIntMul,      4>;
+def : HWAuxWriteRes<WriteIntMulAux,    4>;
 def : HWVALUWriteRes<WriteFloatFMA,    1>;
+def : HWAuxWriteRes<WriteFloatFMAAux,  1>;
 def : HWVALUWriteRes<WriteDouble,      4>;
+def : HWAuxWriteRes<WriteDoubleAux,    4>;
 def : HWVALUWriteRes<WriteDoubleAdd,   2>;
 def : HWVALUWriteRes<WriteDoubleCvt,   4>;
 def : HWVALUWriteRes<WriteTrans64,     4>;
@@ -196,9 +215,13 @@
 defm : SICommonWriteRes;
 
 def : HWVALUWriteRes<Write64Bit,       2>;
+def : HWAuxWriteRes<Write64BitAux,     2>;
 def : HWVALUWriteRes<WriteIntMul,      4>;
+def : HWAuxWriteRes<WriteIntMulAux,    4>;
 def : HWVALUWriteRes<WriteFloatFMA,    16>;
+def : HWAuxWriteRes<WriteFloatFMAAux,  16>;
 def : HWVALUWriteRes<WriteDouble,      16>;
+def : HWAuxWriteRes<WriteDoubleAux,    16>;
 def : HWVALUWriteRes<WriteDoubleAdd,    8>;
 def : HWVALUWriteRes<WriteDoubleCvt,    4>;
 def : HWVALUWriteRes<WriteTrans64,     16>;
@@ -216,12 +239,16 @@
 defm : SICommonWriteRes;
 
 def : HWVALUWriteRes<WriteFloatFMA,    1>;
+def : HWAuxWriteRes<WriteFloatFMAAux,  1>;
 def : HWVALUWriteRes<WriteDouble,      1>;
+def : HWAuxWriteRes<WriteDoubleAux,    1>;
 def : HWVALUWriteRes<WriteDoubleAdd,   1>;
 def : HWVALUWriteRes<WriteDoubleCvt,   1>;
 def : HWVALUWriteRes<WriteTrans64,     4>;
 def : HWVALUWriteRes<WriteIntMul,      1>;
+def : HWAuxWriteRes<WriteIntMulAux,    1>;
 def : HWVALUWriteRes<Write64Bit,       1>;
+def : HWAuxWriteRes<Write64BitAux,     1>;
 
 def : InstRW<[WriteCopy], (instrs COPY)>;
 def : InstRW<[Write64Bit], (instregex "^V_ACCVGPR_WRITE_B32_e64$")>;
@@ -238,15 +265,20 @@
 // The latency values are 1 / (operations / cycle).
 // Add 1 stall cycle for VGPR read.
 def : HWWriteRes<Write32Bit,         [HWVALU, HWRC],   5>;
+def : HWWriteRes<Write32BitAux,      [HWRC],           5>;
 def : HWWriteRes<WriteFloatCvt,      [HWVALU, HWRC],   5>;
 def : HWWriteRes<Write64Bit,         [HWVALU, HWRC],   6>;
+def : HWWriteRes<Write64BitAux,      [HWRC],           6>;
 def : HWWriteRes<WriteTrans32,       [HWVALU, HWRC],   10>;
 def : HWWriteRes<WriteQuarterRate32, [HWVALU, HWRC],   8>;
 def : HWWriteRes<WriteFloatFMA,      [HWVALU, HWRC],   5>;
+def : HWWriteRes<WriteFloatFMAAux,   [HWRC],           5>;
 def : HWWriteRes<WriteDouble,        [HWVALU, HWRC],   22>;
+def : HWWriteRes<WriteDoubleAux,     [HWRC],           22>;
 def : HWWriteRes<WriteDoubleAdd,     [HWVALU, HWRC],   22>;
 def : HWWriteRes<WriteDoubleCvt,     [HWVALU, HWRC],   22>;
 def : HWWriteRes<WriteIntMul,        [HWVALU, HWRC],   8>;
+def : HWWriteRes<WriteIntMulAux,     [HWRC],           8>;
 def : HWWriteRes<WriteTrans64,       [HWVALU, HWRC],   24>;
 
 def : HWWriteRes<WriteBranch,        [HWBranch],       32>;
diff --git a/llvm/lib/Target/AMDGPU/VOP1Instructions.td b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
--- a/llvm/lib/Target/AMDGPU/VOP1Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
@@ -445,7 +445,7 @@
   def V_SWAP_B32 : VOP1_Pseudo<"v_swap_b32", VOP_SWAP_I32, [], 1> {
     let Constraints = "$vdst = $src1, $vdst1 = $src0";
     let DisableEncoding = "$vdst1,$src1";
-    let SchedRW = [Write64Bit, Write64Bit];
+    let SchedRW = [Write64Bit, Write64BitAux];
   }
 
   defm V_SAT_PK_U8_I16    : VOP1Inst<"v_sat_pk_u8_i16", VOP_I32_I32>;
@@ -470,7 +470,7 @@
     def V_SWAPREL_B32 : VOP1_Pseudo<"v_swaprel_b32", VOP_SWAP_I32, [], 1> {
       let Constraints = "$vdst = $src1, $vdst1 = $src0";
       let DisableEncoding = "$vdst1,$src1";
-      let SchedRW = [Write64Bit, Write64Bit];
+      let SchedRW = [Write64Bit, Write64BitAux];
     }
   } // End Uses = [M0]
 } // End SubtargetPredicate = isGFX10Plus
diff --git a/llvm/lib/Target/AMDGPU/VOP2Instructions.td b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
--- a/llvm/lib/Target/AMDGPU/VOP2Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
@@ -179,7 +179,7 @@
                       bit GFX9Renamed = 0,
                       bit useSGPRInput = !eq(P.NumSrcArgs, 3)> {
   let renamedInGFX9 = GFX9Renamed in {
-    let SchedRW = [Write32Bit, WriteSALU] in {
+    let SchedRW = [Write32Bit, Write32BitAux] in {
       let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]), Defs = [VCC] in {
         def _e32 : VOP2_Pseudo <opName, P, VOPPatOrNull<node,P>.ret>,
                    Commutable_REV<revOp#"_e32", !eq(revOp, opName)> {
diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
--- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -391,11 +391,11 @@
 
 
 let mayRaiseFPException = 0 in { // Seems suspicious but manual doesn't say it does.
-  let SchedRW = [WriteFloatFMA, WriteSALU] in
+  let SchedRW = [WriteFloatFMA, WriteFloatFMAAux] in
   defm V_DIV_SCALE_F32 : VOP3Inst_Pseudo_Wrapper <"v_div_scale_f32", VOP3b_F32_I1_F32_F32_F32, [], 1> ;
 
   // Double precision division pre-scale.
-  let SchedRW = [WriteDouble, WriteSALU], FPDPRounding = 1 in
+  let SchedRW = [WriteDouble, WriteDoubleAux], FPDPRounding = 1 in
   defm V_DIV_SCALE_F64 : VOP3Inst_Pseudo_Wrapper <"v_div_scale_f64", VOP3b_F64_I1_F64_F64_F64, [], 1>;
 } // End mayRaiseFPException = 0
 
@@ -447,10 +447,10 @@
 } // End Constraints = "@earlyclobber $vdst", SchedRW = [WriteQuarterRate32]
 
 let isCommutable = 1 in {
-let SchedRW = [WriteIntMul, WriteSALU] in {
+let SchedRW = [WriteIntMul, WriteIntMulAux] in {
 defm V_MAD_U64_U32 : VOP3Inst <"v_mad_u64_u32", VOP3b_I64_I1_I32_I32_I64>;
 defm V_MAD_I64_I32 : VOP3Inst <"v_mad_i64_i32", VOP3b_I64_I1_I32_I32_I64>;
-} // End SchedRW = [WriteIntMul, WriteSALU]
+} // End SchedRW = [WriteIntMul, WriteIntMulAux]
 } // End isCommutable = 1
 
 } // End SubtargetPredicate = isGFX7Plus
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll
@@ -11,31 +11,54 @@
 ; GCN-NEXT:    s_mov_b32 s6, s33
 ; GCN-NEXT:    s_add_u32 s33, s32, 0x3fc0
 ; GCN-NEXT:    s_and_b32 s33, s33, 0xffffc000
-; GCN-NEXT:    v_add_co_u32_e32 v3, vcc, 64, v0
-; GCN-NEXT:    buffer_store_dword v40, off, s[0:3], s33 offset:52 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v41, off, s[0:3], s33 offset:48 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v42, off, s[0:3], s33 offset:44 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v43, off, s[0:3], s33 offset:40 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s33 offset:36 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], s33 offset:32 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v46, off, s[0:3], s33 offset:28 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v47, off, s[0:3], s33 offset:24 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v56, off, s[0:3], s33 offset:20 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v57, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v58, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v59, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v60, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v61, off, s[0:3], s33 ; 4-byte Folded Spill
-; GCN-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v1, vcc
-; GCN-NEXT:    s_movk_i32 s4, 0x80
-; GCN-NEXT:    global_load_dwordx4 v[8:11], v[3:4], off offset:16
-; GCN-NEXT:    global_load_dwordx4 v[12:15], v[3:4], off offset:32
-; GCN-NEXT:    global_load_dwordx4 v[56:59], v[3:4], off offset:48
+; GCN-NEXT:    v_add_co_u32_e32 v12, vcc, 64, v0
+; GCN-NEXT:    buffer_store_dword v40, off, s[0:3], s33 offset:44 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v41, off, s[0:3], s33 offset:40 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v42, off, s[0:3], s33 offset:36 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v43, off, s[0:3], s33 offset:32 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s33 offset:28 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], s33 offset:24 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v46, off, s[0:3], s33 offset:20 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v47, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v56, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v57, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v58, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v59, off, s[0:3], s33 ; 4-byte Folded Spill
+; GCN-NEXT:    v_addc_co_u32_e32 v13, vcc, 0, v1, vcc
+; GCN-NEXT:    global_load_dwordx4 v[4:7], v[12:13], off offset:16
+; GCN-NEXT:    global_load_dwordx4 v[8:11], v[12:13], off offset:32
 ; GCN-NEXT:    s_mov_b32 s5, 0
-; GCN-NEXT:    v_mov_b32_e32 v3, s4
-; GCN-NEXT:    v_mov_b32_e32 v4, s5
-; GCN-NEXT:    v_add_co_u32_e32 v3, vcc, v0, v3
-; GCN-NEXT:    v_addc_co_u32_e32 v4, vcc, v1, v4, vcc
+; GCN-NEXT:    s_movk_i32 s4, 0x80
+; GCN-NEXT:    v_mov_b32_e32 v17, s5
+; GCN-NEXT:    v_mov_b32_e32 v16, s4
+; GCN-NEXT:    s_movk_i32 s4, 0xc0
+; GCN-NEXT:    s_add_u32 s32, s32, 0x10000
+; GCN-NEXT:    s_sub_u32 s32, s32, 0x10000
+; GCN-NEXT:    s_waitcnt vmcnt(0)
+; GCN-NEXT:    buffer_store_dword v0, off, s[0:3], s33 offset:640 ; 4-byte Folded Spill
+; GCN-NEXT:    s_waitcnt vmcnt(0)
+; GCN-NEXT:    buffer_store_dword v1, off, s[0:3], s33 offset:644 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v2, off, s[0:3], s33 offset:648 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v3, off, s[0:3], s33 offset:652 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v4, off, s[0:3], s33 offset:656 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v5, off, s[0:3], s33 offset:660 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v6, off, s[0:3], s33 offset:664 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v7, off, s[0:3], s33 offset:668 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v8, off, s[0:3], s33 offset:672 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v9, off, s[0:3], s33 offset:676 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v10, off, s[0:3], s33 offset:680 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v11, off, s[0:3], s33 offset:684 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v12, off, s[0:3], s33 offset:688 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v13, off, s[0:3], s33 offset:692 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v14, off, s[0:3], s33 offset:696 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v15, off, s[0:3], s33 offset:700 ; 4-byte Folded Spill
+; GCN-NEXT:    v_add_co_u32_e32 v52, vcc, v0, v16
+; GCN-NEXT:    v_addc_co_u32_e32 v53, vcc, v1, v17, vcc
+; GCN-NEXT:    v_mov_b32_e32 v17, s5
+; GCN-NEXT:    v_mov_b32_e32 v16, s4
+; GCN-NEXT:    v_add_co_u32_e32 v56, vcc, v0, v16
+; GCN-NEXT:    global_load_dwordx4 v[12:15], v[12:13], off offset:48
+; GCN-NEXT:    v_addc_co_u32_e32 v57, vcc, v1, v17, vcc
 ; GCN-NEXT:    global_load_dwordx4 v[16:19], v[0:1], off
 ; GCN-NEXT:    global_load_dwordx4 v[20:23], v[0:1], off offset:16
 ; GCN-NEXT:    global_load_dwordx4 v[24:27], v[0:1], off offset:32
@@ -43,41 +66,15 @@
 ; GCN-NEXT:    global_load_dwordx4 v[32:35], v[0:1], off offset:64
 ; GCN-NEXT:    global_load_dwordx4 v[36:39], v[0:1], off offset:128
 ; GCN-NEXT:    global_load_dwordx4 v[40:43], v[0:1], off offset:192
-; GCN-NEXT:    global_load_dwordx4 v[44:47], v[3:4], off offset:16
-; GCN-NEXT:    global_load_dwordx4 v[48:51], v[3:4], off offset:32
-; GCN-NEXT:    global_load_dwordx4 v[52:55], v[3:4], off offset:48
-; GCN-NEXT:    s_movk_i32 s4, 0xc0
-; GCN-NEXT:    v_mov_b32_e32 v6, s5
-; GCN-NEXT:    v_mov_b32_e32 v5, s4
-; GCN-NEXT:    v_add_co_u32_e32 v60, vcc, v0, v5
-; GCN-NEXT:    v_addc_co_u32_e32 v61, vcc, v1, v6, vcc
+; GCN-NEXT:    global_load_dwordx4 v[44:47], v[52:53], off offset:16
+; GCN-NEXT:    global_load_dwordx4 v[8:11], v[52:53], off offset:32
+; GCN-NEXT:    global_load_dwordx4 v[52:55], v[52:53], off offset:48
+; GCN-NEXT:    global_load_dwordx4 v[48:51], v[56:57], off offset:16
 ; GCN-NEXT:    v_and_b32_e32 v0, 63, v2
 ; GCN-NEXT:    v_lshrrev_b32_e64 v1, 6, s33
 ; GCN-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
 ; GCN-NEXT:    v_add_u32_e32 v1, 0x100, v1
 ; GCN-NEXT:    v_add_u32_e32 v0, v1, v0
-; GCN-NEXT:    s_add_u32 s32, s32, 0x10000
-; GCN-NEXT:    s_sub_u32 s32, s32, 0x10000
-; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    buffer_store_dword v40, off, s[0:3], s33 offset:640 ; 4-byte Folded Spill
-; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    buffer_store_dword v41, off, s[0:3], s33 offset:644 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v42, off, s[0:3], s33 offset:648 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v43, off, s[0:3], s33 offset:652 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s33 offset:656 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], s33 offset:660 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v46, off, s[0:3], s33 offset:664 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v47, off, s[0:3], s33 offset:668 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v48, off, s[0:3], s33 offset:672 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v49, off, s[0:3], s33 offset:676 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v50, off, s[0:3], s33 offset:680 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v51, off, s[0:3], s33 offset:684 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v52, off, s[0:3], s33 offset:688 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v53, off, s[0:3], s33 offset:692 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v54, off, s[0:3], s33 offset:696 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v55, off, s[0:3], s33 offset:700 ; 4-byte Folded Spill
-; GCN-NEXT:    global_load_dwordx4 v[4:7], v[60:61], off offset:16
-; GCN-NEXT:    global_load_dwordx4 v[52:55], v[60:61], off offset:32
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
 ; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s33 offset:576 ; 4-byte Folded Spill
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
@@ -96,7 +93,7 @@
 ; GCN-NEXT:    buffer_store_dword v57, off, s[0:3], s33 offset:628 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v58, off, s[0:3], s33 offset:632 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v59, off, s[0:3], s33 offset:636 ; 4-byte Folded Spill
-; GCN-NEXT:    global_load_dwordx4 v[52:55], v[60:61], off offset:48
+; GCN-NEXT:    global_load_dwordx4 v[48:51], v[56:57], off offset:32
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
 ; GCN-NEXT:    buffer_store_dword v40, off, s[0:3], s33 offset:512 ; 4-byte Folded Spill
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
@@ -115,6 +112,7 @@
 ; GCN-NEXT:    buffer_store_dword v53, off, s[0:3], s33 offset:564 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v54, off, s[0:3], s33 offset:568 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v55, off, s[0:3], s33 offset:572 ; 4-byte Folded Spill
+; GCN-NEXT:    global_load_dwordx4 v[56:59], v[56:57], off offset:48
 ; GCN-NEXT:    buffer_store_dword v16, off, s[0:3], s33 offset:256
 ; GCN-NEXT:    buffer_store_dword v17, off, s[0:3], s33 offset:260
 ; GCN-NEXT:    buffer_store_dword v18, off, s[0:3], s33 offset:264
@@ -139,59 +137,55 @@
 ; GCN-NEXT:    buffer_store_dword v37, off, s[0:3], s33 offset:388
 ; GCN-NEXT:    buffer_store_dword v38, off, s[0:3], s33 offset:392
 ; GCN-NEXT:    buffer_store_dword v39, off, s[0:3], s33 offset:396
-; GCN-NEXT:    buffer_store_dword v8, off, s[0:3], s33 offset:336
-; GCN-NEXT:    buffer_store_dword v9, off, s[0:3], s33 offset:340
-; GCN-NEXT:    buffer_store_dword v10, off, s[0:3], s33 offset:344
-; GCN-NEXT:    buffer_store_dword v11, off, s[0:3], s33 offset:348
-; GCN-NEXT:    buffer_store_dword v12, off, s[0:3], s33 offset:352
-; GCN-NEXT:    buffer_store_dword v13, off, s[0:3], s33 offset:356
-; GCN-NEXT:    buffer_store_dword v14, off, s[0:3], s33 offset:360
-; GCN-NEXT:    buffer_store_dword v15, off, s[0:3], s33 offset:364
-; GCN-NEXT:    buffer_store_dword v56, off, s[0:3], s33 offset:368
-; GCN-NEXT:    buffer_store_dword v57, off, s[0:3], s33 offset:372
-; GCN-NEXT:    buffer_store_dword v58, off, s[0:3], s33 offset:376
-; GCN-NEXT:    buffer_store_dword v59, off, s[0:3], s33 offset:380
-; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s33 offset:400
-; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], s33 offset:404
-; GCN-NEXT:    buffer_store_dword v46, off, s[0:3], s33 offset:408
-; GCN-NEXT:    buffer_store_dword v47, off, s[0:3], s33 offset:412
-; GCN-NEXT:    buffer_store_dword v48, off, s[0:3], s33 offset:416
-; GCN-NEXT:    buffer_store_dword v49, off, s[0:3], s33 offset:420
-; GCN-NEXT:    buffer_store_dword v50, off, s[0:3], s33 offset:424
-; GCN-NEXT:    buffer_store_dword v51, off, s[0:3], s33 offset:428
-; GCN-NEXT:    buffer_load_dword v8, off, s[0:3], s33 offset:640 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v9, off, s[0:3], s33 offset:644 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v10, off, s[0:3], s33 offset:648 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v11, off, s[0:3], s33 offset:652 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v12, off, s[0:3], s33 offset:656 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v13, off, s[0:3], s33 offset:660 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v14, off, s[0:3], s33 offset:664 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v15, off, s[0:3], s33 offset:668 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v16, off, s[0:3], s33 offset:672 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v17, off, s[0:3], s33 offset:676 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v18, off, s[0:3], s33 offset:680 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v19, off, s[0:3], s33 offset:684 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v20, off, s[0:3], s33 offset:688 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v21, off, s[0:3], s33 offset:692 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v22, off, s[0:3], s33 offset:696 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v23, off, s[0:3], s33 offset:700 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_store_dword v4, off, s[0:3], s33 offset:336
+; GCN-NEXT:    buffer_store_dword v5, off, s[0:3], s33 offset:340
+; GCN-NEXT:    buffer_store_dword v6, off, s[0:3], s33 offset:344
+; GCN-NEXT:    buffer_store_dword v7, off, s[0:3], s33 offset:348
+; GCN-NEXT:    buffer_load_dword v16, off, s[0:3], s33 offset:640 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v17, off, s[0:3], s33 offset:644 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v18, off, s[0:3], s33 offset:648 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v19, off, s[0:3], s33 offset:652 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v20, off, s[0:3], s33 offset:656 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v21, off, s[0:3], s33 offset:660 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v22, off, s[0:3], s33 offset:664 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v23, off, s[0:3], s33 offset:668 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v24, off, s[0:3], s33 offset:672 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v25, off, s[0:3], s33 offset:676 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v26, off, s[0:3], s33 offset:680 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v27, off, s[0:3], s33 offset:684 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v28, off, s[0:3], s33 offset:688 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v29, off, s[0:3], s33 offset:692 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v30, off, s[0:3], s33 offset:696 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v31, off, s[0:3], s33 offset:700 ; 4-byte Folded Reload
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    v_mov_b32_e32 v12, v20
-; GCN-NEXT:    v_mov_b32_e32 v13, v21
-; GCN-NEXT:    v_mov_b32_e32 v14, v22
-; GCN-NEXT:    v_mov_b32_e32 v15, v23
-; GCN-NEXT:    buffer_store_dword v12, off, s[0:3], s33 offset:432
-; GCN-NEXT:    buffer_store_dword v13, off, s[0:3], s33 offset:436
-; GCN-NEXT:    buffer_store_dword v14, off, s[0:3], s33 offset:440
-; GCN-NEXT:    buffer_store_dword v15, off, s[0:3], s33 offset:444
+; GCN-NEXT:    v_mov_b32_e32 v16, v24
+; GCN-NEXT:    v_mov_b32_e32 v17, v25
+; GCN-NEXT:    v_mov_b32_e32 v18, v26
+; GCN-NEXT:    v_mov_b32_e32 v19, v27
+; GCN-NEXT:    buffer_store_dword v16, off, s[0:3], s33 offset:352
+; GCN-NEXT:    buffer_store_dword v17, off, s[0:3], s33 offset:356
+; GCN-NEXT:    buffer_store_dword v18, off, s[0:3], s33 offset:360
+; GCN-NEXT:    buffer_store_dword v19, off, s[0:3], s33 offset:364
+; GCN-NEXT:    buffer_store_dword v12, off, s[0:3], s33 offset:368
+; GCN-NEXT:    buffer_store_dword v13, off, s[0:3], s33 offset:372
+; GCN-NEXT:    buffer_store_dword v14, off, s[0:3], s33 offset:376
+; GCN-NEXT:    buffer_store_dword v15, off, s[0:3], s33 offset:380
 ; GCN-NEXT:    buffer_store_dword v40, off, s[0:3], s33 offset:448
 ; GCN-NEXT:    buffer_store_dword v41, off, s[0:3], s33 offset:452
 ; GCN-NEXT:    buffer_store_dword v42, off, s[0:3], s33 offset:456
 ; GCN-NEXT:    buffer_store_dword v43, off, s[0:3], s33 offset:460
-; GCN-NEXT:    buffer_store_dword v4, off, s[0:3], s33 offset:464
-; GCN-NEXT:    buffer_store_dword v5, off, s[0:3], s33 offset:468
-; GCN-NEXT:    buffer_store_dword v6, off, s[0:3], s33 offset:472
-; GCN-NEXT:    buffer_store_dword v7, off, s[0:3], s33 offset:476
+; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s33 offset:400
+; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], s33 offset:404
+; GCN-NEXT:    buffer_store_dword v46, off, s[0:3], s33 offset:408
+; GCN-NEXT:    buffer_store_dword v47, off, s[0:3], s33 offset:412
+; GCN-NEXT:    buffer_store_dword v8, off, s[0:3], s33 offset:416
+; GCN-NEXT:    buffer_store_dword v9, off, s[0:3], s33 offset:420
+; GCN-NEXT:    buffer_store_dword v10, off, s[0:3], s33 offset:424
+; GCN-NEXT:    buffer_store_dword v11, off, s[0:3], s33 offset:428
+; GCN-NEXT:    buffer_store_dword v52, off, s[0:3], s33 offset:432
+; GCN-NEXT:    buffer_store_dword v53, off, s[0:3], s33 offset:436
+; GCN-NEXT:    buffer_store_dword v54, off, s[0:3], s33 offset:440
+; GCN-NEXT:    buffer_store_dword v55, off, s[0:3], s33 offset:444
 ; GCN-NEXT:    buffer_load_dword v3, off, s[0:3], s33 offset:576 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v4, off, s[0:3], s33 offset:580 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v5, off, s[0:3], s33 offset:584 ; 4-byte Folded Reload
@@ -209,14 +203,14 @@
 ; GCN-NEXT:    buffer_load_dword v17, off, s[0:3], s33 offset:632 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v18, off, s[0:3], s33 offset:636 ; 4-byte Folded Reload
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    v_mov_b32_e32 v8, v11
-; GCN-NEXT:    v_mov_b32_e32 v9, v12
-; GCN-NEXT:    v_mov_b32_e32 v10, v13
-; GCN-NEXT:    v_mov_b32_e32 v11, v14
-; GCN-NEXT:    buffer_store_dword v8, off, s[0:3], s33 offset:480
-; GCN-NEXT:    buffer_store_dword v9, off, s[0:3], s33 offset:484
-; GCN-NEXT:    buffer_store_dword v10, off, s[0:3], s33 offset:488
-; GCN-NEXT:    buffer_store_dword v11, off, s[0:3], s33 offset:492
+; GCN-NEXT:    v_mov_b32_e32 v4, v7
+; GCN-NEXT:    v_mov_b32_e32 v5, v8
+; GCN-NEXT:    v_mov_b32_e32 v6, v9
+; GCN-NEXT:    v_mov_b32_e32 v7, v10
+; GCN-NEXT:    buffer_store_dword v4, off, s[0:3], s33 offset:464
+; GCN-NEXT:    buffer_store_dword v5, off, s[0:3], s33 offset:468
+; GCN-NEXT:    buffer_store_dword v6, off, s[0:3], s33 offset:472
+; GCN-NEXT:    buffer_store_dword v7, off, s[0:3], s33 offset:476
 ; GCN-NEXT:    buffer_load_dword v3, off, s[0:3], s33 offset:512 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v4, off, s[0:3], s33 offset:516 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v5, off, s[0:3], s33 offset:520 ; 4-byte Folded Reload
@@ -234,29 +228,31 @@
 ; GCN-NEXT:    buffer_load_dword v17, off, s[0:3], s33 offset:568 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v18, off, s[0:3], s33 offset:572 ; 4-byte Folded Reload
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    v_mov_b32_e32 v12, v15
-; GCN-NEXT:    v_mov_b32_e32 v13, v16
-; GCN-NEXT:    v_mov_b32_e32 v14, v17
-; GCN-NEXT:    v_mov_b32_e32 v15, v18
-; GCN-NEXT:    buffer_store_dword v12, off, s[0:3], s33 offset:496
-; GCN-NEXT:    buffer_store_dword v13, off, s[0:3], s33 offset:500
-; GCN-NEXT:    buffer_store_dword v14, off, s[0:3], s33 offset:504
-; GCN-NEXT:    buffer_store_dword v15, off, s[0:3], s33 offset:508
+; GCN-NEXT:    v_mov_b32_e32 v8, v11
+; GCN-NEXT:    v_mov_b32_e32 v9, v12
+; GCN-NEXT:    v_mov_b32_e32 v10, v13
+; GCN-NEXT:    v_mov_b32_e32 v11, v14
+; GCN-NEXT:    buffer_store_dword v8, off, s[0:3], s33 offset:480
+; GCN-NEXT:    buffer_store_dword v9, off, s[0:3], s33 offset:484
+; GCN-NEXT:    buffer_store_dword v10, off, s[0:3], s33 offset:488
+; GCN-NEXT:    buffer_store_dword v11, off, s[0:3], s33 offset:492
+; GCN-NEXT:    buffer_store_dword v56, off, s[0:3], s33 offset:496
+; GCN-NEXT:    buffer_store_dword v57, off, s[0:3], s33 offset:500
+; GCN-NEXT:    buffer_store_dword v58, off, s[0:3], s33 offset:504
+; GCN-NEXT:    buffer_store_dword v59, off, s[0:3], s33 offset:508
 ; GCN-NEXT:    buffer_load_dword v0, v0, s[0:3], 0 offen
-; GCN-NEXT:    buffer_load_dword v61, off, s[0:3], s33 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v60, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v59, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v58, off, s[0:3], s33 offset:12 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v57, off, s[0:3], s33 offset:16 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v56, off, s[0:3], s33 offset:20 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v47, off, s[0:3], s33 offset:24 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v46, off, s[0:3], s33 offset:28 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v45, off, s[0:3], s33 offset:32 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v44, off, s[0:3], s33 offset:36 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v43, off, s[0:3], s33 offset:40 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v42, off, s[0:3], s33 offset:44 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v41, off, s[0:3], s33 offset:48 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v40, off, s[0:3], s33 offset:52 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v59, off, s[0:3], s33 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v58, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v57, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v56, off, s[0:3], s33 offset:12 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v47, off, s[0:3], s33 offset:16 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v46, off, s[0:3], s33 offset:20 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v45, off, s[0:3], s33 offset:24 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v44, off, s[0:3], s33 offset:28 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v43, off, s[0:3], s33 offset:32 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v42, off, s[0:3], s33 offset:36 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v41, off, s[0:3], s33 offset:40 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v40, off, s[0:3], s33 offset:44 ; 4-byte Folded Reload
 ; GCN-NEXT:    s_mov_b32 s33, s6
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
@@ -272,31 +268,54 @@
 ; GCN-NEXT:    s_mov_b32 s6, s33
 ; GCN-NEXT:    s_add_u32 s33, s32, 0x3fc0
 ; GCN-NEXT:    s_and_b32 s33, s33, 0xffffc000
-; GCN-NEXT:    v_add_co_u32_e32 v3, vcc, 64, v0
-; GCN-NEXT:    buffer_store_dword v40, off, s[0:3], s33 offset:52 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v41, off, s[0:3], s33 offset:48 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v42, off, s[0:3], s33 offset:44 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v43, off, s[0:3], s33 offset:40 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s33 offset:36 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], s33 offset:32 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v46, off, s[0:3], s33 offset:28 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v47, off, s[0:3], s33 offset:24 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v56, off, s[0:3], s33 offset:20 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v57, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v58, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v59, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v60, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v61, off, s[0:3], s33 ; 4-byte Folded Spill
-; GCN-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v1, vcc
-; GCN-NEXT:    s_movk_i32 s4, 0x80
-; GCN-NEXT:    global_load_dwordx4 v[8:11], v[3:4], off offset:16
-; GCN-NEXT:    global_load_dwordx4 v[12:15], v[3:4], off offset:32
-; GCN-NEXT:    global_load_dwordx4 v[56:59], v[3:4], off offset:48
+; GCN-NEXT:    v_add_co_u32_e32 v12, vcc, 64, v0
+; GCN-NEXT:    buffer_store_dword v40, off, s[0:3], s33 offset:44 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v41, off, s[0:3], s33 offset:40 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v42, off, s[0:3], s33 offset:36 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v43, off, s[0:3], s33 offset:32 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s33 offset:28 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], s33 offset:24 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v46, off, s[0:3], s33 offset:20 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v47, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v56, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v57, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v58, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v59, off, s[0:3], s33 ; 4-byte Folded Spill
+; GCN-NEXT:    v_addc_co_u32_e32 v13, vcc, 0, v1, vcc
+; GCN-NEXT:    global_load_dwordx4 v[4:7], v[12:13], off offset:16
+; GCN-NEXT:    global_load_dwordx4 v[8:11], v[12:13], off offset:32
 ; GCN-NEXT:    s_mov_b32 s5, 0
-; GCN-NEXT:    v_mov_b32_e32 v3, s4
-; GCN-NEXT:    v_mov_b32_e32 v4, s5
-; GCN-NEXT:    v_add_co_u32_e32 v3, vcc, v0, v3
-; GCN-NEXT:    v_addc_co_u32_e32 v4, vcc, v1, v4, vcc
+; GCN-NEXT:    s_movk_i32 s4, 0x80
+; GCN-NEXT:    v_mov_b32_e32 v17, s5
+; GCN-NEXT:    v_mov_b32_e32 v16, s4
+; GCN-NEXT:    s_movk_i32 s4, 0xc0
+; GCN-NEXT:    s_add_u32 s32, s32, 0x10000
+; GCN-NEXT:    s_sub_u32 s32, s32, 0x10000
+; GCN-NEXT:    s_waitcnt vmcnt(0)
+; GCN-NEXT:    buffer_store_dword v0, off, s[0:3], s33 offset:640 ; 4-byte Folded Spill
+; GCN-NEXT:    s_waitcnt vmcnt(0)
+; GCN-NEXT:    buffer_store_dword v1, off, s[0:3], s33 offset:644 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v2, off, s[0:3], s33 offset:648 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v3, off, s[0:3], s33 offset:652 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v4, off, s[0:3], s33 offset:656 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v5, off, s[0:3], s33 offset:660 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v6, off, s[0:3], s33 offset:664 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v7, off, s[0:3], s33 offset:668 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v8, off, s[0:3], s33 offset:672 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v9, off, s[0:3], s33 offset:676 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v10, off, s[0:3], s33 offset:680 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v11, off, s[0:3], s33 offset:684 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v12, off, s[0:3], s33 offset:688 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v13, off, s[0:3], s33 offset:692 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v14, off, s[0:3], s33 offset:696 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v15, off, s[0:3], s33 offset:700 ; 4-byte Folded Spill
+; GCN-NEXT:    v_add_co_u32_e32 v52, vcc, v0, v16
+; GCN-NEXT:    v_addc_co_u32_e32 v53, vcc, v1, v17, vcc
+; GCN-NEXT:    v_mov_b32_e32 v17, s5
+; GCN-NEXT:    v_mov_b32_e32 v16, s4
+; GCN-NEXT:    v_add_co_u32_e32 v56, vcc, v0, v16
+; GCN-NEXT:    global_load_dwordx4 v[12:15], v[12:13], off offset:48
+; GCN-NEXT:    v_addc_co_u32_e32 v57, vcc, v1, v17, vcc
 ; GCN-NEXT:    global_load_dwordx4 v[16:19], v[0:1], off
 ; GCN-NEXT:    global_load_dwordx4 v[20:23], v[0:1], off offset:16
 ; GCN-NEXT:    global_load_dwordx4 v[24:27], v[0:1], off offset:32
@@ -304,41 +323,15 @@
 ; GCN-NEXT:    global_load_dwordx4 v[32:35], v[0:1], off offset:64
 ; GCN-NEXT:    global_load_dwordx4 v[36:39], v[0:1], off offset:128
 ; GCN-NEXT:    global_load_dwordx4 v[40:43], v[0:1], off offset:192
-; GCN-NEXT:    global_load_dwordx4 v[44:47], v[3:4], off offset:16
-; GCN-NEXT:    global_load_dwordx4 v[48:51], v[3:4], off offset:32
-; GCN-NEXT:    global_load_dwordx4 v[52:55], v[3:4], off offset:48
-; GCN-NEXT:    s_movk_i32 s4, 0xc0
-; GCN-NEXT:    v_mov_b32_e32 v6, s5
-; GCN-NEXT:    v_mov_b32_e32 v5, s4
-; GCN-NEXT:    v_add_co_u32_e32 v60, vcc, v0, v5
-; GCN-NEXT:    v_addc_co_u32_e32 v61, vcc, v1, v6, vcc
+; GCN-NEXT:    global_load_dwordx4 v[44:47], v[52:53], off offset:16
+; GCN-NEXT:    global_load_dwordx4 v[8:11], v[52:53], off offset:32
+; GCN-NEXT:    global_load_dwordx4 v[52:55], v[52:53], off offset:48
+; GCN-NEXT:    global_load_dwordx4 v[48:51], v[56:57], off offset:16
 ; GCN-NEXT:    v_lshrrev_b32_e32 v0, 1, v2
 ; GCN-NEXT:    v_and_b32_e32 v0, 63, v0
 ; GCN-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
 ; GCN-NEXT:    v_and_b32_e32 v1, 1, v2
 ; GCN-NEXT:    v_lshlrev_b32_e32 v1, 4, v1
-; GCN-NEXT:    s_add_u32 s32, s32, 0x10000
-; GCN-NEXT:    s_sub_u32 s32, s32, 0x10000
-; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    buffer_store_dword v40, off, s[0:3], s33 offset:640 ; 4-byte Folded Spill
-; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    buffer_store_dword v41, off, s[0:3], s33 offset:644 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v42, off, s[0:3], s33 offset:648 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v43, off, s[0:3], s33 offset:652 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s33 offset:656 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], s33 offset:660 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v46, off, s[0:3], s33 offset:664 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v47, off, s[0:3], s33 offset:668 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v48, off, s[0:3], s33 offset:672 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v49, off, s[0:3], s33 offset:676 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v50, off, s[0:3], s33 offset:680 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v51, off, s[0:3], s33 offset:684 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v52, off, s[0:3], s33 offset:688 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v53, off, s[0:3], s33 offset:692 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v54, off, s[0:3], s33 offset:696 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v55, off, s[0:3], s33 offset:700 ; 4-byte Folded Spill
-; GCN-NEXT:    global_load_dwordx4 v[4:7], v[60:61], off offset:16
-; GCN-NEXT:    global_load_dwordx4 v[52:55], v[60:61], off offset:32
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
 ; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s33 offset:576 ; 4-byte Folded Spill
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
@@ -357,7 +350,7 @@
 ; GCN-NEXT:    buffer_store_dword v57, off, s[0:3], s33 offset:628 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v58, off, s[0:3], s33 offset:632 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v59, off, s[0:3], s33 offset:636 ; 4-byte Folded Spill
-; GCN-NEXT:    global_load_dwordx4 v[52:55], v[60:61], off offset:48
+; GCN-NEXT:    global_load_dwordx4 v[48:51], v[56:57], off offset:32
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
 ; GCN-NEXT:    buffer_store_dword v40, off, s[0:3], s33 offset:512 ; 4-byte Folded Spill
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
@@ -376,6 +369,7 @@
 ; GCN-NEXT:    buffer_store_dword v53, off, s[0:3], s33 offset:564 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v54, off, s[0:3], s33 offset:568 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v55, off, s[0:3], s33 offset:572 ; 4-byte Folded Spill
+; GCN-NEXT:    global_load_dwordx4 v[56:59], v[56:57], off offset:48
 ; GCN-NEXT:    buffer_store_dword v16, off, s[0:3], s33 offset:256
 ; GCN-NEXT:    buffer_store_dword v17, off, s[0:3], s33 offset:260
 ; GCN-NEXT:    buffer_store_dword v18, off, s[0:3], s33 offset:264
@@ -400,59 +394,55 @@
 ; GCN-NEXT:    buffer_store_dword v37, off, s[0:3], s33 offset:388
 ; GCN-NEXT:    buffer_store_dword v38, off, s[0:3], s33 offset:392
 ; GCN-NEXT:    buffer_store_dword v39, off, s[0:3], s33 offset:396
-; GCN-NEXT:    buffer_store_dword v8, off, s[0:3], s33 offset:336
-; GCN-NEXT:    buffer_store_dword v9, off, s[0:3], s33 offset:340
-; GCN-NEXT:    buffer_store_dword v10, off, s[0:3], s33 offset:344
-; GCN-NEXT:    buffer_store_dword v11, off, s[0:3], s33 offset:348
-; GCN-NEXT:    buffer_store_dword v12, off, s[0:3], s33 offset:352
-; GCN-NEXT:    buffer_store_dword v13, off, s[0:3], s33 offset:356
-; GCN-NEXT:    buffer_store_dword v14, off, s[0:3], s33 offset:360
-; GCN-NEXT:    buffer_store_dword v15, off, s[0:3], s33 offset:364
-; GCN-NEXT:    buffer_store_dword v56, off, s[0:3], s33 offset:368
-; GCN-NEXT:    buffer_store_dword v57, off, s[0:3], s33 offset:372
-; GCN-NEXT:    buffer_store_dword v58, off, s[0:3], s33 offset:376
-; GCN-NEXT:    buffer_store_dword v59, off, s[0:3], s33 offset:380
-; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s33 offset:400
-; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], s33 offset:404
-; GCN-NEXT:    buffer_store_dword v46, off, s[0:3], s33 offset:408
-; GCN-NEXT:    buffer_store_dword v47, off, s[0:3], s33 offset:412
-; GCN-NEXT:    buffer_store_dword v48, off, s[0:3], s33 offset:416
-; GCN-NEXT:    buffer_store_dword v49, off, s[0:3], s33 offset:420
-; GCN-NEXT:    buffer_store_dword v50, off, s[0:3], s33 offset:424
-; GCN-NEXT:    buffer_store_dword v51, off, s[0:3], s33 offset:428
-; GCN-NEXT:    buffer_load_dword v8, off, s[0:3], s33 offset:640 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v9, off, s[0:3], s33 offset:644 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v10, off, s[0:3], s33 offset:648 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v11, off, s[0:3], s33 offset:652 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v12, off, s[0:3], s33 offset:656 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v13, off, s[0:3], s33 offset:660 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v14, off, s[0:3], s33 offset:664 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v15, off, s[0:3], s33 offset:668 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v16, off, s[0:3], s33 offset:672 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v17, off, s[0:3], s33 offset:676 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v18, off, s[0:3], s33 offset:680 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v19, off, s[0:3], s33 offset:684 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v20, off, s[0:3], s33 offset:688 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v21, off, s[0:3], s33 offset:692 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v22, off, s[0:3], s33 offset:696 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v23, off, s[0:3], s33 offset:700 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_store_dword v4, off, s[0:3], s33 offset:336
+; GCN-NEXT:    buffer_store_dword v5, off, s[0:3], s33 offset:340
+; GCN-NEXT:    buffer_store_dword v6, off, s[0:3], s33 offset:344
+; GCN-NEXT:    buffer_store_dword v7, off, s[0:3], s33 offset:348
+; GCN-NEXT:    buffer_load_dword v16, off, s[0:3], s33 offset:640 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v17, off, s[0:3], s33 offset:644 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v18, off, s[0:3], s33 offset:648 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v19, off, s[0:3], s33 offset:652 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v20, off, s[0:3], s33 offset:656 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v21, off, s[0:3], s33 offset:660 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v22, off, s[0:3], s33 offset:664 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v23, off, s[0:3], s33 offset:668 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v24, off, s[0:3], s33 offset:672 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v25, off, s[0:3], s33 offset:676 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v26, off, s[0:3], s33 offset:680 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v27, off, s[0:3], s33 offset:684 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v28, off, s[0:3], s33 offset:688 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v29, off, s[0:3], s33 offset:692 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v30, off, s[0:3], s33 offset:696 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v31, off, s[0:3], s33 offset:700 ; 4-byte Folded Reload
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    v_mov_b32_e32 v12, v20
-; GCN-NEXT:    v_mov_b32_e32 v13, v21
-; GCN-NEXT:    v_mov_b32_e32 v14, v22
-; GCN-NEXT:    v_mov_b32_e32 v15, v23
-; GCN-NEXT:    buffer_store_dword v12, off, s[0:3], s33 offset:432
-; GCN-NEXT:    buffer_store_dword v13, off, s[0:3], s33 offset:436
-; GCN-NEXT:    buffer_store_dword v14, off, s[0:3], s33 offset:440
-; GCN-NEXT:    buffer_store_dword v15, off, s[0:3], s33 offset:444
+; GCN-NEXT:    v_mov_b32_e32 v16, v24
+; GCN-NEXT:    v_mov_b32_e32 v17, v25
+; GCN-NEXT:    v_mov_b32_e32 v18, v26
+; GCN-NEXT:    v_mov_b32_e32 v19, v27
+; GCN-NEXT:    buffer_store_dword v16, off, s[0:3], s33 offset:352
+; GCN-NEXT:    buffer_store_dword v17, off, s[0:3], s33 offset:356
+; GCN-NEXT:    buffer_store_dword v18, off, s[0:3], s33 offset:360
+; GCN-NEXT:    buffer_store_dword v19, off, s[0:3], s33 offset:364
+; GCN-NEXT:    buffer_store_dword v12, off, s[0:3], s33 offset:368
+; GCN-NEXT:    buffer_store_dword v13, off, s[0:3], s33 offset:372
+; GCN-NEXT:    buffer_store_dword v14, off, s[0:3], s33 offset:376
+; GCN-NEXT:    buffer_store_dword v15, off, s[0:3], s33 offset:380
 ; GCN-NEXT:    buffer_store_dword v40, off, s[0:3], s33 offset:448
 ; GCN-NEXT:    buffer_store_dword v41, off, s[0:3], s33 offset:452
 ; GCN-NEXT:    buffer_store_dword v42, off, s[0:3], s33 offset:456
 ; GCN-NEXT:    buffer_store_dword v43, off, s[0:3], s33 offset:460
-; GCN-NEXT:    buffer_store_dword v4, off, s[0:3], s33 offset:464
-; GCN-NEXT:    buffer_store_dword v5, off, s[0:3], s33 offset:468
-; GCN-NEXT:    buffer_store_dword v6, off, s[0:3], s33 offset:472
-; GCN-NEXT:    buffer_store_dword v7, off, s[0:3], s33 offset:476
+; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s33 offset:400
+; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], s33 offset:404
+; GCN-NEXT:    buffer_store_dword v46, off, s[0:3], s33 offset:408
+; GCN-NEXT:    buffer_store_dword v47, off, s[0:3], s33 offset:412
+; GCN-NEXT:    buffer_store_dword v8, off, s[0:3], s33 offset:416
+; GCN-NEXT:    buffer_store_dword v9, off, s[0:3], s33 offset:420
+; GCN-NEXT:    buffer_store_dword v10, off, s[0:3], s33 offset:424
+; GCN-NEXT:    buffer_store_dword v11, off, s[0:3], s33 offset:428
+; GCN-NEXT:    buffer_store_dword v52, off, s[0:3], s33 offset:432
+; GCN-NEXT:    buffer_store_dword v53, off, s[0:3], s33 offset:436
+; GCN-NEXT:    buffer_store_dword v54, off, s[0:3], s33 offset:440
+; GCN-NEXT:    buffer_store_dword v55, off, s[0:3], s33 offset:444
 ; GCN-NEXT:    buffer_load_dword v3, off, s[0:3], s33 offset:576 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v4, off, s[0:3], s33 offset:580 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v5, off, s[0:3], s33 offset:584 ; 4-byte Folded Reload
@@ -470,14 +460,14 @@
 ; GCN-NEXT:    buffer_load_dword v17, off, s[0:3], s33 offset:632 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v18, off, s[0:3], s33 offset:636 ; 4-byte Folded Reload
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    v_mov_b32_e32 v8, v11
-; GCN-NEXT:    v_mov_b32_e32 v9, v12
-; GCN-NEXT:    v_mov_b32_e32 v10, v13
-; GCN-NEXT:    v_mov_b32_e32 v11, v14
-; GCN-NEXT:    buffer_store_dword v8, off, s[0:3], s33 offset:480
-; GCN-NEXT:    buffer_store_dword v9, off, s[0:3], s33 offset:484
-; GCN-NEXT:    buffer_store_dword v10, off, s[0:3], s33 offset:488
-; GCN-NEXT:    buffer_store_dword v11, off, s[0:3], s33 offset:492
+; GCN-NEXT:    v_mov_b32_e32 v4, v7
+; GCN-NEXT:    v_mov_b32_e32 v5, v8
+; GCN-NEXT:    v_mov_b32_e32 v6, v9
+; GCN-NEXT:    v_mov_b32_e32 v7, v10
+; GCN-NEXT:    buffer_store_dword v4, off, s[0:3], s33 offset:464
+; GCN-NEXT:    buffer_store_dword v5, off, s[0:3], s33 offset:468
+; GCN-NEXT:    buffer_store_dword v6, off, s[0:3], s33 offset:472
+; GCN-NEXT:    buffer_store_dword v7, off, s[0:3], s33 offset:476
 ; GCN-NEXT:    buffer_load_dword v3, off, s[0:3], s33 offset:512 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v4, off, s[0:3], s33 offset:516 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v5, off, s[0:3], s33 offset:520 ; 4-byte Folded Reload
@@ -495,34 +485,36 @@
 ; GCN-NEXT:    buffer_load_dword v17, off, s[0:3], s33 offset:568 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v18, off, s[0:3], s33 offset:572 ; 4-byte Folded Reload
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    v_mov_b32_e32 v12, v15
-; GCN-NEXT:    v_mov_b32_e32 v13, v16
-; GCN-NEXT:    v_mov_b32_e32 v14, v17
-; GCN-NEXT:    v_mov_b32_e32 v15, v18
-; GCN-NEXT:    buffer_store_dword v12, off, s[0:3], s33 offset:496
-; GCN-NEXT:    buffer_store_dword v13, off, s[0:3], s33 offset:500
-; GCN-NEXT:    buffer_store_dword v14, off, s[0:3], s33 offset:504
-; GCN-NEXT:    buffer_store_dword v15, off, s[0:3], s33 offset:508
-; GCN-NEXT:    v_lshrrev_b32_e64 v15, 6, s33
-; GCN-NEXT:    v_add_u32_e32 v15, 0x100, v15
-; GCN-NEXT:    v_add_u32_e32 v0, v15, v0
+; GCN-NEXT:    v_mov_b32_e32 v8, v11
+; GCN-NEXT:    v_mov_b32_e32 v9, v12
+; GCN-NEXT:    v_mov_b32_e32 v10, v13
+; GCN-NEXT:    v_mov_b32_e32 v11, v14
+; GCN-NEXT:    buffer_store_dword v8, off, s[0:3], s33 offset:480
+; GCN-NEXT:    buffer_store_dword v9, off, s[0:3], s33 offset:484
+; GCN-NEXT:    buffer_store_dword v10, off, s[0:3], s33 offset:488
+; GCN-NEXT:    buffer_store_dword v11, off, s[0:3], s33 offset:492
+; GCN-NEXT:    buffer_store_dword v56, off, s[0:3], s33 offset:496
+; GCN-NEXT:    buffer_store_dword v57, off, s[0:3], s33 offset:500
+; GCN-NEXT:    buffer_store_dword v58, off, s[0:3], s33 offset:504
+; GCN-NEXT:    buffer_store_dword v59, off, s[0:3], s33 offset:508
+; GCN-NEXT:    v_lshrrev_b32_e64 v11, 6, s33
+; GCN-NEXT:    v_add_u32_e32 v11, 0x100, v11
+; GCN-NEXT:    v_add_u32_e32 v0, v11, v0
 ; GCN-NEXT:    buffer_load_dword v0, v0, s[0:3], 0 offen
-; GCN-NEXT:    buffer_load_dword v61, off, s[0:3], s33 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v60, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v59, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v58, off, s[0:3], s33 offset:12 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v57, off, s[0:3], s33 offset:16 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v56, off, s[0:3], s33 offset:20 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v47, off, s[0:3], s33 offset:24 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v46, off, s[0:3], s33 offset:28 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v45, off, s[0:3], s33 offset:32 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v44, off, s[0:3], s33 offset:36 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v43, off, s[0:3], s33 offset:40 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v42, off, s[0:3], s33 offset:44 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v41, off, s[0:3], s33 offset:48 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v40, off, s[0:3], s33 offset:52 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v59, off, s[0:3], s33 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v58, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v57, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v56, off, s[0:3], s33 offset:12 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v47, off, s[0:3], s33 offset:16 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v46, off, s[0:3], s33 offset:20 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v45, off, s[0:3], s33 offset:24 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v44, off, s[0:3], s33 offset:28 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v43, off, s[0:3], s33 offset:32 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v42, off, s[0:3], s33 offset:36 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v41, off, s[0:3], s33 offset:40 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v40, off, s[0:3], s33 offset:44 ; 4-byte Folded Reload
 ; GCN-NEXT:    s_mov_b32 s33, s6
-; GCN-NEXT:    s_waitcnt vmcnt(14)
+; GCN-NEXT:    s_waitcnt vmcnt(12)
 ; GCN-NEXT:    v_lshrrev_b32_e32 v0, v1, v0
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
@@ -538,31 +530,54 @@
 ; GCN-NEXT:    s_mov_b32 s6, s33
 ; GCN-NEXT:    s_add_u32 s33, s32, 0x3fc0
 ; GCN-NEXT:    s_and_b32 s33, s33, 0xffffc000
-; GCN-NEXT:    v_add_co_u32_e32 v3, vcc, 64, v0
-; GCN-NEXT:    buffer_store_dword v40, off, s[0:3], s33 offset:52 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v41, off, s[0:3], s33 offset:48 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v42, off, s[0:3], s33 offset:44 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v43, off, s[0:3], s33 offset:40 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s33 offset:36 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], s33 offset:32 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v46, off, s[0:3], s33 offset:28 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v47, off, s[0:3], s33 offset:24 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v56, off, s[0:3], s33 offset:20 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v57, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v58, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v59, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v60, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v61, off, s[0:3], s33 ; 4-byte Folded Spill
-; GCN-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v1, vcc
-; GCN-NEXT:    s_movk_i32 s4, 0x80
-; GCN-NEXT:    global_load_dwordx4 v[8:11], v[3:4], off offset:16
-; GCN-NEXT:    global_load_dwordx4 v[12:15], v[3:4], off offset:32
-; GCN-NEXT:    global_load_dwordx4 v[56:59], v[3:4], off offset:48
+; GCN-NEXT:    v_add_co_u32_e32 v12, vcc, 64, v0
+; GCN-NEXT:    buffer_store_dword v40, off, s[0:3], s33 offset:44 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v41, off, s[0:3], s33 offset:40 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v42, off, s[0:3], s33 offset:36 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v43, off, s[0:3], s33 offset:32 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s33 offset:28 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], s33 offset:24 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v46, off, s[0:3], s33 offset:20 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v47, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v56, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v57, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v58, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v59, off, s[0:3], s33 ; 4-byte Folded Spill
+; GCN-NEXT:    v_addc_co_u32_e32 v13, vcc, 0, v1, vcc
+; GCN-NEXT:    global_load_dwordx4 v[4:7], v[12:13], off offset:16
+; GCN-NEXT:    global_load_dwordx4 v[8:11], v[12:13], off offset:32
 ; GCN-NEXT:    s_mov_b32 s5, 0
-; GCN-NEXT:    v_mov_b32_e32 v3, s4
-; GCN-NEXT:    v_mov_b32_e32 v4, s5
-; GCN-NEXT:    v_add_co_u32_e32 v3, vcc, v0, v3
-; GCN-NEXT:    v_addc_co_u32_e32 v4, vcc, v1, v4, vcc
+; GCN-NEXT:    s_movk_i32 s4, 0x80
+; GCN-NEXT:    v_mov_b32_e32 v17, s5
+; GCN-NEXT:    v_mov_b32_e32 v16, s4
+; GCN-NEXT:    s_movk_i32 s4, 0xc0
+; GCN-NEXT:    s_add_u32 s32, s32, 0x10000
+; GCN-NEXT:    s_sub_u32 s32, s32, 0x10000
+; GCN-NEXT:    s_waitcnt vmcnt(0)
+; GCN-NEXT:    buffer_store_dword v0, off, s[0:3], s33 offset:640 ; 4-byte Folded Spill
+; GCN-NEXT:    s_waitcnt vmcnt(0)
+; GCN-NEXT:    buffer_store_dword v1, off, s[0:3], s33 offset:644 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v2, off, s[0:3], s33 offset:648 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v3, off, s[0:3], s33 offset:652 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v4, off, s[0:3], s33 offset:656 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v5, off, s[0:3], s33 offset:660 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v6, off, s[0:3], s33 offset:664 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v7, off, s[0:3], s33 offset:668 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v8, off, s[0:3], s33 offset:672 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v9, off, s[0:3], s33 offset:676 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v10, off, s[0:3], s33 offset:680 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v11, off, s[0:3], s33 offset:684 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v12, off, s[0:3], s33 offset:688 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v13, off, s[0:3], s33 offset:692 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v14, off, s[0:3], s33 offset:696 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v15, off, s[0:3], s33 offset:700 ; 4-byte Folded Spill
+; GCN-NEXT:    v_add_co_u32_e32 v52, vcc, v0, v16
+; GCN-NEXT:    v_addc_co_u32_e32 v53, vcc, v1, v17, vcc
+; GCN-NEXT:    v_mov_b32_e32 v17, s5
+; GCN-NEXT:    v_mov_b32_e32 v16, s4
+; GCN-NEXT:    v_add_co_u32_e32 v56, vcc, v0, v16
+; GCN-NEXT:    global_load_dwordx4 v[12:15], v[12:13], off offset:48
+; GCN-NEXT:    v_addc_co_u32_e32 v57, vcc, v1, v17, vcc
 ; GCN-NEXT:    global_load_dwordx4 v[16:19], v[0:1], off
 ; GCN-NEXT:    global_load_dwordx4 v[20:23], v[0:1], off offset:16
 ; GCN-NEXT:    global_load_dwordx4 v[24:27], v[0:1], off offset:32
@@ -570,41 +585,15 @@
 ; GCN-NEXT:    global_load_dwordx4 v[32:35], v[0:1], off offset:64
 ; GCN-NEXT:    global_load_dwordx4 v[36:39], v[0:1], off offset:128
 ; GCN-NEXT:    global_load_dwordx4 v[40:43], v[0:1], off offset:192
-; GCN-NEXT:    global_load_dwordx4 v[44:47], v[3:4], off offset:16
-; GCN-NEXT:    global_load_dwordx4 v[48:51], v[3:4], off offset:32
-; GCN-NEXT:    global_load_dwordx4 v[52:55], v[3:4], off offset:48
-; GCN-NEXT:    s_movk_i32 s4, 0xc0
-; GCN-NEXT:    v_mov_b32_e32 v6, s5
-; GCN-NEXT:    v_mov_b32_e32 v5, s4
-; GCN-NEXT:    v_add_co_u32_e32 v60, vcc, v0, v5
-; GCN-NEXT:    v_addc_co_u32_e32 v61, vcc, v1, v6, vcc
+; GCN-NEXT:    global_load_dwordx4 v[44:47], v[52:53], off offset:16
+; GCN-NEXT:    global_load_dwordx4 v[8:11], v[52:53], off offset:32
+; GCN-NEXT:    global_load_dwordx4 v[52:55], v[52:53], off offset:48
+; GCN-NEXT:    global_load_dwordx4 v[48:51], v[56:57], off offset:16
 ; GCN-NEXT:    v_and_b32_e32 v0, 31, v2
 ; GCN-NEXT:    v_lshrrev_b32_e64 v2, 6, s33
 ; GCN-NEXT:    v_lshlrev_b32_e32 v0, 3, v0
 ; GCN-NEXT:    v_add_u32_e32 v2, 0x100, v2
 ; GCN-NEXT:    v_add_u32_e32 v1, v2, v0
-; GCN-NEXT:    s_add_u32 s32, s32, 0x10000
-; GCN-NEXT:    s_sub_u32 s32, s32, 0x10000
-; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    buffer_store_dword v40, off, s[0:3], s33 offset:640 ; 4-byte Folded Spill
-; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    buffer_store_dword v41, off, s[0:3], s33 offset:644 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v42, off, s[0:3], s33 offset:648 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v43, off, s[0:3], s33 offset:652 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s33 offset:656 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], s33 offset:660 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v46, off, s[0:3], s33 offset:664 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v47, off, s[0:3], s33 offset:668 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v48, off, s[0:3], s33 offset:672 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v49, off, s[0:3], s33 offset:676 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v50, off, s[0:3], s33 offset:680 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v51, off, s[0:3], s33 offset:684 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v52, off, s[0:3], s33 offset:688 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v53, off, s[0:3], s33 offset:692 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v54, off, s[0:3], s33 offset:696 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v55, off, s[0:3], s33 offset:700 ; 4-byte Folded Spill
-; GCN-NEXT:    global_load_dwordx4 v[4:7], v[60:61], off offset:16
-; GCN-NEXT:    global_load_dwordx4 v[52:55], v[60:61], off offset:32
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
 ; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s33 offset:576 ; 4-byte Folded Spill
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
@@ -623,7 +612,7 @@
 ; GCN-NEXT:    buffer_store_dword v57, off, s[0:3], s33 offset:628 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v58, off, s[0:3], s33 offset:632 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v59, off, s[0:3], s33 offset:636 ; 4-byte Folded Spill
-; GCN-NEXT:    global_load_dwordx4 v[52:55], v[60:61], off offset:48
+; GCN-NEXT:    global_load_dwordx4 v[48:51], v[56:57], off offset:32
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
 ; GCN-NEXT:    buffer_store_dword v40, off, s[0:3], s33 offset:512 ; 4-byte Folded Spill
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
@@ -642,6 +631,7 @@
 ; GCN-NEXT:    buffer_store_dword v53, off, s[0:3], s33 offset:564 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v54, off, s[0:3], s33 offset:568 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v55, off, s[0:3], s33 offset:572 ; 4-byte Folded Spill
+; GCN-NEXT:    global_load_dwordx4 v[56:59], v[56:57], off offset:48
 ; GCN-NEXT:    buffer_store_dword v16, off, s[0:3], s33 offset:256
 ; GCN-NEXT:    buffer_store_dword v17, off, s[0:3], s33 offset:260
 ; GCN-NEXT:    buffer_store_dword v18, off, s[0:3], s33 offset:264
@@ -666,59 +656,55 @@
 ; GCN-NEXT:    buffer_store_dword v37, off, s[0:3], s33 offset:388
 ; GCN-NEXT:    buffer_store_dword v38, off, s[0:3], s33 offset:392
 ; GCN-NEXT:    buffer_store_dword v39, off, s[0:3], s33 offset:396
-; GCN-NEXT:    buffer_store_dword v8, off, s[0:3], s33 offset:336
-; GCN-NEXT:    buffer_store_dword v9, off, s[0:3], s33 offset:340
-; GCN-NEXT:    buffer_store_dword v10, off, s[0:3], s33 offset:344
-; GCN-NEXT:    buffer_store_dword v11, off, s[0:3], s33 offset:348
-; GCN-NEXT:    buffer_store_dword v12, off, s[0:3], s33 offset:352
-; GCN-NEXT:    buffer_store_dword v13, off, s[0:3], s33 offset:356
-; GCN-NEXT:    buffer_store_dword v14, off, s[0:3], s33 offset:360
-; GCN-NEXT:    buffer_store_dword v15, off, s[0:3], s33 offset:364
-; GCN-NEXT:    buffer_store_dword v56, off, s[0:3], s33 offset:368
-; GCN-NEXT:    buffer_store_dword v57, off, s[0:3], s33 offset:372
-; GCN-NEXT:    buffer_store_dword v58, off, s[0:3], s33 offset:376
-; GCN-NEXT:    buffer_store_dword v59, off, s[0:3], s33 offset:380
-; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s33 offset:400
-; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], s33 offset:404
-; GCN-NEXT:    buffer_store_dword v46, off, s[0:3], s33 offset:408
-; GCN-NEXT:    buffer_store_dword v47, off, s[0:3], s33 offset:412
-; GCN-NEXT:    buffer_store_dword v48, off, s[0:3], s33 offset:416
-; GCN-NEXT:    buffer_store_dword v49, off, s[0:3], s33 offset:420
-; GCN-NEXT:    buffer_store_dword v50, off, s[0:3], s33 offset:424
-; GCN-NEXT:    buffer_store_dword v51, off, s[0:3], s33 offset:428
-; GCN-NEXT:    buffer_load_dword v8, off, s[0:3], s33 offset:640 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v9, off, s[0:3], s33 offset:644 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v10, off, s[0:3], s33 offset:648 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v11, off, s[0:3], s33 offset:652 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v12, off, s[0:3], s33 offset:656 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v13, off, s[0:3], s33 offset:660 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v14, off, s[0:3], s33 offset:664 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v15, off, s[0:3], s33 offset:668 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v16, off, s[0:3], s33 offset:672 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v17, off, s[0:3], s33 offset:676 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v18, off, s[0:3], s33 offset:680 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v19, off, s[0:3], s33 offset:684 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v20, off, s[0:3], s33 offset:688 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v21, off, s[0:3], s33 offset:692 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v22, off, s[0:3], s33 offset:696 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v23, off, s[0:3], s33 offset:700 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_store_dword v4, off, s[0:3], s33 offset:336
+; GCN-NEXT:    buffer_store_dword v5, off, s[0:3], s33 offset:340
+; GCN-NEXT:    buffer_store_dword v6, off, s[0:3], s33 offset:344
+; GCN-NEXT:    buffer_store_dword v7, off, s[0:3], s33 offset:348
+; GCN-NEXT:    buffer_load_dword v16, off, s[0:3], s33 offset:640 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v17, off, s[0:3], s33 offset:644 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v18, off, s[0:3], s33 offset:648 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v19, off, s[0:3], s33 offset:652 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v20, off, s[0:3], s33 offset:656 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v21, off, s[0:3], s33 offset:660 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v22, off, s[0:3], s33 offset:664 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v23, off, s[0:3], s33 offset:668 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v24, off, s[0:3], s33 offset:672 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v25, off, s[0:3], s33 offset:676 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v26, off, s[0:3], s33 offset:680 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v27, off, s[0:3], s33 offset:684 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v28, off, s[0:3], s33 offset:688 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v29, off, s[0:3], s33 offset:692 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v30, off, s[0:3], s33 offset:696 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v31, off, s[0:3], s33 offset:700 ; 4-byte Folded Reload
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    v_mov_b32_e32 v12, v20
-; GCN-NEXT:    v_mov_b32_e32 v13, v21
-; GCN-NEXT:    v_mov_b32_e32 v14, v22
-; GCN-NEXT:    v_mov_b32_e32 v15, v23
-; GCN-NEXT:    buffer_store_dword v12, off, s[0:3], s33 offset:432
-; GCN-NEXT:    buffer_store_dword v13, off, s[0:3], s33 offset:436
-; GCN-NEXT:    buffer_store_dword v14, off, s[0:3], s33 offset:440
-; GCN-NEXT:    buffer_store_dword v15, off, s[0:3], s33 offset:444
+; GCN-NEXT:    v_mov_b32_e32 v16, v24
+; GCN-NEXT:    v_mov_b32_e32 v17, v25
+; GCN-NEXT:    v_mov_b32_e32 v18, v26
+; GCN-NEXT:    v_mov_b32_e32 v19, v27
+; GCN-NEXT:    buffer_store_dword v16, off, s[0:3], s33 offset:352
+; GCN-NEXT:    buffer_store_dword v17, off, s[0:3], s33 offset:356
+; GCN-NEXT:    buffer_store_dword v18, off, s[0:3], s33 offset:360
+; GCN-NEXT:    buffer_store_dword v19, off, s[0:3], s33 offset:364
+; GCN-NEXT:    buffer_store_dword v12, off, s[0:3], s33 offset:368
+; GCN-NEXT:    buffer_store_dword v13, off, s[0:3], s33 offset:372
+; GCN-NEXT:    buffer_store_dword v14, off, s[0:3], s33 offset:376
+; GCN-NEXT:    buffer_store_dword v15, off, s[0:3], s33 offset:380
 ; GCN-NEXT:    buffer_store_dword v40, off, s[0:3], s33 offset:448
 ; GCN-NEXT:    buffer_store_dword v41, off, s[0:3], s33 offset:452
 ; GCN-NEXT:    buffer_store_dword v42, off, s[0:3], s33 offset:456
 ; GCN-NEXT:    buffer_store_dword v43, off, s[0:3], s33 offset:460
-; GCN-NEXT:    buffer_store_dword v4, off, s[0:3], s33 offset:464
-; GCN-NEXT:    buffer_store_dword v5, off, s[0:3], s33 offset:468
-; GCN-NEXT:    buffer_store_dword v6, off, s[0:3], s33 offset:472
-; GCN-NEXT:    buffer_store_dword v7, off, s[0:3], s33 offset:476
+; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s33 offset:400
+; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], s33 offset:404
+; GCN-NEXT:    buffer_store_dword v46, off, s[0:3], s33 offset:408
+; GCN-NEXT:    buffer_store_dword v47, off, s[0:3], s33 offset:412
+; GCN-NEXT:    buffer_store_dword v8, off, s[0:3], s33 offset:416
+; GCN-NEXT:    buffer_store_dword v9, off, s[0:3], s33 offset:420
+; GCN-NEXT:    buffer_store_dword v10, off, s[0:3], s33 offset:424
+; GCN-NEXT:    buffer_store_dword v11, off, s[0:3], s33 offset:428
+; GCN-NEXT:    buffer_store_dword v52, off, s[0:3], s33 offset:432
+; GCN-NEXT:    buffer_store_dword v53, off, s[0:3], s33 offset:436
+; GCN-NEXT:    buffer_store_dword v54, off, s[0:3], s33 offset:440
+; GCN-NEXT:    buffer_store_dword v55, off, s[0:3], s33 offset:444
 ; GCN-NEXT:    buffer_load_dword v3, off, s[0:3], s33 offset:576 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v4, off, s[0:3], s33 offset:580 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v5, off, s[0:3], s33 offset:584 ; 4-byte Folded Reload
@@ -736,14 +722,14 @@
 ; GCN-NEXT:    buffer_load_dword v17, off, s[0:3], s33 offset:632 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v18, off, s[0:3], s33 offset:636 ; 4-byte Folded Reload
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    v_mov_b32_e32 v8, v11
-; GCN-NEXT:    v_mov_b32_e32 v9, v12
-; GCN-NEXT:    v_mov_b32_e32 v10, v13
-; GCN-NEXT:    v_mov_b32_e32 v11, v14
-; GCN-NEXT:    buffer_store_dword v8, off, s[0:3], s33 offset:480
-; GCN-NEXT:    buffer_store_dword v9, off, s[0:3], s33 offset:484
-; GCN-NEXT:    buffer_store_dword v10, off, s[0:3], s33 offset:488
-; GCN-NEXT:    buffer_store_dword v11, off, s[0:3], s33 offset:492
+; GCN-NEXT:    v_mov_b32_e32 v4, v7
+; GCN-NEXT:    v_mov_b32_e32 v5, v8
+; GCN-NEXT:    v_mov_b32_e32 v6, v9
+; GCN-NEXT:    v_mov_b32_e32 v7, v10
+; GCN-NEXT:    buffer_store_dword v4, off, s[0:3], s33 offset:464
+; GCN-NEXT:    buffer_store_dword v5, off, s[0:3], s33 offset:468
+; GCN-NEXT:    buffer_store_dword v6, off, s[0:3], s33 offset:472
+; GCN-NEXT:    buffer_store_dword v7, off, s[0:3], s33 offset:476
 ; GCN-NEXT:    buffer_load_dword v3, off, s[0:3], s33 offset:512 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v4, off, s[0:3], s33 offset:516 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v5, off, s[0:3], s33 offset:520 ; 4-byte Folded Reload
@@ -761,30 +747,32 @@
 ; GCN-NEXT:    buffer_load_dword v17, off, s[0:3], s33 offset:568 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v18, off, s[0:3], s33 offset:572 ; 4-byte Folded Reload
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    v_mov_b32_e32 v12, v15
-; GCN-NEXT:    v_mov_b32_e32 v13, v16
-; GCN-NEXT:    v_mov_b32_e32 v14, v17
-; GCN-NEXT:    v_mov_b32_e32 v15, v18
-; GCN-NEXT:    buffer_store_dword v12, off, s[0:3], s33 offset:496
-; GCN-NEXT:    buffer_store_dword v13, off, s[0:3], s33 offset:500
-; GCN-NEXT:    buffer_store_dword v14, off, s[0:3], s33 offset:504
-; GCN-NEXT:    buffer_store_dword v15, off, s[0:3], s33 offset:508
+; GCN-NEXT:    v_mov_b32_e32 v8, v11
+; GCN-NEXT:    v_mov_b32_e32 v9, v12
+; GCN-NEXT:    v_mov_b32_e32 v10, v13
+; GCN-NEXT:    v_mov_b32_e32 v11, v14
+; GCN-NEXT:    buffer_store_dword v8, off, s[0:3], s33 offset:480
+; GCN-NEXT:    buffer_store_dword v9, off, s[0:3], s33 offset:484
+; GCN-NEXT:    buffer_store_dword v10, off, s[0:3], s33 offset:488
+; GCN-NEXT:    buffer_store_dword v11, off, s[0:3], s33 offset:492
+; GCN-NEXT:    buffer_store_dword v56, off, s[0:3], s33 offset:496
+; GCN-NEXT:    buffer_store_dword v57, off, s[0:3], s33 offset:500
+; GCN-NEXT:    buffer_store_dword v58, off, s[0:3], s33 offset:504
+; GCN-NEXT:    buffer_store_dword v59, off, s[0:3], s33 offset:508
 ; GCN-NEXT:    buffer_load_dword v0, v1, s[0:3], 0 offen
 ; GCN-NEXT:    buffer_load_dword v1, v1, s[0:3], 0 offen offset:4
-; GCN-NEXT:    buffer_load_dword v61, off, s[0:3], s33 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v60, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v59, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v58, off, s[0:3], s33 offset:12 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v57, off, s[0:3], s33 offset:16 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v56, off, s[0:3], s33 offset:20 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v47, off, s[0:3], s33 offset:24 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v46, off, s[0:3], s33 offset:28 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v45, off, s[0:3], s33 offset:32 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v44, off, s[0:3], s33 offset:36 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v43, off, s[0:3], s33 offset:40 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v42, off, s[0:3], s33 offset:44 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v41, off, s[0:3], s33 offset:48 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v40, off, s[0:3], s33 offset:52 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v59, off, s[0:3], s33 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v58, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v57, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v56, off, s[0:3], s33 offset:12 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v47, off, s[0:3], s33 offset:16 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v46, off, s[0:3], s33 offset:20 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v45, off, s[0:3], s33 offset:24 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v44, off, s[0:3], s33 offset:28 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v43, off, s[0:3], s33 offset:32 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v42, off, s[0:3], s33 offset:36 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v41, off, s[0:3], s33 offset:40 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v40, off, s[0:3], s33 offset:44 ; 4-byte Folded Reload
 ; GCN-NEXT:    s_mov_b32 s33, s6
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
@@ -422,17 +422,17 @@
 ; GFX6-IEEE-NEXT:    v_fma_f32 v7, v8, v5, v7
 ; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v4, v7, v6
 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v5, v7
+; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, s[4:5], v1, v1, v0
+; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v6, v5
 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v2, v4, v3, v2
-; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, v0
-; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v4, v3
-; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, vcc, v0, v1, v0
+; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, vcc, v0, v1, v0
 ; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v2, v2
-; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v3, v4, 1.0
-; GFX6-IEEE-NEXT:    v_fma_f32 v4, v6, v4, v4
-; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v5, v4
-; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v3, v6, v5
+; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v5, v6, 1.0
+; GFX6-IEEE-NEXT:    v_fma_f32 v4, v4, v6, v6
+; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v3, v4
+; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v5, v6, v3
 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
-; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v3, v6, v5
+; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v5, v6, v3
 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v4, v6
 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v3, v1, v0
 ; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v0, v0
@@ -601,17 +601,17 @@
 ; GFX6-IEEE-NEXT:    v_fma_f32 v7, v8, v5, v7
 ; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v4, v7, v6
 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v5, v7
+; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, s[4:5], v1, v1, v0
+; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v6, v5
 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v2, v4, v3, v2
-; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, v0
-; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v4, v3
-; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, vcc, v0, v1, v0
+; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, vcc, v0, v1, v0
 ; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v2, v2
-; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v3, v4, 1.0
-; GFX6-IEEE-NEXT:    v_fma_f32 v4, v6, v4, v4
-; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v5, v4
-; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v3, v6, v5
+; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v5, v6, 1.0
+; GFX6-IEEE-NEXT:    v_fma_f32 v4, v4, v6, v6
+; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v3, v4
+; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v5, v6, v3
 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
-; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v3, v6, v5
+; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v5, v6, v3
 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v4, v6
 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v3, v1, v0
 ; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v0, v0
@@ -730,18 +730,18 @@
 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
 ; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v3, v6, v5
 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v4, v6
+; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, s[4:5], v0, v0, v1
+; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v5, v4
 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v2, v3, v2, v1
-; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, s[4:5], v0, v0, v1
-; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v4, v3
-; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, vcc, v1, v0, v1
+; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, vcc, v1, v0, v1
 ; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v2, v2
-; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v3, v4, 1.0
-; GFX6-IEEE-NEXT:    v_fma_f32 v4, v6, v4, v4
-; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v5, v4
-; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v3, v6, v5
-; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
-; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v3, v6, v5
-; GFX6-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v4, v6
+; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v4, v5, 1.0
+; GFX6-IEEE-NEXT:    v_fma_f32 v5, v6, v5, v5
+; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v3, v5
+; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v4, v6, v3
+; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v5, v6
+; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v4, v6, v3
+; GFX6-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v5, v6
 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v3, v0, v1
 ; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v0, v0
 ; GFX6-IEEE-NEXT:    v_bfe_u32 v1, v2, 0, 16
@@ -768,25 +768,25 @@
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v6, v7, v4, v6
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v3, -v3, v6, v5
 ; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v3, v3, v4, v6
-; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v4, s6
+; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v5, s6
 ; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v3, v3, v4, v6
 ; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v1, v3, v2, v1
 ; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
 ; GFX6-FLUSH-NEXT:    v_cvt_f16_f32_e32 v1, v1
-; GFX6-FLUSH-NEXT:    v_div_scale_f32 v2, s[4:5], v0, v0, v4
+; GFX6-FLUSH-NEXT:    v_div_scale_f32 v2, s[4:5], v0, v0, v5
 ; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v3, v2
-; GFX6-FLUSH-NEXT:    v_div_scale_f32 v5, vcc, v4, v0, v4
+; GFX6-FLUSH-NEXT:    v_div_scale_f32 v4, vcc, v5, v0, v5
 ; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v2, v3, 1.0
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v3, v6, v3, v3
-; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v6, v5, v3
-; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v2, v6, v5
+; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v6, v4, v3
+; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v2, v6, v4
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v6, v7, v3, v6
-; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v2, v6, v5
+; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v2, v6, v4
 ; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
 ; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v3, v6
-; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v0, v2, v0, v4
+; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v0, v2, v0, v5
 ; GFX6-FLUSH-NEXT:    v_cvt_f16_f32_e32 v0, v0
 ; GFX6-FLUSH-NEXT:    v_bfe_u32 v1, v1, 0, 16
 ; GFX6-FLUSH-NEXT:    v_bfe_u32 v0, v0, 0, 16
@@ -855,18 +855,18 @@
 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
 ; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v3, v6, v5
 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v4, v6
+; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, s[4:5], v0, v0, v1
+; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v5, v4
 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v2, v3, v2, v1
-; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, s[4:5], v0, v0, v1
-; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v4, v3
-; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, vcc, v1, v0, v1
+; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, vcc, v1, v0, v1
 ; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v2, v2
-; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v3, v4, 1.0
-; GFX6-IEEE-NEXT:    v_fma_f32 v4, v6, v4, v4
-; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v5, v4
-; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v3, v6, v5
-; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
-; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v3, v6, v5
-; GFX6-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v4, v6
+; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v4, v5, 1.0
+; GFX6-IEEE-NEXT:    v_fma_f32 v5, v6, v5, v5
+; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v3, v5
+; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v4, v6, v3
+; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v5, v6
+; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v4, v6, v3
+; GFX6-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v5, v6
 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v3, v0, v1
 ; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v0, v0
 ; GFX6-IEEE-NEXT:    v_bfe_u32 v1, v2, 0, 16
@@ -893,25 +893,25 @@
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v6, v7, v4, v6
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v3, -v3, v6, v5
 ; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v3, v3, v4, v6
-; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v4, s6
+; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v5, s6
 ; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v3, v3, v4, v6
 ; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v1, v3, v2, v1
 ; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
 ; GFX6-FLUSH-NEXT:    v_cvt_f16_f32_e32 v1, v1
-; GFX6-FLUSH-NEXT:    v_div_scale_f32 v2, s[4:5], v0, v0, v4
+; GFX6-FLUSH-NEXT:    v_div_scale_f32 v2, s[4:5], v0, v0, v5
 ; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v3, v2
-; GFX6-FLUSH-NEXT:    v_div_scale_f32 v5, vcc, v4, v0, v4
+; GFX6-FLUSH-NEXT:    v_div_scale_f32 v4, vcc, v5, v0, v5
 ; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v2, v3, 1.0
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v3, v6, v3, v3
-; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v6, v5, v3
-; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v2, v6, v5
+; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v6, v4, v3
+; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v2, v6, v4
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v6, v7, v3, v6
-; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v2, v6, v5
+; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v2, v6, v4
 ; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
 ; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v3, v6
-; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v0, v2, v0, v4
+; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v0, v2, v0, v5
 ; GFX6-FLUSH-NEXT:    v_cvt_f16_f32_e32 v0, v0
 ; GFX6-FLUSH-NEXT:    v_bfe_u32 v1, v1, 0, 16
 ; GFX6-FLUSH-NEXT:    v_bfe_u32 v0, v0, 0, 16
@@ -1022,18 +1022,18 @@
 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
 ; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v3, v6, v5
 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v4, v6
+; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, s[4:5], v0, v0, v1
+; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v5, v4
 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v2, v3, v2, v1
-; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, s[4:5], v0, v0, v1
-; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v4, v3
-; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, vcc, v1, v0, v1
+; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, vcc, v1, v0, v1
 ; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v2, v2
-; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v3, v4, 1.0
-; GFX6-IEEE-NEXT:    v_fma_f32 v4, v6, v4, v4
-; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v5, v4
-; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v3, v6, v5
-; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
-; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v3, v6, v5
-; GFX6-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v4, v6
+; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v4, v5, 1.0
+; GFX6-IEEE-NEXT:    v_fma_f32 v5, v6, v5, v5
+; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v3, v5
+; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v4, v6, v3
+; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v5, v6
+; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v4, v6, v3
+; GFX6-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v5, v6
 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v3, v0, v1
 ; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v0, v0
 ; GFX6-IEEE-NEXT:    v_bfe_u32 v1, v2, 0, 16
@@ -1060,25 +1060,25 @@
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v6, v7, v4, v6
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v3, -v3, v6, v5
 ; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v3, v3, v4, v6
-; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v4, s6
+; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v5, s6
 ; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v3, v3, v4, v6
 ; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v1, v3, v2, v1
 ; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
 ; GFX6-FLUSH-NEXT:    v_cvt_f16_f32_e32 v1, v1
-; GFX6-FLUSH-NEXT:    v_div_scale_f32 v2, s[4:5], v0, v0, v4
+; GFX6-FLUSH-NEXT:    v_div_scale_f32 v2, s[4:5], v0, v0, v5
 ; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v3, v2
-; GFX6-FLUSH-NEXT:    v_div_scale_f32 v5, vcc, v4, v0, v4
+; GFX6-FLUSH-NEXT:    v_div_scale_f32 v4, vcc, v5, v0, v5
 ; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v2, v3, 1.0
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v3, v6, v3, v3
-; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v6, v5, v3
-; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v2, v6, v5
+; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v6, v4, v3
+; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v2, v6, v4
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v6, v7, v3, v6
-; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v2, v6, v5
+; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v2, v6, v4
 ; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
 ; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v3, v6
-; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v0, v2, v0, v4
+; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v0, v2, v0, v5
 ; GFX6-FLUSH-NEXT:    v_cvt_f16_f32_e32 v0, v0
 ; GFX6-FLUSH-NEXT:    v_bfe_u32 v1, v1, 0, 16
 ; GFX6-FLUSH-NEXT:    v_bfe_u32 v0, v0, 0, 16
@@ -1176,17 +1176,17 @@
 ; GFX6-IEEE-NEXT:    v_fma_f32 v7, v8, v5, v7
 ; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v4, v7, v6
 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v5, v7
+; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, s[4:5], v1, v1, v0
+; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v6, v5
 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v2, v4, v3, v2
-; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, v0
-; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v4, v3
-; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, vcc, v0, v1, v0
+; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, vcc, v0, v1, v0
 ; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v2, v2
-; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v3, v4, 1.0
-; GFX6-IEEE-NEXT:    v_fma_f32 v4, v6, v4, v4
-; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v5, v4
-; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v3, v6, v5
+; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v5, v6, 1.0
+; GFX6-IEEE-NEXT:    v_fma_f32 v4, v4, v6, v6
+; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v3, v4
+; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v5, v6, v3
 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
-; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v3, v6, v5
+; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v5, v6, v3
 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v4, v6
 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v3, v1, v0
 ; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v0, v0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
@@ -390,18 +390,18 @@
 ; GFX6-IEEE-NEXT:    v_fma_f32 v8, -v4, v7, v6
 ; GFX6-IEEE-NEXT:    v_fma_f32 v7, v8, v5, v7
 ; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v4, v7, v6
+; GFX6-IEEE-NEXT:    v_div_scale_f32 v6, s[4:5], v3, v3, v1
+; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v8, v6
 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v5, v7
-; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, s[4:5], v3, v3, v1
-; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v6, v5
 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, vcc, v1, v3, v1
-; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v5, v6, 1.0
-; GFX6-IEEE-NEXT:    v_fma_f32 v4, v4, v6, v6
-; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v2, v4
-; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v5, v6, v2
-; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
-; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v5, v6, v2
-; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v6
+; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v6, v8, 1.0
+; GFX6-IEEE-NEXT:    v_fma_f32 v4, v4, v8, v8
+; GFX6-IEEE-NEXT:    v_mul_f32_e32 v5, v2, v4
+; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v6, v5, v2
+; GFX6-IEEE-NEXT:    v_fma_f32 v5, v7, v4, v5
+; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v6, v5, v2
+; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v1, v2, v3, v1
 ; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
 ;
@@ -419,20 +419,20 @@
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v7, v8, v5, v7
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v4, -v4, v7, v6
 ; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FLUSH-NEXT:    v_div_scale_f32 v6, s[4:5], v3, v3, v1
 ; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v4, v4, v5, v7
-; GFX6-FLUSH-NEXT:    v_div_scale_f32 v5, s[4:5], v3, v3, v1
 ; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
-; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v6, v5
+; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v8, v6
 ; GFX6-FLUSH-NEXT:    v_div_scale_f32 v2, vcc, v1, v3, v1
 ; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; GFX6-FLUSH-NEXT:    v_fma_f32 v4, -v5, v6, 1.0
-; GFX6-FLUSH-NEXT:    v_fma_f32 v4, v4, v6, v6
-; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v6, v2, v4
-; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v5, v6, v2
-; GFX6-FLUSH-NEXT:    v_fma_f32 v6, v7, v4, v6
-; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v5, v6, v2
+; GFX6-FLUSH-NEXT:    v_fma_f32 v4, -v6, v8, 1.0
+; GFX6-FLUSH-NEXT:    v_fma_f32 v4, v4, v8, v8
+; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v5, v2, v4
+; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v6, v5, v2
+; GFX6-FLUSH-NEXT:    v_fma_f32 v5, v7, v4, v5
+; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v6, v5, v2
 ; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v4, v6
+; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
 ; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v1, v2, v3, v1
 ; GFX6-FLUSH-NEXT:    s_setpc_b64 s[30:31]
 ;
@@ -524,18 +524,18 @@
 ; GFX6-IEEE-NEXT:    v_fma_f32 v8, -v4, v7, v6
 ; GFX6-IEEE-NEXT:    v_fma_f32 v7, v8, v5, v7
 ; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v4, v7, v6
+; GFX6-IEEE-NEXT:    v_div_scale_f32 v6, s[4:5], v3, v3, v1
+; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v8, v6
 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v5, v7
-; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, s[4:5], v3, v3, v1
-; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v6, v5
 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, vcc, v1, v3, v1
-; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v5, v6, 1.0
-; GFX6-IEEE-NEXT:    v_fma_f32 v4, v4, v6, v6
-; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v2, v4
-; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v5, v6, v2
-; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
-; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v5, v6, v2
-; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v6
+; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v6, v8, 1.0
+; GFX6-IEEE-NEXT:    v_fma_f32 v4, v4, v8, v8
+; GFX6-IEEE-NEXT:    v_mul_f32_e32 v5, v2, v4
+; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v6, v5, v2
+; GFX6-IEEE-NEXT:    v_fma_f32 v5, v7, v4, v5
+; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v6, v5, v2
+; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v1, v2, v3, v1
 ; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
 ;
@@ -602,18 +602,18 @@
 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v2, v5, v4
 ; GFX6-IEEE-NEXT:    v_fma_f32 v5, v6, v3, v5
 ; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v2, v5, v4
+; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, s[4:5], v1, v1, 1.0
+; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v6, v4
 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
-; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
-; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v4, v3
 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0
 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, vcc, 1.0, v1, 1.0
-; GFX6-IEEE-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
-; GFX6-IEEE-NEXT:    v_fma_f32 v4, v5, v4, v4
-; GFX6-IEEE-NEXT:    v_mul_f32_e32 v5, v2, v4
-; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v3, v5, v2
-; GFX6-IEEE-NEXT:    v_fma_f32 v5, v6, v4, v5
-; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v3, v5, v2
-; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v4, v6, 1.0
+; GFX6-IEEE-NEXT:    v_fma_f32 v3, v3, v6, v6
+; GFX6-IEEE-NEXT:    v_mul_f32_e32 v5, v2, v3
+; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v4, v5, v2
+; GFX6-IEEE-NEXT:    v_fma_f32 v5, v6, v3, v5
+; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v4, v5, v2
+; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v1, v2, v1, 1.0
 ; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
 ;
@@ -631,20 +631,20 @@
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v5, v6, v3, v5
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v2, v5, v4
 ; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FLUSH-NEXT:    v_div_scale_f32 v4, s[4:5], v1, v1, 1.0
 ; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
-; GFX6-FLUSH-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
 ; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0
-; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v4, v3
+; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v6, v4
 ; GFX6-FLUSH-NEXT:    v_div_scale_f32 v2, vcc, 1.0, v1, 1.0
 ; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; GFX6-FLUSH-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
-; GFX6-FLUSH-NEXT:    v_fma_f32 v4, v5, v4, v4
-; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v5, v2, v4
-; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v3, v5, v2
-; GFX6-FLUSH-NEXT:    v_fma_f32 v5, v6, v4, v5
-; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v3, v5, v2
+; GFX6-FLUSH-NEXT:    v_fma_f32 v3, -v4, v6, 1.0
+; GFX6-FLUSH-NEXT:    v_fma_f32 v3, v3, v6, v6
+; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v5, v2, v3
+; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v4, v5, v2
+; GFX6-FLUSH-NEXT:    v_fma_f32 v5, v6, v3, v5
+; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v4, v5, v2
 ; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
 ; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v1, v2, v1, 1.0
 ; GFX6-FLUSH-NEXT:    s_setpc_b64 s[30:31]
 ;
@@ -723,18 +723,18 @@
 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v2, v5, v4
 ; GFX6-IEEE-NEXT:    v_fma_f32 v5, v6, v3, v5
 ; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v2, v5, v4
+; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, s[4:5], v1, v1, 1.0
+; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v6, v4
 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
-; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
-; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v4, v3
 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0
 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, vcc, 1.0, v1, 1.0
-; GFX6-IEEE-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
-; GFX6-IEEE-NEXT:    v_fma_f32 v4, v5, v4, v4
-; GFX6-IEEE-NEXT:    v_mul_f32_e32 v5, v2, v4
-; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v3, v5, v2
-; GFX6-IEEE-NEXT:    v_fma_f32 v5, v6, v4, v5
-; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v3, v5, v2
-; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v4, v6, 1.0
+; GFX6-IEEE-NEXT:    v_fma_f32 v3, v3, v6, v6
+; GFX6-IEEE-NEXT:    v_mul_f32_e32 v5, v2, v3
+; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v4, v5, v2
+; GFX6-IEEE-NEXT:    v_fma_f32 v5, v6, v3, v5
+; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v4, v5, v2
+; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v1, v2, v1, 1.0
 ; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
 ;
@@ -752,20 +752,20 @@
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v5, v6, v3, v5
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v2, v5, v4
 ; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FLUSH-NEXT:    v_div_scale_f32 v4, s[4:5], v1, v1, 1.0
 ; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
-; GFX6-FLUSH-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
 ; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0
-; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v4, v3
+; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v6, v4
 ; GFX6-FLUSH-NEXT:    v_div_scale_f32 v2, vcc, 1.0, v1, 1.0
 ; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; GFX6-FLUSH-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
-; GFX6-FLUSH-NEXT:    v_fma_f32 v4, v5, v4, v4
-; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v5, v2, v4
-; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v3, v5, v2
-; GFX6-FLUSH-NEXT:    v_fma_f32 v5, v6, v4, v5
-; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v3, v5, v2
+; GFX6-FLUSH-NEXT:    v_fma_f32 v3, -v4, v6, 1.0
+; GFX6-FLUSH-NEXT:    v_fma_f32 v3, v3, v6, v6
+; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v5, v2, v3
+; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v4, v5, v2
+; GFX6-FLUSH-NEXT:    v_fma_f32 v5, v6, v3, v5
+; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v4, v5, v2
 ; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
 ; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v1, v2, v1, 1.0
 ; GFX6-FLUSH-NEXT:    s_setpc_b64 s[30:31]
 ;
@@ -898,18 +898,18 @@
 ; GFX6-IEEE-NEXT:    v_fma_f32 v8, -v4, v7, v6
 ; GFX6-IEEE-NEXT:    v_fma_f32 v7, v8, v5, v7
 ; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v4, v7, v6
+; GFX6-IEEE-NEXT:    v_div_scale_f32 v6, s[4:5], v3, v3, v1
+; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v8, v6
 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v5, v7
-; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, s[4:5], v3, v3, v1
-; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v6, v5
 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, vcc, v1, v3, v1
-; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v5, v6, 1.0
-; GFX6-IEEE-NEXT:    v_fma_f32 v4, v4, v6, v6
-; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v2, v4
-; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v5, v6, v2
-; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
-; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v5, v6, v2
-; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v6
+; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v6, v8, 1.0
+; GFX6-IEEE-NEXT:    v_fma_f32 v4, v4, v8, v8
+; GFX6-IEEE-NEXT:    v_mul_f32_e32 v5, v2, v4
+; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v6, v5, v2
+; GFX6-IEEE-NEXT:    v_fma_f32 v5, v7, v4, v5
+; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v6, v5, v2
+; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v1, v2, v3, v1
 ; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
 ;
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
@@ -397,30 +397,30 @@
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    v_div_scale_f64 v[8:9], s[4:5], v[4:5], v[4:5], v[0:1]
-; GFX6-NEXT:    v_div_scale_f64 v[14:15], s[4:5], v[6:7], v[6:7], v[2:3]
+; GFX6-NEXT:    v_div_scale_f64 v[12:13], s[4:5], v[6:7], v[6:7], v[2:3]
 ; GFX6-NEXT:    v_div_scale_f64 v[18:19], s[4:5], v[0:1], v[4:5], v[0:1]
 ; GFX6-NEXT:    v_rcp_f64_e32 v[10:11], v[8:9]
-; GFX6-NEXT:    v_rcp_f64_e32 v[16:17], v[14:15]
-; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v19
 ; GFX6-NEXT:    v_cmp_eq_u32_e64 s[4:5], v5, v9
-; GFX6-NEXT:    v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
+; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v19
 ; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
-; GFX6-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
-; GFX6-NEXT:    v_cmp_eq_u32_e64 s[4:5], v7, v15
-; GFX6-NEXT:    v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
-; GFX6-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
-; GFX6-NEXT:    v_fma_f64 v[12:13], -v[14:15], v[16:17], 1.0
-; GFX6-NEXT:    v_fma_f64 v[12:13], v[16:17], v[12:13], v[16:17]
+; GFX6-NEXT:    v_fma_f64 v[14:15], -v[8:9], v[10:11], 1.0
+; GFX6-NEXT:    v_cmp_eq_u32_e64 s[4:5], v7, v13
+; GFX6-NEXT:    v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
+; GFX6-NEXT:    v_rcp_f64_e32 v[14:15], v[12:13]
+; GFX6-NEXT:    v_fma_f64 v[16:17], -v[8:9], v[10:11], 1.0
+; GFX6-NEXT:    v_fma_f64 v[10:11], v[10:11], v[16:17], v[10:11]
+; GFX6-NEXT:    v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0
+; GFX6-NEXT:    v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
 ; GFX6-NEXT:    v_mul_f64 v[16:17], v[18:19], v[10:11]
 ; GFX6-NEXT:    v_fma_f64 v[18:19], -v[8:9], v[16:17], v[18:19]
-; GFX6-NEXT:    v_fma_f64 v[8:9], -v[14:15], v[12:13], 1.0
+; GFX6-NEXT:    v_fma_f64 v[8:9], -v[12:13], v[14:15], 1.0
 ; GFX6-NEXT:    v_div_fmas_f64 v[10:11], v[18:19], v[10:11], v[16:17]
-; GFX6-NEXT:    v_fma_f64 v[8:9], v[12:13], v[8:9], v[12:13]
-; GFX6-NEXT:    v_div_scale_f64 v[12:13], s[6:7], v[2:3], v[6:7], v[2:3]
+; GFX6-NEXT:    v_fma_f64 v[8:9], v[14:15], v[8:9], v[14:15]
+; GFX6-NEXT:    v_div_scale_f64 v[14:15], s[6:7], v[2:3], v[6:7], v[2:3]
 ; GFX6-NEXT:    v_div_fixup_f64 v[0:1], v[10:11], v[4:5], v[0:1]
-; GFX6-NEXT:    v_mul_f64 v[16:17], v[12:13], v[8:9]
-; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v13
-; GFX6-NEXT:    v_fma_f64 v[18:19], -v[14:15], v[16:17], v[12:13]
+; GFX6-NEXT:    v_mul_f64 v[16:17], v[14:15], v[8:9]
+; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v15
+; GFX6-NEXT:    v_fma_f64 v[18:19], -v[12:13], v[16:17], v[14:15]
 ; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
 ; GFX6-NEXT:    s_nop 1
 ; GFX6-NEXT:    v_div_fmas_f64 v[8:9], v[18:19], v[8:9], v[16:17]
@@ -435,22 +435,22 @@
 ; GFX8-NEXT:    v_rcp_f64_e32 v[12:13], v[8:9]
 ; GFX8-NEXT:    v_rcp_f64_e32 v[14:15], v[10:11]
 ; GFX8-NEXT:    v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
-; GFX8-NEXT:    v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
-; GFX8-NEXT:    v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
-; GFX8-NEXT:    v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
-; GFX8-NEXT:    v_div_scale_f64 v[18:19], vcc, v[0:1], v[4:5], v[0:1]
-; GFX8-NEXT:    v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
 ; GFX8-NEXT:    v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
 ; GFX8-NEXT:    v_fma_f64 v[16:17], -v[10:11], v[14:15], 1.0
+; GFX8-NEXT:    v_fma_f64 v[18:19], -v[8:9], v[12:13], 1.0
 ; GFX8-NEXT:    v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
-; GFX8-NEXT:    v_mul_f64 v[16:17], v[18:19], v[12:13]
-; GFX8-NEXT:    v_fma_f64 v[8:9], -v[8:9], v[16:17], v[18:19]
-; GFX8-NEXT:    v_div_scale_f64 v[18:19], s[4:5], v[2:3], v[6:7], v[2:3]
-; GFX8-NEXT:    v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[16:17]
+; GFX8-NEXT:    v_div_scale_f64 v[16:17], vcc, v[0:1], v[4:5], v[0:1]
+; GFX8-NEXT:    v_fma_f64 v[12:13], v[12:13], v[18:19], v[12:13]
+; GFX8-NEXT:    v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
+; GFX8-NEXT:    v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
+; GFX8-NEXT:    v_mul_f64 v[18:19], v[16:17], v[12:13]
+; GFX8-NEXT:    v_fma_f64 v[8:9], -v[8:9], v[18:19], v[16:17]
+; GFX8-NEXT:    v_div_scale_f64 v[16:17], s[4:5], v[2:3], v[6:7], v[2:3]
+; GFX8-NEXT:    v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[18:19]
+; GFX8-NEXT:    v_mul_f64 v[20:21], v[16:17], v[14:15]
 ; GFX8-NEXT:    s_mov_b64 vcc, s[4:5]
-; GFX8-NEXT:    v_mul_f64 v[20:21], v[18:19], v[14:15]
 ; GFX8-NEXT:    v_div_fixup_f64 v[0:1], v[8:9], v[4:5], v[0:1]
-; GFX8-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[20:21], v[18:19]
+; GFX8-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[20:21], v[16:17]
 ; GFX8-NEXT:    v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[20:21]
 ; GFX8-NEXT:    v_div_fixup_f64 v[2:3], v[10:11], v[6:7], v[2:3]
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
@@ -463,22 +463,22 @@
 ; GFX9-NEXT:    v_rcp_f64_e32 v[12:13], v[8:9]
 ; GFX9-NEXT:    v_rcp_f64_e32 v[14:15], v[10:11]
 ; GFX9-NEXT:    v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
-; GFX9-NEXT:    v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
-; GFX9-NEXT:    v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
-; GFX9-NEXT:    v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
-; GFX9-NEXT:    v_div_scale_f64 v[18:19], vcc, v[0:1], v[4:5], v[0:1]
-; GFX9-NEXT:    v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
 ; GFX9-NEXT:    v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
 ; GFX9-NEXT:    v_fma_f64 v[16:17], -v[10:11], v[14:15], 1.0
+; GFX9-NEXT:    v_fma_f64 v[18:19], -v[8:9], v[12:13], 1.0
 ; GFX9-NEXT:    v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
-; GFX9-NEXT:    v_mul_f64 v[16:17], v[18:19], v[12:13]
-; GFX9-NEXT:    v_fma_f64 v[8:9], -v[8:9], v[16:17], v[18:19]
-; GFX9-NEXT:    v_div_scale_f64 v[18:19], s[4:5], v[2:3], v[6:7], v[2:3]
-; GFX9-NEXT:    v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[16:17]
+; GFX9-NEXT:    v_div_scale_f64 v[16:17], vcc, v[0:1], v[4:5], v[0:1]
+; GFX9-NEXT:    v_fma_f64 v[12:13], v[12:13], v[18:19], v[12:13]
+; GFX9-NEXT:    v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
+; GFX9-NEXT:    v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
+; GFX9-NEXT:    v_mul_f64 v[18:19], v[16:17], v[12:13]
+; GFX9-NEXT:    v_fma_f64 v[8:9], -v[8:9], v[18:19], v[16:17]
+; GFX9-NEXT:    v_div_scale_f64 v[16:17], s[4:5], v[2:3], v[6:7], v[2:3]
+; GFX9-NEXT:    v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[18:19]
+; GFX9-NEXT:    v_mul_f64 v[20:21], v[16:17], v[14:15]
 ; GFX9-NEXT:    s_mov_b64 vcc, s[4:5]
-; GFX9-NEXT:    v_mul_f64 v[20:21], v[18:19], v[14:15]
 ; GFX9-NEXT:    v_div_fixup_f64 v[0:1], v[8:9], v[4:5], v[0:1]
-; GFX9-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[20:21], v[18:19]
+; GFX9-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[20:21], v[16:17]
 ; GFX9-NEXT:    v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[20:21]
 ; GFX9-NEXT:    v_div_fixup_f64 v[2:3], v[10:11], v[6:7], v[2:3]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
@@ -516,30 +516,30 @@
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    v_div_scale_f64 v[8:9], s[4:5], v[4:5], v[4:5], v[0:1]
-; GFX6-NEXT:    v_div_scale_f64 v[14:15], s[4:5], v[6:7], v[6:7], v[2:3]
+; GFX6-NEXT:    v_div_scale_f64 v[12:13], s[4:5], v[6:7], v[6:7], v[2:3]
 ; GFX6-NEXT:    v_div_scale_f64 v[18:19], s[4:5], v[0:1], v[4:5], v[0:1]
 ; GFX6-NEXT:    v_rcp_f64_e32 v[10:11], v[8:9]
-; GFX6-NEXT:    v_rcp_f64_e32 v[16:17], v[14:15]
-; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v19
 ; GFX6-NEXT:    v_cmp_eq_u32_e64 s[4:5], v5, v9
-; GFX6-NEXT:    v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
+; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v19
 ; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
-; GFX6-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
-; GFX6-NEXT:    v_cmp_eq_u32_e64 s[4:5], v7, v15
-; GFX6-NEXT:    v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
-; GFX6-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
-; GFX6-NEXT:    v_fma_f64 v[12:13], -v[14:15], v[16:17], 1.0
-; GFX6-NEXT:    v_fma_f64 v[12:13], v[16:17], v[12:13], v[16:17]
+; GFX6-NEXT:    v_fma_f64 v[14:15], -v[8:9], v[10:11], 1.0
+; GFX6-NEXT:    v_cmp_eq_u32_e64 s[4:5], v7, v13
+; GFX6-NEXT:    v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
+; GFX6-NEXT:    v_rcp_f64_e32 v[14:15], v[12:13]
+; GFX6-NEXT:    v_fma_f64 v[16:17], -v[8:9], v[10:11], 1.0
+; GFX6-NEXT:    v_fma_f64 v[10:11], v[10:11], v[16:17], v[10:11]
+; GFX6-NEXT:    v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0
+; GFX6-NEXT:    v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
 ; GFX6-NEXT:    v_mul_f64 v[16:17], v[18:19], v[10:11]
 ; GFX6-NEXT:    v_fma_f64 v[18:19], -v[8:9], v[16:17], v[18:19]
-; GFX6-NEXT:    v_fma_f64 v[8:9], -v[14:15], v[12:13], 1.0
+; GFX6-NEXT:    v_fma_f64 v[8:9], -v[12:13], v[14:15], 1.0
 ; GFX6-NEXT:    v_div_fmas_f64 v[10:11], v[18:19], v[10:11], v[16:17]
-; GFX6-NEXT:    v_fma_f64 v[8:9], v[12:13], v[8:9], v[12:13]
-; GFX6-NEXT:    v_div_scale_f64 v[12:13], s[6:7], v[2:3], v[6:7], v[2:3]
+; GFX6-NEXT:    v_fma_f64 v[8:9], v[14:15], v[8:9], v[14:15]
+; GFX6-NEXT:    v_div_scale_f64 v[14:15], s[6:7], v[2:3], v[6:7], v[2:3]
 ; GFX6-NEXT:    v_div_fixup_f64 v[0:1], v[10:11], v[4:5], v[0:1]
-; GFX6-NEXT:    v_mul_f64 v[16:17], v[12:13], v[8:9]
-; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v13
-; GFX6-NEXT:    v_fma_f64 v[18:19], -v[14:15], v[16:17], v[12:13]
+; GFX6-NEXT:    v_mul_f64 v[16:17], v[14:15], v[8:9]
+; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v15
+; GFX6-NEXT:    v_fma_f64 v[18:19], -v[12:13], v[16:17], v[14:15]
 ; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
 ; GFX6-NEXT:    s_nop 1
 ; GFX6-NEXT:    v_div_fmas_f64 v[8:9], v[18:19], v[8:9], v[16:17]
@@ -554,22 +554,22 @@
 ; GFX8-NEXT:    v_rcp_f64_e32 v[12:13], v[8:9]
 ; GFX8-NEXT:    v_rcp_f64_e32 v[14:15], v[10:11]
 ; GFX8-NEXT:    v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
-; GFX8-NEXT:    v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
-; GFX8-NEXT:    v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
-; GFX8-NEXT:    v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
-; GFX8-NEXT:    v_div_scale_f64 v[18:19], vcc, v[0:1], v[4:5], v[0:1]
-; GFX8-NEXT:    v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
 ; GFX8-NEXT:    v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
 ; GFX8-NEXT:    v_fma_f64 v[16:17], -v[10:11], v[14:15], 1.0
+; GFX8-NEXT:    v_fma_f64 v[18:19], -v[8:9], v[12:13], 1.0
 ; GFX8-NEXT:    v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
-; GFX8-NEXT:    v_mul_f64 v[16:17], v[18:19], v[12:13]
-; GFX8-NEXT:    v_fma_f64 v[8:9], -v[8:9], v[16:17], v[18:19]
-; GFX8-NEXT:    v_div_scale_f64 v[18:19], s[4:5], v[2:3], v[6:7], v[2:3]
-; GFX8-NEXT:    v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[16:17]
+; GFX8-NEXT:    v_div_scale_f64 v[16:17], vcc, v[0:1], v[4:5], v[0:1]
+; GFX8-NEXT:    v_fma_f64 v[12:13], v[12:13], v[18:19], v[12:13]
+; GFX8-NEXT:    v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
+; GFX8-NEXT:    v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
+; GFX8-NEXT:    v_mul_f64 v[18:19], v[16:17], v[12:13]
+; GFX8-NEXT:    v_fma_f64 v[8:9], -v[8:9], v[18:19], v[16:17]
+; GFX8-NEXT:    v_div_scale_f64 v[16:17], s[4:5], v[2:3], v[6:7], v[2:3]
+; GFX8-NEXT:    v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[18:19]
+; GFX8-NEXT:    v_mul_f64 v[20:21], v[16:17], v[14:15]
 ; GFX8-NEXT:    s_mov_b64 vcc, s[4:5]
-; GFX8-NEXT:    v_mul_f64 v[20:21], v[18:19], v[14:15]
 ; GFX8-NEXT:    v_div_fixup_f64 v[0:1], v[8:9], v[4:5], v[0:1]
-; GFX8-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[20:21], v[18:19]
+; GFX8-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[20:21], v[16:17]
 ; GFX8-NEXT:    v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[20:21]
 ; GFX8-NEXT:    v_div_fixup_f64 v[2:3], v[10:11], v[6:7], v[2:3]
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
@@ -582,22 +582,22 @@
 ; GFX9-NEXT:    v_rcp_f64_e32 v[12:13], v[8:9]
 ; GFX9-NEXT:    v_rcp_f64_e32 v[14:15], v[10:11]
 ; GFX9-NEXT:    v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
-; GFX9-NEXT:    v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
-; GFX9-NEXT:    v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
-; GFX9-NEXT:    v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
-; GFX9-NEXT:    v_div_scale_f64 v[18:19], vcc, v[0:1], v[4:5], v[0:1]
-; GFX9-NEXT:    v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
 ; GFX9-NEXT:    v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
 ; GFX9-NEXT:    v_fma_f64 v[16:17], -v[10:11], v[14:15], 1.0
+; GFX9-NEXT:    v_fma_f64 v[18:19], -v[8:9], v[12:13], 1.0
 ; GFX9-NEXT:    v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
-; GFX9-NEXT:    v_mul_f64 v[16:17], v[18:19], v[12:13]
-; GFX9-NEXT:    v_fma_f64 v[8:9], -v[8:9], v[16:17], v[18:19]
-; GFX9-NEXT:    v_div_scale_f64 v[18:19], s[4:5], v[2:3], v[6:7], v[2:3]
-; GFX9-NEXT:    v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[16:17]
+; GFX9-NEXT:    v_div_scale_f64 v[16:17], vcc, v[0:1], v[4:5], v[0:1]
+; GFX9-NEXT:    v_fma_f64 v[12:13], v[12:13], v[18:19], v[12:13]
+; GFX9-NEXT:    v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
+; GFX9-NEXT:    v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
+; GFX9-NEXT:    v_mul_f64 v[18:19], v[16:17], v[12:13]
+; GFX9-NEXT:    v_fma_f64 v[8:9], -v[8:9], v[18:19], v[16:17]
+; GFX9-NEXT:    v_div_scale_f64 v[16:17], s[4:5], v[2:3], v[6:7], v[2:3]
+; GFX9-NEXT:    v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[18:19]
+; GFX9-NEXT:    v_mul_f64 v[20:21], v[16:17], v[14:15]
 ; GFX9-NEXT:    s_mov_b64 vcc, s[4:5]
-; GFX9-NEXT:    v_mul_f64 v[20:21], v[18:19], v[14:15]
 ; GFX9-NEXT:    v_div_fixup_f64 v[0:1], v[8:9], v[4:5], v[0:1]
-; GFX9-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[20:21], v[18:19]
+; GFX9-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[20:21], v[16:17]
 ; GFX9-NEXT:    v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[20:21]
 ; GFX9-NEXT:    v_div_fixup_f64 v[2:3], v[10:11], v[6:7], v[2:3]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
@@ -610,33 +610,34 @@
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    v_div_scale_f64 v[4:5], s[4:5], v[0:1], v[0:1], 1.0
-; GFX6-NEXT:    v_div_scale_f64 v[10:11], s[4:5], 1.0, v[0:1], 1.0
+; GFX6-NEXT:    v_div_scale_f64 v[8:9], s[4:5], v[2:3], v[2:3], 1.0
+; GFX6-NEXT:    v_div_scale_f64 v[12:13], s[4:5], 1.0, v[0:1], 1.0
 ; GFX6-NEXT:    v_mov_b32_e32 v18, 0x3ff00000
 ; GFX6-NEXT:    v_rcp_f64_e32 v[6:7], v[4:5]
-; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, v18, v11
-; GFX6-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
-; GFX6-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
-; GFX6-NEXT:    v_div_scale_f64 v[8:9], s[4:5], v[2:3], v[2:3], 1.0
-; GFX6-NEXT:    v_fma_f64 v[12:13], -v[4:5], v[6:7], 1.0
 ; GFX6-NEXT:    v_cmp_eq_u32_e64 s[4:5], v1, v5
-; GFX6-NEXT:    v_fma_f64 v[6:7], v[6:7], v[12:13], v[6:7]
-; GFX6-NEXT:    v_rcp_f64_e32 v[12:13], v[8:9]
-; GFX6-NEXT:    v_mul_f64 v[14:15], v[10:11], v[6:7]
+; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, v18, v13
 ; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
-; GFX6-NEXT:    v_fma_f64 v[10:11], -v[4:5], v[14:15], v[10:11]
-; GFX6-NEXT:    v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
-; GFX6-NEXT:    v_div_fmas_f64 v[6:7], v[10:11], v[6:7], v[14:15]
-; GFX6-NEXT:    v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
-; GFX6-NEXT:    v_div_scale_f64 v[16:17], s[6:7], 1.0, v[2:3], 1.0
-; GFX6-NEXT:    v_fma_f64 v[4:5], -v[8:9], v[12:13], 1.0
+; GFX6-NEXT:    v_fma_f64 v[10:11], -v[4:5], v[6:7], 1.0
 ; GFX6-NEXT:    v_cmp_eq_u32_e64 s[4:5], v3, v9
-; GFX6-NEXT:    v_fma_f64 v[4:5], v[12:13], v[4:5], v[12:13]
-; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, v18, v17
-; GFX6-NEXT:    v_mul_f64 v[12:13], v[16:17], v[4:5]
+; GFX6-NEXT:    v_fma_f64 v[6:7], v[6:7], v[10:11], v[6:7]
+; GFX6-NEXT:    v_rcp_f64_e32 v[10:11], v[8:9]
+; GFX6-NEXT:    v_fma_f64 v[14:15], -v[4:5], v[6:7], 1.0
+; GFX6-NEXT:    v_fma_f64 v[6:7], v[6:7], v[14:15], v[6:7]
+; GFX6-NEXT:    v_fma_f64 v[14:15], -v[8:9], v[10:11], 1.0
+; GFX6-NEXT:    v_mul_f64 v[16:17], v[12:13], v[6:7]
+; GFX6-NEXT:    v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
+; GFX6-NEXT:    v_fma_f64 v[12:13], -v[4:5], v[16:17], v[12:13]
+; GFX6-NEXT:    v_fma_f64 v[4:5], -v[8:9], v[10:11], 1.0
+; GFX6-NEXT:    v_div_scale_f64 v[14:15], s[6:7], 1.0, v[2:3], 1.0
+; GFX6-NEXT:    v_fma_f64 v[4:5], v[10:11], v[4:5], v[10:11]
+; GFX6-NEXT:    v_div_fmas_f64 v[6:7], v[12:13], v[6:7], v[16:17]
+; GFX6-NEXT:    v_mul_f64 v[10:11], v[14:15], v[4:5]
+; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, v18, v15
+; GFX6-NEXT:    v_fma_f64 v[12:13], -v[8:9], v[10:11], v[14:15]
 ; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
-; GFX6-NEXT:    v_fma_f64 v[10:11], -v[8:9], v[12:13], v[16:17]
 ; GFX6-NEXT:    v_div_fixup_f64 v[0:1], v[6:7], v[0:1], 1.0
-; GFX6-NEXT:    v_div_fmas_f64 v[4:5], v[10:11], v[4:5], v[12:13]
+; GFX6-NEXT:    s_nop 0
+; GFX6-NEXT:    v_div_fmas_f64 v[4:5], v[12:13], v[4:5], v[10:11]
 ; GFX6-NEXT:    v_div_fixup_f64 v[2:3], v[4:5], v[2:3], 1.0
 ; GFX6-NEXT:    s_setpc_b64 s[30:31]
 ;
@@ -704,33 +705,34 @@
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    v_div_scale_f64 v[4:5], s[4:5], v[0:1], v[0:1], 1.0
-; GFX6-NEXT:    v_div_scale_f64 v[10:11], s[4:5], 1.0, v[0:1], 1.0
+; GFX6-NEXT:    v_div_scale_f64 v[8:9], s[4:5], v[2:3], v[2:3], 1.0
+; GFX6-NEXT:    v_div_scale_f64 v[12:13], s[4:5], 1.0, v[0:1], 1.0
 ; GFX6-NEXT:    v_mov_b32_e32 v18, 0x3ff00000
 ; GFX6-NEXT:    v_rcp_f64_e32 v[6:7], v[4:5]
-; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, v18, v11
-; GFX6-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
-; GFX6-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
-; GFX6-NEXT:    v_div_scale_f64 v[8:9], s[4:5], v[2:3], v[2:3], 1.0
-; GFX6-NEXT:    v_fma_f64 v[12:13], -v[4:5], v[6:7], 1.0
 ; GFX6-NEXT:    v_cmp_eq_u32_e64 s[4:5], v1, v5
-; GFX6-NEXT:    v_fma_f64 v[6:7], v[6:7], v[12:13], v[6:7]
-; GFX6-NEXT:    v_rcp_f64_e32 v[12:13], v[8:9]
-; GFX6-NEXT:    v_mul_f64 v[14:15], v[10:11], v[6:7]
+; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, v18, v13
 ; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
-; GFX6-NEXT:    v_fma_f64 v[10:11], -v[4:5], v[14:15], v[10:11]
-; GFX6-NEXT:    v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
-; GFX6-NEXT:    v_div_fmas_f64 v[6:7], v[10:11], v[6:7], v[14:15]
-; GFX6-NEXT:    v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
-; GFX6-NEXT:    v_div_scale_f64 v[16:17], s[6:7], 1.0, v[2:3], 1.0
-; GFX6-NEXT:    v_fma_f64 v[4:5], -v[8:9], v[12:13], 1.0
+; GFX6-NEXT:    v_fma_f64 v[10:11], -v[4:5], v[6:7], 1.0
 ; GFX6-NEXT:    v_cmp_eq_u32_e64 s[4:5], v3, v9
-; GFX6-NEXT:    v_fma_f64 v[4:5], v[12:13], v[4:5], v[12:13]
-; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, v18, v17
-; GFX6-NEXT:    v_mul_f64 v[12:13], v[16:17], v[4:5]
+; GFX6-NEXT:    v_fma_f64 v[6:7], v[6:7], v[10:11], v[6:7]
+; GFX6-NEXT:    v_rcp_f64_e32 v[10:11], v[8:9]
+; GFX6-NEXT:    v_fma_f64 v[14:15], -v[4:5], v[6:7], 1.0
+; GFX6-NEXT:    v_fma_f64 v[6:7], v[6:7], v[14:15], v[6:7]
+; GFX6-NEXT:    v_fma_f64 v[14:15], -v[8:9], v[10:11], 1.0
+; GFX6-NEXT:    v_mul_f64 v[16:17], v[12:13], v[6:7]
+; GFX6-NEXT:    v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
+; GFX6-NEXT:    v_fma_f64 v[12:13], -v[4:5], v[16:17], v[12:13]
+; GFX6-NEXT:    v_fma_f64 v[4:5], -v[8:9], v[10:11], 1.0
+; GFX6-NEXT:    v_div_scale_f64 v[14:15], s[6:7], 1.0, v[2:3], 1.0
+; GFX6-NEXT:    v_fma_f64 v[4:5], v[10:11], v[4:5], v[10:11]
+; GFX6-NEXT:    v_div_fmas_f64 v[6:7], v[12:13], v[6:7], v[16:17]
+; GFX6-NEXT:    v_mul_f64 v[10:11], v[14:15], v[4:5]
+; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, v18, v15
+; GFX6-NEXT:    v_fma_f64 v[12:13], -v[8:9], v[10:11], v[14:15]
 ; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
-; GFX6-NEXT:    v_fma_f64 v[10:11], -v[8:9], v[12:13], v[16:17]
 ; GFX6-NEXT:    v_div_fixup_f64 v[0:1], v[6:7], v[0:1], 1.0
-; GFX6-NEXT:    v_div_fmas_f64 v[4:5], v[10:11], v[4:5], v[12:13]
+; GFX6-NEXT:    s_nop 0
+; GFX6-NEXT:    v_div_fmas_f64 v[4:5], v[12:13], v[4:5], v[10:11]
 ; GFX6-NEXT:    v_div_fixup_f64 v[2:3], v[4:5], v[2:3], 1.0
 ; GFX6-NEXT:    s_setpc_b64 s[30:31]
 ;
@@ -823,33 +825,34 @@
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    v_div_scale_f64 v[4:5], s[4:5], v[0:1], v[0:1], 1.0
-; GFX6-NEXT:    v_div_scale_f64 v[10:11], s[4:5], 1.0, v[0:1], 1.0
+; GFX6-NEXT:    v_div_scale_f64 v[8:9], s[4:5], v[2:3], v[2:3], 1.0
+; GFX6-NEXT:    v_div_scale_f64 v[12:13], s[4:5], 1.0, v[0:1], 1.0
 ; GFX6-NEXT:    v_mov_b32_e32 v18, 0x3ff00000
 ; GFX6-NEXT:    v_rcp_f64_e32 v[6:7], v[4:5]
-; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, v18, v11
-; GFX6-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
-; GFX6-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
-; GFX6-NEXT:    v_div_scale_f64 v[8:9], s[4:5], v[2:3], v[2:3], 1.0
-; GFX6-NEXT:    v_fma_f64 v[12:13], -v[4:5], v[6:7], 1.0
 ; GFX6-NEXT:    v_cmp_eq_u32_e64 s[4:5], v1, v5
-; GFX6-NEXT:    v_fma_f64 v[6:7], v[6:7], v[12:13], v[6:7]
-; GFX6-NEXT:    v_rcp_f64_e32 v[12:13], v[8:9]
-; GFX6-NEXT:    v_mul_f64 v[14:15], v[10:11], v[6:7]
+; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, v18, v13
 ; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
-; GFX6-NEXT:    v_fma_f64 v[10:11], -v[4:5], v[14:15], v[10:11]
-; GFX6-NEXT:    v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
-; GFX6-NEXT:    v_div_fmas_f64 v[6:7], v[10:11], v[6:7], v[14:15]
-; GFX6-NEXT:    v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
-; GFX6-NEXT:    v_div_scale_f64 v[16:17], s[6:7], 1.0, v[2:3], 1.0
-; GFX6-NEXT:    v_fma_f64 v[4:5], -v[8:9], v[12:13], 1.0
+; GFX6-NEXT:    v_fma_f64 v[10:11], -v[4:5], v[6:7], 1.0
 ; GFX6-NEXT:    v_cmp_eq_u32_e64 s[4:5], v3, v9
-; GFX6-NEXT:    v_fma_f64 v[4:5], v[12:13], v[4:5], v[12:13]
-; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, v18, v17
-; GFX6-NEXT:    v_mul_f64 v[12:13], v[16:17], v[4:5]
+; GFX6-NEXT:    v_fma_f64 v[6:7], v[6:7], v[10:11], v[6:7]
+; GFX6-NEXT:    v_rcp_f64_e32 v[10:11], v[8:9]
+; GFX6-NEXT:    v_fma_f64 v[14:15], -v[4:5], v[6:7], 1.0
+; GFX6-NEXT:    v_fma_f64 v[6:7], v[6:7], v[14:15], v[6:7]
+; GFX6-NEXT:    v_fma_f64 v[14:15], -v[8:9], v[10:11], 1.0
+; GFX6-NEXT:    v_mul_f64 v[16:17], v[12:13], v[6:7]
+; GFX6-NEXT:    v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
+; GFX6-NEXT:    v_fma_f64 v[12:13], -v[4:5], v[16:17], v[12:13]
+; GFX6-NEXT:    v_fma_f64 v[4:5], -v[8:9], v[10:11], 1.0
+; GFX6-NEXT:    v_div_scale_f64 v[14:15], s[6:7], 1.0, v[2:3], 1.0
+; GFX6-NEXT:    v_fma_f64 v[4:5], v[10:11], v[4:5], v[10:11]
+; GFX6-NEXT:    v_div_fmas_f64 v[6:7], v[12:13], v[6:7], v[16:17]
+; GFX6-NEXT:    v_mul_f64 v[10:11], v[14:15], v[4:5]
+; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, v18, v15
+; GFX6-NEXT:    v_fma_f64 v[12:13], -v[8:9], v[10:11], v[14:15]
 ; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
-; GFX6-NEXT:    v_fma_f64 v[10:11], -v[8:9], v[12:13], v[16:17]
 ; GFX6-NEXT:    v_div_fixup_f64 v[0:1], v[6:7], v[0:1], 1.0
-; GFX6-NEXT:    v_div_fmas_f64 v[4:5], v[10:11], v[4:5], v[12:13]
+; GFX6-NEXT:    s_nop 0
+; GFX6-NEXT:    v_div_fmas_f64 v[4:5], v[12:13], v[4:5], v[10:11]
 ; GFX6-NEXT:    v_div_fixup_f64 v[2:3], v[4:5], v[2:3], 1.0
 ; GFX6-NEXT:    s_setpc_b64 s[30:31]
 ;
@@ -942,30 +945,30 @@
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    v_div_scale_f64 v[8:9], s[4:5], v[4:5], v[4:5], v[0:1]
-; GFX6-NEXT:    v_div_scale_f64 v[14:15], s[4:5], v[6:7], v[6:7], v[2:3]
+; GFX6-NEXT:    v_div_scale_f64 v[12:13], s[4:5], v[6:7], v[6:7], v[2:3]
 ; GFX6-NEXT:    v_div_scale_f64 v[18:19], s[4:5], v[0:1], v[4:5], v[0:1]
 ; GFX6-NEXT:    v_rcp_f64_e32 v[10:11], v[8:9]
-; GFX6-NEXT:    v_rcp_f64_e32 v[16:17], v[14:15]
-; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v19
 ; GFX6-NEXT:    v_cmp_eq_u32_e64 s[4:5], v5, v9
-; GFX6-NEXT:    v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
+; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v19
 ; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
-; GFX6-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
-; GFX6-NEXT:    v_cmp_eq_u32_e64 s[4:5], v7, v15
-; GFX6-NEXT:    v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
-; GFX6-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
-; GFX6-NEXT:    v_fma_f64 v[12:13], -v[14:15], v[16:17], 1.0
-; GFX6-NEXT:    v_fma_f64 v[12:13], v[16:17], v[12:13], v[16:17]
+; GFX6-NEXT:    v_fma_f64 v[14:15], -v[8:9], v[10:11], 1.0
+; GFX6-NEXT:    v_cmp_eq_u32_e64 s[4:5], v7, v13
+; GFX6-NEXT:    v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
+; GFX6-NEXT:    v_rcp_f64_e32 v[14:15], v[12:13]
+; GFX6-NEXT:    v_fma_f64 v[16:17], -v[8:9], v[10:11], 1.0
+; GFX6-NEXT:    v_fma_f64 v[10:11], v[10:11], v[16:17], v[10:11]
+; GFX6-NEXT:    v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0
+; GFX6-NEXT:    v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
 ; GFX6-NEXT:    v_mul_f64 v[16:17], v[18:19], v[10:11]
 ; GFX6-NEXT:    v_fma_f64 v[18:19], -v[8:9], v[16:17], v[18:19]
-; GFX6-NEXT:    v_fma_f64 v[8:9], -v[14:15], v[12:13], 1.0
+; GFX6-NEXT:    v_fma_f64 v[8:9], -v[12:13], v[14:15], 1.0
 ; GFX6-NEXT:    v_div_fmas_f64 v[10:11], v[18:19], v[10:11], v[16:17]
-; GFX6-NEXT:    v_fma_f64 v[8:9], v[12:13], v[8:9], v[12:13]
-; GFX6-NEXT:    v_div_scale_f64 v[12:13], s[6:7], v[2:3], v[6:7], v[2:3]
+; GFX6-NEXT:    v_fma_f64 v[8:9], v[14:15], v[8:9], v[14:15]
+; GFX6-NEXT:    v_div_scale_f64 v[14:15], s[6:7], v[2:3], v[6:7], v[2:3]
 ; GFX6-NEXT:    v_div_fixup_f64 v[0:1], v[10:11], v[4:5], v[0:1]
-; GFX6-NEXT:    v_mul_f64 v[16:17], v[12:13], v[8:9]
-; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v13
-; GFX6-NEXT:    v_fma_f64 v[18:19], -v[14:15], v[16:17], v[12:13]
+; GFX6-NEXT:    v_mul_f64 v[16:17], v[14:15], v[8:9]
+; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v15
+; GFX6-NEXT:    v_fma_f64 v[18:19], -v[12:13], v[16:17], v[14:15]
 ; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
 ; GFX6-NEXT:    s_nop 1
 ; GFX6-NEXT:    v_div_fmas_f64 v[8:9], v[18:19], v[8:9], v[16:17]
@@ -980,22 +983,22 @@
 ; GFX8-NEXT:    v_rcp_f64_e32 v[12:13], v[8:9]
 ; GFX8-NEXT:    v_rcp_f64_e32 v[14:15], v[10:11]
 ; GFX8-NEXT:    v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
-; GFX8-NEXT:    v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
-; GFX8-NEXT:    v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
-; GFX8-NEXT:    v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
-; GFX8-NEXT:    v_div_scale_f64 v[18:19], vcc, v[0:1], v[4:5], v[0:1]
-; GFX8-NEXT:    v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
 ; GFX8-NEXT:    v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
 ; GFX8-NEXT:    v_fma_f64 v[16:17], -v[10:11], v[14:15], 1.0
+; GFX8-NEXT:    v_fma_f64 v[18:19], -v[8:9], v[12:13], 1.0
 ; GFX8-NEXT:    v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
-; GFX8-NEXT:    v_mul_f64 v[16:17], v[18:19], v[12:13]
-; GFX8-NEXT:    v_fma_f64 v[8:9], -v[8:9], v[16:17], v[18:19]
-; GFX8-NEXT:    v_div_scale_f64 v[18:19], s[4:5], v[2:3], v[6:7], v[2:3]
-; GFX8-NEXT:    v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[16:17]
+; GFX8-NEXT:    v_div_scale_f64 v[16:17], vcc, v[0:1], v[4:5], v[0:1]
+; GFX8-NEXT:    v_fma_f64 v[12:13], v[12:13], v[18:19], v[12:13]
+; GFX8-NEXT:    v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
+; GFX8-NEXT:    v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
+; GFX8-NEXT:    v_mul_f64 v[18:19], v[16:17], v[12:13]
+; GFX8-NEXT:    v_fma_f64 v[8:9], -v[8:9], v[18:19], v[16:17]
+; GFX8-NEXT:    v_div_scale_f64 v[16:17], s[4:5], v[2:3], v[6:7], v[2:3]
+; GFX8-NEXT:    v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[18:19]
+; GFX8-NEXT:    v_mul_f64 v[20:21], v[16:17], v[14:15]
 ; GFX8-NEXT:    s_mov_b64 vcc, s[4:5]
-; GFX8-NEXT:    v_mul_f64 v[20:21], v[18:19], v[14:15]
 ; GFX8-NEXT:    v_div_fixup_f64 v[0:1], v[8:9], v[4:5], v[0:1]
-; GFX8-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[20:21], v[18:19]
+; GFX8-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[20:21], v[16:17]
 ; GFX8-NEXT:    v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[20:21]
 ; GFX8-NEXT:    v_div_fixup_f64 v[2:3], v[10:11], v[6:7], v[2:3]
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
@@ -1008,22 +1011,22 @@
 ; GFX9-NEXT:    v_rcp_f64_e32 v[12:13], v[8:9]
 ; GFX9-NEXT:    v_rcp_f64_e32 v[14:15], v[10:11]
 ; GFX9-NEXT:    v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
-; GFX9-NEXT:    v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
-; GFX9-NEXT:    v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
-; GFX9-NEXT:    v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
-; GFX9-NEXT:    v_div_scale_f64 v[18:19], vcc, v[0:1], v[4:5], v[0:1]
-; GFX9-NEXT:    v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
 ; GFX9-NEXT:    v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
 ; GFX9-NEXT:    v_fma_f64 v[16:17], -v[10:11], v[14:15], 1.0
+; GFX9-NEXT:    v_fma_f64 v[18:19], -v[8:9], v[12:13], 1.0
 ; GFX9-NEXT:    v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
-; GFX9-NEXT:    v_mul_f64 v[16:17], v[18:19], v[12:13]
-; GFX9-NEXT:    v_fma_f64 v[8:9], -v[8:9], v[16:17], v[18:19]
-; GFX9-NEXT:    v_div_scale_f64 v[18:19], s[4:5], v[2:3], v[6:7], v[2:3]
-; GFX9-NEXT:    v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[16:17]
+; GFX9-NEXT:    v_div_scale_f64 v[16:17], vcc, v[0:1], v[4:5], v[0:1]
+; GFX9-NEXT:    v_fma_f64 v[12:13], v[12:13], v[18:19], v[12:13]
+; GFX9-NEXT:    v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
+; GFX9-NEXT:    v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
+; GFX9-NEXT:    v_mul_f64 v[18:19], v[16:17], v[12:13]
+; GFX9-NEXT:    v_fma_f64 v[8:9], -v[8:9], v[18:19], v[16:17]
+; GFX9-NEXT:    v_div_scale_f64 v[16:17], s[4:5], v[2:3], v[6:7], v[2:3]
+; GFX9-NEXT:    v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[18:19]
+; GFX9-NEXT:    v_mul_f64 v[20:21], v[16:17], v[14:15]
 ; GFX9-NEXT:    s_mov_b64 vcc, s[4:5]
-; GFX9-NEXT:    v_mul_f64 v[20:21], v[18:19], v[14:15]
 ; GFX9-NEXT:    v_div_fixup_f64 v[0:1], v[8:9], v[4:5], v[0:1]
-; GFX9-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[20:21], v[18:19]
+; GFX9-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[20:21], v[16:17]
 ; GFX9-NEXT:    v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[20:21]
 ; GFX9-NEXT:    v_div_fixup_f64 v[2:3], v[10:11], v[6:7], v[2:3]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
@@ -2020,41 +2020,41 @@
 ; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v6, 24
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v6, v6
 ; GFX6-NEXT:    s_sub_i32 s4, 0, 24
-; GFX6-NEXT:    v_and_b32_e32 v4, 0xffffff, v4
 ; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v8, 24
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v8, v8
 ; GFX6-NEXT:    v_mul_f32_e32 v6, 0x4f7ffffe, v6
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v6, v6
+; GFX6-NEXT:    v_and_b32_e32 v4, 0xffffff, v4
+; GFX6-NEXT:    v_mul_f32_e32 v8, 0x4f7ffffe, v8
+; GFX6-NEXT:    v_mov_b32_e32 v9, 0xffffff
 ; GFX6-NEXT:    v_mul_lo_u32 v7, s4, v6
+; GFX6-NEXT:    v_and_b32_e32 v5, v5, v9
+; GFX6-NEXT:    v_and_b32_e32 v2, v2, v9
+; GFX6-NEXT:    v_lshrrev_b32_e32 v2, 1, v2
 ; GFX6-NEXT:    v_mul_hi_u32 v7, v6, v7
 ; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
 ; GFX6-NEXT:    v_mul_hi_u32 v6, v4, v6
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v7, v8
-; GFX6-NEXT:    v_mov_b32_e32 v8, 0xffffff
-; GFX6-NEXT:    v_and_b32_e32 v2, v2, v8
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v7, v8
 ; GFX6-NEXT:    v_mul_lo_u32 v6, v6, 24
-; GFX6-NEXT:    v_mul_f32_e32 v7, 0x4f7ffffe, v7
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v7, v7
-; GFX6-NEXT:    v_lshrrev_b32_e32 v2, 1, v2
+; GFX6-NEXT:    v_mul_lo_u32 v8, s4, v7
 ; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, v4, v6
 ; GFX6-NEXT:    v_subrev_i32_e32 v6, vcc, 24, v4
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v4
+; GFX6-NEXT:    v_mul_hi_u32 v8, v7, v8
 ; GFX6-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
 ; GFX6-NEXT:    v_subrev_i32_e32 v6, vcc, 24, v4
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v4
 ; GFX6-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v6, s4, v7
-; GFX6-NEXT:    v_sub_i32_e32 v9, vcc, 23, v4
-; GFX6-NEXT:    v_and_b32_e32 v4, v4, v8
+; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; GFX6-NEXT:    v_mul_hi_u32 v7, v5, v7
+; GFX6-NEXT:    v_sub_i32_e32 v6, vcc, 23, v4
+; GFX6-NEXT:    v_and_b32_e32 v4, v4, v9
 ; GFX6-NEXT:    v_lshlrev_b32_e32 v0, v4, v0
-; GFX6-NEXT:    v_mul_hi_u32 v6, v7, v6
-; GFX6-NEXT:    v_and_b32_e32 v4, v5, v8
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v7, v6
-; GFX6-NEXT:    v_mul_hi_u32 v5, v4, v5
-; GFX6-NEXT:    v_and_b32_e32 v6, v9, v8
+; GFX6-NEXT:    v_mul_lo_u32 v4, v7, 24
+; GFX6-NEXT:    v_and_b32_e32 v6, v6, v9
 ; GFX6-NEXT:    v_lshrrev_b32_e32 v2, v6, v2
 ; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
-; GFX6-NEXT:    v_mul_lo_u32 v5, v5, 24
-; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, v4, v5
+; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, v5, v4
 ; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, 24, v2
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
 ; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
@@ -2062,11 +2062,11 @@
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
 ; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
 ; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, 23, v2
-; GFX6-NEXT:    v_and_b32_e32 v2, v2, v8
+; GFX6-NEXT:    v_and_b32_e32 v2, v2, v9
 ; GFX6-NEXT:    v_lshlrev_b32_e32 v1, v2, v1
-; GFX6-NEXT:    v_and_b32_e32 v2, v3, v8
+; GFX6-NEXT:    v_and_b32_e32 v2, v3, v9
 ; GFX6-NEXT:    v_lshrrev_b32_e32 v2, 1, v2
-; GFX6-NEXT:    v_and_b32_e32 v3, v4, v8
+; GFX6-NEXT:    v_and_b32_e32 v3, v4, v9
 ; GFX6-NEXT:    v_lshrrev_b32_e32 v2, v3, v2
 ; GFX6-NEXT:    v_or_b32_e32 v1, v1, v2
 ; GFX6-NEXT:    s_setpc_b64 s[30:31]
@@ -2077,41 +2077,41 @@
 ; GFX8-NEXT:    v_cvt_f32_ubyte0_e32 v6, 24
 ; GFX8-NEXT:    v_rcp_iflag_f32_e32 v6, v6
 ; GFX8-NEXT:    s_sub_i32 s4, 0, 24
-; GFX8-NEXT:    v_and_b32_e32 v4, 0xffffff, v4
 ; GFX8-NEXT:    v_cvt_f32_ubyte0_e32 v8, 24
+; GFX8-NEXT:    v_rcp_iflag_f32_e32 v8, v8
 ; GFX8-NEXT:    v_mul_f32_e32 v6, 0x4f7ffffe, v6
 ; GFX8-NEXT:    v_cvt_u32_f32_e32 v6, v6
+; GFX8-NEXT:    v_and_b32_e32 v4, 0xffffff, v4
+; GFX8-NEXT:    v_mul_f32_e32 v8, 0x4f7ffffe, v8
+; GFX8-NEXT:    v_mov_b32_e32 v9, 0xffffff
 ; GFX8-NEXT:    v_mul_lo_u32 v7, s4, v6
+; GFX8-NEXT:    v_and_b32_e32 v5, v5, v9
+; GFX8-NEXT:    v_and_b32_e32 v2, v2, v9
+; GFX8-NEXT:    v_lshrrev_b32_e32 v2, 1, v2
 ; GFX8-NEXT:    v_mul_hi_u32 v7, v6, v7
 ; GFX8-NEXT:    v_add_u32_e32 v6, vcc, v6, v7
 ; GFX8-NEXT:    v_mul_hi_u32 v6, v4, v6
-; GFX8-NEXT:    v_rcp_iflag_f32_e32 v7, v8
-; GFX8-NEXT:    v_mov_b32_e32 v8, 0xffffff
-; GFX8-NEXT:    v_and_b32_e32 v2, v2, v8
+; GFX8-NEXT:    v_cvt_u32_f32_e32 v7, v8
 ; GFX8-NEXT:    v_mul_lo_u32 v6, v6, 24
-; GFX8-NEXT:    v_mul_f32_e32 v7, 0x4f7ffffe, v7
-; GFX8-NEXT:    v_cvt_u32_f32_e32 v7, v7
-; GFX8-NEXT:    v_lshrrev_b32_e32 v2, 1, v2
+; GFX8-NEXT:    v_mul_lo_u32 v8, s4, v7
 ; GFX8-NEXT:    v_sub_u32_e32 v4, vcc, v4, v6
 ; GFX8-NEXT:    v_subrev_u32_e32 v6, vcc, 24, v4
 ; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v4
+; GFX8-NEXT:    v_mul_hi_u32 v8, v7, v8
 ; GFX8-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
 ; GFX8-NEXT:    v_subrev_u32_e32 v6, vcc, 24, v4
 ; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v4
 ; GFX8-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
-; GFX8-NEXT:    v_mul_lo_u32 v6, s4, v7
-; GFX8-NEXT:    v_sub_u32_e32 v9, vcc, 23, v4
-; GFX8-NEXT:    v_and_b32_e32 v4, v4, v8
+; GFX8-NEXT:    v_add_u32_e32 v7, vcc, v7, v8
+; GFX8-NEXT:    v_mul_hi_u32 v7, v5, v7
+; GFX8-NEXT:    v_sub_u32_e32 v6, vcc, 23, v4
+; GFX8-NEXT:    v_and_b32_e32 v4, v4, v9
 ; GFX8-NEXT:    v_lshlrev_b32_e32 v0, v4, v0
-; GFX8-NEXT:    v_mul_hi_u32 v6, v7, v6
-; GFX8-NEXT:    v_and_b32_e32 v4, v5, v8
-; GFX8-NEXT:    v_add_u32_e32 v5, vcc, v7, v6
-; GFX8-NEXT:    v_mul_hi_u32 v5, v4, v5
-; GFX8-NEXT:    v_and_b32_e32 v6, v9, v8
+; GFX8-NEXT:    v_mul_lo_u32 v4, v7, 24
+; GFX8-NEXT:    v_and_b32_e32 v6, v6, v9
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v2, v6, v2
 ; GFX8-NEXT:    v_or_b32_e32 v0, v0, v2
-; GFX8-NEXT:    v_mul_lo_u32 v5, v5, 24
-; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, v4, v5
+; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, v5, v4
 ; GFX8-NEXT:    v_subrev_u32_e32 v4, vcc, 24, v2
 ; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
 ; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
@@ -2119,11 +2119,11 @@
 ; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
 ; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
 ; GFX8-NEXT:    v_sub_u32_e32 v4, vcc, 23, v2
-; GFX8-NEXT:    v_and_b32_e32 v2, v2, v8
+; GFX8-NEXT:    v_and_b32_e32 v2, v2, v9
 ; GFX8-NEXT:    v_lshlrev_b32_e32 v1, v2, v1
-; GFX8-NEXT:    v_and_b32_e32 v2, v3, v8
+; GFX8-NEXT:    v_and_b32_e32 v2, v3, v9
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v2, 1, v2
-; GFX8-NEXT:    v_and_b32_e32 v3, v4, v8
+; GFX8-NEXT:    v_and_b32_e32 v3, v4, v9
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v2, v3, v2
 ; GFX8-NEXT:    v_or_b32_e32 v1, v1, v2
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
@@ -1534,40 +1534,40 @@
 ; GFX6-NEXT:    s_lshr_b32 s12, s5, 8
 ; GFX6-NEXT:    s_and_b32 s5, s5, s10
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
-; GFX6-NEXT:    v_mul_hi_u32 v0, s4, v0
 ; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v1, 24
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v1
+; GFX6-NEXT:    v_mul_hi_u32 v0, s4, v0
 ; GFX6-NEXT:    s_lshl_b32 s5, s5, 8
-; GFX6-NEXT:    v_mul_lo_u32 v0, v0, 24
 ; GFX6-NEXT:    s_and_b32 s8, s12, s10
 ; GFX6-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v1
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT:    v_mul_lo_u32 v0, v0, 24
+; GFX6-NEXT:    s_or_b32 s5, s11, s5
+; GFX6-NEXT:    s_bfe_u32 s8, s8, 0x100000
+; GFX6-NEXT:    v_mul_lo_u32 v3, s9, v1
 ; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
 ; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, 24, v0
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v0
+; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
 ; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
 ; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, 24, v0
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v0
-; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v2, s9, v1
-; GFX6-NEXT:    s_or_b32 s5, s11, s5
-; GFX6-NEXT:    s_bfe_u32 s8, s8, 0x100000
 ; GFX6-NEXT:    s_bfe_u32 s5, s5, 0x100000
-; GFX6-NEXT:    v_mul_hi_u32 v2, v1, v2
 ; GFX6-NEXT:    s_lshl_b32 s8, s8, 16
+; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
 ; GFX6-NEXT:    s_or_b32 s5, s5, s8
-; GFX6-NEXT:    s_bfe_u32 s0, s0, 0x100000
-; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v2
+; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
 ; GFX6-NEXT:    v_mul_hi_u32 v1, s5, v1
+; GFX6-NEXT:    s_bfe_u32 s0, s0, 0x100000
 ; GFX6-NEXT:    s_bfe_u32 s6, s6, 0x100000
 ; GFX6-NEXT:    s_mov_b32 s8, 0xffffff
-; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, 23, v0
 ; GFX6-NEXT:    v_mul_lo_u32 v1, v1, 24
+; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, 23, v0
 ; GFX6-NEXT:    s_lshl_b32 s4, s6, 17
 ; GFX6-NEXT:    s_lshl_b32 s0, s0, 1
 ; GFX6-NEXT:    v_and_b32_e32 v0, s8, v0
 ; GFX6-NEXT:    s_or_b32 s0, s4, s0
-; GFX6-NEXT:    v_and_b32_e32 v2, s8, v3
+; GFX6-NEXT:    v_and_b32_e32 v2, s8, v2
 ; GFX6-NEXT:    v_lshl_b32_e32 v2, s0, v2
 ; GFX6-NEXT:    v_lshr_b32_e32 v0, s2, v0
 ; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s5, v1
@@ -1580,13 +1580,13 @@
 ; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
 ; GFX6-NEXT:    s_bfe_u32 s1, s1, 0x100000
 ; GFX6-NEXT:    s_bfe_u32 s7, s7, 0x100000
-; GFX6-NEXT:    v_mov_b32_e32 v4, 0xffffff
+; GFX6-NEXT:    v_mov_b32_e32 v3, 0xffffff
 ; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, 23, v1
 ; GFX6-NEXT:    s_lshl_b32 s0, s7, 17
 ; GFX6-NEXT:    s_lshl_b32 s1, s1, 1
-; GFX6-NEXT:    v_and_b32_e32 v1, v1, v4
+; GFX6-NEXT:    v_and_b32_e32 v1, v1, v3
+; GFX6-NEXT:    v_and_b32_e32 v2, v2, v3
 ; GFX6-NEXT:    s_or_b32 s0, s0, s1
-; GFX6-NEXT:    v_and_b32_e32 v2, v2, v4
 ; GFX6-NEXT:    v_lshl_b32_e32 v2, s0, v2
 ; GFX6-NEXT:    v_lshr_b32_e32 v1, s3, v1
 ; GFX6-NEXT:    v_or_b32_e32 v1, v2, v1
@@ -1672,40 +1672,40 @@
 ; GFX8-NEXT:    s_lshr_b32 s13, s5, 8
 ; GFX8-NEXT:    s_and_b32 s5, s5, s10
 ; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
-; GFX8-NEXT:    v_mul_hi_u32 v0, s4, v0
 ; GFX8-NEXT:    v_cvt_f32_ubyte0_e32 v1, 24
 ; GFX8-NEXT:    v_rcp_iflag_f32_e32 v1, v1
+; GFX8-NEXT:    v_mul_hi_u32 v0, s4, v0
 ; GFX8-NEXT:    s_lshl_b32 s5, s5, s11
-; GFX8-NEXT:    v_mul_lo_u32 v0, v0, 24
 ; GFX8-NEXT:    s_and_b32 s8, s13, s10
 ; GFX8-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v1
 ; GFX8-NEXT:    v_cvt_u32_f32_e32 v1, v1
+; GFX8-NEXT:    v_mul_lo_u32 v0, v0, 24
+; GFX8-NEXT:    s_or_b32 s5, s12, s5
+; GFX8-NEXT:    s_bfe_u32 s8, s8, 0x100000
+; GFX8-NEXT:    v_mul_lo_u32 v3, s9, v1
 ; GFX8-NEXT:    v_sub_u32_e32 v0, vcc, s4, v0
 ; GFX8-NEXT:    v_subrev_u32_e32 v2, vcc, 24, v0
 ; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v0
+; GFX8-NEXT:    v_mul_hi_u32 v3, v1, v3
 ; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
 ; GFX8-NEXT:    v_subrev_u32_e32 v2, vcc, 24, v0
 ; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v0
-; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX8-NEXT:    v_mul_lo_u32 v2, s9, v1
-; GFX8-NEXT:    s_or_b32 s5, s12, s5
-; GFX8-NEXT:    s_bfe_u32 s8, s8, 0x100000
 ; GFX8-NEXT:    s_bfe_u32 s5, s5, 0x100000
-; GFX8-NEXT:    v_mul_hi_u32 v2, v1, v2
 ; GFX8-NEXT:    s_lshl_b32 s8, s8, 16
+; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
 ; GFX8-NEXT:    s_or_b32 s5, s5, s8
-; GFX8-NEXT:    s_bfe_u32 s0, s0, 0x100000
-; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v2
+; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v3
 ; GFX8-NEXT:    v_mul_hi_u32 v1, s5, v1
+; GFX8-NEXT:    s_bfe_u32 s0, s0, 0x100000
 ; GFX8-NEXT:    s_bfe_u32 s6, s6, 0x100000
 ; GFX8-NEXT:    s_mov_b32 s8, 0xffffff
-; GFX8-NEXT:    v_sub_u32_e32 v3, vcc, 23, v0
 ; GFX8-NEXT:    v_mul_lo_u32 v1, v1, 24
+; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, 23, v0
 ; GFX8-NEXT:    s_lshl_b32 s4, s6, 17
 ; GFX8-NEXT:    s_lshl_b32 s0, s0, 1
 ; GFX8-NEXT:    v_and_b32_e32 v0, s8, v0
 ; GFX8-NEXT:    s_or_b32 s0, s4, s0
-; GFX8-NEXT:    v_and_b32_e32 v2, s8, v3
+; GFX8-NEXT:    v_and_b32_e32 v2, s8, v2
 ; GFX8-NEXT:    v_lshlrev_b32_e64 v2, v2, s0
 ; GFX8-NEXT:    v_lshrrev_b32_e64 v0, v0, s2
 ; GFX8-NEXT:    v_sub_u32_e32 v1, vcc, s5, v1
@@ -1718,13 +1718,13 @@
 ; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
 ; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
 ; GFX8-NEXT:    s_bfe_u32 s7, s7, 0x100000
-; GFX8-NEXT:    v_mov_b32_e32 v4, 0xffffff
+; GFX8-NEXT:    v_mov_b32_e32 v3, 0xffffff
 ; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, 23, v1
 ; GFX8-NEXT:    s_lshl_b32 s0, s7, 17
 ; GFX8-NEXT:    s_lshl_b32 s1, s1, 1
-; GFX8-NEXT:    v_and_b32_e32 v1, v1, v4
-; GFX8-NEXT:    v_and_b32_e32 v2, v2, v4
+; GFX8-NEXT:    v_and_b32_e32 v1, v1, v3
 ; GFX8-NEXT:    s_or_b32 s0, s0, s1
+; GFX8-NEXT:    v_and_b32_e32 v2, v2, v3
 ; GFX8-NEXT:    v_lshlrev_b32_e64 v2, v2, s0
 ; GFX8-NEXT:    v_lshrrev_b32_e64 v1, v1, s3
 ; GFX8-NEXT:    v_or_b32_e32 v1, v2, v1
@@ -2020,42 +2020,42 @@
 ; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v6, 24
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v6, v6
 ; GFX6-NEXT:    s_sub_i32 s4, 0, 24
-; GFX6-NEXT:    v_and_b32_e32 v4, 0xffffff, v4
 ; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v8, 24
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v8, v8
 ; GFX6-NEXT:    v_mul_f32_e32 v6, 0x4f7ffffe, v6
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v6, v6
-; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
-; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 1, v1
+; GFX6-NEXT:    v_and_b32_e32 v4, 0xffffff, v4
+; GFX6-NEXT:    v_mul_f32_e32 v8, 0x4f7ffffe, v8
+; GFX6-NEXT:    v_mov_b32_e32 v9, 0xffffff
 ; GFX6-NEXT:    v_mul_lo_u32 v7, s4, v6
+; GFX6-NEXT:    v_and_b32_e32 v5, v5, v9
+; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
+; GFX6-NEXT:    v_and_b32_e32 v2, v2, v9
 ; GFX6-NEXT:    v_mul_hi_u32 v7, v6, v7
+; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 1, v1
+; GFX6-NEXT:    v_and_b32_e32 v3, v3, v9
 ; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
 ; GFX6-NEXT:    v_mul_hi_u32 v6, v4, v6
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v7, v8
-; GFX6-NEXT:    v_mov_b32_e32 v8, 0xffffff
-; GFX6-NEXT:    v_and_b32_e32 v5, v5, v8
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v7, v8
 ; GFX6-NEXT:    v_mul_lo_u32 v6, v6, 24
-; GFX6-NEXT:    v_mul_f32_e32 v7, 0x4f7ffffe, v7
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v7, v7
-; GFX6-NEXT:    v_and_b32_e32 v2, v2, v8
+; GFX6-NEXT:    v_mul_lo_u32 v8, s4, v7
 ; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, v4, v6
 ; GFX6-NEXT:    v_subrev_i32_e32 v6, vcc, 24, v4
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v4
+; GFX6-NEXT:    v_mul_hi_u32 v8, v7, v8
 ; GFX6-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
 ; GFX6-NEXT:    v_subrev_i32_e32 v6, vcc, 24, v4
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v4
 ; GFX6-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v6, s4, v7
-; GFX6-NEXT:    v_sub_i32_e32 v9, vcc, 23, v4
-; GFX6-NEXT:    v_and_b32_e32 v9, v9, v8
-; GFX6-NEXT:    v_and_b32_e32 v4, v4, v8
-; GFX6-NEXT:    v_mul_hi_u32 v6, v7, v6
-; GFX6-NEXT:    v_lshlrev_b32_e32 v0, v9, v0
+; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; GFX6-NEXT:    v_mul_hi_u32 v7, v5, v7
+; GFX6-NEXT:    v_sub_i32_e32 v6, vcc, 23, v4
+; GFX6-NEXT:    v_and_b32_e32 v6, v6, v9
+; GFX6-NEXT:    v_lshlrev_b32_e32 v0, v6, v0
+; GFX6-NEXT:    v_mul_lo_u32 v6, v7, 24
+; GFX6-NEXT:    v_and_b32_e32 v4, v4, v9
 ; GFX6-NEXT:    v_lshrrev_b32_e32 v2, v4, v2
 ; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
-; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; GFX6-NEXT:    v_mul_hi_u32 v6, v5, v6
-; GFX6-NEXT:    v_and_b32_e32 v3, v3, v8
-; GFX6-NEXT:    v_mul_lo_u32 v6, v6, 24
 ; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, v5, v6
 ; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, 24, v2
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
@@ -2064,8 +2064,8 @@
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
 ; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
 ; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, 23, v2
-; GFX6-NEXT:    v_and_b32_e32 v2, v2, v8
-; GFX6-NEXT:    v_and_b32_e32 v4, v4, v8
+; GFX6-NEXT:    v_and_b32_e32 v2, v2, v9
+; GFX6-NEXT:    v_and_b32_e32 v4, v4, v9
 ; GFX6-NEXT:    v_lshlrev_b32_e32 v1, v4, v1
 ; GFX6-NEXT:    v_lshrrev_b32_e32 v2, v2, v3
 ; GFX6-NEXT:    v_or_b32_e32 v1, v1, v2
@@ -2077,42 +2077,42 @@
 ; GFX8-NEXT:    v_cvt_f32_ubyte0_e32 v6, 24
 ; GFX8-NEXT:    v_rcp_iflag_f32_e32 v6, v6
 ; GFX8-NEXT:    s_sub_i32 s4, 0, 24
-; GFX8-NEXT:    v_and_b32_e32 v4, 0xffffff, v4
 ; GFX8-NEXT:    v_cvt_f32_ubyte0_e32 v8, 24
+; GFX8-NEXT:    v_rcp_iflag_f32_e32 v8, v8
 ; GFX8-NEXT:    v_mul_f32_e32 v6, 0x4f7ffffe, v6
 ; GFX8-NEXT:    v_cvt_u32_f32_e32 v6, v6
-; GFX8-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
-; GFX8-NEXT:    v_lshlrev_b32_e32 v1, 1, v1
+; GFX8-NEXT:    v_and_b32_e32 v4, 0xffffff, v4
+; GFX8-NEXT:    v_mul_f32_e32 v8, 0x4f7ffffe, v8
+; GFX8-NEXT:    v_mov_b32_e32 v9, 0xffffff
 ; GFX8-NEXT:    v_mul_lo_u32 v7, s4, v6
+; GFX8-NEXT:    v_and_b32_e32 v5, v5, v9
+; GFX8-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
+; GFX8-NEXT:    v_and_b32_e32 v2, v2, v9
 ; GFX8-NEXT:    v_mul_hi_u32 v7, v6, v7
+; GFX8-NEXT:    v_lshlrev_b32_e32 v1, 1, v1
+; GFX8-NEXT:    v_and_b32_e32 v3, v3, v9
 ; GFX8-NEXT:    v_add_u32_e32 v6, vcc, v6, v7
 ; GFX8-NEXT:    v_mul_hi_u32 v6, v4, v6
-; GFX8-NEXT:    v_rcp_iflag_f32_e32 v7, v8
-; GFX8-NEXT:    v_mov_b32_e32 v8, 0xffffff
-; GFX8-NEXT:    v_and_b32_e32 v5, v5, v8
+; GFX8-NEXT:    v_cvt_u32_f32_e32 v7, v8
 ; GFX8-NEXT:    v_mul_lo_u32 v6, v6, 24
-; GFX8-NEXT:    v_mul_f32_e32 v7, 0x4f7ffffe, v7
-; GFX8-NEXT:    v_cvt_u32_f32_e32 v7, v7
-; GFX8-NEXT:    v_and_b32_e32 v2, v2, v8
+; GFX8-NEXT:    v_mul_lo_u32 v8, s4, v7
 ; GFX8-NEXT:    v_sub_u32_e32 v4, vcc, v4, v6
 ; GFX8-NEXT:    v_subrev_u32_e32 v6, vcc, 24, v4
 ; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v4
+; GFX8-NEXT:    v_mul_hi_u32 v8, v7, v8
 ; GFX8-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
 ; GFX8-NEXT:    v_subrev_u32_e32 v6, vcc, 24, v4
 ; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v4
 ; GFX8-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
-; GFX8-NEXT:    v_mul_lo_u32 v6, s4, v7
-; GFX8-NEXT:    v_sub_u32_e32 v9, vcc, 23, v4
-; GFX8-NEXT:    v_and_b32_e32 v9, v9, v8
-; GFX8-NEXT:    v_and_b32_e32 v4, v4, v8
-; GFX8-NEXT:    v_mul_hi_u32 v6, v7, v6
-; GFX8-NEXT:    v_lshlrev_b32_e32 v0, v9, v0
+; GFX8-NEXT:    v_add_u32_e32 v7, vcc, v7, v8
+; GFX8-NEXT:    v_mul_hi_u32 v7, v5, v7
+; GFX8-NEXT:    v_sub_u32_e32 v6, vcc, 23, v4
+; GFX8-NEXT:    v_and_b32_e32 v6, v6, v9
+; GFX8-NEXT:    v_lshlrev_b32_e32 v0, v6, v0
+; GFX8-NEXT:    v_mul_lo_u32 v6, v7, 24
+; GFX8-NEXT:    v_and_b32_e32 v4, v4, v9
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v2, v4, v2
 ; GFX8-NEXT:    v_or_b32_e32 v0, v0, v2
-; GFX8-NEXT:    v_add_u32_e32 v6, vcc, v7, v6
-; GFX8-NEXT:    v_mul_hi_u32 v6, v5, v6
-; GFX8-NEXT:    v_and_b32_e32 v3, v3, v8
-; GFX8-NEXT:    v_mul_lo_u32 v6, v6, 24
 ; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, v5, v6
 ; GFX8-NEXT:    v_subrev_u32_e32 v4, vcc, 24, v2
 ; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
@@ -2121,8 +2121,8 @@
 ; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
 ; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
 ; GFX8-NEXT:    v_sub_u32_e32 v4, vcc, 23, v2
-; GFX8-NEXT:    v_and_b32_e32 v2, v2, v8
-; GFX8-NEXT:    v_and_b32_e32 v4, v4, v8
+; GFX8-NEXT:    v_and_b32_e32 v2, v2, v9
+; GFX8-NEXT:    v_and_b32_e32 v4, v4, v9
 ; GFX8-NEXT:    v_lshlrev_b32_e32 v1, v4, v1
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v2, v2, v3
 ; GFX8-NEXT:    v_or_b32_e32 v1, v1, v2
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.dec.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.dec.ll
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.dec.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.dec.ll
@@ -365,18 +365,18 @@
 ; CI-LABEL: global_atomic_dec_ret_i32_offset_addr64:
 ; CI:       ; %bb.0:
 ; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
-; CI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
+; CI-NEXT:    v_lshlrev_b32_e32 v4, 2, v0
 ; CI-NEXT:    s_waitcnt lgkmcnt(0)
 ; CI-NEXT:    v_mov_b32_e32 v0, s2
+; CI-NEXT:    v_mov_b32_e32 v3, s1
 ; CI-NEXT:    v_mov_b32_e32 v1, s3
-; CI-NEXT:    v_add_i32_e32 v3, vcc, v0, v2
-; CI-NEXT:    v_addc_u32_e32 v4, vcc, 0, v1, vcc
-; CI-NEXT:    v_mov_b32_e32 v0, s0
-; CI-NEXT:    v_mov_b32_e32 v1, s1
-; CI-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
-; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; CI-NEXT:    v_add_i32_e32 v2, vcc, 20, v3
-; CI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; CI-NEXT:    v_add_i32_e32 v5, vcc, v0, v4
+; CI-NEXT:    v_mov_b32_e32 v2, s0
+; CI-NEXT:    v_addc_u32_e32 v6, vcc, 0, v1, vcc
+; CI-NEXT:    v_add_i32_e32 v0, vcc, v2, v4
+; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
+; CI-NEXT:    v_add_i32_e32 v2, vcc, 20, v5
+; CI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v6, vcc
 ; CI-NEXT:    v_mov_b32_e32 v4, 42
 ; CI-NEXT:    flat_atomic_dec v2, v[2:3], v4 glc
 ; CI-NEXT:    s_waitcnt vmcnt(0)
@@ -386,18 +386,18 @@
 ; VI-LABEL: global_atomic_dec_ret_i32_offset_addr64:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
-; VI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
+; VI-NEXT:    v_lshlrev_b32_e32 v4, 2, v0
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
 ; VI-NEXT:    v_mov_b32_e32 v0, s2
+; VI-NEXT:    v_mov_b32_e32 v3, s1
 ; VI-NEXT:    v_mov_b32_e32 v1, s3
-; VI-NEXT:    v_add_u32_e32 v3, vcc, v0, v2
-; VI-NEXT:    v_addc_u32_e32 v4, vcc, 0, v1, vcc
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v2
-; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT:    v_add_u32_e32 v2, vcc, 20, v3
-; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; VI-NEXT:    v_add_u32_e32 v5, vcc, v0, v4
+; VI-NEXT:    v_mov_b32_e32 v2, s0
+; VI-NEXT:    v_addc_u32_e32 v6, vcc, 0, v1, vcc
+; VI-NEXT:    v_add_u32_e32 v0, vcc, v2, v4
+; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
+; VI-NEXT:    v_add_u32_e32 v2, vcc, 20, v5
+; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v6, vcc
 ; VI-NEXT:    v_mov_b32_e32 v4, 42
 ; VI-NEXT:    flat_atomic_dec v2, v[2:3], v4 glc
 ; VI-NEXT:    s_waitcnt vmcnt(0)
@@ -668,18 +668,18 @@
 ; CI-LABEL: flat_atomic_dec_ret_i32_offset_addr64:
 ; CI:       ; %bb.0:
 ; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
-; CI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
+; CI-NEXT:    v_lshlrev_b32_e32 v4, 2, v0
 ; CI-NEXT:    s_waitcnt lgkmcnt(0)
 ; CI-NEXT:    v_mov_b32_e32 v0, s2
+; CI-NEXT:    v_mov_b32_e32 v3, s1
 ; CI-NEXT:    v_mov_b32_e32 v1, s3
-; CI-NEXT:    v_add_i32_e32 v3, vcc, v0, v2
-; CI-NEXT:    v_addc_u32_e32 v4, vcc, 0, v1, vcc
-; CI-NEXT:    v_mov_b32_e32 v0, s0
-; CI-NEXT:    v_mov_b32_e32 v1, s1
-; CI-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
-; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; CI-NEXT:    v_add_i32_e32 v2, vcc, 20, v3
-; CI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; CI-NEXT:    v_add_i32_e32 v5, vcc, v0, v4
+; CI-NEXT:    v_mov_b32_e32 v2, s0
+; CI-NEXT:    v_addc_u32_e32 v6, vcc, 0, v1, vcc
+; CI-NEXT:    v_add_i32_e32 v0, vcc, v2, v4
+; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
+; CI-NEXT:    v_add_i32_e32 v2, vcc, 20, v5
+; CI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v6, vcc
 ; CI-NEXT:    v_mov_b32_e32 v4, 42
 ; CI-NEXT:    flat_atomic_dec v2, v[2:3], v4 glc
 ; CI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -689,18 +689,18 @@
 ; VI-LABEL: flat_atomic_dec_ret_i32_offset_addr64:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
-; VI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
+; VI-NEXT:    v_lshlrev_b32_e32 v4, 2, v0
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
 ; VI-NEXT:    v_mov_b32_e32 v0, s2
+; VI-NEXT:    v_mov_b32_e32 v3, s1
 ; VI-NEXT:    v_mov_b32_e32 v1, s3
-; VI-NEXT:    v_add_u32_e32 v3, vcc, v0, v2
-; VI-NEXT:    v_addc_u32_e32 v4, vcc, 0, v1, vcc
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v2
-; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT:    v_add_u32_e32 v2, vcc, 20, v3
-; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; VI-NEXT:    v_add_u32_e32 v5, vcc, v0, v4
+; VI-NEXT:    v_mov_b32_e32 v2, s0
+; VI-NEXT:    v_addc_u32_e32 v6, vcc, 0, v1, vcc
+; VI-NEXT:    v_add_u32_e32 v0, vcc, v2, v4
+; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
+; VI-NEXT:    v_add_u32_e32 v2, vcc, 20, v5
+; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v6, vcc
 ; VI-NEXT:    v_mov_b32_e32 v4, 42
 ; VI-NEXT:    flat_atomic_dec v2, v[2:3], v4 glc
 ; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -983,19 +983,19 @@
 ; CI-LABEL: flat_atomic_dec_ret_i64_offset_addr64:
 ; CI:       ; %bb.0:
 ; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
-; CI-NEXT:    v_lshlrev_b32_e32 v2, 3, v0
+; CI-NEXT:    v_lshlrev_b32_e32 v4, 3, v0
 ; CI-NEXT:    s_waitcnt lgkmcnt(0)
 ; CI-NEXT:    v_mov_b32_e32 v0, s2
+; CI-NEXT:    v_mov_b32_e32 v3, s1
 ; CI-NEXT:    v_mov_b32_e32 v1, s3
-; CI-NEXT:    v_add_i32_e32 v3, vcc, v0, v2
-; CI-NEXT:    v_addc_u32_e32 v4, vcc, 0, v1, vcc
-; CI-NEXT:    v_mov_b32_e32 v0, s0
-; CI-NEXT:    v_mov_b32_e32 v1, s1
-; CI-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
-; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; CI-NEXT:    v_add_i32_e32 v2, vcc, 40, v3
-; CI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; CI-NEXT:    v_add_i32_e32 v5, vcc, v0, v4
+; CI-NEXT:    v_mov_b32_e32 v2, s0
+; CI-NEXT:    v_addc_u32_e32 v6, vcc, 0, v1, vcc
+; CI-NEXT:    v_add_i32_e32 v0, vcc, v2, v4
+; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
+; CI-NEXT:    v_add_i32_e32 v2, vcc, 40, v5
 ; CI-NEXT:    v_mov_b32_e32 v4, 42
+; CI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v6, vcc
 ; CI-NEXT:    v_mov_b32_e32 v5, 0
 ; CI-NEXT:    flat_atomic_dec_x2 v[2:3], v[2:3], v[4:5] glc
 ; CI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -1005,19 +1005,19 @@
 ; VI-LABEL: flat_atomic_dec_ret_i64_offset_addr64:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
-; VI-NEXT:    v_lshlrev_b32_e32 v2, 3, v0
+; VI-NEXT:    v_lshlrev_b32_e32 v4, 3, v0
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
 ; VI-NEXT:    v_mov_b32_e32 v0, s2
+; VI-NEXT:    v_mov_b32_e32 v3, s1
 ; VI-NEXT:    v_mov_b32_e32 v1, s3
-; VI-NEXT:    v_add_u32_e32 v3, vcc, v0, v2
-; VI-NEXT:    v_addc_u32_e32 v4, vcc, 0, v1, vcc
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v2
-; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT:    v_add_u32_e32 v2, vcc, 40, v3
-; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; VI-NEXT:    v_add_u32_e32 v5, vcc, v0, v4
+; VI-NEXT:    v_mov_b32_e32 v2, s0
+; VI-NEXT:    v_addc_u32_e32 v6, vcc, 0, v1, vcc
+; VI-NEXT:    v_add_u32_e32 v0, vcc, v2, v4
+; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
+; VI-NEXT:    v_add_u32_e32 v2, vcc, 40, v5
 ; VI-NEXT:    v_mov_b32_e32 v4, 42
+; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v6, vcc
 ; VI-NEXT:    v_mov_b32_e32 v5, 0
 ; VI-NEXT:    flat_atomic_dec_x2 v[2:3], v[2:3], v[4:5] glc
 ; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -1542,19 +1542,19 @@
 ; CI-LABEL: global_atomic_dec_ret_i64_offset_addr64:
 ; CI:       ; %bb.0:
 ; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
-; CI-NEXT:    v_lshlrev_b32_e32 v2, 3, v0
+; CI-NEXT:    v_lshlrev_b32_e32 v4, 3, v0
 ; CI-NEXT:    s_waitcnt lgkmcnt(0)
 ; CI-NEXT:    v_mov_b32_e32 v0, s2
+; CI-NEXT:    v_mov_b32_e32 v3, s1
 ; CI-NEXT:    v_mov_b32_e32 v1, s3
-; CI-NEXT:    v_add_i32_e32 v3, vcc, v0, v2
-; CI-NEXT:    v_addc_u32_e32 v4, vcc, 0, v1, vcc
-; CI-NEXT:    v_mov_b32_e32 v0, s0
-; CI-NEXT:    v_mov_b32_e32 v1, s1
-; CI-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
-; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; CI-NEXT:    v_add_i32_e32 v2, vcc, 40, v3
-; CI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; CI-NEXT:    v_add_i32_e32 v5, vcc, v0, v4
+; CI-NEXT:    v_mov_b32_e32 v2, s0
+; CI-NEXT:    v_addc_u32_e32 v6, vcc, 0, v1, vcc
+; CI-NEXT:    v_add_i32_e32 v0, vcc, v2, v4
+; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
+; CI-NEXT:    v_add_i32_e32 v2, vcc, 40, v5
 ; CI-NEXT:    v_mov_b32_e32 v4, 42
+; CI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v6, vcc
 ; CI-NEXT:    v_mov_b32_e32 v5, 0
 ; CI-NEXT:    flat_atomic_dec_x2 v[2:3], v[2:3], v[4:5] glc
 ; CI-NEXT:    s_waitcnt vmcnt(0)
@@ -1564,19 +1564,19 @@
 ; VI-LABEL: global_atomic_dec_ret_i64_offset_addr64:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
-; VI-NEXT:    v_lshlrev_b32_e32 v2, 3, v0
+; VI-NEXT:    v_lshlrev_b32_e32 v4, 3, v0
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
 ; VI-NEXT:    v_mov_b32_e32 v0, s2
+; VI-NEXT:    v_mov_b32_e32 v3, s1
 ; VI-NEXT:    v_mov_b32_e32 v1, s3
-; VI-NEXT:    v_add_u32_e32 v3, vcc, v0, v2
-; VI-NEXT:    v_addc_u32_e32 v4, vcc, 0, v1, vcc
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v2
-; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT:    v_add_u32_e32 v2, vcc, 40, v3
-; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; VI-NEXT:    v_add_u32_e32 v5, vcc, v0, v4
+; VI-NEXT:    v_mov_b32_e32 v2, s0
+; VI-NEXT:    v_addc_u32_e32 v6, vcc, 0, v1, vcc
+; VI-NEXT:    v_add_u32_e32 v0, vcc, v2, v4
+; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
+; VI-NEXT:    v_add_u32_e32 v2, vcc, 40, v5
 ; VI-NEXT:    v_mov_b32_e32 v4, 42
+; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v6, vcc
 ; VI-NEXT:    v_mov_b32_e32 v5, 0
 ; VI-NEXT:    flat_atomic_dec_x2 v[2:3], v[2:3], v[4:5] glc
 ; VI-NEXT:    s_waitcnt vmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll
@@ -351,18 +351,18 @@
 ; CI-LABEL: global_atomic_inc_ret_i32_offset_addr64:
 ; CI:       ; %bb.0:
 ; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
-; CI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
+; CI-NEXT:    v_lshlrev_b32_e32 v4, 2, v0
 ; CI-NEXT:    s_waitcnt lgkmcnt(0)
 ; CI-NEXT:    v_mov_b32_e32 v0, s2
+; CI-NEXT:    v_mov_b32_e32 v3, s1
 ; CI-NEXT:    v_mov_b32_e32 v1, s3
-; CI-NEXT:    v_add_i32_e32 v3, vcc, v0, v2
-; CI-NEXT:    v_addc_u32_e32 v4, vcc, 0, v1, vcc
-; CI-NEXT:    v_mov_b32_e32 v0, s0
-; CI-NEXT:    v_mov_b32_e32 v1, s1
-; CI-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
-; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; CI-NEXT:    v_add_i32_e32 v2, vcc, 20, v3
-; CI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; CI-NEXT:    v_add_i32_e32 v5, vcc, v0, v4
+; CI-NEXT:    v_mov_b32_e32 v2, s0
+; CI-NEXT:    v_addc_u32_e32 v6, vcc, 0, v1, vcc
+; CI-NEXT:    v_add_i32_e32 v0, vcc, v2, v4
+; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
+; CI-NEXT:    v_add_i32_e32 v2, vcc, 20, v5
+; CI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v6, vcc
 ; CI-NEXT:    v_mov_b32_e32 v4, 42
 ; CI-NEXT:    flat_atomic_inc v2, v[2:3], v4 glc
 ; CI-NEXT:    s_waitcnt vmcnt(0)
@@ -372,18 +372,18 @@
 ; VI-LABEL: global_atomic_inc_ret_i32_offset_addr64:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
-; VI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
+; VI-NEXT:    v_lshlrev_b32_e32 v4, 2, v0
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
 ; VI-NEXT:    v_mov_b32_e32 v0, s2
+; VI-NEXT:    v_mov_b32_e32 v3, s1
 ; VI-NEXT:    v_mov_b32_e32 v1, s3
-; VI-NEXT:    v_add_u32_e32 v3, vcc, v0, v2
-; VI-NEXT:    v_addc_u32_e32 v4, vcc, 0, v1, vcc
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v2
-; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT:    v_add_u32_e32 v2, vcc, 20, v3
-; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; VI-NEXT:    v_add_u32_e32 v5, vcc, v0, v4
+; VI-NEXT:    v_mov_b32_e32 v2, s0
+; VI-NEXT:    v_addc_u32_e32 v6, vcc, 0, v1, vcc
+; VI-NEXT:    v_add_u32_e32 v0, vcc, v2, v4
+; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
+; VI-NEXT:    v_add_u32_e32 v2, vcc, 20, v5
+; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v6, vcc
 ; VI-NEXT:    v_mov_b32_e32 v4, 42
 ; VI-NEXT:    flat_atomic_inc v2, v[2:3], v4 glc
 ; VI-NEXT:    s_waitcnt vmcnt(0)
@@ -869,19 +869,19 @@
 ; CI-LABEL: global_atomic_inc_ret_i64_offset_addr64:
 ; CI:       ; %bb.0:
 ; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
-; CI-NEXT:    v_lshlrev_b32_e32 v2, 3, v0
+; CI-NEXT:    v_lshlrev_b32_e32 v4, 3, v0
 ; CI-NEXT:    s_waitcnt lgkmcnt(0)
 ; CI-NEXT:    v_mov_b32_e32 v0, s2
+; CI-NEXT:    v_mov_b32_e32 v3, s1
 ; CI-NEXT:    v_mov_b32_e32 v1, s3
-; CI-NEXT:    v_add_i32_e32 v3, vcc, v0, v2
-; CI-NEXT:    v_addc_u32_e32 v4, vcc, 0, v1, vcc
-; CI-NEXT:    v_mov_b32_e32 v0, s0
-; CI-NEXT:    v_mov_b32_e32 v1, s1
-; CI-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
-; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; CI-NEXT:    v_add_i32_e32 v2, vcc, 40, v3
-; CI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; CI-NEXT:    v_add_i32_e32 v5, vcc, v0, v4
+; CI-NEXT:    v_mov_b32_e32 v2, s0
+; CI-NEXT:    v_addc_u32_e32 v6, vcc, 0, v1, vcc
+; CI-NEXT:    v_add_i32_e32 v0, vcc, v2, v4
+; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
+; CI-NEXT:    v_add_i32_e32 v2, vcc, 40, v5
 ; CI-NEXT:    v_mov_b32_e32 v4, 42
+; CI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v6, vcc
 ; CI-NEXT:    v_mov_b32_e32 v5, 0
 ; CI-NEXT:    flat_atomic_inc_x2 v[2:3], v[2:3], v[4:5] glc
 ; CI-NEXT:    s_waitcnt vmcnt(0)
@@ -891,19 +891,19 @@
 ; VI-LABEL: global_atomic_inc_ret_i64_offset_addr64:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
-; VI-NEXT:    v_lshlrev_b32_e32 v2, 3, v0
+; VI-NEXT:    v_lshlrev_b32_e32 v4, 3, v0
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
 ; VI-NEXT:    v_mov_b32_e32 v0, s2
+; VI-NEXT:    v_mov_b32_e32 v3, s1
 ; VI-NEXT:    v_mov_b32_e32 v1, s3
-; VI-NEXT:    v_add_u32_e32 v3, vcc, v0, v2
-; VI-NEXT:    v_addc_u32_e32 v4, vcc, 0, v1, vcc
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v2
-; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT:    v_add_u32_e32 v2, vcc, 40, v3
-; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; VI-NEXT:    v_add_u32_e32 v5, vcc, v0, v4
+; VI-NEXT:    v_mov_b32_e32 v2, s0
+; VI-NEXT:    v_addc_u32_e32 v6, vcc, 0, v1, vcc
+; VI-NEXT:    v_add_u32_e32 v0, vcc, v2, v4
+; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
+; VI-NEXT:    v_add_u32_e32 v2, vcc, 40, v5
 ; VI-NEXT:    v_mov_b32_e32 v4, 42
+; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v6, vcc
 ; VI-NEXT:    v_mov_b32_e32 v5, 0
 ; VI-NEXT:    flat_atomic_inc_x2 v[2:3], v[2:3], v[4:5] glc
 ; VI-NEXT:    s_waitcnt vmcnt(0)
@@ -1107,18 +1107,18 @@
 ; CI-LABEL: flat_atomic_inc_ret_i32_offset_addr64:
 ; CI:       ; %bb.0:
 ; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
-; CI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
+; CI-NEXT:    v_lshlrev_b32_e32 v4, 2, v0
 ; CI-NEXT:    s_waitcnt lgkmcnt(0)
 ; CI-NEXT:    v_mov_b32_e32 v0, s2
+; CI-NEXT:    v_mov_b32_e32 v3, s1
 ; CI-NEXT:    v_mov_b32_e32 v1, s3
-; CI-NEXT:    v_add_i32_e32 v3, vcc, v0, v2
-; CI-NEXT:    v_addc_u32_e32 v4, vcc, 0, v1, vcc
-; CI-NEXT:    v_mov_b32_e32 v0, s0
-; CI-NEXT:    v_mov_b32_e32 v1, s1
-; CI-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
-; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; CI-NEXT:    v_add_i32_e32 v2, vcc, 20, v3
-; CI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; CI-NEXT:    v_add_i32_e32 v5, vcc, v0, v4
+; CI-NEXT:    v_mov_b32_e32 v2, s0
+; CI-NEXT:    v_addc_u32_e32 v6, vcc, 0, v1, vcc
+; CI-NEXT:    v_add_i32_e32 v0, vcc, v2, v4
+; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
+; CI-NEXT:    v_add_i32_e32 v2, vcc, 20, v5
+; CI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v6, vcc
 ; CI-NEXT:    v_mov_b32_e32 v4, 42
 ; CI-NEXT:    flat_atomic_inc v2, v[2:3], v4 glc
 ; CI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -1128,18 +1128,18 @@
 ; VI-LABEL: flat_atomic_inc_ret_i32_offset_addr64:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
-; VI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
+; VI-NEXT:    v_lshlrev_b32_e32 v4, 2, v0
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
 ; VI-NEXT:    v_mov_b32_e32 v0, s2
+; VI-NEXT:    v_mov_b32_e32 v3, s1
 ; VI-NEXT:    v_mov_b32_e32 v1, s3
-; VI-NEXT:    v_add_u32_e32 v3, vcc, v0, v2
-; VI-NEXT:    v_addc_u32_e32 v4, vcc, 0, v1, vcc
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v2
-; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT:    v_add_u32_e32 v2, vcc, 20, v3
-; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; VI-NEXT:    v_add_u32_e32 v5, vcc, v0, v4
+; VI-NEXT:    v_mov_b32_e32 v2, s0
+; VI-NEXT:    v_addc_u32_e32 v6, vcc, 0, v1, vcc
+; VI-NEXT:    v_add_u32_e32 v0, vcc, v2, v4
+; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
+; VI-NEXT:    v_add_u32_e32 v2, vcc, 20, v5
+; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v6, vcc
 ; VI-NEXT:    v_mov_b32_e32 v4, 42
 ; VI-NEXT:    flat_atomic_inc v2, v[2:3], v4 glc
 ; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -1155,8 +1155,8 @@
 ; GFX9-NEXT:    v_mov_b32_e32 v3, s1
 ; GFX9-NEXT:    v_mov_b32_e32 v1, s3
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v4
-; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
 ; GFX9-NEXT:    v_mov_b32_e32 v2, s0
+; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v4
 ; GFX9-NEXT:    v_mov_b32_e32 v4, 42
 ; GFX9-NEXT:    flat_atomic_inc v0, v[0:1], v4 offset:20 glc
@@ -1420,19 +1420,19 @@
 ; CI-LABEL: flat_atomic_inc_ret_i64_offset_addr64:
 ; CI:       ; %bb.0:
 ; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
-; CI-NEXT:    v_lshlrev_b32_e32 v2, 3, v0
+; CI-NEXT:    v_lshlrev_b32_e32 v4, 3, v0
 ; CI-NEXT:    s_waitcnt lgkmcnt(0)
 ; CI-NEXT:    v_mov_b32_e32 v0, s2
+; CI-NEXT:    v_mov_b32_e32 v3, s1
 ; CI-NEXT:    v_mov_b32_e32 v1, s3
-; CI-NEXT:    v_add_i32_e32 v3, vcc, v0, v2
-; CI-NEXT:    v_addc_u32_e32 v4, vcc, 0, v1, vcc
-; CI-NEXT:    v_mov_b32_e32 v0, s0
-; CI-NEXT:    v_mov_b32_e32 v1, s1
-; CI-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
-; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; CI-NEXT:    v_add_i32_e32 v2, vcc, 40, v3
-; CI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; CI-NEXT:    v_add_i32_e32 v5, vcc, v0, v4
+; CI-NEXT:    v_mov_b32_e32 v2, s0
+; CI-NEXT:    v_addc_u32_e32 v6, vcc, 0, v1, vcc
+; CI-NEXT:    v_add_i32_e32 v0, vcc, v2, v4
+; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
+; CI-NEXT:    v_add_i32_e32 v2, vcc, 40, v5
 ; CI-NEXT:    v_mov_b32_e32 v4, 42
+; CI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v6, vcc
 ; CI-NEXT:    v_mov_b32_e32 v5, 0
 ; CI-NEXT:    flat_atomic_inc_x2 v[2:3], v[2:3], v[4:5] glc
 ; CI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -1442,19 +1442,19 @@
 ; VI-LABEL: flat_atomic_inc_ret_i64_offset_addr64:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
-; VI-NEXT:    v_lshlrev_b32_e32 v2, 3, v0
+; VI-NEXT:    v_lshlrev_b32_e32 v4, 3, v0
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
 ; VI-NEXT:    v_mov_b32_e32 v0, s2
+; VI-NEXT:    v_mov_b32_e32 v3, s1
 ; VI-NEXT:    v_mov_b32_e32 v1, s3
-; VI-NEXT:    v_add_u32_e32 v3, vcc, v0, v2
-; VI-NEXT:    v_addc_u32_e32 v4, vcc, 0, v1, vcc
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v2
-; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT:    v_add_u32_e32 v2, vcc, 40, v3
-; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; VI-NEXT:    v_add_u32_e32 v5, vcc, v0, v4
+; VI-NEXT:    v_mov_b32_e32 v2, s0
+; VI-NEXT:    v_addc_u32_e32 v6, vcc, 0, v1, vcc
+; VI-NEXT:    v_add_u32_e32 v0, vcc, v2, v4
+; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
+; VI-NEXT:    v_add_u32_e32 v2, vcc, 40, v5
 ; VI-NEXT:    v_mov_b32_e32 v4, 42
+; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v6, vcc
 ; VI-NEXT:    v_mov_b32_e32 v5, 0
 ; VI-NEXT:    flat_atomic_inc_x2 v[2:3], v[2:3], v[4:5] glc
 ; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -1470,8 +1470,8 @@
 ; GFX9-NEXT:    v_mov_b32_e32 v3, s1
 ; GFX9-NEXT:    v_mov_b32_e32 v1, s3
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v4
-; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
 ; GFX9-NEXT:    v_mov_b32_e32 v2, s0
+; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v4
 ; GFX9-NEXT:    v_mov_b32_e32 v4, 42
 ; GFX9-NEXT:    v_mov_b32_e32 v5, 0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll
@@ -971,10 +971,10 @@
 ;
 ; GFX8-LABEL: test_div_fmas_f32_i1_phi_vcc:
 ; GFX8:       ; %bb.0: ; %entry
-; GFX8-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
+; GFX8-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
 ; GFX8-NEXT:    s_load_dwordx2 s[6:7], s[0:1], 0x4c
 ; GFX8-NEXT:    v_lshlrev_b32_e32 v3, 2, v0
-; GFX8-NEXT:    s_mov_b32 s2, 0
+; GFX8-NEXT:    s_mov_b32 s4, 0
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s6
 ; GFX8-NEXT:    v_mov_b32_e32 v2, s7
@@ -990,12 +990,12 @@
 ; GFX8-NEXT:    s_load_dword s0, s[0:1], 0x0
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NEXT:    s_cmp_lg_u32 s0, 0
-; GFX8-NEXT:    s_cselect_b32 s2, 1, 0
+; GFX8-NEXT:    s_cselect_b32 s4, 1, 0
 ; GFX8-NEXT:  BB13_2: ; %exit
 ; GFX8-NEXT:    s_or_b64 exec, exec, s[6:7]
-; GFX8-NEXT:    s_add_u32 s0, s4, 8
-; GFX8-NEXT:    s_addc_u32 s1, s5, 0
-; GFX8-NEXT:    s_and_b32 s2, 1, s2
+; GFX8-NEXT:    s_add_u32 s0, s2, 8
+; GFX8-NEXT:    s_addc_u32 s1, s3, 0
+; GFX8-NEXT:    s_and_b32 s2, 1, s4
 ; GFX8-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s2
 ; GFX8-NEXT:    s_waitcnt vmcnt(0)
 ; GFX8-NEXT:    s_nop 2
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
@@ -245,25 +245,23 @@
 ; GFX7-LABEL: v_mul_i64:
 ; GFX7:       ; %bb.0:
 ; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT:    v_mul_lo_u32 v4, v0, v3
 ; GFX7-NEXT:    v_mul_lo_u32 v1, v1, v2
-; GFX7-NEXT:    v_mul_lo_u32 v3, v0, v2
-; GFX7-NEXT:    v_mul_hi_u32 v0, v0, v2
+; GFX7-NEXT:    v_mul_lo_u32 v3, v0, v3
+; GFX7-NEXT:    v_mul_hi_u32 v4, v0, v2
+; GFX7-NEXT:    v_mul_lo_u32 v0, v0, v2
+; GFX7-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
 ; GFX7-NEXT:    v_add_i32_e32 v1, vcc, v1, v4
-; GFX7-NEXT:    v_add_i32_e32 v1, vcc, v1, v0
-; GFX7-NEXT:    v_mov_b32_e32 v0, v3
 ; GFX7-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX8-LABEL: v_mul_i64:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT:    v_mul_lo_u32 v4, v0, v3
 ; GFX8-NEXT:    v_mul_lo_u32 v1, v1, v2
-; GFX8-NEXT:    v_mul_lo_u32 v3, v0, v2
-; GFX8-NEXT:    v_mul_hi_u32 v0, v0, v2
+; GFX8-NEXT:    v_mul_lo_u32 v3, v0, v3
+; GFX8-NEXT:    v_mul_hi_u32 v4, v0, v2
+; GFX8-NEXT:    v_mul_lo_u32 v0, v0, v2
+; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v3
 ; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v4
-; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v0
-; GFX8-NEXT:    v_mov_b32_e32 v0, v3
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: v_mul_i64:
@@ -1595,12 +1593,11 @@
 ; GFX7-NEXT:    v_add_i32_e32 v18, vcc, v19, v18
 ; GFX7-NEXT:    v_cndmask_b32_e64 v19, 0, 1, vcc
 ; GFX7-NEXT:    v_add_i32_e32 v19, vcc, v20, v19
+; GFX7-NEXT:    v_mul_hi_u32 v20, v0, v9
 ; GFX7-NEXT:    v_add_i32_e32 v18, vcc, v18, v21
-; GFX7-NEXT:    v_mul_hi_u32 v21, v0, v9
-; GFX7-NEXT:    v_cndmask_b32_e64 v20, 0, 1, vcc
-; GFX7-NEXT:    v_add_i32_e32 v19, vcc, v19, v20
-; GFX7-NEXT:    v_mul_lo_u32 v22, v0, v11
-; GFX7-NEXT:    v_add_i32_e32 v18, vcc, v18, v21
+; GFX7-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v19, vcc, v19, v21
+; GFX7-NEXT:    v_add_i32_e32 v18, vcc, v18, v20
 ; GFX7-NEXT:    v_cndmask_b32_e64 v20, 0, 1, vcc
 ; GFX7-NEXT:    v_add_i32_e32 v19, vcc, v19, v20
 ; GFX7-NEXT:    v_add_i32_e32 v17, vcc, v18, v17
@@ -1609,27 +1606,25 @@
 ; GFX7-NEXT:    v_mul_lo_u32 v21, v2, v9
 ; GFX7-NEXT:    v_add_i32_e32 v18, vcc, v19, v18
 ; GFX7-NEXT:    v_mul_lo_u32 v19, v1, v10
-; GFX7-NEXT:    v_mul_lo_u32 v23, v1, v11
+; GFX7-NEXT:    v_mul_lo_u32 v22, v0, v11
 ; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v20, v21
 ; GFX7-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
 ; GFX7-NEXT:    v_add_i32_e32 v19, vcc, v20, v19
 ; GFX7-NEXT:    v_cndmask_b32_e64 v20, 0, 1, vcc
 ; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v21, v20
+; GFX7-NEXT:    v_mul_hi_u32 v21, v2, v8
 ; GFX7-NEXT:    v_add_i32_e32 v19, vcc, v19, v22
-; GFX7-NEXT:    v_mul_hi_u32 v22, v2, v8
-; GFX7-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
-; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v20, v21
-; GFX7-NEXT:    v_mul_lo_u32 v7, v7, v8
-; GFX7-NEXT:    v_add_i32_e32 v19, vcc, v19, v22
+; GFX7-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v20, v22
 ; GFX7-NEXT:    v_mul_hi_u32 v22, v1, v9
+; GFX7-NEXT:    v_add_i32_e32 v19, vcc, v19, v21
 ; GFX7-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
 ; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v20, v21
-; GFX7-NEXT:    v_mul_lo_u32 v15, v0, v15
-; GFX7-NEXT:    v_add_i32_e32 v19, vcc, v19, v22
-; GFX7-NEXT:    v_mul_hi_u32 v22, v0, v10
-; GFX7-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
-; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v20, v21
+; GFX7-NEXT:    v_mul_hi_u32 v21, v0, v10
 ; GFX7-NEXT:    v_add_i32_e32 v19, vcc, v19, v22
+; GFX7-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v20, v22
+; GFX7-NEXT:    v_add_i32_e32 v19, vcc, v19, v21
 ; GFX7-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
 ; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v20, v21
 ; GFX7-NEXT:    v_add_i32_e32 v18, vcc, v19, v18
@@ -1638,32 +1633,33 @@
 ; GFX7-NEXT:    v_mul_lo_u32 v22, v3, v9
 ; GFX7-NEXT:    v_add_i32_e32 v19, vcc, v20, v19
 ; GFX7-NEXT:    v_mul_lo_u32 v20, v2, v10
+; GFX7-NEXT:    v_mul_lo_u32 v23, v1, v11
 ; GFX7-NEXT:    v_add_i32_e32 v21, vcc, v21, v22
 ; GFX7-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
 ; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v21, v20
 ; GFX7-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
 ; GFX7-NEXT:    v_add_i32_e32 v21, vcc, v22, v21
+; GFX7-NEXT:    v_mul_lo_u32 v22, v0, v12
 ; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v20, v23
-; GFX7-NEXT:    v_mul_lo_u32 v23, v0, v12
-; GFX7-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
-; GFX7-NEXT:    v_add_i32_e32 v21, vcc, v21, v22
-; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v20, v23
+; GFX7-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v21, vcc, v21, v23
 ; GFX7-NEXT:    v_mul_hi_u32 v23, v3, v8
+; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v20, v22
 ; GFX7-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
 ; GFX7-NEXT:    v_add_i32_e32 v21, vcc, v21, v22
+; GFX7-NEXT:    v_mul_hi_u32 v22, v2, v9
 ; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v20, v23
-; GFX7-NEXT:    v_mul_hi_u32 v23, v2, v9
-; GFX7-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
-; GFX7-NEXT:    v_add_i32_e32 v21, vcc, v21, v22
-; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v20, v23
+; GFX7-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v21, vcc, v21, v23
 ; GFX7-NEXT:    v_mul_hi_u32 v23, v1, v10
+; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v20, v22
 ; GFX7-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
 ; GFX7-NEXT:    v_add_i32_e32 v21, vcc, v21, v22
+; GFX7-NEXT:    v_mul_hi_u32 v22, v0, v11
 ; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v20, v23
-; GFX7-NEXT:    v_mul_hi_u32 v23, v0, v11
-; GFX7-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
-; GFX7-NEXT:    v_add_i32_e32 v21, vcc, v21, v22
-; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v20, v23
+; GFX7-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v21, vcc, v21, v23
+; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v20, v22
 ; GFX7-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
 ; GFX7-NEXT:    v_add_i32_e32 v21, vcc, v21, v22
 ; GFX7-NEXT:    v_add_i32_e32 v19, vcc, v20, v19
@@ -1672,12 +1668,14 @@
 ; GFX7-NEXT:    v_mul_lo_u32 v23, v4, v9
 ; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v21, v20
 ; GFX7-NEXT:    v_mul_lo_u32 v21, v3, v10
+; GFX7-NEXT:    v_mul_lo_u32 v7, v7, v8
 ; GFX7-NEXT:    v_add_i32_e32 v22, vcc, v22, v23
 ; GFX7-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
 ; GFX7-NEXT:    v_add_i32_e32 v21, vcc, v22, v21
 ; GFX7-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
 ; GFX7-NEXT:    v_add_i32_e32 v22, vcc, v23, v22
 ; GFX7-NEXT:    v_mul_lo_u32 v23, v2, v11
+; GFX7-NEXT:    v_mul_lo_u32 v15, v0, v15
 ; GFX7-NEXT:    v_add_i32_e32 v21, vcc, v21, v23
 ; GFX7-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
 ; GFX7-NEXT:    v_add_i32_e32 v22, vcc, v22, v23
@@ -1821,12 +1819,11 @@
 ; GFX8-NEXT:    v_add_u32_e32 v18, vcc, v19, v18
 ; GFX8-NEXT:    v_cndmask_b32_e64 v19, 0, 1, vcc
 ; GFX8-NEXT:    v_add_u32_e32 v19, vcc, v20, v19
+; GFX8-NEXT:    v_mul_hi_u32 v20, v0, v9
 ; GFX8-NEXT:    v_add_u32_e32 v18, vcc, v18, v21
-; GFX8-NEXT:    v_mul_hi_u32 v21, v0, v9
-; GFX8-NEXT:    v_cndmask_b32_e64 v20, 0, 1, vcc
-; GFX8-NEXT:    v_add_u32_e32 v19, vcc, v19, v20
-; GFX8-NEXT:    v_mul_lo_u32 v22, v0, v11
-; GFX8-NEXT:    v_add_u32_e32 v18, vcc, v18, v21
+; GFX8-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v19, vcc, v19, v21
+; GFX8-NEXT:    v_add_u32_e32 v18, vcc, v18, v20
 ; GFX8-NEXT:    v_cndmask_b32_e64 v20, 0, 1, vcc
 ; GFX8-NEXT:    v_add_u32_e32 v19, vcc, v19, v20
 ; GFX8-NEXT:    v_add_u32_e32 v17, vcc, v18, v17
@@ -1835,27 +1832,25 @@
 ; GFX8-NEXT:    v_mul_lo_u32 v21, v2, v9
 ; GFX8-NEXT:    v_add_u32_e32 v18, vcc, v19, v18
 ; GFX8-NEXT:    v_mul_lo_u32 v19, v1, v10
-; GFX8-NEXT:    v_mul_lo_u32 v23, v1, v11
+; GFX8-NEXT:    v_mul_lo_u32 v22, v0, v11
 ; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v20, v21
 ; GFX8-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
 ; GFX8-NEXT:    v_add_u32_e32 v19, vcc, v20, v19
 ; GFX8-NEXT:    v_cndmask_b32_e64 v20, 0, 1, vcc
 ; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v21, v20
+; GFX8-NEXT:    v_mul_hi_u32 v21, v2, v8
 ; GFX8-NEXT:    v_add_u32_e32 v19, vcc, v19, v22
-; GFX8-NEXT:    v_mul_hi_u32 v22, v2, v8
-; GFX8-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
-; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v20, v21
-; GFX8-NEXT:    v_mul_lo_u32 v7, v7, v8
-; GFX8-NEXT:    v_add_u32_e32 v19, vcc, v19, v22
+; GFX8-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v20, v22
 ; GFX8-NEXT:    v_mul_hi_u32 v22, v1, v9
+; GFX8-NEXT:    v_add_u32_e32 v19, vcc, v19, v21
 ; GFX8-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
 ; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v20, v21
-; GFX8-NEXT:    v_mul_lo_u32 v15, v0, v15
-; GFX8-NEXT:    v_add_u32_e32 v19, vcc, v19, v22
-; GFX8-NEXT:    v_mul_hi_u32 v22, v0, v10
-; GFX8-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
-; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v20, v21
+; GFX8-NEXT:    v_mul_hi_u32 v21, v0, v10
 ; GFX8-NEXT:    v_add_u32_e32 v19, vcc, v19, v22
+; GFX8-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v20, v22
+; GFX8-NEXT:    v_add_u32_e32 v19, vcc, v19, v21
 ; GFX8-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
 ; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v20, v21
 ; GFX8-NEXT:    v_add_u32_e32 v18, vcc, v19, v18
@@ -1864,32 +1859,33 @@
 ; GFX8-NEXT:    v_mul_lo_u32 v22, v3, v9
 ; GFX8-NEXT:    v_add_u32_e32 v19, vcc, v20, v19
 ; GFX8-NEXT:    v_mul_lo_u32 v20, v2, v10
+; GFX8-NEXT:    v_mul_lo_u32 v23, v1, v11
 ; GFX8-NEXT:    v_add_u32_e32 v21, vcc, v21, v22
 ; GFX8-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
 ; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v21, v20
 ; GFX8-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
 ; GFX8-NEXT:    v_add_u32_e32 v21, vcc, v22, v21
+; GFX8-NEXT:    v_mul_lo_u32 v22, v0, v12
 ; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v20, v23
-; GFX8-NEXT:    v_mul_lo_u32 v23, v0, v12
-; GFX8-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
-; GFX8-NEXT:    v_add_u32_e32 v21, vcc, v21, v22
-; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v20, v23
+; GFX8-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v21, vcc, v21, v23
 ; GFX8-NEXT:    v_mul_hi_u32 v23, v3, v8
+; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v20, v22
 ; GFX8-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
 ; GFX8-NEXT:    v_add_u32_e32 v21, vcc, v21, v22
+; GFX8-NEXT:    v_mul_hi_u32 v22, v2, v9
 ; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v20, v23
-; GFX8-NEXT:    v_mul_hi_u32 v23, v2, v9
-; GFX8-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
-; GFX8-NEXT:    v_add_u32_e32 v21, vcc, v21, v22
-; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v20, v23
+; GFX8-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v21, vcc, v21, v23
 ; GFX8-NEXT:    v_mul_hi_u32 v23, v1, v10
+; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v20, v22
 ; GFX8-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
 ; GFX8-NEXT:    v_add_u32_e32 v21, vcc, v21, v22
+; GFX8-NEXT:    v_mul_hi_u32 v22, v0, v11
 ; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v20, v23
-; GFX8-NEXT:    v_mul_hi_u32 v23, v0, v11
-; GFX8-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
-; GFX8-NEXT:    v_add_u32_e32 v21, vcc, v21, v22
-; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v20, v23
+; GFX8-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v21, vcc, v21, v23
+; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v20, v22
 ; GFX8-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
 ; GFX8-NEXT:    v_add_u32_e32 v21, vcc, v21, v22
 ; GFX8-NEXT:    v_add_u32_e32 v19, vcc, v20, v19
@@ -1898,12 +1894,14 @@
 ; GFX8-NEXT:    v_mul_lo_u32 v23, v4, v9
 ; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v21, v20
 ; GFX8-NEXT:    v_mul_lo_u32 v21, v3, v10
+; GFX8-NEXT:    v_mul_lo_u32 v7, v7, v8
 ; GFX8-NEXT:    v_add_u32_e32 v22, vcc, v22, v23
 ; GFX8-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
 ; GFX8-NEXT:    v_add_u32_e32 v21, vcc, v22, v21
 ; GFX8-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
 ; GFX8-NEXT:    v_add_u32_e32 v22, vcc, v23, v22
 ; GFX8-NEXT:    v_mul_lo_u32 v23, v2, v11
+; GFX8-NEXT:    v_mul_lo_u32 v15, v0, v15
 ; GFX8-NEXT:    v_add_u32_e32 v21, vcc, v21, v23
 ; GFX8-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
 ; GFX8-NEXT:    v_add_u32_e32 v22, vcc, v22, v23
@@ -2062,9 +2060,9 @@
 ; GFX9-NEXT:    v_mul_lo_u32 v22, v0, v11
 ; GFX9-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v19, vcc, v20, v19
+; GFX9-NEXT:    v_mul_hi_u32 v23, v2, v8
 ; GFX9-NEXT:    v_cndmask_b32_e64 v20, 0, 1, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v19, vcc, v19, v22
-; GFX9-NEXT:    v_mul_hi_u32 v23, v2, v8
 ; GFX9-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
 ; GFX9-NEXT:    v_add3_u32 v20, v21, v20, v22
 ; GFX9-NEXT:    v_mul_hi_u32 v21, v1, v9
@@ -2073,23 +2071,23 @@
 ; GFX9-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v19, vcc, v19, v21
 ; GFX9-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
-; GFX9-NEXT:    v_add3_u32 v20, v20, v22, v21
 ; GFX9-NEXT:    v_add_co_u32_e32 v19, vcc, v19, v23
-; GFX9-NEXT:    v_mul_lo_u32 v22, v4, v8
-; GFX9-NEXT:    v_mul_lo_u32 v23, v3, v9
+; GFX9-NEXT:    v_add3_u32 v20, v20, v22, v21
 ; GFX9-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v18, vcc, v19, v18
 ; GFX9-NEXT:    v_cndmask_b32_e64 v19, 0, 1, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v22, v4, v8
+; GFX9-NEXT:    v_mul_lo_u32 v23, v3, v9
 ; GFX9-NEXT:    v_add3_u32 v19, v20, v21, v19
 ; GFX9-NEXT:    v_mul_lo_u32 v20, v2, v10
-; GFX9-NEXT:    v_add_co_u32_e32 v21, vcc, v22, v23
-; GFX9-NEXT:    v_mul_lo_u32 v23, v1, v11
+; GFX9-NEXT:    v_mul_lo_u32 v21, v1, v11
+; GFX9-NEXT:    v_add_co_u32_e32 v22, vcc, v22, v23
+; GFX9-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v20, vcc, v22, v20
 ; GFX9-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v20, vcc, v21, v20
+; GFX9-NEXT:    v_add_co_u32_e32 v20, vcc, v20, v21
 ; GFX9-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v20, vcc, v20, v23
-; GFX9-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
-; GFX9-NEXT:    v_add3_u32 v21, v22, v21, v23
+; GFX9-NEXT:    v_add3_u32 v21, v23, v22, v21
 ; GFX9-NEXT:    v_mul_lo_u32 v22, v0, v12
 ; GFX9-NEXT:    v_mul_hi_u32 v23, v3, v8
 ; GFX9-NEXT:    v_mul_lo_u32 v7, v7, v8
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
@@ -4205,8 +4205,8 @@
 ; GFX10-NEXT:    v_ashrrev_i32_e32 v6, 31, v11
 ; GFX10-NEXT:    v_cmp_lt_i64_e64 s4, v[10:11], v[0:1]
 ; GFX10-NEXT:    v_add_co_u32_e64 v0, s5, v6, 0
-; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s5, 0x80000000, v6, s5
 ; GFX10-NEXT:    s_xor_b32 vcc_lo, vcc_lo, s4
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s5, 0x80000000, v6, s5
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, v10, v0, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v1, v11, v1, vcc_lo
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
@@ -4383,8 +4383,8 @@
 ; GFX10-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
 ; GFX10-NEXT:    v_cmp_gt_i64_e64 s0, s[0:1], v[2:3]
 ; GFX10-NEXT:    v_add_co_u32_e64 v0, s1, v4, 0
-; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s1, 0x80000000, v4, s1
 ; GFX10-NEXT:    s_xor_b32 vcc_lo, vcc_lo, s0
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s1, 0x80000000, v4, s1
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo
 ; GFX10-NEXT:    ; return to shader part epilog
@@ -4450,8 +4450,8 @@
 ; GFX10-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
 ; GFX10-NEXT:    v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[0:1]
 ; GFX10-NEXT:    v_add_co_u32_e64 v0, s0, v4, 0
-; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s0, 0x80000000, v4, s0
 ; GFX10-NEXT:    s_xor_b32 vcc_lo, s1, vcc_lo
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s0, 0x80000000, v4, s0
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo
 ; GFX10-NEXT:    ; return to shader part epilog
@@ -4552,15 +4552,15 @@
 ; GFX10-NEXT:    v_cmp_gt_i64_e64 s6, 0, v[6:7]
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v9, vcc_lo, v15, v5, vcc_lo
 ; GFX10-NEXT:    v_add_co_u32_e64 v19, vcc_lo, v17, v6
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v20, vcc_lo, v18, v7, vcc_lo
 ; GFX10-NEXT:    v_ashrrev_i32_e32 v12, 31, v9
+; GFX10-NEXT:    v_add_co_ci_u32_e32 v20, vcc_lo, v18, v7, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_i64_e32 vcc_lo, v[8:9], v[14:15]
-; GFX10-NEXT:    v_ashrrev_i32_e32 v0, 31, v20
 ; GFX10-NEXT:    v_add_co_u32_e64 v1, s5, v12, 0
+; GFX10-NEXT:    v_ashrrev_i32_e32 v0, 31, v20
+; GFX10-NEXT:    s_xor_b32 vcc_lo, s4, vcc_lo
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v4, s5, 0x80000000, v12, s5
-; GFX10-NEXT:    v_cmp_lt_i64_e64 s5, v[19:20], v[17:18]
 ; GFX10-NEXT:    v_add_co_u32_e64 v2, s7, v0, 0
-; GFX10-NEXT:    s_xor_b32 vcc_lo, s4, vcc_lo
+; GFX10-NEXT:    v_cmp_lt_i64_e64 s5, v[19:20], v[17:18]
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v3, s7, 0x80000000, v0, s7
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, v8, v1, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v1, v9, v4, vcc_lo
@@ -5325,52 +5325,52 @@
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v6, vcc_lo, s2, v2, vcc_lo
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
 ; GFX10-NEXT:    v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[4:5]
-; GFX10-NEXT:    s_movk_i32 s0, 0x7f
-; GFX10-NEXT:    s_sub_i32 s1, 64, s0
-; GFX10-NEXT:    v_lshrrev_b64 v[15:16], s0, v[4:5]
+; GFX10-NEXT:    s_movk_i32 s1, 0x7f
+; GFX10-NEXT:    s_sub_i32 s0, 64, s1
+; GFX10-NEXT:    v_lshrrev_b64 v[15:16], s1, v[4:5]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[6:7]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[6:7]
 ; GFX10-NEXT:    v_cndmask_b32_e32 v10, v9, v8, vcc_lo
 ; GFX10-NEXT:    v_cmp_gt_u64_e32 vcc_lo, 0, v[0:1]
-; GFX10-NEXT:    v_lshlrev_b64 v[8:9], s1, v[6:7]
-; GFX10-NEXT:    s_sub_i32 s1, s0, 64
-; GFX10-NEXT:    s_cmp_lt_u32 s0, 64
-; GFX10-NEXT:    v_ashrrev_i64 v[0:1], s0, v[6:7]
+; GFX10-NEXT:    v_lshlrev_b64 v[8:9], s0, v[6:7]
+; GFX10-NEXT:    s_sub_i32 s0, s1, 64
+; GFX10-NEXT:    s_cmp_lt_u32 s1, 64
 ; GFX10-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_gt_i64_e32 vcc_lo, 0, v[2:3]
-; GFX10-NEXT:    v_or_b32_e32 v8, v15, v8
-; GFX10-NEXT:    v_or_b32_e32 v9, v16, v9
-; GFX10-NEXT:    v_ashrrev_i32_e32 v15, 31, v7
+; GFX10-NEXT:    v_or_b32_e32 v0, v15, v8
+; GFX10-NEXT:    v_or_b32_e32 v1, v16, v9
 ; GFX10-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
-; GFX10-NEXT:    v_ashrrev_i64 v[2:3], s1, v[6:7]
+; GFX10-NEXT:    v_ashrrev_i64 v[2:3], s0, v[6:7]
 ; GFX10-NEXT:    v_cndmask_b32_e32 v11, v12, v11, vcc_lo
 ; GFX10-NEXT:    s_cselect_b32 vcc_lo, 1, 0
-; GFX10-NEXT:    s_cmp_eq_u32 s0, 0
-; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v9, vcc_lo
-; GFX10-NEXT:    s_cselect_b32 s1, 1, 0
-; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v8, vcc_lo
-; GFX10-NEXT:    s_and_b32 s0, 1, s1
+; GFX10-NEXT:    s_cmp_eq_u32 s1, 0
+; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v0, vcc_lo
+; GFX10-NEXT:    s_cselect_b32 s0, 1, 0
+; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v1, vcc_lo
+; GFX10-NEXT:    s_and_b32 s0, 1, s0
+; GFX10-NEXT:    v_ashrrev_i64 v[0:1], s1, v[6:7]
+; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, s0
 ; GFX10-NEXT:    s_and_b32 s1, 1, vcc_lo
-; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s0
-; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, s1
-; GFX10-NEXT:    v_xor_b32_e32 v9, v11, v10
-; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, v15, v0, s0
-; GFX10-NEXT:    v_and_b32_e32 v8, 1, v9
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, v15, v1, s0
-; GFX10-NEXT:    v_add_co_u32_e64 v2, vcc_lo, v2, 0
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
-; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, v8
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v8, vcc_lo, 0, v0, vcc_lo
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v9, vcc_lo, 0x80000000, v1, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, v4, v2, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, v5, v3, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v2, v6, v8, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v3, v7, v9, s0
+; GFX10-NEXT:    v_xor_b32_e32 v8, v11, v10
+; GFX10-NEXT:    v_ashrrev_i32_e32 v11, 31, v7
+; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s1
+; GFX10-NEXT:    v_cndmask_b32_e64 v2, v2, v4, s0
+; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, v5, s0
+; GFX10-NEXT:    v_and_b32_e32 v8, 1, v8
+; GFX10-NEXT:    v_cndmask_b32_e32 v0, v11, v0, vcc_lo
+; GFX10-NEXT:    v_add_co_u32_e64 v2, s0, v2, 0
+; GFX10-NEXT:    v_cndmask_b32_e32 v1, v11, v1, vcc_lo
+; GFX10-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v8
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v3, s0, 0, v3, s0
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v8, s0, 0, v0, s0
+; GFX10-NEXT:    v_cndmask_b32_e32 v0, v4, v2, vcc_lo
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v9, s0, 0x80000000, v1, s0
+; GFX10-NEXT:    v_cndmask_b32_e32 v1, v5, v3, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e32 v2, v6, v8, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e32 v3, v7, v9, vcc_lo
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = call i128 @llvm.sadd.sat.i128(i128 %lhs, i128 %rhs)
   %cast = bitcast i128 %result to <4 x float>
@@ -5569,64 +5569,60 @@
 ;
 ; GFX10-LABEL: saddsat_i128_vs:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_mov_b32_e32 v5, v0
-; GFX10-NEXT:    v_mov_b32_e32 v6, v1
-; GFX10-NEXT:    v_mov_b32_e32 v9, v2
-; GFX10-NEXT:    v_mov_b32_e32 v10, v3
-; GFX10-NEXT:    s_cmp_eq_u64 s[2:3], 0
-; GFX10-NEXT:    v_add_co_u32_e64 v15, vcc_lo, v5, s0
+; GFX10-NEXT:    v_add_co_u32_e64 v14, vcc_lo, v0, s0
 ; GFX10-NEXT:    v_cmp_lt_u64_e64 s0, s[0:1], 0
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v16, vcc_lo, s1, v6, vcc_lo
+; GFX10-NEXT:    s_cmp_eq_u64 s[2:3], 0
 ; GFX10-NEXT:    s_cselect_b32 s4, 1, 0
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v19, vcc_lo, s2, v9, vcc_lo
-; GFX10-NEXT:    s_and_b32 s1, 1, s4
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v20, vcc_lo, s3, v10, vcc_lo
-; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[15:16], v[5:6]
+; GFX10-NEXT:    v_add_co_ci_u32_e32 v15, vcc_lo, s1, v1, vcc_lo
+; GFX10-NEXT:    s_movk_i32 s1, 0x7f
 ; GFX10-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s0
 ; GFX10-NEXT:    v_cmp_lt_i64_e64 s0, s[2:3], 0
-; GFX10-NEXT:    v_ashrrev_i32_e32 v7, 31, v20
+; GFX10-NEXT:    v_add_co_ci_u32_e32 v4, vcc_lo, s2, v2, vcc_lo
+; GFX10-NEXT:    s_sub_i32 s2, 64, s1
+; GFX10-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s0
+; GFX10-NEXT:    v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
+; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[14:15], v[0:1]
+; GFX10-NEXT:    s_and_b32 s0, 1, s4
 ; GFX10-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX10-NEXT:    v_cmp_lt_i64_e32 vcc_lo, v[19:20], v[9:10]
+; GFX10-NEXT:    v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[2:3]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX10-NEXT:    v_cmp_eq_u64_e32 vcc_lo, v[19:20], v[9:10]
-; GFX10-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s0
-; GFX10-NEXT:    s_movk_i32 s0, 0x7f
-; GFX10-NEXT:    s_sub_i32 s2, 64, s0
+; GFX10-NEXT:    v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[2:3]
+; GFX10-NEXT:    v_lshlrev_b64 v[2:3], s2, v[4:5]
 ; GFX10-NEXT:    v_cndmask_b32_e32 v10, v1, v0, vcc_lo
-; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s1
-; GFX10-NEXT:    v_lshrrev_b64 v[0:1], s0, v[15:16]
-; GFX10-NEXT:    v_lshlrev_b64 v[2:3], s2, v[19:20]
-; GFX10-NEXT:    s_sub_i32 s1, s0, 64
-; GFX10-NEXT:    s_cmp_lt_u32 s0, 64
+; GFX10-NEXT:    v_lshrrev_b64 v[0:1], s1, v[14:15]
+; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s0
+; GFX10-NEXT:    s_sub_i32 s0, s1, 64
+; GFX10-NEXT:    s_cmp_lt_u32 s1, 64
 ; GFX10-NEXT:    v_cndmask_b32_e32 v11, v9, v8, vcc_lo
 ; GFX10-NEXT:    s_cselect_b32 vcc_lo, 1, 0
-; GFX10-NEXT:    v_ashrrev_i64 v[8:9], s1, v[19:20]
-; GFX10-NEXT:    s_cmp_eq_u32 s0, 0
-; GFX10-NEXT:    v_or_b32_e32 v2, v0, v2
-; GFX10-NEXT:    v_or_b32_e32 v3, v1, v3
-; GFX10-NEXT:    s_cselect_b32 s1, 1, 0
-; GFX10-NEXT:    v_ashrrev_i64 v[0:1], s0, v[19:20]
-; GFX10-NEXT:    s_and_b32 s0, 1, s1
-; GFX10-NEXT:    v_cndmask_b32_e32 v2, v8, v2, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e32 v3, v9, v3, vcc_lo
+; GFX10-NEXT:    v_ashrrev_i64 v[7:8], s0, v[4:5]
+; GFX10-NEXT:    s_cmp_eq_u32 s1, 0
+; GFX10-NEXT:    v_or_b32_e32 v0, v0, v2
+; GFX10-NEXT:    s_cselect_b32 s0, 1, 0
+; GFX10-NEXT:    v_or_b32_e32 v1, v1, v3
+; GFX10-NEXT:    s_and_b32 s0, 1, s0
+; GFX10-NEXT:    v_xor_b32_e32 v2, v11, v10
+; GFX10-NEXT:    v_cndmask_b32_e32 v3, v7, v0, vcc_lo
+; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, s0
+; GFX10-NEXT:    v_cndmask_b32_e32 v8, v8, v1, vcc_lo
+; GFX10-NEXT:    v_ashrrev_i64 v[0:1], s1, v[4:5]
 ; GFX10-NEXT:    s_and_b32 s1, 1, vcc_lo
-; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s0
-; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, s1
-; GFX10-NEXT:    v_xor_b32_e32 v9, v11, v10
-; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v15, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v16, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, v7, v0, s0
-; GFX10-NEXT:    v_and_b32_e32 v8, 1, v9
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, v7, v1, s0
-; GFX10-NEXT:    v_add_co_u32_e64 v2, vcc_lo, v2, 0
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
-; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, v8
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v8, vcc_lo, 0, v0, vcc_lo
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v9, vcc_lo, 0x80000000, v1, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, v15, v2, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, v16, v3, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v2, v19, v8, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v3, v20, v9, s0
+; GFX10-NEXT:    v_ashrrev_i32_e32 v7, 31, v5
+; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, v14, s0
+; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s1
+; GFX10-NEXT:    v_cndmask_b32_e64 v8, v8, v15, s0
+; GFX10-NEXT:    v_and_b32_e32 v2, 1, v2
+; GFX10-NEXT:    v_add_co_u32_e64 v3, s0, v3, 0
+; GFX10-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e32 v1, v7, v1, vcc_lo
+; GFX10-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v2
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v8, s0, 0, v8, s0
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v2, s0, 0, v0, s0
+; GFX10-NEXT:    v_cndmask_b32_e32 v0, v14, v3, vcc_lo
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v7, s0, 0x80000000, v1, s0
+; GFX10-NEXT:    v_cndmask_b32_e32 v1, v15, v8, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e32 v3, v5, v7, vcc_lo
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = call i128 @llvm.sadd.sat.i128(i128 %lhs, i128 %rhs)
   %cast = bitcast i128 %result to <4 x float>
@@ -5963,109 +5959,109 @@
 ; GFX10-NEXT:    v_mov_b32_e32 v23, v1
 ; GFX10-NEXT:    v_mov_b32_e32 v20, v2
 ; GFX10-NEXT:    v_mov_b32_e32 v21, v3
-; GFX10-NEXT:    s_movk_i32 s5, 0x7f
+; GFX10-NEXT:    s_movk_i32 s6, 0x7f
 ; GFX10-NEXT:    v_add_co_u32_e64 v16, vcc_lo, v22, v8
-; GFX10-NEXT:    s_sub_i32 s6, 64, s5
+; GFX10-NEXT:    s_sub_i32 s5, 64, s6
+; GFX10-NEXT:    s_sub_i32 s7, s6, 64
+; GFX10-NEXT:    s_cmp_lt_u32 s6, 64
+; GFX10-NEXT:    v_mov_b32_e32 v26, v4
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v17, vcc_lo, v23, v9, vcc_lo
-; GFX10-NEXT:    s_sub_i32 s7, s5, 64
+; GFX10-NEXT:    v_mov_b32_e32 v27, v5
+; GFX10-NEXT:    v_mov_b32_e32 v4, v6
+; GFX10-NEXT:    v_mov_b32_e32 v5, v7
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v18, vcc_lo, v20, v10, vcc_lo
-; GFX10-NEXT:    s_cmp_lt_u32 s5, 64
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v19, vcc_lo, v21, v11, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[16:17], v[22:23]
-; GFX10-NEXT:    v_mov_b32_e32 v26, v4
-; GFX10-NEXT:    v_mov_b32_e32 v27, v5
-; GFX10-NEXT:    v_mov_b32_e32 v24, v6
-; GFX10-NEXT:    v_lshlrev_b64 v[2:3], s6, v[18:19]
-; GFX10-NEXT:    v_mov_b32_e32 v25, v7
+; GFX10-NEXT:    v_lshlrev_b64 v[2:3], s5, v[18:19]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_i64_e32 vcc_lo, v[18:19], v[20:21]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_eq_u64_e32 vcc_lo, v[18:19], v[20:21]
 ; GFX10-NEXT:    v_cndmask_b32_e32 v20, v1, v0, vcc_lo
 ; GFX10-NEXT:    v_cmp_gt_u64_e32 vcc_lo, 0, v[8:9]
-; GFX10-NEXT:    v_lshrrev_b64 v[0:1], s5, v[16:17]
+; GFX10-NEXT:    v_lshrrev_b64 v[0:1], s6, v[16:17]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_gt_i64_e32 vcc_lo, 0, v[10:11]
 ; GFX10-NEXT:    v_or_b32_e32 v2, v0, v2
 ; GFX10-NEXT:    v_or_b32_e32 v3, v1, v3
-; GFX10-NEXT:    v_ashrrev_i64 v[0:1], s5, v[18:19]
+; GFX10-NEXT:    v_ashrrev_i64 v[0:1], s6, v[18:19]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11]
 ; GFX10-NEXT:    v_ashrrev_i32_e32 v11, 31, v19
 ; GFX10-NEXT:    v_cndmask_b32_e32 v10, v9, v8, vcc_lo
 ; GFX10-NEXT:    s_cselect_b32 vcc_lo, 1, 0
 ; GFX10-NEXT:    v_ashrrev_i64 v[8:9], s7, v[18:19]
-; GFX10-NEXT:    s_cmp_eq_u32 s5, 0
+; GFX10-NEXT:    s_cmp_eq_u32 s6, 0
 ; GFX10-NEXT:    s_cselect_b32 s4, 1, 0
 ; GFX10-NEXT:    s_and_b32 s8, 1, vcc_lo
 ; GFX10-NEXT:    s_and_b32 s4, 1, s4
-; GFX10-NEXT:    v_cndmask_b32_e32 v3, v9, v3, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v2, v8, v2, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e32 v3, v9, v3, vcc_lo
 ; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s4
 ; GFX10-NEXT:    v_cmp_ne_u32_e64 s4, 0, s8
-; GFX10-NEXT:    v_xor_b32_e32 v9, v10, v20
-; GFX10-NEXT:    s_cmp_lt_u32 s5, 64
+; GFX10-NEXT:    v_xor_b32_e32 v10, v10, v20
+; GFX10-NEXT:    s_cmp_lt_u32 s6, 64
 ; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v16, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v17, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e64 v0, v11, v0, s4
 ; GFX10-NEXT:    v_cndmask_b32_e64 v1, v11, v1, s4
-; GFX10-NEXT:    v_and_b32_e32 v8, 1, v9
-; GFX10-NEXT:    v_add_co_u32_e64 v2, vcc_lo, v2, 0
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v20, vcc_lo, 0, v0, vcc_lo
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v21, vcc_lo, 0x80000000, v1, vcc_lo
-; GFX10-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v8
 ; GFX10-NEXT:    v_add_co_u32_e64 v8, s4, v26, v12
+; GFX10-NEXT:    v_add_co_u32_e64 v2, vcc_lo, v2, 0
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v9, s4, v27, v13, s4
-; GFX10-NEXT:    v_add_co_ci_u32_e64 v10, s4, v24, v14, s4
-; GFX10-NEXT:    v_cndmask_b32_e32 v0, v16, v2, vcc_lo
-; GFX10-NEXT:    v_add_co_ci_u32_e64 v11, s4, v25, v15, s4
+; GFX10-NEXT:    v_add_co_ci_u32_e32 v20, vcc_lo, 0, v3, vcc_lo
+; GFX10-NEXT:    v_add_co_ci_u32_e32 v21, vcc_lo, 0, v0, vcc_lo
+; GFX10-NEXT:    v_and_b32_e32 v0, 1, v10
+; GFX10-NEXT:    v_add_co_ci_u32_e32 v22, vcc_lo, 0x80000000, v1, vcc_lo
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v10, vcc_lo, v4, v14, s4
 ; GFX10-NEXT:    v_cmp_lt_u64_e64 s4, v[8:9], v[26:27]
-; GFX10-NEXT:    v_cndmask_b32_e32 v1, v17, v3, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e32 v2, v18, v20, vcc_lo
-; GFX10-NEXT:    v_lshrrev_b64 v[3:4], s5, v[8:9]
-; GFX10-NEXT:    v_cndmask_b32_e64 v5, 0, 1, s4
-; GFX10-NEXT:    v_cmp_lt_i64_e64 s4, v[10:11], v[24:25]
-; GFX10-NEXT:    v_cndmask_b32_e64 v16, 0, 1, s4
+; GFX10-NEXT:    v_add_co_ci_u32_e32 v11, vcc_lo, v5, v15, vcc_lo
+; GFX10-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX10-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s4
+; GFX10-NEXT:    v_cmp_lt_i64_e64 s4, v[10:11], v[4:5]
+; GFX10-NEXT:    v_cndmask_b32_e32 v0, v16, v2, vcc_lo
+; GFX10-NEXT:    v_ashrrev_i64 v[23:24], s7, v[10:11]
+; GFX10-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s4
 ; GFX10-NEXT:    v_cmp_gt_u64_e64 s4, 0, v[12:13]
-; GFX10-NEXT:    v_lshlrev_b64 v[12:13], s6, v[10:11]
-; GFX10-NEXT:    v_cndmask_b32_e64 v17, 0, 1, s4
+; GFX10-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s4
 ; GFX10-NEXT:    v_cmp_gt_i64_e64 s4, 0, v[14:15]
-; GFX10-NEXT:    v_or_b32_e32 v12, v3, v12
-; GFX10-NEXT:    v_or_b32_e32 v13, v4, v13
-; GFX10-NEXT:    v_ashrrev_i64 v[3:4], s5, v[10:11]
-; GFX10-NEXT:    v_cndmask_b32_e64 v18, 0, 1, s4
-; GFX10-NEXT:    v_cmp_eq_u64_e64 s4, v[10:11], v[24:25]
-; GFX10-NEXT:    v_cndmask_b32_e64 v7, v16, v5, s4
+; GFX10-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s4
+; GFX10-NEXT:    v_cmp_eq_u64_e64 s4, v[10:11], v[4:5]
+; GFX10-NEXT:    v_lshlrev_b64 v[4:5], s5, v[10:11]
+; GFX10-NEXT:    v_cndmask_b32_e64 v16, v2, v1, s4
 ; GFX10-NEXT:    v_cmp_eq_u64_e64 s4, 0, v[14:15]
-; GFX10-NEXT:    v_ashrrev_i64 v[5:6], s7, v[10:11]
-; GFX10-NEXT:    v_cndmask_b32_e64 v14, v18, v17, s4
+; GFX10-NEXT:    v_lshrrev_b64 v[2:3], s6, v[8:9]
+; GFX10-NEXT:    v_cndmask_b32_e32 v1, v17, v20, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e64 v15, v13, v12, s4
 ; GFX10-NEXT:    s_cselect_b32 s4, 1, 0
-; GFX10-NEXT:    s_cmp_eq_u32 s5, 0
-; GFX10-NEXT:    v_cndmask_b32_e64 v5, v5, v12, s4
-; GFX10-NEXT:    s_cselect_b32 s6, 1, 0
-; GFX10-NEXT:    v_cndmask_b32_e64 v6, v6, v13, s4
-; GFX10-NEXT:    s_and_b32 s5, 1, s6
-; GFX10-NEXT:    s_and_b32 s6, 1, s4
-; GFX10-NEXT:    v_cmp_ne_u32_e64 s4, 0, s5
-; GFX10-NEXT:    v_xor_b32_e32 v7, v14, v7
-; GFX10-NEXT:    v_ashrrev_i32_e32 v18, 31, v11
-; GFX10-NEXT:    v_cmp_ne_u32_e64 s5, 0, s6
-; GFX10-NEXT:    v_cndmask_b32_e64 v5, v5, v8, s4
-; GFX10-NEXT:    v_cndmask_b32_e64 v6, v6, v9, s4
-; GFX10-NEXT:    v_and_b32_e32 v7, 1, v7
-; GFX10-NEXT:    v_cndmask_b32_e64 v3, v18, v3, s5
-; GFX10-NEXT:    v_cndmask_b32_e64 v4, v18, v4, s5
-; GFX10-NEXT:    v_add_co_u32_e64 v5, s4, v5, 0
-; GFX10-NEXT:    v_add_co_ci_u32_e64 v6, s4, 0, v6, s4
-; GFX10-NEXT:    v_cmp_ne_u32_e64 s5, 0, v7
-; GFX10-NEXT:    v_add_co_ci_u32_e64 v7, s4, 0, v3, s4
-; GFX10-NEXT:    v_cndmask_b32_e32 v3, v19, v21, vcc_lo
-; GFX10-NEXT:    v_add_co_ci_u32_e64 v12, s4, 0x80000000, v4, s4
-; GFX10-NEXT:    v_cndmask_b32_e64 v4, v8, v5, s5
-; GFX10-NEXT:    v_cndmask_b32_e64 v5, v9, v6, s5
-; GFX10-NEXT:    v_cndmask_b32_e64 v6, v10, v7, s5
-; GFX10-NEXT:    v_cndmask_b32_e64 v7, v11, v12, s5
+; GFX10-NEXT:    s_cmp_eq_u32 s6, 0
+; GFX10-NEXT:    v_or_b32_e32 v2, v2, v4
+; GFX10-NEXT:    s_cselect_b32 s5, 1, 0
+; GFX10-NEXT:    v_or_b32_e32 v3, v3, v5
+; GFX10-NEXT:    s_and_b32 s5, 1, s5
+; GFX10-NEXT:    v_ashrrev_i32_e32 v13, 31, v11
+; GFX10-NEXT:    v_cndmask_b32_e64 v5, v23, v2, s4
+; GFX10-NEXT:    v_cmp_ne_u32_e64 s5, 0, s5
+; GFX10-NEXT:    v_cndmask_b32_e64 v6, v24, v3, s4
+; GFX10-NEXT:    s_and_b32 s4, 1, s4
+; GFX10-NEXT:    v_ashrrev_i64 v[2:3], s6, v[10:11]
+; GFX10-NEXT:    v_cmp_ne_u32_e64 s4, 0, s4
+; GFX10-NEXT:    v_cndmask_b32_e64 v5, v5, v8, s5
+; GFX10-NEXT:    v_cndmask_b32_e64 v6, v6, v9, s5
+; GFX10-NEXT:    v_xor_b32_e32 v4, v15, v16
+; GFX10-NEXT:    v_cndmask_b32_e64 v12, v13, v2, s4
+; GFX10-NEXT:    v_add_co_u32_e64 v5, s5, v5, 0
+; GFX10-NEXT:    v_cndmask_b32_e64 v3, v13, v3, s4
+; GFX10-NEXT:    v_and_b32_e32 v4, 1, v4
+; GFX10-NEXT:    v_cndmask_b32_e32 v2, v18, v21, vcc_lo
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v6, s5, 0, v6, s5
+; GFX10-NEXT:    v_cmp_ne_u32_e64 s4, 0, v4
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v7, s5, 0, v12, s5
+; GFX10-NEXT:    v_cndmask_b32_e64 v4, v8, v5, s4
+; GFX10-NEXT:    v_cndmask_b32_e64 v5, v9, v6, s4
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v12, s5, 0x80000000, v3, s5
+; GFX10-NEXT:    v_cndmask_b32_e64 v6, v10, v7, s4
+; GFX10-NEXT:    v_cndmask_b32_e32 v3, v19, v22, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e64 v7, v11, v12, s4
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = call <2 x i128> @llvm.sadd.sat.v2i128(<2 x i128> %lhs, <2 x i128> %rhs)
   ret <2 x i128> %result
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
@@ -23,137 +23,137 @@
 ; CHECK-NEXT:    v_xor_b32_e32 v3, v3, v4
 ; CHECK-NEXT:    v_cvt_f32_u32_e32 v6, v5
 ; CHECK-NEXT:    v_cvt_f32_u32_e32 v7, v3
-; CHECK-NEXT:    v_ashrrev_i32_e32 v8, 31, v1
+; CHECK-NEXT:    v_sub_i32_e32 v8, vcc, 0, v5
+; CHECK-NEXT:    v_subb_u32_e32 v9, vcc, 0, v3, vcc
+; CHECK-NEXT:    v_ashrrev_i32_e32 v14, 31, v1
 ; CHECK-NEXT:    v_mac_f32_e32 v6, 0x4f800000, v7
 ; CHECK-NEXT:    v_rcp_iflag_f32_e32 v6, v6
-; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v0, v8
-; CHECK-NEXT:    v_addc_u32_e32 v1, vcc, v1, v8, vcc
-; CHECK-NEXT:    v_sub_i32_e32 v10, vcc, 0, v5
 ; CHECK-NEXT:    v_mul_f32_e32 v6, 0x5f7ffffc, v6
-; CHECK-NEXT:    v_mul_f32_e32 v9, 0x2f800000, v6
-; CHECK-NEXT:    v_trunc_f32_e32 v9, v9
-; CHECK-NEXT:    v_mac_f32_e32 v6, 0xcf800000, v9
+; CHECK-NEXT:    v_mul_f32_e32 v7, 0x2f800000, v6
+; CHECK-NEXT:    v_trunc_f32_e32 v7, v7
+; CHECK-NEXT:    v_mac_f32_e32 v6, 0xcf800000, v7
 ; CHECK-NEXT:    v_cvt_u32_f32_e32 v6, v6
-; CHECK-NEXT:    v_cvt_u32_f32_e32 v9, v9
-; CHECK-NEXT:    v_subb_u32_e32 v11, vcc, 0, v3, vcc
-; CHECK-NEXT:    v_xor_b32_e32 v7, v7, v8
-; CHECK-NEXT:    v_mul_lo_u32 v12, v11, v6
-; CHECK-NEXT:    v_mul_lo_u32 v13, v10, v9
-; CHECK-NEXT:    v_mul_hi_u32 v15, v10, v6
-; CHECK-NEXT:    v_mul_lo_u32 v14, v10, v6
-; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v8
-; CHECK-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
-; CHECK-NEXT:    v_add_i32_e32 v12, vcc, v12, v15
-; CHECK-NEXT:    v_mul_lo_u32 v13, v9, v14
-; CHECK-NEXT:    v_mul_lo_u32 v15, v6, v12
-; CHECK-NEXT:    v_mul_hi_u32 v16, v6, v14
-; CHECK-NEXT:    v_mul_hi_u32 v14, v9, v14
-; CHECK-NEXT:    v_add_i32_e32 v13, vcc, v13, v15
-; CHECK-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v13, vcc, v13, v16
+; CHECK-NEXT:    v_cvt_u32_f32_e32 v7, v7
+; CHECK-NEXT:    v_mul_lo_u32 v11, v9, v6
+; CHECK-NEXT:    v_mul_lo_u32 v10, v8, v7
+; CHECK-NEXT:    v_mul_hi_u32 v13, v8, v6
+; CHECK-NEXT:    v_mul_lo_u32 v12, v8, v6
+; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v10, v13
+; CHECK-NEXT:    v_mul_lo_u32 v11, v7, v12
+; CHECK-NEXT:    v_mul_lo_u32 v13, v6, v10
+; CHECK-NEXT:    v_mul_hi_u32 v16, v6, v12
+; CHECK-NEXT:    v_add_i32_e32 v15, vcc, v0, v14
+; CHECK-NEXT:    v_addc_u32_e32 v1, vcc, v1, v14, vcc
+; CHECK-NEXT:    v_add_i32_e32 v11, vcc, v11, v13
+; CHECK-NEXT:    v_mul_lo_u32 v17, v7, v10
+; CHECK-NEXT:    v_mul_hi_u32 v12, v7, v12
+; CHECK-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v11, vcc, v11, v16
+; CHECK-NEXT:    v_mul_hi_u32 v16, v6, v10
+; CHECK-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v11, vcc, v13, v11
+; CHECK-NEXT:    v_add_i32_e32 v12, vcc, v17, v12
 ; CHECK-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v16, v9, v12
-; CHECK-NEXT:    v_add_i32_e32 v13, vcc, v15, v13
-; CHECK-NEXT:    v_mul_hi_u32 v15, v6, v12
-; CHECK-NEXT:    v_mul_hi_u32 v12, v9, v12
-; CHECK-NEXT:    v_add_i32_e32 v14, vcc, v16, v14
+; CHECK-NEXT:    v_add_i32_e32 v12, vcc, v12, v16
 ; CHECK-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v14, vcc, v14, v15
-; CHECK-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v15, vcc, v16, v15
-; CHECK-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
-; CHECK-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
-; CHECK-NEXT:    v_add_i32_e32 v12, vcc, v12, v14
-; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v13
-; CHECK-NEXT:    v_addc_u32_e64 v13, s[4:5], v9, v12, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v11, v11, v6
-; CHECK-NEXT:    v_mul_lo_u32 v14, v10, v13
-; CHECK-NEXT:    v_mul_lo_u32 v15, v10, v6
-; CHECK-NEXT:    v_mul_hi_u32 v10, v10, v6
+; CHECK-NEXT:    v_add_i32_e32 v13, vcc, v13, v16
+; CHECK-NEXT:    v_mul_hi_u32 v10, v7, v10
+; CHECK-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
+; CHECK-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
+; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
+; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v11
+; CHECK-NEXT:    v_addc_u32_e64 v11, s[4:5], v7, v10, vcc
+; CHECK-NEXT:    v_mul_lo_u32 v9, v9, v6
+; CHECK-NEXT:    v_mul_lo_u32 v12, v8, v11
+; CHECK-NEXT:    v_mul_hi_u32 v13, v8, v6
+; CHECK-NEXT:    v_mul_lo_u32 v8, v8, v6
+; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v10
 ; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v12
-; CHECK-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v14
-; CHECK-NEXT:    v_mul_hi_u32 v12, v6, v15
-; CHECK-NEXT:    v_add_i32_e64 v10, s[4:5], v11, v10
-; CHECK-NEXT:    v_mul_lo_u32 v11, v13, v15
-; CHECK-NEXT:    v_mul_lo_u32 v14, v6, v10
-; CHECK-NEXT:    v_mul_hi_u32 v15, v13, v15
-; CHECK-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v14
-; CHECK-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
-; CHECK-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; CHECK-NEXT:    v_mul_lo_u32 v12, v13, v10
-; CHECK-NEXT:    v_add_i32_e64 v11, s[4:5], v14, v11
-; CHECK-NEXT:    v_mul_hi_u32 v14, v6, v10
-; CHECK-NEXT:    v_mul_hi_u32 v10, v13, v10
-; CHECK-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v15
-; CHECK-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v14
-; CHECK-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v14, s[4:5], v15, v14
-; CHECK-NEXT:    v_add_i32_e64 v11, s[4:5], v12, v11
+; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v13
+; CHECK-NEXT:    v_mul_lo_u32 v12, v11, v8
+; CHECK-NEXT:    v_mul_lo_u32 v13, v6, v9
+; CHECK-NEXT:    v_mul_hi_u32 v10, v6, v8
+; CHECK-NEXT:    v_mul_lo_u32 v16, v11, v9
+; CHECK-NEXT:    v_mul_hi_u32 v8, v11, v8
+; CHECK-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v13
+; CHECK-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v10, s[4:5], v12, v10
+; CHECK-NEXT:    v_mul_hi_u32 v12, v6, v9
+; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v10, s[4:5], v13, v10
+; CHECK-NEXT:    v_add_i32_e64 v8, s[4:5], v16, v8
+; CHECK-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v12
 ; CHECK-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v12, s[4:5], v14, v12
-; CHECK-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v12
-; CHECK-NEXT:    v_addc_u32_e32 v9, vcc, v9, v10, vcc
-; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v11
-; CHECK-NEXT:    v_addc_u32_e32 v9, vcc, 0, v9, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v10, v1, v6
-; CHECK-NEXT:    v_mul_lo_u32 v11, v7, v9
-; CHECK-NEXT:    v_mul_hi_u32 v12, v7, v6
+; CHECK-NEXT:    v_add_i32_e64 v12, s[4:5], v13, v12
+; CHECK-NEXT:    v_mul_hi_u32 v9, v11, v9
+; CHECK-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v10
+; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v10, s[4:5], v12, v10
+; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v10
+; CHECK-NEXT:    v_addc_u32_e32 v7, vcc, v7, v9, vcc
+; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; CHECK-NEXT:    v_xor_b32_e32 v15, v15, v14
+; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v14
+; CHECK-NEXT:    v_addc_u32_e32 v7, vcc, 0, v7, vcc
+; CHECK-NEXT:    v_mul_lo_u32 v8, v1, v6
+; CHECK-NEXT:    v_mul_lo_u32 v9, v15, v7
+; CHECK-NEXT:    v_mul_hi_u32 v10, v15, v6
+; CHECK-NEXT:    v_mul_lo_u32 v11, v1, v7
 ; CHECK-NEXT:    v_mul_hi_u32 v6, v1, v6
-; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
-; CHECK-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
-; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v12, v1, v9
-; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; CHECK-NEXT:    v_mul_hi_u32 v11, v7, v9
-; CHECK-NEXT:    v_mul_hi_u32 v9, v1, v9
-; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v12, v6
-; CHECK-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v11
-; CHECK-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
+; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
+; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; CHECK-NEXT:    v_mul_hi_u32 v10, v15, v7
+; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v11, v6
+; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v10
 ; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
 ; CHECK-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; CHECK-NEXT:    v_mul_lo_u32 v10, v3, v6
-; CHECK-NEXT:    v_mul_lo_u32 v11, v5, v9
-; CHECK-NEXT:    v_mul_hi_u32 v13, v5, v6
-; CHECK-NEXT:    v_mul_lo_u32 v12, v5, v6
-; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
-; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v10, v13
-; CHECK-NEXT:    v_sub_i32_e32 v7, vcc, v7, v12
-; CHECK-NEXT:    v_subb_u32_e64 v11, s[4:5], v1, v10, vcc
-; CHECK-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v10
-; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v11, v3
+; CHECK-NEXT:    v_mul_hi_u32 v7, v1, v7
+; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; CHECK-NEXT:    v_mul_lo_u32 v8, v3, v6
+; CHECK-NEXT:    v_mul_lo_u32 v9, v5, v7
+; CHECK-NEXT:    v_mul_hi_u32 v10, v5, v6
+; CHECK-NEXT:    v_mul_lo_u32 v11, v5, v6
+; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
+; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; CHECK-NEXT:    v_sub_i32_e32 v9, vcc, v15, v11
+; CHECK-NEXT:    v_subb_u32_e64 v10, s[4:5], v1, v8, vcc
+; CHECK-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v8
+; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v10, v3
 ; CHECK-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
-; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
-; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v5
-; CHECK-NEXT:    v_sub_i32_e32 v7, vcc, v7, v5
+; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
+; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v9, v5
+; CHECK-NEXT:    v_sub_i32_e32 v9, vcc, v9, v5
 ; CHECK-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CHECK-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[4:5]
-; CHECK-NEXT:    v_cmp_eq_u32_e64 s[4:5], v11, v3
-; CHECK-NEXT:    v_add_i32_e32 v11, vcc, 1, v6
-; CHECK-NEXT:    v_cndmask_b32_e64 v10, v10, v12, s[4:5]
-; CHECK-NEXT:    v_addc_u32_e32 v12, vcc, 0, v9, vcc
+; CHECK-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
+; CHECK-NEXT:    v_cmp_eq_u32_e64 s[4:5], v10, v3
+; CHECK-NEXT:    v_add_i32_e32 v10, vcc, 1, v6
+; CHECK-NEXT:    v_cndmask_b32_e64 v8, v8, v11, s[4:5]
+; CHECK-NEXT:    v_addc_u32_e32 v11, vcc, 0, v7, vcc
 ; CHECK-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v3
-; CHECK-NEXT:    v_cndmask_b32_e64 v13, 0, -1, vcc
-; CHECK-NEXT:    v_cmp_ge_u32_e32 vcc, v7, v5
+; CHECK-NEXT:    v_cndmask_b32_e64 v12, 0, -1, vcc
+; CHECK-NEXT:    v_cmp_ge_u32_e32 vcc, v9, v5
 ; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
 ; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v3
-; CHECK-NEXT:    v_cndmask_b32_e32 v1, v13, v5, vcc
-; CHECK-NEXT:    v_add_i32_e32 v3, vcc, 1, v11
-; CHECK-NEXT:    v_addc_u32_e32 v5, vcc, 0, v12, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v1, v12, v5, vcc
+; CHECK-NEXT:    v_add_i32_e32 v3, vcc, 1, v10
+; CHECK-NEXT:    v_addc_u32_e32 v5, vcc, 0, v11, vcc
 ; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1
-; CHECK-NEXT:    v_cndmask_b32_e32 v1, v11, v3, vcc
-; CHECK-NEXT:    v_cndmask_b32_e32 v3, v12, v5, vcc
-; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
+; CHECK-NEXT:    v_cndmask_b32_e32 v1, v10, v3, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v3, v11, v5, vcc
+; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v8
 ; CHECK-NEXT:    v_cndmask_b32_e32 v1, v6, v1, vcc
-; CHECK-NEXT:    v_xor_b32_e32 v5, v8, v4
-; CHECK-NEXT:    v_cndmask_b32_e32 v3, v9, v3, vcc
+; CHECK-NEXT:    v_xor_b32_e32 v5, v14, v4
+; CHECK-NEXT:    v_cndmask_b32_e32 v3, v7, v3, vcc
 ; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v5
 ; CHECK-NEXT:    v_xor_b32_e32 v3, v3, v5
 ; CHECK-NEXT:    v_sub_i32_e32 v4, vcc, v1, v5
@@ -236,30 +236,29 @@
 ; CHECK-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; CHECK-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; CHECK-NEXT:    s_subb_u32 s5, 0, s11
-; CHECK-NEXT:    v_mov_b32_e32 v6, s11
 ; CHECK-NEXT:    v_mul_lo_u32 v2, s5, v0
 ; CHECK-NEXT:    v_mul_lo_u32 v3, s3, v1
-; CHECK-NEXT:    v_mul_hi_u32 v5, s3, v0
-; CHECK-NEXT:    v_mul_lo_u32 v4, s3, v0
+; CHECK-NEXT:    v_mul_hi_u32 v4, s3, v0
+; CHECK-NEXT:    v_mul_lo_u32 v5, s3, v0
 ; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
-; CHECK-NEXT:    v_mul_lo_u32 v3, v1, v4
-; CHECK-NEXT:    v_mul_lo_u32 v5, v0, v2
-; CHECK-NEXT:    v_mul_hi_u32 v7, v0, v4
-; CHECK-NEXT:    v_mul_hi_u32 v4, v1, v4
-; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
-; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
-; CHECK-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
+; CHECK-NEXT:    v_mul_lo_u32 v3, v1, v5
+; CHECK-NEXT:    v_mul_lo_u32 v4, v0, v2
+; CHECK-NEXT:    v_mul_hi_u32 v6, v0, v5
 ; CHECK-NEXT:    v_mul_lo_u32 v7, v1, v2
-; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
-; CHECK-NEXT:    v_mul_hi_u32 v5, v0, v2
-; CHECK-NEXT:    v_mul_hi_u32 v2, v1, v2
-; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
-; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
+; CHECK-NEXT:    v_mul_hi_u32 v5, v1, v5
+; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v3, v4
+; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
+; CHECK-NEXT:    v_mul_hi_u32 v6, v0, v2
+; CHECK-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v7, v5
 ; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
+; CHECK-NEXT:    v_mul_hi_u32 v2, v1, v2
 ; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
 ; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
@@ -268,31 +267,31 @@
 ; CHECK-NEXT:    v_addc_u32_e64 v3, s[0:1], v1, v2, vcc
 ; CHECK-NEXT:    v_mul_lo_u32 v4, s5, v0
 ; CHECK-NEXT:    v_mul_lo_u32 v5, s3, v3
-; CHECK-NEXT:    v_mul_hi_u32 v8, s3, v0
+; CHECK-NEXT:    v_mul_hi_u32 v6, s3, v0
 ; CHECK-NEXT:    v_mul_lo_u32 v7, s3, v0
 ; CHECK-NEXT:    v_add_i32_e64 v1, s[0:1], v1, v2
 ; CHECK-NEXT:    v_add_i32_e64 v4, s[0:1], v4, v5
-; CHECK-NEXT:    v_add_i32_e64 v4, s[0:1], v4, v8
+; CHECK-NEXT:    v_add_i32_e64 v4, s[0:1], v4, v6
 ; CHECK-NEXT:    v_mul_lo_u32 v5, v3, v7
-; CHECK-NEXT:    v_mul_lo_u32 v8, v0, v4
+; CHECK-NEXT:    v_mul_lo_u32 v6, v0, v4
 ; CHECK-NEXT:    v_mul_hi_u32 v2, v0, v7
+; CHECK-NEXT:    v_mul_lo_u32 v8, v3, v4
 ; CHECK-NEXT:    v_mul_hi_u32 v7, v3, v7
-; CHECK-NEXT:    v_add_i32_e64 v5, s[0:1], v5, v8
-; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[0:1]
+; CHECK-NEXT:    v_add_i32_e64 v5, s[0:1], v5, v6
+; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s[0:1]
 ; CHECK-NEXT:    v_add_i32_e64 v2, s[0:1], v5, v2
+; CHECK-NEXT:    v_mul_hi_u32 v5, v0, v4
 ; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s[0:1]
-; CHECK-NEXT:    v_mul_lo_u32 v5, v3, v4
-; CHECK-NEXT:    v_add_i32_e64 v2, s[0:1], v8, v2
-; CHECK-NEXT:    v_mul_hi_u32 v8, v0, v4
-; CHECK-NEXT:    v_mul_hi_u32 v3, v3, v4
-; CHECK-NEXT:    v_add_i32_e64 v5, s[0:1], v5, v7
+; CHECK-NEXT:    v_add_i32_e64 v2, s[0:1], v6, v2
+; CHECK-NEXT:    v_add_i32_e64 v6, s[0:1], v8, v7
 ; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, 1, s[0:1]
-; CHECK-NEXT:    v_add_i32_e64 v5, s[0:1], v5, v8
-; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[0:1]
-; CHECK-NEXT:    v_add_i32_e64 v7, s[0:1], v7, v8
+; CHECK-NEXT:    v_add_i32_e64 v5, s[0:1], v6, v5
+; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s[0:1]
+; CHECK-NEXT:    v_add_i32_e64 v6, s[0:1], v7, v6
+; CHECK-NEXT:    v_mul_hi_u32 v3, v3, v4
 ; CHECK-NEXT:    v_add_i32_e64 v2, s[0:1], v5, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, s[0:1]
-; CHECK-NEXT:    v_add_i32_e64 v4, s[0:1], v7, v5
+; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, 1, s[0:1]
+; CHECK-NEXT:    v_add_i32_e64 v4, s[0:1], v6, v4
 ; CHECK-NEXT:    v_add_i32_e64 v3, s[0:1], v3, v4
 ; CHECK-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
@@ -300,45 +299,46 @@
 ; CHECK-NEXT:    v_mul_lo_u32 v2, s13, v0
 ; CHECK-NEXT:    v_mul_lo_u32 v3, s12, v1
 ; CHECK-NEXT:    v_mul_hi_u32 v5, s12, v0
+; CHECK-NEXT:    v_mul_lo_u32 v6, s13, v1
 ; CHECK-NEXT:    v_mul_hi_u32 v0, s13, v0
-; CHECK-NEXT:    v_mov_b32_e32 v4, s13
 ; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
 ; CHECK-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; CHECK-NEXT:    v_mul_hi_u32 v5, s12, v1
 ; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v5, s13, v1
 ; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; CHECK-NEXT:    v_mul_hi_u32 v3, s12, v1
-; CHECK-NEXT:    v_mul_hi_u32 v1, s13, v1
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v5, v0
-; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
+; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v6, v0
 ; CHECK-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
+; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v5
+; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
+; CHECK-NEXT:    v_mul_hi_u32 v1, s13, v1
 ; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
 ; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v1, v2
 ; CHECK-NEXT:    v_mul_lo_u32 v2, s11, v0
 ; CHECK-NEXT:    v_mul_lo_u32 v1, s10, v1
-; CHECK-NEXT:    v_mul_hi_u32 v5, s10, v0
-; CHECK-NEXT:    v_mul_lo_u32 v3, s10, v0
+; CHECK-NEXT:    v_mul_hi_u32 v3, s10, v0
+; CHECK-NEXT:    v_mul_lo_u32 v5, s10, v0
+; CHECK-NEXT:    v_mov_b32_e32 v6, s13
 ; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
-; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v1, v5
-; CHECK-NEXT:    v_sub_i32_e32 v2, vcc, s12, v3
-; CHECK-NEXT:    v_subb_u32_e64 v3, s[0:1], v4, v1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
+; CHECK-NEXT:    v_sub_i32_e32 v2, vcc, s12, v5
+; CHECK-NEXT:    v_subb_u32_e64 v3, s[0:1], v6, v1, vcc
 ; CHECK-NEXT:    v_sub_i32_e64 v1, s[0:1], s13, v1
+; CHECK-NEXT:    v_mov_b32_e32 v4, s11
 ; CHECK-NEXT:    v_cmp_le_u32_e64 s[0:1], s11, v3
-; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[0:1]
+; CHECK-NEXT:    v_subb_u32_e32 v1, vcc, v1, v4, vcc
+; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
 ; CHECK-NEXT:    v_cmp_le_u32_e64 s[0:1], s10, v2
-; CHECK-NEXT:    v_subb_u32_e32 v1, vcc, v1, v6, vcc
 ; CHECK-NEXT:    v_subrev_i32_e32 v2, vcc, s10, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
-; CHECK-NEXT:    v_cmp_eq_u32_e64 s[0:1], s11, v3
-; CHECK-NEXT:    v_cndmask_b32_e64 v3, v4, v5, s[0:1]
 ; CHECK-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v4, vcc, 1, v0
+; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
+; CHECK-NEXT:    v_cmp_eq_u32_e64 s[0:1], s11, v3
 ; CHECK-NEXT:    v_cmp_le_u32_e32 vcc, s11, v1
+; CHECK-NEXT:    v_cndmask_b32_e64 v3, v5, v6, s[0:1]
 ; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
 ; CHECK-NEXT:    v_cmp_le_u32_e32 vcc, s10, v2
 ; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
@@ -408,279 +408,279 @@
 ; GISEL-NEXT:    v_xor_b32_e32 v5, v5, v8
 ; GISEL-NEXT:    v_cvt_f32_u32_e32 v9, v4
 ; GISEL-NEXT:    v_cvt_f32_u32_e32 v10, v5
-; GISEL-NEXT:    v_ashrrev_i32_e32 v11, 31, v1
-; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v11
-; GISEL-NEXT:    v_addc_u32_e32 v1, vcc, v1, v11, vcc
+; GISEL-NEXT:    v_sub_i32_e32 v11, vcc, 0, v4
+; GISEL-NEXT:    v_subb_u32_e32 v12, vcc, 0, v5, vcc
+; GISEL-NEXT:    v_ashrrev_i32_e32 v17, 31, v1
 ; GISEL-NEXT:    v_mac_f32_e32 v9, 0x4f800000, v10
 ; GISEL-NEXT:    v_rcp_iflag_f32_e32 v9, v9
-; GISEL-NEXT:    v_sub_i32_e32 v12, vcc, 0, v4
-; GISEL-NEXT:    v_subb_u32_e32 v13, vcc, 0, v5, vcc
-; GISEL-NEXT:    v_xor_b32_e32 v0, v0, v11
+; GISEL-NEXT:    v_xor_b32_e32 v8, v17, v8
 ; GISEL-NEXT:    v_mul_f32_e32 v9, 0x5f7ffffc, v9
 ; GISEL-NEXT:    v_mul_f32_e32 v10, 0x2f800000, v9
 ; GISEL-NEXT:    v_trunc_f32_e32 v10, v10
 ; GISEL-NEXT:    v_mac_f32_e32 v9, 0xcf800000, v10
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v9, v9
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v10, v10
-; GISEL-NEXT:    v_xor_b32_e32 v1, v1, v11
-; GISEL-NEXT:    v_mul_lo_u32 v14, v13, v9
-; GISEL-NEXT:    v_mul_lo_u32 v15, v12, v10
-; GISEL-NEXT:    v_mul_hi_u32 v17, v12, v9
-; GISEL-NEXT:    v_mul_lo_u32 v16, v12, v9
-; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v15
-; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v17
-; GISEL-NEXT:    v_mul_lo_u32 v15, v10, v16
-; GISEL-NEXT:    v_mul_lo_u32 v17, v9, v14
+; GISEL-NEXT:    v_mul_lo_u32 v13, v12, v9
+; GISEL-NEXT:    v_mul_lo_u32 v14, v11, v10
+; GISEL-NEXT:    v_mul_hi_u32 v15, v11, v9
+; GISEL-NEXT:    v_mul_lo_u32 v16, v11, v9
+; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v14
+; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v15
+; GISEL-NEXT:    v_mul_lo_u32 v14, v10, v16
+; GISEL-NEXT:    v_mul_lo_u32 v15, v9, v13
 ; GISEL-NEXT:    v_mul_hi_u32 v18, v9, v16
+; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v17
+; GISEL-NEXT:    v_addc_u32_e32 v1, vcc, v1, v17, vcc
+; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v15
+; GISEL-NEXT:    v_mul_lo_u32 v19, v10, v13
 ; GISEL-NEXT:    v_mul_hi_u32 v16, v10, v16
-; GISEL-NEXT:    v_add_i32_e32 v15, vcc, v15, v17
-; GISEL-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v15, vcc, v15, v18
 ; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v18, v10, v14
-; GISEL-NEXT:    v_add_i32_e32 v15, vcc, v17, v15
-; GISEL-NEXT:    v_mul_hi_u32 v17, v9, v14
-; GISEL-NEXT:    v_mul_hi_u32 v14, v10, v14
-; GISEL-NEXT:    v_add_i32_e32 v16, vcc, v18, v16
+; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v18
+; GISEL-NEXT:    v_mul_hi_u32 v18, v9, v13
+; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
+; GISEL-NEXT:    v_add_i32_e32 v15, vcc, v19, v16
+; GISEL-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v15, vcc, v15, v18
 ; GISEL-NEXT:    v_cndmask_b32_e64 v18, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v16, vcc, v16, v17
-; GISEL-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v17, vcc, v18, v17
+; GISEL-NEXT:    v_add_i32_e32 v16, vcc, v16, v18
+; GISEL-NEXT:    v_mul_hi_u32 v13, v10, v13
+; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
+; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v15, vcc, v16, v15
-; GISEL-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v16, vcc, v17, v16
-; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v16
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v15
-; GISEL-NEXT:    v_addc_u32_e64 v15, s[4:5], v10, v14, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v13, v13, v9
-; GISEL-NEXT:    v_mul_lo_u32 v16, v12, v15
-; GISEL-NEXT:    v_mul_lo_u32 v17, v12, v9
-; GISEL-NEXT:    v_mul_hi_u32 v12, v12, v9
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v14
-; GISEL-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v16
-; GISEL-NEXT:    v_mul_hi_u32 v14, v9, v17
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v13, v12
-; GISEL-NEXT:    v_mul_lo_u32 v13, v15, v17
+; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v15
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v14
+; GISEL-NEXT:    v_addc_u32_e64 v14, s[4:5], v10, v13, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v12, v12, v9
+; GISEL-NEXT:    v_mul_lo_u32 v15, v11, v14
+; GISEL-NEXT:    v_mul_hi_u32 v16, v11, v9
+; GISEL-NEXT:    v_mul_lo_u32 v11, v11, v9
+; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v13
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v15
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v16
+; GISEL-NEXT:    v_mul_lo_u32 v15, v14, v11
 ; GISEL-NEXT:    v_mul_lo_u32 v16, v9, v12
-; GISEL-NEXT:    v_mul_hi_u32 v17, v15, v17
-; GISEL-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v16
+; GISEL-NEXT:    v_mul_hi_u32 v13, v9, v11
+; GISEL-NEXT:    v_mul_lo_u32 v18, v14, v12
+; GISEL-NEXT:    v_mul_hi_u32 v11, v14, v11
+; GISEL-NEXT:    v_add_i32_e64 v15, s[4:5], v15, v16
 ; GISEL-NEXT:    v_cndmask_b32_e64 v16, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v14
+; GISEL-NEXT:    v_add_i32_e64 v13, s[4:5], v15, v13
+; GISEL-NEXT:    v_mul_hi_u32 v15, v9, v12
 ; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; GISEL-NEXT:    v_mul_lo_u32 v14, v15, v12
 ; GISEL-NEXT:    v_add_i32_e64 v13, s[4:5], v16, v13
-; GISEL-NEXT:    v_mul_hi_u32 v16, v9, v12
-; GISEL-NEXT:    v_mul_hi_u32 v12, v15, v12
-; GISEL-NEXT:    v_add_i32_e64 v14, s[4:5], v14, v17
-; GISEL-NEXT:    v_cndmask_b32_e64 v17, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v14, s[4:5], v14, v16
+; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v18, v11
 ; GISEL-NEXT:    v_cndmask_b32_e64 v16, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v16, s[4:5], v17, v16
-; GISEL-NEXT:    v_add_i32_e64 v13, s[4:5], v14, v13
-; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v14, s[4:5], v16, v14
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v14
+; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v15
+; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v15, s[4:5], v16, v15
+; GISEL-NEXT:    v_mul_hi_u32 v12, v14, v12
+; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v13
+; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v13, s[4:5], v15, v13
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v13
 ; GISEL-NEXT:    v_addc_u32_e32 v10, vcc, v10, v12, vcc
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v13
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; GISEL-NEXT:    v_xor_b32_e32 v0, v0, v17
+; GISEL-NEXT:    v_xor_b32_e32 v1, v1, v17
 ; GISEL-NEXT:    v_addc_u32_e32 v10, vcc, 0, v10, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v12, v1, v9
-; GISEL-NEXT:    v_mul_lo_u32 v13, v0, v10
-; GISEL-NEXT:    v_mul_hi_u32 v14, v0, v9
+; GISEL-NEXT:    v_mul_lo_u32 v11, v1, v9
+; GISEL-NEXT:    v_mul_lo_u32 v12, v0, v10
+; GISEL-NEXT:    v_mul_hi_u32 v13, v0, v9
+; GISEL-NEXT:    v_mul_lo_u32 v14, v1, v10
 ; GISEL-NEXT:    v_mul_hi_u32 v9, v1, v9
-; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
-; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v14
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v14, v1, v10
-; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v13
 ; GISEL-NEXT:    v_mul_hi_u32 v13, v0, v10
-; GISEL-NEXT:    v_mul_hi_u32 v10, v1, v10
+; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
 ; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v14, v9
-; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v13
 ; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
-; GISEL-NEXT:    v_mul_lo_u32 v12, v5, v9
-; GISEL-NEXT:    v_mul_lo_u32 v13, v4, v10
-; GISEL-NEXT:    v_mul_hi_u32 v15, v4, v9
-; GISEL-NEXT:    v_mul_lo_u32 v14, v4, v9
 ; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
-; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v15
+; GISEL-NEXT:    v_mul_hi_u32 v10, v1, v10
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
+; GISEL-NEXT:    v_mul_lo_u32 v11, v5, v9
+; GISEL-NEXT:    v_mul_lo_u32 v12, v4, v10
+; GISEL-NEXT:    v_mul_hi_u32 v13, v4, v9
+; GISEL-NEXT:    v_mul_lo_u32 v14, v4, v9
+; GISEL-NEXT:    v_ashrrev_i32_e32 v16, 31, v3
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v13
 ; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v14
-; GISEL-NEXT:    v_subb_u32_e64 v13, s[4:5], v1, v12, vcc
-; GISEL-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v12
-; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v13, v5
+; GISEL-NEXT:    v_subb_u32_e64 v12, s[4:5], v1, v11, vcc
+; GISEL-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v11
+; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v12, v5
 ; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v5, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
 ; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v0, v4
 ; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
 ; GISEL-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v13, v5
-; GISEL-NEXT:    v_add_i32_e32 v13, vcc, 1, v9
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, v12, v14, s[4:5]
-; GISEL-NEXT:    v_addc_u32_e32 v14, vcc, 0, v10, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v12, v5
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, 1, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v11, v11, v13, s[4:5]
+; GISEL-NEXT:    v_addc_u32_e32 v13, vcc, 0, v10, vcc
 ; GISEL-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v5
-; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, -1, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, -1, vcc
 ; GISEL-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v4
 ; GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
 ; GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v5
-; GISEL-NEXT:    v_cndmask_b32_e32 v0, v15, v0, vcc
-; GISEL-NEXT:    v_add_i32_e32 v1, vcc, 1, v13
-; GISEL-NEXT:    v_addc_u32_e32 v4, vcc, 0, v14, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
-; GISEL-NEXT:    v_cndmask_b32_e32 v0, v13, v1, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v1, v14, v4, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v12
+; GISEL-NEXT:    v_cndmask_b32_e32 v0, v14, v0, vcc
+; GISEL-NEXT:    v_add_i32_e32 v1, vcc, 1, v12
+; GISEL-NEXT:    v_addc_u32_e32 v4, vcc, 0, v13, vcc
 ; GISEL-NEXT:    v_ashrrev_i32_e32 v5, 31, v7
-; GISEL-NEXT:    v_cndmask_b32_e32 v1, v10, v1, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v0, v9, v0, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v5
 ; GISEL-NEXT:    v_addc_u32_e32 v7, vcc, v7, v5, vcc
-; GISEL-NEXT:    v_xor_b32_e32 v7, v7, v5
 ; GISEL-NEXT:    v_xor_b32_e32 v6, v6, v5
-; GISEL-NEXT:    v_xor_b32_e32 v4, v11, v8
-; GISEL-NEXT:    v_cvt_f32_u32_e32 v8, v6
-; GISEL-NEXT:    v_cvt_f32_u32_e32 v9, v7
-; GISEL-NEXT:    v_ashrrev_i32_e32 v10, 31, v3
-; GISEL-NEXT:    v_add_i32_e32 v2, vcc, v2, v10
-; GISEL-NEXT:    v_addc_u32_e32 v3, vcc, v3, v10, vcc
-; GISEL-NEXT:    v_mac_f32_e32 v8, 0x4f800000, v9
-; GISEL-NEXT:    v_rcp_iflag_f32_e32 v8, v8
-; GISEL-NEXT:    v_sub_i32_e32 v11, vcc, 0, v6
-; GISEL-NEXT:    v_subb_u32_e32 v12, vcc, 0, v7, vcc
-; GISEL-NEXT:    v_xor_b32_e32 v0, v0, v4
-; GISEL-NEXT:    v_mul_f32_e32 v8, 0x5f7ffffc, v8
-; GISEL-NEXT:    v_mul_f32_e32 v9, 0x2f800000, v8
+; GISEL-NEXT:    v_xor_b32_e32 v7, v7, v5
+; GISEL-NEXT:    v_cvt_f32_u32_e32 v14, v6
+; GISEL-NEXT:    v_cvt_f32_u32_e32 v15, v7
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
+; GISEL-NEXT:    v_cndmask_b32_e32 v0, v12, v1, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v1, v13, v4, vcc
+; GISEL-NEXT:    v_mac_f32_e32 v14, 0x4f800000, v15
+; GISEL-NEXT:    v_rcp_iflag_f32_e32 v4, v14
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11
+; GISEL-NEXT:    v_cndmask_b32_e32 v0, v9, v0, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v1, v10, v1, vcc
+; GISEL-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
+; GISEL-NEXT:    v_mul_f32_e32 v9, 0x2f800000, v4
 ; GISEL-NEXT:    v_trunc_f32_e32 v9, v9
-; GISEL-NEXT:    v_mac_f32_e32 v8, 0xcf800000, v9
-; GISEL-NEXT:    v_cvt_u32_f32_e32 v8, v8
+; GISEL-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v9
+; GISEL-NEXT:    v_cvt_u32_f32_e32 v4, v4
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v9, v9
-; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v10
-; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v10
-; GISEL-NEXT:    v_mul_lo_u32 v13, v12, v8
-; GISEL-NEXT:    v_mul_lo_u32 v14, v11, v9
-; GISEL-NEXT:    v_mul_hi_u32 v16, v11, v8
-; GISEL-NEXT:    v_mul_lo_u32 v15, v11, v8
-; GISEL-NEXT:    v_xor_b32_e32 v1, v1, v4
+; GISEL-NEXT:    v_sub_i32_e32 v10, vcc, 0, v6
+; GISEL-NEXT:    v_subb_u32_e32 v11, vcc, 0, v7, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v12, v11, v4
+; GISEL-NEXT:    v_mul_lo_u32 v13, v10, v9
+; GISEL-NEXT:    v_mul_hi_u32 v14, v10, v4
+; GISEL-NEXT:    v_mul_lo_u32 v15, v10, v4
+; GISEL-NEXT:    v_xor_b32_e32 v0, v0, v8
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v14
+; GISEL-NEXT:    v_mul_lo_u32 v13, v9, v15
+; GISEL-NEXT:    v_mul_lo_u32 v14, v4, v12
+; GISEL-NEXT:    v_mul_hi_u32 v17, v4, v15
+; GISEL-NEXT:    v_add_i32_e32 v2, vcc, v2, v16
+; GISEL-NEXT:    v_addc_u32_e32 v3, vcc, v3, v16, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v14
-; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v16
-; GISEL-NEXT:    v_mul_lo_u32 v14, v9, v15
-; GISEL-NEXT:    v_mul_lo_u32 v16, v8, v13
-; GISEL-NEXT:    v_mul_hi_u32 v17, v8, v15
+; GISEL-NEXT:    v_mul_lo_u32 v18, v9, v12
 ; GISEL-NEXT:    v_mul_hi_u32 v15, v9, v15
-; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v16
-; GISEL-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v17
 ; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v17, v9, v13
-; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v16, v14
-; GISEL-NEXT:    v_mul_hi_u32 v16, v8, v13
-; GISEL-NEXT:    v_mul_hi_u32 v13, v9, v13
-; GISEL-NEXT:    v_add_i32_e32 v15, vcc, v17, v15
+; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v17
+; GISEL-NEXT:    v_mul_hi_u32 v17, v4, v12
+; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
+; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v18, v15
+; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v17
 ; GISEL-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v15, vcc, v15, v16
-; GISEL-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v16, vcc, v17, v16
+; GISEL-NEXT:    v_add_i32_e32 v15, vcc, v15, v17
+; GISEL-NEXT:    v_mul_hi_u32 v12, v9, v12
+; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
+; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
-; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v15, vcc, v16, v15
-; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v15
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v14
-; GISEL-NEXT:    v_addc_u32_e64 v14, s[4:5], v9, v13, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v12, v12, v8
-; GISEL-NEXT:    v_mul_lo_u32 v15, v11, v14
-; GISEL-NEXT:    v_mul_lo_u32 v16, v11, v8
-; GISEL-NEXT:    v_mul_hi_u32 v11, v11, v8
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v13
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v15
-; GISEL-NEXT:    v_mul_hi_u32 v13, v8, v16
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v12, v11
-; GISEL-NEXT:    v_mul_lo_u32 v12, v14, v16
-; GISEL-NEXT:    v_mul_lo_u32 v15, v8, v11
-; GISEL-NEXT:    v_mul_hi_u32 v16, v14, v16
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v15
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v14
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v13
+; GISEL-NEXT:    v_addc_u32_e64 v13, s[4:5], v9, v12, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v11, v11, v4
+; GISEL-NEXT:    v_mul_lo_u32 v14, v10, v13
+; GISEL-NEXT:    v_mul_hi_u32 v15, v10, v4
+; GISEL-NEXT:    v_mul_lo_u32 v10, v10, v4
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v12
+; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v14
+; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v15
+; GISEL-NEXT:    v_mul_lo_u32 v14, v13, v10
+; GISEL-NEXT:    v_mul_lo_u32 v15, v4, v11
+; GISEL-NEXT:    v_mul_hi_u32 v12, v4, v10
+; GISEL-NEXT:    v_mul_lo_u32 v17, v13, v11
+; GISEL-NEXT:    v_mul_hi_u32 v10, v13, v10
+; GISEL-NEXT:    v_add_i32_e64 v14, s[4:5], v14, v15
 ; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v13
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v14, v12
+; GISEL-NEXT:    v_mul_hi_u32 v14, v4, v11
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_mul_lo_u32 v13, v14, v11
 ; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v15, v12
-; GISEL-NEXT:    v_mul_hi_u32 v15, v8, v11
-; GISEL-NEXT:    v_mul_hi_u32 v11, v14, v11
-; GISEL-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v16
-; GISEL-NEXT:    v_cndmask_b32_e64 v16, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v15
+; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v17, v10
 ; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v15, s[4:5], v16, v15
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v13, v12
-; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v13, s[4:5], v15, v13
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v13
+; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v14
+; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v14, s[4:5], v15, v14
+; GISEL-NEXT:    v_mul_hi_u32 v11, v13, v11
+; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v12
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v14, v12
+; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
 ; GISEL-NEXT:    v_addc_u32_e32 v9, vcc, v9, v11, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v12
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v10
+; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v16
+; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v16
 ; GISEL-NEXT:    v_addc_u32_e32 v9, vcc, 0, v9, vcc
-; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
-; GISEL-NEXT:    v_mul_lo_u32 v11, v3, v8
-; GISEL-NEXT:    v_mul_lo_u32 v12, v2, v9
-; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v4, vcc
-; GISEL-NEXT:    v_mul_hi_u32 v4, v2, v8
-; GISEL-NEXT:    v_mul_hi_u32 v8, v3, v8
-; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v11, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v11, v3, v9
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v12, v4
+; GISEL-NEXT:    v_mul_lo_u32 v10, v3, v4
+; GISEL-NEXT:    v_mul_lo_u32 v11, v2, v9
+; GISEL-NEXT:    v_mul_hi_u32 v12, v2, v4
+; GISEL-NEXT:    v_mul_lo_u32 v13, v3, v9
+; GISEL-NEXT:    v_mul_hi_u32 v4, v3, v4
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
+; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
 ; GISEL-NEXT:    v_mul_hi_u32 v12, v2, v9
-; GISEL-NEXT:    v_mul_hi_u32 v9, v3, v9
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v11, v8
+; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v13, v4
 ; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v12
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v12
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v8, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v11, v8
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
-; GISEL-NEXT:    v_mul_lo_u32 v9, v7, v4
-; GISEL-NEXT:    v_mul_lo_u32 v11, v6, v8
+; GISEL-NEXT:    v_mul_hi_u32 v9, v3, v9
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v10
+; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
+; GISEL-NEXT:    v_mul_lo_u32 v11, v7, v4
+; GISEL-NEXT:    v_mul_lo_u32 v12, v6, v9
 ; GISEL-NEXT:    v_mul_hi_u32 v13, v6, v4
-; GISEL-NEXT:    v_mul_lo_u32 v12, v6, v4
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v13
-; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v12
-; GISEL-NEXT:    v_subb_u32_e64 v11, s[4:5], v3, v9, vcc
-; GISEL-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v9
-; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v11, v7
+; GISEL-NEXT:    v_mul_lo_u32 v10, v6, v4
+; GISEL-NEXT:    v_xor_b32_e32 v1, v1, v8
+; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v8
+; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v8, vcc
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v11, v12
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v13
+; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v10
+; GISEL-NEXT:    v_subb_u32_e64 v10, s[4:5], v3, v8, vcc
+; GISEL-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v8
+; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v10, v7
 ; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v7, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
 ; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v2, v6
 ; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v6
 ; GISEL-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v11, v7
-; GISEL-NEXT:    v_add_i32_e32 v11, vcc, 1, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v9, v9, v12, s[4:5]
-; GISEL-NEXT:    v_addc_u32_e32 v12, vcc, 0, v8, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v10, v7
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, 1, v4
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, v8, v11, s[4:5]
+; GISEL-NEXT:    v_addc_u32_e32 v11, vcc, 0, v9, vcc
 ; GISEL-NEXT:    v_cmp_ge_u32_e32 vcc, v3, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, -1, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, -1, vcc
 ; GISEL-NEXT:    v_cmp_ge_u32_e32 vcc, v2, v6
 ; GISEL-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
 ; GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v7
-; GISEL-NEXT:    v_cndmask_b32_e32 v2, v13, v2, vcc
-; GISEL-NEXT:    v_add_i32_e32 v3, vcc, 1, v11
-; GISEL-NEXT:    v_addc_u32_e32 v6, vcc, 0, v12, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v2, v12, v2, vcc
+; GISEL-NEXT:    v_add_i32_e32 v3, vcc, 1, v10
+; GISEL-NEXT:    v_addc_u32_e32 v6, vcc, 0, v11, vcc
 ; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
-; GISEL-NEXT:    v_cndmask_b32_e32 v2, v11, v3, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v3, v12, v6, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v9
+; GISEL-NEXT:    v_cndmask_b32_e32 v2, v10, v3, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v3, v11, v6, vcc
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v8
 ; GISEL-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
-; GISEL-NEXT:    v_xor_b32_e32 v4, v10, v5
-; GISEL-NEXT:    v_cndmask_b32_e32 v3, v8, v3, vcc
+; GISEL-NEXT:    v_xor_b32_e32 v4, v16, v5
+; GISEL-NEXT:    v_cndmask_b32_e32 v3, v9, v3, vcc
 ; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v4
 ; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v4
 ; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v4
@@ -707,137 +707,137 @@
 ; CGP-NEXT:    v_xor_b32_e32 v5, v5, v0
 ; CGP-NEXT:    v_cvt_f32_u32_e32 v10, v1
 ; CGP-NEXT:    v_cvt_f32_u32_e32 v11, v5
-; CGP-NEXT:    v_ashrrev_i32_e32 v12, 31, v9
+; CGP-NEXT:    v_sub_i32_e32 v12, vcc, 0, v1
+; CGP-NEXT:    v_subb_u32_e32 v13, vcc, 0, v5, vcc
+; CGP-NEXT:    v_ashrrev_i32_e32 v18, 31, v9
 ; CGP-NEXT:    v_mac_f32_e32 v10, 0x4f800000, v11
 ; CGP-NEXT:    v_rcp_iflag_f32_e32 v10, v10
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v8, v12
-; CGP-NEXT:    v_addc_u32_e32 v9, vcc, v9, v12, vcc
-; CGP-NEXT:    v_sub_i32_e32 v14, vcc, 0, v1
 ; CGP-NEXT:    v_mul_f32_e32 v10, 0x5f7ffffc, v10
-; CGP-NEXT:    v_mul_f32_e32 v13, 0x2f800000, v10
-; CGP-NEXT:    v_trunc_f32_e32 v13, v13
-; CGP-NEXT:    v_mac_f32_e32 v10, 0xcf800000, v13
+; CGP-NEXT:    v_mul_f32_e32 v11, 0x2f800000, v10
+; CGP-NEXT:    v_trunc_f32_e32 v11, v11
+; CGP-NEXT:    v_mac_f32_e32 v10, 0xcf800000, v11
 ; CGP-NEXT:    v_cvt_u32_f32_e32 v10, v10
-; CGP-NEXT:    v_cvt_u32_f32_e32 v13, v13
-; CGP-NEXT:    v_subb_u32_e32 v15, vcc, 0, v5, vcc
-; CGP-NEXT:    v_xor_b32_e32 v11, v11, v12
-; CGP-NEXT:    v_mul_lo_u32 v16, v15, v10
-; CGP-NEXT:    v_mul_lo_u32 v17, v14, v13
-; CGP-NEXT:    v_mul_hi_u32 v19, v14, v10
-; CGP-NEXT:    v_mul_lo_u32 v18, v14, v10
-; CGP-NEXT:    v_xor_b32_e32 v9, v9, v12
-; CGP-NEXT:    v_add_i32_e32 v16, vcc, v16, v17
-; CGP-NEXT:    v_add_i32_e32 v16, vcc, v16, v19
-; CGP-NEXT:    v_mul_lo_u32 v17, v13, v18
-; CGP-NEXT:    v_mul_lo_u32 v19, v10, v16
-; CGP-NEXT:    v_mul_hi_u32 v20, v10, v18
-; CGP-NEXT:    v_mul_hi_u32 v18, v13, v18
-; CGP-NEXT:    v_add_i32_e32 v17, vcc, v17, v19
-; CGP-NEXT:    v_cndmask_b32_e64 v19, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v17, vcc, v17, v20
+; CGP-NEXT:    v_cvt_u32_f32_e32 v11, v11
+; CGP-NEXT:    v_mul_lo_u32 v15, v13, v10
+; CGP-NEXT:    v_mul_lo_u32 v14, v12, v11
+; CGP-NEXT:    v_mul_hi_u32 v17, v12, v10
+; CGP-NEXT:    v_mul_lo_u32 v16, v12, v10
+; CGP-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
+; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v17
+; CGP-NEXT:    v_mul_lo_u32 v15, v11, v16
+; CGP-NEXT:    v_mul_lo_u32 v17, v10, v14
+; CGP-NEXT:    v_mul_hi_u32 v20, v10, v16
+; CGP-NEXT:    v_add_i32_e32 v19, vcc, v8, v18
+; CGP-NEXT:    v_addc_u32_e32 v9, vcc, v9, v18, vcc
+; CGP-NEXT:    v_add_i32_e32 v15, vcc, v15, v17
+; CGP-NEXT:    v_mul_lo_u32 v21, v11, v14
+; CGP-NEXT:    v_mul_hi_u32 v16, v11, v16
+; CGP-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v15, vcc, v15, v20
+; CGP-NEXT:    v_mul_hi_u32 v20, v10, v14
+; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v15, vcc, v17, v15
+; CGP-NEXT:    v_add_i32_e32 v16, vcc, v21, v16
 ; CGP-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v20, v13, v16
-; CGP-NEXT:    v_add_i32_e32 v17, vcc, v19, v17
-; CGP-NEXT:    v_mul_hi_u32 v19, v10, v16
-; CGP-NEXT:    v_mul_hi_u32 v16, v13, v16
-; CGP-NEXT:    v_add_i32_e32 v18, vcc, v20, v18
+; CGP-NEXT:    v_add_i32_e32 v16, vcc, v16, v20
 ; CGP-NEXT:    v_cndmask_b32_e64 v20, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v18, vcc, v18, v19
-; CGP-NEXT:    v_cndmask_b32_e64 v19, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v19, vcc, v20, v19
-; CGP-NEXT:    v_add_i32_e32 v17, vcc, v18, v17
-; CGP-NEXT:    v_cndmask_b32_e64 v18, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v18, vcc, v19, v18
-; CGP-NEXT:    v_add_i32_e32 v16, vcc, v16, v18
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v17
-; CGP-NEXT:    v_addc_u32_e64 v17, s[4:5], v13, v16, vcc
-; CGP-NEXT:    v_mul_lo_u32 v15, v15, v10
-; CGP-NEXT:    v_mul_lo_u32 v18, v14, v17
-; CGP-NEXT:    v_mul_lo_u32 v19, v14, v10
-; CGP-NEXT:    v_mul_hi_u32 v14, v14, v10
+; CGP-NEXT:    v_add_i32_e32 v17, vcc, v17, v20
+; CGP-NEXT:    v_mul_hi_u32 v14, v11, v14
+; CGP-NEXT:    v_add_i32_e32 v15, vcc, v16, v15
+; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v16, vcc, v17, v16
+; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v16
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v15
+; CGP-NEXT:    v_addc_u32_e64 v15, s[4:5], v11, v14, vcc
+; CGP-NEXT:    v_mul_lo_u32 v13, v13, v10
+; CGP-NEXT:    v_mul_lo_u32 v16, v12, v15
+; CGP-NEXT:    v_mul_hi_u32 v17, v12, v10
+; CGP-NEXT:    v_mul_lo_u32 v12, v12, v10
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v14
 ; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v16
-; CGP-NEXT:    v_add_i32_e64 v15, s[4:5], v15, v18
-; CGP-NEXT:    v_mul_hi_u32 v16, v10, v19
-; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v15, v14
-; CGP-NEXT:    v_mul_lo_u32 v15, v17, v19
-; CGP-NEXT:    v_mul_lo_u32 v18, v10, v14
-; CGP-NEXT:    v_mul_hi_u32 v19, v17, v19
-; CGP-NEXT:    v_add_i32_e64 v15, s[4:5], v15, v18
-; CGP-NEXT:    v_cndmask_b32_e64 v18, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v15, s[4:5], v15, v16
-; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
-; CGP-NEXT:    v_mul_lo_u32 v16, v17, v14
-; CGP-NEXT:    v_add_i32_e64 v15, s[4:5], v18, v15
-; CGP-NEXT:    v_mul_hi_u32 v18, v10, v14
-; CGP-NEXT:    v_mul_hi_u32 v14, v17, v14
-; CGP-NEXT:    v_add_i32_e64 v16, s[4:5], v16, v19
-; CGP-NEXT:    v_cndmask_b32_e64 v19, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v16, s[4:5], v16, v18
-; CGP-NEXT:    v_cndmask_b32_e64 v18, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v18, s[4:5], v19, v18
-; CGP-NEXT:    v_add_i32_e64 v15, s[4:5], v16, v15
+; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v17
+; CGP-NEXT:    v_mul_lo_u32 v16, v15, v12
+; CGP-NEXT:    v_mul_lo_u32 v17, v10, v13
+; CGP-NEXT:    v_mul_hi_u32 v14, v10, v12
+; CGP-NEXT:    v_mul_lo_u32 v20, v15, v13
+; CGP-NEXT:    v_mul_hi_u32 v12, v15, v12
+; CGP-NEXT:    v_add_i32_e64 v16, s[4:5], v16, v17
+; CGP-NEXT:    v_cndmask_b32_e64 v17, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v16, v14
+; CGP-NEXT:    v_mul_hi_u32 v16, v10, v13
+; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v17, v14
+; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v20, v12
+; CGP-NEXT:    v_cndmask_b32_e64 v17, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v16
 ; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v16, s[4:5], v18, v16
-; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v14, v16
-; CGP-NEXT:    v_addc_u32_e32 v13, vcc, v13, v14, vcc
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v15
-; CGP-NEXT:    v_addc_u32_e32 v13, vcc, 0, v13, vcc
-; CGP-NEXT:    v_mul_lo_u32 v14, v9, v10
-; CGP-NEXT:    v_mul_lo_u32 v15, v11, v13
-; CGP-NEXT:    v_mul_hi_u32 v16, v11, v10
+; CGP-NEXT:    v_add_i32_e64 v16, s[4:5], v17, v16
+; CGP-NEXT:    v_mul_hi_u32 v13, v15, v13
+; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v14
+; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v16, v14
+; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v14
+; CGP-NEXT:    v_addc_u32_e32 v11, vcc, v11, v13, vcc
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
+; CGP-NEXT:    v_xor_b32_e32 v19, v19, v18
+; CGP-NEXT:    v_xor_b32_e32 v9, v9, v18
+; CGP-NEXT:    v_addc_u32_e32 v11, vcc, 0, v11, vcc
+; CGP-NEXT:    v_mul_lo_u32 v12, v9, v10
+; CGP-NEXT:    v_mul_lo_u32 v13, v19, v11
+; CGP-NEXT:    v_mul_hi_u32 v14, v19, v10
+; CGP-NEXT:    v_mul_lo_u32 v15, v9, v11
 ; CGP-NEXT:    v_mul_hi_u32 v10, v9, v10
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v15
-; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v16
-; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v16, v9, v13
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
-; CGP-NEXT:    v_mul_hi_u32 v15, v11, v13
-; CGP-NEXT:    v_mul_hi_u32 v13, v9, v13
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v16, v10
-; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v15
-; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v15, vcc, v16, v15
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
+; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v14
+; CGP-NEXT:    v_mul_hi_u32 v14, v19, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v15, v10
+; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
 ; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v14
 ; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
 ; CGP-NEXT:    v_add_i32_e32 v13, vcc, v13, v14
-; CGP-NEXT:    v_mul_lo_u32 v14, v5, v10
-; CGP-NEXT:    v_mul_lo_u32 v15, v1, v13
-; CGP-NEXT:    v_mul_hi_u32 v17, v1, v10
-; CGP-NEXT:    v_mul_lo_u32 v16, v1, v10
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v15
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v17
-; CGP-NEXT:    v_sub_i32_e32 v11, vcc, v11, v16
-; CGP-NEXT:    v_subb_u32_e64 v15, s[4:5], v9, v14, vcc
-; CGP-NEXT:    v_sub_i32_e64 v9, s[4:5], v9, v14
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v15, v5
+; CGP-NEXT:    v_mul_hi_u32 v11, v9, v11
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
+; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
+; CGP-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
+; CGP-NEXT:    v_mul_lo_u32 v12, v5, v10
+; CGP-NEXT:    v_mul_lo_u32 v13, v1, v11
+; CGP-NEXT:    v_mul_hi_u32 v14, v1, v10
+; CGP-NEXT:    v_mul_lo_u32 v15, v1, v10
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v14
+; CGP-NEXT:    v_sub_i32_e32 v13, vcc, v19, v15
+; CGP-NEXT:    v_subb_u32_e64 v14, s[4:5], v9, v12, vcc
+; CGP-NEXT:    v_sub_i32_e64 v9, s[4:5], v9, v12
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v14, v5
 ; CGP-NEXT:    v_subb_u32_e32 v9, vcc, v9, v5, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v11, v1
-; CGP-NEXT:    v_sub_i32_e32 v11, vcc, v11, v1
+; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v13, v1
+; CGP-NEXT:    v_sub_i32_e32 v13, vcc, v13, v1
 ; CGP-NEXT:    v_subbrev_u32_e32 v9, vcc, 0, v9, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], v15, v5
-; CGP-NEXT:    v_add_i32_e32 v15, vcc, 1, v10
-; CGP-NEXT:    v_cndmask_b32_e64 v14, v14, v16, s[4:5]
-; CGP-NEXT:    v_addc_u32_e32 v16, vcc, 0, v13, vcc
+; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], v14, v5
+; CGP-NEXT:    v_add_i32_e32 v14, vcc, 1, v10
+; CGP-NEXT:    v_cndmask_b32_e64 v12, v12, v15, s[4:5]
+; CGP-NEXT:    v_addc_u32_e32 v15, vcc, 0, v11, vcc
 ; CGP-NEXT:    v_cmp_ge_u32_e32 vcc, v9, v5
-; CGP-NEXT:    v_cndmask_b32_e64 v17, 0, -1, vcc
-; CGP-NEXT:    v_cmp_ge_u32_e32 vcc, v11, v1
+; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, -1, vcc
+; CGP-NEXT:    v_cmp_ge_u32_e32 vcc, v13, v1
 ; CGP-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc
 ; CGP-NEXT:    v_cmp_eq_u32_e32 vcc, v9, v5
-; CGP-NEXT:    v_cndmask_b32_e32 v1, v17, v1, vcc
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, 1, v15
-; CGP-NEXT:    v_addc_u32_e32 v9, vcc, 0, v16, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v1, v16, v1, vcc
+; CGP-NEXT:    v_add_i32_e32 v5, vcc, 1, v14
+; CGP-NEXT:    v_addc_u32_e32 v9, vcc, 0, v15, vcc
 ; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1
-; CGP-NEXT:    v_cndmask_b32_e32 v1, v15, v5, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v5, v16, v9, vcc
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v14
+; CGP-NEXT:    v_cndmask_b32_e32 v1, v14, v5, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v5, v15, v9, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v12
 ; CGP-NEXT:    v_cndmask_b32_e32 v1, v10, v1, vcc
-; CGP-NEXT:    v_xor_b32_e32 v9, v12, v0
-; CGP-NEXT:    v_cndmask_b32_e32 v5, v13, v5, vcc
+; CGP-NEXT:    v_xor_b32_e32 v9, v18, v0
+; CGP-NEXT:    v_cndmask_b32_e32 v5, v11, v5, vcc
 ; CGP-NEXT:    v_xor_b32_e32 v0, v1, v9
 ; CGP-NEXT:    v_xor_b32_e32 v1, v5, v9
 ; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v0, v9
@@ -884,137 +884,137 @@
 ; CGP-NEXT:    v_xor_b32_e32 v7, v7, v4
 ; CGP-NEXT:    v_cvt_f32_u32_e32 v8, v5
 ; CGP-NEXT:    v_cvt_f32_u32_e32 v9, v7
-; CGP-NEXT:    v_ashrrev_i32_e32 v10, 31, v3
+; CGP-NEXT:    v_sub_i32_e32 v10, vcc, 0, v5
+; CGP-NEXT:    v_subb_u32_e32 v11, vcc, 0, v7, vcc
+; CGP-NEXT:    v_ashrrev_i32_e32 v16, 31, v3
 ; CGP-NEXT:    v_mac_f32_e32 v8, 0x4f800000, v9
 ; CGP-NEXT:    v_rcp_iflag_f32_e32 v8, v8
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v2, v10
-; CGP-NEXT:    v_addc_u32_e32 v3, vcc, v3, v10, vcc
-; CGP-NEXT:    v_sub_i32_e32 v12, vcc, 0, v5
 ; CGP-NEXT:    v_mul_f32_e32 v8, 0x5f7ffffc, v8
-; CGP-NEXT:    v_mul_f32_e32 v11, 0x2f800000, v8
-; CGP-NEXT:    v_trunc_f32_e32 v11, v11
-; CGP-NEXT:    v_mac_f32_e32 v8, 0xcf800000, v11
+; CGP-NEXT:    v_mul_f32_e32 v9, 0x2f800000, v8
+; CGP-NEXT:    v_trunc_f32_e32 v9, v9
+; CGP-NEXT:    v_mac_f32_e32 v8, 0xcf800000, v9
 ; CGP-NEXT:    v_cvt_u32_f32_e32 v8, v8
-; CGP-NEXT:    v_cvt_u32_f32_e32 v11, v11
-; CGP-NEXT:    v_subb_u32_e32 v13, vcc, 0, v7, vcc
-; CGP-NEXT:    v_xor_b32_e32 v9, v9, v10
-; CGP-NEXT:    v_mul_lo_u32 v14, v13, v8
-; CGP-NEXT:    v_mul_lo_u32 v15, v12, v11
-; CGP-NEXT:    v_mul_hi_u32 v17, v12, v8
-; CGP-NEXT:    v_mul_lo_u32 v16, v12, v8
-; CGP-NEXT:    v_xor_b32_e32 v3, v3, v10
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v15
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v17
-; CGP-NEXT:    v_mul_lo_u32 v15, v11, v16
-; CGP-NEXT:    v_mul_lo_u32 v17, v8, v14
-; CGP-NEXT:    v_mul_hi_u32 v18, v8, v16
-; CGP-NEXT:    v_mul_hi_u32 v16, v11, v16
-; CGP-NEXT:    v_add_i32_e32 v15, vcc, v15, v17
-; CGP-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v15, vcc, v15, v18
+; CGP-NEXT:    v_cvt_u32_f32_e32 v9, v9
+; CGP-NEXT:    v_mul_lo_u32 v13, v11, v8
+; CGP-NEXT:    v_mul_lo_u32 v12, v10, v9
+; CGP-NEXT:    v_mul_hi_u32 v15, v10, v8
+; CGP-NEXT:    v_mul_lo_u32 v14, v10, v8
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v15
+; CGP-NEXT:    v_mul_lo_u32 v13, v9, v14
+; CGP-NEXT:    v_mul_lo_u32 v15, v8, v12
+; CGP-NEXT:    v_mul_hi_u32 v18, v8, v14
+; CGP-NEXT:    v_add_i32_e32 v17, vcc, v2, v16
+; CGP-NEXT:    v_addc_u32_e32 v3, vcc, v3, v16, vcc
+; CGP-NEXT:    v_add_i32_e32 v13, vcc, v13, v15
+; CGP-NEXT:    v_mul_lo_u32 v19, v9, v12
+; CGP-NEXT:    v_mul_hi_u32 v14, v9, v14
 ; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v18, v11, v14
-; CGP-NEXT:    v_add_i32_e32 v15, vcc, v17, v15
-; CGP-NEXT:    v_mul_hi_u32 v17, v8, v14
-; CGP-NEXT:    v_mul_hi_u32 v14, v11, v14
-; CGP-NEXT:    v_add_i32_e32 v16, vcc, v18, v16
+; CGP-NEXT:    v_add_i32_e32 v13, vcc, v13, v18
+; CGP-NEXT:    v_mul_hi_u32 v18, v8, v12
+; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v13, vcc, v15, v13
+; CGP-NEXT:    v_add_i32_e32 v14, vcc, v19, v14
+; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v18
 ; CGP-NEXT:    v_cndmask_b32_e64 v18, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v16, vcc, v16, v17
-; CGP-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v17, vcc, v18, v17
-; CGP-NEXT:    v_add_i32_e32 v15, vcc, v16, v15
-; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v16, vcc, v17, v16
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v16
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v15
-; CGP-NEXT:    v_addc_u32_e64 v15, s[4:5], v11, v14, vcc
-; CGP-NEXT:    v_mul_lo_u32 v13, v13, v8
-; CGP-NEXT:    v_mul_lo_u32 v16, v12, v15
-; CGP-NEXT:    v_mul_lo_u32 v17, v12, v8
-; CGP-NEXT:    v_mul_hi_u32 v12, v12, v8
+; CGP-NEXT:    v_add_i32_e32 v15, vcc, v15, v18
+; CGP-NEXT:    v_mul_hi_u32 v12, v9, v12
+; CGP-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
+; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v14
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v13
+; CGP-NEXT:    v_addc_u32_e64 v13, s[4:5], v9, v12, vcc
+; CGP-NEXT:    v_mul_lo_u32 v11, v11, v8
+; CGP-NEXT:    v_mul_lo_u32 v14, v10, v13
+; CGP-NEXT:    v_mul_hi_u32 v15, v10, v8
+; CGP-NEXT:    v_mul_lo_u32 v10, v10, v8
+; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v12
 ; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v14
-; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v16
-; CGP-NEXT:    v_mul_hi_u32 v14, v8, v17
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v13, v12
-; CGP-NEXT:    v_mul_lo_u32 v13, v15, v17
-; CGP-NEXT:    v_mul_lo_u32 v16, v8, v12
-; CGP-NEXT:    v_mul_hi_u32 v17, v15, v17
-; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v16
-; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v14
-; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; CGP-NEXT:    v_mul_lo_u32 v14, v15, v12
-; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v16, v13
-; CGP-NEXT:    v_mul_hi_u32 v16, v8, v12
-; CGP-NEXT:    v_mul_hi_u32 v12, v15, v12
-; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v14, v17
-; CGP-NEXT:    v_cndmask_b32_e64 v17, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v14, v16
-; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v16, s[4:5], v17, v16
-; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v14, v13
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v15
+; CGP-NEXT:    v_mul_lo_u32 v14, v13, v10
+; CGP-NEXT:    v_mul_lo_u32 v15, v8, v11
+; CGP-NEXT:    v_mul_hi_u32 v12, v8, v10
+; CGP-NEXT:    v_mul_lo_u32 v18, v13, v11
+; CGP-NEXT:    v_mul_hi_u32 v10, v13, v10
+; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v14, v15
+; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v14, v12
+; CGP-NEXT:    v_mul_hi_u32 v14, v8, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v15, v12
+; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v18, v10
+; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v14
 ; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v16, v14
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v14
-; CGP-NEXT:    v_addc_u32_e32 v11, vcc, v11, v12, vcc
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v13
-; CGP-NEXT:    v_addc_u32_e32 v11, vcc, 0, v11, vcc
-; CGP-NEXT:    v_mul_lo_u32 v12, v3, v8
-; CGP-NEXT:    v_mul_lo_u32 v13, v9, v11
-; CGP-NEXT:    v_mul_hi_u32 v14, v9, v8
+; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v15, v14
+; CGP-NEXT:    v_mul_hi_u32 v11, v13, v11
+; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v12
+; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v14, v12
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
+; CGP-NEXT:    v_addc_u32_e32 v9, vcc, v9, v11, vcc
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; CGP-NEXT:    v_xor_b32_e32 v17, v17, v16
+; CGP-NEXT:    v_xor_b32_e32 v3, v3, v16
+; CGP-NEXT:    v_addc_u32_e32 v9, vcc, 0, v9, vcc
+; CGP-NEXT:    v_mul_lo_u32 v10, v3, v8
+; CGP-NEXT:    v_mul_lo_u32 v11, v17, v9
+; CGP-NEXT:    v_mul_hi_u32 v12, v17, v8
+; CGP-NEXT:    v_mul_lo_u32 v13, v3, v9
 ; CGP-NEXT:    v_mul_hi_u32 v8, v3, v8
-; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
-; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v14
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v14, v3, v11
-; CGP-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
-; CGP-NEXT:    v_mul_hi_u32 v13, v9, v11
-; CGP-NEXT:    v_mul_hi_u32 v11, v3, v11
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, v14, v8
-; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v13
-; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
+; CGP-NEXT:    v_mul_hi_u32 v12, v17, v9
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v13, v8
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
 ; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v12
 ; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
 ; CGP-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
-; CGP-NEXT:    v_mul_lo_u32 v12, v7, v8
-; CGP-NEXT:    v_mul_lo_u32 v13, v5, v11
-; CGP-NEXT:    v_mul_hi_u32 v15, v5, v8
-; CGP-NEXT:    v_mul_lo_u32 v14, v5, v8
-; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
-; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v15
-; CGP-NEXT:    v_sub_i32_e32 v9, vcc, v9, v14
-; CGP-NEXT:    v_subb_u32_e64 v13, s[4:5], v3, v12, vcc
-; CGP-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v12
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v13, v7
+; CGP-NEXT:    v_mul_hi_u32 v9, v3, v9
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
+; CGP-NEXT:    v_mul_lo_u32 v10, v7, v8
+; CGP-NEXT:    v_mul_lo_u32 v11, v5, v9
+; CGP-NEXT:    v_mul_hi_u32 v12, v5, v8
+; CGP-NEXT:    v_mul_lo_u32 v13, v5, v8
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
+; CGP-NEXT:    v_sub_i32_e32 v11, vcc, v17, v13
+; CGP-NEXT:    v_subb_u32_e64 v12, s[4:5], v3, v10, vcc
+; CGP-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v10
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v12, v7
 ; CGP-NEXT:    v_subb_u32_e32 v3, vcc, v3, v7, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v9, v5
-; CGP-NEXT:    v_sub_i32_e32 v9, vcc, v9, v5
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v11, v5
+; CGP-NEXT:    v_sub_i32_e32 v11, vcc, v11, v5
 ; CGP-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], v13, v7
-; CGP-NEXT:    v_add_i32_e32 v13, vcc, 1, v8
-; CGP-NEXT:    v_cndmask_b32_e64 v12, v12, v14, s[4:5]
-; CGP-NEXT:    v_addc_u32_e32 v14, vcc, 0, v11, vcc
+; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], v12, v7
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, 1, v8
+; CGP-NEXT:    v_cndmask_b32_e64 v10, v10, v13, s[4:5]
+; CGP-NEXT:    v_addc_u32_e32 v13, vcc, 0, v9, vcc
 ; CGP-NEXT:    v_cmp_ge_u32_e32 vcc, v3, v7
-; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, -1, vcc
-; CGP-NEXT:    v_cmp_ge_u32_e32 vcc, v9, v5
+; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, -1, vcc
+; CGP-NEXT:    v_cmp_ge_u32_e32 vcc, v11, v5
 ; CGP-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
 ; CGP-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v7
-; CGP-NEXT:    v_cndmask_b32_e32 v3, v15, v5, vcc
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, 1, v13
-; CGP-NEXT:    v_addc_u32_e32 v7, vcc, 0, v14, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v3, v14, v5, vcc
+; CGP-NEXT:    v_add_i32_e32 v5, vcc, 1, v12
+; CGP-NEXT:    v_addc_u32_e32 v7, vcc, 0, v13, vcc
 ; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v3
-; CGP-NEXT:    v_cndmask_b32_e32 v3, v13, v5, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v5, v14, v7, vcc
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v12
+; CGP-NEXT:    v_cndmask_b32_e32 v3, v12, v5, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v5, v13, v7, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
 ; CGP-NEXT:    v_cndmask_b32_e32 v3, v8, v3, vcc
-; CGP-NEXT:    v_xor_b32_e32 v7, v10, v4
-; CGP-NEXT:    v_cndmask_b32_e32 v5, v11, v5, vcc
+; CGP-NEXT:    v_xor_b32_e32 v7, v16, v4
+; CGP-NEXT:    v_cndmask_b32_e32 v5, v9, v5, vcc
 ; CGP-NEXT:    v_xor_b32_e32 v3, v3, v7
 ; CGP-NEXT:    v_xor_b32_e32 v5, v5, v7
 ; CGP-NEXT:    v_sub_i32_e32 v4, vcc, v3, v7
@@ -1058,141 +1058,141 @@
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:    v_cvt_f32_u32_e32 v2, 0x1000
-; CHECK-NEXT:    v_cvt_f32_ubyte0_e32 v4, 0
+; CHECK-NEXT:    v_cvt_f32_ubyte0_e32 v3, 0
 ; CHECK-NEXT:    s_movk_i32 s6, 0xf000
-; CHECK-NEXT:    v_ashrrev_i32_e32 v3, 31, v1
-; CHECK-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v4
+; CHECK-NEXT:    v_ashrrev_i32_e32 v8, 31, v1
+; CHECK-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
 ; CHECK-NEXT:    v_rcp_iflag_f32_e32 v2, v2
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
-; CHECK-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
-; CHECK-NEXT:    v_xor_b32_e32 v0, v0, v3
 ; CHECK-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
-; CHECK-NEXT:    v_mul_f32_e32 v4, 0x2f800000, v2
-; CHECK-NEXT:    v_trunc_f32_e32 v4, v4
-; CHECK-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v4
+; CHECK-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
+; CHECK-NEXT:    v_trunc_f32_e32 v3, v3
+; CHECK-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
 ; CHECK-NEXT:    v_cvt_u32_f32_e32 v2, v2
-; CHECK-NEXT:    v_cvt_u32_f32_e32 v4, v4
-; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v3
+; CHECK-NEXT:    v_cvt_u32_f32_e32 v3, v3
 ; CHECK-NEXT:    v_mul_lo_u32 v5, -1, v2
-; CHECK-NEXT:    v_mul_lo_u32 v6, s6, v4
-; CHECK-NEXT:    v_mul_hi_u32 v8, s6, v2
-; CHECK-NEXT:    v_mul_lo_u32 v7, s6, v2
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
-; CHECK-NEXT:    v_mul_lo_u32 v6, v4, v7
-; CHECK-NEXT:    v_mul_lo_u32 v8, v2, v5
-; CHECK-NEXT:    v_mul_hi_u32 v9, v2, v7
-; CHECK-NEXT:    v_mul_hi_u32 v7, v4, v7
-; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
-; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CHECK-NEXT:    v_mul_lo_u32 v4, s6, v3
+; CHECK-NEXT:    v_mul_hi_u32 v7, s6, v2
+; CHECK-NEXT:    v_mul_lo_u32 v6, s6, v2
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; CHECK-NEXT:    v_mul_lo_u32 v5, v3, v6
+; CHECK-NEXT:    v_mul_lo_u32 v7, v2, v4
+; CHECK-NEXT:    v_mul_hi_u32 v9, v2, v6
+; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v8
+; CHECK-NEXT:    v_addc_u32_e32 v1, vcc, v1, v8, vcc
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; CHECK-NEXT:    v_mul_lo_u32 v10, v3, v4
+; CHECK-NEXT:    v_mul_hi_u32 v6, v3, v6
+; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v9
+; CHECK-NEXT:    v_mul_hi_u32 v9, v2, v4
+; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
+; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v10, v6
+; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
-; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v9, v4, v5
-; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
-; CHECK-NEXT:    v_mul_hi_u32 v8, v2, v5
-; CHECK-NEXT:    v_mul_hi_u32 v5, v4, v5
-; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v9, v7
 ; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; CHECK-NEXT:    v_mul_hi_u32 v4, v3, v4
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
+; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
-; CHECK-NEXT:    v_addc_u32_e64 v6, s[4:5], v4, v5, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v7, -1, v2
-; CHECK-NEXT:    v_mul_lo_u32 v8, s6, v6
-; CHECK-NEXT:    v_mul_hi_u32 v10, s6, v2
-; CHECK-NEXT:    v_mul_lo_u32 v9, s6, v2
-; CHECK-NEXT:    v_add_i32_e64 v4, s[4:5], v4, v5
-; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v8
-; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v10
-; CHECK-NEXT:    v_mul_lo_u32 v8, v6, v9
-; CHECK-NEXT:    v_mul_lo_u32 v10, v2, v7
-; CHECK-NEXT:    v_mul_hi_u32 v5, v2, v9
-; CHECK-NEXT:    v_mul_hi_u32 v9, v6, v9
-; CHECK-NEXT:    s_movk_i32 s6, 0x1000
-; CHECK-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v10
-; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v5, s[4:5], v8, v5
-; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, s[4:5]
-; CHECK-NEXT:    v_mul_lo_u32 v8, v6, v7
-; CHECK-NEXT:    v_add_i32_e64 v5, s[4:5], v10, v5
-; CHECK-NEXT:    v_mul_hi_u32 v10, v2, v7
-; CHECK-NEXT:    v_mul_hi_u32 v6, v6, v7
-; CHECK-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; CHECK-NEXT:    v_addc_u32_e64 v5, s[4:5], v3, v4, vcc
+; CHECK-NEXT:    v_mul_lo_u32 v6, -1, v2
+; CHECK-NEXT:    v_mul_lo_u32 v7, s6, v5
+; CHECK-NEXT:    v_mul_hi_u32 v9, s6, v2
+; CHECK-NEXT:    v_mul_lo_u32 v10, s6, v2
+; CHECK-NEXT:    v_add_i32_e64 v3, s[4:5], v3, v4
+; CHECK-NEXT:    v_add_i32_e64 v6, s[4:5], v6, v7
+; CHECK-NEXT:    v_add_i32_e64 v6, s[4:5], v6, v9
+; CHECK-NEXT:    v_mul_lo_u32 v7, v5, v10
+; CHECK-NEXT:    v_mul_lo_u32 v9, v2, v6
+; CHECK-NEXT:    v_mul_hi_u32 v4, v2, v10
+; CHECK-NEXT:    v_mul_lo_u32 v11, v5, v6
+; CHECK-NEXT:    v_mul_hi_u32 v10, v5, v10
+; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v9
 ; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v10
+; CHECK-NEXT:    v_add_i32_e64 v4, s[4:5], v7, v4
+; CHECK-NEXT:    v_mul_hi_u32 v7, v2, v6
+; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v4, s[4:5], v9, v4
+; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v10
 ; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v10
-; CHECK-NEXT:    v_add_i32_e64 v5, s[4:5], v8, v5
-; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v9, v8
-; CHECK-NEXT:    v_add_i32_e64 v6, s[4:5], v6, v7
-; CHECK-NEXT:    v_addc_u32_e32 v4, vcc, v4, v6, vcc
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
-; CHECK-NEXT:    v_addc_u32_e32 v4, vcc, 0, v4, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v5, v1, v2
-; CHECK-NEXT:    v_mul_lo_u32 v6, v0, v4
-; CHECK-NEXT:    v_mul_hi_u32 v7, v0, v2
+; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v9, v7
+; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v10, v9
+; CHECK-NEXT:    v_mul_hi_u32 v5, v5, v6
+; CHECK-NEXT:    v_add_i32_e64 v4, s[4:5], v7, v4
+; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v6, s[4:5], v9, v6
+; CHECK-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v6
+; CHECK-NEXT:    v_addc_u32_e32 v3, vcc, v3, v5, vcc
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
+; CHECK-NEXT:    v_xor_b32_e32 v0, v0, v8
+; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v8
+; CHECK-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; CHECK-NEXT:    v_mul_lo_u32 v4, v1, v2
+; CHECK-NEXT:    v_mul_lo_u32 v5, v0, v3
+; CHECK-NEXT:    v_mul_hi_u32 v6, v0, v2
+; CHECK-NEXT:    v_mul_lo_u32 v7, v1, v3
 ; CHECK-NEXT:    v_mul_hi_u32 v2, v1, v2
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
-; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
 ; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v7, v1, v4
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; CHECK-NEXT:    v_mul_hi_u32 v6, v0, v4
-; CHECK-NEXT:    v_mul_hi_u32 v4, v1, v4
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; CHECK-NEXT:    v_mul_hi_u32 v6, v0, v3
+; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v7, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
 ; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
-; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
-; CHECK-NEXT:    v_mul_lo_u32 v5, 0, v2
-; CHECK-NEXT:    v_mul_lo_u32 v6, s6, v4
-; CHECK-NEXT:    v_mul_hi_u32 v8, s6, v2
-; CHECK-NEXT:    v_mul_lo_u32 v7, s6, v2
 ; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
+; CHECK-NEXT:    v_mul_hi_u32 v3, v1, v3
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
+; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; CHECK-NEXT:    s_movk_i32 s6, 0x1000
+; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v3, v4
+; CHECK-NEXT:    v_mul_lo_u32 v4, 0, v2
+; CHECK-NEXT:    v_mul_lo_u32 v5, s6, v3
+; CHECK-NEXT:    v_mul_hi_u32 v6, s6, v2
+; CHECK-NEXT:    v_mul_lo_u32 v7, s6, v2
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
 ; CHECK-NEXT:    v_sub_i32_e32 v0, vcc, v0, v7
-; CHECK-NEXT:    v_subb_u32_e64 v6, s[4:5], v1, v5, vcc
-; CHECK-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v5
-; CHECK-NEXT:    v_cmp_le_u32_e64 s[4:5], 0, v6
+; CHECK-NEXT:    v_subb_u32_e64 v5, s[4:5], v1, v4, vcc
+; CHECK-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v4
+; CHECK-NEXT:    v_cmp_le_u32_e64 s[4:5], 0, v5
 ; CHECK-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[4:5]
+; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[4:5]
 ; CHECK-NEXT:    v_cmp_le_u32_e64 s[4:5], s6, v0
 ; CHECK-NEXT:    v_subrev_i32_e32 v0, vcc, s6, v0
 ; CHECK-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
-; CHECK-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v6
-; CHECK-NEXT:    v_add_i32_e32 v6, vcc, 1, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v5, v5, v7, s[4:5]
-; CHECK-NEXT:    v_addc_u32_e32 v7, vcc, 0, v4, vcc
+; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[4:5]
+; CHECK-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v5
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, 1, v2
+; CHECK-NEXT:    v_cndmask_b32_e64 v4, v4, v6, s[4:5]
+; CHECK-NEXT:    v_addc_u32_e32 v6, vcc, 0, v3, vcc
 ; CHECK-NEXT:    v_cmp_le_u32_e32 vcc, 0, v1
-; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
+; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
 ; CHECK-NEXT:    v_cmp_le_u32_e32 vcc, s6, v0
 ; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
 ; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
-; CHECK-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc
-; CHECK-NEXT:    v_add_i32_e32 v1, vcc, 1, v6
-; CHECK-NEXT:    v_addc_u32_e32 v8, vcc, 0, v7, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc
+; CHECK-NEXT:    v_add_i32_e32 v1, vcc, 1, v5
+; CHECK-NEXT:    v_addc_u32_e32 v7, vcc, 0, v6, vcc
 ; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
-; CHECK-NEXT:    v_cndmask_b32_e32 v0, v6, v1, vcc
-; CHECK-NEXT:    v_cndmask_b32_e32 v1, v7, v8, vcc
-; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
+; CHECK-NEXT:    v_cndmask_b32_e32 v0, v5, v1, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v1, v6, v7, vcc
+; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
 ; CHECK-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
-; CHECK-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc
-; CHECK-NEXT:    v_xor_b32_e32 v0, v0, v3
-; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v3
-; CHECK-NEXT:    v_sub_i32_e32 v0, vcc, v0, v3
-; CHECK-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
+; CHECK-NEXT:    v_xor_b32_e32 v0, v0, v8
+; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v8
+; CHECK-NEXT:    v_sub_i32_e32 v0, vcc, v0, v8
+; CHECK-NEXT:    v_subb_u32_e32 v1, vcc, v1, v8, vcc
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %result = sdiv i64 %num, 4096
   ret i64 %result
@@ -1220,557 +1220,557 @@
 ; GISEL-NEXT:    v_rcp_iflag_f32_e32 v4, v4
 ; GISEL-NEXT:    s_cmp_lg_u32 s4, 0
 ; GISEL-NEXT:    s_subb_u32 s12, 0, s9
-; GISEL-NEXT:    v_ashrrev_i32_e32 v6, 31, v1
+; GISEL-NEXT:    v_ashrrev_i32_e32 v10, 31, v1
 ; GISEL-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
 ; GISEL-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
 ; GISEL-NEXT:    v_trunc_f32_e32 v5, v5
 ; GISEL-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v4, v4
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v5, v5
-; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v6
-; GISEL-NEXT:    v_addc_u32_e32 v1, vcc, v1, v6, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v7, s12, v4
-; GISEL-NEXT:    v_mul_lo_u32 v8, s11, v5
-; GISEL-NEXT:    v_mul_hi_u32 v10, s11, v4
+; GISEL-NEXT:    v_mul_lo_u32 v6, s12, v4
+; GISEL-NEXT:    v_mul_lo_u32 v7, s11, v5
+; GISEL-NEXT:    v_mul_hi_u32 v8, s11, v4
 ; GISEL-NEXT:    v_mul_lo_u32 v9, s11, v4
-; GISEL-NEXT:    v_xor_b32_e32 v0, v0, v6
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
-; GISEL-NEXT:    v_mul_lo_u32 v8, v5, v9
-; GISEL-NEXT:    v_mul_lo_u32 v10, v4, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; GISEL-NEXT:    v_mul_lo_u32 v7, v5, v9
+; GISEL-NEXT:    v_mul_lo_u32 v8, v4, v6
 ; GISEL-NEXT:    v_mul_hi_u32 v11, v4, v9
+; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v10
+; GISEL-NEXT:    v_addc_u32_e32 v1, vcc, v1, v10, vcc
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; GISEL-NEXT:    v_mul_lo_u32 v12, v5, v6
 ; GISEL-NEXT:    v_mul_hi_u32 v9, v5, v9
-; GISEL-NEXT:    v_xor_b32_e32 v1, v1, v6
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v11, v5, v7
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
-; GISEL-NEXT:    v_mul_hi_u32 v10, v4, v7
-; GISEL-NEXT:    v_mul_hi_u32 v7, v5, v7
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v11, v9
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v11
+; GISEL-NEXT:    v_mul_hi_u32 v11, v4, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v12, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
 ; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; GISEL-NEXT:    v_mul_hi_u32 v6, v5, v6
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
-; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
-; GISEL-NEXT:    v_addc_u32_e64 v8, s[4:5], v5, v7, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v9, s12, v4
-; GISEL-NEXT:    v_mul_lo_u32 v10, s11, v8
-; GISEL-NEXT:    v_mul_hi_u32 v12, s11, v4
-; GISEL-NEXT:    v_mul_lo_u32 v11, s11, v4
-; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v7
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v10
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v12
-; GISEL-NEXT:    v_mul_lo_u32 v10, v8, v11
-; GISEL-NEXT:    v_mul_lo_u32 v12, v4, v9
-; GISEL-NEXT:    v_mul_hi_u32 v7, v4, v11
-; GISEL-NEXT:    v_mul_hi_u32 v11, v8, v11
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v12
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v10, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, s[4:5]
-; GISEL-NEXT:    v_mul_lo_u32 v10, v8, v9
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v12, v7
-; GISEL-NEXT:    v_mul_hi_u32 v12, v4, v9
-; GISEL-NEXT:    v_mul_hi_u32 v8, v8, v9
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v11
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; GISEL-NEXT:    v_addc_u32_e64 v7, s[4:5], v5, v6, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v8, s12, v4
+; GISEL-NEXT:    v_mul_lo_u32 v9, s11, v7
+; GISEL-NEXT:    v_mul_hi_u32 v11, s11, v4
+; GISEL-NEXT:    v_mul_lo_u32 v12, s11, v4
+; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v6
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v11
+; GISEL-NEXT:    v_mul_lo_u32 v9, v7, v12
+; GISEL-NEXT:    v_mul_lo_u32 v11, v4, v8
+; GISEL-NEXT:    v_mul_hi_u32 v6, v4, v12
+; GISEL-NEXT:    v_mul_lo_u32 v13, v7, v8
+; GISEL-NEXT:    v_mul_hi_u32 v12, v7, v12
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v11
 ; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v12
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v9, v6
+; GISEL-NEXT:    v_mul_hi_u32 v9, v4, v8
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v11, v6
+; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v13, v12
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v10, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v10
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
-; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v8, vcc
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v12, v11
+; GISEL-NEXT:    v_mul_hi_u32 v7, v7, v8
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v9, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v11, v8
+; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v8
+; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v7, vcc
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; GISEL-NEXT:    v_xor_b32_e32 v0, v0, v10
+; GISEL-NEXT:    v_xor_b32_e32 v1, v1, v10
 ; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v7, v1, v4
-; GISEL-NEXT:    v_mul_lo_u32 v8, v0, v5
-; GISEL-NEXT:    v_mul_hi_u32 v10, v0, v4
+; GISEL-NEXT:    v_mul_lo_u32 v6, v1, v4
+; GISEL-NEXT:    v_mul_lo_u32 v7, v0, v5
+; GISEL-NEXT:    v_mul_hi_u32 v8, v0, v4
+; GISEL-NEXT:    v_mul_lo_u32 v9, v1, v5
 ; GISEL-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GISEL-NEXT:    v_mov_b32_e32 v9, s9
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
 ; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v10, v1, v5
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
 ; GISEL-NEXT:    v_mul_hi_u32 v8, v0, v5
-; GISEL-NEXT:    v_mul_hi_u32 v5, v1, v5
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v10, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v9, v4
+; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; GISEL-NEXT:    v_mul_lo_u32 v7, s9, v4
-; GISEL-NEXT:    v_mul_lo_u32 v8, s8, v5
-; GISEL-NEXT:    v_mul_hi_u32 v11, s8, v4
-; GISEL-NEXT:    v_mul_lo_u32 v10, s8, v4
 ; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v11
-; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v10
-; GISEL-NEXT:    v_subb_u32_e64 v8, s[4:5], v1, v7, vcc
-; GISEL-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v7
-; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s9, v8
-; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v9, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
+; GISEL-NEXT:    v_mul_hi_u32 v5, v1, v5
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
+; GISEL-NEXT:    v_mul_lo_u32 v6, s9, v4
+; GISEL-NEXT:    v_mul_lo_u32 v7, s8, v5
+; GISEL-NEXT:    v_mul_hi_u32 v8, s8, v4
+; GISEL-NEXT:    v_mul_lo_u32 v9, s8, v4
+; GISEL-NEXT:    v_mov_b32_e32 v11, s9
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v9
+; GISEL-NEXT:    v_subb_u32_e64 v7, s[4:5], v1, v6, vcc
+; GISEL-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v6
+; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s9, v7
+; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v11, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[4:5]
 ; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s8, v0
 ; GISEL-NEXT:    v_subrev_i32_e32 v0, vcc, s8, v0
 ; GISEL-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], s9, v8
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, 1, v4
-; GISEL-NEXT:    v_addc_u32_e32 v9, vcc, 0, v5, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], s9, v7
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, 1, v4
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, v6, v8, s[4:5]
+; GISEL-NEXT:    v_addc_u32_e32 v8, vcc, 0, v5, vcc
 ; GISEL-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, v7, v10, s[4:5]
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, -1, vcc
-; GISEL-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
 ; GISEL-NEXT:    s_add_u32 s4, s10, 0
 ; GISEL-NEXT:    s_cselect_b32 s5, 1, 0
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
+; GISEL-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
+; GISEL-NEXT:    s_and_b32 s5, s5, 1
 ; GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
 ; GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v1
-; GISEL-NEXT:    s_and_b32 s5, s5, 1
-; GISEL-NEXT:    v_cndmask_b32_e32 v0, v10, v0, vcc
-; GISEL-NEXT:    v_add_i32_e32 v1, vcc, 1, v8
 ; GISEL-NEXT:    s_cmp_lg_u32 s5, 0
-; GISEL-NEXT:    v_addc_u32_e32 v10, vcc, 0, v9, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
+; GISEL-NEXT:    v_cndmask_b32_e32 v0, v9, v0, vcc
+; GISEL-NEXT:    v_add_i32_e32 v1, vcc, 1, v7
+; GISEL-NEXT:    v_addc_u32_e32 v9, vcc, 0, v8, vcc
 ; GISEL-NEXT:    s_addc_u32 s5, 0, 0
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
 ; GISEL-NEXT:    s_xor_b64 s[6:7], s[4:5], s[6:7]
-; GISEL-NEXT:    v_cndmask_b32_e32 v0, v8, v1, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v1, v9, v10, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
+; GISEL-NEXT:    v_cndmask_b32_e32 v0, v7, v1, vcc
+; GISEL-NEXT:    v_cvt_f32_u32_e32 v1, s6
+; GISEL-NEXT:    v_cvt_f32_u32_e32 v7, s7
+; GISEL-NEXT:    v_cndmask_b32_e32 v8, v8, v9, vcc
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
 ; GISEL-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc
-; GISEL-NEXT:    v_cvt_f32_u32_e32 v4, s6
-; GISEL-NEXT:    v_cvt_f32_u32_e32 v5, s7
+; GISEL-NEXT:    v_mac_f32_e32 v1, 0x4f800000, v7
+; GISEL-NEXT:    v_rcp_iflag_f32_e32 v1, v1
+; GISEL-NEXT:    v_cndmask_b32_e32 v4, v5, v8, vcc
 ; GISEL-NEXT:    s_sub_u32 s8, 0, s6
 ; GISEL-NEXT:    s_cselect_b32 s4, 1, 0
+; GISEL-NEXT:    v_mul_f32_e32 v1, 0x5f7ffffc, v1
+; GISEL-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v1
+; GISEL-NEXT:    v_trunc_f32_e32 v5, v5
+; GISEL-NEXT:    v_mac_f32_e32 v1, 0xcf800000, v5
+; GISEL-NEXT:    v_cvt_u32_f32_e32 v1, v1
+; GISEL-NEXT:    v_cvt_u32_f32_e32 v5, v5
 ; GISEL-NEXT:    s_and_b32 s4, s4, 1
-; GISEL-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
-; GISEL-NEXT:    v_rcp_iflag_f32_e32 v4, v4
 ; GISEL-NEXT:    s_cmp_lg_u32 s4, 0
 ; GISEL-NEXT:    s_subb_u32 s9, 0, s7
-; GISEL-NEXT:    v_xor_b32_e32 v0, v0, v6
-; GISEL-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
-; GISEL-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
-; GISEL-NEXT:    v_trunc_f32_e32 v5, v5
-; GISEL-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
-; GISEL-NEXT:    v_cvt_u32_f32_e32 v4, v4
-; GISEL-NEXT:    v_cvt_u32_f32_e32 v5, v5
-; GISEL-NEXT:    v_xor_b32_e32 v1, v1, v6
-; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v6
-; GISEL-NEXT:    v_mul_lo_u32 v7, s9, v4
-; GISEL-NEXT:    v_mul_lo_u32 v8, s8, v5
-; GISEL-NEXT:    v_mul_hi_u32 v10, s8, v4
-; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v6, vcc
-; GISEL-NEXT:    v_ashrrev_i32_e32 v6, 31, v3
-; GISEL-NEXT:    v_mul_lo_u32 v9, s8, v4
-; GISEL-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
-; GISEL-NEXT:    v_addc_u32_e32 v3, vcc, v3, v6, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v6, s9, v1
+; GISEL-NEXT:    v_mul_lo_u32 v7, s8, v5
+; GISEL-NEXT:    v_mul_hi_u32 v8, s8, v1
+; GISEL-NEXT:    v_mul_lo_u32 v9, s8, v1
+; GISEL-NEXT:    v_ashrrev_i32_e32 v11, 31, v3
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; GISEL-NEXT:    v_mul_lo_u32 v7, v5, v9
+; GISEL-NEXT:    v_mul_lo_u32 v8, v1, v6
+; GISEL-NEXT:    v_mul_hi_u32 v12, v1, v9
+; GISEL-NEXT:    v_add_i32_e32 v2, vcc, v2, v11
+; GISEL-NEXT:    v_addc_u32_e32 v3, vcc, v3, v11, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
-; GISEL-NEXT:    v_mul_lo_u32 v8, v5, v9
-; GISEL-NEXT:    v_mul_lo_u32 v10, v4, v7
-; GISEL-NEXT:    v_mul_hi_u32 v11, v4, v9
+; GISEL-NEXT:    v_mul_lo_u32 v13, v5, v6
 ; GISEL-NEXT:    v_mul_hi_u32 v9, v5, v9
-; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v6
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v11, v5, v7
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
-; GISEL-NEXT:    v_mul_hi_u32 v10, v4, v7
-; GISEL-NEXT:    v_mul_hi_u32 v7, v5, v7
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v11, v9
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v12
+; GISEL-NEXT:    v_mul_hi_u32 v12, v1, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v13, v9
 ; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
-; GISEL-NEXT:    v_addc_u32_e64 v8, s[4:5], v5, v7, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v9, s9, v4
-; GISEL-NEXT:    v_mul_lo_u32 v10, s8, v8
-; GISEL-NEXT:    v_mul_hi_u32 v12, s8, v4
-; GISEL-NEXT:    v_mul_lo_u32 v11, s8, v4
-; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v7
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v10
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v12
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
+; GISEL-NEXT:    v_mul_hi_u32 v6, v5, v6
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; GISEL-NEXT:    v_add_i32_e32 v1, vcc, v1, v7
+; GISEL-NEXT:    v_addc_u32_e64 v7, s[4:5], v5, v6, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v8, s9, v1
+; GISEL-NEXT:    v_mul_lo_u32 v9, s8, v7
+; GISEL-NEXT:    v_mul_hi_u32 v12, s8, v1
+; GISEL-NEXT:    v_mul_lo_u32 v13, s8, v1
+; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v6
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v12
+; GISEL-NEXT:    v_mul_lo_u32 v9, v7, v13
+; GISEL-NEXT:    v_mul_lo_u32 v12, v1, v8
+; GISEL-NEXT:    v_mul_hi_u32 v6, v1, v13
+; GISEL-NEXT:    v_mul_lo_u32 v14, v7, v8
+; GISEL-NEXT:    v_mul_hi_u32 v13, v7, v13
 ; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v12
-; GISEL-NEXT:    v_mul_lo_u32 v10, v8, v11
-; GISEL-NEXT:    v_mul_lo_u32 v12, v4, v9
-; GISEL-NEXT:    v_mul_hi_u32 v7, v4, v11
-; GISEL-NEXT:    v_mul_hi_u32 v11, v8, v11
-; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v6
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v12
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v10, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, s[4:5]
-; GISEL-NEXT:    v_mul_lo_u32 v10, v8, v9
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v12, v7
-; GISEL-NEXT:    v_mul_hi_u32 v12, v4, v9
-; GISEL-NEXT:    v_mul_hi_u32 v8, v8, v9
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v11
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v12
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v9, v6
+; GISEL-NEXT:    v_mul_hi_u32 v9, v1, v8
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v12, v6
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v14, v13
+; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v12, v9
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v10, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v10
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
-; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v8, vcc
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v13, v12
+; GISEL-NEXT:    v_mul_hi_u32 v7, v7, v8
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v9, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v12, v8
+; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v8
+; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v7, vcc
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v1, v6
+; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v11
 ; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v7, v3, v4
+; GISEL-NEXT:    v_xor_b32_e32 v0, v0, v10
+; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v11
+; GISEL-NEXT:    v_xor_b32_e32 v4, v4, v10
+; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v10
+; GISEL-NEXT:    v_mul_lo_u32 v7, v3, v6
 ; GISEL-NEXT:    v_mul_lo_u32 v8, v2, v5
-; GISEL-NEXT:    v_mul_hi_u32 v10, v2, v4
-; GISEL-NEXT:    v_mul_hi_u32 v4, v3, v4
-; GISEL-NEXT:    v_mov_b32_e32 v9, s7
+; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v4, v10, vcc
+; GISEL-NEXT:    v_mul_hi_u32 v4, v2, v6
+; GISEL-NEXT:    v_mul_lo_u32 v9, v3, v5
 ; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; GISEL-NEXT:    v_mul_hi_u32 v6, v3, v6
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v10, v3, v5
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; GISEL-NEXT:    v_mul_hi_u32 v8, v2, v5
-; GISEL-NEXT:    v_mul_hi_u32 v5, v3, v5
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v10, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
+; GISEL-NEXT:    v_mul_hi_u32 v7, v2, v5
+; GISEL-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v8, v4
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v9, v6
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
 ; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; GISEL-NEXT:    v_mul_lo_u32 v7, s7, v4
-; GISEL-NEXT:    v_mul_lo_u32 v8, s6, v5
-; GISEL-NEXT:    v_mul_hi_u32 v11, s6, v4
-; GISEL-NEXT:    v_mul_lo_u32 v10, s6, v4
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v11
-; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v10
-; GISEL-NEXT:    v_subb_u32_e64 v8, s[4:5], v3, v7, vcc
-; GISEL-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v7
-; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s7, v8
-; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v9, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
+; GISEL-NEXT:    v_mul_hi_u32 v5, v3, v5
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
+; GISEL-NEXT:    v_mul_lo_u32 v6, s7, v4
+; GISEL-NEXT:    v_mul_lo_u32 v7, s6, v5
+; GISEL-NEXT:    v_mul_hi_u32 v8, s6, v4
+; GISEL-NEXT:    v_mul_lo_u32 v9, s6, v4
+; GISEL-NEXT:    v_mov_b32_e32 v10, s7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v9
+; GISEL-NEXT:    v_subb_u32_e64 v7, s[4:5], v3, v6, vcc
+; GISEL-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v6
+; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s7, v7
+; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v10, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[4:5]
 ; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s6, v2
 ; GISEL-NEXT:    v_subrev_i32_e32 v2, vcc, s6, v2
 ; GISEL-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], s7, v8
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, 1, v4
-; GISEL-NEXT:    v_addc_u32_e32 v9, vcc, 0, v5, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], s7, v7
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, 1, v4
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, v6, v8, s[4:5]
+; GISEL-NEXT:    v_addc_u32_e32 v8, vcc, 0, v5, vcc
 ; GISEL-NEXT:    v_cmp_le_u32_e32 vcc, s7, v3
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, v7, v10, s[4:5]
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, -1, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
 ; GISEL-NEXT:    v_cmp_le_u32_e32 vcc, s6, v2
 ; GISEL-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
 ; GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, s7, v3
-; GISEL-NEXT:    v_cndmask_b32_e32 v2, v10, v2, vcc
-; GISEL-NEXT:    v_add_i32_e32 v3, vcc, 1, v8
-; GISEL-NEXT:    v_addc_u32_e32 v10, vcc, 0, v9, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v2, v9, v2, vcc
+; GISEL-NEXT:    v_add_i32_e32 v3, vcc, 1, v7
+; GISEL-NEXT:    v_addc_u32_e32 v9, vcc, 0, v8, vcc
 ; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
-; GISEL-NEXT:    v_cndmask_b32_e32 v2, v8, v3, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v3, v9, v10, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
+; GISEL-NEXT:    v_cndmask_b32_e32 v2, v7, v3, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v3, v8, v9, vcc
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
 ; GISEL-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
 ; GISEL-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc
-; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v6
-; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v6
-; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v6
-; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v6, vcc
+; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v11
+; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v11
+; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v11
+; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v11, vcc
 ; GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; CGP-LABEL: v_sdiv_v2i64_pow2k_denom:
 ; CGP:       ; %bb.0:
 ; CGP-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CGP-NEXT:    v_cvt_f32_u32_e32 v4, 0x1000
-; CGP-NEXT:    v_cvt_f32_ubyte0_e32 v6, 0
+; CGP-NEXT:    v_cvt_f32_ubyte0_e32 v5, 0
 ; CGP-NEXT:    s_movk_i32 s6, 0xf000
-; CGP-NEXT:    v_ashrrev_i32_e32 v5, 31, v1
-; CGP-NEXT:    v_mov_b32_e32 v7, v4
-; CGP-NEXT:    v_mac_f32_e32 v7, 0x4f800000, v6
-; CGP-NEXT:    v_rcp_iflag_f32_e32 v7, v7
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v5
-; CGP-NEXT:    v_addc_u32_e32 v1, vcc, v1, v5, vcc
-; CGP-NEXT:    v_xor_b32_e32 v0, v0, v5
-; CGP-NEXT:    v_mul_f32_e32 v7, 0x5f7ffffc, v7
-; CGP-NEXT:    v_mul_f32_e32 v8, 0x2f800000, v7
-; CGP-NEXT:    v_trunc_f32_e32 v8, v8
-; CGP-NEXT:    v_mac_f32_e32 v7, 0xcf800000, v8
-; CGP-NEXT:    v_cvt_u32_f32_e32 v7, v7
-; CGP-NEXT:    v_cvt_u32_f32_e32 v8, v8
-; CGP-NEXT:    v_xor_b32_e32 v1, v1, v5
+; CGP-NEXT:    v_ashrrev_i32_e32 v12, 31, v1
+; CGP-NEXT:    v_mov_b32_e32 v6, v4
+; CGP-NEXT:    v_mac_f32_e32 v6, 0x4f800000, v5
+; CGP-NEXT:    v_rcp_iflag_f32_e32 v6, v6
 ; CGP-NEXT:    s_movk_i32 s7, 0x1000
-; CGP-NEXT:    v_mul_lo_u32 v9, -1, v7
-; CGP-NEXT:    v_mul_lo_u32 v10, s6, v8
-; CGP-NEXT:    v_mul_hi_u32 v12, s6, v7
-; CGP-NEXT:    v_mul_lo_u32 v11, s6, v7
-; CGP-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v6
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
-; CGP-NEXT:    v_mul_lo_u32 v10, v8, v11
-; CGP-NEXT:    v_mul_lo_u32 v12, v7, v9
-; CGP-NEXT:    v_mul_hi_u32 v13, v7, v11
-; CGP-NEXT:    v_mul_hi_u32 v11, v8, v11
+; CGP-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
 ; CGP-NEXT:    v_rcp_iflag_f32_e32 v4, v4
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v13
-; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v13, v8, v9
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v12, v10
-; CGP-NEXT:    v_mul_hi_u32 v12, v7, v9
-; CGP-NEXT:    v_mul_hi_u32 v9, v8, v9
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v13, v11
-; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
-; CGP-NEXT:    v_addc_u32_e64 v10, s[4:5], v8, v9, vcc
-; CGP-NEXT:    v_mul_lo_u32 v11, -1, v7
-; CGP-NEXT:    v_mul_lo_u32 v12, s6, v10
-; CGP-NEXT:    v_mul_hi_u32 v14, s6, v7
-; CGP-NEXT:    v_mul_lo_u32 v13, s6, v7
-; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
-; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
-; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v14
-; CGP-NEXT:    v_mul_lo_u32 v12, v10, v13
-; CGP-NEXT:    v_mul_lo_u32 v14, v7, v11
-; CGP-NEXT:    v_mul_hi_u32 v9, v7, v13
-; CGP-NEXT:    v_mul_hi_u32 v13, v10, v13
+; CGP-NEXT:    v_mul_f32_e32 v6, 0x5f7ffffc, v6
+; CGP-NEXT:    v_mul_f32_e32 v7, 0x2f800000, v6
+; CGP-NEXT:    v_trunc_f32_e32 v7, v7
+; CGP-NEXT:    v_mac_f32_e32 v6, 0xcf800000, v7
+; CGP-NEXT:    v_cvt_u32_f32_e32 v6, v6
+; CGP-NEXT:    v_cvt_u32_f32_e32 v7, v7
 ; CGP-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v14
-; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v12, v9
-; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
-; CGP-NEXT:    v_mul_lo_u32 v12, v10, v11
-; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v14, v9
-; CGP-NEXT:    v_mul_hi_u32 v14, v7, v11
-; CGP-NEXT:    v_mul_hi_u32 v10, v10, v11
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v13
-; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v14
-; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v14
-; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v12, v9
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v13, v12
-; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v11
-; CGP-NEXT:    v_addc_u32_e32 v8, vcc, v8, v10, vcc
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
-; CGP-NEXT:    v_addc_u32_e32 v8, vcc, 0, v8, vcc
-; CGP-NEXT:    v_mul_lo_u32 v9, v1, v7
-; CGP-NEXT:    v_mul_lo_u32 v10, v0, v8
-; CGP-NEXT:    v_mul_hi_u32 v11, v0, v7
-; CGP-NEXT:    v_mul_hi_u32 v7, v1, v7
-; CGP-NEXT:    v_ashrrev_i32_e32 v6, 31, v3
+; CGP-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
+; CGP-NEXT:    v_mul_lo_u32 v9, -1, v6
+; CGP-NEXT:    v_mul_lo_u32 v8, s6, v7
+; CGP-NEXT:    v_mul_hi_u32 v10, s6, v6
+; CGP-NEXT:    v_mul_lo_u32 v11, s6, v6
+; CGP-NEXT:    v_trunc_f32_e32 v5, v5
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; CGP-NEXT:    v_mul_lo_u32 v9, v7, v11
+; CGP-NEXT:    v_mul_lo_u32 v10, v6, v8
+; CGP-NEXT:    v_mul_hi_u32 v13, v6, v11
+; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v12
+; CGP-NEXT:    v_addc_u32_e32 v1, vcc, v1, v12, vcc
 ; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
+; CGP-NEXT:    v_mul_lo_u32 v14, v7, v8
+; CGP-NEXT:    v_mul_hi_u32 v11, v7, v11
 ; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v13
+; CGP-NEXT:    v_mul_hi_u32 v13, v6, v8
 ; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v11, v1, v8
 ; CGP-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
-; CGP-NEXT:    v_mul_hi_u32 v10, v0, v8
-; CGP-NEXT:    v_mul_hi_u32 v8, v1, v8
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v11, v7
-; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
-; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
-; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
-; CGP-NEXT:    v_mul_lo_u32 v9, 0, v7
-; CGP-NEXT:    v_mul_lo_u32 v10, s7, v8
-; CGP-NEXT:    v_mul_hi_u32 v12, s7, v7
-; CGP-NEXT:    v_mul_lo_u32 v11, s7, v7
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
-; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v0, v11
-; CGP-NEXT:    v_subb_u32_e64 v10, s[4:5], v1, v9, vcc
-; CGP-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v9
-; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], 0, v10
-; CGP-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], s7, v0
-; CGP-NEXT:    v_subrev_i32_e32 v0, vcc, s7, v0
-; CGP-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v10
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, 1, v7
-; CGP-NEXT:    v_cndmask_b32_e64 v9, v9, v11, s[4:5]
-; CGP-NEXT:    v_addc_u32_e32 v11, vcc, 0, v8, vcc
-; CGP-NEXT:    v_cmp_le_u32_e32 vcc, 0, v1
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, -1, vcc
-; CGP-NEXT:    v_cmp_le_u32_e32 vcc, s7, v0
-; CGP-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
-; CGP-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
-; CGP-NEXT:    v_cndmask_b32_e32 v0, v12, v0, vcc
-; CGP-NEXT:    v_add_i32_e32 v1, vcc, 1, v10
-; CGP-NEXT:    v_addc_u32_e32 v12, vcc, 0, v11, vcc
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
-; CGP-NEXT:    v_cndmask_b32_e32 v0, v10, v1, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v1, v11, v12, vcc
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v9
-; CGP-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc
-; CGP-NEXT:    v_mul_f32_e32 v7, 0x2f800000, v4
-; CGP-NEXT:    v_trunc_f32_e32 v7, v7
-; CGP-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v7
-; CGP-NEXT:    v_cvt_u32_f32_e32 v4, v4
-; CGP-NEXT:    v_cvt_u32_f32_e32 v7, v7
-; CGP-NEXT:    v_cndmask_b32_e32 v1, v8, v1, vcc
-; CGP-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
-; CGP-NEXT:    v_mul_lo_u32 v8, -1, v4
-; CGP-NEXT:    v_mul_lo_u32 v9, s6, v7
-; CGP-NEXT:    v_mul_hi_u32 v11, s6, v4
-; CGP-NEXT:    v_mul_lo_u32 v10, s6, v4
-; CGP-NEXT:    v_addc_u32_e32 v3, vcc, v3, v6, vcc
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
-; CGP-NEXT:    v_mul_lo_u32 v9, v7, v10
-; CGP-NEXT:    v_mul_lo_u32 v11, v4, v8
-; CGP-NEXT:    v_mul_hi_u32 v12, v4, v10
-; CGP-NEXT:    v_mul_hi_u32 v10, v7, v10
-; CGP-NEXT:    v_xor_b32_e32 v0, v0, v5
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v14, v11
 ; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
-; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v12, v7, v8
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v11, v9
-; CGP-NEXT:    v_mul_hi_u32 v11, v4, v8
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v13
+; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v11, vcc, v11, v13
 ; CGP-NEXT:    v_mul_hi_u32 v8, v7, v8
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v12, v10
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
-; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
 ; CGP-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
 ; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
 ; CGP-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
 ; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v9
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
 ; CGP-NEXT:    v_addc_u32_e64 v9, s[4:5], v7, v8, vcc
-; CGP-NEXT:    v_mul_lo_u32 v10, -1, v4
+; CGP-NEXT:    v_mul_lo_u32 v10, -1, v6
 ; CGP-NEXT:    v_mul_lo_u32 v11, s6, v9
-; CGP-NEXT:    v_mul_hi_u32 v13, s6, v4
-; CGP-NEXT:    v_mul_lo_u32 v12, s6, v4
+; CGP-NEXT:    v_mul_hi_u32 v13, s6, v6
+; CGP-NEXT:    v_mul_lo_u32 v14, s6, v6
 ; CGP-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v8
 ; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v11
 ; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v13
-; CGP-NEXT:    v_mul_lo_u32 v11, v9, v12
-; CGP-NEXT:    v_mul_lo_u32 v13, v4, v10
-; CGP-NEXT:    v_mul_hi_u32 v8, v4, v12
-; CGP-NEXT:    v_mul_hi_u32 v12, v9, v12
-; CGP-NEXT:    v_xor_b32_e32 v2, v2, v6
+; CGP-NEXT:    v_mul_lo_u32 v11, v9, v14
+; CGP-NEXT:    v_mul_lo_u32 v13, v6, v10
+; CGP-NEXT:    v_mul_hi_u32 v8, v6, v14
+; CGP-NEXT:    v_mul_lo_u32 v15, v9, v10
+; CGP-NEXT:    v_mul_hi_u32 v14, v9, v14
 ; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v13
 ; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
 ; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v11, v8
+; CGP-NEXT:    v_mul_hi_u32 v11, v6, v10
 ; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
-; CGP-NEXT:    v_mul_lo_u32 v11, v9, v10
 ; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v13, v8
-; CGP-NEXT:    v_mul_hi_u32 v13, v4, v10
-; CGP-NEXT:    v_mul_hi_u32 v9, v9, v10
-; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v13
+; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v15, v14
+; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v13, v11
 ; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v13
+; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v14, v13
+; CGP-NEXT:    v_mul_hi_u32 v9, v9, v10
 ; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v11, v8
-; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v12, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v13, v10
 ; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v10
 ; CGP-NEXT:    v_addc_u32_e32 v7, vcc, v7, v9, vcc
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; CGP-NEXT:    v_xor_b32_e32 v0, v0, v12
+; CGP-NEXT:    v_xor_b32_e32 v1, v1, v12
 ; CGP-NEXT:    v_addc_u32_e32 v7, vcc, 0, v7, vcc
-; CGP-NEXT:    v_xor_b32_e32 v3, v3, v6
-; CGP-NEXT:    v_xor_b32_e32 v1, v1, v5
-; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v0, v5
-; CGP-NEXT:    v_mul_lo_u32 v8, v3, v4
-; CGP-NEXT:    v_mul_lo_u32 v9, v2, v7
-; CGP-NEXT:    v_subb_u32_e32 v1, vcc, v1, v5, vcc
-; CGP-NEXT:    v_mul_hi_u32 v5, v2, v4
-; CGP-NEXT:    v_mul_hi_u32 v4, v3, v4
+; CGP-NEXT:    v_mul_lo_u32 v8, v1, v6
+; CGP-NEXT:    v_mul_lo_u32 v9, v0, v7
+; CGP-NEXT:    v_mul_hi_u32 v10, v0, v6
+; CGP-NEXT:    v_mul_lo_u32 v11, v1, v7
+; CGP-NEXT:    v_mul_hi_u32 v6, v1, v6
 ; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
 ; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; CGP-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v8, v3, v7
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v9, v5
-; CGP-NEXT:    v_mul_hi_u32 v9, v2, v7
-; CGP-NEXT:    v_mul_hi_u32 v7, v3, v7
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v8, v4
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; CGP-NEXT:    v_mul_hi_u32 v10, v0, v7
 ; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v9
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v11, v6
 ; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v10
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
+; CGP-NEXT:    v_mul_hi_u32 v7, v1, v7
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; CGP-NEXT:    v_mul_lo_u32 v8, 0, v6
+; CGP-NEXT:    v_mul_lo_u32 v9, s7, v7
+; CGP-NEXT:    v_mul_hi_u32 v10, s7, v6
+; CGP-NEXT:    v_mul_lo_u32 v11, s7, v6
+; CGP-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
 ; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
-; CGP-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v0, v11
+; CGP-NEXT:    v_subb_u32_e64 v9, s[4:5], v1, v8, vcc
+; CGP-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v8
+; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], 0, v9
+; CGP-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], s7, v0
+; CGP-NEXT:    v_subrev_i32_e32 v0, vcc, s7, v0
+; CGP-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v9
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, 1, v6
+; CGP-NEXT:    v_cndmask_b32_e64 v8, v8, v10, s[4:5]
+; CGP-NEXT:    v_addc_u32_e32 v10, vcc, 0, v7, vcc
+; CGP-NEXT:    v_cmp_le_u32_e32 vcc, 0, v1
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, -1, vcc
+; CGP-NEXT:    v_cmp_le_u32_e32 vcc, s7, v0
+; CGP-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
+; CGP-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
+; CGP-NEXT:    v_cndmask_b32_e32 v0, v11, v0, vcc
+; CGP-NEXT:    v_add_i32_e32 v1, vcc, 1, v9
+; CGP-NEXT:    v_cvt_u32_f32_e32 v4, v4
+; CGP-NEXT:    v_cvt_u32_f32_e32 v5, v5
+; CGP-NEXT:    v_addc_u32_e32 v11, vcc, 0, v10, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
+; CGP-NEXT:    v_cndmask_b32_e32 v0, v9, v1, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v1, v10, v11, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v8
+; CGP-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v1, v7, v1, vcc
+; CGP-NEXT:    v_mul_lo_u32 v6, -1, v4
+; CGP-NEXT:    v_mul_lo_u32 v7, s6, v5
+; CGP-NEXT:    v_mul_hi_u32 v8, s6, v4
+; CGP-NEXT:    v_mul_lo_u32 v9, s6, v4
+; CGP-NEXT:    v_ashrrev_i32_e32 v10, 31, v3
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; CGP-NEXT:    v_mul_lo_u32 v7, v5, v9
+; CGP-NEXT:    v_mul_lo_u32 v8, v4, v6
+; CGP-NEXT:    v_mul_hi_u32 v11, v4, v9
+; CGP-NEXT:    v_add_i32_e32 v2, vcc, v2, v10
+; CGP-NEXT:    v_addc_u32_e32 v3, vcc, v3, v10, vcc
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; CGP-NEXT:    v_mul_lo_u32 v13, v5, v6
+; CGP-NEXT:    v_mul_hi_u32 v9, v5, v9
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v11
+; CGP-NEXT:    v_mul_hi_u32 v11, v4, v6
+; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v13, v9
+; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; CGP-NEXT:    v_mul_hi_u32 v6, v5, v6
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; CGP-NEXT:    v_addc_u32_e64 v7, s[4:5], v5, v6, vcc
+; CGP-NEXT:    v_mul_lo_u32 v8, -1, v4
+; CGP-NEXT:    v_mul_lo_u32 v9, s6, v7
+; CGP-NEXT:    v_mul_hi_u32 v11, s6, v4
+; CGP-NEXT:    v_mul_lo_u32 v13, s6, v4
+; CGP-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v6
+; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
+; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v11
+; CGP-NEXT:    v_mul_lo_u32 v9, v7, v13
+; CGP-NEXT:    v_mul_lo_u32 v11, v4, v8
+; CGP-NEXT:    v_mul_hi_u32 v6, v4, v13
+; CGP-NEXT:    v_mul_lo_u32 v14, v7, v8
+; CGP-NEXT:    v_mul_hi_u32 v13, v7, v13
+; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v6, s[4:5], v9, v6
+; CGP-NEXT:    v_mul_hi_u32 v9, v4, v8
+; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v6, s[4:5], v11, v6
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v14, v13
+; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v9
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v13, v11
+; CGP-NEXT:    v_mul_hi_u32 v7, v7, v8
+; CGP-NEXT:    v_add_i32_e64 v6, s[4:5], v9, v6
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v11, v8
+; CGP-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v8
+; CGP-NEXT:    v_addc_u32_e32 v5, vcc, v5, v7, vcc
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; CGP-NEXT:    v_xor_b32_e32 v2, v2, v10
+; CGP-NEXT:    v_xor_b32_e32 v3, v3, v10
+; CGP-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; CGP-NEXT:    v_mul_lo_u32 v6, v3, v4
+; CGP-NEXT:    v_mul_lo_u32 v7, v2, v5
+; CGP-NEXT:    v_mul_hi_u32 v8, v2, v4
+; CGP-NEXT:    v_mul_lo_u32 v9, v3, v5
+; CGP-NEXT:    v_mul_hi_u32 v4, v3, v4
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; CGP-NEXT:    v_mul_hi_u32 v8, v2, v5
+; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v9, v4
+; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; CGP-NEXT:    v_mul_hi_u32 v5, v3, v5
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
 ; CGP-NEXT:    v_mul_lo_u32 v7, 0, v4
 ; CGP-NEXT:    v_mul_lo_u32 v8, s7, v5
-; CGP-NEXT:    v_mul_hi_u32 v10, s7, v4
-; CGP-NEXT:    v_mul_lo_u32 v9, s7, v4
+; CGP-NEXT:    v_mul_hi_u32 v9, s7, v4
+; CGP-NEXT:    v_xor_b32_e32 v0, v0, v12
+; CGP-NEXT:    v_mul_lo_u32 v6, s7, v4
+; CGP-NEXT:    v_xor_b32_e32 v1, v1, v12
+; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v0, v12
+; CGP-NEXT:    v_subb_u32_e32 v1, vcc, v1, v12, vcc
 ; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
-; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v2, v9
-; CGP-NEXT:    v_subb_u32_e64 v8, s[4:5], v3, v7, vcc
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v2, v6
+; CGP-NEXT:    v_subb_u32_e64 v6, s[4:5], v3, v7, vcc
 ; CGP-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v7
-; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], 0, v8
+; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], 0, v6
 ; CGP-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
 ; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
 ; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], s7, v2
 ; CGP-NEXT:    v_subrev_i32_e32 v2, vcc, s7, v2
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v6
 ; CGP-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v8
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, 1, v4
-; CGP-NEXT:    v_cndmask_b32_e64 v7, v7, v9, s[4:5]
-; CGP-NEXT:    v_addc_u32_e32 v9, vcc, 0, v5, vcc
+; CGP-NEXT:    v_cndmask_b32_e64 v6, v7, v8, s[4:5]
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, 1, v4
+; CGP-NEXT:    v_addc_u32_e32 v8, vcc, 0, v5, vcc
 ; CGP-NEXT:    v_cmp_le_u32_e32 vcc, 0, v3
-; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, -1, vcc
+; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
 ; CGP-NEXT:    v_cmp_le_u32_e32 vcc, s7, v2
 ; CGP-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
 ; CGP-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v3
-; CGP-NEXT:    v_cndmask_b32_e32 v2, v10, v2, vcc
-; CGP-NEXT:    v_add_i32_e32 v3, vcc, 1, v8
-; CGP-NEXT:    v_addc_u32_e32 v10, vcc, 0, v9, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v2, v9, v2, vcc
+; CGP-NEXT:    v_add_i32_e32 v3, vcc, 1, v7
+; CGP-NEXT:    v_addc_u32_e32 v9, vcc, 0, v8, vcc
 ; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
-; CGP-NEXT:    v_cndmask_b32_e32 v2, v8, v3, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v3, v9, v10, vcc
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
+; CGP-NEXT:    v_cndmask_b32_e32 v2, v7, v3, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v3, v8, v9, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
 ; CGP-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
 ; CGP-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc
-; CGP-NEXT:    v_xor_b32_e32 v2, v2, v6
-; CGP-NEXT:    v_xor_b32_e32 v3, v3, v6
-; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v2, v6
-; CGP-NEXT:    v_subb_u32_e32 v3, vcc, v3, v6, vcc
+; CGP-NEXT:    v_xor_b32_e32 v2, v2, v10
+; CGP-NEXT:    v_xor_b32_e32 v3, v3, v10
+; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v2, v10
+; CGP-NEXT:    v_subb_u32_e32 v3, vcc, v3, v10, vcc
 ; CGP-NEXT:    s_setpc_b64 s[30:31]
   %result = sdiv <2 x i64> %num, <i64 4096, i64 4096>
   ret <2 x i64> %result
@@ -1781,141 +1781,141 @@
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:    v_cvt_f32_u32_e32 v2, 0x12d8fb
-; CHECK-NEXT:    v_cvt_f32_ubyte0_e32 v4, 0
+; CHECK-NEXT:    v_cvt_f32_ubyte0_e32 v3, 0
 ; CHECK-NEXT:    s_mov_b32 s6, 0xffed2705
-; CHECK-NEXT:    v_ashrrev_i32_e32 v3, 31, v1
-; CHECK-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v4
+; CHECK-NEXT:    v_ashrrev_i32_e32 v8, 31, v1
+; CHECK-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
 ; CHECK-NEXT:    v_rcp_iflag_f32_e32 v2, v2
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
-; CHECK-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
-; CHECK-NEXT:    v_xor_b32_e32 v0, v0, v3
 ; CHECK-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
-; CHECK-NEXT:    v_mul_f32_e32 v4, 0x2f800000, v2
-; CHECK-NEXT:    v_trunc_f32_e32 v4, v4
-; CHECK-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v4
+; CHECK-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
+; CHECK-NEXT:    v_trunc_f32_e32 v3, v3
+; CHECK-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
 ; CHECK-NEXT:    v_cvt_u32_f32_e32 v2, v2
-; CHECK-NEXT:    v_cvt_u32_f32_e32 v4, v4
-; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v3
+; CHECK-NEXT:    v_cvt_u32_f32_e32 v3, v3
 ; CHECK-NEXT:    v_mul_lo_u32 v5, -1, v2
-; CHECK-NEXT:    v_mul_lo_u32 v6, s6, v4
-; CHECK-NEXT:    v_mul_hi_u32 v8, s6, v2
-; CHECK-NEXT:    v_mul_lo_u32 v7, s6, v2
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
-; CHECK-NEXT:    v_mul_lo_u32 v6, v4, v7
-; CHECK-NEXT:    v_mul_lo_u32 v8, v2, v5
-; CHECK-NEXT:    v_mul_hi_u32 v9, v2, v7
-; CHECK-NEXT:    v_mul_hi_u32 v7, v4, v7
-; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
-; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CHECK-NEXT:    v_mul_lo_u32 v4, s6, v3
+; CHECK-NEXT:    v_mul_hi_u32 v7, s6, v2
+; CHECK-NEXT:    v_mul_lo_u32 v6, s6, v2
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; CHECK-NEXT:    v_mul_lo_u32 v5, v3, v6
+; CHECK-NEXT:    v_mul_lo_u32 v7, v2, v4
+; CHECK-NEXT:    v_mul_hi_u32 v9, v2, v6
+; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v8
+; CHECK-NEXT:    v_addc_u32_e32 v1, vcc, v1, v8, vcc
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; CHECK-NEXT:    v_mul_lo_u32 v10, v3, v4
+; CHECK-NEXT:    v_mul_hi_u32 v6, v3, v6
+; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v9
+; CHECK-NEXT:    v_mul_hi_u32 v9, v2, v4
+; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
+; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v10, v6
+; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
-; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v9, v4, v5
-; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
-; CHECK-NEXT:    v_mul_hi_u32 v8, v2, v5
-; CHECK-NEXT:    v_mul_hi_u32 v5, v4, v5
-; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v9, v7
 ; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; CHECK-NEXT:    v_mul_hi_u32 v4, v3, v4
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
+; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
-; CHECK-NEXT:    v_addc_u32_e64 v6, s[4:5], v4, v5, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v7, -1, v2
-; CHECK-NEXT:    v_mul_lo_u32 v8, s6, v6
-; CHECK-NEXT:    v_mul_hi_u32 v10, s6, v2
-; CHECK-NEXT:    v_mul_lo_u32 v9, s6, v2
-; CHECK-NEXT:    v_add_i32_e64 v4, s[4:5], v4, v5
-; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v8
-; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v10
-; CHECK-NEXT:    v_mul_lo_u32 v8, v6, v9
-; CHECK-NEXT:    v_mul_lo_u32 v10, v2, v7
-; CHECK-NEXT:    v_mul_hi_u32 v5, v2, v9
-; CHECK-NEXT:    v_mul_hi_u32 v9, v6, v9
-; CHECK-NEXT:    s_mov_b32 s6, 0x12d8fb
-; CHECK-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v10
-; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v5, s[4:5], v8, v5
-; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, s[4:5]
-; CHECK-NEXT:    v_mul_lo_u32 v8, v6, v7
-; CHECK-NEXT:    v_add_i32_e64 v5, s[4:5], v10, v5
-; CHECK-NEXT:    v_mul_hi_u32 v10, v2, v7
-; CHECK-NEXT:    v_mul_hi_u32 v6, v6, v7
-; CHECK-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; CHECK-NEXT:    v_addc_u32_e64 v5, s[4:5], v3, v4, vcc
+; CHECK-NEXT:    v_mul_lo_u32 v6, -1, v2
+; CHECK-NEXT:    v_mul_lo_u32 v7, s6, v5
+; CHECK-NEXT:    v_mul_hi_u32 v9, s6, v2
+; CHECK-NEXT:    v_mul_lo_u32 v10, s6, v2
+; CHECK-NEXT:    v_add_i32_e64 v3, s[4:5], v3, v4
+; CHECK-NEXT:    v_add_i32_e64 v6, s[4:5], v6, v7
+; CHECK-NEXT:    v_add_i32_e64 v6, s[4:5], v6, v9
+; CHECK-NEXT:    v_mul_lo_u32 v7, v5, v10
+; CHECK-NEXT:    v_mul_lo_u32 v9, v2, v6
+; CHECK-NEXT:    v_mul_hi_u32 v4, v2, v10
+; CHECK-NEXT:    v_mul_lo_u32 v11, v5, v6
+; CHECK-NEXT:    v_mul_hi_u32 v10, v5, v10
+; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v9
 ; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v10
+; CHECK-NEXT:    v_add_i32_e64 v4, s[4:5], v7, v4
+; CHECK-NEXT:    v_mul_hi_u32 v7, v2, v6
+; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v4, s[4:5], v9, v4
+; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v10
 ; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v10
-; CHECK-NEXT:    v_add_i32_e64 v5, s[4:5], v8, v5
-; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v9, v8
-; CHECK-NEXT:    v_add_i32_e64 v6, s[4:5], v6, v7
-; CHECK-NEXT:    v_addc_u32_e32 v4, vcc, v4, v6, vcc
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
-; CHECK-NEXT:    v_addc_u32_e32 v4, vcc, 0, v4, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v5, v1, v2
-; CHECK-NEXT:    v_mul_lo_u32 v6, v0, v4
-; CHECK-NEXT:    v_mul_hi_u32 v7, v0, v2
+; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v9, v7
+; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v10, v9
+; CHECK-NEXT:    v_mul_hi_u32 v5, v5, v6
+; CHECK-NEXT:    v_add_i32_e64 v4, s[4:5], v7, v4
+; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v6, s[4:5], v9, v6
+; CHECK-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v6
+; CHECK-NEXT:    v_addc_u32_e32 v3, vcc, v3, v5, vcc
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
+; CHECK-NEXT:    v_xor_b32_e32 v0, v0, v8
+; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v8
+; CHECK-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; CHECK-NEXT:    v_mul_lo_u32 v4, v1, v2
+; CHECK-NEXT:    v_mul_lo_u32 v5, v0, v3
+; CHECK-NEXT:    v_mul_hi_u32 v6, v0, v2
+; CHECK-NEXT:    v_mul_lo_u32 v7, v1, v3
 ; CHECK-NEXT:    v_mul_hi_u32 v2, v1, v2
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
-; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
 ; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v7, v1, v4
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; CHECK-NEXT:    v_mul_hi_u32 v6, v0, v4
-; CHECK-NEXT:    v_mul_hi_u32 v4, v1, v4
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; CHECK-NEXT:    v_mul_hi_u32 v6, v0, v3
+; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v7, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
 ; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
-; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
-; CHECK-NEXT:    v_mul_lo_u32 v5, 0, v2
-; CHECK-NEXT:    v_mul_lo_u32 v6, s6, v4
-; CHECK-NEXT:    v_mul_hi_u32 v8, s6, v2
-; CHECK-NEXT:    v_mul_lo_u32 v7, s6, v2
 ; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
+; CHECK-NEXT:    v_mul_hi_u32 v3, v1, v3
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
+; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; CHECK-NEXT:    s_mov_b32 s6, 0x12d8fb
+; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v3, v4
+; CHECK-NEXT:    v_mul_lo_u32 v4, 0, v2
+; CHECK-NEXT:    v_mul_lo_u32 v5, s6, v3
+; CHECK-NEXT:    v_mul_hi_u32 v6, s6, v2
+; CHECK-NEXT:    v_mul_lo_u32 v7, s6, v2
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
 ; CHECK-NEXT:    v_sub_i32_e32 v0, vcc, v0, v7
-; CHECK-NEXT:    v_subb_u32_e64 v6, s[4:5], v1, v5, vcc
-; CHECK-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v5
-; CHECK-NEXT:    v_cmp_le_u32_e64 s[4:5], 0, v6
+; CHECK-NEXT:    v_subb_u32_e64 v5, s[4:5], v1, v4, vcc
+; CHECK-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v4
+; CHECK-NEXT:    v_cmp_le_u32_e64 s[4:5], 0, v5
 ; CHECK-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[4:5]
+; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[4:5]
 ; CHECK-NEXT:    v_cmp_le_u32_e64 s[4:5], s6, v0
 ; CHECK-NEXT:    v_subrev_i32_e32 v0, vcc, s6, v0
 ; CHECK-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
-; CHECK-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v6
-; CHECK-NEXT:    v_add_i32_e32 v6, vcc, 1, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v5, v5, v7, s[4:5]
-; CHECK-NEXT:    v_addc_u32_e32 v7, vcc, 0, v4, vcc
+; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[4:5]
+; CHECK-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v5
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, 1, v2
+; CHECK-NEXT:    v_cndmask_b32_e64 v4, v4, v6, s[4:5]
+; CHECK-NEXT:    v_addc_u32_e32 v6, vcc, 0, v3, vcc
 ; CHECK-NEXT:    v_cmp_le_u32_e32 vcc, 0, v1
-; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
+; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
 ; CHECK-NEXT:    v_cmp_le_u32_e32 vcc, s6, v0
 ; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
 ; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
-; CHECK-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc
-; CHECK-NEXT:    v_add_i32_e32 v1, vcc, 1, v6
-; CHECK-NEXT:    v_addc_u32_e32 v8, vcc, 0, v7, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc
+; CHECK-NEXT:    v_add_i32_e32 v1, vcc, 1, v5
+; CHECK-NEXT:    v_addc_u32_e32 v7, vcc, 0, v6, vcc
 ; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
-; CHECK-NEXT:    v_cndmask_b32_e32 v0, v6, v1, vcc
-; CHECK-NEXT:    v_cndmask_b32_e32 v1, v7, v8, vcc
-; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
+; CHECK-NEXT:    v_cndmask_b32_e32 v0, v5, v1, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v1, v6, v7, vcc
+; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
 ; CHECK-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
-; CHECK-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc
-; CHECK-NEXT:    v_xor_b32_e32 v0, v0, v3
-; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v3
-; CHECK-NEXT:    v_sub_i32_e32 v0, vcc, v0, v3
-; CHECK-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
+; CHECK-NEXT:    v_xor_b32_e32 v0, v0, v8
+; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v8
+; CHECK-NEXT:    v_sub_i32_e32 v0, vcc, v0, v8
+; CHECK-NEXT:    v_subb_u32_e32 v1, vcc, v1, v8, vcc
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %result = sdiv i64 %num, 1235195
   ret i64 %result
@@ -1943,557 +1943,557 @@
 ; GISEL-NEXT:    v_rcp_iflag_f32_e32 v4, v4
 ; GISEL-NEXT:    s_cmp_lg_u32 s4, 0
 ; GISEL-NEXT:    s_subb_u32 s12, 0, s9
-; GISEL-NEXT:    v_ashrrev_i32_e32 v6, 31, v1
+; GISEL-NEXT:    v_ashrrev_i32_e32 v10, 31, v1
 ; GISEL-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
 ; GISEL-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
 ; GISEL-NEXT:    v_trunc_f32_e32 v5, v5
 ; GISEL-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v4, v4
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v5, v5
-; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v6
-; GISEL-NEXT:    v_addc_u32_e32 v1, vcc, v1, v6, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v7, s12, v4
-; GISEL-NEXT:    v_mul_lo_u32 v8, s11, v5
-; GISEL-NEXT:    v_mul_hi_u32 v10, s11, v4
+; GISEL-NEXT:    v_mul_lo_u32 v6, s12, v4
+; GISEL-NEXT:    v_mul_lo_u32 v7, s11, v5
+; GISEL-NEXT:    v_mul_hi_u32 v8, s11, v4
 ; GISEL-NEXT:    v_mul_lo_u32 v9, s11, v4
-; GISEL-NEXT:    v_xor_b32_e32 v0, v0, v6
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
-; GISEL-NEXT:    v_mul_lo_u32 v8, v5, v9
-; GISEL-NEXT:    v_mul_lo_u32 v10, v4, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; GISEL-NEXT:    v_mul_lo_u32 v7, v5, v9
+; GISEL-NEXT:    v_mul_lo_u32 v8, v4, v6
 ; GISEL-NEXT:    v_mul_hi_u32 v11, v4, v9
+; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v10
+; GISEL-NEXT:    v_addc_u32_e32 v1, vcc, v1, v10, vcc
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; GISEL-NEXT:    v_mul_lo_u32 v12, v5, v6
 ; GISEL-NEXT:    v_mul_hi_u32 v9, v5, v9
-; GISEL-NEXT:    v_xor_b32_e32 v1, v1, v6
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v11, v5, v7
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
-; GISEL-NEXT:    v_mul_hi_u32 v10, v4, v7
-; GISEL-NEXT:    v_mul_hi_u32 v7, v5, v7
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v11, v9
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v11
+; GISEL-NEXT:    v_mul_hi_u32 v11, v4, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v12, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
 ; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; GISEL-NEXT:    v_mul_hi_u32 v6, v5, v6
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
-; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
-; GISEL-NEXT:    v_addc_u32_e64 v8, s[4:5], v5, v7, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v9, s12, v4
-; GISEL-NEXT:    v_mul_lo_u32 v10, s11, v8
-; GISEL-NEXT:    v_mul_hi_u32 v12, s11, v4
-; GISEL-NEXT:    v_mul_lo_u32 v11, s11, v4
-; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v7
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v10
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v12
-; GISEL-NEXT:    v_mul_lo_u32 v10, v8, v11
-; GISEL-NEXT:    v_mul_lo_u32 v12, v4, v9
-; GISEL-NEXT:    v_mul_hi_u32 v7, v4, v11
-; GISEL-NEXT:    v_mul_hi_u32 v11, v8, v11
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v12
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v10, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, s[4:5]
-; GISEL-NEXT:    v_mul_lo_u32 v10, v8, v9
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v12, v7
-; GISEL-NEXT:    v_mul_hi_u32 v12, v4, v9
-; GISEL-NEXT:    v_mul_hi_u32 v8, v8, v9
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v11
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; GISEL-NEXT:    v_addc_u32_e64 v7, s[4:5], v5, v6, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v8, s12, v4
+; GISEL-NEXT:    v_mul_lo_u32 v9, s11, v7
+; GISEL-NEXT:    v_mul_hi_u32 v11, s11, v4
+; GISEL-NEXT:    v_mul_lo_u32 v12, s11, v4
+; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v6
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v11
+; GISEL-NEXT:    v_mul_lo_u32 v9, v7, v12
+; GISEL-NEXT:    v_mul_lo_u32 v11, v4, v8
+; GISEL-NEXT:    v_mul_hi_u32 v6, v4, v12
+; GISEL-NEXT:    v_mul_lo_u32 v13, v7, v8
+; GISEL-NEXT:    v_mul_hi_u32 v12, v7, v12
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v11
 ; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v12
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v9, v6
+; GISEL-NEXT:    v_mul_hi_u32 v9, v4, v8
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v11, v6
+; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v13, v12
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v10, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v10
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
-; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v8, vcc
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v12, v11
+; GISEL-NEXT:    v_mul_hi_u32 v7, v7, v8
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v9, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v11, v8
+; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v8
+; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v7, vcc
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; GISEL-NEXT:    v_xor_b32_e32 v0, v0, v10
+; GISEL-NEXT:    v_xor_b32_e32 v1, v1, v10
 ; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v7, v1, v4
-; GISEL-NEXT:    v_mul_lo_u32 v8, v0, v5
-; GISEL-NEXT:    v_mul_hi_u32 v10, v0, v4
+; GISEL-NEXT:    v_mul_lo_u32 v6, v1, v4
+; GISEL-NEXT:    v_mul_lo_u32 v7, v0, v5
+; GISEL-NEXT:    v_mul_hi_u32 v8, v0, v4
+; GISEL-NEXT:    v_mul_lo_u32 v9, v1, v5
 ; GISEL-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GISEL-NEXT:    v_mov_b32_e32 v9, s9
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
 ; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v10, v1, v5
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
 ; GISEL-NEXT:    v_mul_hi_u32 v8, v0, v5
-; GISEL-NEXT:    v_mul_hi_u32 v5, v1, v5
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v10, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v9, v4
+; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; GISEL-NEXT:    v_mul_lo_u32 v7, s9, v4
-; GISEL-NEXT:    v_mul_lo_u32 v8, s8, v5
-; GISEL-NEXT:    v_mul_hi_u32 v11, s8, v4
-; GISEL-NEXT:    v_mul_lo_u32 v10, s8, v4
 ; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v11
-; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v10
-; GISEL-NEXT:    v_subb_u32_e64 v8, s[4:5], v1, v7, vcc
-; GISEL-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v7
-; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s9, v8
-; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v9, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
+; GISEL-NEXT:    v_mul_hi_u32 v5, v1, v5
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
+; GISEL-NEXT:    v_mul_lo_u32 v6, s9, v4
+; GISEL-NEXT:    v_mul_lo_u32 v7, s8, v5
+; GISEL-NEXT:    v_mul_hi_u32 v8, s8, v4
+; GISEL-NEXT:    v_mul_lo_u32 v9, s8, v4
+; GISEL-NEXT:    v_mov_b32_e32 v11, s9
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v9
+; GISEL-NEXT:    v_subb_u32_e64 v7, s[4:5], v1, v6, vcc
+; GISEL-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v6
+; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s9, v7
+; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v11, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[4:5]
 ; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s8, v0
 ; GISEL-NEXT:    v_subrev_i32_e32 v0, vcc, s8, v0
 ; GISEL-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], s9, v8
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, 1, v4
-; GISEL-NEXT:    v_addc_u32_e32 v9, vcc, 0, v5, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], s9, v7
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, 1, v4
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, v6, v8, s[4:5]
+; GISEL-NEXT:    v_addc_u32_e32 v8, vcc, 0, v5, vcc
 ; GISEL-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, v7, v10, s[4:5]
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, -1, vcc
-; GISEL-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
 ; GISEL-NEXT:    s_add_u32 s4, s10, 0
 ; GISEL-NEXT:    s_cselect_b32 s5, 1, 0
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
+; GISEL-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
+; GISEL-NEXT:    s_and_b32 s5, s5, 1
 ; GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
 ; GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v1
-; GISEL-NEXT:    s_and_b32 s5, s5, 1
-; GISEL-NEXT:    v_cndmask_b32_e32 v0, v10, v0, vcc
-; GISEL-NEXT:    v_add_i32_e32 v1, vcc, 1, v8
 ; GISEL-NEXT:    s_cmp_lg_u32 s5, 0
-; GISEL-NEXT:    v_addc_u32_e32 v10, vcc, 0, v9, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
+; GISEL-NEXT:    v_cndmask_b32_e32 v0, v9, v0, vcc
+; GISEL-NEXT:    v_add_i32_e32 v1, vcc, 1, v7
+; GISEL-NEXT:    v_addc_u32_e32 v9, vcc, 0, v8, vcc
 ; GISEL-NEXT:    s_addc_u32 s5, 0, 0
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
 ; GISEL-NEXT:    s_xor_b64 s[6:7], s[4:5], s[6:7]
-; GISEL-NEXT:    v_cndmask_b32_e32 v0, v8, v1, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v1, v9, v10, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
+; GISEL-NEXT:    v_cndmask_b32_e32 v0, v7, v1, vcc
+; GISEL-NEXT:    v_cvt_f32_u32_e32 v1, s6
+; GISEL-NEXT:    v_cvt_f32_u32_e32 v7, s7
+; GISEL-NEXT:    v_cndmask_b32_e32 v8, v8, v9, vcc
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
 ; GISEL-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc
-; GISEL-NEXT:    v_cvt_f32_u32_e32 v4, s6
-; GISEL-NEXT:    v_cvt_f32_u32_e32 v5, s7
+; GISEL-NEXT:    v_mac_f32_e32 v1, 0x4f800000, v7
+; GISEL-NEXT:    v_rcp_iflag_f32_e32 v1, v1
+; GISEL-NEXT:    v_cndmask_b32_e32 v4, v5, v8, vcc
 ; GISEL-NEXT:    s_sub_u32 s8, 0, s6
 ; GISEL-NEXT:    s_cselect_b32 s4, 1, 0
+; GISEL-NEXT:    v_mul_f32_e32 v1, 0x5f7ffffc, v1
+; GISEL-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v1
+; GISEL-NEXT:    v_trunc_f32_e32 v5, v5
+; GISEL-NEXT:    v_mac_f32_e32 v1, 0xcf800000, v5
+; GISEL-NEXT:    v_cvt_u32_f32_e32 v1, v1
+; GISEL-NEXT:    v_cvt_u32_f32_e32 v5, v5
 ; GISEL-NEXT:    s_and_b32 s4, s4, 1
-; GISEL-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
-; GISEL-NEXT:    v_rcp_iflag_f32_e32 v4, v4
 ; GISEL-NEXT:    s_cmp_lg_u32 s4, 0
 ; GISEL-NEXT:    s_subb_u32 s9, 0, s7
-; GISEL-NEXT:    v_xor_b32_e32 v0, v0, v6
-; GISEL-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
-; GISEL-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
-; GISEL-NEXT:    v_trunc_f32_e32 v5, v5
-; GISEL-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
-; GISEL-NEXT:    v_cvt_u32_f32_e32 v4, v4
-; GISEL-NEXT:    v_cvt_u32_f32_e32 v5, v5
-; GISEL-NEXT:    v_xor_b32_e32 v1, v1, v6
-; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v6
-; GISEL-NEXT:    v_mul_lo_u32 v7, s9, v4
-; GISEL-NEXT:    v_mul_lo_u32 v8, s8, v5
-; GISEL-NEXT:    v_mul_hi_u32 v10, s8, v4
-; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v6, vcc
-; GISEL-NEXT:    v_ashrrev_i32_e32 v6, 31, v3
-; GISEL-NEXT:    v_mul_lo_u32 v9, s8, v4
-; GISEL-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
-; GISEL-NEXT:    v_addc_u32_e32 v3, vcc, v3, v6, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v6, s9, v1
+; GISEL-NEXT:    v_mul_lo_u32 v7, s8, v5
+; GISEL-NEXT:    v_mul_hi_u32 v8, s8, v1
+; GISEL-NEXT:    v_mul_lo_u32 v9, s8, v1
+; GISEL-NEXT:    v_ashrrev_i32_e32 v11, 31, v3
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; GISEL-NEXT:    v_mul_lo_u32 v7, v5, v9
+; GISEL-NEXT:    v_mul_lo_u32 v8, v1, v6
+; GISEL-NEXT:    v_mul_hi_u32 v12, v1, v9
+; GISEL-NEXT:    v_add_i32_e32 v2, vcc, v2, v11
+; GISEL-NEXT:    v_addc_u32_e32 v3, vcc, v3, v11, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
-; GISEL-NEXT:    v_mul_lo_u32 v8, v5, v9
-; GISEL-NEXT:    v_mul_lo_u32 v10, v4, v7
-; GISEL-NEXT:    v_mul_hi_u32 v11, v4, v9
+; GISEL-NEXT:    v_mul_lo_u32 v13, v5, v6
 ; GISEL-NEXT:    v_mul_hi_u32 v9, v5, v9
-; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v6
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v11, v5, v7
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
-; GISEL-NEXT:    v_mul_hi_u32 v10, v4, v7
-; GISEL-NEXT:    v_mul_hi_u32 v7, v5, v7
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v11, v9
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v12
+; GISEL-NEXT:    v_mul_hi_u32 v12, v1, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v13, v9
 ; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
-; GISEL-NEXT:    v_addc_u32_e64 v8, s[4:5], v5, v7, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v9, s9, v4
-; GISEL-NEXT:    v_mul_lo_u32 v10, s8, v8
-; GISEL-NEXT:    v_mul_hi_u32 v12, s8, v4
-; GISEL-NEXT:    v_mul_lo_u32 v11, s8, v4
-; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v7
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v10
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v12
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
+; GISEL-NEXT:    v_mul_hi_u32 v6, v5, v6
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; GISEL-NEXT:    v_add_i32_e32 v1, vcc, v1, v7
+; GISEL-NEXT:    v_addc_u32_e64 v7, s[4:5], v5, v6, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v8, s9, v1
+; GISEL-NEXT:    v_mul_lo_u32 v9, s8, v7
+; GISEL-NEXT:    v_mul_hi_u32 v12, s8, v1
+; GISEL-NEXT:    v_mul_lo_u32 v13, s8, v1
+; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v6
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v12
+; GISEL-NEXT:    v_mul_lo_u32 v9, v7, v13
+; GISEL-NEXT:    v_mul_lo_u32 v12, v1, v8
+; GISEL-NEXT:    v_mul_hi_u32 v6, v1, v13
+; GISEL-NEXT:    v_mul_lo_u32 v14, v7, v8
+; GISEL-NEXT:    v_mul_hi_u32 v13, v7, v13
 ; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v12
-; GISEL-NEXT:    v_mul_lo_u32 v10, v8, v11
-; GISEL-NEXT:    v_mul_lo_u32 v12, v4, v9
-; GISEL-NEXT:    v_mul_hi_u32 v7, v4, v11
-; GISEL-NEXT:    v_mul_hi_u32 v11, v8, v11
-; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v6
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v12
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v10, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, s[4:5]
-; GISEL-NEXT:    v_mul_lo_u32 v10, v8, v9
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v12, v7
-; GISEL-NEXT:    v_mul_hi_u32 v12, v4, v9
-; GISEL-NEXT:    v_mul_hi_u32 v8, v8, v9
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v11
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v12
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v9, v6
+; GISEL-NEXT:    v_mul_hi_u32 v9, v1, v8
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v12, v6
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v14, v13
+; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v12, v9
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v10, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v10
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
-; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v8, vcc
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v13, v12
+; GISEL-NEXT:    v_mul_hi_u32 v7, v7, v8
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v9, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v12, v8
+; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v8
+; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v7, vcc
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v1, v6
+; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v11
 ; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v7, v3, v4
+; GISEL-NEXT:    v_xor_b32_e32 v0, v0, v10
+; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v11
+; GISEL-NEXT:    v_xor_b32_e32 v4, v4, v10
+; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v10
+; GISEL-NEXT:    v_mul_lo_u32 v7, v3, v6
 ; GISEL-NEXT:    v_mul_lo_u32 v8, v2, v5
-; GISEL-NEXT:    v_mul_hi_u32 v10, v2, v4
-; GISEL-NEXT:    v_mul_hi_u32 v4, v3, v4
-; GISEL-NEXT:    v_mov_b32_e32 v9, s7
+; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v4, v10, vcc
+; GISEL-NEXT:    v_mul_hi_u32 v4, v2, v6
+; GISEL-NEXT:    v_mul_lo_u32 v9, v3, v5
 ; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; GISEL-NEXT:    v_mul_hi_u32 v6, v3, v6
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v10, v3, v5
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; GISEL-NEXT:    v_mul_hi_u32 v8, v2, v5
-; GISEL-NEXT:    v_mul_hi_u32 v5, v3, v5
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v10, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
+; GISEL-NEXT:    v_mul_hi_u32 v7, v2, v5
+; GISEL-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v8, v4
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v9, v6
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
 ; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; GISEL-NEXT:    v_mul_lo_u32 v7, s7, v4
-; GISEL-NEXT:    v_mul_lo_u32 v8, s6, v5
-; GISEL-NEXT:    v_mul_hi_u32 v11, s6, v4
-; GISEL-NEXT:    v_mul_lo_u32 v10, s6, v4
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v11
-; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v10
-; GISEL-NEXT:    v_subb_u32_e64 v8, s[4:5], v3, v7, vcc
-; GISEL-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v7
-; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s7, v8
-; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v9, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
+; GISEL-NEXT:    v_mul_hi_u32 v5, v3, v5
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
+; GISEL-NEXT:    v_mul_lo_u32 v6, s7, v4
+; GISEL-NEXT:    v_mul_lo_u32 v7, s6, v5
+; GISEL-NEXT:    v_mul_hi_u32 v8, s6, v4
+; GISEL-NEXT:    v_mul_lo_u32 v9, s6, v4
+; GISEL-NEXT:    v_mov_b32_e32 v10, s7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v9
+; GISEL-NEXT:    v_subb_u32_e64 v7, s[4:5], v3, v6, vcc
+; GISEL-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v6
+; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s7, v7
+; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v10, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[4:5]
 ; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s6, v2
 ; GISEL-NEXT:    v_subrev_i32_e32 v2, vcc, s6, v2
 ; GISEL-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], s7, v8
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, 1, v4
-; GISEL-NEXT:    v_addc_u32_e32 v9, vcc, 0, v5, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], s7, v7
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, 1, v4
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, v6, v8, s[4:5]
+; GISEL-NEXT:    v_addc_u32_e32 v8, vcc, 0, v5, vcc
 ; GISEL-NEXT:    v_cmp_le_u32_e32 vcc, s7, v3
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, v7, v10, s[4:5]
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, -1, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
 ; GISEL-NEXT:    v_cmp_le_u32_e32 vcc, s6, v2
 ; GISEL-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
 ; GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, s7, v3
-; GISEL-NEXT:    v_cndmask_b32_e32 v2, v10, v2, vcc
-; GISEL-NEXT:    v_add_i32_e32 v3, vcc, 1, v8
-; GISEL-NEXT:    v_addc_u32_e32 v10, vcc, 0, v9, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v2, v9, v2, vcc
+; GISEL-NEXT:    v_add_i32_e32 v3, vcc, 1, v7
+; GISEL-NEXT:    v_addc_u32_e32 v9, vcc, 0, v8, vcc
 ; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
-; GISEL-NEXT:    v_cndmask_b32_e32 v2, v8, v3, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v3, v9, v10, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
+; GISEL-NEXT:    v_cndmask_b32_e32 v2, v7, v3, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v3, v8, v9, vcc
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
 ; GISEL-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
 ; GISEL-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc
-; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v6
-; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v6
-; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v6
-; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v6, vcc
+; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v11
+; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v11
+; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v11
+; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v11, vcc
 ; GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; CGP-LABEL: v_sdiv_v2i64_oddk_denom:
 ; CGP:       ; %bb.0:
 ; CGP-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CGP-NEXT:    v_cvt_f32_u32_e32 v4, 0x12d8fb
-; CGP-NEXT:    v_cvt_f32_ubyte0_e32 v6, 0
+; CGP-NEXT:    v_cvt_f32_ubyte0_e32 v5, 0
 ; CGP-NEXT:    s_mov_b32 s6, 0xffed2705
-; CGP-NEXT:    v_ashrrev_i32_e32 v5, 31, v1
-; CGP-NEXT:    v_mov_b32_e32 v7, v4
-; CGP-NEXT:    v_mac_f32_e32 v7, 0x4f800000, v6
-; CGP-NEXT:    v_rcp_iflag_f32_e32 v7, v7
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v5
-; CGP-NEXT:    v_addc_u32_e32 v1, vcc, v1, v5, vcc
-; CGP-NEXT:    v_xor_b32_e32 v0, v0, v5
-; CGP-NEXT:    v_mul_f32_e32 v7, 0x5f7ffffc, v7
-; CGP-NEXT:    v_mul_f32_e32 v8, 0x2f800000, v7
-; CGP-NEXT:    v_trunc_f32_e32 v8, v8
-; CGP-NEXT:    v_mac_f32_e32 v7, 0xcf800000, v8
-; CGP-NEXT:    v_cvt_u32_f32_e32 v7, v7
-; CGP-NEXT:    v_cvt_u32_f32_e32 v8, v8
-; CGP-NEXT:    v_xor_b32_e32 v1, v1, v5
+; CGP-NEXT:    v_ashrrev_i32_e32 v12, 31, v1
+; CGP-NEXT:    v_mov_b32_e32 v6, v4
+; CGP-NEXT:    v_mac_f32_e32 v6, 0x4f800000, v5
+; CGP-NEXT:    v_rcp_iflag_f32_e32 v6, v6
 ; CGP-NEXT:    s_mov_b32 s7, 0x12d8fb
-; CGP-NEXT:    v_mul_lo_u32 v9, -1, v7
-; CGP-NEXT:    v_mul_lo_u32 v10, s6, v8
-; CGP-NEXT:    v_mul_hi_u32 v12, s6, v7
-; CGP-NEXT:    v_mul_lo_u32 v11, s6, v7
-; CGP-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v6
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
-; CGP-NEXT:    v_mul_lo_u32 v10, v8, v11
-; CGP-NEXT:    v_mul_lo_u32 v12, v7, v9
-; CGP-NEXT:    v_mul_hi_u32 v13, v7, v11
-; CGP-NEXT:    v_mul_hi_u32 v11, v8, v11
+; CGP-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
 ; CGP-NEXT:    v_rcp_iflag_f32_e32 v4, v4
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v13
-; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v13, v8, v9
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v12, v10
-; CGP-NEXT:    v_mul_hi_u32 v12, v7, v9
-; CGP-NEXT:    v_mul_hi_u32 v9, v8, v9
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v13, v11
-; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
-; CGP-NEXT:    v_addc_u32_e64 v10, s[4:5], v8, v9, vcc
-; CGP-NEXT:    v_mul_lo_u32 v11, -1, v7
-; CGP-NEXT:    v_mul_lo_u32 v12, s6, v10
-; CGP-NEXT:    v_mul_hi_u32 v14, s6, v7
-; CGP-NEXT:    v_mul_lo_u32 v13, s6, v7
-; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
-; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
-; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v14
-; CGP-NEXT:    v_mul_lo_u32 v12, v10, v13
-; CGP-NEXT:    v_mul_lo_u32 v14, v7, v11
-; CGP-NEXT:    v_mul_hi_u32 v9, v7, v13
-; CGP-NEXT:    v_mul_hi_u32 v13, v10, v13
+; CGP-NEXT:    v_mul_f32_e32 v6, 0x5f7ffffc, v6
+; CGP-NEXT:    v_mul_f32_e32 v7, 0x2f800000, v6
+; CGP-NEXT:    v_trunc_f32_e32 v7, v7
+; CGP-NEXT:    v_mac_f32_e32 v6, 0xcf800000, v7
+; CGP-NEXT:    v_cvt_u32_f32_e32 v6, v6
+; CGP-NEXT:    v_cvt_u32_f32_e32 v7, v7
 ; CGP-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v14
-; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v12, v9
-; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
-; CGP-NEXT:    v_mul_lo_u32 v12, v10, v11
-; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v14, v9
-; CGP-NEXT:    v_mul_hi_u32 v14, v7, v11
-; CGP-NEXT:    v_mul_hi_u32 v10, v10, v11
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v13
-; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v14
-; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v14
-; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v12, v9
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v13, v12
-; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v11
-; CGP-NEXT:    v_addc_u32_e32 v8, vcc, v8, v10, vcc
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
-; CGP-NEXT:    v_addc_u32_e32 v8, vcc, 0, v8, vcc
-; CGP-NEXT:    v_mul_lo_u32 v9, v1, v7
-; CGP-NEXT:    v_mul_lo_u32 v10, v0, v8
-; CGP-NEXT:    v_mul_hi_u32 v11, v0, v7
-; CGP-NEXT:    v_mul_hi_u32 v7, v1, v7
-; CGP-NEXT:    v_ashrrev_i32_e32 v6, 31, v3
+; CGP-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
+; CGP-NEXT:    v_mul_lo_u32 v9, -1, v6
+; CGP-NEXT:    v_mul_lo_u32 v8, s6, v7
+; CGP-NEXT:    v_mul_hi_u32 v10, s6, v6
+; CGP-NEXT:    v_mul_lo_u32 v11, s6, v6
+; CGP-NEXT:    v_trunc_f32_e32 v5, v5
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; CGP-NEXT:    v_mul_lo_u32 v9, v7, v11
+; CGP-NEXT:    v_mul_lo_u32 v10, v6, v8
+; CGP-NEXT:    v_mul_hi_u32 v13, v6, v11
+; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v12
+; CGP-NEXT:    v_addc_u32_e32 v1, vcc, v1, v12, vcc
 ; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
+; CGP-NEXT:    v_mul_lo_u32 v14, v7, v8
+; CGP-NEXT:    v_mul_hi_u32 v11, v7, v11
 ; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v13
+; CGP-NEXT:    v_mul_hi_u32 v13, v6, v8
 ; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v11, v1, v8
 ; CGP-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
-; CGP-NEXT:    v_mul_hi_u32 v10, v0, v8
-; CGP-NEXT:    v_mul_hi_u32 v8, v1, v8
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v11, v7
-; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
-; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
-; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
-; CGP-NEXT:    v_mul_lo_u32 v9, 0, v7
-; CGP-NEXT:    v_mul_lo_u32 v10, s7, v8
-; CGP-NEXT:    v_mul_hi_u32 v12, s7, v7
-; CGP-NEXT:    v_mul_lo_u32 v11, s7, v7
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
-; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v0, v11
-; CGP-NEXT:    v_subb_u32_e64 v10, s[4:5], v1, v9, vcc
-; CGP-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v9
-; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], 0, v10
-; CGP-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], s7, v0
-; CGP-NEXT:    v_subrev_i32_e32 v0, vcc, s7, v0
-; CGP-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v10
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, 1, v7
-; CGP-NEXT:    v_cndmask_b32_e64 v9, v9, v11, s[4:5]
-; CGP-NEXT:    v_addc_u32_e32 v11, vcc, 0, v8, vcc
-; CGP-NEXT:    v_cmp_le_u32_e32 vcc, 0, v1
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, -1, vcc
-; CGP-NEXT:    v_cmp_le_u32_e32 vcc, s7, v0
-; CGP-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
-; CGP-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
-; CGP-NEXT:    v_cndmask_b32_e32 v0, v12, v0, vcc
-; CGP-NEXT:    v_add_i32_e32 v1, vcc, 1, v10
-; CGP-NEXT:    v_addc_u32_e32 v12, vcc, 0, v11, vcc
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
-; CGP-NEXT:    v_cndmask_b32_e32 v0, v10, v1, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v1, v11, v12, vcc
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v9
-; CGP-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc
-; CGP-NEXT:    v_mul_f32_e32 v7, 0x2f800000, v4
-; CGP-NEXT:    v_trunc_f32_e32 v7, v7
-; CGP-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v7
-; CGP-NEXT:    v_cvt_u32_f32_e32 v4, v4
-; CGP-NEXT:    v_cvt_u32_f32_e32 v7, v7
-; CGP-NEXT:    v_cndmask_b32_e32 v1, v8, v1, vcc
-; CGP-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
-; CGP-NEXT:    v_mul_lo_u32 v8, -1, v4
-; CGP-NEXT:    v_mul_lo_u32 v9, s6, v7
-; CGP-NEXT:    v_mul_hi_u32 v11, s6, v4
-; CGP-NEXT:    v_mul_lo_u32 v10, s6, v4
-; CGP-NEXT:    v_addc_u32_e32 v3, vcc, v3, v6, vcc
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
-; CGP-NEXT:    v_mul_lo_u32 v9, v7, v10
-; CGP-NEXT:    v_mul_lo_u32 v11, v4, v8
-; CGP-NEXT:    v_mul_hi_u32 v12, v4, v10
-; CGP-NEXT:    v_mul_hi_u32 v10, v7, v10
-; CGP-NEXT:    v_xor_b32_e32 v0, v0, v5
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v14, v11
 ; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
-; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v12, v7, v8
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v11, v9
-; CGP-NEXT:    v_mul_hi_u32 v11, v4, v8
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v13
+; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v11, vcc, v11, v13
 ; CGP-NEXT:    v_mul_hi_u32 v8, v7, v8
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v12, v10
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
-; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
 ; CGP-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
 ; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
 ; CGP-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
 ; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v9
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
 ; CGP-NEXT:    v_addc_u32_e64 v9, s[4:5], v7, v8, vcc
-; CGP-NEXT:    v_mul_lo_u32 v10, -1, v4
+; CGP-NEXT:    v_mul_lo_u32 v10, -1, v6
 ; CGP-NEXT:    v_mul_lo_u32 v11, s6, v9
-; CGP-NEXT:    v_mul_hi_u32 v13, s6, v4
-; CGP-NEXT:    v_mul_lo_u32 v12, s6, v4
+; CGP-NEXT:    v_mul_hi_u32 v13, s6, v6
+; CGP-NEXT:    v_mul_lo_u32 v14, s6, v6
 ; CGP-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v8
 ; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v11
 ; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v13
-; CGP-NEXT:    v_mul_lo_u32 v11, v9, v12
-; CGP-NEXT:    v_mul_lo_u32 v13, v4, v10
-; CGP-NEXT:    v_mul_hi_u32 v8, v4, v12
-; CGP-NEXT:    v_mul_hi_u32 v12, v9, v12
-; CGP-NEXT:    v_xor_b32_e32 v2, v2, v6
+; CGP-NEXT:    v_mul_lo_u32 v11, v9, v14
+; CGP-NEXT:    v_mul_lo_u32 v13, v6, v10
+; CGP-NEXT:    v_mul_hi_u32 v8, v6, v14
+; CGP-NEXT:    v_mul_lo_u32 v15, v9, v10
+; CGP-NEXT:    v_mul_hi_u32 v14, v9, v14
 ; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v13
 ; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
 ; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v11, v8
+; CGP-NEXT:    v_mul_hi_u32 v11, v6, v10
 ; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
-; CGP-NEXT:    v_mul_lo_u32 v11, v9, v10
 ; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v13, v8
-; CGP-NEXT:    v_mul_hi_u32 v13, v4, v10
-; CGP-NEXT:    v_mul_hi_u32 v9, v9, v10
-; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v13
+; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v15, v14
+; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v13, v11
 ; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v13
+; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v14, v13
+; CGP-NEXT:    v_mul_hi_u32 v9, v9, v10
 ; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v11, v8
-; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v12, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v13, v10
 ; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v10
 ; CGP-NEXT:    v_addc_u32_e32 v7, vcc, v7, v9, vcc
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; CGP-NEXT:    v_xor_b32_e32 v0, v0, v12
+; CGP-NEXT:    v_xor_b32_e32 v1, v1, v12
 ; CGP-NEXT:    v_addc_u32_e32 v7, vcc, 0, v7, vcc
-; CGP-NEXT:    v_xor_b32_e32 v3, v3, v6
-; CGP-NEXT:    v_xor_b32_e32 v1, v1, v5
-; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v0, v5
-; CGP-NEXT:    v_mul_lo_u32 v8, v3, v4
-; CGP-NEXT:    v_mul_lo_u32 v9, v2, v7
-; CGP-NEXT:    v_subb_u32_e32 v1, vcc, v1, v5, vcc
-; CGP-NEXT:    v_mul_hi_u32 v5, v2, v4
-; CGP-NEXT:    v_mul_hi_u32 v4, v3, v4
+; CGP-NEXT:    v_mul_lo_u32 v8, v1, v6
+; CGP-NEXT:    v_mul_lo_u32 v9, v0, v7
+; CGP-NEXT:    v_mul_hi_u32 v10, v0, v6
+; CGP-NEXT:    v_mul_lo_u32 v11, v1, v7
+; CGP-NEXT:    v_mul_hi_u32 v6, v1, v6
 ; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
 ; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; CGP-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v8, v3, v7
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v9, v5
-; CGP-NEXT:    v_mul_hi_u32 v9, v2, v7
-; CGP-NEXT:    v_mul_hi_u32 v7, v3, v7
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v8, v4
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; CGP-NEXT:    v_mul_hi_u32 v10, v0, v7
 ; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v9
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v11, v6
 ; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v10
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
+; CGP-NEXT:    v_mul_hi_u32 v7, v1, v7
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; CGP-NEXT:    v_mul_lo_u32 v8, 0, v6
+; CGP-NEXT:    v_mul_lo_u32 v9, s7, v7
+; CGP-NEXT:    v_mul_hi_u32 v10, s7, v6
+; CGP-NEXT:    v_mul_lo_u32 v11, s7, v6
+; CGP-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
 ; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
-; CGP-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v0, v11
+; CGP-NEXT:    v_subb_u32_e64 v9, s[4:5], v1, v8, vcc
+; CGP-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v8
+; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], 0, v9
+; CGP-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], s7, v0
+; CGP-NEXT:    v_subrev_i32_e32 v0, vcc, s7, v0
+; CGP-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v9
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, 1, v6
+; CGP-NEXT:    v_cndmask_b32_e64 v8, v8, v10, s[4:5]
+; CGP-NEXT:    v_addc_u32_e32 v10, vcc, 0, v7, vcc
+; CGP-NEXT:    v_cmp_le_u32_e32 vcc, 0, v1
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, -1, vcc
+; CGP-NEXT:    v_cmp_le_u32_e32 vcc, s7, v0
+; CGP-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
+; CGP-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
+; CGP-NEXT:    v_cndmask_b32_e32 v0, v11, v0, vcc
+; CGP-NEXT:    v_add_i32_e32 v1, vcc, 1, v9
+; CGP-NEXT:    v_cvt_u32_f32_e32 v4, v4
+; CGP-NEXT:    v_cvt_u32_f32_e32 v5, v5
+; CGP-NEXT:    v_addc_u32_e32 v11, vcc, 0, v10, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
+; CGP-NEXT:    v_cndmask_b32_e32 v0, v9, v1, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v1, v10, v11, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v8
+; CGP-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v1, v7, v1, vcc
+; CGP-NEXT:    v_mul_lo_u32 v6, -1, v4
+; CGP-NEXT:    v_mul_lo_u32 v7, s6, v5
+; CGP-NEXT:    v_mul_hi_u32 v8, s6, v4
+; CGP-NEXT:    v_mul_lo_u32 v9, s6, v4
+; CGP-NEXT:    v_ashrrev_i32_e32 v10, 31, v3
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; CGP-NEXT:    v_mul_lo_u32 v7, v5, v9
+; CGP-NEXT:    v_mul_lo_u32 v8, v4, v6
+; CGP-NEXT:    v_mul_hi_u32 v11, v4, v9
+; CGP-NEXT:    v_add_i32_e32 v2, vcc, v2, v10
+; CGP-NEXT:    v_addc_u32_e32 v3, vcc, v3, v10, vcc
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; CGP-NEXT:    v_mul_lo_u32 v13, v5, v6
+; CGP-NEXT:    v_mul_hi_u32 v9, v5, v9
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v11
+; CGP-NEXT:    v_mul_hi_u32 v11, v4, v6
+; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v13, v9
+; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; CGP-NEXT:    v_mul_hi_u32 v6, v5, v6
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; CGP-NEXT:    v_addc_u32_e64 v7, s[4:5], v5, v6, vcc
+; CGP-NEXT:    v_mul_lo_u32 v8, -1, v4
+; CGP-NEXT:    v_mul_lo_u32 v9, s6, v7
+; CGP-NEXT:    v_mul_hi_u32 v11, s6, v4
+; CGP-NEXT:    v_mul_lo_u32 v13, s6, v4
+; CGP-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v6
+; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
+; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v11
+; CGP-NEXT:    v_mul_lo_u32 v9, v7, v13
+; CGP-NEXT:    v_mul_lo_u32 v11, v4, v8
+; CGP-NEXT:    v_mul_hi_u32 v6, v4, v13
+; CGP-NEXT:    v_mul_lo_u32 v14, v7, v8
+; CGP-NEXT:    v_mul_hi_u32 v13, v7, v13
+; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v6, s[4:5], v9, v6
+; CGP-NEXT:    v_mul_hi_u32 v9, v4, v8
+; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v6, s[4:5], v11, v6
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v14, v13
+; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v9
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v13, v11
+; CGP-NEXT:    v_mul_hi_u32 v7, v7, v8
+; CGP-NEXT:    v_add_i32_e64 v6, s[4:5], v9, v6
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v11, v8
+; CGP-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v8
+; CGP-NEXT:    v_addc_u32_e32 v5, vcc, v5, v7, vcc
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; CGP-NEXT:    v_xor_b32_e32 v2, v2, v10
+; CGP-NEXT:    v_xor_b32_e32 v3, v3, v10
+; CGP-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; CGP-NEXT:    v_mul_lo_u32 v6, v3, v4
+; CGP-NEXT:    v_mul_lo_u32 v7, v2, v5
+; CGP-NEXT:    v_mul_hi_u32 v8, v2, v4
+; CGP-NEXT:    v_mul_lo_u32 v9, v3, v5
+; CGP-NEXT:    v_mul_hi_u32 v4, v3, v4
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; CGP-NEXT:    v_mul_hi_u32 v8, v2, v5
+; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v9, v4
+; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; CGP-NEXT:    v_mul_hi_u32 v5, v3, v5
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
 ; CGP-NEXT:    v_mul_lo_u32 v7, 0, v4
 ; CGP-NEXT:    v_mul_lo_u32 v8, s7, v5
-; CGP-NEXT:    v_mul_hi_u32 v10, s7, v4
-; CGP-NEXT:    v_mul_lo_u32 v9, s7, v4
+; CGP-NEXT:    v_mul_hi_u32 v9, s7, v4
+; CGP-NEXT:    v_xor_b32_e32 v0, v0, v12
+; CGP-NEXT:    v_mul_lo_u32 v6, s7, v4
+; CGP-NEXT:    v_xor_b32_e32 v1, v1, v12
+; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v0, v12
+; CGP-NEXT:    v_subb_u32_e32 v1, vcc, v1, v12, vcc
 ; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
-; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v2, v9
-; CGP-NEXT:    v_subb_u32_e64 v8, s[4:5], v3, v7, vcc
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v2, v6
+; CGP-NEXT:    v_subb_u32_e64 v6, s[4:5], v3, v7, vcc
 ; CGP-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v7
-; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], 0, v8
+; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], 0, v6
 ; CGP-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
 ; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
 ; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], s7, v2
 ; CGP-NEXT:    v_subrev_i32_e32 v2, vcc, s7, v2
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v6
 ; CGP-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v8
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, 1, v4
-; CGP-NEXT:    v_cndmask_b32_e64 v7, v7, v9, s[4:5]
-; CGP-NEXT:    v_addc_u32_e32 v9, vcc, 0, v5, vcc
+; CGP-NEXT:    v_cndmask_b32_e64 v6, v7, v8, s[4:5]
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, 1, v4
+; CGP-NEXT:    v_addc_u32_e32 v8, vcc, 0, v5, vcc
 ; CGP-NEXT:    v_cmp_le_u32_e32 vcc, 0, v3
-; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, -1, vcc
+; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
 ; CGP-NEXT:    v_cmp_le_u32_e32 vcc, s7, v2
 ; CGP-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
 ; CGP-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v3
-; CGP-NEXT:    v_cndmask_b32_e32 v2, v10, v2, vcc
-; CGP-NEXT:    v_add_i32_e32 v3, vcc, 1, v8
-; CGP-NEXT:    v_addc_u32_e32 v10, vcc, 0, v9, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v2, v9, v2, vcc
+; CGP-NEXT:    v_add_i32_e32 v3, vcc, 1, v7
+; CGP-NEXT:    v_addc_u32_e32 v9, vcc, 0, v8, vcc
 ; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
-; CGP-NEXT:    v_cndmask_b32_e32 v2, v8, v3, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v3, v9, v10, vcc
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
+; CGP-NEXT:    v_cndmask_b32_e32 v2, v7, v3, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v3, v8, v9, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
 ; CGP-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
 ; CGP-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc
-; CGP-NEXT:    v_xor_b32_e32 v2, v2, v6
-; CGP-NEXT:    v_xor_b32_e32 v3, v3, v6
-; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v2, v6
-; CGP-NEXT:    v_subb_u32_e32 v3, vcc, v3, v6, vcc
+; CGP-NEXT:    v_xor_b32_e32 v2, v2, v10
+; CGP-NEXT:    v_xor_b32_e32 v3, v3, v10
+; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v2, v10
+; CGP-NEXT:    v_subb_u32_e32 v3, vcc, v3, v10, vcc
 ; CGP-NEXT:    s_setpc_b64 s[30:31]
   %result = sdiv <2 x i64> %num, <i64 1235195, i64 1235195>
   ret <2 x i64> %result
@@ -2521,137 +2521,137 @@
 ; CHECK-NEXT:    v_xor_b32_e32 v5, v5, v2
 ; CHECK-NEXT:    v_cvt_f32_u32_e32 v6, v3
 ; CHECK-NEXT:    v_cvt_f32_u32_e32 v7, v5
-; CHECK-NEXT:    v_ashrrev_i32_e32 v8, 31, v1
+; CHECK-NEXT:    v_sub_i32_e32 v8, vcc, 0, v3
+; CHECK-NEXT:    v_subb_u32_e32 v9, vcc, 0, v5, vcc
+; CHECK-NEXT:    v_ashrrev_i32_e32 v14, 31, v1
 ; CHECK-NEXT:    v_mac_f32_e32 v6, 0x4f800000, v7
 ; CHECK-NEXT:    v_rcp_iflag_f32_e32 v6, v6
-; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v0, v8
-; CHECK-NEXT:    v_addc_u32_e32 v1, vcc, v1, v8, vcc
-; CHECK-NEXT:    v_sub_i32_e32 v10, vcc, 0, v3
 ; CHECK-NEXT:    v_mul_f32_e32 v6, 0x5f7ffffc, v6
-; CHECK-NEXT:    v_mul_f32_e32 v9, 0x2f800000, v6
-; CHECK-NEXT:    v_trunc_f32_e32 v9, v9
-; CHECK-NEXT:    v_mac_f32_e32 v6, 0xcf800000, v9
+; CHECK-NEXT:    v_mul_f32_e32 v7, 0x2f800000, v6
+; CHECK-NEXT:    v_trunc_f32_e32 v7, v7
+; CHECK-NEXT:    v_mac_f32_e32 v6, 0xcf800000, v7
 ; CHECK-NEXT:    v_cvt_u32_f32_e32 v6, v6
-; CHECK-NEXT:    v_cvt_u32_f32_e32 v9, v9
-; CHECK-NEXT:    v_subb_u32_e32 v11, vcc, 0, v5, vcc
-; CHECK-NEXT:    v_xor_b32_e32 v7, v7, v8
-; CHECK-NEXT:    v_mul_lo_u32 v12, v11, v6
-; CHECK-NEXT:    v_mul_lo_u32 v13, v10, v9
-; CHECK-NEXT:    v_mul_hi_u32 v15, v10, v6
-; CHECK-NEXT:    v_mul_lo_u32 v14, v10, v6
-; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v8
-; CHECK-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
-; CHECK-NEXT:    v_add_i32_e32 v12, vcc, v12, v15
-; CHECK-NEXT:    v_mul_lo_u32 v13, v9, v14
-; CHECK-NEXT:    v_mul_lo_u32 v15, v6, v12
-; CHECK-NEXT:    v_mul_hi_u32 v16, v6, v14
-; CHECK-NEXT:    v_mul_hi_u32 v14, v9, v14
-; CHECK-NEXT:    v_add_i32_e32 v13, vcc, v13, v15
-; CHECK-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v13, vcc, v13, v16
+; CHECK-NEXT:    v_cvt_u32_f32_e32 v7, v7
+; CHECK-NEXT:    v_mul_lo_u32 v11, v9, v6
+; CHECK-NEXT:    v_mul_lo_u32 v10, v8, v7
+; CHECK-NEXT:    v_mul_hi_u32 v13, v8, v6
+; CHECK-NEXT:    v_mul_lo_u32 v12, v8, v6
+; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v10, v13
+; CHECK-NEXT:    v_mul_lo_u32 v11, v7, v12
+; CHECK-NEXT:    v_mul_lo_u32 v13, v6, v10
+; CHECK-NEXT:    v_mul_hi_u32 v16, v6, v12
+; CHECK-NEXT:    v_add_i32_e32 v15, vcc, v0, v14
+; CHECK-NEXT:    v_addc_u32_e32 v1, vcc, v1, v14, vcc
+; CHECK-NEXT:    v_add_i32_e32 v11, vcc, v11, v13
+; CHECK-NEXT:    v_mul_lo_u32 v17, v7, v10
+; CHECK-NEXT:    v_mul_hi_u32 v12, v7, v12
+; CHECK-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v11, vcc, v11, v16
+; CHECK-NEXT:    v_mul_hi_u32 v16, v6, v10
+; CHECK-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v11, vcc, v13, v11
+; CHECK-NEXT:    v_add_i32_e32 v12, vcc, v17, v12
 ; CHECK-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v16, v9, v12
-; CHECK-NEXT:    v_add_i32_e32 v13, vcc, v15, v13
-; CHECK-NEXT:    v_mul_hi_u32 v15, v6, v12
-; CHECK-NEXT:    v_mul_hi_u32 v12, v9, v12
-; CHECK-NEXT:    v_add_i32_e32 v14, vcc, v16, v14
+; CHECK-NEXT:    v_add_i32_e32 v12, vcc, v12, v16
 ; CHECK-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v14, vcc, v14, v15
-; CHECK-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v15, vcc, v16, v15
-; CHECK-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
-; CHECK-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
-; CHECK-NEXT:    v_add_i32_e32 v12, vcc, v12, v14
-; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v13
-; CHECK-NEXT:    v_addc_u32_e64 v13, s[4:5], v9, v12, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v11, v11, v6
-; CHECK-NEXT:    v_mul_lo_u32 v14, v10, v13
-; CHECK-NEXT:    v_mul_lo_u32 v15, v10, v6
-; CHECK-NEXT:    v_mul_hi_u32 v10, v10, v6
+; CHECK-NEXT:    v_add_i32_e32 v13, vcc, v13, v16
+; CHECK-NEXT:    v_mul_hi_u32 v10, v7, v10
+; CHECK-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
+; CHECK-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
+; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
+; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v11
+; CHECK-NEXT:    v_addc_u32_e64 v11, s[4:5], v7, v10, vcc
+; CHECK-NEXT:    v_mul_lo_u32 v9, v9, v6
+; CHECK-NEXT:    v_mul_lo_u32 v12, v8, v11
+; CHECK-NEXT:    v_mul_hi_u32 v13, v8, v6
+; CHECK-NEXT:    v_mul_lo_u32 v8, v8, v6
+; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v10
 ; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v12
-; CHECK-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v14
-; CHECK-NEXT:    v_mul_hi_u32 v12, v6, v15
-; CHECK-NEXT:    v_add_i32_e64 v10, s[4:5], v11, v10
-; CHECK-NEXT:    v_mul_lo_u32 v11, v13, v15
-; CHECK-NEXT:    v_mul_lo_u32 v14, v6, v10
-; CHECK-NEXT:    v_mul_hi_u32 v15, v13, v15
-; CHECK-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v14
-; CHECK-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
-; CHECK-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; CHECK-NEXT:    v_mul_lo_u32 v12, v13, v10
-; CHECK-NEXT:    v_add_i32_e64 v11, s[4:5], v14, v11
-; CHECK-NEXT:    v_mul_hi_u32 v14, v6, v10
-; CHECK-NEXT:    v_mul_hi_u32 v10, v13, v10
-; CHECK-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v15
-; CHECK-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v14
-; CHECK-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v14, s[4:5], v15, v14
-; CHECK-NEXT:    v_add_i32_e64 v11, s[4:5], v12, v11
+; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v13
+; CHECK-NEXT:    v_mul_lo_u32 v12, v11, v8
+; CHECK-NEXT:    v_mul_lo_u32 v13, v6, v9
+; CHECK-NEXT:    v_mul_hi_u32 v10, v6, v8
+; CHECK-NEXT:    v_mul_lo_u32 v16, v11, v9
+; CHECK-NEXT:    v_mul_hi_u32 v8, v11, v8
+; CHECK-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v13
+; CHECK-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v10, s[4:5], v12, v10
+; CHECK-NEXT:    v_mul_hi_u32 v12, v6, v9
+; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v10, s[4:5], v13, v10
+; CHECK-NEXT:    v_add_i32_e64 v8, s[4:5], v16, v8
+; CHECK-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v12
 ; CHECK-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v12, s[4:5], v14, v12
-; CHECK-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v12
-; CHECK-NEXT:    v_addc_u32_e32 v9, vcc, v9, v10, vcc
-; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v11
-; CHECK-NEXT:    v_addc_u32_e32 v9, vcc, 0, v9, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v10, v1, v6
-; CHECK-NEXT:    v_mul_lo_u32 v11, v7, v9
-; CHECK-NEXT:    v_mul_hi_u32 v12, v7, v6
+; CHECK-NEXT:    v_add_i32_e64 v12, s[4:5], v13, v12
+; CHECK-NEXT:    v_mul_hi_u32 v9, v11, v9
+; CHECK-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v10
+; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v10, s[4:5], v12, v10
+; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v10
+; CHECK-NEXT:    v_addc_u32_e32 v7, vcc, v7, v9, vcc
+; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; CHECK-NEXT:    v_xor_b32_e32 v15, v15, v14
+; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v14
+; CHECK-NEXT:    v_addc_u32_e32 v7, vcc, 0, v7, vcc
+; CHECK-NEXT:    v_mul_lo_u32 v8, v1, v6
+; CHECK-NEXT:    v_mul_lo_u32 v9, v15, v7
+; CHECK-NEXT:    v_mul_hi_u32 v10, v15, v6
+; CHECK-NEXT:    v_mul_lo_u32 v11, v1, v7
 ; CHECK-NEXT:    v_mul_hi_u32 v6, v1, v6
-; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
-; CHECK-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
-; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v12, v1, v9
-; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; CHECK-NEXT:    v_mul_hi_u32 v11, v7, v9
-; CHECK-NEXT:    v_mul_hi_u32 v9, v1, v9
-; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v12, v6
-; CHECK-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v11
-; CHECK-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
+; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
+; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; CHECK-NEXT:    v_mul_hi_u32 v10, v15, v7
+; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v11, v6
+; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v10
 ; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
 ; CHECK-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; CHECK-NEXT:    v_mul_lo_u32 v10, v5, v6
-; CHECK-NEXT:    v_mul_lo_u32 v11, v3, v9
-; CHECK-NEXT:    v_mul_hi_u32 v13, v3, v6
-; CHECK-NEXT:    v_mul_lo_u32 v12, v3, v6
-; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
-; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v10, v13
-; CHECK-NEXT:    v_sub_i32_e32 v7, vcc, v7, v12
-; CHECK-NEXT:    v_subb_u32_e64 v11, s[4:5], v1, v10, vcc
-; CHECK-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v10
-; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v11, v5
+; CHECK-NEXT:    v_mul_hi_u32 v7, v1, v7
+; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; CHECK-NEXT:    v_mul_lo_u32 v8, v5, v6
+; CHECK-NEXT:    v_mul_lo_u32 v9, v3, v7
+; CHECK-NEXT:    v_mul_hi_u32 v10, v3, v6
+; CHECK-NEXT:    v_mul_lo_u32 v11, v3, v6
+; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
+; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; CHECK-NEXT:    v_sub_i32_e32 v9, vcc, v15, v11
+; CHECK-NEXT:    v_subb_u32_e64 v10, s[4:5], v1, v8, vcc
+; CHECK-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v8
+; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v10, v5
 ; CHECK-NEXT:    v_subb_u32_e32 v1, vcc, v1, v5, vcc
-; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
-; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v3
-; CHECK-NEXT:    v_sub_i32_e32 v7, vcc, v7, v3
+; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
+; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v9, v3
+; CHECK-NEXT:    v_sub_i32_e32 v9, vcc, v9, v3
 ; CHECK-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CHECK-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[4:5]
-; CHECK-NEXT:    v_cmp_eq_u32_e64 s[4:5], v11, v5
-; CHECK-NEXT:    v_add_i32_e32 v11, vcc, 1, v6
-; CHECK-NEXT:    v_cndmask_b32_e64 v10, v10, v12, s[4:5]
-; CHECK-NEXT:    v_addc_u32_e32 v12, vcc, 0, v9, vcc
+; CHECK-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
+; CHECK-NEXT:    v_cmp_eq_u32_e64 s[4:5], v10, v5
+; CHECK-NEXT:    v_add_i32_e32 v10, vcc, 1, v6
+; CHECK-NEXT:    v_cndmask_b32_e64 v8, v8, v11, s[4:5]
+; CHECK-NEXT:    v_addc_u32_e32 v11, vcc, 0, v7, vcc
 ; CHECK-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v5
-; CHECK-NEXT:    v_cndmask_b32_e64 v13, 0, -1, vcc
-; CHECK-NEXT:    v_cmp_ge_u32_e32 vcc, v7, v3
+; CHECK-NEXT:    v_cndmask_b32_e64 v12, 0, -1, vcc
+; CHECK-NEXT:    v_cmp_ge_u32_e32 vcc, v9, v3
 ; CHECK-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
 ; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v5
-; CHECK-NEXT:    v_cndmask_b32_e32 v1, v13, v3, vcc
-; CHECK-NEXT:    v_add_i32_e32 v3, vcc, 1, v11
-; CHECK-NEXT:    v_addc_u32_e32 v5, vcc, 0, v12, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v1, v12, v3, vcc
+; CHECK-NEXT:    v_add_i32_e32 v3, vcc, 1, v10
+; CHECK-NEXT:    v_addc_u32_e32 v5, vcc, 0, v11, vcc
 ; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1
-; CHECK-NEXT:    v_cndmask_b32_e32 v1, v11, v3, vcc
-; CHECK-NEXT:    v_cndmask_b32_e32 v3, v12, v5, vcc
-; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
+; CHECK-NEXT:    v_cndmask_b32_e32 v1, v10, v3, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v3, v11, v5, vcc
+; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v8
 ; CHECK-NEXT:    v_cndmask_b32_e32 v1, v6, v1, vcc
-; CHECK-NEXT:    v_xor_b32_e32 v5, v8, v2
-; CHECK-NEXT:    v_cndmask_b32_e32 v3, v9, v3, vcc
+; CHECK-NEXT:    v_xor_b32_e32 v5, v14, v2
+; CHECK-NEXT:    v_cndmask_b32_e32 v3, v7, v3, vcc
 ; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v5
 ; CHECK-NEXT:    v_xor_b32_e32 v3, v3, v5
 ; CHECK-NEXT:    v_sub_i32_e32 v2, vcc, v1, v5
@@ -2698,7 +2698,7 @@
 ; GISEL-NEXT:    s_movk_i32 s6, 0x1000
 ; GISEL-NEXT:    s_mov_b32 s7, 0
 ; GISEL-NEXT:    v_lshl_b64 v[4:5], s[6:7], v4
-; GISEL-NEXT:    v_ashrrev_i32_e32 v10, 31, v1
+; GISEL-NEXT:    v_ashrrev_i32_e32 v16, 31, v1
 ; GISEL-NEXT:    v_ashrrev_i32_e32 v7, 31, v5
 ; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
 ; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v7, vcc
@@ -2706,279 +2706,279 @@
 ; GISEL-NEXT:    v_xor_b32_e32 v5, v5, v7
 ; GISEL-NEXT:    v_cvt_f32_u32_e32 v8, v4
 ; GISEL-NEXT:    v_cvt_f32_u32_e32 v9, v5
-; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v10
-; GISEL-NEXT:    v_addc_u32_e32 v1, vcc, v1, v10, vcc
-; GISEL-NEXT:    v_sub_i32_e32 v11, vcc, 0, v4
+; GISEL-NEXT:    v_sub_i32_e32 v10, vcc, 0, v4
+; GISEL-NEXT:    v_subb_u32_e32 v11, vcc, 0, v5, vcc
 ; GISEL-NEXT:    v_mac_f32_e32 v8, 0x4f800000, v9
 ; GISEL-NEXT:    v_rcp_iflag_f32_e32 v8, v8
-; GISEL-NEXT:    v_xor_b32_e32 v9, v0, v10
-; GISEL-NEXT:    v_subb_u32_e32 v12, vcc, 0, v5, vcc
-; GISEL-NEXT:    v_xor_b32_e32 v17, v1, v10
-; GISEL-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v8
-; GISEL-NEXT:    v_mul_f32_e32 v8, 0x2f800000, v0
-; GISEL-NEXT:    v_trunc_f32_e32 v8, v8
-; GISEL-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v8
-; GISEL-NEXT:    v_cvt_u32_f32_e32 v0, v0
+; GISEL-NEXT:    v_mul_f32_e32 v8, 0x5f7ffffc, v8
+; GISEL-NEXT:    v_mul_f32_e32 v9, 0x2f800000, v8
+; GISEL-NEXT:    v_trunc_f32_e32 v9, v9
+; GISEL-NEXT:    v_mac_f32_e32 v8, 0xcf800000, v9
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v8, v8
-; GISEL-NEXT:    v_mul_lo_u32 v13, v12, v0
-; GISEL-NEXT:    v_mul_lo_u32 v14, v11, v8
-; GISEL-NEXT:    v_mul_hi_u32 v16, v11, v0
-; GISEL-NEXT:    v_mul_lo_u32 v15, v11, v0
+; GISEL-NEXT:    v_cvt_u32_f32_e32 v9, v9
+; GISEL-NEXT:    v_mul_lo_u32 v12, v11, v8
+; GISEL-NEXT:    v_mul_lo_u32 v13, v10, v9
+; GISEL-NEXT:    v_mul_hi_u32 v14, v10, v8
+; GISEL-NEXT:    v_mul_lo_u32 v15, v10, v8
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v14
+; GISEL-NEXT:    v_mul_lo_u32 v13, v9, v15
+; GISEL-NEXT:    v_mul_lo_u32 v14, v8, v12
+; GISEL-NEXT:    v_mul_hi_u32 v17, v8, v15
+; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v16
+; GISEL-NEXT:    v_addc_u32_e32 v1, vcc, v1, v16, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v14
-; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v16
-; GISEL-NEXT:    v_mul_lo_u32 v14, v8, v15
-; GISEL-NEXT:    v_mul_lo_u32 v16, v0, v13
-; GISEL-NEXT:    v_mul_hi_u32 v1, v0, v15
-; GISEL-NEXT:    v_mul_hi_u32 v15, v8, v15
-; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v16
-; GISEL-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v1, vcc, v14, v1
-; GISEL-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v14, v8, v13
-; GISEL-NEXT:    v_add_i32_e32 v1, vcc, v16, v1
-; GISEL-NEXT:    v_mul_hi_u32 v16, v0, v13
-; GISEL-NEXT:    v_mul_hi_u32 v13, v8, v13
-; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v15
+; GISEL-NEXT:    v_mul_lo_u32 v18, v9, v12
+; GISEL-NEXT:    v_mul_hi_u32 v15, v9, v15
+; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v17
+; GISEL-NEXT:    v_mul_hi_u32 v17, v8, v12
+; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
+; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v18, v15
 ; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v16
-; GISEL-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v15, vcc, v15, v16
-; GISEL-NEXT:    v_add_i32_e32 v1, vcc, v14, v1
+; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v17
+; GISEL-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v15, vcc, v15, v17
+; GISEL-NEXT:    v_mul_hi_u32 v12, v9, v12
+; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
 ; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
-; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v14
-; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
-; GISEL-NEXT:    v_addc_u32_e64 v1, s[4:5], v8, v13, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v12, v12, v0
-; GISEL-NEXT:    v_mul_lo_u32 v14, v11, v1
-; GISEL-NEXT:    v_mul_lo_u32 v15, v11, v0
-; GISEL-NEXT:    v_mul_hi_u32 v11, v11, v0
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v13
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v14
-; GISEL-NEXT:    v_mul_hi_u32 v13, v0, v15
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v12, v11
-; GISEL-NEXT:    v_mul_lo_u32 v12, v1, v15
-; GISEL-NEXT:    v_mul_lo_u32 v14, v0, v11
-; GISEL-NEXT:    v_mul_hi_u32 v15, v1, v15
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v14
-; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v13
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_mul_lo_u32 v13, v1, v11
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v14, v12
-; GISEL-NEXT:    v_mul_hi_u32 v14, v0, v11
-; GISEL-NEXT:    v_mul_hi_u32 v1, v1, v11
-; GISEL-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v15
-; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v14
-; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v14, s[4:5], v15, v14
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v13, v12
-; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v14, v13
-; GISEL-NEXT:    v_add_i32_e64 v1, s[4:5], v1, v11
-; GISEL-NEXT:    v_addc_u32_e32 v1, vcc, v8, v1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v0, v12
-; GISEL-NEXT:    v_addc_u32_e32 v11, vcc, 0, v1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v12, v17, v8
-; GISEL-NEXT:    v_mul_lo_u32 v13, v9, v11
-; GISEL-NEXT:    v_lshl_b64 v[0:1], s[6:7], v6
-; GISEL-NEXT:    v_mul_hi_u32 v6, v9, v8
-; GISEL-NEXT:    v_mul_hi_u32 v8, v17, v8
-; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
-; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v12, v6
-; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v12, v17, v11
-; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v13, v6
-; GISEL-NEXT:    v_mul_hi_u32 v13, v9, v11
-; GISEL-NEXT:    v_mul_hi_u32 v11, v17, v11
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v12, v8
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v14
 ; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v13
-; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
-; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
+; GISEL-NEXT:    v_addc_u32_e64 v13, s[4:5], v9, v12, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v11, v11, v8
+; GISEL-NEXT:    v_mul_lo_u32 v14, v10, v13
+; GISEL-NEXT:    v_mul_hi_u32 v15, v10, v8
+; GISEL-NEXT:    v_mul_lo_u32 v10, v10, v8
+; GISEL-NEXT:    v_xor_b32_e32 v17, v0, v16
+; GISEL-NEXT:    v_add_i32_e64 v0, s[4:5], v11, v14
+; GISEL-NEXT:    v_add_i32_e64 v0, s[4:5], v0, v15
+; GISEL-NEXT:    v_mul_lo_u32 v11, v13, v10
+; GISEL-NEXT:    v_mul_lo_u32 v14, v8, v0
+; GISEL-NEXT:    v_xor_b32_e32 v15, v1, v16
+; GISEL-NEXT:    v_add_i32_e64 v1, s[4:5], v9, v12
+; GISEL-NEXT:    v_mul_hi_u32 v9, v8, v10
+; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v14
+; GISEL-NEXT:    v_mul_lo_u32 v14, v13, v0
+; GISEL-NEXT:    v_mul_hi_u32 v10, v13, v10
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v9
+; GISEL-NEXT:    v_mul_hi_u32 v11, v8, v0
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v12, v9
+; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v14, v10
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v11
+; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v12, v11
+; GISEL-NEXT:    v_mul_hi_u32 v0, v13, v0
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v10, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v11, v10
+; GISEL-NEXT:    v_add_i32_e64 v0, s[4:5], v0, v10
+; GISEL-NEXT:    v_addc_u32_e32 v0, vcc, v1, v0, vcc
+; GISEL-NEXT:    v_add_i32_e32 v1, vcc, v8, v9
+; GISEL-NEXT:    v_addc_u32_e32 v0, vcc, 0, v0, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v8, v15, v1
+; GISEL-NEXT:    v_mul_lo_u32 v9, v17, v0
+; GISEL-NEXT:    v_mul_hi_u32 v10, v17, v1
+; GISEL-NEXT:    v_mul_lo_u32 v11, v15, v0
+; GISEL-NEXT:    v_mul_hi_u32 v1, v15, v1
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; GISEL-NEXT:    v_mul_hi_u32 v10, v17, v0
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v12, v8
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v11, v8
-; GISEL-NEXT:    v_mul_lo_u32 v11, v5, v6
-; GISEL-NEXT:    v_mul_lo_u32 v12, v4, v8
-; GISEL-NEXT:    v_mul_hi_u32 v14, v4, v6
-; GISEL-NEXT:    v_mul_lo_u32 v13, v4, v6
-; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
-; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v14
-; GISEL-NEXT:    v_sub_i32_e32 v9, vcc, v9, v13
-; GISEL-NEXT:    v_subb_u32_e64 v12, s[4:5], v17, v11, vcc
-; GISEL-NEXT:    v_sub_i32_e64 v11, s[4:5], v17, v11
-; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v12, v5
-; GISEL-NEXT:    v_subb_u32_e32 v11, vcc, v11, v5, vcc
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; GISEL-NEXT:    v_add_i32_e32 v1, vcc, v11, v1
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v1, vcc, v1, v10
+; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
+; GISEL-NEXT:    v_mul_hi_u32 v0, v15, v0
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v1, v8
+; GISEL-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v1, vcc, v9, v1
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v0, v1
+; GISEL-NEXT:    v_mul_lo_u32 v10, v5, v8
+; GISEL-NEXT:    v_mul_lo_u32 v11, v4, v9
+; GISEL-NEXT:    v_mul_hi_u32 v12, v4, v8
+; GISEL-NEXT:    v_mul_lo_u32 v13, v4, v8
+; GISEL-NEXT:    v_lshl_b64 v[0:1], s[6:7], v6
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v10, v11
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v12
+; GISEL-NEXT:    v_sub_i32_e32 v10, vcc, v17, v13
+; GISEL-NEXT:    v_subb_u32_e64 v11, s[4:5], v15, v6, vcc
+; GISEL-NEXT:    v_sub_i32_e64 v6, s[4:5], v15, v6
+; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v11, v5
+; GISEL-NEXT:    v_subb_u32_e32 v6, vcc, v6, v5, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v10, v4
+; GISEL-NEXT:    v_sub_i32_e32 v10, vcc, v10, v4
 ; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v9, v4
-; GISEL-NEXT:    v_sub_i32_e32 v9, vcc, v9, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v12, v5
-; GISEL-NEXT:    v_subbrev_u32_e32 v11, vcc, 0, v11, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, v13, v14, s[4:5]
-; GISEL-NEXT:    v_add_i32_e32 v13, vcc, 1, v6
-; GISEL-NEXT:    v_addc_u32_e32 v14, vcc, 0, v8, vcc
-; GISEL-NEXT:    v_cmp_ge_u32_e32 vcc, v11, v5
-; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, -1, vcc
-; GISEL-NEXT:    v_cmp_ge_u32_e32 vcc, v9, v4
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v11, v5
+; GISEL-NEXT:    v_subbrev_u32_e32 v6, vcc, 0, v6, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v11, v12, v13, s[4:5]
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, 1, v8
+; GISEL-NEXT:    v_addc_u32_e32 v13, vcc, 0, v9, vcc
+; GISEL-NEXT:    v_cmp_ge_u32_e32 vcc, v6, v5
+; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, -1, vcc
+; GISEL-NEXT:    v_cmp_ge_u32_e32 vcc, v10, v4
 ; GISEL-NEXT:    v_cndmask_b32_e64 v4, 0, -1, vcc
-; GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v11, v5
-; GISEL-NEXT:    v_cndmask_b32_e32 v4, v15, v4, vcc
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, 1, v13
-; GISEL-NEXT:    v_addc_u32_e32 v9, vcc, 0, v14, vcc
+; GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v6, v5
+; GISEL-NEXT:    v_cndmask_b32_e32 v4, v14, v4, vcc
+; GISEL-NEXT:    v_add_i32_e32 v5, vcc, 1, v12
+; GISEL-NEXT:    v_addc_u32_e32 v6, vcc, 0, v13, vcc
+; GISEL-NEXT:    v_ashrrev_i32_e32 v10, 31, v1
+; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v10
+; GISEL-NEXT:    v_addc_u32_e32 v1, vcc, v1, v10, vcc
+; GISEL-NEXT:    v_xor_b32_e32 v14, v0, v10
+; GISEL-NEXT:    v_xor_b32_e32 v15, v1, v10
+; GISEL-NEXT:    v_cvt_f32_u32_e32 v0, v14
+; GISEL-NEXT:    v_cvt_f32_u32_e32 v1, v15
 ; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
-; GISEL-NEXT:    v_cndmask_b32_e32 v4, v13, v5, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v5, v14, v9, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v12
-; GISEL-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc
-; GISEL-NEXT:    v_xor_b32_e32 v6, v10, v7
-; GISEL-NEXT:    v_ashrrev_i32_e32 v7, 31, v1
-; GISEL-NEXT:    v_cndmask_b32_e32 v5, v8, v5, vcc
-; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v7
-; GISEL-NEXT:    v_addc_u32_e32 v1, vcc, v1, v7, vcc
-; GISEL-NEXT:    v_xor_b32_e32 v8, v0, v7
-; GISEL-NEXT:    v_xor_b32_e32 v9, v1, v7
-; GISEL-NEXT:    v_cvt_f32_u32_e32 v0, v8
-; GISEL-NEXT:    v_cvt_f32_u32_e32 v1, v9
-; GISEL-NEXT:    v_ashrrev_i32_e32 v10, 31, v3
-; GISEL-NEXT:    v_xor_b32_e32 v4, v4, v6
-; GISEL-NEXT:    v_xor_b32_e32 v5, v5, v6
+; GISEL-NEXT:    v_cndmask_b32_e32 v4, v12, v5, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v5, v13, v6, vcc
 ; GISEL-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
 ; GISEL-NEXT:    v_rcp_iflag_f32_e32 v0, v0
-; GISEL-NEXT:    v_add_i32_e32 v1, vcc, v2, v10
-; GISEL-NEXT:    v_addc_u32_e32 v2, vcc, v3, v10, vcc
-; GISEL-NEXT:    v_xor_b32_e32 v3, v1, v10
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11
+; GISEL-NEXT:    v_cndmask_b32_e32 v1, v8, v4, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v4, v9, v5, vcc
 ; GISEL-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GISEL-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
-; GISEL-NEXT:    v_trunc_f32_e32 v1, v1
-; GISEL-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
+; GISEL-NEXT:    v_mul_f32_e32 v6, 0x2f800000, v0
+; GISEL-NEXT:    v_trunc_f32_e32 v6, v6
+; GISEL-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v6
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; GISEL-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GISEL-NEXT:    v_sub_i32_e32 v11, vcc, 0, v8
-; GISEL-NEXT:    v_subb_u32_e32 v12, vcc, 0, v9, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v13, v12, v0
-; GISEL-NEXT:    v_mul_lo_u32 v14, v11, v1
-; GISEL-NEXT:    v_mul_hi_u32 v16, v11, v0
-; GISEL-NEXT:    v_mul_lo_u32 v15, v11, v0
-; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v10
-; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v14
-; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v16
-; GISEL-NEXT:    v_mul_lo_u32 v14, v1, v15
-; GISEL-NEXT:    v_mul_lo_u32 v16, v0, v13
-; GISEL-NEXT:    v_mul_hi_u32 v17, v0, v15
-; GISEL-NEXT:    v_mul_hi_u32 v15, v1, v15
-; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v16
-; GISEL-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v17
-; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v17, v1, v13
-; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v16, v14
-; GISEL-NEXT:    v_mul_hi_u32 v16, v0, v13
-; GISEL-NEXT:    v_mul_hi_u32 v13, v1, v13
-; GISEL-NEXT:    v_add_i32_e32 v15, vcc, v17, v15
+; GISEL-NEXT:    v_cvt_u32_f32_e32 v6, v6
+; GISEL-NEXT:    v_xor_b32_e32 v5, v16, v7
+; GISEL-NEXT:    v_sub_i32_e32 v7, vcc, 0, v14
+; GISEL-NEXT:    v_subb_u32_e32 v8, vcc, 0, v15, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v9, v8, v0
+; GISEL-NEXT:    v_mul_lo_u32 v11, v7, v6
+; GISEL-NEXT:    v_mul_hi_u32 v12, v7, v0
+; GISEL-NEXT:    v_mul_lo_u32 v13, v7, v0
+; GISEL-NEXT:    v_ashrrev_i32_e32 v16, 31, v3
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
+; GISEL-NEXT:    v_mul_lo_u32 v11, v6, v13
+; GISEL-NEXT:    v_mul_lo_u32 v12, v0, v9
+; GISEL-NEXT:    v_mul_hi_u32 v17, v0, v13
+; GISEL-NEXT:    v_add_i32_e32 v2, vcc, v2, v16
+; GISEL-NEXT:    v_addc_u32_e32 v3, vcc, v3, v16, vcc
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
+; GISEL-NEXT:    v_mul_lo_u32 v18, v6, v9
+; GISEL-NEXT:    v_mul_hi_u32 v13, v6, v13
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v17
+; GISEL-NEXT:    v_mul_hi_u32 v17, v0, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v18, v13
+; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v17
 ; GISEL-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v15, vcc, v15, v16
-; GISEL-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v16, vcc, v17, v16
-; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
-; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v15, vcc, v16, v15
-; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v15
-; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v14
-; GISEL-NEXT:    v_addc_u32_e64 v14, s[4:5], v1, v13, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v12, v12, v0
-; GISEL-NEXT:    v_mul_lo_u32 v15, v11, v14
-; GISEL-NEXT:    v_mul_lo_u32 v16, v11, v0
-; GISEL-NEXT:    v_mul_hi_u32 v11, v11, v0
-; GISEL-NEXT:    v_add_i32_e64 v1, s[4:5], v1, v13
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v15
-; GISEL-NEXT:    v_mul_hi_u32 v13, v0, v16
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v12, v11
-; GISEL-NEXT:    v_mul_lo_u32 v12, v14, v16
-; GISEL-NEXT:    v_mul_lo_u32 v15, v0, v11
-; GISEL-NEXT:    v_mul_hi_u32 v16, v14, v16
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v15
-; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v17
+; GISEL-NEXT:    v_mul_hi_u32 v9, v6, v9
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
+; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v11
+; GISEL-NEXT:    v_addc_u32_e64 v11, s[4:5], v6, v9, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v8, v8, v0
+; GISEL-NEXT:    v_mul_lo_u32 v12, v7, v11
+; GISEL-NEXT:    v_mul_hi_u32 v13, v7, v0
+; GISEL-NEXT:    v_mul_lo_u32 v7, v7, v0
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v6, v9
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v12
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v13
+; GISEL-NEXT:    v_mul_lo_u32 v12, v11, v7
+; GISEL-NEXT:    v_mul_lo_u32 v13, v0, v8
+; GISEL-NEXT:    v_mul_hi_u32 v9, v0, v7
+; GISEL-NEXT:    v_mul_lo_u32 v17, v11, v8
+; GISEL-NEXT:    v_mul_hi_u32 v7, v11, v7
 ; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v13
+; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v12, v9
+; GISEL-NEXT:    v_mul_hi_u32 v12, v0, v8
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v13, v9
+; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v17, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v12
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_mul_lo_u32 v13, v14, v11
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v15, v12
-; GISEL-NEXT:    v_mul_hi_u32 v15, v0, v11
-; GISEL-NEXT:    v_mul_hi_u32 v11, v14, v11
-; GISEL-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v16
-; GISEL-NEXT:    v_cndmask_b32_e64 v16, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v15
-; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v15, s[4:5], v16, v15
 ; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v13, v12
-; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v13, s[4:5], v15, v13
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v13
-; GISEL-NEXT:    v_addc_u32_e32 v1, vcc, v1, v11, vcc
-; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v0, v12
-; GISEL-NEXT:    v_addc_u32_e32 v12, vcc, 0, v1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v13, v2, v11
-; GISEL-NEXT:    v_mul_lo_u32 v14, v3, v12
-; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v4, v6
-; GISEL-NEXT:    v_mul_hi_u32 v4, v3, v11
-; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v5, v6, vcc
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v13, v14
-; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v5, v2, v12
-; GISEL-NEXT:    v_mul_hi_u32 v11, v2, v11
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
-; GISEL-NEXT:    v_mul_hi_u32 v6, v3, v12
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v11
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
-; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v11, v6
-; GISEL-NEXT:    v_mul_hi_u32 v11, v2, v12
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v11, v5
-; GISEL-NEXT:    v_mul_lo_u32 v6, v9, v4
-; GISEL-NEXT:    v_mul_lo_u32 v11, v8, v5
-; GISEL-NEXT:    v_mul_hi_u32 v13, v8, v4
-; GISEL-NEXT:    v_mul_lo_u32 v12, v8, v4
-; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v11
-; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v13
-; GISEL-NEXT:    v_sub_i32_e32 v3, vcc, v3, v12
-; GISEL-NEXT:    v_subb_u32_e64 v11, s[4:5], v2, v6, vcc
-; GISEL-NEXT:    v_sub_i32_e64 v2, s[4:5], v2, v6
-; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v11, v9
-; GISEL-NEXT:    v_subb_u32_e32 v2, vcc, v2, v9, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v3, v8
-; GISEL-NEXT:    v_sub_i32_e32 v3, vcc, v3, v8
-; GISEL-NEXT:    v_subbrev_u32_e32 v2, vcc, 0, v2, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v11, v9
-; GISEL-NEXT:    v_add_i32_e32 v11, vcc, 1, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v6, v6, v12, s[4:5]
-; GISEL-NEXT:    v_addc_u32_e32 v12, vcc, 0, v5, vcc
-; GISEL-NEXT:    v_cmp_ge_u32_e32 vcc, v2, v9
-; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, -1, vcc
-; GISEL-NEXT:    v_cmp_ge_u32_e32 vcc, v3, v8
-; GISEL-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
-; GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v2, v9
-; GISEL-NEXT:    v_cndmask_b32_e32 v2, v13, v3, vcc
-; GISEL-NEXT:    v_add_i32_e32 v3, vcc, 1, v11
-; GISEL-NEXT:    v_addc_u32_e32 v8, vcc, 0, v12, vcc
+; GISEL-NEXT:    v_mul_hi_u32 v8, v11, v8
+; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v12, v9
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
+; GISEL-NEXT:    v_addc_u32_e32 v6, vcc, v6, v8, vcc
+; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v7
+; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v16
+; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v16
+; GISEL-NEXT:    v_addc_u32_e32 v6, vcc, 0, v6, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v7, v3, v0
+; GISEL-NEXT:    v_mul_lo_u32 v8, v2, v6
+; GISEL-NEXT:    v_mul_hi_u32 v9, v2, v0
+; GISEL-NEXT:    v_mul_lo_u32 v11, v3, v6
+; GISEL-NEXT:    v_mul_hi_u32 v0, v3, v0
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; GISEL-NEXT:    v_mul_hi_u32 v9, v2, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v11, v0
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
+; GISEL-NEXT:    v_mul_hi_u32 v6, v3, v6
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v0, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v8, v0
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v0
+; GISEL-NEXT:    v_mul_lo_u32 v9, v15, v7
+; GISEL-NEXT:    v_mul_lo_u32 v11, v14, v6
+; GISEL-NEXT:    v_mul_hi_u32 v12, v14, v7
+; GISEL-NEXT:    v_xor_b32_e32 v1, v1, v5
+; GISEL-NEXT:    v_mul_lo_u32 v8, v14, v7
+; GISEL-NEXT:    v_xor_b32_e32 v4, v4, v5
+; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v1, v5
+; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v4, v5, vcc
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v9, v11
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v12
+; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v8
+; GISEL-NEXT:    v_subb_u32_e64 v5, s[4:5], v3, v4, vcc
+; GISEL-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v4
+; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v5, v15
+; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v15, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v2, v14
+; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v14
+; GISEL-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v5, v15
+; GISEL-NEXT:    v_add_i32_e32 v5, vcc, 1, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v4, v4, v8, s[4:5]
+; GISEL-NEXT:    v_addc_u32_e32 v8, vcc, 0, v6, vcc
+; GISEL-NEXT:    v_cmp_ge_u32_e32 vcc, v3, v15
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
+; GISEL-NEXT:    v_cmp_ge_u32_e32 vcc, v2, v14
+; GISEL-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
+; GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v15
+; GISEL-NEXT:    v_cndmask_b32_e32 v2, v9, v2, vcc
+; GISEL-NEXT:    v_add_i32_e32 v3, vcc, 1, v5
+; GISEL-NEXT:    v_addc_u32_e32 v9, vcc, 0, v8, vcc
 ; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
-; GISEL-NEXT:    v_cndmask_b32_e32 v2, v11, v3, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v3, v12, v8, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
-; GISEL-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
-; GISEL-NEXT:    v_xor_b32_e32 v4, v10, v7
-; GISEL-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v2, v5, v3, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v3, v8, v9, vcc
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
+; GISEL-NEXT:    v_cndmask_b32_e32 v2, v7, v2, vcc
+; GISEL-NEXT:    v_xor_b32_e32 v4, v16, v10
+; GISEL-NEXT:    v_cndmask_b32_e32 v3, v6, v3, vcc
 ; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v4
 ; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v4
 ; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v4
@@ -3009,137 +3009,137 @@
 ; CGP-NEXT:    v_xor_b32_e32 v4, v4, v0
 ; CGP-NEXT:    v_cvt_f32_u32_e32 v6, v1
 ; CGP-NEXT:    v_cvt_f32_u32_e32 v11, v4
-; CGP-NEXT:    v_ashrrev_i32_e32 v12, 31, v7
+; CGP-NEXT:    v_sub_i32_e32 v12, vcc, 0, v1
+; CGP-NEXT:    v_subb_u32_e32 v13, vcc, 0, v4, vcc
+; CGP-NEXT:    v_ashrrev_i32_e32 v18, 31, v7
 ; CGP-NEXT:    v_mac_f32_e32 v6, 0x4f800000, v11
 ; CGP-NEXT:    v_rcp_iflag_f32_e32 v6, v6
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v5, v12
-; CGP-NEXT:    v_addc_u32_e32 v7, vcc, v7, v12, vcc
-; CGP-NEXT:    v_sub_i32_e32 v14, vcc, 0, v1
 ; CGP-NEXT:    v_mul_f32_e32 v6, 0x5f7ffffc, v6
-; CGP-NEXT:    v_mul_f32_e32 v13, 0x2f800000, v6
-; CGP-NEXT:    v_trunc_f32_e32 v13, v13
-; CGP-NEXT:    v_mac_f32_e32 v6, 0xcf800000, v13
+; CGP-NEXT:    v_mul_f32_e32 v11, 0x2f800000, v6
+; CGP-NEXT:    v_trunc_f32_e32 v11, v11
+; CGP-NEXT:    v_mac_f32_e32 v6, 0xcf800000, v11
 ; CGP-NEXT:    v_cvt_u32_f32_e32 v6, v6
-; CGP-NEXT:    v_cvt_u32_f32_e32 v13, v13
-; CGP-NEXT:    v_subb_u32_e32 v15, vcc, 0, v4, vcc
-; CGP-NEXT:    v_xor_b32_e32 v11, v11, v12
-; CGP-NEXT:    v_mul_lo_u32 v16, v15, v6
-; CGP-NEXT:    v_mul_lo_u32 v17, v14, v13
-; CGP-NEXT:    v_mul_hi_u32 v19, v14, v6
-; CGP-NEXT:    v_mul_lo_u32 v18, v14, v6
-; CGP-NEXT:    v_xor_b32_e32 v7, v7, v12
-; CGP-NEXT:    v_add_i32_e32 v16, vcc, v16, v17
-; CGP-NEXT:    v_add_i32_e32 v16, vcc, v16, v19
-; CGP-NEXT:    v_mul_lo_u32 v17, v13, v18
-; CGP-NEXT:    v_mul_lo_u32 v19, v6, v16
-; CGP-NEXT:    v_mul_hi_u32 v20, v6, v18
-; CGP-NEXT:    v_mul_hi_u32 v18, v13, v18
-; CGP-NEXT:    v_add_i32_e32 v17, vcc, v17, v19
-; CGP-NEXT:    v_cndmask_b32_e64 v19, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v17, vcc, v17, v20
+; CGP-NEXT:    v_cvt_u32_f32_e32 v11, v11
+; CGP-NEXT:    v_mul_lo_u32 v15, v13, v6
+; CGP-NEXT:    v_mul_lo_u32 v14, v12, v11
+; CGP-NEXT:    v_mul_hi_u32 v17, v12, v6
+; CGP-NEXT:    v_mul_lo_u32 v16, v12, v6
+; CGP-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
+; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v17
+; CGP-NEXT:    v_mul_lo_u32 v15, v11, v16
+; CGP-NEXT:    v_mul_lo_u32 v17, v6, v14
+; CGP-NEXT:    v_mul_hi_u32 v20, v6, v16
+; CGP-NEXT:    v_add_i32_e32 v19, vcc, v5, v18
+; CGP-NEXT:    v_addc_u32_e32 v7, vcc, v7, v18, vcc
+; CGP-NEXT:    v_add_i32_e32 v15, vcc, v15, v17
+; CGP-NEXT:    v_mul_lo_u32 v21, v11, v14
+; CGP-NEXT:    v_mul_hi_u32 v16, v11, v16
+; CGP-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v15, vcc, v15, v20
+; CGP-NEXT:    v_mul_hi_u32 v20, v6, v14
+; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v15, vcc, v17, v15
+; CGP-NEXT:    v_add_i32_e32 v16, vcc, v21, v16
 ; CGP-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v20, v13, v16
-; CGP-NEXT:    v_add_i32_e32 v17, vcc, v19, v17
-; CGP-NEXT:    v_mul_hi_u32 v19, v6, v16
-; CGP-NEXT:    v_mul_hi_u32 v16, v13, v16
-; CGP-NEXT:    v_add_i32_e32 v18, vcc, v20, v18
+; CGP-NEXT:    v_add_i32_e32 v16, vcc, v16, v20
 ; CGP-NEXT:    v_cndmask_b32_e64 v20, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v18, vcc, v18, v19
-; CGP-NEXT:    v_cndmask_b32_e64 v19, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v19, vcc, v20, v19
-; CGP-NEXT:    v_add_i32_e32 v17, vcc, v18, v17
-; CGP-NEXT:    v_cndmask_b32_e64 v18, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v18, vcc, v19, v18
-; CGP-NEXT:    v_add_i32_e32 v16, vcc, v16, v18
-; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v17
-; CGP-NEXT:    v_addc_u32_e64 v17, s[4:5], v13, v16, vcc
-; CGP-NEXT:    v_mul_lo_u32 v15, v15, v6
-; CGP-NEXT:    v_mul_lo_u32 v18, v14, v17
-; CGP-NEXT:    v_mul_lo_u32 v19, v14, v6
-; CGP-NEXT:    v_mul_hi_u32 v14, v14, v6
+; CGP-NEXT:    v_add_i32_e32 v17, vcc, v17, v20
+; CGP-NEXT:    v_mul_hi_u32 v14, v11, v14
+; CGP-NEXT:    v_add_i32_e32 v15, vcc, v16, v15
+; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v16, vcc, v17, v16
+; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v16
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v15
+; CGP-NEXT:    v_addc_u32_e64 v15, s[4:5], v11, v14, vcc
+; CGP-NEXT:    v_mul_lo_u32 v13, v13, v6
+; CGP-NEXT:    v_mul_lo_u32 v16, v12, v15
+; CGP-NEXT:    v_mul_hi_u32 v17, v12, v6
+; CGP-NEXT:    v_mul_lo_u32 v12, v12, v6
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v14
 ; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v16
-; CGP-NEXT:    v_add_i32_e64 v15, s[4:5], v15, v18
-; CGP-NEXT:    v_mul_hi_u32 v16, v6, v19
-; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v15, v14
-; CGP-NEXT:    v_mul_lo_u32 v15, v17, v19
-; CGP-NEXT:    v_mul_lo_u32 v18, v6, v14
-; CGP-NEXT:    v_mul_hi_u32 v19, v17, v19
-; CGP-NEXT:    v_add_i32_e64 v15, s[4:5], v15, v18
-; CGP-NEXT:    v_cndmask_b32_e64 v18, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v15, s[4:5], v15, v16
-; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
-; CGP-NEXT:    v_mul_lo_u32 v16, v17, v14
-; CGP-NEXT:    v_add_i32_e64 v15, s[4:5], v18, v15
-; CGP-NEXT:    v_mul_hi_u32 v18, v6, v14
-; CGP-NEXT:    v_mul_hi_u32 v14, v17, v14
-; CGP-NEXT:    v_add_i32_e64 v16, s[4:5], v16, v19
-; CGP-NEXT:    v_cndmask_b32_e64 v19, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v16, s[4:5], v16, v18
-; CGP-NEXT:    v_cndmask_b32_e64 v18, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v18, s[4:5], v19, v18
-; CGP-NEXT:    v_add_i32_e64 v15, s[4:5], v16, v15
+; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v17
+; CGP-NEXT:    v_mul_lo_u32 v16, v15, v12
+; CGP-NEXT:    v_mul_lo_u32 v17, v6, v13
+; CGP-NEXT:    v_mul_hi_u32 v14, v6, v12
+; CGP-NEXT:    v_mul_lo_u32 v20, v15, v13
+; CGP-NEXT:    v_mul_hi_u32 v12, v15, v12
+; CGP-NEXT:    v_add_i32_e64 v16, s[4:5], v16, v17
+; CGP-NEXT:    v_cndmask_b32_e64 v17, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v16, v14
+; CGP-NEXT:    v_mul_hi_u32 v16, v6, v13
+; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v17, v14
+; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v20, v12
+; CGP-NEXT:    v_cndmask_b32_e64 v17, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v16
 ; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v16, s[4:5], v18, v16
-; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v14, v16
-; CGP-NEXT:    v_addc_u32_e32 v13, vcc, v13, v14, vcc
-; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v15
-; CGP-NEXT:    v_addc_u32_e32 v13, vcc, 0, v13, vcc
-; CGP-NEXT:    v_mul_lo_u32 v14, v7, v6
-; CGP-NEXT:    v_mul_lo_u32 v15, v11, v13
-; CGP-NEXT:    v_mul_hi_u32 v16, v11, v6
+; CGP-NEXT:    v_add_i32_e64 v16, s[4:5], v17, v16
+; CGP-NEXT:    v_mul_hi_u32 v13, v15, v13
+; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v14
+; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v16, v14
+; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v14
+; CGP-NEXT:    v_addc_u32_e32 v11, vcc, v11, v13, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v12
+; CGP-NEXT:    v_xor_b32_e32 v19, v19, v18
+; CGP-NEXT:    v_xor_b32_e32 v7, v7, v18
+; CGP-NEXT:    v_addc_u32_e32 v11, vcc, 0, v11, vcc
+; CGP-NEXT:    v_mul_lo_u32 v12, v7, v6
+; CGP-NEXT:    v_mul_lo_u32 v13, v19, v11
+; CGP-NEXT:    v_mul_hi_u32 v14, v19, v6
+; CGP-NEXT:    v_mul_lo_u32 v15, v7, v11
 ; CGP-NEXT:    v_mul_hi_u32 v6, v7, v6
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v15
-; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v16
-; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v16, v7, v13
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
-; CGP-NEXT:    v_mul_hi_u32 v15, v11, v13
-; CGP-NEXT:    v_mul_hi_u32 v13, v7, v13
-; CGP-NEXT:    v_add_i32_e32 v6, vcc, v16, v6
-; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v15
-; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v15, vcc, v16, v15
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
+; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v14
+; CGP-NEXT:    v_mul_hi_u32 v14, v19, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v15, v6
+; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
 ; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v14
 ; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
 ; CGP-NEXT:    v_add_i32_e32 v13, vcc, v13, v14
-; CGP-NEXT:    v_mul_lo_u32 v14, v4, v6
-; CGP-NEXT:    v_mul_lo_u32 v15, v1, v13
-; CGP-NEXT:    v_mul_hi_u32 v17, v1, v6
-; CGP-NEXT:    v_mul_lo_u32 v16, v1, v6
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v15
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v17
-; CGP-NEXT:    v_sub_i32_e32 v11, vcc, v11, v16
-; CGP-NEXT:    v_subb_u32_e64 v15, s[4:5], v7, v14, vcc
-; CGP-NEXT:    v_sub_i32_e64 v7, s[4:5], v7, v14
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v15, v4
+; CGP-NEXT:    v_mul_hi_u32 v11, v7, v11
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v12
+; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
+; CGP-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
+; CGP-NEXT:    v_mul_lo_u32 v12, v4, v6
+; CGP-NEXT:    v_mul_lo_u32 v13, v1, v11
+; CGP-NEXT:    v_mul_hi_u32 v14, v1, v6
+; CGP-NEXT:    v_mul_lo_u32 v15, v1, v6
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v14
+; CGP-NEXT:    v_sub_i32_e32 v13, vcc, v19, v15
+; CGP-NEXT:    v_subb_u32_e64 v14, s[4:5], v7, v12, vcc
+; CGP-NEXT:    v_sub_i32_e64 v7, s[4:5], v7, v12
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v14, v4
 ; CGP-NEXT:    v_subb_u32_e32 v7, vcc, v7, v4, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v11, v1
-; CGP-NEXT:    v_sub_i32_e32 v11, vcc, v11, v1
+; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v13, v1
+; CGP-NEXT:    v_sub_i32_e32 v13, vcc, v13, v1
 ; CGP-NEXT:    v_subbrev_u32_e32 v7, vcc, 0, v7, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], v15, v4
-; CGP-NEXT:    v_add_i32_e32 v15, vcc, 1, v6
-; CGP-NEXT:    v_cndmask_b32_e64 v14, v14, v16, s[4:5]
-; CGP-NEXT:    v_addc_u32_e32 v16, vcc, 0, v13, vcc
+; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], v14, v4
+; CGP-NEXT:    v_add_i32_e32 v14, vcc, 1, v6
+; CGP-NEXT:    v_cndmask_b32_e64 v12, v12, v15, s[4:5]
+; CGP-NEXT:    v_addc_u32_e32 v15, vcc, 0, v11, vcc
 ; CGP-NEXT:    v_cmp_ge_u32_e32 vcc, v7, v4
-; CGP-NEXT:    v_cndmask_b32_e64 v17, 0, -1, vcc
-; CGP-NEXT:    v_cmp_ge_u32_e32 vcc, v11, v1
+; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, -1, vcc
+; CGP-NEXT:    v_cmp_ge_u32_e32 vcc, v13, v1
 ; CGP-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc
 ; CGP-NEXT:    v_cmp_eq_u32_e32 vcc, v7, v4
-; CGP-NEXT:    v_cndmask_b32_e32 v1, v17, v1, vcc
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, 1, v15
-; CGP-NEXT:    v_addc_u32_e32 v7, vcc, 0, v16, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v1, v16, v1, vcc
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, 1, v14
+; CGP-NEXT:    v_addc_u32_e32 v7, vcc, 0, v15, vcc
 ; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1
-; CGP-NEXT:    v_cndmask_b32_e32 v1, v15, v4, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v4, v16, v7, vcc
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v14
+; CGP-NEXT:    v_cndmask_b32_e32 v1, v14, v4, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v4, v15, v7, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v12
 ; CGP-NEXT:    v_cndmask_b32_e32 v1, v6, v1, vcc
-; CGP-NEXT:    v_xor_b32_e32 v6, v12, v0
-; CGP-NEXT:    v_cndmask_b32_e32 v4, v13, v4, vcc
+; CGP-NEXT:    v_xor_b32_e32 v6, v18, v0
+; CGP-NEXT:    v_cndmask_b32_e32 v4, v11, v4, vcc
 ; CGP-NEXT:    v_xor_b32_e32 v0, v1, v6
 ; CGP-NEXT:    v_xor_b32_e32 v1, v4, v6
 ; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v0, v6
@@ -3186,137 +3186,137 @@
 ; CGP-NEXT:    v_xor_b32_e32 v6, v6, v4
 ; CGP-NEXT:    v_cvt_f32_u32_e32 v7, v5
 ; CGP-NEXT:    v_cvt_f32_u32_e32 v9, v6
-; CGP-NEXT:    v_ashrrev_i32_e32 v10, 31, v3
+; CGP-NEXT:    v_sub_i32_e32 v10, vcc, 0, v5
+; CGP-NEXT:    v_subb_u32_e32 v11, vcc, 0, v6, vcc
+; CGP-NEXT:    v_ashrrev_i32_e32 v16, 31, v3
 ; CGP-NEXT:    v_mac_f32_e32 v7, 0x4f800000, v9
 ; CGP-NEXT:    v_rcp_iflag_f32_e32 v7, v7
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v2, v10
-; CGP-NEXT:    v_addc_u32_e32 v3, vcc, v3, v10, vcc
-; CGP-NEXT:    v_sub_i32_e32 v12, vcc, 0, v5
 ; CGP-NEXT:    v_mul_f32_e32 v7, 0x5f7ffffc, v7
-; CGP-NEXT:    v_mul_f32_e32 v11, 0x2f800000, v7
-; CGP-NEXT:    v_trunc_f32_e32 v11, v11
-; CGP-NEXT:    v_mac_f32_e32 v7, 0xcf800000, v11
+; CGP-NEXT:    v_mul_f32_e32 v9, 0x2f800000, v7
+; CGP-NEXT:    v_trunc_f32_e32 v9, v9
+; CGP-NEXT:    v_mac_f32_e32 v7, 0xcf800000, v9
 ; CGP-NEXT:    v_cvt_u32_f32_e32 v7, v7
-; CGP-NEXT:    v_cvt_u32_f32_e32 v11, v11
-; CGP-NEXT:    v_subb_u32_e32 v13, vcc, 0, v6, vcc
-; CGP-NEXT:    v_xor_b32_e32 v9, v9, v10
-; CGP-NEXT:    v_mul_lo_u32 v14, v13, v7
-; CGP-NEXT:    v_mul_lo_u32 v15, v12, v11
-; CGP-NEXT:    v_mul_hi_u32 v17, v12, v7
-; CGP-NEXT:    v_mul_lo_u32 v16, v12, v7
-; CGP-NEXT:    v_xor_b32_e32 v3, v3, v10
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v15
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v17
-; CGP-NEXT:    v_mul_lo_u32 v15, v11, v16
-; CGP-NEXT:    v_mul_lo_u32 v17, v7, v14
-; CGP-NEXT:    v_mul_hi_u32 v18, v7, v16
-; CGP-NEXT:    v_mul_hi_u32 v16, v11, v16
-; CGP-NEXT:    v_add_i32_e32 v15, vcc, v15, v17
-; CGP-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v15, vcc, v15, v18
+; CGP-NEXT:    v_cvt_u32_f32_e32 v9, v9
+; CGP-NEXT:    v_mul_lo_u32 v13, v11, v7
+; CGP-NEXT:    v_mul_lo_u32 v12, v10, v9
+; CGP-NEXT:    v_mul_hi_u32 v15, v10, v7
+; CGP-NEXT:    v_mul_lo_u32 v14, v10, v7
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v15
+; CGP-NEXT:    v_mul_lo_u32 v13, v9, v14
+; CGP-NEXT:    v_mul_lo_u32 v15, v7, v12
+; CGP-NEXT:    v_mul_hi_u32 v18, v7, v14
+; CGP-NEXT:    v_add_i32_e32 v17, vcc, v2, v16
+; CGP-NEXT:    v_addc_u32_e32 v3, vcc, v3, v16, vcc
+; CGP-NEXT:    v_add_i32_e32 v13, vcc, v13, v15
+; CGP-NEXT:    v_mul_lo_u32 v19, v9, v12
+; CGP-NEXT:    v_mul_hi_u32 v14, v9, v14
 ; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v18, v11, v14
-; CGP-NEXT:    v_add_i32_e32 v15, vcc, v17, v15
-; CGP-NEXT:    v_mul_hi_u32 v17, v7, v14
-; CGP-NEXT:    v_mul_hi_u32 v14, v11, v14
-; CGP-NEXT:    v_add_i32_e32 v16, vcc, v18, v16
+; CGP-NEXT:    v_add_i32_e32 v13, vcc, v13, v18
+; CGP-NEXT:    v_mul_hi_u32 v18, v7, v12
+; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v13, vcc, v15, v13
+; CGP-NEXT:    v_add_i32_e32 v14, vcc, v19, v14
+; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v18
 ; CGP-NEXT:    v_cndmask_b32_e64 v18, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v16, vcc, v16, v17
-; CGP-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v17, vcc, v18, v17
-; CGP-NEXT:    v_add_i32_e32 v15, vcc, v16, v15
-; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v16, vcc, v17, v16
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v16
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v15
-; CGP-NEXT:    v_addc_u32_e64 v15, s[4:5], v11, v14, vcc
-; CGP-NEXT:    v_mul_lo_u32 v13, v13, v7
-; CGP-NEXT:    v_mul_lo_u32 v16, v12, v15
-; CGP-NEXT:    v_mul_lo_u32 v17, v12, v7
-; CGP-NEXT:    v_mul_hi_u32 v12, v12, v7
+; CGP-NEXT:    v_add_i32_e32 v15, vcc, v15, v18
+; CGP-NEXT:    v_mul_hi_u32 v12, v9, v12
+; CGP-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
+; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v14
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v13
+; CGP-NEXT:    v_addc_u32_e64 v13, s[4:5], v9, v12, vcc
+; CGP-NEXT:    v_mul_lo_u32 v11, v11, v7
+; CGP-NEXT:    v_mul_lo_u32 v14, v10, v13
+; CGP-NEXT:    v_mul_hi_u32 v15, v10, v7
+; CGP-NEXT:    v_mul_lo_u32 v10, v10, v7
+; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v12
 ; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v14
-; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v16
-; CGP-NEXT:    v_mul_hi_u32 v14, v7, v17
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v13, v12
-; CGP-NEXT:    v_mul_lo_u32 v13, v15, v17
-; CGP-NEXT:    v_mul_lo_u32 v16, v7, v12
-; CGP-NEXT:    v_mul_hi_u32 v17, v15, v17
-; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v16
-; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v14
-; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; CGP-NEXT:    v_mul_lo_u32 v14, v15, v12
-; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v16, v13
-; CGP-NEXT:    v_mul_hi_u32 v16, v7, v12
-; CGP-NEXT:    v_mul_hi_u32 v12, v15, v12
-; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v14, v17
-; CGP-NEXT:    v_cndmask_b32_e64 v17, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v14, v16
-; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v16, s[4:5], v17, v16
-; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v14, v13
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v15
+; CGP-NEXT:    v_mul_lo_u32 v14, v13, v10
+; CGP-NEXT:    v_mul_lo_u32 v15, v7, v11
+; CGP-NEXT:    v_mul_hi_u32 v12, v7, v10
+; CGP-NEXT:    v_mul_lo_u32 v18, v13, v11
+; CGP-NEXT:    v_mul_hi_u32 v10, v13, v10
+; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v14, v15
+; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v14, v12
+; CGP-NEXT:    v_mul_hi_u32 v14, v7, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v15, v12
+; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v18, v10
+; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v14
 ; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v16, v14
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v14
-; CGP-NEXT:    v_addc_u32_e32 v11, vcc, v11, v12, vcc
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v13
-; CGP-NEXT:    v_addc_u32_e32 v11, vcc, 0, v11, vcc
-; CGP-NEXT:    v_mul_lo_u32 v12, v3, v7
-; CGP-NEXT:    v_mul_lo_u32 v13, v9, v11
-; CGP-NEXT:    v_mul_hi_u32 v14, v9, v7
+; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v15, v14
+; CGP-NEXT:    v_mul_hi_u32 v11, v13, v11
+; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v12
+; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v14, v12
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
+; CGP-NEXT:    v_addc_u32_e32 v9, vcc, v9, v11, vcc
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
+; CGP-NEXT:    v_xor_b32_e32 v17, v17, v16
+; CGP-NEXT:    v_xor_b32_e32 v3, v3, v16
+; CGP-NEXT:    v_addc_u32_e32 v9, vcc, 0, v9, vcc
+; CGP-NEXT:    v_mul_lo_u32 v10, v3, v7
+; CGP-NEXT:    v_mul_lo_u32 v11, v17, v9
+; CGP-NEXT:    v_mul_hi_u32 v12, v17, v7
+; CGP-NEXT:    v_mul_lo_u32 v13, v3, v9
 ; CGP-NEXT:    v_mul_hi_u32 v7, v3, v7
-; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
-; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v14
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v14, v3, v11
-; CGP-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
-; CGP-NEXT:    v_mul_hi_u32 v13, v9, v11
-; CGP-NEXT:    v_mul_hi_u32 v11, v3, v11
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v14, v7
-; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v13
-; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
+; CGP-NEXT:    v_mul_hi_u32 v12, v17, v9
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v13, v7
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
 ; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v12
 ; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
 ; CGP-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
-; CGP-NEXT:    v_mul_lo_u32 v12, v6, v7
-; CGP-NEXT:    v_mul_lo_u32 v13, v5, v11
-; CGP-NEXT:    v_mul_hi_u32 v15, v5, v7
-; CGP-NEXT:    v_mul_lo_u32 v14, v5, v7
-; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
-; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v15
-; CGP-NEXT:    v_sub_i32_e32 v9, vcc, v9, v14
-; CGP-NEXT:    v_subb_u32_e64 v13, s[4:5], v3, v12, vcc
-; CGP-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v12
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v13, v6
+; CGP-NEXT:    v_mul_hi_u32 v9, v3, v9
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
+; CGP-NEXT:    v_mul_lo_u32 v10, v6, v7
+; CGP-NEXT:    v_mul_lo_u32 v11, v5, v9
+; CGP-NEXT:    v_mul_hi_u32 v12, v5, v7
+; CGP-NEXT:    v_mul_lo_u32 v13, v5, v7
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
+; CGP-NEXT:    v_sub_i32_e32 v11, vcc, v17, v13
+; CGP-NEXT:    v_subb_u32_e64 v12, s[4:5], v3, v10, vcc
+; CGP-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v10
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v12, v6
 ; CGP-NEXT:    v_subb_u32_e32 v3, vcc, v3, v6, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v9, v5
-; CGP-NEXT:    v_sub_i32_e32 v9, vcc, v9, v5
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v11, v5
+; CGP-NEXT:    v_sub_i32_e32 v11, vcc, v11, v5
 ; CGP-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], v13, v6
-; CGP-NEXT:    v_add_i32_e32 v13, vcc, 1, v7
-; CGP-NEXT:    v_cndmask_b32_e64 v12, v12, v14, s[4:5]
-; CGP-NEXT:    v_addc_u32_e32 v14, vcc, 0, v11, vcc
+; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], v12, v6
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, 1, v7
+; CGP-NEXT:    v_cndmask_b32_e64 v10, v10, v13, s[4:5]
+; CGP-NEXT:    v_addc_u32_e32 v13, vcc, 0, v9, vcc
 ; CGP-NEXT:    v_cmp_ge_u32_e32 vcc, v3, v6
-; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, -1, vcc
-; CGP-NEXT:    v_cmp_ge_u32_e32 vcc, v9, v5
+; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, -1, vcc
+; CGP-NEXT:    v_cmp_ge_u32_e32 vcc, v11, v5
 ; CGP-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
 ; CGP-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v6
-; CGP-NEXT:    v_cndmask_b32_e32 v3, v15, v5, vcc
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, 1, v13
-; CGP-NEXT:    v_addc_u32_e32 v6, vcc, 0, v14, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v3, v14, v5, vcc
+; CGP-NEXT:    v_add_i32_e32 v5, vcc, 1, v12
+; CGP-NEXT:    v_addc_u32_e32 v6, vcc, 0, v13, vcc
 ; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v3
-; CGP-NEXT:    v_cndmask_b32_e32 v3, v13, v5, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v5, v14, v6, vcc
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v12
+; CGP-NEXT:    v_cndmask_b32_e32 v3, v12, v5, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v5, v13, v6, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
 ; CGP-NEXT:    v_cndmask_b32_e32 v3, v7, v3, vcc
-; CGP-NEXT:    v_xor_b32_e32 v6, v10, v4
-; CGP-NEXT:    v_cndmask_b32_e32 v5, v11, v5, vcc
+; CGP-NEXT:    v_xor_b32_e32 v6, v16, v4
+; CGP-NEXT:    v_cndmask_b32_e32 v5, v9, v5, vcc
 ; CGP-NEXT:    v_xor_b32_e32 v3, v3, v6
 ; CGP-NEXT:    v_xor_b32_e32 v5, v5, v6
 ; CGP-NEXT:    v_sub_i32_e32 v4, vcc, v3, v6
@@ -3396,11 +3396,11 @@
 ; CGP-NEXT:    v_rcp_f32_e32 v2, v1
 ; CGP-NEXT:    v_mul_f32_e32 v2, v0, v2
 ; CGP-NEXT:    v_trunc_f32_e32 v2, v2
+; CGP-NEXT:    v_cvt_i32_f32_e32 v3, v2
 ; CGP-NEXT:    v_mad_f32 v0, -v2, v1, v0
-; CGP-NEXT:    v_cvt_i32_f32_e32 v2, v2
 ; CGP-NEXT:    v_cmp_ge_f32_e64 s[4:5], |v0|, |v1|
 ; CGP-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
+; CGP-NEXT:    v_add_i32_e32 v0, vcc, v3, v0
 ; CGP-NEXT:    v_bfe_i32 v0, v0, 0, 25
 ; CGP-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
 ; CGP-NEXT:    s_setpc_b64 s[30:31]
@@ -3435,29 +3435,27 @@
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v5, v5
 ; GISEL-NEXT:    v_mul_lo_u32 v9, v8, v4
 ; GISEL-NEXT:    v_mul_lo_u32 v10, v7, v5
-; GISEL-NEXT:    v_mul_hi_u32 v12, v7, v4
-; GISEL-NEXT:    v_mul_lo_u32 v11, v7, v4
+; GISEL-NEXT:    v_mul_hi_u32 v11, v7, v4
+; GISEL-NEXT:    v_mul_lo_u32 v12, v7, v4
 ; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
-; GISEL-NEXT:    v_mul_lo_u32 v10, v5, v11
-; GISEL-NEXT:    v_mul_lo_u32 v12, v4, v9
-; GISEL-NEXT:    v_mul_hi_u32 v14, v4, v11
-; GISEL-NEXT:    v_add_i32_e32 v0, vcc, 0, v0
-; GISEL-NEXT:    v_addc_u32_e64 v13, s[4:5], 0, 0, vcc
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v14
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; GISEL-NEXT:    v_mul_lo_u32 v10, v5, v12
+; GISEL-NEXT:    v_mul_lo_u32 v11, v4, v9
+; GISEL-NEXT:    v_mul_hi_u32 v13, v4, v12
 ; GISEL-NEXT:    v_mul_lo_u32 v14, v5, v9
-; GISEL-NEXT:    v_mul_hi_u32 v11, v5, v11
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v12, v10
-; GISEL-NEXT:    v_mul_hi_u32 v12, v4, v9
-; GISEL-NEXT:    v_mul_hi_u32 v9, v5, v9
-; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v14, v11
-; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
+; GISEL-NEXT:    v_mul_hi_u32 v12, v5, v12
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
+; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v13
+; GISEL-NEXT:    v_mul_hi_u32 v13, v4, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v14, v12
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v14, v12
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v13
+; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
+; GISEL-NEXT:    v_mul_hi_u32 v9, v5, v9
 ; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
 ; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
@@ -3466,63 +3464,65 @@
 ; GISEL-NEXT:    v_addc_u32_e64 v10, s[4:5], v5, v9, vcc
 ; GISEL-NEXT:    v_mul_lo_u32 v8, v8, v4
 ; GISEL-NEXT:    v_mul_lo_u32 v11, v7, v10
-; GISEL-NEXT:    v_mul_lo_u32 v12, v7, v4
-; GISEL-NEXT:    v_mul_hi_u32 v7, v7, v4
-; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v9
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v11
-; GISEL-NEXT:    v_mul_hi_u32 v9, v4, v12
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v8, v7
-; GISEL-NEXT:    v_mul_lo_u32 v8, v10, v12
-; GISEL-NEXT:    v_mul_lo_u32 v11, v4, v7
-; GISEL-NEXT:    v_mul_hi_u32 v12, v10, v12
+; GISEL-NEXT:    v_mul_hi_u32 v12, v7, v4
+; GISEL-NEXT:    v_mul_lo_u32 v7, v7, v4
 ; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v11
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
-; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
-; GISEL-NEXT:    v_mul_lo_u32 v9, v10, v7
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v11, v8
-; GISEL-NEXT:    v_mul_hi_u32 v11, v4, v7
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v12
+; GISEL-NEXT:    v_add_i32_e64 v0, s[4:5], 0, v0
+; GISEL-NEXT:    v_mul_lo_u32 v11, v10, v7
+; GISEL-NEXT:    v_mul_lo_u32 v12, v4, v8
+; GISEL-NEXT:    v_addc_u32_e64 v13, s[4:5], 0, 0, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v9
+; GISEL-NEXT:    v_mul_hi_u32 v9, v4, v7
+; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
+; GISEL-NEXT:    v_mul_lo_u32 v14, v10, v8
 ; GISEL-NEXT:    v_mul_hi_u32 v7, v10, v7
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v12
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v11
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v9
+; GISEL-NEXT:    v_mul_hi_u32 v11, v4, v8
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v12, v9
+; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v14, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v11
 ; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
 ; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v12, v11
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v9, v8
+; GISEL-NEXT:    v_mul_hi_u32 v8, v10, v8
+; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v9
 ; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
 ; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v9
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v9
-; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v7, vcc
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
+; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v8, vcc
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
 ; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
 ; GISEL-NEXT:    v_mul_lo_u32 v7, v13, v4
 ; GISEL-NEXT:    v_mul_lo_u32 v8, v0, v5
 ; GISEL-NEXT:    v_mul_hi_u32 v9, v0, v4
+; GISEL-NEXT:    v_mul_lo_u32 v10, v13, v5
 ; GISEL-NEXT:    v_mul_hi_u32 v4, v13, v4
 ; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; GISEL-NEXT:    v_mul_hi_u32 v9, v0, v5
 ; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v9, v13, v5
 ; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; GISEL-NEXT:    v_mul_hi_u32 v8, v0, v5
-; GISEL-NEXT:    v_mul_hi_u32 v5, v13, v5
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v9, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v10, v4
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
+; GISEL-NEXT:    v_mul_hi_u32 v5, v13, v5
 ; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
 ; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
 ; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
 ; GISEL-NEXT:    v_mul_lo_u32 v7, v3, v4
 ; GISEL-NEXT:    v_mul_lo_u32 v8, v1, v5
-; GISEL-NEXT:    v_mul_hi_u32 v10, v1, v4
-; GISEL-NEXT:    v_mul_lo_u32 v9, v1, v4
+; GISEL-NEXT:    v_mul_hi_u32 v9, v1, v4
+; GISEL-NEXT:    v_mul_lo_u32 v10, v1, v4
 ; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
-; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v9
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v10
 ; GISEL-NEXT:    v_subb_u32_e64 v8, s[4:5], v13, v7, vcc
 ; GISEL-NEXT:    v_sub_i32_e64 v7, s[4:5], v13, v7
 ; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v8, v3
@@ -3530,159 +3530,159 @@
 ; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
 ; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v0, v1
 ; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
+; GISEL-NEXT:    v_subbrev_u32_e32 v7, vcc, 0, v7, vcc
 ; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
 ; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v8, v3
-; GISEL-NEXT:    v_subbrev_u32_e32 v7, vcc, 0, v7, vcc
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, 0, v6
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, v9, v10, s[4:5]
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, 1, v4
-; GISEL-NEXT:    v_addc_u32_e32 v10, vcc, 0, v5, vcc
+; GISEL-NEXT:    v_addc_u32_e64 v9, s[4:5], 0, 0, vcc
+; GISEL-NEXT:    v_cvt_f32_u32_e32 v10, v6
+; GISEL-NEXT:    v_cvt_f32_u32_e32 v11, v9
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, 1, v4
+; GISEL-NEXT:    v_addc_u32_e32 v13, vcc, 0, v5, vcc
 ; GISEL-NEXT:    v_cmp_ge_u32_e32 vcc, v7, v3
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, -1, vcc
+; GISEL-NEXT:    v_mac_f32_e32 v10, 0x4f800000, v11
+; GISEL-NEXT:    v_rcp_iflag_f32_e32 v10, v10
+; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, -1, vcc
 ; GISEL-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v1
 ; GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
+; GISEL-NEXT:    v_mul_f32_e32 v1, 0x5f7ffffc, v10
 ; GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v7, v3
-; GISEL-NEXT:    v_cndmask_b32_e32 v0, v11, v0, vcc
-; GISEL-NEXT:    v_add_i32_e32 v1, vcc, 1, v9
-; GISEL-NEXT:    v_addc_u32_e32 v3, vcc, 0, v10, vcc
-; GISEL-NEXT:    v_add_i32_e32 v6, vcc, 0, v6
-; GISEL-NEXT:    v_addc_u32_e64 v7, s[4:5], 0, 0, vcc
-; GISEL-NEXT:    v_cvt_f32_u32_e32 v11, v6
-; GISEL-NEXT:    v_cvt_f32_u32_e32 v12, v7
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
-; GISEL-NEXT:    v_cndmask_b32_e32 v0, v9, v1, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v1, v10, v3, vcc
-; GISEL-NEXT:    v_mac_f32_e32 v11, 0x4f800000, v12
-; GISEL-NEXT:    v_rcp_iflag_f32_e32 v3, v11
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v8
-; GISEL-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc
-; GISEL-NEXT:    v_mul_f32_e32 v3, 0x5f7ffffc, v3
-; GISEL-NEXT:    v_mul_f32_e32 v4, 0x2f800000, v3
-; GISEL-NEXT:    v_trunc_f32_e32 v4, v4
-; GISEL-NEXT:    v_mac_f32_e32 v3, 0xcf800000, v4
+; GISEL-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v1
+; GISEL-NEXT:    v_trunc_f32_e32 v3, v3
+; GISEL-NEXT:    v_mac_f32_e32 v1, 0xcf800000, v3
+; GISEL-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v3, v3
-; GISEL-NEXT:    v_cvt_u32_f32_e32 v4, v4
-; GISEL-NEXT:    v_sub_i32_e32 v5, vcc, 0, v6
-; GISEL-NEXT:    v_subb_u32_e32 v8, vcc, 0, v7, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v9, v8, v3
-; GISEL-NEXT:    v_mul_lo_u32 v10, v5, v4
-; GISEL-NEXT:    v_mul_hi_u32 v12, v5, v3
-; GISEL-NEXT:    v_mul_lo_u32 v11, v5, v3
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
-; GISEL-NEXT:    v_mul_lo_u32 v10, v4, v11
-; GISEL-NEXT:    v_mul_lo_u32 v12, v3, v9
-; GISEL-NEXT:    v_mul_hi_u32 v14, v3, v11
+; GISEL-NEXT:    v_cndmask_b32_e32 v0, v14, v0, vcc
+; GISEL-NEXT:    v_sub_i32_e32 v7, vcc, 0, v6
+; GISEL-NEXT:    v_subb_u32_e32 v10, vcc, 0, v9, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v14, v10, v1
+; GISEL-NEXT:    v_mul_lo_u32 v15, v7, v3
+; GISEL-NEXT:    v_mul_hi_u32 v16, v7, v1
+; GISEL-NEXT:    v_mul_lo_u32 v11, v7, v1
+; GISEL-NEXT:    v_add_i32_e32 v17, vcc, 1, v12
+; GISEL-NEXT:    v_addc_u32_e32 v18, vcc, 0, v13, vcc
+; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v15
+; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v16
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
+; GISEL-NEXT:    v_mul_lo_u32 v15, v3, v11
+; GISEL-NEXT:    v_mul_lo_u32 v16, v1, v14
+; GISEL-NEXT:    v_cndmask_b32_e32 v0, v12, v17, vcc
+; GISEL-NEXT:    v_mul_hi_u32 v12, v1, v11
+; GISEL-NEXT:    v_mul_lo_u32 v17, v3, v14
+; GISEL-NEXT:    v_add_i32_e64 v15, s[4:5], v15, v16
+; GISEL-NEXT:    v_mul_hi_u32 v11, v3, v11
+; GISEL-NEXT:    v_cndmask_b32_e64 v16, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v15, v12
+; GISEL-NEXT:    v_mul_hi_u32 v15, v1, v14
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v16, v12
+; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v17, v11
+; GISEL-NEXT:    v_cndmask_b32_e64 v16, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v15
+; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v15, s[4:5], v16, v15
+; GISEL-NEXT:    v_mul_hi_u32 v14, v3, v14
+; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v15, v12
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v14, v12
+; GISEL-NEXT:    v_add_i32_e64 v1, s[4:5], v1, v11
+; GISEL-NEXT:    v_addc_u32_e64 v11, s[6:7], v3, v12, s[4:5]
+; GISEL-NEXT:    v_mul_lo_u32 v10, v10, v1
+; GISEL-NEXT:    v_mul_lo_u32 v14, v7, v11
+; GISEL-NEXT:    v_mul_hi_u32 v15, v7, v1
+; GISEL-NEXT:    v_mul_lo_u32 v7, v7, v1
+; GISEL-NEXT:    v_cndmask_b32_e32 v13, v13, v18, vcc
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v14
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v15
 ; GISEL-NEXT:    v_add_i32_e32 v2, vcc, 0, v2
-; GISEL-NEXT:    v_addc_u32_e64 v13, s[4:5], 0, 0, vcc
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
+; GISEL-NEXT:    v_mul_lo_u32 v14, v11, v7
+; GISEL-NEXT:    v_mul_lo_u32 v15, v1, v10
+; GISEL-NEXT:    v_addc_u32_e64 v16, s[6:7], 0, 0, vcc
+; GISEL-NEXT:    v_add_i32_e32 v3, vcc, v3, v12
+; GISEL-NEXT:    v_mul_hi_u32 v12, v1, v7
+; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v15
+; GISEL-NEXT:    v_mul_lo_u32 v17, v11, v10
+; GISEL-NEXT:    v_mul_hi_u32 v7, v11, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v14, v12
+; GISEL-NEXT:    v_mul_hi_u32 v14, v1, v10
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v14
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v14, v4, v9
-; GISEL-NEXT:    v_mul_hi_u32 v11, v4, v11
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v12, v10
-; GISEL-NEXT:    v_mul_hi_u32 v12, v3, v9
-; GISEL-NEXT:    v_mul_hi_u32 v9, v4, v9
-; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v14, v11
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v15, v12
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v17, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v14
 ; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v14, v12
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
+; GISEL-NEXT:    v_mul_hi_u32 v10, v11, v10
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v12
 ; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
-; GISEL-NEXT:    v_add_i32_e32 v3, vcc, v3, v10
-; GISEL-NEXT:    v_addc_u32_e64 v10, s[4:5], v4, v9, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v8, v8, v3
-; GISEL-NEXT:    v_mul_lo_u32 v11, v5, v10
-; GISEL-NEXT:    v_mul_lo_u32 v12, v5, v3
-; GISEL-NEXT:    v_mul_hi_u32 v5, v5, v3
-; GISEL-NEXT:    v_add_i32_e64 v4, s[4:5], v4, v9
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v11
-; GISEL-NEXT:    v_mul_hi_u32 v9, v3, v12
-; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v8, v5
-; GISEL-NEXT:    v_mul_lo_u32 v8, v10, v12
-; GISEL-NEXT:    v_mul_lo_u32 v11, v3, v5
-; GISEL-NEXT:    v_mul_hi_u32 v12, v10, v12
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v11
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
-; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
-; GISEL-NEXT:    v_mul_lo_u32 v9, v10, v5
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v11, v8
-; GISEL-NEXT:    v_mul_hi_u32 v11, v3, v5
-; GISEL-NEXT:    v_mul_hi_u32 v5, v10, v5
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v12
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v11
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v12, v11
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v9, v8
-; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v9
-; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v9
-; GISEL-NEXT:    v_addc_u32_e32 v4, vcc, v4, v5, vcc
-; GISEL-NEXT:    v_add_i32_e32 v3, vcc, v3, v8
-; GISEL-NEXT:    v_addc_u32_e32 v4, vcc, 0, v4, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v5, v13, v3
-; GISEL-NEXT:    v_mul_lo_u32 v8, v2, v4
-; GISEL-NEXT:    v_mul_hi_u32 v9, v2, v3
-; GISEL-NEXT:    v_subrev_i32_e32 v0, vcc, 0, v0
-; GISEL-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v14, v11
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
+; GISEL-NEXT:    v_addc_u32_e64 v3, vcc, v3, v10, s[4:5]
+; GISEL-NEXT:    v_add_i32_e32 v1, vcc, v1, v7
+; GISEL-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v8
+; GISEL-NEXT:    v_mul_lo_u32 v7, v16, v1
+; GISEL-NEXT:    v_mul_lo_u32 v10, v2, v3
+; GISEL-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v4, v5, v13, vcc
+; GISEL-NEXT:    v_mul_hi_u32 v5, v2, v1
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
+; GISEL-NEXT:    v_mul_lo_u32 v10, v16, v3
+; GISEL-NEXT:    v_mul_hi_u32 v1, v16, v1
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v9
+; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
+; GISEL-NEXT:    v_mul_hi_u32 v7, v2, v3
 ; GISEL-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v9, v13, v4
-; GISEL-NEXT:    v_mul_hi_u32 v3, v13, v3
 ; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; GISEL-NEXT:    v_mul_hi_u32 v8, v2, v4
-; GISEL-NEXT:    v_mul_hi_u32 v4, v13, v4
-; GISEL-NEXT:    v_add_i32_e32 v3, vcc, v9, v3
-; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v3, vcc, v3, v8
+; GISEL-NEXT:    v_add_i32_e32 v1, vcc, v10, v1
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
-; GISEL-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
-; GISEL-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
-; GISEL-NEXT:    v_mul_lo_u32 v5, v7, v3
-; GISEL-NEXT:    v_mul_lo_u32 v8, v6, v4
-; GISEL-NEXT:    v_mul_hi_u32 v10, v6, v3
-; GISEL-NEXT:    v_mul_lo_u32 v9, v6, v3
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v10
-; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v9
-; GISEL-NEXT:    v_subb_u32_e64 v8, s[4:5], v13, v5, vcc
-; GISEL-NEXT:    v_sub_i32_e64 v5, s[4:5], v13, v5
-; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v8, v7
-; GISEL-NEXT:    v_subb_u32_e32 v5, vcc, v5, v7, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e32 v1, vcc, v1, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_mul_hi_u32 v3, v16, v3
+; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v1, v5
+; GISEL-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v1, vcc, v7, v1
+; GISEL-NEXT:    v_add_i32_e32 v3, vcc, v3, v1
+; GISEL-NEXT:    v_mul_lo_u32 v8, v9, v5
+; GISEL-NEXT:    v_mul_lo_u32 v10, v6, v3
+; GISEL-NEXT:    v_mul_hi_u32 v11, v6, v5
+; GISEL-NEXT:    v_mul_lo_u32 v7, v6, v5
+; GISEL-NEXT:    v_subrev_i32_e32 v0, vcc, 0, v0
+; GISEL-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v4, vcc
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v8, v10
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v11
+; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v7
+; GISEL-NEXT:    v_subb_u32_e64 v7, s[4:5], v16, v4, vcc
+; GISEL-NEXT:    v_sub_i32_e64 v4, s[4:5], v16, v4
+; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v9
+; GISEL-NEXT:    v_subb_u32_e32 v4, vcc, v4, v9, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
 ; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v2, v6
 ; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v6
 ; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v8, v7
-; GISEL-NEXT:    v_subbrev_u32_e32 v5, vcc, 0, v5, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v8, v9, v10, s[4:5]
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, 1, v3
-; GISEL-NEXT:    v_addc_u32_e32 v10, vcc, 0, v4, vcc
-; GISEL-NEXT:    v_cmp_ge_u32_e32 vcc, v5, v7
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v7, v9
+; GISEL-NEXT:    v_subbrev_u32_e32 v4, vcc, 0, v4, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v7, v8, v10, s[4:5]
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, 1, v5
+; GISEL-NEXT:    v_addc_u32_e32 v10, vcc, 0, v3, vcc
+; GISEL-NEXT:    v_cmp_ge_u32_e32 vcc, v4, v9
 ; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, -1, vcc
 ; GISEL-NEXT:    v_cmp_ge_u32_e32 vcc, v2, v6
 ; GISEL-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
-; GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v5, v7
+; GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v4, v9
 ; GISEL-NEXT:    v_cndmask_b32_e32 v2, v11, v2, vcc
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, 1, v9
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, 1, v8
 ; GISEL-NEXT:    v_addc_u32_e32 v6, vcc, 0, v10, vcc
 ; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
-; GISEL-NEXT:    v_cndmask_b32_e32 v2, v9, v5, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v5, v10, v6, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v8
-; GISEL-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v3, v4, v5, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v2, v8, v4, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v4, v10, v6, vcc
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
+; GISEL-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
 ; GISEL-NEXT:    v_subrev_i32_e32 v2, vcc, 0, v2
 ; GISEL-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
 ; GISEL-NEXT:    s_setpc_b64 s[30:31]
@@ -3710,12 +3710,12 @@
 ; CGP-NEXT:    v_add_i32_e32 v0, vcc, v3, v0
 ; CGP-NEXT:    v_mul_f32_e32 v3, v2, v5
 ; CGP-NEXT:    v_trunc_f32_e32 v3, v3
+; CGP-NEXT:    v_cvt_i32_f32_e32 v5, v3
 ; CGP-NEXT:    v_mad_f32 v2, -v3, v4, v2
-; CGP-NEXT:    v_cvt_i32_f32_e32 v3, v3
 ; CGP-NEXT:    v_cmp_ge_f32_e64 s[4:5], |v2|, |v4|
 ; CGP-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
 ; CGP-NEXT:    v_bfe_i32 v0, v0, 0, 25
-; CGP-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; CGP-NEXT:    v_bfe_i32 v2, v2, 0, 25
 ; CGP-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
 ; CGP-NEXT:    v_ashrrev_i32_e32 v3, 31, v2
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
@@ -19,143 +19,143 @@
 ; CHECK-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
 ; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v2, v4
 ; CHECK-NEXT:    v_addc_u32_e32 v3, vcc, v3, v4, vcc
-; CHECK-NEXT:    v_xor_b32_e32 v3, v3, v4
 ; CHECK-NEXT:    v_xor_b32_e32 v5, v5, v4
+; CHECK-NEXT:    v_xor_b32_e32 v3, v3, v4
 ; CHECK-NEXT:    v_cvt_f32_u32_e32 v4, v5
 ; CHECK-NEXT:    v_cvt_f32_u32_e32 v6, v3
-; CHECK-NEXT:    v_ashrrev_i32_e32 v7, 31, v1
+; CHECK-NEXT:    v_sub_i32_e32 v7, vcc, 0, v5
+; CHECK-NEXT:    v_subb_u32_e32 v8, vcc, 0, v3, vcc
+; CHECK-NEXT:    v_ashrrev_i32_e32 v13, 31, v1
 ; CHECK-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v6
 ; CHECK-NEXT:    v_rcp_iflag_f32_e32 v4, v4
-; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v0, v7
-; CHECK-NEXT:    v_addc_u32_e32 v1, vcc, v1, v7, vcc
-; CHECK-NEXT:    v_sub_i32_e32 v9, vcc, 0, v5
 ; CHECK-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
-; CHECK-NEXT:    v_mul_f32_e32 v8, 0x2f800000, v4
-; CHECK-NEXT:    v_trunc_f32_e32 v8, v8
-; CHECK-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v8
+; CHECK-NEXT:    v_mul_f32_e32 v6, 0x2f800000, v4
+; CHECK-NEXT:    v_trunc_f32_e32 v6, v6
+; CHECK-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v6
 ; CHECK-NEXT:    v_cvt_u32_f32_e32 v4, v4
-; CHECK-NEXT:    v_cvt_u32_f32_e32 v8, v8
-; CHECK-NEXT:    v_subb_u32_e32 v10, vcc, 0, v3, vcc
-; CHECK-NEXT:    v_xor_b32_e32 v6, v6, v7
-; CHECK-NEXT:    v_mul_lo_u32 v11, v10, v4
-; CHECK-NEXT:    v_mul_lo_u32 v12, v9, v8
-; CHECK-NEXT:    v_mul_hi_u32 v14, v9, v4
-; CHECK-NEXT:    v_mul_lo_u32 v13, v9, v4
-; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v7
-; CHECK-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
-; CHECK-NEXT:    v_add_i32_e32 v11, vcc, v11, v14
-; CHECK-NEXT:    v_mul_lo_u32 v12, v8, v13
-; CHECK-NEXT:    v_mul_lo_u32 v14, v4, v11
-; CHECK-NEXT:    v_mul_hi_u32 v15, v4, v13
-; CHECK-NEXT:    v_mul_hi_u32 v13, v8, v13
-; CHECK-NEXT:    v_add_i32_e32 v12, vcc, v12, v14
-; CHECK-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v12, vcc, v12, v15
+; CHECK-NEXT:    v_cvt_u32_f32_e32 v6, v6
+; CHECK-NEXT:    v_mul_lo_u32 v10, v8, v4
+; CHECK-NEXT:    v_mul_lo_u32 v9, v7, v6
+; CHECK-NEXT:    v_mul_hi_u32 v12, v7, v4
+; CHECK-NEXT:    v_mul_lo_u32 v11, v7, v4
+; CHECK-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
+; CHECK-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
+; CHECK-NEXT:    v_mul_lo_u32 v10, v6, v11
+; CHECK-NEXT:    v_mul_lo_u32 v12, v4, v9
+; CHECK-NEXT:    v_mul_hi_u32 v15, v4, v11
+; CHECK-NEXT:    v_add_i32_e32 v14, vcc, v0, v13
+; CHECK-NEXT:    v_addc_u32_e32 v1, vcc, v1, v13, vcc
+; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
+; CHECK-NEXT:    v_mul_lo_u32 v16, v6, v9
+; CHECK-NEXT:    v_mul_hi_u32 v11, v6, v11
 ; CHECK-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v15, v8, v11
-; CHECK-NEXT:    v_add_i32_e32 v12, vcc, v14, v12
-; CHECK-NEXT:    v_mul_hi_u32 v14, v4, v11
-; CHECK-NEXT:    v_mul_hi_u32 v11, v8, v11
-; CHECK-NEXT:    v_add_i32_e32 v13, vcc, v15, v13
+; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v10, v15
+; CHECK-NEXT:    v_mul_hi_u32 v15, v4, v9
+; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v12, v10
+; CHECK-NEXT:    v_add_i32_e32 v11, vcc, v16, v11
+; CHECK-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v11, vcc, v11, v15
 ; CHECK-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v13, vcc, v13, v14
-; CHECK-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
-; CHECK-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
-; CHECK-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
-; CHECK-NEXT:    v_add_i32_e32 v11, vcc, v11, v13
-; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v12
-; CHECK-NEXT:    v_addc_u32_e64 v12, s[4:5], v8, v11, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v10, v10, v4
-; CHECK-NEXT:    v_mul_lo_u32 v13, v9, v12
-; CHECK-NEXT:    v_mul_lo_u32 v14, v9, v4
-; CHECK-NEXT:    v_mul_hi_u32 v9, v9, v4
+; CHECK-NEXT:    v_add_i32_e32 v12, vcc, v12, v15
+; CHECK-NEXT:    v_mul_hi_u32 v9, v6, v9
+; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; CHECK-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
+; CHECK-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v10
+; CHECK-NEXT:    v_addc_u32_e64 v10, s[4:5], v6, v9, vcc
+; CHECK-NEXT:    v_mul_lo_u32 v8, v8, v4
+; CHECK-NEXT:    v_mul_lo_u32 v11, v7, v10
+; CHECK-NEXT:    v_mul_hi_u32 v12, v7, v4
+; CHECK-NEXT:    v_mul_lo_u32 v7, v7, v4
+; CHECK-NEXT:    v_add_i32_e64 v6, s[4:5], v6, v9
 ; CHECK-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v11
-; CHECK-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v13
-; CHECK-NEXT:    v_mul_hi_u32 v11, v4, v14
-; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v10, v9
-; CHECK-NEXT:    v_mul_lo_u32 v10, v12, v14
-; CHECK-NEXT:    v_mul_lo_u32 v13, v4, v9
-; CHECK-NEXT:    v_mul_hi_u32 v14, v12, v14
-; CHECK-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v13
-; CHECK-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v11
-; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
-; CHECK-NEXT:    v_mul_lo_u32 v11, v12, v9
-; CHECK-NEXT:    v_add_i32_e64 v10, s[4:5], v13, v10
-; CHECK-NEXT:    v_mul_hi_u32 v13, v4, v9
-; CHECK-NEXT:    v_mul_hi_u32 v9, v12, v9
-; CHECK-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v14
-; CHECK-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v13
-; CHECK-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v13, s[4:5], v14, v13
-; CHECK-NEXT:    v_add_i32_e64 v10, s[4:5], v11, v10
+; CHECK-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v12
+; CHECK-NEXT:    v_mul_lo_u32 v11, v10, v7
+; CHECK-NEXT:    v_mul_lo_u32 v12, v4, v8
+; CHECK-NEXT:    v_mul_hi_u32 v9, v4, v7
+; CHECK-NEXT:    v_mul_lo_u32 v15, v10, v8
+; CHECK-NEXT:    v_mul_hi_u32 v7, v10, v7
+; CHECK-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
+; CHECK-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v9
+; CHECK-NEXT:    v_mul_hi_u32 v11, v4, v8
+; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v12, v9
+; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v15, v7
+; CHECK-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v11
 ; CHECK-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v11, s[4:5], v13, v11
-; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v11
-; CHECK-NEXT:    v_addc_u32_e32 v8, vcc, v8, v9, vcc
-; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v10
-; CHECK-NEXT:    v_addc_u32_e32 v8, vcc, 0, v8, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v9, v1, v4
-; CHECK-NEXT:    v_mul_lo_u32 v10, v6, v8
-; CHECK-NEXT:    v_mul_hi_u32 v11, v6, v4
+; CHECK-NEXT:    v_add_i32_e64 v11, s[4:5], v12, v11
+; CHECK-NEXT:    v_mul_hi_u32 v8, v10, v8
+; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v9
+; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v9
+; CHECK-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
+; CHECK-NEXT:    v_addc_u32_e32 v6, vcc, v6, v8, vcc
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; CHECK-NEXT:    v_xor_b32_e32 v14, v14, v13
+; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v13
+; CHECK-NEXT:    v_addc_u32_e32 v6, vcc, 0, v6, vcc
+; CHECK-NEXT:    v_mul_lo_u32 v7, v1, v4
+; CHECK-NEXT:    v_mul_lo_u32 v8, v14, v6
+; CHECK-NEXT:    v_mul_hi_u32 v9, v14, v4
+; CHECK-NEXT:    v_mul_lo_u32 v10, v1, v6
 ; CHECK-NEXT:    v_mul_hi_u32 v4, v1, v4
-; CHECK-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
-; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v11, v1, v8
-; CHECK-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
-; CHECK-NEXT:    v_mul_hi_u32 v10, v6, v8
-; CHECK-NEXT:    v_mul_hi_u32 v8, v1, v8
-; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v11, v4
-; CHECK-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v10
-; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; CHECK-NEXT:    v_mul_hi_u32 v9, v14, v6
+; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v10, v4
+; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v9
 ; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
 ; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
-; CHECK-NEXT:    v_mul_lo_u32 v9, v3, v4
-; CHECK-NEXT:    v_mul_lo_u32 v8, v5, v8
-; CHECK-NEXT:    v_mul_lo_u32 v10, v5, v4
-; CHECK-NEXT:    v_mul_hi_u32 v4, v5, v4
-; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
-; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v8, v4
-; CHECK-NEXT:    v_sub_i32_e32 v6, vcc, v6, v10
-; CHECK-NEXT:    v_subb_u32_e64 v8, s[4:5], v1, v4, vcc
-; CHECK-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v4
-; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v8, v3
-; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[4:5]
-; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v6, v5
-; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
-; CHECK-NEXT:    v_cmp_eq_u32_e64 s[4:5], v8, v3
+; CHECK-NEXT:    v_mul_hi_u32 v6, v1, v6
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; CHECK-NEXT:    v_mul_lo_u32 v7, v3, v4
+; CHECK-NEXT:    v_mul_lo_u32 v6, v5, v6
+; CHECK-NEXT:    v_mul_hi_u32 v8, v5, v4
+; CHECK-NEXT:    v_mul_lo_u32 v4, v5, v4
+; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; CHECK-NEXT:    v_sub_i32_e32 v4, vcc, v14, v4
+; CHECK-NEXT:    v_subb_u32_e64 v7, s[4:5], v1, v6, vcc
+; CHECK-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v6
+; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v3
+; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[4:5]
+; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v4, v5
+; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
+; CHECK-NEXT:    v_cmp_eq_u32_e64 s[4:5], v7, v3
 ; CHECK-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
-; CHECK-NEXT:    v_cndmask_b32_e64 v4, v4, v9, s[4:5]
-; CHECK-NEXT:    v_sub_i32_e32 v9, vcc, v6, v5
-; CHECK-NEXT:    v_subbrev_u32_e64 v10, s[4:5], 0, v1, vcc
-; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v10, v3
-; CHECK-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
-; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v9, v5
+; CHECK-NEXT:    v_cndmask_b32_e64 v6, v6, v8, s[4:5]
+; CHECK-NEXT:    v_sub_i32_e32 v8, vcc, v4, v5
+; CHECK-NEXT:    v_subbrev_u32_e64 v9, s[4:5], 0, v1, vcc
+; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v9, v3
+; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
+; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v8, v5
 ; CHECK-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
-; CHECK-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[4:5]
-; CHECK-NEXT:    v_cmp_eq_u32_e64 s[4:5], v10, v3
-; CHECK-NEXT:    v_sub_i32_e32 v3, vcc, v9, v5
-; CHECK-NEXT:    v_cndmask_b32_e64 v11, v11, v12, s[4:5]
+; CHECK-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
+; CHECK-NEXT:    v_cmp_eq_u32_e64 s[4:5], v9, v3
+; CHECK-NEXT:    v_sub_i32_e32 v3, vcc, v8, v5
+; CHECK-NEXT:    v_cndmask_b32_e64 v10, v10, v11, s[4:5]
 ; CHECK-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11
-; CHECK-NEXT:    v_cndmask_b32_e32 v3, v9, v3, vcc
-; CHECK-NEXT:    v_cndmask_b32_e32 v1, v10, v1, vcc
-; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
-; CHECK-NEXT:    v_cndmask_b32_e32 v3, v6, v3, vcc
-; CHECK-NEXT:    v_cndmask_b32_e32 v1, v8, v1, vcc
-; CHECK-NEXT:    v_xor_b32_e32 v3, v3, v7
-; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v7
-; CHECK-NEXT:    v_sub_i32_e32 v4, vcc, v3, v7
-; CHECK-NEXT:    v_subb_u32_e32 v5, vcc, v1, v7, vcc
+; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
+; CHECK-NEXT:    v_cndmask_b32_e32 v3, v8, v3, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v1, v9, v1, vcc
+; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
+; CHECK-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v1, v7, v1, vcc
+; CHECK-NEXT:    v_xor_b32_e32 v3, v3, v13
+; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v13
+; CHECK-NEXT:    v_sub_i32_e32 v4, vcc, v3, v13
+; CHECK-NEXT:    v_subb_u32_e32 v5, vcc, v1, v13, vcc
 ; CHECK-NEXT:  BB0_2: ; %Flow
 ; CHECK-NEXT:    s_or_saveexec_b64 s[4:5], s[6:7]
 ; CHECK-NEXT:    s_xor_b64 exec, exec, s[4:5]
@@ -232,30 +232,29 @@
 ; CHECK-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; CHECK-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; CHECK-NEXT:    s_subb_u32 s5, 0, s11
-; CHECK-NEXT:    v_mov_b32_e32 v6, s11
 ; CHECK-NEXT:    v_mul_lo_u32 v2, s5, v0
 ; CHECK-NEXT:    v_mul_lo_u32 v3, s3, v1
-; CHECK-NEXT:    v_mul_hi_u32 v5, s3, v0
-; CHECK-NEXT:    v_mul_lo_u32 v4, s3, v0
+; CHECK-NEXT:    v_mul_hi_u32 v4, s3, v0
+; CHECK-NEXT:    v_mul_lo_u32 v5, s3, v0
 ; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
-; CHECK-NEXT:    v_mul_lo_u32 v3, v1, v4
-; CHECK-NEXT:    v_mul_lo_u32 v5, v0, v2
-; CHECK-NEXT:    v_mul_hi_u32 v7, v0, v4
-; CHECK-NEXT:    v_mul_hi_u32 v4, v1, v4
-; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
-; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
-; CHECK-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
+; CHECK-NEXT:    v_mul_lo_u32 v3, v1, v5
+; CHECK-NEXT:    v_mul_lo_u32 v4, v0, v2
+; CHECK-NEXT:    v_mul_hi_u32 v6, v0, v5
 ; CHECK-NEXT:    v_mul_lo_u32 v7, v1, v2
-; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
-; CHECK-NEXT:    v_mul_hi_u32 v5, v0, v2
-; CHECK-NEXT:    v_mul_hi_u32 v2, v1, v2
-; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
-; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
+; CHECK-NEXT:    v_mul_hi_u32 v5, v1, v5
+; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v3, v4
+; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
+; CHECK-NEXT:    v_mul_hi_u32 v6, v0, v2
+; CHECK-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v7, v5
 ; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
+; CHECK-NEXT:    v_mul_hi_u32 v2, v1, v2
 ; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
 ; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
@@ -264,31 +263,31 @@
 ; CHECK-NEXT:    v_addc_u32_e64 v3, s[0:1], v1, v2, vcc
 ; CHECK-NEXT:    v_mul_lo_u32 v4, s5, v0
 ; CHECK-NEXT:    v_mul_lo_u32 v5, s3, v3
-; CHECK-NEXT:    v_mul_hi_u32 v8, s3, v0
+; CHECK-NEXT:    v_mul_hi_u32 v6, s3, v0
 ; CHECK-NEXT:    v_mul_lo_u32 v7, s3, v0
 ; CHECK-NEXT:    v_add_i32_e64 v1, s[0:1], v1, v2
 ; CHECK-NEXT:    v_add_i32_e64 v4, s[0:1], v4, v5
-; CHECK-NEXT:    v_add_i32_e64 v4, s[0:1], v4, v8
+; CHECK-NEXT:    v_add_i32_e64 v4, s[0:1], v4, v6
 ; CHECK-NEXT:    v_mul_lo_u32 v5, v3, v7
-; CHECK-NEXT:    v_mul_lo_u32 v8, v0, v4
+; CHECK-NEXT:    v_mul_lo_u32 v6, v0, v4
 ; CHECK-NEXT:    v_mul_hi_u32 v2, v0, v7
+; CHECK-NEXT:    v_mul_lo_u32 v8, v3, v4
 ; CHECK-NEXT:    v_mul_hi_u32 v7, v3, v7
-; CHECK-NEXT:    v_add_i32_e64 v5, s[0:1], v5, v8
-; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[0:1]
+; CHECK-NEXT:    v_add_i32_e64 v5, s[0:1], v5, v6
+; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s[0:1]
 ; CHECK-NEXT:    v_add_i32_e64 v2, s[0:1], v5, v2
+; CHECK-NEXT:    v_mul_hi_u32 v5, v0, v4
 ; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s[0:1]
-; CHECK-NEXT:    v_mul_lo_u32 v5, v3, v4
-; CHECK-NEXT:    v_add_i32_e64 v2, s[0:1], v8, v2
-; CHECK-NEXT:    v_mul_hi_u32 v8, v0, v4
-; CHECK-NEXT:    v_mul_hi_u32 v3, v3, v4
-; CHECK-NEXT:    v_add_i32_e64 v5, s[0:1], v5, v7
+; CHECK-NEXT:    v_add_i32_e64 v2, s[0:1], v6, v2
+; CHECK-NEXT:    v_add_i32_e64 v6, s[0:1], v8, v7
 ; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, 1, s[0:1]
-; CHECK-NEXT:    v_add_i32_e64 v5, s[0:1], v5, v8
-; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[0:1]
-; CHECK-NEXT:    v_add_i32_e64 v7, s[0:1], v7, v8
+; CHECK-NEXT:    v_add_i32_e64 v5, s[0:1], v6, v5
+; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s[0:1]
+; CHECK-NEXT:    v_add_i32_e64 v6, s[0:1], v7, v6
+; CHECK-NEXT:    v_mul_hi_u32 v3, v3, v4
 ; CHECK-NEXT:    v_add_i32_e64 v2, s[0:1], v5, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, s[0:1]
-; CHECK-NEXT:    v_add_i32_e64 v4, s[0:1], v7, v5
+; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, 1, s[0:1]
+; CHECK-NEXT:    v_add_i32_e64 v4, s[0:1], v6, v4
 ; CHECK-NEXT:    v_add_i32_e64 v3, s[0:1], v3, v4
 ; CHECK-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
@@ -296,54 +295,55 @@
 ; CHECK-NEXT:    v_mul_lo_u32 v2, s9, v0
 ; CHECK-NEXT:    v_mul_lo_u32 v3, s8, v1
 ; CHECK-NEXT:    v_mul_hi_u32 v5, s8, v0
+; CHECK-NEXT:    v_mul_lo_u32 v6, s9, v1
 ; CHECK-NEXT:    v_mul_hi_u32 v0, s9, v0
-; CHECK-NEXT:    v_mov_b32_e32 v4, s9
 ; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
 ; CHECK-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; CHECK-NEXT:    v_mul_hi_u32 v5, s8, v1
 ; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v5, s9, v1
 ; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; CHECK-NEXT:    v_mul_hi_u32 v3, s8, v1
-; CHECK-NEXT:    v_mul_hi_u32 v1, s9, v1
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v5, v0
-; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
+; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v6, v0
 ; CHECK-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
+; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v5
+; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
+; CHECK-NEXT:    v_mul_hi_u32 v1, s9, v1
 ; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
 ; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v1, v2
 ; CHECK-NEXT:    v_mul_lo_u32 v2, s11, v0
 ; CHECK-NEXT:    v_mul_lo_u32 v1, s10, v1
-; CHECK-NEXT:    v_mul_lo_u32 v3, s10, v0
-; CHECK-NEXT:    v_mul_hi_u32 v0, s10, v0
+; CHECK-NEXT:    v_mul_hi_u32 v3, s10, v0
+; CHECK-NEXT:    v_mul_lo_u32 v0, s10, v0
+; CHECK-NEXT:    v_mov_b32_e32 v5, s9
 ; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
-; CHECK-NEXT:    v_sub_i32_e32 v1, vcc, s8, v3
-; CHECK-NEXT:    v_subb_u32_e64 v2, s[0:1], v4, v0, vcc
-; CHECK-NEXT:    v_sub_i32_e64 v0, s[0:1], s9, v0
+; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
+; CHECK-NEXT:    v_sub_i32_e32 v0, vcc, s8, v0
+; CHECK-NEXT:    v_subb_u32_e64 v2, s[0:1], v5, v1, vcc
+; CHECK-NEXT:    v_sub_i32_e64 v1, s[0:1], s9, v1
 ; CHECK-NEXT:    v_cmp_le_u32_e64 s[0:1], s11, v2
+; CHECK-NEXT:    v_mov_b32_e32 v4, s11
 ; CHECK-NEXT:    v_cndmask_b32_e64 v3, 0, -1, s[0:1]
-; CHECK-NEXT:    v_cmp_le_u32_e64 s[0:1], s10, v1
-; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[0:1]
+; CHECK-NEXT:    v_cmp_le_u32_e64 s[0:1], s10, v0
+; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
 ; CHECK-NEXT:    v_cmp_eq_u32_e64 s[0:1], s11, v2
-; CHECK-NEXT:    v_subb_u32_e32 v0, vcc, v0, v6, vcc
-; CHECK-NEXT:    v_cndmask_b32_e64 v2, v3, v4, s[0:1]
-; CHECK-NEXT:    v_subrev_i32_e32 v3, vcc, s10, v1
-; CHECK-NEXT:    v_subbrev_u32_e32 v0, vcc, 0, v0, vcc
-; CHECK-NEXT:    v_cmp_le_u32_e32 vcc, s11, v0
+; CHECK-NEXT:    v_subb_u32_e32 v1, vcc, v1, v4, vcc
+; CHECK-NEXT:    v_cndmask_b32_e64 v2, v3, v5, s[0:1]
+; CHECK-NEXT:    v_subrev_i32_e32 v3, vcc, s10, v0
+; CHECK-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
+; CHECK-NEXT:    v_cmp_le_u32_e32 vcc, s11, v1
 ; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, -1, vcc
 ; CHECK-NEXT:    v_cmp_le_u32_e32 vcc, s10, v3
 ; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
-; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc, s11, v0
-; CHECK-NEXT:    v_cndmask_b32_e32 v0, v4, v5, vcc
+; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc, s11, v1
+; CHECK-NEXT:    v_cndmask_b32_e32 v1, v4, v5, vcc
 ; CHECK-NEXT:    v_subrev_i32_e32 v4, vcc, s10, v3
-; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
-; CHECK-NEXT:    v_cndmask_b32_e32 v0, v3, v4, vcc
+; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1
+; CHECK-NEXT:    v_cndmask_b32_e32 v1, v3, v4, vcc
 ; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
-; CHECK-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
 ; CHECK-NEXT:    v_xor_b32_e32 v0, s6, v0
 ; CHECK-NEXT:    v_subrev_i32_e32 v0, vcc, s6, v0
 ; CHECK-NEXT:    s_mov_b32 s1, 0
@@ -396,287 +396,287 @@
 ; GISEL-NEXT:    v_ashrrev_i32_e32 v8, 31, v5
 ; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
 ; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v8, vcc
-; GISEL-NEXT:    v_xor_b32_e32 v5, v5, v8
 ; GISEL-NEXT:    v_xor_b32_e32 v4, v4, v8
+; GISEL-NEXT:    v_xor_b32_e32 v5, v5, v8
 ; GISEL-NEXT:    v_cvt_f32_u32_e32 v8, v4
 ; GISEL-NEXT:    v_cvt_f32_u32_e32 v9, v5
-; GISEL-NEXT:    v_ashrrev_i32_e32 v10, 31, v1
-; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v10
-; GISEL-NEXT:    v_addc_u32_e32 v1, vcc, v1, v10, vcc
+; GISEL-NEXT:    v_sub_i32_e32 v10, vcc, 0, v4
+; GISEL-NEXT:    v_subb_u32_e32 v11, vcc, 0, v5, vcc
+; GISEL-NEXT:    v_ashrrev_i32_e32 v16, 31, v1
 ; GISEL-NEXT:    v_mac_f32_e32 v8, 0x4f800000, v9
 ; GISEL-NEXT:    v_rcp_iflag_f32_e32 v8, v8
-; GISEL-NEXT:    v_sub_i32_e32 v11, vcc, 0, v4
-; GISEL-NEXT:    v_subb_u32_e32 v12, vcc, 0, v5, vcc
-; GISEL-NEXT:    v_xor_b32_e32 v0, v0, v10
 ; GISEL-NEXT:    v_mul_f32_e32 v8, 0x5f7ffffc, v8
 ; GISEL-NEXT:    v_mul_f32_e32 v9, 0x2f800000, v8
 ; GISEL-NEXT:    v_trunc_f32_e32 v9, v9
 ; GISEL-NEXT:    v_mac_f32_e32 v8, 0xcf800000, v9
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v8, v8
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v9, v9
-; GISEL-NEXT:    v_xor_b32_e32 v1, v1, v10
-; GISEL-NEXT:    v_mul_lo_u32 v13, v12, v8
-; GISEL-NEXT:    v_mul_lo_u32 v14, v11, v9
-; GISEL-NEXT:    v_mul_hi_u32 v16, v11, v8
-; GISEL-NEXT:    v_mul_lo_u32 v15, v11, v8
-; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v14
-; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v16
-; GISEL-NEXT:    v_mul_lo_u32 v14, v9, v15
-; GISEL-NEXT:    v_mul_lo_u32 v16, v8, v13
+; GISEL-NEXT:    v_mul_lo_u32 v12, v11, v8
+; GISEL-NEXT:    v_mul_lo_u32 v13, v10, v9
+; GISEL-NEXT:    v_mul_hi_u32 v14, v10, v8
+; GISEL-NEXT:    v_mul_lo_u32 v15, v10, v8
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v14
+; GISEL-NEXT:    v_mul_lo_u32 v13, v9, v15
+; GISEL-NEXT:    v_mul_lo_u32 v14, v8, v12
 ; GISEL-NEXT:    v_mul_hi_u32 v17, v8, v15
+; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v16
+; GISEL-NEXT:    v_addc_u32_e32 v1, vcc, v1, v16, vcc
+; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v14
+; GISEL-NEXT:    v_mul_lo_u32 v18, v9, v12
 ; GISEL-NEXT:    v_mul_hi_u32 v15, v9, v15
-; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v16
-; GISEL-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v17
 ; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v17, v9, v13
-; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v16, v14
-; GISEL-NEXT:    v_mul_hi_u32 v16, v8, v13
-; GISEL-NEXT:    v_mul_hi_u32 v13, v9, v13
-; GISEL-NEXT:    v_add_i32_e32 v15, vcc, v17, v15
+; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v17
+; GISEL-NEXT:    v_mul_hi_u32 v17, v8, v12
+; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
+; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v18, v15
+; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v17
 ; GISEL-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v15, vcc, v15, v16
-; GISEL-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v16, vcc, v17, v16
+; GISEL-NEXT:    v_add_i32_e32 v15, vcc, v15, v17
+; GISEL-NEXT:    v_mul_hi_u32 v12, v9, v12
+; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
+; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
-; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v15, vcc, v16, v15
-; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v15
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v14
-; GISEL-NEXT:    v_addc_u32_e64 v14, s[4:5], v9, v13, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v12, v12, v8
-; GISEL-NEXT:    v_mul_lo_u32 v15, v11, v14
-; GISEL-NEXT:    v_mul_lo_u32 v16, v11, v8
-; GISEL-NEXT:    v_mul_hi_u32 v11, v11, v8
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v13
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v15
-; GISEL-NEXT:    v_mul_hi_u32 v13, v8, v16
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v12, v11
-; GISEL-NEXT:    v_mul_lo_u32 v12, v14, v16
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v14
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v13
+; GISEL-NEXT:    v_addc_u32_e64 v13, s[4:5], v9, v12, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v11, v11, v8
+; GISEL-NEXT:    v_mul_lo_u32 v14, v10, v13
+; GISEL-NEXT:    v_mul_hi_u32 v15, v10, v8
+; GISEL-NEXT:    v_mul_lo_u32 v10, v10, v8
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v12
+; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v14
+; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v15
+; GISEL-NEXT:    v_mul_lo_u32 v14, v13, v10
 ; GISEL-NEXT:    v_mul_lo_u32 v15, v8, v11
-; GISEL-NEXT:    v_mul_hi_u32 v16, v14, v16
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v15
+; GISEL-NEXT:    v_mul_hi_u32 v12, v8, v10
+; GISEL-NEXT:    v_mul_lo_u32 v17, v13, v11
+; GISEL-NEXT:    v_mul_hi_u32 v10, v13, v10
+; GISEL-NEXT:    v_add_i32_e64 v14, s[4:5], v14, v15
 ; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v13
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v14, v12
+; GISEL-NEXT:    v_mul_hi_u32 v14, v8, v11
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_mul_lo_u32 v13, v14, v11
 ; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v15, v12
-; GISEL-NEXT:    v_mul_hi_u32 v15, v8, v11
-; GISEL-NEXT:    v_mul_hi_u32 v11, v14, v11
-; GISEL-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v16
-; GISEL-NEXT:    v_cndmask_b32_e64 v16, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v15
+; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v17, v10
 ; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v15, s[4:5], v16, v15
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v13, v12
-; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v13, s[4:5], v15, v13
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v13
+; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v14
+; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v14, s[4:5], v15, v14
+; GISEL-NEXT:    v_mul_hi_u32 v11, v13, v11
+; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v12
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v14, v12
+; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
 ; GISEL-NEXT:    v_addc_u32_e32 v9, vcc, v9, v11, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v12
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; GISEL-NEXT:    v_xor_b32_e32 v0, v0, v16
+; GISEL-NEXT:    v_xor_b32_e32 v1, v1, v16
 ; GISEL-NEXT:    v_addc_u32_e32 v9, vcc, 0, v9, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v11, v1, v8
-; GISEL-NEXT:    v_mul_lo_u32 v12, v0, v9
-; GISEL-NEXT:    v_mul_hi_u32 v13, v0, v8
+; GISEL-NEXT:    v_mul_lo_u32 v10, v1, v8
+; GISEL-NEXT:    v_mul_lo_u32 v11, v0, v9
+; GISEL-NEXT:    v_mul_hi_u32 v12, v0, v8
+; GISEL-NEXT:    v_mul_lo_u32 v13, v1, v9
 ; GISEL-NEXT:    v_mul_hi_u32 v8, v1, v8
-; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v13
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
 ; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v13, v1, v9
-; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
 ; GISEL-NEXT:    v_mul_hi_u32 v12, v0, v9
-; GISEL-NEXT:    v_mul_hi_u32 v9, v1, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
 ; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v13, v8
-; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v12
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
-; GISEL-NEXT:    v_mul_lo_u32 v11, v5, v8
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
+; GISEL-NEXT:    v_mul_hi_u32 v9, v1, v9
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
+; GISEL-NEXT:    v_mul_lo_u32 v10, v5, v8
 ; GISEL-NEXT:    v_mul_lo_u32 v9, v4, v9
-; GISEL-NEXT:    v_mul_lo_u32 v12, v4, v8
-; GISEL-NEXT:    v_mul_hi_u32 v8, v4, v8
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v11, v9
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
-; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v12
-; GISEL-NEXT:    v_subb_u32_e64 v9, s[4:5], v1, v8, vcc
-; GISEL-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v8
-; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v9, v5
-; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
+; GISEL-NEXT:    v_mul_hi_u32 v11, v4, v8
+; GISEL-NEXT:    v_mul_lo_u32 v8, v4, v8
+; GISEL-NEXT:    v_ashrrev_i32_e32 v14, 31, v3
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v8
+; GISEL-NEXT:    v_subb_u32_e64 v8, s[4:5], v1, v9, vcc
+; GISEL-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v9
+; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v8, v5
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
 ; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v0, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v9, v5
+; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v8, v5
 ; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v5, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v8, v8, v11, s[4:5]
-; GISEL-NEXT:    v_sub_i32_e32 v11, vcc, v0, v4
-; GISEL-NEXT:    v_subbrev_u32_e64 v12, s[4:5], 0, v1, vcc
-; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v12, v5
-; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v11, v4
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, v9, v10, s[4:5]
+; GISEL-NEXT:    v_sub_i32_e32 v10, vcc, v0, v4
+; GISEL-NEXT:    v_subbrev_u32_e64 v11, s[4:5], 0, v1, vcc
+; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v11, v5
 ; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v5, vcc
-; GISEL-NEXT:    v_sub_i32_e32 v4, vcc, v11, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v12, v5
-; GISEL-NEXT:    v_cndmask_b32_e64 v13, v13, v14, s[4:5]
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v10, v4
+; GISEL-NEXT:    v_sub_i32_e32 v4, vcc, v10, v4
+; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v11, v5
 ; GISEL-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v13
-; GISEL-NEXT:    v_cndmask_b32_e32 v4, v11, v4, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v1, v12, v1, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v8
+; GISEL-NEXT:    v_ashrrev_i32_e32 v5, 31, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v5
+; GISEL-NEXT:    v_addc_u32_e32 v7, vcc, v7, v5, vcc
+; GISEL-NEXT:    v_xor_b32_e32 v6, v6, v5
+; GISEL-NEXT:    v_xor_b32_e32 v5, v7, v5
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, v12, v13, s[4:5]
+; GISEL-NEXT:    v_cvt_f32_u32_e32 v7, v6
+; GISEL-NEXT:    v_cvt_f32_u32_e32 v13, v5
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v12
+; GISEL-NEXT:    v_cndmask_b32_e32 v4, v10, v4, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v1, v11, v1, vcc
+; GISEL-NEXT:    v_mac_f32_e32 v7, 0x4f800000, v13
+; GISEL-NEXT:    v_rcp_iflag_f32_e32 v7, v7
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v9
 ; GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
-; GISEL-NEXT:    v_ashrrev_i32_e32 v4, 31, v7
-; GISEL-NEXT:    v_cndmask_b32_e32 v1, v9, v1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v6, v4
-; GISEL-NEXT:    v_addc_u32_e32 v6, vcc, v7, v4, vcc
-; GISEL-NEXT:    v_xor_b32_e32 v5, v5, v4
-; GISEL-NEXT:    v_xor_b32_e32 v4, v6, v4
-; GISEL-NEXT:    v_cvt_f32_u32_e32 v6, v5
-; GISEL-NEXT:    v_cvt_f32_u32_e32 v7, v4
-; GISEL-NEXT:    v_ashrrev_i32_e32 v8, 31, v3
-; GISEL-NEXT:    v_add_i32_e32 v2, vcc, v2, v8
-; GISEL-NEXT:    v_addc_u32_e32 v3, vcc, v3, v8, vcc
-; GISEL-NEXT:    v_mac_f32_e32 v6, 0x4f800000, v7
-; GISEL-NEXT:    v_rcp_iflag_f32_e32 v6, v6
-; GISEL-NEXT:    v_sub_i32_e32 v9, vcc, 0, v5
-; GISEL-NEXT:    v_subb_u32_e32 v11, vcc, 0, v4, vcc
-; GISEL-NEXT:    v_xor_b32_e32 v0, v0, v10
-; GISEL-NEXT:    v_mul_f32_e32 v6, 0x5f7ffffc, v6
-; GISEL-NEXT:    v_mul_f32_e32 v7, 0x2f800000, v6
+; GISEL-NEXT:    v_cndmask_b32_e32 v1, v8, v1, vcc
+; GISEL-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v7
+; GISEL-NEXT:    v_mul_f32_e32 v7, 0x2f800000, v4
 ; GISEL-NEXT:    v_trunc_f32_e32 v7, v7
-; GISEL-NEXT:    v_mac_f32_e32 v6, 0xcf800000, v7
-; GISEL-NEXT:    v_cvt_u32_f32_e32 v6, v6
+; GISEL-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v7
+; GISEL-NEXT:    v_cvt_u32_f32_e32 v4, v4
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v7, v7
-; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v8
-; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v8
-; GISEL-NEXT:    v_mul_lo_u32 v12, v11, v6
-; GISEL-NEXT:    v_mul_lo_u32 v13, v9, v7
-; GISEL-NEXT:    v_mul_hi_u32 v15, v9, v6
-; GISEL-NEXT:    v_mul_lo_u32 v14, v9, v6
-; GISEL-NEXT:    v_xor_b32_e32 v1, v1, v10
-; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
-; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v15
-; GISEL-NEXT:    v_mul_lo_u32 v13, v7, v14
-; GISEL-NEXT:    v_mul_lo_u32 v15, v6, v12
-; GISEL-NEXT:    v_mul_hi_u32 v16, v6, v14
-; GISEL-NEXT:    v_mul_hi_u32 v14, v7, v14
-; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v15
-; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v16
+; GISEL-NEXT:    v_sub_i32_e32 v8, vcc, 0, v6
+; GISEL-NEXT:    v_subb_u32_e32 v9, vcc, 0, v5, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v10, v9, v4
+; GISEL-NEXT:    v_mul_lo_u32 v11, v8, v7
+; GISEL-NEXT:    v_mul_hi_u32 v12, v8, v4
+; GISEL-NEXT:    v_mul_lo_u32 v13, v8, v4
+; GISEL-NEXT:    v_xor_b32_e32 v0, v0, v16
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
+; GISEL-NEXT:    v_mul_lo_u32 v11, v7, v13
+; GISEL-NEXT:    v_mul_lo_u32 v12, v4, v10
+; GISEL-NEXT:    v_mul_hi_u32 v15, v4, v13
+; GISEL-NEXT:    v_add_i32_e32 v2, vcc, v2, v14
+; GISEL-NEXT:    v_addc_u32_e32 v3, vcc, v3, v14, vcc
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
+; GISEL-NEXT:    v_mul_lo_u32 v17, v7, v10
+; GISEL-NEXT:    v_mul_hi_u32 v13, v7, v13
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v15
+; GISEL-NEXT:    v_mul_hi_u32 v15, v4, v10
+; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v17, v13
 ; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v16, v7, v12
-; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v15, v13
-; GISEL-NEXT:    v_mul_hi_u32 v15, v6, v12
-; GISEL-NEXT:    v_mul_hi_u32 v12, v7, v12
-; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v16, v14
-; GISEL-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v15
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v15
 ; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v15, vcc, v16, v15
-; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
-; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
-; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v14
-; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v13
-; GISEL-NEXT:    v_addc_u32_e64 v13, s[4:5], v7, v12, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v11, v11, v6
-; GISEL-NEXT:    v_mul_lo_u32 v14, v9, v13
-; GISEL-NEXT:    v_mul_lo_u32 v15, v9, v6
-; GISEL-NEXT:    v_mul_hi_u32 v9, v9, v6
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v12
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v14
-; GISEL-NEXT:    v_mul_hi_u32 v12, v6, v15
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v9
-; GISEL-NEXT:    v_mul_lo_u32 v11, v13, v15
-; GISEL-NEXT:    v_mul_lo_u32 v14, v6, v9
-; GISEL-NEXT:    v_mul_hi_u32 v15, v13, v15
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v14
-; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; GISEL-NEXT:    v_mul_lo_u32 v12, v13, v9
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v14, v11
-; GISEL-NEXT:    v_mul_hi_u32 v14, v6, v9
-; GISEL-NEXT:    v_mul_hi_u32 v9, v13, v9
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v15
-; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v14
-; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v14, s[4:5], v15, v14
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v12, v11
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v14, v12
+; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v15
+; GISEL-NEXT:    v_mul_hi_u32 v10, v7, v10
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v11
+; GISEL-NEXT:    v_addc_u32_e64 v11, s[4:5], v7, v10, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v9, v9, v4
+; GISEL-NEXT:    v_mul_lo_u32 v12, v8, v11
+; GISEL-NEXT:    v_mul_hi_u32 v13, v8, v4
+; GISEL-NEXT:    v_mul_lo_u32 v8, v8, v4
+; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v10
 ; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v12
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v13
+; GISEL-NEXT:    v_mul_lo_u32 v12, v11, v8
+; GISEL-NEXT:    v_mul_lo_u32 v13, v4, v9
+; GISEL-NEXT:    v_mul_hi_u32 v10, v4, v8
+; GISEL-NEXT:    v_mul_lo_u32 v15, v11, v9
+; GISEL-NEXT:    v_mul_hi_u32 v8, v11, v8
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v13
+; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v12, v10
+; GISEL-NEXT:    v_mul_hi_u32 v12, v4, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v13, v10
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v15, v8
+; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v12
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v13, v12
+; GISEL-NEXT:    v_mul_hi_u32 v9, v11, v9
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v10
+; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v12, v10
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v10
 ; GISEL-NEXT:    v_addc_u32_e32 v7, vcc, v7, v9, vcc
-; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v11
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
+; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v14
+; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v14
 ; GISEL-NEXT:    v_addc_u32_e32 v7, vcc, 0, v7, vcc
-; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v10
-; GISEL-NEXT:    v_mul_lo_u32 v9, v3, v6
-; GISEL-NEXT:    v_mul_lo_u32 v11, v2, v7
-; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v10, vcc
-; GISEL-NEXT:    v_mul_hi_u32 v10, v2, v6
-; GISEL-NEXT:    v_mul_hi_u32 v6, v3, v6
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
+; GISEL-NEXT:    v_mul_lo_u32 v8, v3, v4
+; GISEL-NEXT:    v_mul_lo_u32 v9, v2, v7
+; GISEL-NEXT:    v_mul_hi_u32 v10, v2, v4
+; GISEL-NEXT:    v_mul_lo_u32 v11, v3, v7
+; GISEL-NEXT:    v_mul_hi_u32 v4, v3, v4
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
 ; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v10, v3, v7
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v11, v9
-; GISEL-NEXT:    v_mul_hi_u32 v11, v2, v7
-; GISEL-NEXT:    v_mul_hi_u32 v7, v3, v7
-; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v10, v6
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v11
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
-; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; GISEL-NEXT:    v_mul_hi_u32 v10, v2, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v11, v4
 ; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
-; GISEL-NEXT:    v_mul_lo_u32 v9, v4, v6
-; GISEL-NEXT:    v_mul_lo_u32 v7, v5, v7
-; GISEL-NEXT:    v_mul_lo_u32 v10, v5, v6
-; GISEL-NEXT:    v_mul_hi_u32 v6, v5, v6
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v10
+; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
+; GISEL-NEXT:    v_mul_hi_u32 v7, v3, v7
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; GISEL-NEXT:    v_mul_lo_u32 v9, v5, v4
+; GISEL-NEXT:    v_mul_lo_u32 v7, v6, v7
+; GISEL-NEXT:    v_mul_lo_u32 v8, v6, v4
+; GISEL-NEXT:    v_mul_hi_u32 v4, v6, v4
+; GISEL-NEXT:    v_xor_b32_e32 v1, v1, v16
+; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v16
+; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v16, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v9, v7
-; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v10
-; GISEL-NEXT:    v_subb_u32_e64 v7, s[4:5], v3, v6, vcc
-; GISEL-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v6
-; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v2, v5
-; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v7, v4
-; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v4, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v6, v6, v9, s[4:5]
-; GISEL-NEXT:    v_sub_i32_e32 v9, vcc, v2, v5
-; GISEL-NEXT:    v_subbrev_u32_e64 v10, s[4:5], 0, v3, vcc
-; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v10, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v9, v5
-; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v4, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v10, v4
-; GISEL-NEXT:    v_sub_i32_e32 v4, vcc, v9, v5
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, v11, v12, s[4:5]
-; GISEL-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11
-; GISEL-NEXT:    v_cndmask_b32_e32 v4, v9, v4, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v3, v10, v3, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
-; GISEL-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v3, v7, v3, vcc
-; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v8
-; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v8
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
 ; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v8
-; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v8, vcc
-; GISEL-NEXT:    s_setpc_b64 s[30:31]
-;
-; CGP-LABEL: v_srem_v2i64:
-; CGP:       ; %bb.0:
+; GISEL-NEXT:    v_subb_u32_e64 v7, s[4:5], v3, v4, vcc
+; GISEL-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v4
+; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v5
+; GISEL-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v2, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v7, v5
+; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v5, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v4, v4, v8, s[4:5]
+; GISEL-NEXT:    v_sub_i32_e32 v8, vcc, v2, v6
+; GISEL-NEXT:    v_subbrev_u32_e64 v9, s[4:5], 0, v3, vcc
+; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v9, v5
+; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v8, v6
+; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v5, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v9, v5
+; GISEL-NEXT:    v_sub_i32_e32 v5, vcc, v8, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v10, v10, v11, s[4:5]
+; GISEL-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
+; GISEL-NEXT:    v_cndmask_b32_e32 v5, v8, v5, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v3, v9, v3, vcc
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
+; GISEL-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v3, v7, v3, vcc
+; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v14
+; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v14
+; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v14
+; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v14, vcc
+; GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; CGP-LABEL: v_srem_v2i64:
+; CGP:       ; %bb.0:
 ; CGP-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CGP-NEXT:    v_mov_b32_e32 v9, v1
 ; CGP-NEXT:    v_mov_b32_e32 v8, v0
@@ -695,139 +695,139 @@
 ; CGP-NEXT:    v_xor_b32_e32 v0, v5, v0
 ; CGP-NEXT:    v_cvt_f32_u32_e32 v5, v1
 ; CGP-NEXT:    v_cvt_f32_u32_e32 v10, v0
-; CGP-NEXT:    v_ashrrev_i32_e32 v11, 31, v9
+; CGP-NEXT:    v_sub_i32_e32 v11, vcc, 0, v1
+; CGP-NEXT:    v_subb_u32_e32 v12, vcc, 0, v0, vcc
+; CGP-NEXT:    v_ashrrev_i32_e32 v17, 31, v9
 ; CGP-NEXT:    v_mac_f32_e32 v5, 0x4f800000, v10
 ; CGP-NEXT:    v_rcp_iflag_f32_e32 v5, v5
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v8, v11
-; CGP-NEXT:    v_addc_u32_e32 v9, vcc, v9, v11, vcc
-; CGP-NEXT:    v_sub_i32_e32 v13, vcc, 0, v1
 ; CGP-NEXT:    v_mul_f32_e32 v5, 0x5f7ffffc, v5
-; CGP-NEXT:    v_mul_f32_e32 v12, 0x2f800000, v5
-; CGP-NEXT:    v_trunc_f32_e32 v12, v12
-; CGP-NEXT:    v_mac_f32_e32 v5, 0xcf800000, v12
+; CGP-NEXT:    v_mul_f32_e32 v10, 0x2f800000, v5
+; CGP-NEXT:    v_trunc_f32_e32 v10, v10
+; CGP-NEXT:    v_mac_f32_e32 v5, 0xcf800000, v10
 ; CGP-NEXT:    v_cvt_u32_f32_e32 v5, v5
-; CGP-NEXT:    v_cvt_u32_f32_e32 v12, v12
-; CGP-NEXT:    v_subb_u32_e32 v14, vcc, 0, v0, vcc
-; CGP-NEXT:    v_xor_b32_e32 v10, v10, v11
-; CGP-NEXT:    v_mul_lo_u32 v15, v14, v5
-; CGP-NEXT:    v_mul_lo_u32 v16, v13, v12
-; CGP-NEXT:    v_mul_hi_u32 v18, v13, v5
-; CGP-NEXT:    v_mul_lo_u32 v17, v13, v5
-; CGP-NEXT:    v_xor_b32_e32 v9, v9, v11
-; CGP-NEXT:    v_add_i32_e32 v15, vcc, v15, v16
-; CGP-NEXT:    v_add_i32_e32 v15, vcc, v15, v18
-; CGP-NEXT:    v_mul_lo_u32 v16, v12, v17
-; CGP-NEXT:    v_mul_lo_u32 v18, v5, v15
-; CGP-NEXT:    v_mul_hi_u32 v19, v5, v17
-; CGP-NEXT:    v_mul_hi_u32 v17, v12, v17
-; CGP-NEXT:    v_add_i32_e32 v16, vcc, v16, v18
-; CGP-NEXT:    v_cndmask_b32_e64 v18, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v16, vcc, v16, v19
+; CGP-NEXT:    v_cvt_u32_f32_e32 v10, v10
+; CGP-NEXT:    v_mul_lo_u32 v14, v12, v5
+; CGP-NEXT:    v_mul_lo_u32 v13, v11, v10
+; CGP-NEXT:    v_mul_hi_u32 v16, v11, v5
+; CGP-NEXT:    v_mul_lo_u32 v15, v11, v5
+; CGP-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
+; CGP-NEXT:    v_add_i32_e32 v13, vcc, v13, v16
+; CGP-NEXT:    v_mul_lo_u32 v14, v10, v15
+; CGP-NEXT:    v_mul_lo_u32 v16, v5, v13
+; CGP-NEXT:    v_mul_hi_u32 v19, v5, v15
+; CGP-NEXT:    v_add_i32_e32 v18, vcc, v8, v17
+; CGP-NEXT:    v_addc_u32_e32 v9, vcc, v9, v17, vcc
+; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v16
+; CGP-NEXT:    v_mul_lo_u32 v20, v10, v13
+; CGP-NEXT:    v_mul_hi_u32 v15, v10, v15
+; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v19
+; CGP-NEXT:    v_mul_hi_u32 v19, v5, v13
+; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v14, vcc, v16, v14
+; CGP-NEXT:    v_add_i32_e32 v15, vcc, v20, v15
 ; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v19, v12, v15
-; CGP-NEXT:    v_add_i32_e32 v16, vcc, v18, v16
-; CGP-NEXT:    v_mul_hi_u32 v18, v5, v15
-; CGP-NEXT:    v_mul_hi_u32 v15, v12, v15
-; CGP-NEXT:    v_add_i32_e32 v17, vcc, v19, v17
+; CGP-NEXT:    v_add_i32_e32 v15, vcc, v15, v19
 ; CGP-NEXT:    v_cndmask_b32_e64 v19, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v17, vcc, v17, v18
-; CGP-NEXT:    v_cndmask_b32_e64 v18, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v18, vcc, v19, v18
-; CGP-NEXT:    v_add_i32_e32 v16, vcc, v17, v16
-; CGP-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v17, vcc, v18, v17
-; CGP-NEXT:    v_add_i32_e32 v15, vcc, v15, v17
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v16
-; CGP-NEXT:    v_addc_u32_e64 v16, s[4:5], v12, v15, vcc
-; CGP-NEXT:    v_mul_lo_u32 v14, v14, v5
-; CGP-NEXT:    v_mul_lo_u32 v17, v13, v16
-; CGP-NEXT:    v_mul_lo_u32 v18, v13, v5
-; CGP-NEXT:    v_mul_hi_u32 v13, v13, v5
+; CGP-NEXT:    v_add_i32_e32 v16, vcc, v16, v19
+; CGP-NEXT:    v_mul_hi_u32 v13, v10, v13
+; CGP-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
+; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v15, vcc, v16, v15
+; CGP-NEXT:    v_add_i32_e32 v13, vcc, v13, v15
+; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v14
+; CGP-NEXT:    v_addc_u32_e64 v14, s[4:5], v10, v13, vcc
+; CGP-NEXT:    v_mul_lo_u32 v12, v12, v5
+; CGP-NEXT:    v_mul_lo_u32 v15, v11, v14
+; CGP-NEXT:    v_mul_hi_u32 v16, v11, v5
+; CGP-NEXT:    v_mul_lo_u32 v11, v11, v5
+; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v13
 ; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v15
-; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v14, v17
-; CGP-NEXT:    v_mul_hi_u32 v15, v5, v18
-; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v14, v13
-; CGP-NEXT:    v_mul_lo_u32 v14, v16, v18
-; CGP-NEXT:    v_mul_lo_u32 v17, v5, v13
-; CGP-NEXT:    v_mul_hi_u32 v18, v16, v18
-; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v14, v17
-; CGP-NEXT:    v_cndmask_b32_e64 v17, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v14, v15
-; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; CGP-NEXT:    v_mul_lo_u32 v15, v16, v13
-; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v17, v14
-; CGP-NEXT:    v_mul_hi_u32 v17, v5, v13
-; CGP-NEXT:    v_mul_hi_u32 v13, v16, v13
-; CGP-NEXT:    v_add_i32_e64 v15, s[4:5], v15, v18
-; CGP-NEXT:    v_cndmask_b32_e64 v18, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v15, s[4:5], v15, v17
-; CGP-NEXT:    v_cndmask_b32_e64 v17, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v17, s[4:5], v18, v17
-; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v15, v14
+; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v16
+; CGP-NEXT:    v_mul_lo_u32 v15, v14, v11
+; CGP-NEXT:    v_mul_lo_u32 v16, v5, v12
+; CGP-NEXT:    v_mul_hi_u32 v13, v5, v11
+; CGP-NEXT:    v_mul_lo_u32 v19, v14, v12
+; CGP-NEXT:    v_mul_hi_u32 v11, v14, v11
+; CGP-NEXT:    v_add_i32_e64 v15, s[4:5], v15, v16
+; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v15, v13
+; CGP-NEXT:    v_mul_hi_u32 v15, v5, v12
+; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v16, v13
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v19, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v15
 ; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v15, s[4:5], v17, v15
-; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v15
-; CGP-NEXT:    v_addc_u32_e32 v12, vcc, v12, v13, vcc
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v14
-; CGP-NEXT:    v_addc_u32_e32 v12, vcc, 0, v12, vcc
-; CGP-NEXT:    v_mul_lo_u32 v13, v9, v5
-; CGP-NEXT:    v_mul_lo_u32 v14, v10, v12
-; CGP-NEXT:    v_mul_hi_u32 v15, v10, v5
+; CGP-NEXT:    v_add_i32_e64 v15, s[4:5], v16, v15
+; CGP-NEXT:    v_mul_hi_u32 v12, v14, v12
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v13
+; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v15, v13
+; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v13
+; CGP-NEXT:    v_addc_u32_e32 v10, vcc, v10, v12, vcc
+; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v11
+; CGP-NEXT:    v_xor_b32_e32 v18, v18, v17
+; CGP-NEXT:    v_xor_b32_e32 v9, v9, v17
+; CGP-NEXT:    v_addc_u32_e32 v10, vcc, 0, v10, vcc
+; CGP-NEXT:    v_mul_lo_u32 v11, v9, v5
+; CGP-NEXT:    v_mul_lo_u32 v12, v18, v10
+; CGP-NEXT:    v_mul_hi_u32 v13, v18, v5
+; CGP-NEXT:    v_mul_lo_u32 v14, v9, v10
 ; CGP-NEXT:    v_mul_hi_u32 v5, v9, v5
-; CGP-NEXT:    v_add_i32_e32 v13, vcc, v13, v14
-; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v13, vcc, v13, v15
-; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v15, v9, v12
-; CGP-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
-; CGP-NEXT:    v_mul_hi_u32 v14, v10, v12
-; CGP-NEXT:    v_mul_hi_u32 v12, v9, v12
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v15, v5
-; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v14
-; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
+; CGP-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
+; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v11, vcc, v11, v13
+; CGP-NEXT:    v_mul_hi_u32 v13, v18, v10
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
+; CGP-NEXT:    v_add_i32_e32 v5, vcc, v14, v5
+; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
 ; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v13
 ; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
 ; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
-; CGP-NEXT:    v_mul_lo_u32 v13, v0, v5
-; CGP-NEXT:    v_mul_lo_u32 v12, v1, v12
-; CGP-NEXT:    v_mul_lo_u32 v14, v1, v5
-; CGP-NEXT:    v_mul_hi_u32 v5, v1, v5
-; CGP-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v12, v5
-; CGP-NEXT:    v_sub_i32_e32 v10, vcc, v10, v14
-; CGP-NEXT:    v_subb_u32_e64 v12, s[4:5], v9, v5, vcc
-; CGP-NEXT:    v_sub_i32_e64 v5, s[4:5], v9, v5
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v12, v0
-; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v10, v1
-; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], v12, v0
-; CGP-NEXT:    v_subb_u32_e32 v5, vcc, v5, v0, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v9, v9, v13, s[4:5]
-; CGP-NEXT:    v_sub_i32_e32 v13, vcc, v10, v1
-; CGP-NEXT:    v_subbrev_u32_e64 v14, s[4:5], 0, v5, vcc
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v14, v0
+; CGP-NEXT:    v_mul_hi_u32 v10, v9, v10
+; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
+; CGP-NEXT:    v_mul_lo_u32 v11, v0, v5
+; CGP-NEXT:    v_mul_lo_u32 v10, v1, v10
+; CGP-NEXT:    v_mul_hi_u32 v12, v1, v5
+; CGP-NEXT:    v_mul_lo_u32 v5, v1, v5
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
+; CGP-NEXT:    v_sub_i32_e32 v5, vcc, v18, v5
+; CGP-NEXT:    v_subb_u32_e64 v11, s[4:5], v9, v10, vcc
+; CGP-NEXT:    v_sub_i32_e64 v9, s[4:5], v9, v10
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v11, v0
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v5, v1
+; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], v11, v0
+; CGP-NEXT:    v_subb_u32_e32 v9, vcc, v9, v0, vcc
+; CGP-NEXT:    v_cndmask_b32_e64 v10, v10, v12, s[4:5]
+; CGP-NEXT:    v_sub_i32_e32 v12, vcc, v5, v1
+; CGP-NEXT:    v_subbrev_u32_e64 v13, s[4:5], 0, v9, vcc
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v13, v0
+; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v12, v1
 ; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v13, v1
-; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], v14, v0
-; CGP-NEXT:    v_subb_u32_e32 v0, vcc, v5, v0, vcc
-; CGP-NEXT:    v_sub_i32_e32 v1, vcc, v13, v1
-; CGP-NEXT:    v_cndmask_b32_e64 v15, v15, v16, s[4:5]
+; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], v13, v0
+; CGP-NEXT:    v_subb_u32_e32 v0, vcc, v9, v0, vcc
+; CGP-NEXT:    v_sub_i32_e32 v1, vcc, v12, v1
+; CGP-NEXT:    v_cndmask_b32_e64 v14, v14, v15, s[4:5]
 ; CGP-NEXT:    v_subbrev_u32_e32 v0, vcc, 0, v0, vcc
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v15
-; CGP-NEXT:    v_cndmask_b32_e32 v1, v13, v1, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v0, v14, v0, vcc
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v9
-; CGP-NEXT:    v_cndmask_b32_e32 v1, v10, v1, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v0, v12, v0, vcc
-; CGP-NEXT:    v_xor_b32_e32 v1, v1, v11
-; CGP-NEXT:    v_xor_b32_e32 v5, v0, v11
-; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v1, v11
-; CGP-NEXT:    v_subb_u32_e32 v1, vcc, v5, v11, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v14
+; CGP-NEXT:    v_cndmask_b32_e32 v1, v12, v1, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v0, v13, v0, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
+; CGP-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v0, v11, v0, vcc
+; CGP-NEXT:    v_xor_b32_e32 v1, v1, v17
+; CGP-NEXT:    v_xor_b32_e32 v5, v0, v17
+; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v1, v17
+; CGP-NEXT:    v_subb_u32_e32 v1, vcc, v5, v17, vcc
 ; CGP-NEXT:  BB2_2: ; %Flow2
 ; CGP-NEXT:    s_or_saveexec_b64 s[4:5], s[6:7]
 ; CGP-NEXT:    s_xor_b64 exec, exec, s[4:5]
@@ -868,139 +868,139 @@
 ; CGP-NEXT:    v_xor_b32_e32 v4, v7, v4
 ; CGP-NEXT:    v_cvt_f32_u32_e32 v7, v5
 ; CGP-NEXT:    v_cvt_f32_u32_e32 v8, v4
-; CGP-NEXT:    v_ashrrev_i32_e32 v9, 31, v3
+; CGP-NEXT:    v_sub_i32_e32 v9, vcc, 0, v5
+; CGP-NEXT:    v_subb_u32_e32 v10, vcc, 0, v4, vcc
+; CGP-NEXT:    v_ashrrev_i32_e32 v15, 31, v3
 ; CGP-NEXT:    v_mac_f32_e32 v7, 0x4f800000, v8
 ; CGP-NEXT:    v_rcp_iflag_f32_e32 v7, v7
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, v2, v9
-; CGP-NEXT:    v_addc_u32_e32 v3, vcc, v3, v9, vcc
-; CGP-NEXT:    v_sub_i32_e32 v11, vcc, 0, v5
 ; CGP-NEXT:    v_mul_f32_e32 v7, 0x5f7ffffc, v7
-; CGP-NEXT:    v_mul_f32_e32 v10, 0x2f800000, v7
-; CGP-NEXT:    v_trunc_f32_e32 v10, v10
-; CGP-NEXT:    v_mac_f32_e32 v7, 0xcf800000, v10
+; CGP-NEXT:    v_mul_f32_e32 v8, 0x2f800000, v7
+; CGP-NEXT:    v_trunc_f32_e32 v8, v8
+; CGP-NEXT:    v_mac_f32_e32 v7, 0xcf800000, v8
 ; CGP-NEXT:    v_cvt_u32_f32_e32 v7, v7
-; CGP-NEXT:    v_cvt_u32_f32_e32 v10, v10
-; CGP-NEXT:    v_subb_u32_e32 v12, vcc, 0, v4, vcc
-; CGP-NEXT:    v_xor_b32_e32 v8, v8, v9
-; CGP-NEXT:    v_mul_lo_u32 v13, v12, v7
-; CGP-NEXT:    v_mul_lo_u32 v14, v11, v10
-; CGP-NEXT:    v_mul_hi_u32 v16, v11, v7
-; CGP-NEXT:    v_mul_lo_u32 v15, v11, v7
-; CGP-NEXT:    v_xor_b32_e32 v3, v3, v9
-; CGP-NEXT:    v_add_i32_e32 v13, vcc, v13, v14
-; CGP-NEXT:    v_add_i32_e32 v13, vcc, v13, v16
-; CGP-NEXT:    v_mul_lo_u32 v14, v10, v15
-; CGP-NEXT:    v_mul_lo_u32 v16, v7, v13
-; CGP-NEXT:    v_mul_hi_u32 v17, v7, v15
-; CGP-NEXT:    v_mul_hi_u32 v15, v10, v15
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v16
-; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v17
+; CGP-NEXT:    v_cvt_u32_f32_e32 v8, v8
+; CGP-NEXT:    v_mul_lo_u32 v12, v10, v7
+; CGP-NEXT:    v_mul_lo_u32 v11, v9, v8
+; CGP-NEXT:    v_mul_hi_u32 v14, v9, v7
+; CGP-NEXT:    v_mul_lo_u32 v13, v9, v7
+; CGP-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
+; CGP-NEXT:    v_add_i32_e32 v11, vcc, v11, v14
+; CGP-NEXT:    v_mul_lo_u32 v12, v8, v13
+; CGP-NEXT:    v_mul_lo_u32 v14, v7, v11
+; CGP-NEXT:    v_mul_hi_u32 v17, v7, v13
+; CGP-NEXT:    v_add_i32_e32 v16, vcc, v2, v15
+; CGP-NEXT:    v_addc_u32_e32 v3, vcc, v3, v15, vcc
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v14
+; CGP-NEXT:    v_mul_lo_u32 v18, v8, v11
+; CGP-NEXT:    v_mul_hi_u32 v13, v8, v13
 ; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v17, v10, v13
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v16, v14
-; CGP-NEXT:    v_mul_hi_u32 v16, v7, v13
-; CGP-NEXT:    v_mul_hi_u32 v13, v10, v13
-; CGP-NEXT:    v_add_i32_e32 v15, vcc, v17, v15
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v17
+; CGP-NEXT:    v_mul_hi_u32 v17, v7, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v14, v12
+; CGP-NEXT:    v_add_i32_e32 v13, vcc, v18, v13
+; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v13, vcc, v13, v17
 ; CGP-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v15, vcc, v15, v16
-; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v16, vcc, v17, v16
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
-; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v15, vcc, v16, v15
-; CGP-NEXT:    v_add_i32_e32 v13, vcc, v13, v15
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v14
-; CGP-NEXT:    v_addc_u32_e64 v14, s[4:5], v10, v13, vcc
-; CGP-NEXT:    v_mul_lo_u32 v12, v12, v7
-; CGP-NEXT:    v_mul_lo_u32 v15, v11, v14
-; CGP-NEXT:    v_mul_lo_u32 v16, v11, v7
-; CGP-NEXT:    v_mul_hi_u32 v11, v11, v7
+; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v17
+; CGP-NEXT:    v_mul_hi_u32 v11, v8, v11
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
+; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
+; CGP-NEXT:    v_add_i32_e32 v11, vcc, v11, v13
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v12
+; CGP-NEXT:    v_addc_u32_e64 v12, s[4:5], v8, v11, vcc
+; CGP-NEXT:    v_mul_lo_u32 v10, v10, v7
+; CGP-NEXT:    v_mul_lo_u32 v13, v9, v12
+; CGP-NEXT:    v_mul_hi_u32 v14, v9, v7
+; CGP-NEXT:    v_mul_lo_u32 v9, v9, v7
+; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v11
 ; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v13
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v15
-; CGP-NEXT:    v_mul_hi_u32 v13, v7, v16
-; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v12, v11
-; CGP-NEXT:    v_mul_lo_u32 v12, v14, v16
-; CGP-NEXT:    v_mul_lo_u32 v15, v7, v11
-; CGP-NEXT:    v_mul_hi_u32 v16, v14, v16
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v15
-; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v13
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; CGP-NEXT:    v_mul_lo_u32 v13, v14, v11
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v15, v12
-; CGP-NEXT:    v_mul_hi_u32 v15, v7, v11
-; CGP-NEXT:    v_mul_hi_u32 v11, v14, v11
-; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v16
-; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v15
-; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v15, s[4:5], v16, v15
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v13, v12
+; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v14
+; CGP-NEXT:    v_mul_lo_u32 v13, v12, v9
+; CGP-NEXT:    v_mul_lo_u32 v14, v7, v10
+; CGP-NEXT:    v_mul_hi_u32 v11, v7, v9
+; CGP-NEXT:    v_mul_lo_u32 v17, v12, v10
+; CGP-NEXT:    v_mul_hi_u32 v9, v12, v9
+; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v14
+; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v13, v11
+; CGP-NEXT:    v_mul_hi_u32 v13, v7, v10
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v14, v11
+; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v17, v9
+; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v13
 ; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v15, v13
-; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v13
-; CGP-NEXT:    v_addc_u32_e32 v10, vcc, v10, v11, vcc
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v12
-; CGP-NEXT:    v_addc_u32_e32 v10, vcc, 0, v10, vcc
-; CGP-NEXT:    v_mul_lo_u32 v11, v3, v7
-; CGP-NEXT:    v_mul_lo_u32 v12, v8, v10
-; CGP-NEXT:    v_mul_hi_u32 v13, v8, v7
+; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v14, v13
+; CGP-NEXT:    v_mul_hi_u32 v10, v12, v10
+; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v13, v11
+; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v11
+; CGP-NEXT:    v_addc_u32_e32 v8, vcc, v8, v10, vcc
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; CGP-NEXT:    v_xor_b32_e32 v16, v16, v15
+; CGP-NEXT:    v_xor_b32_e32 v3, v3, v15
+; CGP-NEXT:    v_addc_u32_e32 v8, vcc, 0, v8, vcc
+; CGP-NEXT:    v_mul_lo_u32 v9, v3, v7
+; CGP-NEXT:    v_mul_lo_u32 v10, v16, v8
+; CGP-NEXT:    v_mul_hi_u32 v11, v16, v7
+; CGP-NEXT:    v_mul_lo_u32 v12, v3, v8
 ; CGP-NEXT:    v_mul_hi_u32 v7, v3, v7
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v11, v13
-; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v13, v3, v10
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
-; CGP-NEXT:    v_mul_hi_u32 v12, v8, v10
-; CGP-NEXT:    v_mul_hi_u32 v10, v3, v10
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v13, v7
-; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v12
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; CGP-NEXT:    v_mul_hi_u32 v11, v16, v8
+; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v12, v7
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
 ; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v11
 ; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
 ; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
-; CGP-NEXT:    v_mul_lo_u32 v11, v4, v7
-; CGP-NEXT:    v_mul_lo_u32 v10, v5, v10
-; CGP-NEXT:    v_mul_lo_u32 v12, v5, v7
-; CGP-NEXT:    v_mul_hi_u32 v7, v5, v7
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
-; CGP-NEXT:    v_sub_i32_e32 v8, vcc, v8, v12
-; CGP-NEXT:    v_subb_u32_e64 v10, s[4:5], v3, v7, vcc
-; CGP-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v7
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v10, v4
-; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v8, v5
-; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], v10, v4
+; CGP-NEXT:    v_mul_hi_u32 v8, v3, v8
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
+; CGP-NEXT:    v_mul_lo_u32 v9, v4, v7
+; CGP-NEXT:    v_mul_lo_u32 v8, v5, v8
+; CGP-NEXT:    v_mul_hi_u32 v10, v5, v7
+; CGP-NEXT:    v_mul_lo_u32 v7, v5, v7
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; CGP-NEXT:    v_sub_i32_e32 v7, vcc, v16, v7
+; CGP-NEXT:    v_subb_u32_e64 v9, s[4:5], v3, v8, vcc
+; CGP-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v8
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v9, v4
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v5
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], v9, v4
 ; CGP-NEXT:    v_subb_u32_e32 v3, vcc, v3, v4, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v7, v7, v11, s[4:5]
-; CGP-NEXT:    v_sub_i32_e32 v11, vcc, v8, v5
-; CGP-NEXT:    v_subbrev_u32_e64 v12, s[4:5], 0, v3, vcc
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v12, v4
-; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v11, v5
+; CGP-NEXT:    v_cndmask_b32_e64 v8, v8, v10, s[4:5]
+; CGP-NEXT:    v_sub_i32_e32 v10, vcc, v7, v5
+; CGP-NEXT:    v_subbrev_u32_e64 v11, s[4:5], 0, v3, vcc
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v11, v4
+; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v10, v5
 ; CGP-NEXT:    v_subb_u32_e32 v3, vcc, v3, v4, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], v12, v4
-; CGP-NEXT:    v_sub_i32_e32 v4, vcc, v11, v5
-; CGP-NEXT:    v_cndmask_b32_e64 v13, v13, v14, s[4:5]
+; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], v11, v4
+; CGP-NEXT:    v_sub_i32_e32 v4, vcc, v10, v5
+; CGP-NEXT:    v_cndmask_b32_e64 v12, v12, v13, s[4:5]
 ; CGP-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v13
-; CGP-NEXT:    v_cndmask_b32_e32 v4, v11, v4, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v3, v12, v3, vcc
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
-; CGP-NEXT:    v_cndmask_b32_e32 v4, v8, v4, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v3, v10, v3, vcc
-; CGP-NEXT:    v_xor_b32_e32 v4, v4, v9
-; CGP-NEXT:    v_xor_b32_e32 v3, v3, v9
-; CGP-NEXT:    v_sub_i32_e32 v4, vcc, v4, v9
-; CGP-NEXT:    v_subb_u32_e32 v5, vcc, v3, v9, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v12
+; CGP-NEXT:    v_cndmask_b32_e32 v4, v10, v4, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v3, v11, v3, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v8
+; CGP-NEXT:    v_cndmask_b32_e32 v4, v7, v4, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v3, v9, v3, vcc
+; CGP-NEXT:    v_xor_b32_e32 v4, v4, v15
+; CGP-NEXT:    v_xor_b32_e32 v3, v3, v15
+; CGP-NEXT:    v_sub_i32_e32 v4, vcc, v4, v15
+; CGP-NEXT:    v_subb_u32_e32 v5, vcc, v3, v15, vcc
 ; CGP-NEXT:  BB2_6: ; %Flow
 ; CGP-NEXT:    s_or_saveexec_b64 s[4:5], s[6:7]
 ; CGP-NEXT:    s_xor_b64 exec, exec, s[4:5]
@@ -1038,139 +1038,139 @@
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:    v_cvt_f32_u32_e32 v2, 0x1000
-; CHECK-NEXT:    v_cvt_f32_ubyte0_e32 v4, 0
+; CHECK-NEXT:    v_cvt_f32_ubyte0_e32 v3, 0
 ; CHECK-NEXT:    s_movk_i32 s6, 0xf000
-; CHECK-NEXT:    v_ashrrev_i32_e32 v3, 31, v1
-; CHECK-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v4
+; CHECK-NEXT:    v_ashrrev_i32_e32 v8, 31, v1
+; CHECK-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
 ; CHECK-NEXT:    v_rcp_iflag_f32_e32 v2, v2
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
-; CHECK-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
-; CHECK-NEXT:    v_xor_b32_e32 v0, v0, v3
 ; CHECK-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
-; CHECK-NEXT:    v_mul_f32_e32 v4, 0x2f800000, v2
-; CHECK-NEXT:    v_trunc_f32_e32 v4, v4
-; CHECK-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v4
+; CHECK-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
+; CHECK-NEXT:    v_trunc_f32_e32 v3, v3
+; CHECK-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
 ; CHECK-NEXT:    v_cvt_u32_f32_e32 v2, v2
-; CHECK-NEXT:    v_cvt_u32_f32_e32 v4, v4
-; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v3
+; CHECK-NEXT:    v_cvt_u32_f32_e32 v3, v3
 ; CHECK-NEXT:    v_mul_lo_u32 v5, -1, v2
-; CHECK-NEXT:    v_mul_lo_u32 v6, s6, v4
-; CHECK-NEXT:    v_mul_hi_u32 v8, s6, v2
-; CHECK-NEXT:    v_mul_lo_u32 v7, s6, v2
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
-; CHECK-NEXT:    v_mul_lo_u32 v6, v4, v7
-; CHECK-NEXT:    v_mul_lo_u32 v8, v2, v5
-; CHECK-NEXT:    v_mul_hi_u32 v9, v2, v7
-; CHECK-NEXT:    v_mul_hi_u32 v7, v4, v7
-; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
-; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CHECK-NEXT:    v_mul_lo_u32 v4, s6, v3
+; CHECK-NEXT:    v_mul_hi_u32 v7, s6, v2
+; CHECK-NEXT:    v_mul_lo_u32 v6, s6, v2
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; CHECK-NEXT:    v_mul_lo_u32 v5, v3, v6
+; CHECK-NEXT:    v_mul_lo_u32 v7, v2, v4
+; CHECK-NEXT:    v_mul_hi_u32 v9, v2, v6
+; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v8
+; CHECK-NEXT:    v_addc_u32_e32 v1, vcc, v1, v8, vcc
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; CHECK-NEXT:    v_mul_lo_u32 v10, v3, v4
+; CHECK-NEXT:    v_mul_hi_u32 v6, v3, v6
+; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v9
+; CHECK-NEXT:    v_mul_hi_u32 v9, v2, v4
+; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
+; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v10, v6
+; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
-; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v9, v4, v5
-; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
-; CHECK-NEXT:    v_mul_hi_u32 v8, v2, v5
-; CHECK-NEXT:    v_mul_hi_u32 v5, v4, v5
-; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v9, v7
 ; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; CHECK-NEXT:    v_mul_hi_u32 v4, v3, v4
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
+; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
-; CHECK-NEXT:    v_addc_u32_e64 v6, s[4:5], v4, v5, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v7, -1, v2
-; CHECK-NEXT:    v_mul_lo_u32 v8, s6, v6
-; CHECK-NEXT:    v_mul_hi_u32 v10, s6, v2
-; CHECK-NEXT:    v_mul_lo_u32 v9, s6, v2
-; CHECK-NEXT:    v_add_i32_e64 v4, s[4:5], v4, v5
-; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v8
-; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v10
-; CHECK-NEXT:    v_mul_lo_u32 v8, v6, v9
-; CHECK-NEXT:    v_mul_lo_u32 v10, v2, v7
-; CHECK-NEXT:    v_mul_hi_u32 v5, v2, v9
-; CHECK-NEXT:    v_mul_hi_u32 v9, v6, v9
-; CHECK-NEXT:    s_movk_i32 s6, 0x1000
-; CHECK-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v10
-; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v5, s[4:5], v8, v5
-; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, s[4:5]
-; CHECK-NEXT:    v_mul_lo_u32 v8, v6, v7
-; CHECK-NEXT:    v_add_i32_e64 v5, s[4:5], v10, v5
-; CHECK-NEXT:    v_mul_hi_u32 v10, v2, v7
-; CHECK-NEXT:    v_mul_hi_u32 v6, v6, v7
-; CHECK-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; CHECK-NEXT:    v_addc_u32_e64 v5, s[4:5], v3, v4, vcc
+; CHECK-NEXT:    v_mul_lo_u32 v6, -1, v2
+; CHECK-NEXT:    v_mul_lo_u32 v7, s6, v5
+; CHECK-NEXT:    v_mul_hi_u32 v9, s6, v2
+; CHECK-NEXT:    v_mul_lo_u32 v10, s6, v2
+; CHECK-NEXT:    v_add_i32_e64 v3, s[4:5], v3, v4
+; CHECK-NEXT:    v_add_i32_e64 v6, s[4:5], v6, v7
+; CHECK-NEXT:    v_add_i32_e64 v6, s[4:5], v6, v9
+; CHECK-NEXT:    v_mul_lo_u32 v7, v5, v10
+; CHECK-NEXT:    v_mul_lo_u32 v9, v2, v6
+; CHECK-NEXT:    v_mul_hi_u32 v4, v2, v10
+; CHECK-NEXT:    v_mul_lo_u32 v11, v5, v6
+; CHECK-NEXT:    v_mul_hi_u32 v10, v5, v10
+; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v9
 ; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v10
+; CHECK-NEXT:    v_add_i32_e64 v4, s[4:5], v7, v4
+; CHECK-NEXT:    v_mul_hi_u32 v7, v2, v6
+; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v4, s[4:5], v9, v4
+; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v10
 ; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v10
-; CHECK-NEXT:    v_add_i32_e64 v5, s[4:5], v8, v5
-; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v9, v8
-; CHECK-NEXT:    v_add_i32_e64 v6, s[4:5], v6, v7
-; CHECK-NEXT:    v_addc_u32_e32 v4, vcc, v4, v6, vcc
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
-; CHECK-NEXT:    v_addc_u32_e32 v4, vcc, 0, v4, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v5, v1, v2
-; CHECK-NEXT:    v_mul_lo_u32 v6, v0, v4
-; CHECK-NEXT:    v_mul_hi_u32 v7, v0, v2
+; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v9, v7
+; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v10, v9
+; CHECK-NEXT:    v_mul_hi_u32 v5, v5, v6
+; CHECK-NEXT:    v_add_i32_e64 v4, s[4:5], v7, v4
+; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v6, s[4:5], v9, v6
+; CHECK-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v6
+; CHECK-NEXT:    v_addc_u32_e32 v3, vcc, v3, v5, vcc
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
+; CHECK-NEXT:    v_xor_b32_e32 v0, v0, v8
+; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v8
+; CHECK-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; CHECK-NEXT:    v_mul_lo_u32 v4, v1, v2
+; CHECK-NEXT:    v_mul_lo_u32 v5, v0, v3
+; CHECK-NEXT:    v_mul_hi_u32 v6, v0, v2
+; CHECK-NEXT:    v_mul_lo_u32 v7, v1, v3
 ; CHECK-NEXT:    v_mul_hi_u32 v2, v1, v2
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
-; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
 ; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v7, v1, v4
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; CHECK-NEXT:    v_mul_hi_u32 v6, v0, v4
-; CHECK-NEXT:    v_mul_hi_u32 v4, v1, v4
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; CHECK-NEXT:    v_mul_hi_u32 v6, v0, v3
+; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v7, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
 ; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
-; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
-; CHECK-NEXT:    v_mul_lo_u32 v5, 0, v2
-; CHECK-NEXT:    v_mul_lo_u32 v4, s6, v4
-; CHECK-NEXT:    v_mul_lo_u32 v6, s6, v2
-; CHECK-NEXT:    v_mul_hi_u32 v2, s6, v2
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
+; CHECK-NEXT:    v_mul_hi_u32 v3, v1, v3
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
+; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
-; CHECK-NEXT:    v_sub_i32_e32 v0, vcc, v0, v6
-; CHECK-NEXT:    v_subb_u32_e64 v4, s[4:5], v1, v2, vcc
-; CHECK-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v2
-; CHECK-NEXT:    v_cmp_le_u32_e64 s[4:5], 0, v4
-; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, -1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v3, v4
+; CHECK-NEXT:    s_movk_i32 s6, 0x1000
+; CHECK-NEXT:    v_mul_lo_u32 v4, 0, v2
+; CHECK-NEXT:    v_mul_lo_u32 v3, s6, v3
+; CHECK-NEXT:    v_mul_hi_u32 v5, s6, v2
+; CHECK-NEXT:    v_mul_lo_u32 v2, s6, v2
+; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
+; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
+; CHECK-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
+; CHECK-NEXT:    v_subb_u32_e64 v2, s[4:5], v1, v3, vcc
+; CHECK-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v3
+; CHECK-NEXT:    v_cmp_le_u32_e64 s[4:5], 0, v2
+; CHECK-NEXT:    v_cndmask_b32_e64 v3, 0, -1, s[4:5]
 ; CHECK-NEXT:    v_cmp_le_u32_e64 s[4:5], s6, v0
-; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[4:5]
-; CHECK-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v4
+; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[4:5]
+; CHECK-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v2
 ; CHECK-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CHECK-NEXT:    v_cndmask_b32_e64 v2, v2, v5, s[4:5]
-; CHECK-NEXT:    v_subrev_i32_e32 v5, vcc, s6, v0
+; CHECK-NEXT:    v_cndmask_b32_e64 v3, v3, v4, s[4:5]
+; CHECK-NEXT:    v_subrev_i32_e32 v4, vcc, s6, v0
 ; CHECK-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
 ; CHECK-NEXT:    v_cmp_le_u32_e32 vcc, 0, v1
+; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
+; CHECK-NEXT:    v_cmp_le_u32_e32 vcc, s6, v4
 ; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
-; CHECK-NEXT:    v_cmp_le_u32_e32 vcc, s6, v5
-; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
 ; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
-; CHECK-NEXT:    v_cndmask_b32_e32 v6, v6, v7, vcc
-; CHECK-NEXT:    v_subrev_i32_e32 v7, vcc, s6, v5
-; CHECK-NEXT:    v_subbrev_u32_e32 v8, vcc, 0, v1, vcc
-; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
-; CHECK-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc
-; CHECK-NEXT:    v_cndmask_b32_e32 v1, v1, v8, vcc
-; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
-; CHECK-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
-; CHECK-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc
-; CHECK-NEXT:    v_xor_b32_e32 v0, v0, v3
-; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v3
-; CHECK-NEXT:    v_sub_i32_e32 v0, vcc, v0, v3
-; CHECK-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
+; CHECK-NEXT:    v_subrev_i32_e32 v6, vcc, s6, v4
+; CHECK-NEXT:    v_subbrev_u32_e32 v7, vcc, 0, v1, vcc
+; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
+; CHECK-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v1, v1, v7, vcc
+; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v3
+; CHECK-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
+; CHECK-NEXT:    v_xor_b32_e32 v0, v0, v8
+; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v8
+; CHECK-NEXT:    v_sub_i32_e32 v0, vcc, v0, v8
+; CHECK-NEXT:    v_subb_u32_e32 v1, vcc, v1, v8, vcc
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %result = srem i64 %num, 4096
   ret i64 %result
@@ -1198,551 +1198,551 @@
 ; GISEL-NEXT:    v_rcp_iflag_f32_e32 v4, v4
 ; GISEL-NEXT:    s_cmp_lg_u32 s4, 0
 ; GISEL-NEXT:    s_subb_u32 s12, 0, s9
-; GISEL-NEXT:    v_ashrrev_i32_e32 v6, 31, v1
+; GISEL-NEXT:    v_ashrrev_i32_e32 v10, 31, v1
 ; GISEL-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
 ; GISEL-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
 ; GISEL-NEXT:    v_trunc_f32_e32 v5, v5
 ; GISEL-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v4, v4
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v5, v5
-; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v6
-; GISEL-NEXT:    v_addc_u32_e32 v1, vcc, v1, v6, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v7, s12, v4
-; GISEL-NEXT:    v_mul_lo_u32 v8, s11, v5
-; GISEL-NEXT:    v_mul_hi_u32 v10, s11, v4
+; GISEL-NEXT:    v_mul_lo_u32 v6, s12, v4
+; GISEL-NEXT:    v_mul_lo_u32 v7, s11, v5
+; GISEL-NEXT:    v_mul_hi_u32 v8, s11, v4
 ; GISEL-NEXT:    v_mul_lo_u32 v9, s11, v4
-; GISEL-NEXT:    v_xor_b32_e32 v0, v0, v6
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
-; GISEL-NEXT:    v_mul_lo_u32 v8, v5, v9
-; GISEL-NEXT:    v_mul_lo_u32 v10, v4, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; GISEL-NEXT:    v_mul_lo_u32 v7, v5, v9
+; GISEL-NEXT:    v_mul_lo_u32 v8, v4, v6
 ; GISEL-NEXT:    v_mul_hi_u32 v11, v4, v9
+; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v10
+; GISEL-NEXT:    v_addc_u32_e32 v1, vcc, v1, v10, vcc
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; GISEL-NEXT:    v_mul_lo_u32 v12, v5, v6
 ; GISEL-NEXT:    v_mul_hi_u32 v9, v5, v9
-; GISEL-NEXT:    v_xor_b32_e32 v1, v1, v6
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v11, v5, v7
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
-; GISEL-NEXT:    v_mul_hi_u32 v10, v4, v7
-; GISEL-NEXT:    v_mul_hi_u32 v7, v5, v7
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v11, v9
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v11
+; GISEL-NEXT:    v_mul_hi_u32 v11, v4, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v12, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
 ; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; GISEL-NEXT:    v_mul_hi_u32 v6, v5, v6
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
-; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
-; GISEL-NEXT:    v_addc_u32_e64 v8, s[4:5], v5, v7, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v9, s12, v4
-; GISEL-NEXT:    v_mul_lo_u32 v10, s11, v8
-; GISEL-NEXT:    v_mul_hi_u32 v12, s11, v4
-; GISEL-NEXT:    v_mul_lo_u32 v11, s11, v4
-; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v7
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v10
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v12
-; GISEL-NEXT:    v_mul_lo_u32 v10, v8, v11
-; GISEL-NEXT:    v_mul_lo_u32 v12, v4, v9
-; GISEL-NEXT:    v_mul_hi_u32 v7, v4, v11
-; GISEL-NEXT:    v_mul_hi_u32 v11, v8, v11
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v12
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v10, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, s[4:5]
-; GISEL-NEXT:    v_mul_lo_u32 v10, v8, v9
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v12, v7
-; GISEL-NEXT:    v_mul_hi_u32 v12, v4, v9
-; GISEL-NEXT:    v_mul_hi_u32 v8, v8, v9
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v11
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; GISEL-NEXT:    v_addc_u32_e64 v7, s[4:5], v5, v6, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v8, s12, v4
+; GISEL-NEXT:    v_mul_lo_u32 v9, s11, v7
+; GISEL-NEXT:    v_mul_hi_u32 v11, s11, v4
+; GISEL-NEXT:    v_mul_lo_u32 v12, s11, v4
+; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v6
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v11
+; GISEL-NEXT:    v_mul_lo_u32 v9, v7, v12
+; GISEL-NEXT:    v_mul_lo_u32 v11, v4, v8
+; GISEL-NEXT:    v_mul_hi_u32 v6, v4, v12
+; GISEL-NEXT:    v_mul_lo_u32 v13, v7, v8
+; GISEL-NEXT:    v_mul_hi_u32 v12, v7, v12
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v11
 ; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v12
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v9, v6
+; GISEL-NEXT:    v_mul_hi_u32 v9, v4, v8
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v11, v6
+; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v13, v12
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v10, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v10
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
-; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v8, vcc
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v12, v11
+; GISEL-NEXT:    v_mul_hi_u32 v7, v7, v8
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v9, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v11, v8
+; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v8
+; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v7, vcc
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; GISEL-NEXT:    v_xor_b32_e32 v0, v0, v10
+; GISEL-NEXT:    v_xor_b32_e32 v1, v1, v10
 ; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v7, v1, v4
-; GISEL-NEXT:    v_mul_lo_u32 v8, v0, v5
-; GISEL-NEXT:    v_mul_hi_u32 v10, v0, v4
+; GISEL-NEXT:    v_mul_lo_u32 v6, v1, v4
+; GISEL-NEXT:    v_mul_lo_u32 v7, v0, v5
+; GISEL-NEXT:    v_mul_hi_u32 v8, v0, v4
+; GISEL-NEXT:    v_mul_lo_u32 v9, v1, v5
 ; GISEL-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GISEL-NEXT:    v_mov_b32_e32 v9, s9
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
 ; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v10, v1, v5
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
 ; GISEL-NEXT:    v_mul_hi_u32 v8, v0, v5
-; GISEL-NEXT:    v_mul_hi_u32 v5, v1, v5
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v10, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v9, v4
+; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; GISEL-NEXT:    v_mul_lo_u32 v7, s9, v4
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; GISEL-NEXT:    v_mul_hi_u32 v5, v1, v5
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
+; GISEL-NEXT:    v_mul_lo_u32 v6, s9, v4
 ; GISEL-NEXT:    v_mul_lo_u32 v5, s8, v5
-; GISEL-NEXT:    v_mul_lo_u32 v8, s8, v4
-; GISEL-NEXT:    v_mul_hi_u32 v4, s8, v4
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v8
-; GISEL-NEXT:    v_subb_u32_e64 v5, s[4:5], v1, v4, vcc
-; GISEL-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v4
-; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s9, v5
-; GISEL-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[4:5]
+; GISEL-NEXT:    v_mul_hi_u32 v7, s8, v4
+; GISEL-NEXT:    v_mul_lo_u32 v4, s8, v4
+; GISEL-NEXT:    v_mov_b32_e32 v8, s9
+; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
+; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
+; GISEL-NEXT:    v_subb_u32_e64 v4, s[4:5], v1, v5, vcc
+; GISEL-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v5
+; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s9, v4
+; GISEL-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[4:5]
 ; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s8, v0
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], s9, v5
-; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v9, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v4, v4, v7, s[4:5]
-; GISEL-NEXT:    v_subrev_i32_e32 v7, vcc, s8, v0
-; GISEL-NEXT:    v_subbrev_u32_e64 v8, s[4:5], 0, v1, vcc
-; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s9, v8
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s8, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], s9, v4
+; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v8, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v5, v5, v6, s[4:5]
+; GISEL-NEXT:    v_subrev_i32_e32 v6, vcc, s8, v0
+; GISEL-NEXT:    v_subbrev_u32_e64 v7, s[4:5], 0, v1, vcc
+; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s9, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s8, v6
 ; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], s9, v8
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, v10, v11, s[4:5]
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], s9, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, v9, v11, s[4:5]
 ; GISEL-NEXT:    s_add_u32 s4, s10, 0
-; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v9, vcc
 ; GISEL-NEXT:    s_cselect_b32 s5, 1, 0
-; GISEL-NEXT:    v_subrev_i32_e32 v9, vcc, s8, v7
+; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v8, vcc
 ; GISEL-NEXT:    s_and_b32 s5, s5, 1
 ; GISEL-NEXT:    s_cmp_lg_u32 s5, 0
+; GISEL-NEXT:    v_subrev_i32_e32 v8, vcc, s8, v6
 ; GISEL-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
 ; GISEL-NEXT:    s_addc_u32 s5, 0, 0
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v9
 ; GISEL-NEXT:    s_xor_b64 s[6:7], s[4:5], s[6:7]
-; GISEL-NEXT:    v_cndmask_b32_e32 v7, v7, v9, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v1, v8, v1, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
-; GISEL-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc
-; GISEL-NEXT:    v_cvt_f32_u32_e32 v4, s6
-; GISEL-NEXT:    v_cvt_f32_u32_e32 v5, s7
+; GISEL-NEXT:    v_cndmask_b32_e32 v6, v6, v8, vcc
+; GISEL-NEXT:    v_cvt_f32_u32_e32 v8, s6
+; GISEL-NEXT:    v_cvt_f32_u32_e32 v9, s7
+; GISEL-NEXT:    v_cndmask_b32_e32 v1, v7, v1, vcc
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
+; GISEL-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc
+; GISEL-NEXT:    v_mac_f32_e32 v8, 0x4f800000, v9
+; GISEL-NEXT:    v_rcp_iflag_f32_e32 v5, v8
 ; GISEL-NEXT:    s_sub_u32 s8, 0, s6
 ; GISEL-NEXT:    s_cselect_b32 s4, 1, 0
 ; GISEL-NEXT:    s_and_b32 s4, s4, 1
-; GISEL-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
-; GISEL-NEXT:    v_rcp_iflag_f32_e32 v4, v4
-; GISEL-NEXT:    s_cmp_lg_u32 s4, 0
-; GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v7, vcc
-; GISEL-NEXT:    s_subb_u32 s9, 0, s7
-; GISEL-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
+; GISEL-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v5
 ; GISEL-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
 ; GISEL-NEXT:    v_trunc_f32_e32 v5, v5
 ; GISEL-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v4, v4
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v5, v5
-; GISEL-NEXT:    v_xor_b32_e32 v0, v0, v6
-; GISEL-NEXT:    v_xor_b32_e32 v1, v1, v6
-; GISEL-NEXT:    v_mul_lo_u32 v7, s9, v4
-; GISEL-NEXT:    v_mul_lo_u32 v8, s8, v5
-; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v6
-; GISEL-NEXT:    v_mul_hi_u32 v10, s8, v4
-; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v6, vcc
-; GISEL-NEXT:    v_ashrrev_i32_e32 v6, 31, v3
+; GISEL-NEXT:    s_cmp_lg_u32 s4, 0
+; GISEL-NEXT:    s_subb_u32 s9, 0, s7
+; GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v6, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v6, s9, v4
+; GISEL-NEXT:    v_mul_lo_u32 v7, s8, v5
+; GISEL-NEXT:    v_mul_hi_u32 v8, s8, v4
 ; GISEL-NEXT:    v_mul_lo_u32 v9, s8, v4
-; GISEL-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
-; GISEL-NEXT:    v_addc_u32_e32 v3, vcc, v3, v6, vcc
+; GISEL-NEXT:    v_ashrrev_i32_e32 v11, 31, v3
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; GISEL-NEXT:    v_mul_lo_u32 v7, v5, v9
+; GISEL-NEXT:    v_mul_lo_u32 v8, v4, v6
+; GISEL-NEXT:    v_mul_hi_u32 v12, v4, v9
+; GISEL-NEXT:    v_add_i32_e32 v2, vcc, v2, v11
+; GISEL-NEXT:    v_addc_u32_e32 v3, vcc, v3, v11, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
-; GISEL-NEXT:    v_mul_lo_u32 v8, v5, v9
-; GISEL-NEXT:    v_mul_lo_u32 v10, v4, v7
-; GISEL-NEXT:    v_mul_hi_u32 v11, v4, v9
+; GISEL-NEXT:    v_mul_lo_u32 v13, v5, v6
 ; GISEL-NEXT:    v_mul_hi_u32 v9, v5, v9
-; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v6
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v11, v5, v7
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
-; GISEL-NEXT:    v_mul_hi_u32 v10, v4, v7
-; GISEL-NEXT:    v_mul_hi_u32 v7, v5, v7
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v11, v9
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v12
+; GISEL-NEXT:    v_mul_hi_u32 v12, v4, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v13, v9
 ; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
-; GISEL-NEXT:    v_addc_u32_e64 v8, s[4:5], v5, v7, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v9, s9, v4
-; GISEL-NEXT:    v_mul_lo_u32 v10, s8, v8
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v12
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
+; GISEL-NEXT:    v_mul_hi_u32 v6, v5, v6
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; GISEL-NEXT:    v_addc_u32_e64 v7, s[4:5], v5, v6, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v8, s9, v4
+; GISEL-NEXT:    v_mul_lo_u32 v9, s8, v7
 ; GISEL-NEXT:    v_mul_hi_u32 v12, s8, v4
-; GISEL-NEXT:    v_mul_lo_u32 v11, s8, v4
-; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v7
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v10
+; GISEL-NEXT:    v_mul_lo_u32 v13, s8, v4
+; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v6
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v12
+; GISEL-NEXT:    v_mul_lo_u32 v9, v7, v13
+; GISEL-NEXT:    v_mul_lo_u32 v12, v4, v8
+; GISEL-NEXT:    v_mul_hi_u32 v6, v4, v13
+; GISEL-NEXT:    v_mul_lo_u32 v14, v7, v8
+; GISEL-NEXT:    v_mul_hi_u32 v13, v7, v13
 ; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v12
-; GISEL-NEXT:    v_mul_lo_u32 v10, v8, v11
-; GISEL-NEXT:    v_mul_lo_u32 v12, v4, v9
-; GISEL-NEXT:    v_mul_hi_u32 v7, v4, v11
-; GISEL-NEXT:    v_mul_hi_u32 v11, v8, v11
-; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v6
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v12
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v10, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, s[4:5]
-; GISEL-NEXT:    v_mul_lo_u32 v10, v8, v9
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v12, v7
-; GISEL-NEXT:    v_mul_hi_u32 v12, v4, v9
-; GISEL-NEXT:    v_mul_hi_u32 v8, v8, v9
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v11
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v12
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v9, v6
+; GISEL-NEXT:    v_mul_hi_u32 v9, v4, v8
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v12, v6
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v14, v13
+; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v12, v9
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v10, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v10
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
-; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v8, vcc
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v13, v12
+; GISEL-NEXT:    v_mul_hi_u32 v7, v7, v8
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v9, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v12, v8
+; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v8
+; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v7, vcc
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v11
+; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v11
 ; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v7, v3, v4
-; GISEL-NEXT:    v_mul_lo_u32 v8, v2, v5
-; GISEL-NEXT:    v_mul_hi_u32 v10, v2, v4
+; GISEL-NEXT:    v_mul_lo_u32 v6, v3, v4
+; GISEL-NEXT:    v_mul_lo_u32 v7, v2, v5
+; GISEL-NEXT:    v_xor_b32_e32 v0, v0, v10
+; GISEL-NEXT:    v_mul_hi_u32 v8, v2, v4
+; GISEL-NEXT:    v_xor_b32_e32 v1, v1, v10
+; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v10
+; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v10, vcc
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; GISEL-NEXT:    v_mul_lo_u32 v9, v3, v5
 ; GISEL-NEXT:    v_mul_hi_u32 v4, v3, v4
-; GISEL-NEXT:    v_mov_b32_e32 v9, s7
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
 ; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v10, v3, v5
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
 ; GISEL-NEXT:    v_mul_hi_u32 v8, v2, v5
-; GISEL-NEXT:    v_mul_hi_u32 v5, v3, v5
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v10, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v9, v4
+; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; GISEL-NEXT:    v_mul_lo_u32 v7, s7, v4
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; GISEL-NEXT:    v_mul_hi_u32 v5, v3, v5
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
+; GISEL-NEXT:    v_mul_lo_u32 v6, s7, v4
 ; GISEL-NEXT:    v_mul_lo_u32 v5, s6, v5
-; GISEL-NEXT:    v_mul_lo_u32 v8, s6, v4
-; GISEL-NEXT:    v_mul_hi_u32 v4, s6, v4
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v8
-; GISEL-NEXT:    v_subb_u32_e64 v5, s[4:5], v3, v4, vcc
-; GISEL-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v4
-; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s7, v5
-; GISEL-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[4:5]
+; GISEL-NEXT:    v_mul_hi_u32 v7, s6, v4
+; GISEL-NEXT:    v_mul_lo_u32 v4, s6, v4
+; GISEL-NEXT:    v_mov_b32_e32 v8, s7
+; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
+; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v4
+; GISEL-NEXT:    v_subb_u32_e64 v4, s[4:5], v3, v5, vcc
+; GISEL-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v5
+; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s7, v4
+; GISEL-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[4:5]
 ; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s6, v2
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], s7, v5
-; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v9, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v4, v4, v7, s[4:5]
-; GISEL-NEXT:    v_subrev_i32_e32 v7, vcc, s6, v2
-; GISEL-NEXT:    v_subbrev_u32_e64 v8, s[4:5], 0, v3, vcc
-; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s7, v8
-; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v9, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], s7, v4
+; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v8, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v5, v5, v6, s[4:5]
+; GISEL-NEXT:    v_subrev_i32_e32 v6, vcc, s6, v2
+; GISEL-NEXT:    v_subbrev_u32_e64 v7, s[4:5], 0, v3, vcc
+; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s7, v7
+; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v8, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s6, v6
+; GISEL-NEXT:    v_subrev_i32_e32 v8, vcc, s6, v6
 ; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s6, v7
-; GISEL-NEXT:    v_subrev_i32_e32 v9, vcc, s6, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], s7, v8
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, v10, v11, s[4:5]
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], s7, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, v9, v10, s[4:5]
 ; GISEL-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
-; GISEL-NEXT:    v_cndmask_b32_e32 v7, v7, v9, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v3, v8, v3, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
-; GISEL-NEXT:    v_cndmask_b32_e32 v2, v2, v7, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc
-; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v6
-; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v6
-; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v6
-; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v6, vcc
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v9
+; GISEL-NEXT:    v_cndmask_b32_e32 v6, v6, v8, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v3, v7, v3, vcc
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
+; GISEL-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
+; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v11
+; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v11
+; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v11
+; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v11, vcc
 ; GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; CGP-LABEL: v_srem_v2i64_pow2k_denom:
 ; CGP:       ; %bb.0:
 ; CGP-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CGP-NEXT:    v_cvt_f32_u32_e32 v4, 0x1000
-; CGP-NEXT:    v_cvt_f32_ubyte0_e32 v6, 0
+; CGP-NEXT:    v_cvt_f32_ubyte0_e32 v5, 0
 ; CGP-NEXT:    s_movk_i32 s6, 0xf000
-; CGP-NEXT:    v_ashrrev_i32_e32 v5, 31, v1
-; CGP-NEXT:    v_mov_b32_e32 v7, v4
-; CGP-NEXT:    v_mac_f32_e32 v7, 0x4f800000, v6
-; CGP-NEXT:    v_rcp_iflag_f32_e32 v7, v7
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v5
-; CGP-NEXT:    v_addc_u32_e32 v1, vcc, v1, v5, vcc
-; CGP-NEXT:    v_xor_b32_e32 v0, v0, v5
-; CGP-NEXT:    v_mul_f32_e32 v7, 0x5f7ffffc, v7
-; CGP-NEXT:    v_mul_f32_e32 v8, 0x2f800000, v7
-; CGP-NEXT:    v_trunc_f32_e32 v8, v8
-; CGP-NEXT:    v_mac_f32_e32 v7, 0xcf800000, v8
-; CGP-NEXT:    v_cvt_u32_f32_e32 v7, v7
-; CGP-NEXT:    v_cvt_u32_f32_e32 v8, v8
-; CGP-NEXT:    v_xor_b32_e32 v1, v1, v5
+; CGP-NEXT:    v_ashrrev_i32_e32 v12, 31, v1
+; CGP-NEXT:    v_mov_b32_e32 v6, v4
+; CGP-NEXT:    v_mac_f32_e32 v6, 0x4f800000, v5
+; CGP-NEXT:    v_rcp_iflag_f32_e32 v6, v6
 ; CGP-NEXT:    s_movk_i32 s7, 0x1000
-; CGP-NEXT:    v_mul_lo_u32 v9, -1, v7
-; CGP-NEXT:    v_mul_lo_u32 v10, s6, v8
-; CGP-NEXT:    v_mul_hi_u32 v12, s6, v7
-; CGP-NEXT:    v_mul_lo_u32 v11, s6, v7
-; CGP-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v6
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
-; CGP-NEXT:    v_mul_lo_u32 v10, v8, v11
-; CGP-NEXT:    v_mul_lo_u32 v12, v7, v9
-; CGP-NEXT:    v_mul_hi_u32 v13, v7, v11
-; CGP-NEXT:    v_mul_hi_u32 v11, v8, v11
+; CGP-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
 ; CGP-NEXT:    v_rcp_iflag_f32_e32 v4, v4
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v13
-; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v13, v8, v9
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v12, v10
-; CGP-NEXT:    v_mul_hi_u32 v12, v7, v9
-; CGP-NEXT:    v_mul_hi_u32 v9, v8, v9
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v13, v11
-; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
-; CGP-NEXT:    v_addc_u32_e64 v10, s[4:5], v8, v9, vcc
-; CGP-NEXT:    v_mul_lo_u32 v11, -1, v7
-; CGP-NEXT:    v_mul_lo_u32 v12, s6, v10
-; CGP-NEXT:    v_mul_hi_u32 v14, s6, v7
-; CGP-NEXT:    v_mul_lo_u32 v13, s6, v7
-; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
-; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
-; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v14
-; CGP-NEXT:    v_mul_lo_u32 v12, v10, v13
-; CGP-NEXT:    v_mul_lo_u32 v14, v7, v11
-; CGP-NEXT:    v_mul_hi_u32 v9, v7, v13
-; CGP-NEXT:    v_mul_hi_u32 v13, v10, v13
+; CGP-NEXT:    v_mul_f32_e32 v6, 0x5f7ffffc, v6
+; CGP-NEXT:    v_mul_f32_e32 v7, 0x2f800000, v6
+; CGP-NEXT:    v_trunc_f32_e32 v7, v7
+; CGP-NEXT:    v_mac_f32_e32 v6, 0xcf800000, v7
+; CGP-NEXT:    v_cvt_u32_f32_e32 v6, v6
+; CGP-NEXT:    v_cvt_u32_f32_e32 v7, v7
 ; CGP-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v14
-; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v12, v9
-; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
-; CGP-NEXT:    v_mul_lo_u32 v12, v10, v11
-; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v14, v9
-; CGP-NEXT:    v_mul_hi_u32 v14, v7, v11
-; CGP-NEXT:    v_mul_hi_u32 v10, v10, v11
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v13
-; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v14
-; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v14
-; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v12, v9
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v13, v12
-; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v11
-; CGP-NEXT:    v_addc_u32_e32 v8, vcc, v8, v10, vcc
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
-; CGP-NEXT:    v_addc_u32_e32 v8, vcc, 0, v8, vcc
-; CGP-NEXT:    v_mul_lo_u32 v9, v1, v7
-; CGP-NEXT:    v_mul_lo_u32 v10, v0, v8
-; CGP-NEXT:    v_mul_hi_u32 v11, v0, v7
-; CGP-NEXT:    v_mul_hi_u32 v7, v1, v7
-; CGP-NEXT:    v_ashrrev_i32_e32 v6, 31, v3
+; CGP-NEXT:    v_mul_lo_u32 v9, -1, v6
+; CGP-NEXT:    v_mul_lo_u32 v8, s6, v7
+; CGP-NEXT:    v_mul_hi_u32 v10, s6, v6
+; CGP-NEXT:    v_mul_lo_u32 v11, s6, v6
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; CGP-NEXT:    v_mul_lo_u32 v9, v7, v11
+; CGP-NEXT:    v_mul_lo_u32 v10, v6, v8
+; CGP-NEXT:    v_mul_hi_u32 v13, v6, v11
+; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v12
+; CGP-NEXT:    v_addc_u32_e32 v1, vcc, v1, v12, vcc
 ; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
+; CGP-NEXT:    v_mul_lo_u32 v14, v7, v8
+; CGP-NEXT:    v_mul_hi_u32 v11, v7, v11
 ; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v13
+; CGP-NEXT:    v_mul_hi_u32 v13, v6, v8
 ; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v11, v1, v8
 ; CGP-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
-; CGP-NEXT:    v_mul_hi_u32 v10, v0, v8
-; CGP-NEXT:    v_mul_hi_u32 v8, v1, v8
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v11, v7
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v14, v11
 ; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
-; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
-; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
-; CGP-NEXT:    v_mul_lo_u32 v9, 0, v7
-; CGP-NEXT:    v_mul_lo_u32 v8, s7, v8
-; CGP-NEXT:    v_mul_lo_u32 v10, s7, v7
-; CGP-NEXT:    v_mul_hi_u32 v7, s7, v7
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v0, v10
-; CGP-NEXT:    v_subb_u32_e64 v8, s[4:5], v1, v7, vcc
-; CGP-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v7
-; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], 0, v8
-; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], s7, v0
-; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v8
-; CGP-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v7, v7, v9, s[4:5]
-; CGP-NEXT:    v_subrev_i32_e32 v9, vcc, s7, v0
-; CGP-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CGP-NEXT:    v_cmp_le_u32_e32 vcc, 0, v1
-; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, -1, vcc
-; CGP-NEXT:    v_cmp_le_u32_e32 vcc, s7, v9
-; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, -1, vcc
-; CGP-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
-; CGP-NEXT:    v_cndmask_b32_e32 v10, v10, v11, vcc
-; CGP-NEXT:    v_subrev_i32_e32 v11, vcc, s7, v9
-; CGP-NEXT:    v_subbrev_u32_e32 v12, vcc, 0, v1, vcc
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
-; CGP-NEXT:    v_cndmask_b32_e32 v9, v9, v11, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v1, v1, v12, vcc
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
-; CGP-NEXT:    v_mul_f32_e32 v7, 0x2f800000, v4
-; CGP-NEXT:    v_trunc_f32_e32 v7, v7
-; CGP-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v7
-; CGP-NEXT:    v_cvt_u32_f32_e32 v4, v4
-; CGP-NEXT:    v_cvt_u32_f32_e32 v7, v7
-; CGP-NEXT:    v_cndmask_b32_e32 v0, v0, v9, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v1, v8, v1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v8, -1, v4
-; CGP-NEXT:    v_mul_lo_u32 v9, s6, v7
-; CGP-NEXT:    v_mul_hi_u32 v11, s6, v4
-; CGP-NEXT:    v_mul_lo_u32 v10, s6, v4
-; CGP-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
-; CGP-NEXT:    v_addc_u32_e32 v3, vcc, v3, v6, vcc
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
-; CGP-NEXT:    v_mul_lo_u32 v9, v7, v10
-; CGP-NEXT:    v_mul_lo_u32 v11, v4, v8
-; CGP-NEXT:    v_mul_hi_u32 v12, v4, v10
-; CGP-NEXT:    v_mul_hi_u32 v10, v7, v10
-; CGP-NEXT:    v_xor_b32_e32 v0, v0, v5
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
-; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
-; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v12, v7, v8
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v11, v9
-; CGP-NEXT:    v_mul_hi_u32 v11, v4, v8
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v13
+; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v11, vcc, v11, v13
 ; CGP-NEXT:    v_mul_hi_u32 v8, v7, v8
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v12, v10
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
-; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
 ; CGP-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
 ; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
 ; CGP-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
 ; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v9
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
 ; CGP-NEXT:    v_addc_u32_e64 v9, s[4:5], v7, v8, vcc
-; CGP-NEXT:    v_mul_lo_u32 v10, -1, v4
+; CGP-NEXT:    v_mul_lo_u32 v10, -1, v6
 ; CGP-NEXT:    v_mul_lo_u32 v11, s6, v9
-; CGP-NEXT:    v_mul_hi_u32 v13, s6, v4
-; CGP-NEXT:    v_mul_lo_u32 v12, s6, v4
+; CGP-NEXT:    v_mul_hi_u32 v13, s6, v6
+; CGP-NEXT:    v_mul_lo_u32 v14, s6, v6
 ; CGP-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v8
 ; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v11
 ; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v13
-; CGP-NEXT:    v_mul_lo_u32 v11, v9, v12
-; CGP-NEXT:    v_mul_lo_u32 v13, v4, v10
-; CGP-NEXT:    v_mul_hi_u32 v8, v4, v12
-; CGP-NEXT:    v_mul_hi_u32 v12, v9, v12
-; CGP-NEXT:    v_xor_b32_e32 v2, v2, v6
+; CGP-NEXT:    v_mul_lo_u32 v11, v9, v14
+; CGP-NEXT:    v_mul_lo_u32 v13, v6, v10
+; CGP-NEXT:    v_mul_hi_u32 v8, v6, v14
+; CGP-NEXT:    v_mul_lo_u32 v15, v9, v10
+; CGP-NEXT:    v_mul_hi_u32 v14, v9, v14
 ; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v13
 ; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
 ; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v11, v8
+; CGP-NEXT:    v_mul_hi_u32 v11, v6, v10
 ; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
-; CGP-NEXT:    v_mul_lo_u32 v11, v9, v10
 ; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v13, v8
-; CGP-NEXT:    v_mul_hi_u32 v13, v4, v10
-; CGP-NEXT:    v_mul_hi_u32 v9, v9, v10
-; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v13
+; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v15, v14
+; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v13, v11
 ; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v13
+; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v14, v13
+; CGP-NEXT:    v_mul_hi_u32 v9, v9, v10
 ; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v11, v8
-; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v12, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v13, v10
 ; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v10
 ; CGP-NEXT:    v_addc_u32_e32 v7, vcc, v7, v9, vcc
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; CGP-NEXT:    v_xor_b32_e32 v0, v0, v12
+; CGP-NEXT:    v_xor_b32_e32 v1, v1, v12
 ; CGP-NEXT:    v_addc_u32_e32 v7, vcc, 0, v7, vcc
-; CGP-NEXT:    v_xor_b32_e32 v3, v3, v6
-; CGP-NEXT:    v_xor_b32_e32 v1, v1, v5
-; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v0, v5
-; CGP-NEXT:    v_mul_lo_u32 v8, v3, v4
-; CGP-NEXT:    v_mul_lo_u32 v9, v2, v7
-; CGP-NEXT:    v_subb_u32_e32 v1, vcc, v1, v5, vcc
-; CGP-NEXT:    v_mul_hi_u32 v5, v2, v4
-; CGP-NEXT:    v_mul_hi_u32 v4, v3, v4
+; CGP-NEXT:    v_mul_lo_u32 v8, v1, v6
+; CGP-NEXT:    v_mul_lo_u32 v9, v0, v7
+; CGP-NEXT:    v_mul_hi_u32 v10, v0, v6
+; CGP-NEXT:    v_mul_lo_u32 v11, v1, v7
+; CGP-NEXT:    v_mul_hi_u32 v6, v1, v6
 ; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
 ; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; CGP-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v8, v3, v7
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v9, v5
-; CGP-NEXT:    v_mul_hi_u32 v9, v2, v7
-; CGP-NEXT:    v_mul_hi_u32 v7, v3, v7
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v8, v4
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; CGP-NEXT:    v_mul_hi_u32 v10, v0, v7
 ; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v9
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v11, v6
 ; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
-; CGP-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v10
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
+; CGP-NEXT:    v_mul_hi_u32 v7, v1, v7
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; CGP-NEXT:    v_mul_lo_u32 v8, 0, v6
+; CGP-NEXT:    v_mul_lo_u32 v7, s7, v7
+; CGP-NEXT:    v_mul_hi_u32 v9, s7, v6
+; CGP-NEXT:    v_mul_lo_u32 v6, s7, v6
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v0, v6
+; CGP-NEXT:    v_subb_u32_e64 v6, s[4:5], v1, v7, vcc
+; CGP-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v7
+; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], 0, v6
+; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], s7, v0
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v6
+; CGP-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
+; CGP-NEXT:    v_cndmask_b32_e64 v7, v7, v8, s[4:5]
+; CGP-NEXT:    v_subrev_i32_e32 v8, vcc, s7, v0
+; CGP-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
+; CGP-NEXT:    v_cmp_le_u32_e32 vcc, 0, v1
+; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
+; CGP-NEXT:    v_cmp_le_u32_e32 vcc, s7, v8
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, -1, vcc
+; CGP-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
+; CGP-NEXT:    v_cndmask_b32_e32 v9, v9, v10, vcc
+; CGP-NEXT:    v_subrev_i32_e32 v10, vcc, s7, v8
+; CGP-NEXT:    v_subbrev_u32_e32 v11, vcc, 0, v1, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v9
+; CGP-NEXT:    v_cndmask_b32_e32 v5, v8, v10, vcc
+; CGP-NEXT:    v_mul_f32_e32 v8, 0x2f800000, v4
+; CGP-NEXT:    v_trunc_f32_e32 v8, v8
+; CGP-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v8
+; CGP-NEXT:    v_cvt_u32_f32_e32 v4, v4
+; CGP-NEXT:    v_cvt_u32_f32_e32 v8, v8
+; CGP-NEXT:    v_cndmask_b32_e32 v1, v1, v11, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
+; CGP-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v1, v6, v1, vcc
+; CGP-NEXT:    v_mul_lo_u32 v5, -1, v4
+; CGP-NEXT:    v_mul_lo_u32 v6, s6, v8
+; CGP-NEXT:    v_mul_hi_u32 v7, s6, v4
+; CGP-NEXT:    v_mul_lo_u32 v9, s6, v4
+; CGP-NEXT:    v_ashrrev_i32_e32 v10, 31, v3
+; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
+; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; CGP-NEXT:    v_mul_lo_u32 v6, v8, v9
+; CGP-NEXT:    v_mul_lo_u32 v7, v4, v5
+; CGP-NEXT:    v_mul_hi_u32 v11, v4, v9
+; CGP-NEXT:    v_add_i32_e32 v2, vcc, v2, v10
+; CGP-NEXT:    v_addc_u32_e32 v3, vcc, v3, v10, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; CGP-NEXT:    v_mul_lo_u32 v13, v8, v5
+; CGP-NEXT:    v_mul_hi_u32 v9, v8, v9
+; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v11
+; CGP-NEXT:    v_mul_hi_u32 v11, v4, v5
+; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v13, v9
+; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; CGP-NEXT:    v_mul_hi_u32 v5, v8, v5
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v9, v7
+; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; CGP-NEXT:    v_addc_u32_e64 v6, s[4:5], v8, v5, vcc
+; CGP-NEXT:    v_mul_lo_u32 v7, -1, v4
+; CGP-NEXT:    v_mul_lo_u32 v9, s6, v6
+; CGP-NEXT:    v_mul_hi_u32 v11, s6, v4
+; CGP-NEXT:    v_mul_lo_u32 v13, s6, v4
+; CGP-NEXT:    v_add_i32_e64 v5, s[4:5], v8, v5
+; CGP-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v9
+; CGP-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v11
+; CGP-NEXT:    v_mul_lo_u32 v9, v6, v13
+; CGP-NEXT:    v_mul_lo_u32 v11, v4, v7
+; CGP-NEXT:    v_mul_hi_u32 v8, v4, v13
+; CGP-NEXT:    v_mul_lo_u32 v14, v6, v7
+; CGP-NEXT:    v_mul_hi_u32 v13, v6, v13
+; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v9, v8
+; CGP-NEXT:    v_mul_hi_u32 v9, v4, v7
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v11, v8
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v14, v13
+; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v9
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v13, v11
+; CGP-NEXT:    v_mul_hi_u32 v6, v6, v7
+; CGP-NEXT:    v_add_i32_e64 v7, s[4:5], v9, v8
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v11, v8
+; CGP-NEXT:    v_add_i32_e64 v6, s[4:5], v6, v8
+; CGP-NEXT:    v_addc_u32_e32 v5, vcc, v5, v6, vcc
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; CGP-NEXT:    v_xor_b32_e32 v2, v2, v10
+; CGP-NEXT:    v_xor_b32_e32 v3, v3, v10
+; CGP-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; CGP-NEXT:    v_mul_lo_u32 v6, v3, v4
+; CGP-NEXT:    v_mul_lo_u32 v7, v2, v5
+; CGP-NEXT:    v_mul_hi_u32 v8, v2, v4
+; CGP-NEXT:    v_mul_lo_u32 v9, v3, v5
+; CGP-NEXT:    v_mul_hi_u32 v4, v3, v4
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; CGP-NEXT:    v_mul_hi_u32 v8, v2, v5
+; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v9, v4
+; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; CGP-NEXT:    v_mul_hi_u32 v5, v3, v5
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
 ; CGP-NEXT:    v_mul_lo_u32 v7, 0, v4
 ; CGP-NEXT:    v_mul_lo_u32 v5, s7, v5
-; CGP-NEXT:    v_mul_lo_u32 v8, s7, v4
+; CGP-NEXT:    v_mul_lo_u32 v6, s7, v4
 ; CGP-NEXT:    v_mul_hi_u32 v4, s7, v4
+; CGP-NEXT:    v_xor_b32_e32 v0, v0, v12
+; CGP-NEXT:    v_xor_b32_e32 v1, v1, v12
+; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v0, v12
+; CGP-NEXT:    v_subb_u32_e32 v1, vcc, v1, v12, vcc
 ; CGP-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
 ; CGP-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v2, v8
+; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v2, v6
 ; CGP-NEXT:    v_subb_u32_e64 v5, s[4:5], v3, v4, vcc
 ; CGP-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v4
 ; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], 0, v5
 ; CGP-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[4:5]
 ; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], s7, v2
-; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
+; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[4:5]
 ; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v5
 ; CGP-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v4, v4, v7, s[4:5]
-; CGP-NEXT:    v_subrev_i32_e32 v7, vcc, s7, v2
+; CGP-NEXT:    v_cndmask_b32_e64 v4, v4, v6, s[4:5]
+; CGP-NEXT:    v_subrev_i32_e32 v6, vcc, s7, v2
 ; CGP-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
 ; CGP-NEXT:    v_cmp_le_u32_e32 vcc, 0, v3
+; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
+; CGP-NEXT:    v_cmp_le_u32_e32 vcc, s7, v6
 ; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
-; CGP-NEXT:    v_cmp_le_u32_e32 vcc, s7, v7
-; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
 ; CGP-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v3
-; CGP-NEXT:    v_cndmask_b32_e32 v8, v8, v9, vcc
-; CGP-NEXT:    v_subrev_i32_e32 v9, vcc, s7, v7
-; CGP-NEXT:    v_subbrev_u32_e32 v10, vcc, 0, v3, vcc
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v8
-; CGP-NEXT:    v_cndmask_b32_e32 v7, v7, v9, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v3, v3, v10, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v7, v7, v8, vcc
+; CGP-NEXT:    v_subrev_i32_e32 v8, vcc, s7, v6
+; CGP-NEXT:    v_subbrev_u32_e32 v9, vcc, 0, v3, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
+; CGP-NEXT:    v_cndmask_b32_e32 v6, v6, v8, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v3, v3, v9, vcc
 ; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
-; CGP-NEXT:    v_cndmask_b32_e32 v2, v2, v7, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc
 ; CGP-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc
-; CGP-NEXT:    v_xor_b32_e32 v2, v2, v6
-; CGP-NEXT:    v_xor_b32_e32 v3, v3, v6
-; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v2, v6
-; CGP-NEXT:    v_subb_u32_e32 v3, vcc, v3, v6, vcc
+; CGP-NEXT:    v_xor_b32_e32 v2, v2, v10
+; CGP-NEXT:    v_xor_b32_e32 v3, v3, v10
+; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v2, v10
+; CGP-NEXT:    v_subb_u32_e32 v3, vcc, v3, v10, vcc
 ; CGP-NEXT:    s_setpc_b64 s[30:31]
   %result = srem <2 x i64> %num, <i64 4096, i64 4096>
   ret <2 x i64> %result
@@ -1753,139 +1753,139 @@
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:    v_cvt_f32_u32_e32 v2, 0x12d8fb
-; CHECK-NEXT:    v_cvt_f32_ubyte0_e32 v4, 0
+; CHECK-NEXT:    v_cvt_f32_ubyte0_e32 v3, 0
 ; CHECK-NEXT:    s_mov_b32 s6, 0xffed2705
-; CHECK-NEXT:    v_ashrrev_i32_e32 v3, 31, v1
-; CHECK-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v4
+; CHECK-NEXT:    v_ashrrev_i32_e32 v8, 31, v1
+; CHECK-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
 ; CHECK-NEXT:    v_rcp_iflag_f32_e32 v2, v2
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
-; CHECK-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
-; CHECK-NEXT:    v_xor_b32_e32 v0, v0, v3
 ; CHECK-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
-; CHECK-NEXT:    v_mul_f32_e32 v4, 0x2f800000, v2
-; CHECK-NEXT:    v_trunc_f32_e32 v4, v4
-; CHECK-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v4
+; CHECK-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
+; CHECK-NEXT:    v_trunc_f32_e32 v3, v3
+; CHECK-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
 ; CHECK-NEXT:    v_cvt_u32_f32_e32 v2, v2
-; CHECK-NEXT:    v_cvt_u32_f32_e32 v4, v4
-; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v3
+; CHECK-NEXT:    v_cvt_u32_f32_e32 v3, v3
 ; CHECK-NEXT:    v_mul_lo_u32 v5, -1, v2
-; CHECK-NEXT:    v_mul_lo_u32 v6, s6, v4
-; CHECK-NEXT:    v_mul_hi_u32 v8, s6, v2
-; CHECK-NEXT:    v_mul_lo_u32 v7, s6, v2
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
-; CHECK-NEXT:    v_mul_lo_u32 v6, v4, v7
-; CHECK-NEXT:    v_mul_lo_u32 v8, v2, v5
-; CHECK-NEXT:    v_mul_hi_u32 v9, v2, v7
-; CHECK-NEXT:    v_mul_hi_u32 v7, v4, v7
-; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
-; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CHECK-NEXT:    v_mul_lo_u32 v4, s6, v3
+; CHECK-NEXT:    v_mul_hi_u32 v7, s6, v2
+; CHECK-NEXT:    v_mul_lo_u32 v6, s6, v2
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; CHECK-NEXT:    v_mul_lo_u32 v5, v3, v6
+; CHECK-NEXT:    v_mul_lo_u32 v7, v2, v4
+; CHECK-NEXT:    v_mul_hi_u32 v9, v2, v6
+; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v8
+; CHECK-NEXT:    v_addc_u32_e32 v1, vcc, v1, v8, vcc
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; CHECK-NEXT:    v_mul_lo_u32 v10, v3, v4
+; CHECK-NEXT:    v_mul_hi_u32 v6, v3, v6
+; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v9
+; CHECK-NEXT:    v_mul_hi_u32 v9, v2, v4
+; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
+; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v10, v6
+; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
-; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v9, v4, v5
-; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
-; CHECK-NEXT:    v_mul_hi_u32 v8, v2, v5
-; CHECK-NEXT:    v_mul_hi_u32 v5, v4, v5
-; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v9, v7
 ; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; CHECK-NEXT:    v_mul_hi_u32 v4, v3, v4
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
+; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
-; CHECK-NEXT:    v_addc_u32_e64 v6, s[4:5], v4, v5, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v7, -1, v2
-; CHECK-NEXT:    v_mul_lo_u32 v8, s6, v6
-; CHECK-NEXT:    v_mul_hi_u32 v10, s6, v2
-; CHECK-NEXT:    v_mul_lo_u32 v9, s6, v2
-; CHECK-NEXT:    v_add_i32_e64 v4, s[4:5], v4, v5
-; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v8
-; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v10
-; CHECK-NEXT:    v_mul_lo_u32 v8, v6, v9
-; CHECK-NEXT:    v_mul_lo_u32 v10, v2, v7
-; CHECK-NEXT:    v_mul_hi_u32 v5, v2, v9
-; CHECK-NEXT:    v_mul_hi_u32 v9, v6, v9
-; CHECK-NEXT:    s_mov_b32 s6, 0x12d8fb
-; CHECK-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v10
-; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v5, s[4:5], v8, v5
-; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, s[4:5]
-; CHECK-NEXT:    v_mul_lo_u32 v8, v6, v7
-; CHECK-NEXT:    v_add_i32_e64 v5, s[4:5], v10, v5
-; CHECK-NEXT:    v_mul_hi_u32 v10, v2, v7
-; CHECK-NEXT:    v_mul_hi_u32 v6, v6, v7
-; CHECK-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; CHECK-NEXT:    v_addc_u32_e64 v5, s[4:5], v3, v4, vcc
+; CHECK-NEXT:    v_mul_lo_u32 v6, -1, v2
+; CHECK-NEXT:    v_mul_lo_u32 v7, s6, v5
+; CHECK-NEXT:    v_mul_hi_u32 v9, s6, v2
+; CHECK-NEXT:    v_mul_lo_u32 v10, s6, v2
+; CHECK-NEXT:    v_add_i32_e64 v3, s[4:5], v3, v4
+; CHECK-NEXT:    v_add_i32_e64 v6, s[4:5], v6, v7
+; CHECK-NEXT:    v_add_i32_e64 v6, s[4:5], v6, v9
+; CHECK-NEXT:    v_mul_lo_u32 v7, v5, v10
+; CHECK-NEXT:    v_mul_lo_u32 v9, v2, v6
+; CHECK-NEXT:    v_mul_hi_u32 v4, v2, v10
+; CHECK-NEXT:    v_mul_lo_u32 v11, v5, v6
+; CHECK-NEXT:    v_mul_hi_u32 v10, v5, v10
+; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v9
 ; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v10
+; CHECK-NEXT:    v_add_i32_e64 v4, s[4:5], v7, v4
+; CHECK-NEXT:    v_mul_hi_u32 v7, v2, v6
+; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v4, s[4:5], v9, v4
+; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v10
 ; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v10
-; CHECK-NEXT:    v_add_i32_e64 v5, s[4:5], v8, v5
-; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v9, v8
-; CHECK-NEXT:    v_add_i32_e64 v6, s[4:5], v6, v7
-; CHECK-NEXT:    v_addc_u32_e32 v4, vcc, v4, v6, vcc
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
-; CHECK-NEXT:    v_addc_u32_e32 v4, vcc, 0, v4, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v5, v1, v2
-; CHECK-NEXT:    v_mul_lo_u32 v6, v0, v4
-; CHECK-NEXT:    v_mul_hi_u32 v7, v0, v2
+; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v9, v7
+; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v10, v9
+; CHECK-NEXT:    v_mul_hi_u32 v5, v5, v6
+; CHECK-NEXT:    v_add_i32_e64 v4, s[4:5], v7, v4
+; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v6, s[4:5], v9, v6
+; CHECK-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v6
+; CHECK-NEXT:    v_addc_u32_e32 v3, vcc, v3, v5, vcc
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
+; CHECK-NEXT:    v_xor_b32_e32 v0, v0, v8
+; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v8
+; CHECK-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; CHECK-NEXT:    v_mul_lo_u32 v4, v1, v2
+; CHECK-NEXT:    v_mul_lo_u32 v5, v0, v3
+; CHECK-NEXT:    v_mul_hi_u32 v6, v0, v2
+; CHECK-NEXT:    v_mul_lo_u32 v7, v1, v3
 ; CHECK-NEXT:    v_mul_hi_u32 v2, v1, v2
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
-; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
 ; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v7, v1, v4
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; CHECK-NEXT:    v_mul_hi_u32 v6, v0, v4
-; CHECK-NEXT:    v_mul_hi_u32 v4, v1, v4
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; CHECK-NEXT:    v_mul_hi_u32 v6, v0, v3
+; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v7, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
 ; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
-; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
-; CHECK-NEXT:    v_mul_lo_u32 v5, 0, v2
-; CHECK-NEXT:    v_mul_lo_u32 v4, s6, v4
-; CHECK-NEXT:    v_mul_lo_u32 v6, s6, v2
-; CHECK-NEXT:    v_mul_hi_u32 v2, s6, v2
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
+; CHECK-NEXT:    v_mul_hi_u32 v3, v1, v3
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
+; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
-; CHECK-NEXT:    v_sub_i32_e32 v0, vcc, v0, v6
-; CHECK-NEXT:    v_subb_u32_e64 v4, s[4:5], v1, v2, vcc
-; CHECK-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v2
-; CHECK-NEXT:    v_cmp_le_u32_e64 s[4:5], 0, v4
-; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, -1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v3, v4
+; CHECK-NEXT:    s_mov_b32 s6, 0x12d8fb
+; CHECK-NEXT:    v_mul_lo_u32 v4, 0, v2
+; CHECK-NEXT:    v_mul_lo_u32 v3, s6, v3
+; CHECK-NEXT:    v_mul_hi_u32 v5, s6, v2
+; CHECK-NEXT:    v_mul_lo_u32 v2, s6, v2
+; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
+; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
+; CHECK-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
+; CHECK-NEXT:    v_subb_u32_e64 v2, s[4:5], v1, v3, vcc
+; CHECK-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v3
+; CHECK-NEXT:    v_cmp_le_u32_e64 s[4:5], 0, v2
+; CHECK-NEXT:    v_cndmask_b32_e64 v3, 0, -1, s[4:5]
 ; CHECK-NEXT:    v_cmp_le_u32_e64 s[4:5], s6, v0
-; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[4:5]
-; CHECK-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v4
+; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[4:5]
+; CHECK-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v2
 ; CHECK-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CHECK-NEXT:    v_cndmask_b32_e64 v2, v2, v5, s[4:5]
-; CHECK-NEXT:    v_subrev_i32_e32 v5, vcc, s6, v0
+; CHECK-NEXT:    v_cndmask_b32_e64 v3, v3, v4, s[4:5]
+; CHECK-NEXT:    v_subrev_i32_e32 v4, vcc, s6, v0
 ; CHECK-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
 ; CHECK-NEXT:    v_cmp_le_u32_e32 vcc, 0, v1
+; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
+; CHECK-NEXT:    v_cmp_le_u32_e32 vcc, s6, v4
 ; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
-; CHECK-NEXT:    v_cmp_le_u32_e32 vcc, s6, v5
-; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
 ; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
-; CHECK-NEXT:    v_cndmask_b32_e32 v6, v6, v7, vcc
-; CHECK-NEXT:    v_subrev_i32_e32 v7, vcc, s6, v5
-; CHECK-NEXT:    v_subbrev_u32_e32 v8, vcc, 0, v1, vcc
-; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
-; CHECK-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc
-; CHECK-NEXT:    v_cndmask_b32_e32 v1, v1, v8, vcc
-; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
-; CHECK-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
-; CHECK-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc
-; CHECK-NEXT:    v_xor_b32_e32 v0, v0, v3
-; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v3
-; CHECK-NEXT:    v_sub_i32_e32 v0, vcc, v0, v3
-; CHECK-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
+; CHECK-NEXT:    v_subrev_i32_e32 v6, vcc, s6, v4
+; CHECK-NEXT:    v_subbrev_u32_e32 v7, vcc, 0, v1, vcc
+; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
+; CHECK-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v1, v1, v7, vcc
+; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v3
+; CHECK-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
+; CHECK-NEXT:    v_xor_b32_e32 v0, v0, v8
+; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v8
+; CHECK-NEXT:    v_sub_i32_e32 v0, vcc, v0, v8
+; CHECK-NEXT:    v_subb_u32_e32 v1, vcc, v1, v8, vcc
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %result = srem i64 %num, 1235195
   ret i64 %result
@@ -1913,551 +1913,551 @@
 ; GISEL-NEXT:    v_rcp_iflag_f32_e32 v4, v4
 ; GISEL-NEXT:    s_cmp_lg_u32 s4, 0
 ; GISEL-NEXT:    s_subb_u32 s12, 0, s9
-; GISEL-NEXT:    v_ashrrev_i32_e32 v6, 31, v1
+; GISEL-NEXT:    v_ashrrev_i32_e32 v10, 31, v1
 ; GISEL-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
 ; GISEL-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
 ; GISEL-NEXT:    v_trunc_f32_e32 v5, v5
 ; GISEL-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v4, v4
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v5, v5
-; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v6
-; GISEL-NEXT:    v_addc_u32_e32 v1, vcc, v1, v6, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v7, s12, v4
-; GISEL-NEXT:    v_mul_lo_u32 v8, s11, v5
-; GISEL-NEXT:    v_mul_hi_u32 v10, s11, v4
+; GISEL-NEXT:    v_mul_lo_u32 v6, s12, v4
+; GISEL-NEXT:    v_mul_lo_u32 v7, s11, v5
+; GISEL-NEXT:    v_mul_hi_u32 v8, s11, v4
 ; GISEL-NEXT:    v_mul_lo_u32 v9, s11, v4
-; GISEL-NEXT:    v_xor_b32_e32 v0, v0, v6
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
-; GISEL-NEXT:    v_mul_lo_u32 v8, v5, v9
-; GISEL-NEXT:    v_mul_lo_u32 v10, v4, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; GISEL-NEXT:    v_mul_lo_u32 v7, v5, v9
+; GISEL-NEXT:    v_mul_lo_u32 v8, v4, v6
 ; GISEL-NEXT:    v_mul_hi_u32 v11, v4, v9
+; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v10
+; GISEL-NEXT:    v_addc_u32_e32 v1, vcc, v1, v10, vcc
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; GISEL-NEXT:    v_mul_lo_u32 v12, v5, v6
 ; GISEL-NEXT:    v_mul_hi_u32 v9, v5, v9
-; GISEL-NEXT:    v_xor_b32_e32 v1, v1, v6
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v11, v5, v7
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
-; GISEL-NEXT:    v_mul_hi_u32 v10, v4, v7
-; GISEL-NEXT:    v_mul_hi_u32 v7, v5, v7
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v11, v9
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v11
+; GISEL-NEXT:    v_mul_hi_u32 v11, v4, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v12, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
 ; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; GISEL-NEXT:    v_mul_hi_u32 v6, v5, v6
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
-; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
-; GISEL-NEXT:    v_addc_u32_e64 v8, s[4:5], v5, v7, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v9, s12, v4
-; GISEL-NEXT:    v_mul_lo_u32 v10, s11, v8
-; GISEL-NEXT:    v_mul_hi_u32 v12, s11, v4
-; GISEL-NEXT:    v_mul_lo_u32 v11, s11, v4
-; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v7
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v10
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v12
-; GISEL-NEXT:    v_mul_lo_u32 v10, v8, v11
-; GISEL-NEXT:    v_mul_lo_u32 v12, v4, v9
-; GISEL-NEXT:    v_mul_hi_u32 v7, v4, v11
-; GISEL-NEXT:    v_mul_hi_u32 v11, v8, v11
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v12
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v10, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, s[4:5]
-; GISEL-NEXT:    v_mul_lo_u32 v10, v8, v9
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v12, v7
-; GISEL-NEXT:    v_mul_hi_u32 v12, v4, v9
-; GISEL-NEXT:    v_mul_hi_u32 v8, v8, v9
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v11
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; GISEL-NEXT:    v_addc_u32_e64 v7, s[4:5], v5, v6, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v8, s12, v4
+; GISEL-NEXT:    v_mul_lo_u32 v9, s11, v7
+; GISEL-NEXT:    v_mul_hi_u32 v11, s11, v4
+; GISEL-NEXT:    v_mul_lo_u32 v12, s11, v4
+; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v6
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v11
+; GISEL-NEXT:    v_mul_lo_u32 v9, v7, v12
+; GISEL-NEXT:    v_mul_lo_u32 v11, v4, v8
+; GISEL-NEXT:    v_mul_hi_u32 v6, v4, v12
+; GISEL-NEXT:    v_mul_lo_u32 v13, v7, v8
+; GISEL-NEXT:    v_mul_hi_u32 v12, v7, v12
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v11
 ; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v12
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v9, v6
+; GISEL-NEXT:    v_mul_hi_u32 v9, v4, v8
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v11, v6
+; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v13, v12
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v10, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v10
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
-; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v8, vcc
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v12, v11
+; GISEL-NEXT:    v_mul_hi_u32 v7, v7, v8
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v9, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v11, v8
+; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v8
+; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v7, vcc
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; GISEL-NEXT:    v_xor_b32_e32 v0, v0, v10
+; GISEL-NEXT:    v_xor_b32_e32 v1, v1, v10
 ; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v7, v1, v4
-; GISEL-NEXT:    v_mul_lo_u32 v8, v0, v5
-; GISEL-NEXT:    v_mul_hi_u32 v10, v0, v4
+; GISEL-NEXT:    v_mul_lo_u32 v6, v1, v4
+; GISEL-NEXT:    v_mul_lo_u32 v7, v0, v5
+; GISEL-NEXT:    v_mul_hi_u32 v8, v0, v4
+; GISEL-NEXT:    v_mul_lo_u32 v9, v1, v5
 ; GISEL-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GISEL-NEXT:    v_mov_b32_e32 v9, s9
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
 ; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v10, v1, v5
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
 ; GISEL-NEXT:    v_mul_hi_u32 v8, v0, v5
-; GISEL-NEXT:    v_mul_hi_u32 v5, v1, v5
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v10, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v9, v4
+; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; GISEL-NEXT:    v_mul_lo_u32 v7, s9, v4
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; GISEL-NEXT:    v_mul_hi_u32 v5, v1, v5
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
+; GISEL-NEXT:    v_mul_lo_u32 v6, s9, v4
 ; GISEL-NEXT:    v_mul_lo_u32 v5, s8, v5
-; GISEL-NEXT:    v_mul_lo_u32 v8, s8, v4
-; GISEL-NEXT:    v_mul_hi_u32 v4, s8, v4
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v8
-; GISEL-NEXT:    v_subb_u32_e64 v5, s[4:5], v1, v4, vcc
-; GISEL-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v4
-; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s9, v5
-; GISEL-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[4:5]
+; GISEL-NEXT:    v_mul_hi_u32 v7, s8, v4
+; GISEL-NEXT:    v_mul_lo_u32 v4, s8, v4
+; GISEL-NEXT:    v_mov_b32_e32 v8, s9
+; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
+; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
+; GISEL-NEXT:    v_subb_u32_e64 v4, s[4:5], v1, v5, vcc
+; GISEL-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v5
+; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s9, v4
+; GISEL-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[4:5]
 ; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s8, v0
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], s9, v5
-; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v9, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v4, v4, v7, s[4:5]
-; GISEL-NEXT:    v_subrev_i32_e32 v7, vcc, s8, v0
-; GISEL-NEXT:    v_subbrev_u32_e64 v8, s[4:5], 0, v1, vcc
-; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s9, v8
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s8, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], s9, v4
+; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v8, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v5, v5, v6, s[4:5]
+; GISEL-NEXT:    v_subrev_i32_e32 v6, vcc, s8, v0
+; GISEL-NEXT:    v_subbrev_u32_e64 v7, s[4:5], 0, v1, vcc
+; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s9, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s8, v6
 ; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], s9, v8
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, v10, v11, s[4:5]
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], s9, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, v9, v11, s[4:5]
 ; GISEL-NEXT:    s_add_u32 s4, s10, 0
-; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v9, vcc
 ; GISEL-NEXT:    s_cselect_b32 s5, 1, 0
-; GISEL-NEXT:    v_subrev_i32_e32 v9, vcc, s8, v7
+; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v8, vcc
 ; GISEL-NEXT:    s_and_b32 s5, s5, 1
 ; GISEL-NEXT:    s_cmp_lg_u32 s5, 0
+; GISEL-NEXT:    v_subrev_i32_e32 v8, vcc, s8, v6
 ; GISEL-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
 ; GISEL-NEXT:    s_addc_u32 s5, 0, 0
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v9
 ; GISEL-NEXT:    s_xor_b64 s[6:7], s[4:5], s[6:7]
-; GISEL-NEXT:    v_cndmask_b32_e32 v7, v7, v9, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v1, v8, v1, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
-; GISEL-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc
-; GISEL-NEXT:    v_cvt_f32_u32_e32 v4, s6
-; GISEL-NEXT:    v_cvt_f32_u32_e32 v5, s7
+; GISEL-NEXT:    v_cndmask_b32_e32 v6, v6, v8, vcc
+; GISEL-NEXT:    v_cvt_f32_u32_e32 v8, s6
+; GISEL-NEXT:    v_cvt_f32_u32_e32 v9, s7
+; GISEL-NEXT:    v_cndmask_b32_e32 v1, v7, v1, vcc
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
+; GISEL-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc
+; GISEL-NEXT:    v_mac_f32_e32 v8, 0x4f800000, v9
+; GISEL-NEXT:    v_rcp_iflag_f32_e32 v5, v8
 ; GISEL-NEXT:    s_sub_u32 s8, 0, s6
 ; GISEL-NEXT:    s_cselect_b32 s4, 1, 0
 ; GISEL-NEXT:    s_and_b32 s4, s4, 1
-; GISEL-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
-; GISEL-NEXT:    v_rcp_iflag_f32_e32 v4, v4
-; GISEL-NEXT:    s_cmp_lg_u32 s4, 0
-; GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v7, vcc
-; GISEL-NEXT:    s_subb_u32 s9, 0, s7
-; GISEL-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
+; GISEL-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v5
 ; GISEL-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
 ; GISEL-NEXT:    v_trunc_f32_e32 v5, v5
 ; GISEL-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v4, v4
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v5, v5
-; GISEL-NEXT:    v_xor_b32_e32 v0, v0, v6
-; GISEL-NEXT:    v_xor_b32_e32 v1, v1, v6
-; GISEL-NEXT:    v_mul_lo_u32 v7, s9, v4
-; GISEL-NEXT:    v_mul_lo_u32 v8, s8, v5
-; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v6
-; GISEL-NEXT:    v_mul_hi_u32 v10, s8, v4
-; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v6, vcc
-; GISEL-NEXT:    v_ashrrev_i32_e32 v6, 31, v3
+; GISEL-NEXT:    s_cmp_lg_u32 s4, 0
+; GISEL-NEXT:    s_subb_u32 s9, 0, s7
+; GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v6, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v6, s9, v4
+; GISEL-NEXT:    v_mul_lo_u32 v7, s8, v5
+; GISEL-NEXT:    v_mul_hi_u32 v8, s8, v4
 ; GISEL-NEXT:    v_mul_lo_u32 v9, s8, v4
-; GISEL-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
-; GISEL-NEXT:    v_addc_u32_e32 v3, vcc, v3, v6, vcc
+; GISEL-NEXT:    v_ashrrev_i32_e32 v11, 31, v3
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; GISEL-NEXT:    v_mul_lo_u32 v7, v5, v9
+; GISEL-NEXT:    v_mul_lo_u32 v8, v4, v6
+; GISEL-NEXT:    v_mul_hi_u32 v12, v4, v9
+; GISEL-NEXT:    v_add_i32_e32 v2, vcc, v2, v11
+; GISEL-NEXT:    v_addc_u32_e32 v3, vcc, v3, v11, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
-; GISEL-NEXT:    v_mul_lo_u32 v8, v5, v9
-; GISEL-NEXT:    v_mul_lo_u32 v10, v4, v7
-; GISEL-NEXT:    v_mul_hi_u32 v11, v4, v9
+; GISEL-NEXT:    v_mul_lo_u32 v13, v5, v6
 ; GISEL-NEXT:    v_mul_hi_u32 v9, v5, v9
-; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v6
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v11, v5, v7
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
-; GISEL-NEXT:    v_mul_hi_u32 v10, v4, v7
-; GISEL-NEXT:    v_mul_hi_u32 v7, v5, v7
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v11, v9
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v12
+; GISEL-NEXT:    v_mul_hi_u32 v12, v4, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v13, v9
 ; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
-; GISEL-NEXT:    v_addc_u32_e64 v8, s[4:5], v5, v7, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v9, s9, v4
-; GISEL-NEXT:    v_mul_lo_u32 v10, s8, v8
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v12
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
+; GISEL-NEXT:    v_mul_hi_u32 v6, v5, v6
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; GISEL-NEXT:    v_addc_u32_e64 v7, s[4:5], v5, v6, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v8, s9, v4
+; GISEL-NEXT:    v_mul_lo_u32 v9, s8, v7
 ; GISEL-NEXT:    v_mul_hi_u32 v12, s8, v4
-; GISEL-NEXT:    v_mul_lo_u32 v11, s8, v4
-; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v7
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v10
+; GISEL-NEXT:    v_mul_lo_u32 v13, s8, v4
+; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v6
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v12
+; GISEL-NEXT:    v_mul_lo_u32 v9, v7, v13
+; GISEL-NEXT:    v_mul_lo_u32 v12, v4, v8
+; GISEL-NEXT:    v_mul_hi_u32 v6, v4, v13
+; GISEL-NEXT:    v_mul_lo_u32 v14, v7, v8
+; GISEL-NEXT:    v_mul_hi_u32 v13, v7, v13
 ; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v12
-; GISEL-NEXT:    v_mul_lo_u32 v10, v8, v11
-; GISEL-NEXT:    v_mul_lo_u32 v12, v4, v9
-; GISEL-NEXT:    v_mul_hi_u32 v7, v4, v11
-; GISEL-NEXT:    v_mul_hi_u32 v11, v8, v11
-; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v6
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v12
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v10, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, s[4:5]
-; GISEL-NEXT:    v_mul_lo_u32 v10, v8, v9
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v12, v7
-; GISEL-NEXT:    v_mul_hi_u32 v12, v4, v9
-; GISEL-NEXT:    v_mul_hi_u32 v8, v8, v9
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v11
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v12
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v9, v6
+; GISEL-NEXT:    v_mul_hi_u32 v9, v4, v8
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v12, v6
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v14, v13
+; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v12, v9
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v10, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v10
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
-; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v8, vcc
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v13, v12
+; GISEL-NEXT:    v_mul_hi_u32 v7, v7, v8
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v9, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v12, v8
+; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v8
+; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v7, vcc
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v11
+; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v11
 ; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v7, v3, v4
-; GISEL-NEXT:    v_mul_lo_u32 v8, v2, v5
-; GISEL-NEXT:    v_mul_hi_u32 v10, v2, v4
+; GISEL-NEXT:    v_mul_lo_u32 v6, v3, v4
+; GISEL-NEXT:    v_mul_lo_u32 v7, v2, v5
+; GISEL-NEXT:    v_xor_b32_e32 v0, v0, v10
+; GISEL-NEXT:    v_mul_hi_u32 v8, v2, v4
+; GISEL-NEXT:    v_xor_b32_e32 v1, v1, v10
+; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v10
+; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v10, vcc
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; GISEL-NEXT:    v_mul_lo_u32 v9, v3, v5
 ; GISEL-NEXT:    v_mul_hi_u32 v4, v3, v4
-; GISEL-NEXT:    v_mov_b32_e32 v9, s7
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
 ; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v10, v3, v5
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
 ; GISEL-NEXT:    v_mul_hi_u32 v8, v2, v5
-; GISEL-NEXT:    v_mul_hi_u32 v5, v3, v5
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v10, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v9, v4
+; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; GISEL-NEXT:    v_mul_lo_u32 v7, s7, v4
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; GISEL-NEXT:    v_mul_hi_u32 v5, v3, v5
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
+; GISEL-NEXT:    v_mul_lo_u32 v6, s7, v4
 ; GISEL-NEXT:    v_mul_lo_u32 v5, s6, v5
-; GISEL-NEXT:    v_mul_lo_u32 v8, s6, v4
-; GISEL-NEXT:    v_mul_hi_u32 v4, s6, v4
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v8
-; GISEL-NEXT:    v_subb_u32_e64 v5, s[4:5], v3, v4, vcc
-; GISEL-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v4
-; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s7, v5
-; GISEL-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[4:5]
+; GISEL-NEXT:    v_mul_hi_u32 v7, s6, v4
+; GISEL-NEXT:    v_mul_lo_u32 v4, s6, v4
+; GISEL-NEXT:    v_mov_b32_e32 v8, s7
+; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
+; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v4
+; GISEL-NEXT:    v_subb_u32_e64 v4, s[4:5], v3, v5, vcc
+; GISEL-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v5
+; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s7, v4
+; GISEL-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[4:5]
 ; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s6, v2
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], s7, v5
-; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v9, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v4, v4, v7, s[4:5]
-; GISEL-NEXT:    v_subrev_i32_e32 v7, vcc, s6, v2
-; GISEL-NEXT:    v_subbrev_u32_e64 v8, s[4:5], 0, v3, vcc
-; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s7, v8
-; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v9, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], s7, v4
+; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v8, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v5, v5, v6, s[4:5]
+; GISEL-NEXT:    v_subrev_i32_e32 v6, vcc, s6, v2
+; GISEL-NEXT:    v_subbrev_u32_e64 v7, s[4:5], 0, v3, vcc
+; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s7, v7
+; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v8, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s6, v6
+; GISEL-NEXT:    v_subrev_i32_e32 v8, vcc, s6, v6
 ; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s6, v7
-; GISEL-NEXT:    v_subrev_i32_e32 v9, vcc, s6, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], s7, v8
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, v10, v11, s[4:5]
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], s7, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, v9, v10, s[4:5]
 ; GISEL-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
-; GISEL-NEXT:    v_cndmask_b32_e32 v7, v7, v9, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v3, v8, v3, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
-; GISEL-NEXT:    v_cndmask_b32_e32 v2, v2, v7, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc
-; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v6
-; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v6
-; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v6
-; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v6, vcc
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v9
+; GISEL-NEXT:    v_cndmask_b32_e32 v6, v6, v8, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v3, v7, v3, vcc
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
+; GISEL-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
+; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v11
+; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v11
+; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v11
+; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v11, vcc
 ; GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; CGP-LABEL: v_srem_v2i64_oddk_denom:
 ; CGP:       ; %bb.0:
 ; CGP-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CGP-NEXT:    v_cvt_f32_u32_e32 v4, 0x12d8fb
-; CGP-NEXT:    v_cvt_f32_ubyte0_e32 v6, 0
+; CGP-NEXT:    v_cvt_f32_ubyte0_e32 v5, 0
 ; CGP-NEXT:    s_mov_b32 s6, 0xffed2705
-; CGP-NEXT:    v_ashrrev_i32_e32 v5, 31, v1
-; CGP-NEXT:    v_mov_b32_e32 v7, v4
-; CGP-NEXT:    v_mac_f32_e32 v7, 0x4f800000, v6
-; CGP-NEXT:    v_rcp_iflag_f32_e32 v7, v7
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v5
-; CGP-NEXT:    v_addc_u32_e32 v1, vcc, v1, v5, vcc
-; CGP-NEXT:    v_xor_b32_e32 v0, v0, v5
-; CGP-NEXT:    v_mul_f32_e32 v7, 0x5f7ffffc, v7
-; CGP-NEXT:    v_mul_f32_e32 v8, 0x2f800000, v7
-; CGP-NEXT:    v_trunc_f32_e32 v8, v8
-; CGP-NEXT:    v_mac_f32_e32 v7, 0xcf800000, v8
-; CGP-NEXT:    v_cvt_u32_f32_e32 v7, v7
-; CGP-NEXT:    v_cvt_u32_f32_e32 v8, v8
-; CGP-NEXT:    v_xor_b32_e32 v1, v1, v5
+; CGP-NEXT:    v_ashrrev_i32_e32 v12, 31, v1
+; CGP-NEXT:    v_mov_b32_e32 v6, v4
+; CGP-NEXT:    v_mac_f32_e32 v6, 0x4f800000, v5
+; CGP-NEXT:    v_rcp_iflag_f32_e32 v6, v6
 ; CGP-NEXT:    s_mov_b32 s7, 0x12d8fb
-; CGP-NEXT:    v_mul_lo_u32 v9, -1, v7
-; CGP-NEXT:    v_mul_lo_u32 v10, s6, v8
-; CGP-NEXT:    v_mul_hi_u32 v12, s6, v7
-; CGP-NEXT:    v_mul_lo_u32 v11, s6, v7
-; CGP-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v6
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
-; CGP-NEXT:    v_mul_lo_u32 v10, v8, v11
-; CGP-NEXT:    v_mul_lo_u32 v12, v7, v9
-; CGP-NEXT:    v_mul_hi_u32 v13, v7, v11
-; CGP-NEXT:    v_mul_hi_u32 v11, v8, v11
+; CGP-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
 ; CGP-NEXT:    v_rcp_iflag_f32_e32 v4, v4
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v13
-; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v13, v8, v9
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v12, v10
-; CGP-NEXT:    v_mul_hi_u32 v12, v7, v9
-; CGP-NEXT:    v_mul_hi_u32 v9, v8, v9
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v13, v11
-; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
-; CGP-NEXT:    v_addc_u32_e64 v10, s[4:5], v8, v9, vcc
-; CGP-NEXT:    v_mul_lo_u32 v11, -1, v7
-; CGP-NEXT:    v_mul_lo_u32 v12, s6, v10
-; CGP-NEXT:    v_mul_hi_u32 v14, s6, v7
-; CGP-NEXT:    v_mul_lo_u32 v13, s6, v7
-; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
-; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
-; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v14
-; CGP-NEXT:    v_mul_lo_u32 v12, v10, v13
-; CGP-NEXT:    v_mul_lo_u32 v14, v7, v11
-; CGP-NEXT:    v_mul_hi_u32 v9, v7, v13
-; CGP-NEXT:    v_mul_hi_u32 v13, v10, v13
+; CGP-NEXT:    v_mul_f32_e32 v6, 0x5f7ffffc, v6
+; CGP-NEXT:    v_mul_f32_e32 v7, 0x2f800000, v6
+; CGP-NEXT:    v_trunc_f32_e32 v7, v7
+; CGP-NEXT:    v_mac_f32_e32 v6, 0xcf800000, v7
+; CGP-NEXT:    v_cvt_u32_f32_e32 v6, v6
+; CGP-NEXT:    v_cvt_u32_f32_e32 v7, v7
 ; CGP-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v14
-; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v12, v9
-; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
-; CGP-NEXT:    v_mul_lo_u32 v12, v10, v11
-; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v14, v9
-; CGP-NEXT:    v_mul_hi_u32 v14, v7, v11
-; CGP-NEXT:    v_mul_hi_u32 v10, v10, v11
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v13
-; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v14
-; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v14
-; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v12, v9
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v13, v12
-; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v11
-; CGP-NEXT:    v_addc_u32_e32 v8, vcc, v8, v10, vcc
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
-; CGP-NEXT:    v_addc_u32_e32 v8, vcc, 0, v8, vcc
-; CGP-NEXT:    v_mul_lo_u32 v9, v1, v7
-; CGP-NEXT:    v_mul_lo_u32 v10, v0, v8
-; CGP-NEXT:    v_mul_hi_u32 v11, v0, v7
-; CGP-NEXT:    v_mul_hi_u32 v7, v1, v7
-; CGP-NEXT:    v_ashrrev_i32_e32 v6, 31, v3
+; CGP-NEXT:    v_mul_lo_u32 v9, -1, v6
+; CGP-NEXT:    v_mul_lo_u32 v8, s6, v7
+; CGP-NEXT:    v_mul_hi_u32 v10, s6, v6
+; CGP-NEXT:    v_mul_lo_u32 v11, s6, v6
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; CGP-NEXT:    v_mul_lo_u32 v9, v7, v11
+; CGP-NEXT:    v_mul_lo_u32 v10, v6, v8
+; CGP-NEXT:    v_mul_hi_u32 v13, v6, v11
+; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v12
+; CGP-NEXT:    v_addc_u32_e32 v1, vcc, v1, v12, vcc
 ; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
+; CGP-NEXT:    v_mul_lo_u32 v14, v7, v8
+; CGP-NEXT:    v_mul_hi_u32 v11, v7, v11
 ; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
-; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v11, v1, v8
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
-; CGP-NEXT:    v_mul_hi_u32 v10, v0, v8
-; CGP-NEXT:    v_mul_hi_u32 v8, v1, v8
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v11, v7
-; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
-; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v13
+; CGP-NEXT:    v_mul_hi_u32 v13, v6, v8
 ; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
 ; CGP-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
-; CGP-NEXT:    v_mul_lo_u32 v9, 0, v7
-; CGP-NEXT:    v_mul_lo_u32 v8, s7, v8
-; CGP-NEXT:    v_mul_lo_u32 v10, s7, v7
-; CGP-NEXT:    v_mul_hi_u32 v7, s7, v7
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v0, v10
-; CGP-NEXT:    v_subb_u32_e64 v8, s[4:5], v1, v7, vcc
-; CGP-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v7
-; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], 0, v8
-; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], s7, v0
-; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v8
-; CGP-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v7, v7, v9, s[4:5]
-; CGP-NEXT:    v_subrev_i32_e32 v9, vcc, s7, v0
-; CGP-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CGP-NEXT:    v_cmp_le_u32_e32 vcc, 0, v1
-; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, -1, vcc
-; CGP-NEXT:    v_cmp_le_u32_e32 vcc, s7, v9
-; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, -1, vcc
-; CGP-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
-; CGP-NEXT:    v_cndmask_b32_e32 v10, v10, v11, vcc
-; CGP-NEXT:    v_subrev_i32_e32 v11, vcc, s7, v9
-; CGP-NEXT:    v_subbrev_u32_e32 v12, vcc, 0, v1, vcc
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
-; CGP-NEXT:    v_cndmask_b32_e32 v9, v9, v11, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v1, v1, v12, vcc
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
-; CGP-NEXT:    v_mul_f32_e32 v7, 0x2f800000, v4
-; CGP-NEXT:    v_trunc_f32_e32 v7, v7
-; CGP-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v7
-; CGP-NEXT:    v_cvt_u32_f32_e32 v4, v4
-; CGP-NEXT:    v_cvt_u32_f32_e32 v7, v7
-; CGP-NEXT:    v_cndmask_b32_e32 v0, v0, v9, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v1, v8, v1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v8, -1, v4
-; CGP-NEXT:    v_mul_lo_u32 v9, s6, v7
-; CGP-NEXT:    v_mul_hi_u32 v11, s6, v4
-; CGP-NEXT:    v_mul_lo_u32 v10, s6, v4
-; CGP-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
-; CGP-NEXT:    v_addc_u32_e32 v3, vcc, v3, v6, vcc
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
-; CGP-NEXT:    v_mul_lo_u32 v9, v7, v10
-; CGP-NEXT:    v_mul_lo_u32 v11, v4, v8
-; CGP-NEXT:    v_mul_hi_u32 v12, v4, v10
-; CGP-NEXT:    v_mul_hi_u32 v10, v7, v10
-; CGP-NEXT:    v_xor_b32_e32 v0, v0, v5
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v14, v11
 ; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
-; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v12, v7, v8
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v11, v9
-; CGP-NEXT:    v_mul_hi_u32 v11, v4, v8
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v13
+; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v11, vcc, v11, v13
 ; CGP-NEXT:    v_mul_hi_u32 v8, v7, v8
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v12, v10
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
-; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
 ; CGP-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
 ; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
 ; CGP-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
 ; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v9
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
 ; CGP-NEXT:    v_addc_u32_e64 v9, s[4:5], v7, v8, vcc
-; CGP-NEXT:    v_mul_lo_u32 v10, -1, v4
+; CGP-NEXT:    v_mul_lo_u32 v10, -1, v6
 ; CGP-NEXT:    v_mul_lo_u32 v11, s6, v9
-; CGP-NEXT:    v_mul_hi_u32 v13, s6, v4
-; CGP-NEXT:    v_mul_lo_u32 v12, s6, v4
+; CGP-NEXT:    v_mul_hi_u32 v13, s6, v6
+; CGP-NEXT:    v_mul_lo_u32 v14, s6, v6
 ; CGP-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v8
 ; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v11
 ; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v13
-; CGP-NEXT:    v_mul_lo_u32 v11, v9, v12
-; CGP-NEXT:    v_mul_lo_u32 v13, v4, v10
-; CGP-NEXT:    v_mul_hi_u32 v8, v4, v12
-; CGP-NEXT:    v_mul_hi_u32 v12, v9, v12
-; CGP-NEXT:    v_xor_b32_e32 v2, v2, v6
+; CGP-NEXT:    v_mul_lo_u32 v11, v9, v14
+; CGP-NEXT:    v_mul_lo_u32 v13, v6, v10
+; CGP-NEXT:    v_mul_hi_u32 v8, v6, v14
+; CGP-NEXT:    v_mul_lo_u32 v15, v9, v10
+; CGP-NEXT:    v_mul_hi_u32 v14, v9, v14
 ; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v13
 ; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
 ; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v11, v8
+; CGP-NEXT:    v_mul_hi_u32 v11, v6, v10
 ; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
-; CGP-NEXT:    v_mul_lo_u32 v11, v9, v10
 ; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v13, v8
-; CGP-NEXT:    v_mul_hi_u32 v13, v4, v10
-; CGP-NEXT:    v_mul_hi_u32 v9, v9, v10
-; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v13
+; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v15, v14
+; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v13, v11
 ; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v13
+; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v14, v13
+; CGP-NEXT:    v_mul_hi_u32 v9, v9, v10
 ; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v11, v8
-; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v12, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v13, v10
 ; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v10
 ; CGP-NEXT:    v_addc_u32_e32 v7, vcc, v7, v9, vcc
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; CGP-NEXT:    v_xor_b32_e32 v0, v0, v12
+; CGP-NEXT:    v_xor_b32_e32 v1, v1, v12
 ; CGP-NEXT:    v_addc_u32_e32 v7, vcc, 0, v7, vcc
-; CGP-NEXT:    v_xor_b32_e32 v3, v3, v6
-; CGP-NEXT:    v_xor_b32_e32 v1, v1, v5
-; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v0, v5
-; CGP-NEXT:    v_mul_lo_u32 v8, v3, v4
-; CGP-NEXT:    v_mul_lo_u32 v9, v2, v7
-; CGP-NEXT:    v_subb_u32_e32 v1, vcc, v1, v5, vcc
-; CGP-NEXT:    v_mul_hi_u32 v5, v2, v4
-; CGP-NEXT:    v_mul_hi_u32 v4, v3, v4
+; CGP-NEXT:    v_mul_lo_u32 v8, v1, v6
+; CGP-NEXT:    v_mul_lo_u32 v9, v0, v7
+; CGP-NEXT:    v_mul_hi_u32 v10, v0, v6
+; CGP-NEXT:    v_mul_lo_u32 v11, v1, v7
+; CGP-NEXT:    v_mul_hi_u32 v6, v1, v6
 ; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
 ; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; CGP-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v8, v3, v7
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v9, v5
-; CGP-NEXT:    v_mul_hi_u32 v9, v2, v7
-; CGP-NEXT:    v_mul_hi_u32 v7, v3, v7
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v8, v4
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; CGP-NEXT:    v_mul_hi_u32 v10, v0, v7
 ; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v9
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v11, v6
 ; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
-; CGP-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v10
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
+; CGP-NEXT:    v_mul_hi_u32 v7, v1, v7
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; CGP-NEXT:    v_mul_lo_u32 v8, 0, v6
+; CGP-NEXT:    v_mul_lo_u32 v7, s7, v7
+; CGP-NEXT:    v_mul_hi_u32 v9, s7, v6
+; CGP-NEXT:    v_mul_lo_u32 v6, s7, v6
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v0, v6
+; CGP-NEXT:    v_subb_u32_e64 v6, s[4:5], v1, v7, vcc
+; CGP-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v7
+; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], 0, v6
+; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], s7, v0
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v6
+; CGP-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
+; CGP-NEXT:    v_cndmask_b32_e64 v7, v7, v8, s[4:5]
+; CGP-NEXT:    v_subrev_i32_e32 v8, vcc, s7, v0
+; CGP-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
+; CGP-NEXT:    v_cmp_le_u32_e32 vcc, 0, v1
+; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
+; CGP-NEXT:    v_cmp_le_u32_e32 vcc, s7, v8
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, -1, vcc
+; CGP-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
+; CGP-NEXT:    v_cndmask_b32_e32 v9, v9, v10, vcc
+; CGP-NEXT:    v_subrev_i32_e32 v10, vcc, s7, v8
+; CGP-NEXT:    v_subbrev_u32_e32 v11, vcc, 0, v1, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v9
+; CGP-NEXT:    v_cndmask_b32_e32 v5, v8, v10, vcc
+; CGP-NEXT:    v_mul_f32_e32 v8, 0x2f800000, v4
+; CGP-NEXT:    v_trunc_f32_e32 v8, v8
+; CGP-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v8
+; CGP-NEXT:    v_cvt_u32_f32_e32 v4, v4
+; CGP-NEXT:    v_cvt_u32_f32_e32 v8, v8
+; CGP-NEXT:    v_cndmask_b32_e32 v1, v1, v11, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
+; CGP-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v1, v6, v1, vcc
+; CGP-NEXT:    v_mul_lo_u32 v5, -1, v4
+; CGP-NEXT:    v_mul_lo_u32 v6, s6, v8
+; CGP-NEXT:    v_mul_hi_u32 v7, s6, v4
+; CGP-NEXT:    v_mul_lo_u32 v9, s6, v4
+; CGP-NEXT:    v_ashrrev_i32_e32 v10, 31, v3
+; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
+; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; CGP-NEXT:    v_mul_lo_u32 v6, v8, v9
+; CGP-NEXT:    v_mul_lo_u32 v7, v4, v5
+; CGP-NEXT:    v_mul_hi_u32 v11, v4, v9
+; CGP-NEXT:    v_add_i32_e32 v2, vcc, v2, v10
+; CGP-NEXT:    v_addc_u32_e32 v3, vcc, v3, v10, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; CGP-NEXT:    v_mul_lo_u32 v13, v8, v5
+; CGP-NEXT:    v_mul_hi_u32 v9, v8, v9
+; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v11
+; CGP-NEXT:    v_mul_hi_u32 v11, v4, v5
+; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v13, v9
+; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; CGP-NEXT:    v_mul_hi_u32 v5, v8, v5
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v9, v7
+; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; CGP-NEXT:    v_addc_u32_e64 v6, s[4:5], v8, v5, vcc
+; CGP-NEXT:    v_mul_lo_u32 v7, -1, v4
+; CGP-NEXT:    v_mul_lo_u32 v9, s6, v6
+; CGP-NEXT:    v_mul_hi_u32 v11, s6, v4
+; CGP-NEXT:    v_mul_lo_u32 v13, s6, v4
+; CGP-NEXT:    v_add_i32_e64 v5, s[4:5], v8, v5
+; CGP-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v9
+; CGP-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v11
+; CGP-NEXT:    v_mul_lo_u32 v9, v6, v13
+; CGP-NEXT:    v_mul_lo_u32 v11, v4, v7
+; CGP-NEXT:    v_mul_hi_u32 v8, v4, v13
+; CGP-NEXT:    v_mul_lo_u32 v14, v6, v7
+; CGP-NEXT:    v_mul_hi_u32 v13, v6, v13
+; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v9, v8
+; CGP-NEXT:    v_mul_hi_u32 v9, v4, v7
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v11, v8
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v14, v13
+; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v9
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v13, v11
+; CGP-NEXT:    v_mul_hi_u32 v6, v6, v7
+; CGP-NEXT:    v_add_i32_e64 v7, s[4:5], v9, v8
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v11, v8
+; CGP-NEXT:    v_add_i32_e64 v6, s[4:5], v6, v8
+; CGP-NEXT:    v_addc_u32_e32 v5, vcc, v5, v6, vcc
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; CGP-NEXT:    v_xor_b32_e32 v2, v2, v10
+; CGP-NEXT:    v_xor_b32_e32 v3, v3, v10
+; CGP-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; CGP-NEXT:    v_mul_lo_u32 v6, v3, v4
+; CGP-NEXT:    v_mul_lo_u32 v7, v2, v5
+; CGP-NEXT:    v_mul_hi_u32 v8, v2, v4
+; CGP-NEXT:    v_mul_lo_u32 v9, v3, v5
+; CGP-NEXT:    v_mul_hi_u32 v4, v3, v4
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; CGP-NEXT:    v_mul_hi_u32 v8, v2, v5
+; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v9, v4
+; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; CGP-NEXT:    v_mul_hi_u32 v5, v3, v5
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
 ; CGP-NEXT:    v_mul_lo_u32 v7, 0, v4
 ; CGP-NEXT:    v_mul_lo_u32 v5, s7, v5
-; CGP-NEXT:    v_mul_lo_u32 v8, s7, v4
+; CGP-NEXT:    v_mul_lo_u32 v6, s7, v4
 ; CGP-NEXT:    v_mul_hi_u32 v4, s7, v4
+; CGP-NEXT:    v_xor_b32_e32 v0, v0, v12
+; CGP-NEXT:    v_xor_b32_e32 v1, v1, v12
+; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v0, v12
+; CGP-NEXT:    v_subb_u32_e32 v1, vcc, v1, v12, vcc
 ; CGP-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
 ; CGP-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v2, v8
+; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v2, v6
 ; CGP-NEXT:    v_subb_u32_e64 v5, s[4:5], v3, v4, vcc
 ; CGP-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v4
 ; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], 0, v5
 ; CGP-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[4:5]
 ; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], s7, v2
-; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
+; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[4:5]
 ; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v5
 ; CGP-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v4, v4, v7, s[4:5]
-; CGP-NEXT:    v_subrev_i32_e32 v7, vcc, s7, v2
+; CGP-NEXT:    v_cndmask_b32_e64 v4, v4, v6, s[4:5]
+; CGP-NEXT:    v_subrev_i32_e32 v6, vcc, s7, v2
 ; CGP-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
 ; CGP-NEXT:    v_cmp_le_u32_e32 vcc, 0, v3
+; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
+; CGP-NEXT:    v_cmp_le_u32_e32 vcc, s7, v6
 ; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
-; CGP-NEXT:    v_cmp_le_u32_e32 vcc, s7, v7
-; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
 ; CGP-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v3
-; CGP-NEXT:    v_cndmask_b32_e32 v8, v8, v9, vcc
-; CGP-NEXT:    v_subrev_i32_e32 v9, vcc, s7, v7
-; CGP-NEXT:    v_subbrev_u32_e32 v10, vcc, 0, v3, vcc
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v8
-; CGP-NEXT:    v_cndmask_b32_e32 v7, v7, v9, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v3, v3, v10, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v7, v7, v8, vcc
+; CGP-NEXT:    v_subrev_i32_e32 v8, vcc, s7, v6
+; CGP-NEXT:    v_subbrev_u32_e32 v9, vcc, 0, v3, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
+; CGP-NEXT:    v_cndmask_b32_e32 v6, v6, v8, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v3, v3, v9, vcc
 ; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
-; CGP-NEXT:    v_cndmask_b32_e32 v2, v2, v7, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc
 ; CGP-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc
-; CGP-NEXT:    v_xor_b32_e32 v2, v2, v6
-; CGP-NEXT:    v_xor_b32_e32 v3, v3, v6
-; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v2, v6
-; CGP-NEXT:    v_subb_u32_e32 v3, vcc, v3, v6, vcc
+; CGP-NEXT:    v_xor_b32_e32 v2, v2, v10
+; CGP-NEXT:    v_xor_b32_e32 v3, v3, v10
+; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v2, v10
+; CGP-NEXT:    v_subb_u32_e32 v3, vcc, v3, v10, vcc
 ; CGP-NEXT:    s_setpc_b64 s[30:31]
   %result = srem <2 x i64> %num, <i64 1235195, i64 1235195>
   ret <2 x i64> %result
@@ -2485,139 +2485,139 @@
 ; CHECK-NEXT:    v_xor_b32_e32 v2, v5, v2
 ; CHECK-NEXT:    v_cvt_f32_u32_e32 v5, v3
 ; CHECK-NEXT:    v_cvt_f32_u32_e32 v6, v2
-; CHECK-NEXT:    v_ashrrev_i32_e32 v7, 31, v1
+; CHECK-NEXT:    v_sub_i32_e32 v7, vcc, 0, v3
+; CHECK-NEXT:    v_subb_u32_e32 v8, vcc, 0, v2, vcc
+; CHECK-NEXT:    v_ashrrev_i32_e32 v13, 31, v1
 ; CHECK-NEXT:    v_mac_f32_e32 v5, 0x4f800000, v6
 ; CHECK-NEXT:    v_rcp_iflag_f32_e32 v5, v5
-; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v0, v7
-; CHECK-NEXT:    v_addc_u32_e32 v1, vcc, v1, v7, vcc
-; CHECK-NEXT:    v_sub_i32_e32 v9, vcc, 0, v3
 ; CHECK-NEXT:    v_mul_f32_e32 v5, 0x5f7ffffc, v5
-; CHECK-NEXT:    v_mul_f32_e32 v8, 0x2f800000, v5
-; CHECK-NEXT:    v_trunc_f32_e32 v8, v8
-; CHECK-NEXT:    v_mac_f32_e32 v5, 0xcf800000, v8
+; CHECK-NEXT:    v_mul_f32_e32 v6, 0x2f800000, v5
+; CHECK-NEXT:    v_trunc_f32_e32 v6, v6
+; CHECK-NEXT:    v_mac_f32_e32 v5, 0xcf800000, v6
 ; CHECK-NEXT:    v_cvt_u32_f32_e32 v5, v5
-; CHECK-NEXT:    v_cvt_u32_f32_e32 v8, v8
-; CHECK-NEXT:    v_subb_u32_e32 v10, vcc, 0, v2, vcc
-; CHECK-NEXT:    v_xor_b32_e32 v6, v6, v7
-; CHECK-NEXT:    v_mul_lo_u32 v11, v10, v5
-; CHECK-NEXT:    v_mul_lo_u32 v12, v9, v8
-; CHECK-NEXT:    v_mul_hi_u32 v14, v9, v5
-; CHECK-NEXT:    v_mul_lo_u32 v13, v9, v5
-; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v7
-; CHECK-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
-; CHECK-NEXT:    v_add_i32_e32 v11, vcc, v11, v14
-; CHECK-NEXT:    v_mul_lo_u32 v12, v8, v13
-; CHECK-NEXT:    v_mul_lo_u32 v14, v5, v11
-; CHECK-NEXT:    v_mul_hi_u32 v15, v5, v13
-; CHECK-NEXT:    v_mul_hi_u32 v13, v8, v13
-; CHECK-NEXT:    v_add_i32_e32 v12, vcc, v12, v14
-; CHECK-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v12, vcc, v12, v15
+; CHECK-NEXT:    v_cvt_u32_f32_e32 v6, v6
+; CHECK-NEXT:    v_mul_lo_u32 v10, v8, v5
+; CHECK-NEXT:    v_mul_lo_u32 v9, v7, v6
+; CHECK-NEXT:    v_mul_hi_u32 v12, v7, v5
+; CHECK-NEXT:    v_mul_lo_u32 v11, v7, v5
+; CHECK-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
+; CHECK-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
+; CHECK-NEXT:    v_mul_lo_u32 v10, v6, v11
+; CHECK-NEXT:    v_mul_lo_u32 v12, v5, v9
+; CHECK-NEXT:    v_mul_hi_u32 v15, v5, v11
+; CHECK-NEXT:    v_add_i32_e32 v14, vcc, v0, v13
+; CHECK-NEXT:    v_addc_u32_e32 v1, vcc, v1, v13, vcc
+; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
+; CHECK-NEXT:    v_mul_lo_u32 v16, v6, v9
+; CHECK-NEXT:    v_mul_hi_u32 v11, v6, v11
+; CHECK-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v10, v15
+; CHECK-NEXT:    v_mul_hi_u32 v15, v5, v9
+; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v12, v10
+; CHECK-NEXT:    v_add_i32_e32 v11, vcc, v16, v11
 ; CHECK-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v15, v8, v11
-; CHECK-NEXT:    v_add_i32_e32 v12, vcc, v14, v12
-; CHECK-NEXT:    v_mul_hi_u32 v14, v5, v11
-; CHECK-NEXT:    v_mul_hi_u32 v11, v8, v11
-; CHECK-NEXT:    v_add_i32_e32 v13, vcc, v15, v13
+; CHECK-NEXT:    v_add_i32_e32 v11, vcc, v11, v15
 ; CHECK-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v13, vcc, v13, v14
-; CHECK-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
-; CHECK-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
-; CHECK-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
-; CHECK-NEXT:    v_add_i32_e32 v11, vcc, v11, v13
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v12
-; CHECK-NEXT:    v_addc_u32_e64 v12, s[4:5], v8, v11, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v10, v10, v5
-; CHECK-NEXT:    v_mul_lo_u32 v13, v9, v12
-; CHECK-NEXT:    v_mul_lo_u32 v14, v9, v5
-; CHECK-NEXT:    v_mul_hi_u32 v9, v9, v5
+; CHECK-NEXT:    v_add_i32_e32 v12, vcc, v12, v15
+; CHECK-NEXT:    v_mul_hi_u32 v9, v6, v9
+; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; CHECK-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
+; CHECK-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v10
+; CHECK-NEXT:    v_addc_u32_e64 v10, s[4:5], v6, v9, vcc
+; CHECK-NEXT:    v_mul_lo_u32 v8, v8, v5
+; CHECK-NEXT:    v_mul_lo_u32 v11, v7, v10
+; CHECK-NEXT:    v_mul_hi_u32 v12, v7, v5
+; CHECK-NEXT:    v_mul_lo_u32 v7, v7, v5
+; CHECK-NEXT:    v_add_i32_e64 v6, s[4:5], v6, v9
 ; CHECK-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v11
-; CHECK-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v13
-; CHECK-NEXT:    v_mul_hi_u32 v11, v5, v14
-; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v10, v9
-; CHECK-NEXT:    v_mul_lo_u32 v10, v12, v14
-; CHECK-NEXT:    v_mul_lo_u32 v13, v5, v9
-; CHECK-NEXT:    v_mul_hi_u32 v14, v12, v14
-; CHECK-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v13
-; CHECK-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v11
-; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
-; CHECK-NEXT:    v_mul_lo_u32 v11, v12, v9
-; CHECK-NEXT:    v_add_i32_e64 v10, s[4:5], v13, v10
-; CHECK-NEXT:    v_mul_hi_u32 v13, v5, v9
-; CHECK-NEXT:    v_mul_hi_u32 v9, v12, v9
-; CHECK-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v14
-; CHECK-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v13
-; CHECK-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v13, s[4:5], v14, v13
-; CHECK-NEXT:    v_add_i32_e64 v10, s[4:5], v11, v10
+; CHECK-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v12
+; CHECK-NEXT:    v_mul_lo_u32 v11, v10, v7
+; CHECK-NEXT:    v_mul_lo_u32 v12, v5, v8
+; CHECK-NEXT:    v_mul_hi_u32 v9, v5, v7
+; CHECK-NEXT:    v_mul_lo_u32 v15, v10, v8
+; CHECK-NEXT:    v_mul_hi_u32 v7, v10, v7
+; CHECK-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
+; CHECK-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v9
+; CHECK-NEXT:    v_mul_hi_u32 v11, v5, v8
+; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v12, v9
+; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v15, v7
+; CHECK-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v11
 ; CHECK-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v11, s[4:5], v13, v11
-; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v11
-; CHECK-NEXT:    v_addc_u32_e32 v8, vcc, v8, v9, vcc
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v10
-; CHECK-NEXT:    v_addc_u32_e32 v8, vcc, 0, v8, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v9, v1, v5
-; CHECK-NEXT:    v_mul_lo_u32 v10, v6, v8
-; CHECK-NEXT:    v_mul_hi_u32 v11, v6, v5
+; CHECK-NEXT:    v_add_i32_e64 v11, s[4:5], v12, v11
+; CHECK-NEXT:    v_mul_hi_u32 v8, v10, v8
+; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v9
+; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v9
+; CHECK-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
+; CHECK-NEXT:    v_addc_u32_e32 v6, vcc, v6, v8, vcc
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; CHECK-NEXT:    v_xor_b32_e32 v14, v14, v13
+; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v13
+; CHECK-NEXT:    v_addc_u32_e32 v6, vcc, 0, v6, vcc
+; CHECK-NEXT:    v_mul_lo_u32 v7, v1, v5
+; CHECK-NEXT:    v_mul_lo_u32 v8, v14, v6
+; CHECK-NEXT:    v_mul_hi_u32 v9, v14, v5
+; CHECK-NEXT:    v_mul_lo_u32 v10, v1, v6
 ; CHECK-NEXT:    v_mul_hi_u32 v5, v1, v5
-; CHECK-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
-; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v11, v1, v8
-; CHECK-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
-; CHECK-NEXT:    v_mul_hi_u32 v10, v6, v8
-; CHECK-NEXT:    v_mul_hi_u32 v8, v1, v8
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v11, v5
-; CHECK-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v10
-; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; CHECK-NEXT:    v_mul_hi_u32 v9, v14, v6
+; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v10, v5
+; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v9
 ; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
 ; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
-; CHECK-NEXT:    v_mul_lo_u32 v9, v2, v5
-; CHECK-NEXT:    v_mul_lo_u32 v8, v3, v8
-; CHECK-NEXT:    v_mul_lo_u32 v10, v3, v5
-; CHECK-NEXT:    v_mul_hi_u32 v5, v3, v5
-; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; CHECK-NEXT:    v_sub_i32_e32 v6, vcc, v6, v10
-; CHECK-NEXT:    v_subb_u32_e64 v8, s[4:5], v1, v5, vcc
-; CHECK-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v5
-; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v8, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[4:5]
-; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v6, v3
-; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
-; CHECK-NEXT:    v_cmp_eq_u32_e64 s[4:5], v8, v2
+; CHECK-NEXT:    v_mul_hi_u32 v6, v1, v6
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; CHECK-NEXT:    v_mul_lo_u32 v7, v2, v5
+; CHECK-NEXT:    v_mul_lo_u32 v6, v3, v6
+; CHECK-NEXT:    v_mul_hi_u32 v8, v3, v5
+; CHECK-NEXT:    v_mul_lo_u32 v5, v3, v5
+; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; CHECK-NEXT:    v_sub_i32_e32 v5, vcc, v14, v5
+; CHECK-NEXT:    v_subb_u32_e64 v7, s[4:5], v1, v6, vcc
+; CHECK-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v6
+; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v2
+; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[4:5]
+; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v5, v3
+; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
+; CHECK-NEXT:    v_cmp_eq_u32_e64 s[4:5], v7, v2
 ; CHECK-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
-; CHECK-NEXT:    v_cndmask_b32_e64 v5, v5, v9, s[4:5]
-; CHECK-NEXT:    v_sub_i32_e32 v9, vcc, v6, v3
-; CHECK-NEXT:    v_subbrev_u32_e64 v10, s[4:5], 0, v1, vcc
-; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v10, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
-; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v9, v3
+; CHECK-NEXT:    v_cndmask_b32_e64 v6, v6, v8, s[4:5]
+; CHECK-NEXT:    v_sub_i32_e32 v8, vcc, v5, v3
+; CHECK-NEXT:    v_subbrev_u32_e64 v9, s[4:5], 0, v1, vcc
+; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v9, v2
+; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
+; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v8, v3
 ; CHECK-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
-; CHECK-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[4:5]
-; CHECK-NEXT:    v_cmp_eq_u32_e64 s[4:5], v10, v2
-; CHECK-NEXT:    v_sub_i32_e32 v2, vcc, v9, v3
-; CHECK-NEXT:    v_cndmask_b32_e64 v11, v11, v12, s[4:5]
+; CHECK-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
+; CHECK-NEXT:    v_cmp_eq_u32_e64 s[4:5], v9, v2
+; CHECK-NEXT:    v_sub_i32_e32 v2, vcc, v8, v3
+; CHECK-NEXT:    v_cndmask_b32_e64 v10, v10, v11, s[4:5]
 ; CHECK-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11
-; CHECK-NEXT:    v_cndmask_b32_e32 v2, v9, v2, vcc
-; CHECK-NEXT:    v_cndmask_b32_e32 v1, v10, v1, vcc
-; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
-; CHECK-NEXT:    v_cndmask_b32_e32 v2, v6, v2, vcc
-; CHECK-NEXT:    v_cndmask_b32_e32 v1, v8, v1, vcc
-; CHECK-NEXT:    v_xor_b32_e32 v2, v2, v7
-; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v7
-; CHECK-NEXT:    v_sub_i32_e32 v2, vcc, v2, v7
-; CHECK-NEXT:    v_subb_u32_e32 v3, vcc, v1, v7, vcc
+; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
+; CHECK-NEXT:    v_cndmask_b32_e32 v2, v8, v2, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v1, v9, v1, vcc
+; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
+; CHECK-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v1, v7, v1, vcc
+; CHECK-NEXT:    v_xor_b32_e32 v2, v2, v13
+; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v13
+; CHECK-NEXT:    v_sub_i32_e32 v2, vcc, v2, v13
+; CHECK-NEXT:    v_subb_u32_e32 v3, vcc, v1, v13, vcc
 ; CHECK-NEXT:  BB7_2: ; %Flow
 ; CHECK-NEXT:    s_or_saveexec_b64 s[4:5], s[6:7]
 ; CHECK-NEXT:    s_xor_b64 exec, exec, s[4:5]
@@ -2658,287 +2658,287 @@
 ; GISEL-NEXT:    s_movk_i32 s6, 0x1000
 ; GISEL-NEXT:    s_mov_b32 s7, 0
 ; GISEL-NEXT:    v_lshl_b64 v[4:5], s[6:7], v4
-; GISEL-NEXT:    v_ashrrev_i32_e32 v9, 31, v1
+; GISEL-NEXT:    v_ashrrev_i32_e32 v15, 31, v1
 ; GISEL-NEXT:    v_ashrrev_i32_e32 v7, 31, v5
 ; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
 ; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v7, vcc
-; GISEL-NEXT:    v_xor_b32_e32 v5, v5, v7
 ; GISEL-NEXT:    v_xor_b32_e32 v4, v4, v7
+; GISEL-NEXT:    v_xor_b32_e32 v5, v5, v7
 ; GISEL-NEXT:    v_cvt_f32_u32_e32 v7, v4
 ; GISEL-NEXT:    v_cvt_f32_u32_e32 v8, v5
-; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v9
-; GISEL-NEXT:    v_addc_u32_e32 v1, vcc, v1, v9, vcc
-; GISEL-NEXT:    v_sub_i32_e32 v10, vcc, 0, v4
+; GISEL-NEXT:    v_sub_i32_e32 v9, vcc, 0, v4
+; GISEL-NEXT:    v_subb_u32_e32 v10, vcc, 0, v5, vcc
 ; GISEL-NEXT:    v_mac_f32_e32 v7, 0x4f800000, v8
 ; GISEL-NEXT:    v_rcp_iflag_f32_e32 v7, v7
-; GISEL-NEXT:    v_xor_b32_e32 v8, v0, v9
-; GISEL-NEXT:    v_subb_u32_e32 v11, vcc, 0, v5, vcc
-; GISEL-NEXT:    v_xor_b32_e32 v16, v1, v9
-; GISEL-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v7
-; GISEL-NEXT:    v_mul_f32_e32 v7, 0x2f800000, v0
-; GISEL-NEXT:    v_trunc_f32_e32 v7, v7
-; GISEL-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v7
-; GISEL-NEXT:    v_cvt_u32_f32_e32 v0, v0
+; GISEL-NEXT:    v_mul_f32_e32 v7, 0x5f7ffffc, v7
+; GISEL-NEXT:    v_mul_f32_e32 v8, 0x2f800000, v7
+; GISEL-NEXT:    v_trunc_f32_e32 v8, v8
+; GISEL-NEXT:    v_mac_f32_e32 v7, 0xcf800000, v8
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v7, v7
-; GISEL-NEXT:    v_mul_lo_u32 v12, v11, v0
-; GISEL-NEXT:    v_mul_lo_u32 v13, v10, v7
-; GISEL-NEXT:    v_mul_hi_u32 v15, v10, v0
-; GISEL-NEXT:    v_mul_lo_u32 v14, v10, v0
+; GISEL-NEXT:    v_cvt_u32_f32_e32 v8, v8
+; GISEL-NEXT:    v_mul_lo_u32 v11, v10, v7
+; GISEL-NEXT:    v_mul_lo_u32 v12, v9, v8
+; GISEL-NEXT:    v_mul_hi_u32 v13, v9, v7
+; GISEL-NEXT:    v_mul_lo_u32 v14, v9, v7
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v13
+; GISEL-NEXT:    v_mul_lo_u32 v12, v8, v14
+; GISEL-NEXT:    v_mul_lo_u32 v13, v7, v11
+; GISEL-NEXT:    v_mul_hi_u32 v16, v7, v14
+; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v15
+; GISEL-NEXT:    v_addc_u32_e32 v1, vcc, v1, v15, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
-; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v15
-; GISEL-NEXT:    v_mul_lo_u32 v13, v7, v14
-; GISEL-NEXT:    v_mul_lo_u32 v15, v0, v12
-; GISEL-NEXT:    v_mul_hi_u32 v1, v0, v14
-; GISEL-NEXT:    v_mul_hi_u32 v14, v7, v14
-; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v15
-; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v1, vcc, v13, v1
-; GISEL-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v13, v7, v12
-; GISEL-NEXT:    v_add_i32_e32 v1, vcc, v15, v1
-; GISEL-NEXT:    v_mul_hi_u32 v15, v0, v12
-; GISEL-NEXT:    v_mul_hi_u32 v12, v7, v12
-; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v14
+; GISEL-NEXT:    v_mul_lo_u32 v17, v8, v11
+; GISEL-NEXT:    v_mul_hi_u32 v14, v8, v14
+; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v16
+; GISEL-NEXT:    v_mul_hi_u32 v16, v7, v11
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
+; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v17, v14
 ; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v15
-; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v15
-; GISEL-NEXT:    v_add_i32_e32 v1, vcc, v13, v1
+; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v16
+; GISEL-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v16
+; GISEL-NEXT:    v_mul_hi_u32 v11, v8, v11
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
 ; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
-; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
-; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
-; GISEL-NEXT:    v_addc_u32_e64 v1, s[4:5], v7, v12, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v11, v11, v0
-; GISEL-NEXT:    v_mul_lo_u32 v13, v10, v1
-; GISEL-NEXT:    v_mul_lo_u32 v14, v10, v0
-; GISEL-NEXT:    v_mul_hi_u32 v10, v10, v0
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v12
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v13
-; GISEL-NEXT:    v_mul_hi_u32 v12, v0, v14
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v11, v10
-; GISEL-NEXT:    v_mul_lo_u32 v11, v1, v14
-; GISEL-NEXT:    v_mul_lo_u32 v13, v0, v10
-; GISEL-NEXT:    v_mul_hi_u32 v14, v1, v14
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v13
-; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; GISEL-NEXT:    v_mul_lo_u32 v12, v1, v10
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v13, v11
-; GISEL-NEXT:    v_mul_hi_u32 v13, v0, v10
-; GISEL-NEXT:    v_mul_hi_u32 v1, v1, v10
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v14
-; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v13
-; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v13, s[4:5], v14, v13
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v12, v11
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v13, v12
-; GISEL-NEXT:    v_add_i32_e64 v1, s[4:5], v1, v10
-; GISEL-NEXT:    v_addc_u32_e32 v1, vcc, v7, v1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v0, v11
-; GISEL-NEXT:    v_addc_u32_e32 v10, vcc, 0, v1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v11, v16, v7
-; GISEL-NEXT:    v_mul_lo_u32 v12, v8, v10
-; GISEL-NEXT:    v_lshl_b64 v[0:1], s[6:7], v6
-; GISEL-NEXT:    v_mul_hi_u32 v6, v8, v7
-; GISEL-NEXT:    v_mul_hi_u32 v7, v16, v7
-; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v11, v6
-; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v11, v16, v10
-; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v12, v6
-; GISEL-NEXT:    v_mul_hi_u32 v12, v8, v10
-; GISEL-NEXT:    v_mul_hi_u32 v10, v16, v10
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v11, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v13
 ; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v12
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
-; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GISEL-NEXT:    v_addc_u32_e64 v12, s[4:5], v8, v11, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v10, v10, v7
+; GISEL-NEXT:    v_mul_lo_u32 v13, v9, v12
+; GISEL-NEXT:    v_mul_hi_u32 v14, v9, v7
+; GISEL-NEXT:    v_mul_lo_u32 v9, v9, v7
+; GISEL-NEXT:    v_xor_b32_e32 v16, v0, v15
+; GISEL-NEXT:    v_add_i32_e64 v0, s[4:5], v10, v13
+; GISEL-NEXT:    v_add_i32_e64 v0, s[4:5], v0, v14
+; GISEL-NEXT:    v_mul_lo_u32 v10, v12, v9
+; GISEL-NEXT:    v_mul_lo_u32 v13, v7, v0
+; GISEL-NEXT:    v_xor_b32_e32 v14, v1, v15
+; GISEL-NEXT:    v_add_i32_e64 v1, s[4:5], v8, v11
+; GISEL-NEXT:    v_mul_hi_u32 v8, v7, v9
+; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v13
+; GISEL-NEXT:    v_mul_lo_u32 v13, v12, v0
+; GISEL-NEXT:    v_mul_hi_u32 v9, v12, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v10, v8
+; GISEL-NEXT:    v_mul_hi_u32 v10, v7, v0
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v11, v8
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v13, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v10
+; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v11, v10
+; GISEL-NEXT:    v_mul_hi_u32 v0, v12, v0
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v9, v8
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v10, v9
+; GISEL-NEXT:    v_add_i32_e64 v0, s[4:5], v0, v9
+; GISEL-NEXT:    v_addc_u32_e32 v0, vcc, v1, v0, vcc
+; GISEL-NEXT:    v_add_i32_e32 v1, vcc, v7, v8
+; GISEL-NEXT:    v_addc_u32_e32 v0, vcc, 0, v0, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v7, v14, v1
+; GISEL-NEXT:    v_mul_lo_u32 v8, v16, v0
+; GISEL-NEXT:    v_mul_hi_u32 v9, v16, v1
+; GISEL-NEXT:    v_mul_lo_u32 v10, v14, v0
+; GISEL-NEXT:    v_mul_hi_u32 v1, v14, v1
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; GISEL-NEXT:    v_mul_hi_u32 v9, v16, v0
 ; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v11, v7
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
-; GISEL-NEXT:    v_mul_lo_u32 v10, v5, v6
-; GISEL-NEXT:    v_mul_lo_u32 v7, v4, v7
-; GISEL-NEXT:    v_mul_lo_u32 v11, v4, v6
-; GISEL-NEXT:    v_mul_hi_u32 v6, v4, v6
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
-; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; GISEL-NEXT:    v_sub_i32_e32 v7, vcc, v8, v11
-; GISEL-NEXT:    v_subb_u32_e64 v8, s[4:5], v16, v6, vcc
-; GISEL-NEXT:    v_sub_i32_e64 v6, s[4:5], v16, v6
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_add_i32_e32 v1, vcc, v10, v1
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v1, vcc, v1, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
+; GISEL-NEXT:    v_mul_hi_u32 v0, v14, v0
+; GISEL-NEXT:    v_add_i32_e32 v1, vcc, v1, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v7
+; GISEL-NEXT:    v_mul_lo_u32 v7, v5, v1
+; GISEL-NEXT:    v_mul_lo_u32 v8, v4, v0
+; GISEL-NEXT:    v_mul_hi_u32 v9, v4, v1
+; GISEL-NEXT:    v_mul_lo_u32 v10, v4, v1
+; GISEL-NEXT:    v_lshl_b64 v[0:1], s[6:7], v6
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v7, v8
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
+; GISEL-NEXT:    v_sub_i32_e32 v7, vcc, v16, v10
+; GISEL-NEXT:    v_subb_u32_e64 v8, s[4:5], v14, v6, vcc
+; GISEL-NEXT:    v_sub_i32_e64 v6, s[4:5], v14, v6
 ; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v8, v5
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
 ; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
 ; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v8, v5
 ; GISEL-NEXT:    v_subb_u32_e32 v6, vcc, v6, v5, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, v10, v11, s[4:5]
-; GISEL-NEXT:    v_sub_i32_e32 v11, vcc, v7, v4
-; GISEL-NEXT:    v_subbrev_u32_e64 v12, s[4:5], 0, v6, vcc
-; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v12, v5
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, v9, v10, s[4:5]
+; GISEL-NEXT:    v_sub_i32_e32 v10, vcc, v7, v4
+; GISEL-NEXT:    v_subbrev_u32_e64 v11, s[4:5], 0, v6, vcc
+; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v11, v5
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v10, v4
 ; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v11, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v12, v5
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v11, v5
 ; GISEL-NEXT:    v_subb_u32_e32 v5, vcc, v6, v5, vcc
-; GISEL-NEXT:    v_sub_i32_e32 v4, vcc, v11, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v13, v13, v14, s[4:5]
+; GISEL-NEXT:    v_sub_i32_e32 v4, vcc, v10, v4
 ; GISEL-NEXT:    v_subbrev_u32_e32 v5, vcc, 0, v5, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v13
-; GISEL-NEXT:    v_cndmask_b32_e32 v4, v11, v4, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v5, v12, v5, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
 ; GISEL-NEXT:    v_ashrrev_i32_e32 v6, 31, v1
-; GISEL-NEXT:    v_cndmask_b32_e32 v5, v8, v5, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v4, v7, v4, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v6
 ; GISEL-NEXT:    v_addc_u32_e32 v1, vcc, v1, v6, vcc
-; GISEL-NEXT:    v_xor_b32_e32 v7, v0, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, v12, v13, s[4:5]
+; GISEL-NEXT:    v_xor_b32_e32 v13, v0, v6
 ; GISEL-NEXT:    v_xor_b32_e32 v6, v1, v6
-; GISEL-NEXT:    v_cvt_f32_u32_e32 v0, v7
+; GISEL-NEXT:    v_cvt_f32_u32_e32 v0, v13
 ; GISEL-NEXT:    v_cvt_f32_u32_e32 v1, v6
-; GISEL-NEXT:    v_ashrrev_i32_e32 v8, 31, v3
-; GISEL-NEXT:    v_xor_b32_e32 v4, v4, v9
-; GISEL-NEXT:    v_xor_b32_e32 v5, v5, v9
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v12
+; GISEL-NEXT:    v_cndmask_b32_e32 v4, v10, v4, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v5, v11, v5, vcc
 ; GISEL-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
 ; GISEL-NEXT:    v_rcp_iflag_f32_e32 v0, v0
-; GISEL-NEXT:    v_add_i32_e32 v1, vcc, v2, v8
-; GISEL-NEXT:    v_addc_u32_e32 v2, vcc, v3, v8, vcc
-; GISEL-NEXT:    v_xor_b32_e32 v3, v1, v8
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v9
+; GISEL-NEXT:    v_cndmask_b32_e32 v1, v7, v4, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v4, v8, v5, vcc
 ; GISEL-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GISEL-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
-; GISEL-NEXT:    v_trunc_f32_e32 v1, v1
-; GISEL-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
+; GISEL-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v0
+; GISEL-NEXT:    v_trunc_f32_e32 v5, v5
+; GISEL-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v5
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; GISEL-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GISEL-NEXT:    v_sub_i32_e32 v10, vcc, 0, v7
-; GISEL-NEXT:    v_subb_u32_e32 v11, vcc, 0, v6, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v12, v11, v0
-; GISEL-NEXT:    v_mul_lo_u32 v13, v10, v1
-; GISEL-NEXT:    v_mul_hi_u32 v15, v10, v0
-; GISEL-NEXT:    v_mul_lo_u32 v14, v10, v0
-; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v8
-; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
-; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v15
-; GISEL-NEXT:    v_mul_lo_u32 v13, v1, v14
-; GISEL-NEXT:    v_mul_lo_u32 v15, v0, v12
-; GISEL-NEXT:    v_mul_hi_u32 v16, v0, v14
-; GISEL-NEXT:    v_mul_hi_u32 v14, v1, v14
-; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v15
-; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v16
-; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v16, v1, v12
-; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v15, v13
-; GISEL-NEXT:    v_mul_hi_u32 v15, v0, v12
-; GISEL-NEXT:    v_mul_hi_u32 v12, v1, v12
-; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v16, v14
+; GISEL-NEXT:    v_cvt_u32_f32_e32 v5, v5
+; GISEL-NEXT:    v_sub_i32_e32 v7, vcc, 0, v13
+; GISEL-NEXT:    v_subb_u32_e32 v8, vcc, 0, v6, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v9, v8, v0
+; GISEL-NEXT:    v_mul_lo_u32 v10, v7, v5
+; GISEL-NEXT:    v_mul_hi_u32 v11, v7, v0
+; GISEL-NEXT:    v_mul_lo_u32 v12, v7, v0
+; GISEL-NEXT:    v_ashrrev_i32_e32 v14, 31, v3
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; GISEL-NEXT:    v_mul_lo_u32 v10, v5, v12
+; GISEL-NEXT:    v_mul_lo_u32 v11, v0, v9
+; GISEL-NEXT:    v_mul_hi_u32 v16, v0, v12
+; GISEL-NEXT:    v_add_i32_e32 v2, vcc, v2, v14
+; GISEL-NEXT:    v_addc_u32_e32 v3, vcc, v3, v14, vcc
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
+; GISEL-NEXT:    v_mul_lo_u32 v17, v5, v9
+; GISEL-NEXT:    v_mul_hi_u32 v12, v5, v12
+; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v16
+; GISEL-NEXT:    v_mul_hi_u32 v16, v0, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v17, v12
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v16
 ; GISEL-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v15
-; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v15, vcc, v16, v15
-; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
-; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
-; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v14
-; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v13
-; GISEL-NEXT:    v_addc_u32_e64 v13, s[4:5], v1, v12, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v11, v11, v0
-; GISEL-NEXT:    v_mul_lo_u32 v14, v10, v13
-; GISEL-NEXT:    v_mul_lo_u32 v15, v10, v0
-; GISEL-NEXT:    v_mul_hi_u32 v10, v10, v0
-; GISEL-NEXT:    v_add_i32_e64 v1, s[4:5], v1, v12
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v14
-; GISEL-NEXT:    v_mul_hi_u32 v12, v0, v15
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v11, v10
-; GISEL-NEXT:    v_mul_lo_u32 v11, v13, v15
-; GISEL-NEXT:    v_mul_lo_u32 v14, v0, v10
-; GISEL-NEXT:    v_mul_hi_u32 v15, v13, v15
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v14
-; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v16
+; GISEL-NEXT:    v_mul_hi_u32 v9, v5, v9
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v10
+; GISEL-NEXT:    v_addc_u32_e64 v10, s[4:5], v5, v9, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v8, v8, v0
+; GISEL-NEXT:    v_mul_lo_u32 v11, v7, v10
+; GISEL-NEXT:    v_mul_hi_u32 v12, v7, v0
+; GISEL-NEXT:    v_mul_lo_u32 v7, v7, v0
+; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v9
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v11
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v12
+; GISEL-NEXT:    v_mul_lo_u32 v11, v10, v7
+; GISEL-NEXT:    v_mul_lo_u32 v12, v0, v8
+; GISEL-NEXT:    v_mul_hi_u32 v9, v0, v7
+; GISEL-NEXT:    v_mul_lo_u32 v16, v10, v8
+; GISEL-NEXT:    v_mul_hi_u32 v7, v10, v7
 ; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v9
+; GISEL-NEXT:    v_mul_hi_u32 v11, v0, v8
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v12, v9
+; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v16, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v11
 ; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; GISEL-NEXT:    v_mul_lo_u32 v12, v13, v10
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v14, v11
-; GISEL-NEXT:    v_mul_hi_u32 v14, v0, v10
-; GISEL-NEXT:    v_mul_hi_u32 v10, v13, v10
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v15
-; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v14
-; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v14, s[4:5], v15, v14
 ; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v12, v11
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v14, v12
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v12
-; GISEL-NEXT:    v_addc_u32_e32 v1, vcc, v1, v10, vcc
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v0, v11
-; GISEL-NEXT:    v_addc_u32_e32 v11, vcc, 0, v1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v12, v2, v10
-; GISEL-NEXT:    v_mul_lo_u32 v13, v3, v11
-; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v4, v9
-; GISEL-NEXT:    v_mul_hi_u32 v4, v3, v10
-; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v5, v9, vcc
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v12, v13
-; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v5, v2, v11
-; GISEL-NEXT:    v_mul_hi_u32 v10, v2, v10
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v9, v4
-; GISEL-NEXT:    v_mul_hi_u32 v9, v3, v11
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v10
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v9
+; GISEL-NEXT:    v_mul_hi_u32 v8, v10, v8
+; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v9
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
+; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v8, vcc
+; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v7
+; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v14
+; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v14
+; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v7, v3, v0
+; GISEL-NEXT:    v_mul_lo_u32 v8, v2, v5
+; GISEL-NEXT:    v_mul_hi_u32 v9, v2, v0
+; GISEL-NEXT:    v_mul_lo_u32 v10, v3, v5
+; GISEL-NEXT:    v_mul_hi_u32 v0, v3, v0
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; GISEL-NEXT:    v_mul_hi_u32 v9, v2, v5
+; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v10, v0
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v9
 ; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
-; GISEL-NEXT:    v_mul_hi_u32 v10, v2, v11
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v9, v5
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v10, v5
-; GISEL-NEXT:    v_mul_lo_u32 v9, v6, v4
-; GISEL-NEXT:    v_mul_lo_u32 v5, v7, v5
-; GISEL-NEXT:    v_mul_lo_u32 v10, v7, v4
-; GISEL-NEXT:    v_mul_hi_u32 v4, v7, v4
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v9, v5
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GISEL-NEXT:    v_sub_i32_e32 v3, vcc, v3, v10
-; GISEL-NEXT:    v_subb_u32_e64 v5, s[4:5], v2, v4, vcc
-; GISEL-NEXT:    v_sub_i32_e64 v2, s[4:5], v2, v4
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
+; GISEL-NEXT:    v_mul_hi_u32 v5, v3, v5
+; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; GISEL-NEXT:    v_mul_lo_u32 v8, v6, v0
+; GISEL-NEXT:    v_mul_lo_u32 v5, v13, v5
+; GISEL-NEXT:    v_mul_hi_u32 v9, v13, v0
+; GISEL-NEXT:    v_xor_b32_e32 v1, v1, v15
+; GISEL-NEXT:    v_mul_lo_u32 v7, v13, v0
+; GISEL-NEXT:    v_xor_b32_e32 v4, v4, v15
+; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v1, v15
+; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v4, v15, vcc
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v8, v5
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v9
+; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v7
+; GISEL-NEXT:    v_subb_u32_e64 v5, s[4:5], v3, v4, vcc
+; GISEL-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v4
 ; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v5, v6
 ; GISEL-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v3, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v2, v13
+; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
 ; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v5, v6
-; GISEL-NEXT:    v_subb_u32_e32 v2, vcc, v2, v6, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v4, v4, v9, s[4:5]
-; GISEL-NEXT:    v_sub_i32_e32 v9, vcc, v3, v7
-; GISEL-NEXT:    v_subbrev_u32_e64 v10, s[4:5], 0, v2, vcc
-; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v10, v6
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v9, v7
-; GISEL-NEXT:    v_subb_u32_e32 v2, vcc, v2, v6, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v10, v6
-; GISEL-NEXT:    v_sub_i32_e32 v6, vcc, v9, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, v11, v12, s[4:5]
-; GISEL-NEXT:    v_subbrev_u32_e32 v2, vcc, 0, v2, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11
-; GISEL-NEXT:    v_cndmask_b32_e32 v6, v9, v6, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v2, v10, v2, vcc
+; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v6, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v4, v4, v7, s[4:5]
+; GISEL-NEXT:    v_sub_i32_e32 v7, vcc, v2, v13
+; GISEL-NEXT:    v_subbrev_u32_e64 v8, s[4:5], 0, v3, vcc
+; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v8, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v13
+; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v6, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v8, v6
+; GISEL-NEXT:    v_sub_i32_e32 v6, vcc, v7, v13
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, v9, v10, s[4:5]
+; GISEL-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v9
+; GISEL-NEXT:    v_cndmask_b32_e32 v6, v7, v6, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v3, v8, v3, vcc
 ; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
-; GISEL-NEXT:    v_cndmask_b32_e32 v3, v3, v6, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc
-; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v8
-; GISEL-NEXT:    v_xor_b32_e32 v4, v2, v8
-; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v3, v8
-; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v4, v8, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc
+; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v14
+; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v14
+; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v14
+; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v14, vcc
 ; GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; CGP-LABEL: v_srem_v2i64_pow2_shl_denom:
@@ -2965,139 +2965,139 @@
 ; CGP-NEXT:    v_xor_b32_e32 v0, v4, v0
 ; CGP-NEXT:    v_cvt_f32_u32_e32 v4, v1
 ; CGP-NEXT:    v_cvt_f32_u32_e32 v6, v0
-; CGP-NEXT:    v_ashrrev_i32_e32 v11, 31, v7
+; CGP-NEXT:    v_sub_i32_e32 v11, vcc, 0, v1
+; CGP-NEXT:    v_subb_u32_e32 v12, vcc, 0, v0, vcc
+; CGP-NEXT:    v_ashrrev_i32_e32 v17, 31, v7
 ; CGP-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v6
 ; CGP-NEXT:    v_rcp_iflag_f32_e32 v4, v4
-; CGP-NEXT:    v_add_i32_e32 v6, vcc, v5, v11
-; CGP-NEXT:    v_addc_u32_e32 v7, vcc, v7, v11, vcc
-; CGP-NEXT:    v_sub_i32_e32 v13, vcc, 0, v1
 ; CGP-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
-; CGP-NEXT:    v_mul_f32_e32 v12, 0x2f800000, v4
-; CGP-NEXT:    v_trunc_f32_e32 v12, v12
-; CGP-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v12
+; CGP-NEXT:    v_mul_f32_e32 v6, 0x2f800000, v4
+; CGP-NEXT:    v_trunc_f32_e32 v6, v6
+; CGP-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v6
 ; CGP-NEXT:    v_cvt_u32_f32_e32 v4, v4
-; CGP-NEXT:    v_cvt_u32_f32_e32 v12, v12
-; CGP-NEXT:    v_subb_u32_e32 v14, vcc, 0, v0, vcc
-; CGP-NEXT:    v_xor_b32_e32 v6, v6, v11
-; CGP-NEXT:    v_mul_lo_u32 v15, v14, v4
-; CGP-NEXT:    v_mul_lo_u32 v16, v13, v12
-; CGP-NEXT:    v_mul_hi_u32 v18, v13, v4
-; CGP-NEXT:    v_mul_lo_u32 v17, v13, v4
-; CGP-NEXT:    v_xor_b32_e32 v7, v7, v11
-; CGP-NEXT:    v_add_i32_e32 v15, vcc, v15, v16
-; CGP-NEXT:    v_add_i32_e32 v15, vcc, v15, v18
-; CGP-NEXT:    v_mul_lo_u32 v16, v12, v17
-; CGP-NEXT:    v_mul_lo_u32 v18, v4, v15
-; CGP-NEXT:    v_mul_hi_u32 v19, v4, v17
-; CGP-NEXT:    v_mul_hi_u32 v17, v12, v17
-; CGP-NEXT:    v_add_i32_e32 v16, vcc, v16, v18
-; CGP-NEXT:    v_cndmask_b32_e64 v18, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v16, vcc, v16, v19
+; CGP-NEXT:    v_cvt_u32_f32_e32 v6, v6
+; CGP-NEXT:    v_mul_lo_u32 v14, v12, v4
+; CGP-NEXT:    v_mul_lo_u32 v13, v11, v6
+; CGP-NEXT:    v_mul_hi_u32 v16, v11, v4
+; CGP-NEXT:    v_mul_lo_u32 v15, v11, v4
+; CGP-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
+; CGP-NEXT:    v_add_i32_e32 v13, vcc, v13, v16
+; CGP-NEXT:    v_mul_lo_u32 v14, v6, v15
+; CGP-NEXT:    v_mul_lo_u32 v16, v4, v13
+; CGP-NEXT:    v_mul_hi_u32 v19, v4, v15
+; CGP-NEXT:    v_add_i32_e32 v18, vcc, v5, v17
+; CGP-NEXT:    v_addc_u32_e32 v7, vcc, v7, v17, vcc
+; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v16
+; CGP-NEXT:    v_mul_lo_u32 v20, v6, v13
+; CGP-NEXT:    v_mul_hi_u32 v15, v6, v15
 ; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v19, v12, v15
-; CGP-NEXT:    v_add_i32_e32 v16, vcc, v18, v16
-; CGP-NEXT:    v_mul_hi_u32 v18, v4, v15
-; CGP-NEXT:    v_mul_hi_u32 v15, v12, v15
-; CGP-NEXT:    v_add_i32_e32 v17, vcc, v19, v17
+; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v19
+; CGP-NEXT:    v_mul_hi_u32 v19, v4, v13
+; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v14, vcc, v16, v14
+; CGP-NEXT:    v_add_i32_e32 v15, vcc, v20, v15
+; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v15, vcc, v15, v19
 ; CGP-NEXT:    v_cndmask_b32_e64 v19, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v17, vcc, v17, v18
-; CGP-NEXT:    v_cndmask_b32_e64 v18, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v18, vcc, v19, v18
-; CGP-NEXT:    v_add_i32_e32 v16, vcc, v17, v16
-; CGP-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v17, vcc, v18, v17
-; CGP-NEXT:    v_add_i32_e32 v15, vcc, v15, v17
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v16
-; CGP-NEXT:    v_addc_u32_e64 v16, s[4:5], v12, v15, vcc
-; CGP-NEXT:    v_mul_lo_u32 v14, v14, v4
-; CGP-NEXT:    v_mul_lo_u32 v17, v13, v16
-; CGP-NEXT:    v_mul_lo_u32 v18, v13, v4
-; CGP-NEXT:    v_mul_hi_u32 v13, v13, v4
+; CGP-NEXT:    v_add_i32_e32 v16, vcc, v16, v19
+; CGP-NEXT:    v_mul_hi_u32 v13, v6, v13
+; CGP-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
+; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v15, vcc, v16, v15
+; CGP-NEXT:    v_add_i32_e32 v13, vcc, v13, v15
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v14
+; CGP-NEXT:    v_addc_u32_e64 v14, s[4:5], v6, v13, vcc
+; CGP-NEXT:    v_mul_lo_u32 v12, v12, v4
+; CGP-NEXT:    v_mul_lo_u32 v15, v11, v14
+; CGP-NEXT:    v_mul_hi_u32 v16, v11, v4
+; CGP-NEXT:    v_mul_lo_u32 v11, v11, v4
+; CGP-NEXT:    v_add_i32_e64 v6, s[4:5], v6, v13
 ; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v15
-; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v14, v17
-; CGP-NEXT:    v_mul_hi_u32 v15, v4, v18
-; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v14, v13
-; CGP-NEXT:    v_mul_lo_u32 v14, v16, v18
-; CGP-NEXT:    v_mul_lo_u32 v17, v4, v13
-; CGP-NEXT:    v_mul_hi_u32 v18, v16, v18
-; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v14, v17
-; CGP-NEXT:    v_cndmask_b32_e64 v17, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v14, v15
-; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; CGP-NEXT:    v_mul_lo_u32 v15, v16, v13
-; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v17, v14
-; CGP-NEXT:    v_mul_hi_u32 v17, v4, v13
-; CGP-NEXT:    v_mul_hi_u32 v13, v16, v13
-; CGP-NEXT:    v_add_i32_e64 v15, s[4:5], v15, v18
-; CGP-NEXT:    v_cndmask_b32_e64 v18, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v15, s[4:5], v15, v17
-; CGP-NEXT:    v_cndmask_b32_e64 v17, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v17, s[4:5], v18, v17
-; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v15, v14
+; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v16
+; CGP-NEXT:    v_mul_lo_u32 v15, v14, v11
+; CGP-NEXT:    v_mul_lo_u32 v16, v4, v12
+; CGP-NEXT:    v_mul_hi_u32 v13, v4, v11
+; CGP-NEXT:    v_mul_lo_u32 v19, v14, v12
+; CGP-NEXT:    v_mul_hi_u32 v11, v14, v11
+; CGP-NEXT:    v_add_i32_e64 v15, s[4:5], v15, v16
+; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v15, v13
+; CGP-NEXT:    v_mul_hi_u32 v15, v4, v12
+; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v16, v13
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v19, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v15
 ; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v15, s[4:5], v17, v15
-; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v15
-; CGP-NEXT:    v_addc_u32_e32 v12, vcc, v12, v13, vcc
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v14
-; CGP-NEXT:    v_addc_u32_e32 v12, vcc, 0, v12, vcc
-; CGP-NEXT:    v_mul_lo_u32 v13, v7, v4
-; CGP-NEXT:    v_mul_lo_u32 v14, v6, v12
-; CGP-NEXT:    v_mul_hi_u32 v15, v6, v4
+; CGP-NEXT:    v_add_i32_e64 v15, s[4:5], v16, v15
+; CGP-NEXT:    v_mul_hi_u32 v12, v14, v12
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v13
+; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v15, v13
+; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v13
+; CGP-NEXT:    v_addc_u32_e32 v6, vcc, v6, v12, vcc
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v11
+; CGP-NEXT:    v_xor_b32_e32 v18, v18, v17
+; CGP-NEXT:    v_xor_b32_e32 v7, v7, v17
+; CGP-NEXT:    v_addc_u32_e32 v6, vcc, 0, v6, vcc
+; CGP-NEXT:    v_mul_lo_u32 v11, v7, v4
+; CGP-NEXT:    v_mul_lo_u32 v12, v18, v6
+; CGP-NEXT:    v_mul_hi_u32 v13, v18, v4
+; CGP-NEXT:    v_mul_lo_u32 v14, v7, v6
 ; CGP-NEXT:    v_mul_hi_u32 v4, v7, v4
-; CGP-NEXT:    v_add_i32_e32 v13, vcc, v13, v14
-; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v13, vcc, v13, v15
-; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v15, v7, v12
-; CGP-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
-; CGP-NEXT:    v_mul_hi_u32 v14, v6, v12
-; CGP-NEXT:    v_mul_hi_u32 v12, v7, v12
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v15, v4
-; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v14
-; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
+; CGP-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
+; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v11, vcc, v11, v13
+; CGP-NEXT:    v_mul_hi_u32 v13, v18, v6
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v14, v4
+; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
 ; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v13
 ; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
 ; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
-; CGP-NEXT:    v_mul_lo_u32 v13, v0, v4
-; CGP-NEXT:    v_mul_lo_u32 v12, v1, v12
-; CGP-NEXT:    v_mul_lo_u32 v14, v1, v4
-; CGP-NEXT:    v_mul_hi_u32 v4, v1, v4
-; CGP-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v12, v4
-; CGP-NEXT:    v_sub_i32_e32 v6, vcc, v6, v14
-; CGP-NEXT:    v_subb_u32_e64 v12, s[4:5], v7, v4, vcc
-; CGP-NEXT:    v_sub_i32_e64 v4, s[4:5], v7, v4
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v12, v0
+; CGP-NEXT:    v_mul_hi_u32 v6, v7, v6
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v11
+; CGP-NEXT:    v_mul_lo_u32 v11, v0, v4
+; CGP-NEXT:    v_mul_lo_u32 v6, v1, v6
+; CGP-NEXT:    v_mul_hi_u32 v12, v1, v4
+; CGP-NEXT:    v_mul_lo_u32 v4, v1, v4
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v11, v6
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v12
+; CGP-NEXT:    v_sub_i32_e32 v4, vcc, v18, v4
+; CGP-NEXT:    v_subb_u32_e64 v11, s[4:5], v7, v6, vcc
+; CGP-NEXT:    v_sub_i32_e64 v6, s[4:5], v7, v6
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v11, v0
 ; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v6, v1
-; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], v12, v0
-; CGP-NEXT:    v_subb_u32_e32 v4, vcc, v4, v0, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v7, v7, v13, s[4:5]
-; CGP-NEXT:    v_sub_i32_e32 v13, vcc, v6, v1
-; CGP-NEXT:    v_subbrev_u32_e64 v14, s[4:5], 0, v4, vcc
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v14, v0
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v4, v1
+; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], v11, v0
+; CGP-NEXT:    v_subb_u32_e32 v6, vcc, v6, v0, vcc
+; CGP-NEXT:    v_cndmask_b32_e64 v7, v7, v12, s[4:5]
+; CGP-NEXT:    v_sub_i32_e32 v12, vcc, v4, v1
+; CGP-NEXT:    v_subbrev_u32_e64 v13, s[4:5], 0, v6, vcc
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v13, v0
+; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v12, v1
 ; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v13, v1
-; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], v14, v0
-; CGP-NEXT:    v_subb_u32_e32 v0, vcc, v4, v0, vcc
-; CGP-NEXT:    v_sub_i32_e32 v1, vcc, v13, v1
-; CGP-NEXT:    v_cndmask_b32_e64 v15, v15, v16, s[4:5]
+; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], v13, v0
+; CGP-NEXT:    v_subb_u32_e32 v0, vcc, v6, v0, vcc
+; CGP-NEXT:    v_sub_i32_e32 v1, vcc, v12, v1
+; CGP-NEXT:    v_cndmask_b32_e64 v14, v14, v15, s[4:5]
 ; CGP-NEXT:    v_subbrev_u32_e32 v0, vcc, 0, v0, vcc
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v15
-; CGP-NEXT:    v_cndmask_b32_e32 v1, v13, v1, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v0, v14, v0, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v14
+; CGP-NEXT:    v_cndmask_b32_e32 v1, v12, v1, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v0, v13, v0, vcc
 ; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
-; CGP-NEXT:    v_cndmask_b32_e32 v1, v6, v1, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v0, v12, v0, vcc
-; CGP-NEXT:    v_xor_b32_e32 v1, v1, v11
-; CGP-NEXT:    v_xor_b32_e32 v4, v0, v11
-; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v1, v11
-; CGP-NEXT:    v_subb_u32_e32 v1, vcc, v4, v11, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v0, v11, v0, vcc
+; CGP-NEXT:    v_xor_b32_e32 v1, v1, v17
+; CGP-NEXT:    v_xor_b32_e32 v4, v0, v17
+; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v1, v17
+; CGP-NEXT:    v_subb_u32_e32 v1, vcc, v4, v17, vcc
 ; CGP-NEXT:  BB8_2: ; %Flow2
 ; CGP-NEXT:    s_or_saveexec_b64 s[4:5], s[6:7]
 ; CGP-NEXT:    s_xor_b64 exec, exec, s[4:5]
@@ -3138,139 +3138,139 @@
 ; CGP-NEXT:    v_xor_b32_e32 v4, v6, v4
 ; CGP-NEXT:    v_cvt_f32_u32_e32 v6, v5
 ; CGP-NEXT:    v_cvt_f32_u32_e32 v7, v4
-; CGP-NEXT:    v_ashrrev_i32_e32 v9, 31, v3
+; CGP-NEXT:    v_sub_i32_e32 v9, vcc, 0, v5
+; CGP-NEXT:    v_subb_u32_e32 v10, vcc, 0, v4, vcc
+; CGP-NEXT:    v_ashrrev_i32_e32 v15, 31, v3
 ; CGP-NEXT:    v_mac_f32_e32 v6, 0x4f800000, v7
 ; CGP-NEXT:    v_rcp_iflag_f32_e32 v6, v6
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v2, v9
-; CGP-NEXT:    v_addc_u32_e32 v3, vcc, v3, v9, vcc
-; CGP-NEXT:    v_sub_i32_e32 v11, vcc, 0, v5
 ; CGP-NEXT:    v_mul_f32_e32 v6, 0x5f7ffffc, v6
-; CGP-NEXT:    v_mul_f32_e32 v10, 0x2f800000, v6
-; CGP-NEXT:    v_trunc_f32_e32 v10, v10
-; CGP-NEXT:    v_mac_f32_e32 v6, 0xcf800000, v10
+; CGP-NEXT:    v_mul_f32_e32 v7, 0x2f800000, v6
+; CGP-NEXT:    v_trunc_f32_e32 v7, v7
+; CGP-NEXT:    v_mac_f32_e32 v6, 0xcf800000, v7
 ; CGP-NEXT:    v_cvt_u32_f32_e32 v6, v6
-; CGP-NEXT:    v_cvt_u32_f32_e32 v10, v10
-; CGP-NEXT:    v_subb_u32_e32 v12, vcc, 0, v4, vcc
-; CGP-NEXT:    v_xor_b32_e32 v7, v7, v9
-; CGP-NEXT:    v_mul_lo_u32 v13, v12, v6
-; CGP-NEXT:    v_mul_lo_u32 v14, v11, v10
-; CGP-NEXT:    v_mul_hi_u32 v16, v11, v6
-; CGP-NEXT:    v_mul_lo_u32 v15, v11, v6
-; CGP-NEXT:    v_xor_b32_e32 v3, v3, v9
-; CGP-NEXT:    v_add_i32_e32 v13, vcc, v13, v14
-; CGP-NEXT:    v_add_i32_e32 v13, vcc, v13, v16
-; CGP-NEXT:    v_mul_lo_u32 v14, v10, v15
-; CGP-NEXT:    v_mul_lo_u32 v16, v6, v13
-; CGP-NEXT:    v_mul_hi_u32 v17, v6, v15
-; CGP-NEXT:    v_mul_hi_u32 v15, v10, v15
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v16
-; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v17
+; CGP-NEXT:    v_cvt_u32_f32_e32 v7, v7
+; CGP-NEXT:    v_mul_lo_u32 v12, v10, v6
+; CGP-NEXT:    v_mul_lo_u32 v11, v9, v7
+; CGP-NEXT:    v_mul_hi_u32 v14, v9, v6
+; CGP-NEXT:    v_mul_lo_u32 v13, v9, v6
+; CGP-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
+; CGP-NEXT:    v_add_i32_e32 v11, vcc, v11, v14
+; CGP-NEXT:    v_mul_lo_u32 v12, v7, v13
+; CGP-NEXT:    v_mul_lo_u32 v14, v6, v11
+; CGP-NEXT:    v_mul_hi_u32 v17, v6, v13
+; CGP-NEXT:    v_add_i32_e32 v16, vcc, v2, v15
+; CGP-NEXT:    v_addc_u32_e32 v3, vcc, v3, v15, vcc
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v14
+; CGP-NEXT:    v_mul_lo_u32 v18, v7, v11
+; CGP-NEXT:    v_mul_hi_u32 v13, v7, v13
 ; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v17, v10, v13
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v16, v14
-; CGP-NEXT:    v_mul_hi_u32 v16, v6, v13
-; CGP-NEXT:    v_mul_hi_u32 v13, v10, v13
-; CGP-NEXT:    v_add_i32_e32 v15, vcc, v17, v15
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v17
+; CGP-NEXT:    v_mul_hi_u32 v17, v6, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v14, v12
+; CGP-NEXT:    v_add_i32_e32 v13, vcc, v18, v13
+; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v13, vcc, v13, v17
 ; CGP-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v15, vcc, v15, v16
-; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v16, vcc, v17, v16
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
-; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v15, vcc, v16, v15
-; CGP-NEXT:    v_add_i32_e32 v13, vcc, v13, v15
-; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v14
-; CGP-NEXT:    v_addc_u32_e64 v14, s[4:5], v10, v13, vcc
-; CGP-NEXT:    v_mul_lo_u32 v12, v12, v6
-; CGP-NEXT:    v_mul_lo_u32 v15, v11, v14
-; CGP-NEXT:    v_mul_lo_u32 v16, v11, v6
-; CGP-NEXT:    v_mul_hi_u32 v11, v11, v6
+; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v17
+; CGP-NEXT:    v_mul_hi_u32 v11, v7, v11
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
+; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
+; CGP-NEXT:    v_add_i32_e32 v11, vcc, v11, v13
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v12
+; CGP-NEXT:    v_addc_u32_e64 v12, s[4:5], v7, v11, vcc
+; CGP-NEXT:    v_mul_lo_u32 v10, v10, v6
+; CGP-NEXT:    v_mul_lo_u32 v13, v9, v12
+; CGP-NEXT:    v_mul_hi_u32 v14, v9, v6
+; CGP-NEXT:    v_mul_lo_u32 v9, v9, v6
+; CGP-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v11
 ; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v13
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v15
-; CGP-NEXT:    v_mul_hi_u32 v13, v6, v16
-; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v12, v11
-; CGP-NEXT:    v_mul_lo_u32 v12, v14, v16
-; CGP-NEXT:    v_mul_lo_u32 v15, v6, v11
-; CGP-NEXT:    v_mul_hi_u32 v16, v14, v16
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v15
-; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v13
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; CGP-NEXT:    v_mul_lo_u32 v13, v14, v11
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v15, v12
-; CGP-NEXT:    v_mul_hi_u32 v15, v6, v11
-; CGP-NEXT:    v_mul_hi_u32 v11, v14, v11
-; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v16
-; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v15
-; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v15, s[4:5], v16, v15
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v13, v12
+; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v14
+; CGP-NEXT:    v_mul_lo_u32 v13, v12, v9
+; CGP-NEXT:    v_mul_lo_u32 v14, v6, v10
+; CGP-NEXT:    v_mul_hi_u32 v11, v6, v9
+; CGP-NEXT:    v_mul_lo_u32 v17, v12, v10
+; CGP-NEXT:    v_mul_hi_u32 v9, v12, v9
+; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v14
+; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v13, v11
+; CGP-NEXT:    v_mul_hi_u32 v13, v6, v10
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v14, v11
+; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v17, v9
+; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v13
 ; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v15, v13
-; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v13
-; CGP-NEXT:    v_addc_u32_e32 v10, vcc, v10, v11, vcc
-; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v12
-; CGP-NEXT:    v_addc_u32_e32 v10, vcc, 0, v10, vcc
-; CGP-NEXT:    v_mul_lo_u32 v11, v3, v6
-; CGP-NEXT:    v_mul_lo_u32 v12, v7, v10
-; CGP-NEXT:    v_mul_hi_u32 v13, v7, v6
+; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v14, v13
+; CGP-NEXT:    v_mul_hi_u32 v10, v12, v10
+; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v13, v11
+; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v11
+; CGP-NEXT:    v_addc_u32_e32 v7, vcc, v7, v10, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
+; CGP-NEXT:    v_xor_b32_e32 v16, v16, v15
+; CGP-NEXT:    v_xor_b32_e32 v3, v3, v15
+; CGP-NEXT:    v_addc_u32_e32 v7, vcc, 0, v7, vcc
+; CGP-NEXT:    v_mul_lo_u32 v9, v3, v6
+; CGP-NEXT:    v_mul_lo_u32 v10, v16, v7
+; CGP-NEXT:    v_mul_hi_u32 v11, v16, v6
+; CGP-NEXT:    v_mul_lo_u32 v12, v3, v7
 ; CGP-NEXT:    v_mul_hi_u32 v6, v3, v6
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v11, v13
-; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v13, v3, v10
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
-; CGP-NEXT:    v_mul_hi_u32 v12, v7, v10
-; CGP-NEXT:    v_mul_hi_u32 v10, v3, v10
-; CGP-NEXT:    v_add_i32_e32 v6, vcc, v13, v6
-; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v12
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; CGP-NEXT:    v_mul_hi_u32 v11, v16, v7
+; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v12, v6
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
 ; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v11
 ; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
 ; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
-; CGP-NEXT:    v_mul_lo_u32 v11, v4, v6
-; CGP-NEXT:    v_mul_lo_u32 v10, v5, v10
-; CGP-NEXT:    v_mul_lo_u32 v12, v5, v6
-; CGP-NEXT:    v_mul_hi_u32 v6, v5, v6
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; CGP-NEXT:    v_add_i32_e32 v6, vcc, v10, v6
-; CGP-NEXT:    v_sub_i32_e32 v7, vcc, v7, v12
-; CGP-NEXT:    v_subb_u32_e64 v10, s[4:5], v3, v6, vcc
-; CGP-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v6
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v10, v4
-; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v5
-; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], v10, v4
+; CGP-NEXT:    v_mul_hi_u32 v7, v3, v7
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
+; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; CGP-NEXT:    v_mul_lo_u32 v9, v4, v6
+; CGP-NEXT:    v_mul_lo_u32 v7, v5, v7
+; CGP-NEXT:    v_mul_hi_u32 v10, v5, v6
+; CGP-NEXT:    v_mul_lo_u32 v6, v5, v6
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v9, v7
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
+; CGP-NEXT:    v_sub_i32_e32 v6, vcc, v16, v6
+; CGP-NEXT:    v_subb_u32_e64 v9, s[4:5], v3, v7, vcc
+; CGP-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v7
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v9, v4
+; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v6, v5
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], v9, v4
 ; CGP-NEXT:    v_subb_u32_e32 v3, vcc, v3, v4, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v6, v6, v11, s[4:5]
-; CGP-NEXT:    v_sub_i32_e32 v11, vcc, v7, v5
-; CGP-NEXT:    v_subbrev_u32_e64 v12, s[4:5], 0, v3, vcc
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v12, v4
-; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v11, v5
+; CGP-NEXT:    v_cndmask_b32_e64 v7, v7, v10, s[4:5]
+; CGP-NEXT:    v_sub_i32_e32 v10, vcc, v6, v5
+; CGP-NEXT:    v_subbrev_u32_e64 v11, s[4:5], 0, v3, vcc
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v11, v4
+; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v10, v5
 ; CGP-NEXT:    v_subb_u32_e32 v3, vcc, v3, v4, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], v12, v4
-; CGP-NEXT:    v_sub_i32_e32 v4, vcc, v11, v5
-; CGP-NEXT:    v_cndmask_b32_e64 v13, v13, v14, s[4:5]
+; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], v11, v4
+; CGP-NEXT:    v_sub_i32_e32 v4, vcc, v10, v5
+; CGP-NEXT:    v_cndmask_b32_e64 v12, v12, v13, s[4:5]
 ; CGP-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v13
-; CGP-NEXT:    v_cndmask_b32_e32 v4, v11, v4, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v3, v12, v3, vcc
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
-; CGP-NEXT:    v_cndmask_b32_e32 v4, v7, v4, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v3, v10, v3, vcc
-; CGP-NEXT:    v_xor_b32_e32 v4, v4, v9
-; CGP-NEXT:    v_xor_b32_e32 v3, v3, v9
-; CGP-NEXT:    v_sub_i32_e32 v4, vcc, v4, v9
-; CGP-NEXT:    v_subb_u32_e32 v5, vcc, v3, v9, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v12
+; CGP-NEXT:    v_cndmask_b32_e32 v4, v10, v4, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v3, v11, v3, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
+; CGP-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v3, v9, v3, vcc
+; CGP-NEXT:    v_xor_b32_e32 v4, v4, v15
+; CGP-NEXT:    v_xor_b32_e32 v3, v3, v15
+; CGP-NEXT:    v_sub_i32_e32 v4, vcc, v4, v15
+; CGP-NEXT:    v_subb_u32_e32 v5, vcc, v3, v15, vcc
 ; CGP-NEXT:  BB8_6: ; %Flow
 ; CGP-NEXT:    s_or_saveexec_b64 s[4:5], s[6:7]
 ; CGP-NEXT:    s_xor_b64 exec, exec, s[4:5]
@@ -3342,11 +3342,11 @@
 ; CGP-NEXT:    v_rcp_f32_e32 v4, v2
 ; CGP-NEXT:    v_mul_f32_e32 v4, v3, v4
 ; CGP-NEXT:    v_trunc_f32_e32 v4, v4
+; CGP-NEXT:    v_cvt_i32_f32_e32 v5, v4
 ; CGP-NEXT:    v_mad_f32 v3, -v4, v2, v3
-; CGP-NEXT:    v_cvt_i32_f32_e32 v4, v4
 ; CGP-NEXT:    v_cmp_ge_f32_e64 s[4:5], |v3|, |v2|
 ; CGP-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
+; CGP-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
 ; CGP-NEXT:    v_mul_lo_u32 v1, v2, v1
 ; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
 ; CGP-NEXT:    v_bfe_i32 v0, v0, 0, 25
@@ -3383,29 +3383,27 @@
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v5, v5
 ; GISEL-NEXT:    v_mul_lo_u32 v9, v8, v4
 ; GISEL-NEXT:    v_mul_lo_u32 v10, v7, v5
-; GISEL-NEXT:    v_mul_hi_u32 v12, v7, v4
-; GISEL-NEXT:    v_mul_lo_u32 v11, v7, v4
+; GISEL-NEXT:    v_mul_hi_u32 v11, v7, v4
+; GISEL-NEXT:    v_mul_lo_u32 v12, v7, v4
 ; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
-; GISEL-NEXT:    v_mul_lo_u32 v10, v5, v11
-; GISEL-NEXT:    v_mul_lo_u32 v12, v4, v9
-; GISEL-NEXT:    v_mul_hi_u32 v14, v4, v11
-; GISEL-NEXT:    v_add_i32_e32 v0, vcc, 0, v0
-; GISEL-NEXT:    v_addc_u32_e64 v13, s[4:5], 0, 0, vcc
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v14
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; GISEL-NEXT:    v_mul_lo_u32 v10, v5, v12
+; GISEL-NEXT:    v_mul_lo_u32 v11, v4, v9
+; GISEL-NEXT:    v_mul_hi_u32 v13, v4, v12
 ; GISEL-NEXT:    v_mul_lo_u32 v14, v5, v9
-; GISEL-NEXT:    v_mul_hi_u32 v11, v5, v11
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v12, v10
-; GISEL-NEXT:    v_mul_hi_u32 v12, v4, v9
-; GISEL-NEXT:    v_mul_hi_u32 v9, v5, v9
-; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v14, v11
-; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
+; GISEL-NEXT:    v_mul_hi_u32 v12, v5, v12
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
+; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v13
+; GISEL-NEXT:    v_mul_hi_u32 v13, v4, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v14, v12
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v14, v12
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v13
+; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
+; GISEL-NEXT:    v_mul_hi_u32 v9, v5, v9
 ; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
 ; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
@@ -3414,221 +3412,223 @@
 ; GISEL-NEXT:    v_addc_u32_e64 v10, s[4:5], v5, v9, vcc
 ; GISEL-NEXT:    v_mul_lo_u32 v8, v8, v4
 ; GISEL-NEXT:    v_mul_lo_u32 v11, v7, v10
-; GISEL-NEXT:    v_mul_lo_u32 v12, v7, v4
-; GISEL-NEXT:    v_mul_hi_u32 v7, v7, v4
-; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v9
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v11
-; GISEL-NEXT:    v_mul_hi_u32 v9, v4, v12
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v8, v7
-; GISEL-NEXT:    v_mul_lo_u32 v8, v10, v12
-; GISEL-NEXT:    v_mul_lo_u32 v11, v4, v7
-; GISEL-NEXT:    v_mul_hi_u32 v12, v10, v12
+; GISEL-NEXT:    v_mul_hi_u32 v12, v7, v4
+; GISEL-NEXT:    v_mul_lo_u32 v7, v7, v4
 ; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v11
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
-; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
-; GISEL-NEXT:    v_mul_lo_u32 v9, v10, v7
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v11, v8
-; GISEL-NEXT:    v_mul_hi_u32 v11, v4, v7
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v12
+; GISEL-NEXT:    v_add_i32_e64 v0, s[4:5], 0, v0
+; GISEL-NEXT:    v_mul_lo_u32 v11, v10, v7
+; GISEL-NEXT:    v_mul_lo_u32 v12, v4, v8
+; GISEL-NEXT:    v_addc_u32_e64 v13, s[4:5], 0, 0, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v9
+; GISEL-NEXT:    v_mul_hi_u32 v9, v4, v7
+; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
+; GISEL-NEXT:    v_mul_lo_u32 v14, v10, v8
 ; GISEL-NEXT:    v_mul_hi_u32 v7, v10, v7
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v12
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v11
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v9
+; GISEL-NEXT:    v_mul_hi_u32 v11, v4, v8
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v12, v9
+; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v14, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v11
 ; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
 ; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v12, v11
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v9, v8
+; GISEL-NEXT:    v_mul_hi_u32 v8, v10, v8
+; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v9
 ; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
 ; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v9
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v9
-; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v7, vcc
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
+; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v8, vcc
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
 ; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
 ; GISEL-NEXT:    v_mul_lo_u32 v7, v13, v4
 ; GISEL-NEXT:    v_mul_lo_u32 v8, v0, v5
 ; GISEL-NEXT:    v_mul_hi_u32 v9, v0, v4
+; GISEL-NEXT:    v_mul_lo_u32 v10, v13, v5
 ; GISEL-NEXT:    v_mul_hi_u32 v4, v13, v4
 ; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; GISEL-NEXT:    v_mul_hi_u32 v9, v0, v5
 ; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v9, v13, v5
 ; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; GISEL-NEXT:    v_mul_hi_u32 v8, v0, v5
-; GISEL-NEXT:    v_mul_hi_u32 v5, v13, v5
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v9, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v10, v4
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
+; GISEL-NEXT:    v_mul_hi_u32 v5, v13, v5
 ; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
 ; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
 ; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
 ; GISEL-NEXT:    v_mul_lo_u32 v7, v3, v4
 ; GISEL-NEXT:    v_mul_lo_u32 v5, v1, v5
-; GISEL-NEXT:    v_mul_lo_u32 v8, v1, v4
-; GISEL-NEXT:    v_mul_hi_u32 v4, v1, v4
+; GISEL-NEXT:    v_mul_hi_u32 v8, v1, v4
+; GISEL-NEXT:    v_mul_lo_u32 v4, v1, v4
 ; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v8
-; GISEL-NEXT:    v_subb_u32_e64 v5, s[4:5], v13, v4, vcc
-; GISEL-NEXT:    v_sub_i32_e64 v4, s[4:5], v13, v4
-; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v5, v3
+; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
+; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
+; GISEL-NEXT:    v_subb_u32_e64 v4, s[4:5], v13, v5, vcc
+; GISEL-NEXT:    v_sub_i32_e64 v5, s[4:5], v13, v5
+; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v4, v3
 ; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
 ; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v0, v1
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v5, v3
-; GISEL-NEXT:    v_subb_u32_e32 v4, vcc, v4, v3, vcc
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v4, v3
+; GISEL-NEXT:    v_subb_u32_e32 v5, vcc, v5, v3, vcc
 ; GISEL-NEXT:    v_cndmask_b32_e64 v7, v7, v8, s[4:5]
 ; GISEL-NEXT:    v_sub_i32_e32 v8, vcc, v0, v1
-; GISEL-NEXT:    v_subbrev_u32_e64 v9, s[4:5], 0, v4, vcc
+; GISEL-NEXT:    v_subbrev_u32_e64 v9, s[4:5], 0, v5, vcc
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], 0, v6
+; GISEL-NEXT:    v_addc_u32_e64 v10, s[4:5], 0, 0, s[4:5]
+; GISEL-NEXT:    v_cvt_f32_u32_e32 v11, v6
+; GISEL-NEXT:    v_cvt_f32_u32_e32 v12, v10
 ; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v9, v3
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, -1, s[4:5]
 ; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v8, v1
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
+; GISEL-NEXT:    v_mac_f32_e32 v11, 0x4f800000, v12
+; GISEL-NEXT:    v_rcp_iflag_f32_e32 v11, v11
+; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, -1, s[4:5]
 ; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v9, v3
-; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v4, v3, vcc
+; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v5, v3, vcc
+; GISEL-NEXT:    v_mul_f32_e32 v5, 0x5f7ffffc, v11
+; GISEL-NEXT:    v_mul_f32_e32 v11, 0x2f800000, v5
+; GISEL-NEXT:    v_trunc_f32_e32 v11, v11
+; GISEL-NEXT:    v_mac_f32_e32 v5, 0xcf800000, v11
+; GISEL-NEXT:    v_cvt_u32_f32_e32 v5, v5
+; GISEL-NEXT:    v_cvt_u32_f32_e32 v11, v11
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, v13, v14, s[4:5]
+; GISEL-NEXT:    v_sub_i32_e32 v13, vcc, 0, v6
+; GISEL-NEXT:    v_subb_u32_e32 v14, vcc, 0, v10, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v16, v14, v5
+; GISEL-NEXT:    v_mul_lo_u32 v17, v13, v11
+; GISEL-NEXT:    v_mul_hi_u32 v18, v13, v5
+; GISEL-NEXT:    v_mul_lo_u32 v15, v13, v5
 ; GISEL-NEXT:    v_sub_i32_e32 v1, vcc, v8, v1
 ; GISEL-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, 0, v6
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, v10, v11, s[4:5]
-; GISEL-NEXT:    v_addc_u32_e64 v6, s[4:5], 0, 0, vcc
-; GISEL-NEXT:    v_cvt_f32_u32_e32 v11, v4
-; GISEL-NEXT:    v_cvt_f32_u32_e32 v12, v6
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
+; GISEL-NEXT:    v_add_i32_e32 v16, vcc, v16, v17
+; GISEL-NEXT:    v_add_i32_e32 v16, vcc, v16, v18
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v12
+; GISEL-NEXT:    v_mul_lo_u32 v17, v11, v15
+; GISEL-NEXT:    v_mul_lo_u32 v18, v5, v16
 ; GISEL-NEXT:    v_cndmask_b32_e32 v1, v8, v1, vcc
+; GISEL-NEXT:    v_mul_hi_u32 v8, v5, v15
+; GISEL-NEXT:    v_mul_hi_u32 v15, v11, v15
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v17, v18
+; GISEL-NEXT:    v_mul_lo_u32 v18, v11, v16
+; GISEL-NEXT:    v_cndmask_b32_e64 v17, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v12, v8
+; GISEL-NEXT:    v_mul_hi_u32 v12, v5, v16
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v17, v8
+; GISEL-NEXT:    v_add_i32_e64 v15, s[4:5], v18, v15
+; GISEL-NEXT:    v_cndmask_b32_e64 v17, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v15, v12
+; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v15, s[4:5], v17, v15
+; GISEL-NEXT:    v_mul_hi_u32 v16, v11, v16
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v12, v8
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v15, v12
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v16, v12
+; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v8
+; GISEL-NEXT:    v_addc_u32_e64 v8, s[6:7], v11, v12, s[4:5]
+; GISEL-NEXT:    v_mul_lo_u32 v14, v14, v5
+; GISEL-NEXT:    v_mul_lo_u32 v15, v13, v8
+; GISEL-NEXT:    v_mul_hi_u32 v16, v13, v5
+; GISEL-NEXT:    v_mul_lo_u32 v13, v13, v5
 ; GISEL-NEXT:    v_cndmask_b32_e32 v3, v9, v3, vcc
-; GISEL-NEXT:    v_mac_f32_e32 v11, 0x4f800000, v12
-; GISEL-NEXT:    v_rcp_iflag_f32_e32 v8, v11
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
-; GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v1, v5, v3, vcc
-; GISEL-NEXT:    v_mul_f32_e32 v3, 0x5f7ffffc, v8
-; GISEL-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v3
-; GISEL-NEXT:    v_trunc_f32_e32 v5, v5
-; GISEL-NEXT:    v_mac_f32_e32 v3, 0xcf800000, v5
-; GISEL-NEXT:    v_cvt_u32_f32_e32 v3, v3
-; GISEL-NEXT:    v_cvt_u32_f32_e32 v5, v5
-; GISEL-NEXT:    v_sub_i32_e32 v7, vcc, 0, v4
-; GISEL-NEXT:    v_subb_u32_e32 v8, vcc, 0, v6, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v9, v8, v3
-; GISEL-NEXT:    v_mul_lo_u32 v10, v7, v5
-; GISEL-NEXT:    v_mul_hi_u32 v12, v7, v3
-; GISEL-NEXT:    v_mul_lo_u32 v11, v7, v3
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
-; GISEL-NEXT:    v_mul_lo_u32 v10, v5, v11
-; GISEL-NEXT:    v_mul_lo_u32 v12, v3, v9
-; GISEL-NEXT:    v_mul_hi_u32 v14, v3, v11
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v14, v15
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v16
 ; GISEL-NEXT:    v_add_i32_e32 v2, vcc, 0, v2
-; GISEL-NEXT:    v_addc_u32_e64 v13, s[4:5], 0, 0, vcc
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
+; GISEL-NEXT:    v_mul_lo_u32 v14, v8, v13
+; GISEL-NEXT:    v_mul_lo_u32 v15, v5, v9
+; GISEL-NEXT:    v_addc_u32_e64 v16, s[6:7], 0, 0, vcc
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
+; GISEL-NEXT:    v_mul_hi_u32 v12, v5, v13
+; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v15
+; GISEL-NEXT:    v_mul_lo_u32 v17, v8, v9
+; GISEL-NEXT:    v_mul_hi_u32 v13, v8, v13
+; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v14, v12
+; GISEL-NEXT:    v_mul_hi_u32 v14, v5, v9
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v14
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v14, v5, v9
-; GISEL-NEXT:    v_mul_hi_u32 v11, v5, v11
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v12, v10
-; GISEL-NEXT:    v_mul_hi_u32 v12, v3, v9
-; GISEL-NEXT:    v_mul_hi_u32 v9, v5, v9
-; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v14, v11
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v15, v12
+; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v17, v13
+; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v14
 ; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
+; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
+; GISEL-NEXT:    v_mul_hi_u32 v8, v8, v9
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v13, v12
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v14, v12
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
-; GISEL-NEXT:    v_add_i32_e32 v3, vcc, v3, v10
-; GISEL-NEXT:    v_addc_u32_e64 v10, s[4:5], v5, v9, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v8, v8, v3
-; GISEL-NEXT:    v_mul_lo_u32 v11, v7, v10
-; GISEL-NEXT:    v_mul_lo_u32 v12, v7, v3
-; GISEL-NEXT:    v_mul_hi_u32 v7, v7, v3
-; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v9
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v11
-; GISEL-NEXT:    v_mul_hi_u32 v9, v3, v12
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v8, v7
-; GISEL-NEXT:    v_mul_lo_u32 v8, v10, v12
-; GISEL-NEXT:    v_mul_lo_u32 v11, v3, v7
-; GISEL-NEXT:    v_mul_hi_u32 v12, v10, v12
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v11
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
-; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
-; GISEL-NEXT:    v_mul_lo_u32 v9, v10, v7
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v11, v8
-; GISEL-NEXT:    v_mul_hi_u32 v11, v3, v7
-; GISEL-NEXT:    v_mul_hi_u32 v7, v10, v7
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v12
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v11
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v12, v11
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v9, v8
-; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v9
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v9
-; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v7, vcc
-; GISEL-NEXT:    v_add_i32_e32 v3, vcc, v3, v8
-; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v7, v13, v3
-; GISEL-NEXT:    v_mul_lo_u32 v8, v2, v5
-; GISEL-NEXT:    v_mul_hi_u32 v9, v2, v3
-; GISEL-NEXT:    v_subrev_i32_e32 v0, vcc, 0, v0
-; GISEL-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v12
+; GISEL-NEXT:    v_addc_u32_e64 v8, vcc, v11, v8, s[4:5]
+; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v9
+; GISEL-NEXT:    v_addc_u32_e32 v8, vcc, 0, v8, vcc
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
+; GISEL-NEXT:    v_mul_lo_u32 v9, v16, v5
+; GISEL-NEXT:    v_mul_lo_u32 v11, v2, v8
+; GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v1, v4, v3, vcc
+; GISEL-NEXT:    v_mul_hi_u32 v3, v2, v5
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v9, v11
+; GISEL-NEXT:    v_mul_lo_u32 v9, v16, v8
+; GISEL-NEXT:    v_mul_hi_u32 v5, v16, v5
 ; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v9, v13, v5
-; GISEL-NEXT:    v_mul_hi_u32 v3, v13, v3
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; GISEL-NEXT:    v_mul_hi_u32 v8, v2, v5
-; GISEL-NEXT:    v_mul_hi_u32 v5, v13, v5
-; GISEL-NEXT:    v_add_i32_e32 v3, vcc, v9, v3
-; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v3, vcc, v3, v8
-; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
-; GISEL-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
+; GISEL-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
+; GISEL-NEXT:    v_mul_hi_u32 v4, v2, v8
+; GISEL-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v3, vcc, v7, v3
+; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v9, v5
 ; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; GISEL-NEXT:    v_mul_lo_u32 v7, v6, v3
-; GISEL-NEXT:    v_mul_lo_u32 v5, v4, v5
-; GISEL-NEXT:    v_mul_lo_u32 v8, v4, v3
-; GISEL-NEXT:    v_mul_hi_u32 v3, v4, v3
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; GISEL-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
-; GISEL-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
-; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v8
-; GISEL-NEXT:    v_subb_u32_e64 v5, s[4:5], v13, v3, vcc
-; GISEL-NEXT:    v_sub_i32_e64 v3, s[4:5], v13, v3
-; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v5, v6
+; GISEL-NEXT:    v_mul_hi_u32 v7, v16, v8
+; GISEL-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
+; GISEL-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
+; GISEL-NEXT:    v_mul_lo_u32 v7, v10, v3
+; GISEL-NEXT:    v_mul_lo_u32 v4, v6, v4
+; GISEL-NEXT:    v_mul_lo_u32 v5, v6, v3
+; GISEL-NEXT:    v_mul_hi_u32 v3, v6, v3
+; GISEL-NEXT:    v_subrev_i32_e32 v0, vcc, 0, v0
+; GISEL-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
+; GISEL-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
+; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v5
+; GISEL-NEXT:    v_subb_u32_e64 v4, s[4:5], v16, v3, vcc
+; GISEL-NEXT:    v_sub_i32_e64 v3, s[4:5], v16, v3
+; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v4, v10
+; GISEL-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v2, v6
 ; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v2, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v5, v6
-; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v6, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, v7, v8, s[4:5]
-; GISEL-NEXT:    v_sub_i32_e32 v8, vcc, v2, v4
-; GISEL-NEXT:    v_subbrev_u32_e64 v9, s[4:5], 0, v3, vcc
-; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v9, v6
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v8, v4
-; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v6, vcc
-; GISEL-NEXT:    v_sub_i32_e32 v4, vcc, v8, v4
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v4, v10
+; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v10, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v5, v5, v7, s[4:5]
+; GISEL-NEXT:    v_sub_i32_e32 v7, vcc, v2, v6
+; GISEL-NEXT:    v_subbrev_u32_e64 v8, s[4:5], 0, v3, vcc
+; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v8, v10
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v6
+; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v10, vcc
+; GISEL-NEXT:    v_sub_i32_e32 v6, vcc, v7, v6
 ; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v9, v6
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, v10, v11, s[4:5]
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v8, v10
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, v9, v11, s[4:5]
 ; GISEL-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
-; GISEL-NEXT:    v_cndmask_b32_e32 v4, v8, v4, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v3, v9, v3, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
-; GISEL-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v9
+; GISEL-NEXT:    v_cndmask_b32_e32 v6, v7, v6, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v3, v8, v3, vcc
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
+; GISEL-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
 ; GISEL-NEXT:    v_subrev_i32_e32 v2, vcc, 0, v2
 ; GISEL-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
 ; GISEL-NEXT:    s_setpc_b64 s[30:31]
@@ -3643,28 +3643,28 @@
 ; CGP-NEXT:    v_cvt_f32_i32_e32 v4, v0
 ; CGP-NEXT:    v_and_b32_e32 v6, s4, v6
 ; CGP-NEXT:    v_rcp_f32_e32 v5, v3
+; CGP-NEXT:    v_cvt_f32_i32_e32 v7, v6
 ; CGP-NEXT:    v_and_b32_e32 v2, s4, v2
+; CGP-NEXT:    v_cvt_f32_i32_e32 v8, v2
 ; CGP-NEXT:    v_mul_f32_e32 v5, v4, v5
 ; CGP-NEXT:    v_trunc_f32_e32 v5, v5
 ; CGP-NEXT:    v_mad_f32 v4, -v5, v3, v4
 ; CGP-NEXT:    v_cvt_i32_f32_e32 v5, v5
+; CGP-NEXT:    v_rcp_f32_e32 v9, v7
 ; CGP-NEXT:    v_cmp_ge_f32_e64 s[4:5], |v4|, |v3|
-; CGP-NEXT:    v_cvt_f32_i32_e32 v4, v6
 ; CGP-NEXT:    v_cndmask_b32_e64 v3, 0, 1, s[4:5]
 ; CGP-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
 ; CGP-NEXT:    v_mul_lo_u32 v1, v3, v1
-; CGP-NEXT:    v_cvt_f32_i32_e32 v3, v2
-; CGP-NEXT:    v_rcp_f32_e32 v5, v4
+; CGP-NEXT:    v_mul_f32_e32 v3, v8, v9
+; CGP-NEXT:    v_trunc_f32_e32 v3, v3
+; CGP-NEXT:    v_cvt_i32_f32_e32 v4, v3
+; CGP-NEXT:    v_mad_f32 v3, -v3, v7, v8
+; CGP-NEXT:    v_cmp_ge_f32_e64 s[4:5], |v3|, |v7|
+; CGP-NEXT:    v_cndmask_b32_e64 v3, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
+; CGP-NEXT:    v_mul_lo_u32 v3, v3, v6
 ; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
 ; CGP-NEXT:    v_bfe_i32 v0, v0, 0, 25
-; CGP-NEXT:    v_mul_f32_e32 v1, v3, v5
-; CGP-NEXT:    v_trunc_f32_e32 v1, v1
-; CGP-NEXT:    v_mad_f32 v3, -v1, v4, v3
-; CGP-NEXT:    v_cvt_i32_f32_e32 v1, v1
-; CGP-NEXT:    v_cmp_ge_f32_e64 s[4:5], |v3|, |v4|
-; CGP-NEXT:    v_cndmask_b32_e64 v3, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
-; CGP-NEXT:    v_mul_lo_u32 v3, v1, v6
 ; CGP-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
 ; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v2, v3
 ; CGP-NEXT:    v_bfe_i32 v2, v2, 0, 25
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
@@ -4191,8 +4191,8 @@
 ; GFX10-NEXT:    v_ashrrev_i32_e32 v6, 31, v11
 ; GFX10-NEXT:    v_cmp_lt_i64_e64 s4, v[10:11], v[0:1]
 ; GFX10-NEXT:    v_add_co_u32_e64 v0, s5, v6, 0
-; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s5, 0x80000000, v6, s5
 ; GFX10-NEXT:    s_xor_b32 vcc_lo, vcc_lo, s4
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s5, 0x80000000, v6, s5
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, v10, v0, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v1, v11, v1, vcc_lo
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
@@ -4369,8 +4369,8 @@
 ; GFX10-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
 ; GFX10-NEXT:    v_cmp_gt_i64_e64 s0, s[0:1], v[2:3]
 ; GFX10-NEXT:    v_add_co_u32_e64 v0, s1, v4, 0
-; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s1, 0x80000000, v4, s1
 ; GFX10-NEXT:    s_xor_b32 vcc_lo, vcc_lo, s0
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s1, 0x80000000, v4, s1
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo
 ; GFX10-NEXT:    ; return to shader part epilog
@@ -4436,8 +4436,8 @@
 ; GFX10-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
 ; GFX10-NEXT:    v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[0:1]
 ; GFX10-NEXT:    v_add_co_u32_e64 v0, s0, v4, 0
-; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s0, 0x80000000, v4, s0
 ; GFX10-NEXT:    s_xor_b32 vcc_lo, s1, vcc_lo
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s0, 0x80000000, v4, s0
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo
 ; GFX10-NEXT:    ; return to shader part epilog
@@ -4538,15 +4538,15 @@
 ; GFX10-NEXT:    v_cmp_lt_i64_e64 s6, 0, v[6:7]
 ; GFX10-NEXT:    v_sub_co_ci_u32_e32 v9, vcc_lo, v15, v5, vcc_lo
 ; GFX10-NEXT:    v_sub_co_u32_e64 v19, vcc_lo, v17, v6
-; GFX10-NEXT:    v_sub_co_ci_u32_e32 v20, vcc_lo, v18, v7, vcc_lo
 ; GFX10-NEXT:    v_ashrrev_i32_e32 v12, 31, v9
+; GFX10-NEXT:    v_sub_co_ci_u32_e32 v20, vcc_lo, v18, v7, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_i64_e32 vcc_lo, v[8:9], v[14:15]
-; GFX10-NEXT:    v_ashrrev_i32_e32 v0, 31, v20
 ; GFX10-NEXT:    v_add_co_u32_e64 v1, s5, v12, 0
+; GFX10-NEXT:    v_ashrrev_i32_e32 v0, 31, v20
+; GFX10-NEXT:    s_xor_b32 vcc_lo, s4, vcc_lo
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v4, s5, 0x80000000, v12, s5
-; GFX10-NEXT:    v_cmp_lt_i64_e64 s5, v[19:20], v[17:18]
 ; GFX10-NEXT:    v_add_co_u32_e64 v2, s7, v0, 0
-; GFX10-NEXT:    s_xor_b32 vcc_lo, s4, vcc_lo
+; GFX10-NEXT:    v_cmp_lt_i64_e64 s5, v[19:20], v[17:18]
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v3, s7, 0x80000000, v0, s7
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, v8, v1, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v1, v9, v4, vcc_lo
@@ -5311,52 +5311,52 @@
 ; GFX10-NEXT:    v_sub_co_ci_u32_e32 v6, vcc_lo, s2, v2, vcc_lo
 ; GFX10-NEXT:    v_sub_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
 ; GFX10-NEXT:    v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[4:5]
-; GFX10-NEXT:    s_movk_i32 s0, 0x7f
-; GFX10-NEXT:    s_sub_i32 s1, 64, s0
-; GFX10-NEXT:    v_lshrrev_b64 v[15:16], s0, v[4:5]
+; GFX10-NEXT:    s_movk_i32 s1, 0x7f
+; GFX10-NEXT:    s_sub_i32 s0, 64, s1
+; GFX10-NEXT:    v_lshrrev_b64 v[15:16], s1, v[4:5]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[6:7]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[6:7]
 ; GFX10-NEXT:    v_cndmask_b32_e32 v10, v9, v8, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, 0, v[0:1]
-; GFX10-NEXT:    v_lshlrev_b64 v[8:9], s1, v[6:7]
-; GFX10-NEXT:    s_sub_i32 s1, s0, 64
-; GFX10-NEXT:    s_cmp_lt_u32 s0, 64
-; GFX10-NEXT:    v_ashrrev_i64 v[0:1], s0, v[6:7]
+; GFX10-NEXT:    v_lshlrev_b64 v[8:9], s0, v[6:7]
+; GFX10-NEXT:    s_sub_i32 s0, s1, 64
+; GFX10-NEXT:    s_cmp_lt_u32 s1, 64
 ; GFX10-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_i64_e32 vcc_lo, 0, v[2:3]
-; GFX10-NEXT:    v_or_b32_e32 v8, v15, v8
-; GFX10-NEXT:    v_or_b32_e32 v9, v16, v9
-; GFX10-NEXT:    v_ashrrev_i32_e32 v15, 31, v7
+; GFX10-NEXT:    v_or_b32_e32 v0, v15, v8
+; GFX10-NEXT:    v_or_b32_e32 v1, v16, v9
 ; GFX10-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
-; GFX10-NEXT:    v_ashrrev_i64 v[2:3], s1, v[6:7]
+; GFX10-NEXT:    v_ashrrev_i64 v[2:3], s0, v[6:7]
 ; GFX10-NEXT:    v_cndmask_b32_e32 v11, v12, v11, vcc_lo
 ; GFX10-NEXT:    s_cselect_b32 vcc_lo, 1, 0
-; GFX10-NEXT:    s_cmp_eq_u32 s0, 0
-; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v9, vcc_lo
-; GFX10-NEXT:    s_cselect_b32 s1, 1, 0
-; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v8, vcc_lo
-; GFX10-NEXT:    s_and_b32 s0, 1, s1
+; GFX10-NEXT:    s_cmp_eq_u32 s1, 0
+; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v0, vcc_lo
+; GFX10-NEXT:    s_cselect_b32 s0, 1, 0
+; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v1, vcc_lo
+; GFX10-NEXT:    s_and_b32 s0, 1, s0
+; GFX10-NEXT:    v_ashrrev_i64 v[0:1], s1, v[6:7]
+; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, s0
 ; GFX10-NEXT:    s_and_b32 s1, 1, vcc_lo
-; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s0
-; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, s1
-; GFX10-NEXT:    v_xor_b32_e32 v9, v11, v10
-; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, v15, v0, s0
-; GFX10-NEXT:    v_and_b32_e32 v8, 1, v9
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, v15, v1, s0
-; GFX10-NEXT:    v_add_co_u32_e64 v2, vcc_lo, v2, 0
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
-; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, v8
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v8, vcc_lo, 0, v0, vcc_lo
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v9, vcc_lo, 0x80000000, v1, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, v4, v2, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, v5, v3, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v2, v6, v8, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v3, v7, v9, s0
+; GFX10-NEXT:    v_xor_b32_e32 v8, v11, v10
+; GFX10-NEXT:    v_ashrrev_i32_e32 v11, 31, v7
+; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s1
+; GFX10-NEXT:    v_cndmask_b32_e64 v2, v2, v4, s0
+; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, v5, s0
+; GFX10-NEXT:    v_and_b32_e32 v8, 1, v8
+; GFX10-NEXT:    v_cndmask_b32_e32 v0, v11, v0, vcc_lo
+; GFX10-NEXT:    v_add_co_u32_e64 v2, s0, v2, 0
+; GFX10-NEXT:    v_cndmask_b32_e32 v1, v11, v1, vcc_lo
+; GFX10-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v8
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v3, s0, 0, v3, s0
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v8, s0, 0, v0, s0
+; GFX10-NEXT:    v_cndmask_b32_e32 v0, v4, v2, vcc_lo
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v9, s0, 0x80000000, v1, s0
+; GFX10-NEXT:    v_cndmask_b32_e32 v1, v5, v3, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e32 v2, v6, v8, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e32 v3, v7, v9, vcc_lo
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = call i128 @llvm.ssub.sat.i128(i128 %lhs, i128 %rhs)
   %cast = bitcast i128 %result to <4 x float>
@@ -5555,64 +5555,60 @@
 ;
 ; GFX10-LABEL: ssubsat_i128_vs:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_mov_b32_e32 v5, v0
-; GFX10-NEXT:    v_mov_b32_e32 v6, v1
-; GFX10-NEXT:    v_mov_b32_e32 v9, v2
-; GFX10-NEXT:    v_mov_b32_e32 v10, v3
-; GFX10-NEXT:    s_cmp_eq_u64 s[2:3], 0
-; GFX10-NEXT:    v_sub_co_u32_e64 v15, vcc_lo, v5, s0
+; GFX10-NEXT:    v_sub_co_u32_e64 v14, vcc_lo, v0, s0
 ; GFX10-NEXT:    v_cmp_gt_u64_e64 s0, s[0:1], 0
-; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v16, vcc_lo, s1, v6, vcc_lo
+; GFX10-NEXT:    s_cmp_eq_u64 s[2:3], 0
 ; GFX10-NEXT:    s_cselect_b32 s4, 1, 0
-; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v19, vcc_lo, s2, v9, vcc_lo
-; GFX10-NEXT:    s_and_b32 s1, 1, s4
-; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v20, vcc_lo, s3, v10, vcc_lo
-; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[15:16], v[5:6]
+; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v15, vcc_lo, s1, v1, vcc_lo
+; GFX10-NEXT:    s_movk_i32 s1, 0x7f
 ; GFX10-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s0
 ; GFX10-NEXT:    v_cmp_gt_i64_e64 s0, s[2:3], 0
-; GFX10-NEXT:    v_ashrrev_i32_e32 v7, 31, v20
+; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v4, vcc_lo, s2, v2, vcc_lo
+; GFX10-NEXT:    s_sub_i32 s2, 64, s1
+; GFX10-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s0
+; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
+; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[14:15], v[0:1]
+; GFX10-NEXT:    s_and_b32 s0, 1, s4
 ; GFX10-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX10-NEXT:    v_cmp_lt_i64_e32 vcc_lo, v[19:20], v[9:10]
+; GFX10-NEXT:    v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[2:3]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX10-NEXT:    v_cmp_eq_u64_e32 vcc_lo, v[19:20], v[9:10]
-; GFX10-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s0
-; GFX10-NEXT:    s_movk_i32 s0, 0x7f
-; GFX10-NEXT:    s_sub_i32 s2, 64, s0
+; GFX10-NEXT:    v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[2:3]
+; GFX10-NEXT:    v_lshlrev_b64 v[2:3], s2, v[4:5]
 ; GFX10-NEXT:    v_cndmask_b32_e32 v10, v1, v0, vcc_lo
-; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s1
-; GFX10-NEXT:    v_lshrrev_b64 v[0:1], s0, v[15:16]
-; GFX10-NEXT:    v_lshlrev_b64 v[2:3], s2, v[19:20]
-; GFX10-NEXT:    s_sub_i32 s1, s0, 64
-; GFX10-NEXT:    s_cmp_lt_u32 s0, 64
+; GFX10-NEXT:    v_lshrrev_b64 v[0:1], s1, v[14:15]
+; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s0
+; GFX10-NEXT:    s_sub_i32 s0, s1, 64
+; GFX10-NEXT:    s_cmp_lt_u32 s1, 64
 ; GFX10-NEXT:    v_cndmask_b32_e32 v11, v9, v8, vcc_lo
 ; GFX10-NEXT:    s_cselect_b32 vcc_lo, 1, 0
-; GFX10-NEXT:    v_ashrrev_i64 v[8:9], s1, v[19:20]
-; GFX10-NEXT:    s_cmp_eq_u32 s0, 0
-; GFX10-NEXT:    v_or_b32_e32 v2, v0, v2
-; GFX10-NEXT:    v_or_b32_e32 v3, v1, v3
-; GFX10-NEXT:    s_cselect_b32 s1, 1, 0
-; GFX10-NEXT:    v_ashrrev_i64 v[0:1], s0, v[19:20]
-; GFX10-NEXT:    s_and_b32 s0, 1, s1
-; GFX10-NEXT:    v_cndmask_b32_e32 v2, v8, v2, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e32 v3, v9, v3, vcc_lo
+; GFX10-NEXT:    v_ashrrev_i64 v[7:8], s0, v[4:5]
+; GFX10-NEXT:    s_cmp_eq_u32 s1, 0
+; GFX10-NEXT:    v_or_b32_e32 v0, v0, v2
+; GFX10-NEXT:    s_cselect_b32 s0, 1, 0
+; GFX10-NEXT:    v_or_b32_e32 v1, v1, v3
+; GFX10-NEXT:    s_and_b32 s0, 1, s0
+; GFX10-NEXT:    v_xor_b32_e32 v2, v11, v10
+; GFX10-NEXT:    v_cndmask_b32_e32 v3, v7, v0, vcc_lo
+; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, s0
+; GFX10-NEXT:    v_cndmask_b32_e32 v8, v8, v1, vcc_lo
+; GFX10-NEXT:    v_ashrrev_i64 v[0:1], s1, v[4:5]
 ; GFX10-NEXT:    s_and_b32 s1, 1, vcc_lo
-; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s0
-; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, s1
-; GFX10-NEXT:    v_xor_b32_e32 v9, v11, v10
-; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v15, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v16, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, v7, v0, s0
-; GFX10-NEXT:    v_and_b32_e32 v8, 1, v9
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, v7, v1, s0
-; GFX10-NEXT:    v_add_co_u32_e64 v2, vcc_lo, v2, 0
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
-; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, v8
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v8, vcc_lo, 0, v0, vcc_lo
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v9, vcc_lo, 0x80000000, v1, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, v15, v2, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, v16, v3, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v2, v19, v8, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v3, v20, v9, s0
+; GFX10-NEXT:    v_ashrrev_i32_e32 v7, 31, v5
+; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, v14, s0
+; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s1
+; GFX10-NEXT:    v_cndmask_b32_e64 v8, v8, v15, s0
+; GFX10-NEXT:    v_and_b32_e32 v2, 1, v2
+; GFX10-NEXT:    v_add_co_u32_e64 v3, s0, v3, 0
+; GFX10-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e32 v1, v7, v1, vcc_lo
+; GFX10-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v2
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v8, s0, 0, v8, s0
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v2, s0, 0, v0, s0
+; GFX10-NEXT:    v_cndmask_b32_e32 v0, v14, v3, vcc_lo
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v7, s0, 0x80000000, v1, s0
+; GFX10-NEXT:    v_cndmask_b32_e32 v1, v15, v8, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e32 v3, v5, v7, vcc_lo
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = call i128 @llvm.ssub.sat.i128(i128 %lhs, i128 %rhs)
   %cast = bitcast i128 %result to <4 x float>
@@ -5949,109 +5945,109 @@
 ; GFX10-NEXT:    v_mov_b32_e32 v23, v1
 ; GFX10-NEXT:    v_mov_b32_e32 v20, v2
 ; GFX10-NEXT:    v_mov_b32_e32 v21, v3
-; GFX10-NEXT:    s_movk_i32 s5, 0x7f
+; GFX10-NEXT:    s_movk_i32 s6, 0x7f
 ; GFX10-NEXT:    v_sub_co_u32_e64 v16, vcc_lo, v22, v8
-; GFX10-NEXT:    s_sub_i32 s6, 64, s5
+; GFX10-NEXT:    s_sub_i32 s5, 64, s6
+; GFX10-NEXT:    s_sub_i32 s7, s6, 64
+; GFX10-NEXT:    s_cmp_lt_u32 s6, 64
+; GFX10-NEXT:    v_mov_b32_e32 v26, v4
 ; GFX10-NEXT:    v_sub_co_ci_u32_e32 v17, vcc_lo, v23, v9, vcc_lo
-; GFX10-NEXT:    s_sub_i32 s7, s5, 64
+; GFX10-NEXT:    v_mov_b32_e32 v27, v5
+; GFX10-NEXT:    v_mov_b32_e32 v4, v6
+; GFX10-NEXT:    v_mov_b32_e32 v5, v7
 ; GFX10-NEXT:    v_sub_co_ci_u32_e32 v18, vcc_lo, v20, v10, vcc_lo
-; GFX10-NEXT:    s_cmp_lt_u32 s5, 64
 ; GFX10-NEXT:    v_sub_co_ci_u32_e32 v19, vcc_lo, v21, v11, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[16:17], v[22:23]
-; GFX10-NEXT:    v_mov_b32_e32 v26, v4
-; GFX10-NEXT:    v_mov_b32_e32 v27, v5
-; GFX10-NEXT:    v_mov_b32_e32 v24, v6
-; GFX10-NEXT:    v_lshlrev_b64 v[2:3], s6, v[18:19]
-; GFX10-NEXT:    v_mov_b32_e32 v25, v7
+; GFX10-NEXT:    v_lshlrev_b64 v[2:3], s5, v[18:19]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_i64_e32 vcc_lo, v[18:19], v[20:21]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_eq_u64_e32 vcc_lo, v[18:19], v[20:21]
 ; GFX10-NEXT:    v_cndmask_b32_e32 v20, v1, v0, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, 0, v[8:9]
-; GFX10-NEXT:    v_lshrrev_b64 v[0:1], s5, v[16:17]
+; GFX10-NEXT:    v_lshrrev_b64 v[0:1], s6, v[16:17]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_i64_e32 vcc_lo, 0, v[10:11]
 ; GFX10-NEXT:    v_or_b32_e32 v2, v0, v2
 ; GFX10-NEXT:    v_or_b32_e32 v3, v1, v3
-; GFX10-NEXT:    v_ashrrev_i64 v[0:1], s5, v[18:19]
+; GFX10-NEXT:    v_ashrrev_i64 v[0:1], s6, v[18:19]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11]
 ; GFX10-NEXT:    v_ashrrev_i32_e32 v11, 31, v19
 ; GFX10-NEXT:    v_cndmask_b32_e32 v10, v9, v8, vcc_lo
 ; GFX10-NEXT:    s_cselect_b32 vcc_lo, 1, 0
 ; GFX10-NEXT:    v_ashrrev_i64 v[8:9], s7, v[18:19]
-; GFX10-NEXT:    s_cmp_eq_u32 s5, 0
+; GFX10-NEXT:    s_cmp_eq_u32 s6, 0
 ; GFX10-NEXT:    s_cselect_b32 s4, 1, 0
 ; GFX10-NEXT:    s_and_b32 s8, 1, vcc_lo
 ; GFX10-NEXT:    s_and_b32 s4, 1, s4
-; GFX10-NEXT:    v_cndmask_b32_e32 v3, v9, v3, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v2, v8, v2, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e32 v3, v9, v3, vcc_lo
 ; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s4
 ; GFX10-NEXT:    v_cmp_ne_u32_e64 s4, 0, s8
-; GFX10-NEXT:    v_xor_b32_e32 v9, v10, v20
-; GFX10-NEXT:    s_cmp_lt_u32 s5, 64
+; GFX10-NEXT:    v_xor_b32_e32 v10, v10, v20
+; GFX10-NEXT:    s_cmp_lt_u32 s6, 64
 ; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v16, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v17, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e64 v0, v11, v0, s4
 ; GFX10-NEXT:    v_cndmask_b32_e64 v1, v11, v1, s4
-; GFX10-NEXT:    v_and_b32_e32 v8, 1, v9
-; GFX10-NEXT:    v_add_co_u32_e64 v2, vcc_lo, v2, 0
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v20, vcc_lo, 0, v0, vcc_lo
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v21, vcc_lo, 0x80000000, v1, vcc_lo
-; GFX10-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v8
 ; GFX10-NEXT:    v_sub_co_u32_e64 v8, s4, v26, v12
+; GFX10-NEXT:    v_add_co_u32_e64 v2, vcc_lo, v2, 0
 ; GFX10-NEXT:    v_sub_co_ci_u32_e64 v9, s4, v27, v13, s4
-; GFX10-NEXT:    v_sub_co_ci_u32_e64 v10, s4, v24, v14, s4
-; GFX10-NEXT:    v_cndmask_b32_e32 v0, v16, v2, vcc_lo
-; GFX10-NEXT:    v_sub_co_ci_u32_e64 v11, s4, v25, v15, s4
+; GFX10-NEXT:    v_add_co_ci_u32_e32 v20, vcc_lo, 0, v3, vcc_lo
+; GFX10-NEXT:    v_add_co_ci_u32_e32 v21, vcc_lo, 0, v0, vcc_lo
+; GFX10-NEXT:    v_and_b32_e32 v0, 1, v10
+; GFX10-NEXT:    v_add_co_ci_u32_e32 v22, vcc_lo, 0x80000000, v1, vcc_lo
+; GFX10-NEXT:    v_sub_co_ci_u32_e64 v10, vcc_lo, v4, v14, s4
 ; GFX10-NEXT:    v_cmp_lt_u64_e64 s4, v[8:9], v[26:27]
-; GFX10-NEXT:    v_cndmask_b32_e32 v1, v17, v3, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e32 v2, v18, v20, vcc_lo
-; GFX10-NEXT:    v_lshrrev_b64 v[3:4], s5, v[8:9]
-; GFX10-NEXT:    v_cndmask_b32_e64 v5, 0, 1, s4
-; GFX10-NEXT:    v_cmp_lt_i64_e64 s4, v[10:11], v[24:25]
-; GFX10-NEXT:    v_cndmask_b32_e64 v16, 0, 1, s4
+; GFX10-NEXT:    v_sub_co_ci_u32_e32 v11, vcc_lo, v5, v15, vcc_lo
+; GFX10-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX10-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s4
+; GFX10-NEXT:    v_cmp_lt_i64_e64 s4, v[10:11], v[4:5]
+; GFX10-NEXT:    v_cndmask_b32_e32 v0, v16, v2, vcc_lo
+; GFX10-NEXT:    v_ashrrev_i64 v[23:24], s7, v[10:11]
+; GFX10-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s4
 ; GFX10-NEXT:    v_cmp_lt_u64_e64 s4, 0, v[12:13]
-; GFX10-NEXT:    v_lshlrev_b64 v[12:13], s6, v[10:11]
-; GFX10-NEXT:    v_cndmask_b32_e64 v17, 0, 1, s4
+; GFX10-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s4
 ; GFX10-NEXT:    v_cmp_lt_i64_e64 s4, 0, v[14:15]
-; GFX10-NEXT:    v_or_b32_e32 v12, v3, v12
-; GFX10-NEXT:    v_or_b32_e32 v13, v4, v13
-; GFX10-NEXT:    v_ashrrev_i64 v[3:4], s5, v[10:11]
-; GFX10-NEXT:    v_cndmask_b32_e64 v18, 0, 1, s4
-; GFX10-NEXT:    v_cmp_eq_u64_e64 s4, v[10:11], v[24:25]
-; GFX10-NEXT:    v_cndmask_b32_e64 v7, v16, v5, s4
+; GFX10-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s4
+; GFX10-NEXT:    v_cmp_eq_u64_e64 s4, v[10:11], v[4:5]
+; GFX10-NEXT:    v_lshlrev_b64 v[4:5], s5, v[10:11]
+; GFX10-NEXT:    v_cndmask_b32_e64 v16, v2, v1, s4
 ; GFX10-NEXT:    v_cmp_eq_u64_e64 s4, 0, v[14:15]
-; GFX10-NEXT:    v_ashrrev_i64 v[5:6], s7, v[10:11]
-; GFX10-NEXT:    v_cndmask_b32_e64 v14, v18, v17, s4
+; GFX10-NEXT:    v_lshrrev_b64 v[2:3], s6, v[8:9]
+; GFX10-NEXT:    v_cndmask_b32_e32 v1, v17, v20, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e64 v15, v13, v12, s4
 ; GFX10-NEXT:    s_cselect_b32 s4, 1, 0
-; GFX10-NEXT:    s_cmp_eq_u32 s5, 0
-; GFX10-NEXT:    v_cndmask_b32_e64 v5, v5, v12, s4
-; GFX10-NEXT:    s_cselect_b32 s6, 1, 0
-; GFX10-NEXT:    v_cndmask_b32_e64 v6, v6, v13, s4
-; GFX10-NEXT:    s_and_b32 s5, 1, s6
-; GFX10-NEXT:    s_and_b32 s6, 1, s4
-; GFX10-NEXT:    v_cmp_ne_u32_e64 s4, 0, s5
-; GFX10-NEXT:    v_xor_b32_e32 v7, v14, v7
-; GFX10-NEXT:    v_ashrrev_i32_e32 v18, 31, v11
-; GFX10-NEXT:    v_cmp_ne_u32_e64 s5, 0, s6
-; GFX10-NEXT:    v_cndmask_b32_e64 v5, v5, v8, s4
-; GFX10-NEXT:    v_cndmask_b32_e64 v6, v6, v9, s4
-; GFX10-NEXT:    v_and_b32_e32 v7, 1, v7
-; GFX10-NEXT:    v_cndmask_b32_e64 v3, v18, v3, s5
-; GFX10-NEXT:    v_cndmask_b32_e64 v4, v18, v4, s5
-; GFX10-NEXT:    v_add_co_u32_e64 v5, s4, v5, 0
-; GFX10-NEXT:    v_add_co_ci_u32_e64 v6, s4, 0, v6, s4
-; GFX10-NEXT:    v_cmp_ne_u32_e64 s5, 0, v7
-; GFX10-NEXT:    v_add_co_ci_u32_e64 v7, s4, 0, v3, s4
-; GFX10-NEXT:    v_cndmask_b32_e32 v3, v19, v21, vcc_lo
-; GFX10-NEXT:    v_add_co_ci_u32_e64 v12, s4, 0x80000000, v4, s4
-; GFX10-NEXT:    v_cndmask_b32_e64 v4, v8, v5, s5
-; GFX10-NEXT:    v_cndmask_b32_e64 v5, v9, v6, s5
-; GFX10-NEXT:    v_cndmask_b32_e64 v6, v10, v7, s5
-; GFX10-NEXT:    v_cndmask_b32_e64 v7, v11, v12, s5
+; GFX10-NEXT:    s_cmp_eq_u32 s6, 0
+; GFX10-NEXT:    v_or_b32_e32 v2, v2, v4
+; GFX10-NEXT:    s_cselect_b32 s5, 1, 0
+; GFX10-NEXT:    v_or_b32_e32 v3, v3, v5
+; GFX10-NEXT:    s_and_b32 s5, 1, s5
+; GFX10-NEXT:    v_ashrrev_i32_e32 v13, 31, v11
+; GFX10-NEXT:    v_cndmask_b32_e64 v5, v23, v2, s4
+; GFX10-NEXT:    v_cmp_ne_u32_e64 s5, 0, s5
+; GFX10-NEXT:    v_cndmask_b32_e64 v6, v24, v3, s4
+; GFX10-NEXT:    s_and_b32 s4, 1, s4
+; GFX10-NEXT:    v_ashrrev_i64 v[2:3], s6, v[10:11]
+; GFX10-NEXT:    v_cmp_ne_u32_e64 s4, 0, s4
+; GFX10-NEXT:    v_cndmask_b32_e64 v5, v5, v8, s5
+; GFX10-NEXT:    v_cndmask_b32_e64 v6, v6, v9, s5
+; GFX10-NEXT:    v_xor_b32_e32 v4, v15, v16
+; GFX10-NEXT:    v_cndmask_b32_e64 v12, v13, v2, s4
+; GFX10-NEXT:    v_add_co_u32_e64 v5, s5, v5, 0
+; GFX10-NEXT:    v_cndmask_b32_e64 v3, v13, v3, s4
+; GFX10-NEXT:    v_and_b32_e32 v4, 1, v4
+; GFX10-NEXT:    v_cndmask_b32_e32 v2, v18, v21, vcc_lo
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v6, s5, 0, v6, s5
+; GFX10-NEXT:    v_cmp_ne_u32_e64 s4, 0, v4
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v7, s5, 0, v12, s5
+; GFX10-NEXT:    v_cndmask_b32_e64 v4, v8, v5, s4
+; GFX10-NEXT:    v_cndmask_b32_e64 v5, v9, v6, s4
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v12, s5, 0x80000000, v3, s5
+; GFX10-NEXT:    v_cndmask_b32_e64 v6, v10, v7, s4
+; GFX10-NEXT:    v_cndmask_b32_e32 v3, v19, v22, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e64 v7, v11, v12, s4
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = call <2 x i128> @llvm.ssub.sat.v2i128(<2 x i128> %lhs, <2 x i128> %rhs)
   ret <2 x i128> %result
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
@@ -3438,24 +3438,24 @@
 ; GFX10-NEXT:    v_mov_b32_e32 v18, v8
 ; GFX10-NEXT:    v_mov_b32_e32 v19, v9
 ; GFX10-NEXT:    v_mov_b32_e32 v16, v10
+; GFX10-NEXT:    v_mov_b32_e32 v22, v12
 ; GFX10-NEXT:    v_mov_b32_e32 v17, v11
-; GFX10-NEXT:    v_mov_b32_e32 v10, v12
 ; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, v0, v18
-; GFX10-NEXT:    v_mov_b32_e32 v11, v13
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, v1, v19, vcc_lo
+; GFX10-NEXT:    v_mov_b32_e32 v23, v13
 ; GFX10-NEXT:    v_mov_b32_e32 v20, v14
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v2, vcc_lo, v2, v16, vcc_lo
+; GFX10-NEXT:    v_add_co_u32_e64 v4, s4, v4, v22
 ; GFX10-NEXT:    v_mov_b32_e32 v21, v15
+; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, v1, v19, vcc_lo
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v5, s4, v5, v23, s4
+; GFX10-NEXT:    v_add_co_ci_u32_e32 v2, vcc_lo, v2, v16, vcc_lo
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, v3, v17, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[18:19]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc_lo
-; GFX10-NEXT:    v_add_co_u32_e64 v4, vcc_lo, v4, v10
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v5, vcc_lo, v5, v11, vcc_lo
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v6, vcc_lo, v6, v20, vcc_lo
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v6, vcc_lo, v6, v20, s4
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v7, vcc_lo, v7, v21, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[16:17]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc_lo
-; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[10:11]
+; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[22:23]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[6:7], v[20:21]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc_lo
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
@@ -3080,12 +3080,12 @@
 ; GFX10-NEXT:    v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[2:3]
 ; GFX10-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc_lo
 ; GFX10-NEXT:    v_sub_co_u32_e64 v0, vcc_lo, s0, v0
-; GFX10-NEXT:    v_sub_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
 ; GFX10-NEXT:    v_and_b32_e32 v4, 1, v4
-; GFX10-NEXT:    v_sub_co_ci_u32_e32 v2, vcc_lo, s2, v2, vcc_lo
-; GFX10-NEXT:    v_sub_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
+; GFX10-NEXT:    v_sub_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
 ; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, v4
+; GFX10-NEXT:    v_sub_co_ci_u32_e32 v2, vcc_lo, s2, v2, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s0
+; GFX10-NEXT:    v_sub_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, 0, s0
 ; GFX10-NEXT:    v_cndmask_b32_e64 v2, v2, 0, s0
 ; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, 0, s0
@@ -3174,12 +3174,12 @@
 ; GFX10-NEXT:    v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[2:3]
 ; GFX10-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc_lo
 ; GFX10-NEXT:    v_sub_co_u32_e64 v0, vcc_lo, v0, s0
-; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
 ; GFX10-NEXT:    v_and_b32_e32 v4, 1, v4
-; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v2, vcc_lo, s2, v2, vcc_lo
-; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
+; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
 ; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, v4
+; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v2, vcc_lo, s2, v2, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s0
+; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, 0, s0
 ; GFX10-NEXT:    v_cndmask_b32_e64 v2, v2, 0, s0
 ; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, 0, s0
@@ -3316,31 +3316,31 @@
 ; GFX10-NEXT:    v_mov_b32_e32 v25, v7
 ; GFX10-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[20:21], v[10:11]
-; GFX10-NEXT:    v_cmp_eq_u64_e64 s5, v[24:25], v[14:15]
+; GFX10-NEXT:    v_cmp_eq_u64_e64 s4, v[24:25], v[14:15]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_eq_u64_e32 vcc_lo, v[20:21], v[10:11]
 ; GFX10-NEXT:    v_cndmask_b32_e32 v16, v17, v16, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[26:27], v[12:13]
-; GFX10-NEXT:    v_and_b32_e32 v16, 1, v16
 ; GFX10-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[24:25], v[14:15]
-; GFX10-NEXT:    v_cmp_ne_u32_e64 s4, 0, v16
 ; GFX10-NEXT:    v_cndmask_b32_e64 v18, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_sub_co_u32_e64 v0, vcc_lo, v22, v8
+; GFX10-NEXT:    v_and_b32_e32 v8, 1, v16
 ; GFX10-NEXT:    v_sub_co_ci_u32_e32 v1, vcc_lo, v23, v9, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v8, v18, v17, s5
+; GFX10-NEXT:    v_cndmask_b32_e64 v9, v18, v17, s4
+; GFX10-NEXT:    v_sub_co_u32_e64 v4, s4, v26, v12
 ; GFX10-NEXT:    v_sub_co_ci_u32_e32 v2, vcc_lo, v20, v10, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s4
+; GFX10-NEXT:    v_sub_co_ci_u32_e64 v5, s4, v27, v13, s4
 ; GFX10-NEXT:    v_sub_co_ci_u32_e32 v3, vcc_lo, v21, v11, vcc_lo
-; GFX10-NEXT:    v_sub_co_u32_e64 v4, vcc_lo, v26, v12
-; GFX10-NEXT:    v_and_b32_e32 v8, 1, v8
-; GFX10-NEXT:    v_sub_co_ci_u32_e32 v5, vcc_lo, v27, v13, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, 0, s4
-; GFX10-NEXT:    v_sub_co_ci_u32_e32 v6, vcc_lo, v24, v14, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v2, v2, 0, s4
+; GFX10-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v8
+; GFX10-NEXT:    v_sub_co_ci_u32_e64 v6, s4, v24, v14, s4
+; GFX10-NEXT:    v_and_b32_e32 v8, 1, v9
+; GFX10-NEXT:    v_cndmask_b32_e64 v0, v0, 0, vcc_lo
+; GFX10-NEXT:    v_sub_co_ci_u32_e64 v7, s4, v25, v15, s4
 ; GFX10-NEXT:    v_cmp_ne_u32_e64 s5, 0, v8
-; GFX10-NEXT:    v_sub_co_ci_u32_e32 v7, vcc_lo, v25, v15, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, 0, s4
+; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, 0, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e64 v2, v2, 0, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, 0, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e64 v4, v4, 0, s5
 ; GFX10-NEXT:    v_cndmask_b32_e64 v5, v5, 0, s5
 ; GFX10-NEXT:    v_cndmask_b32_e64 v6, v6, 0, s5
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
@@ -245,20 +245,20 @@
 ; GFX6-NEXT:    s_xor_b32 s9, s3, s8
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s9
 ; GFX6-NEXT:    s_sub_i32 s3, 0, s9
-; GFX6-NEXT:    s_ashr_i32 s0, s2, 31
-; GFX6-NEXT:    s_add_i32 s1, s2, s0
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
-; GFX6-NEXT:    s_xor_b32 s1, s1, s0
-; GFX6-NEXT:    s_xor_b32 s2, s0, s8
 ; GFX6-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX6-NEXT:    v_mul_lo_u32 v1, s3, v0
+; GFX6-NEXT:    s_ashr_i32 s3, s2, 31
+; GFX6-NEXT:    s_add_i32 s2, s2, s3
+; GFX6-NEXT:    s_xor_b32 s2, s2, s3
 ; GFX6-NEXT:    v_mul_hi_u32 v1, v0, v1
+; GFX6-NEXT:    s_xor_b32 s3, s3, s8
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
-; GFX6-NEXT:    v_mul_hi_u32 v0, s1, v0
+; GFX6-NEXT:    v_mul_hi_u32 v0, s2, v0
 ; GFX6-NEXT:    v_mul_lo_u32 v1, v0, s9
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, 1, v0
-; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s1, v1
+; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s2, v1
 ; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s9, v1
 ; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
 ; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s9, v1
@@ -266,8 +266,8 @@
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, 1, v0
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
 ; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX6-NEXT:    v_xor_b32_e32 v0, s2, v0
-; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s2, v0
+; GFX6-NEXT:    v_xor_b32_e32 v0, s3, v0
+; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s3, v0
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -472,7 +472,7 @@
 ; GFX9-LABEL: udiv_i16:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x2c
-; GFX9-NEXT:    v_mov_b32_e32 v3, 0
+; GFX9-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    s_lshr_b32 s3, s2, 16
@@ -482,11 +482,11 @@
 ; GFX9-NEXT:    v_rcp_iflag_f32_e32 v2, v0
 ; GFX9-NEXT:    v_mul_f32_e32 v2, v1, v2
 ; GFX9-NEXT:    v_trunc_f32_e32 v2, v2
-; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v2
+; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v2
 ; GFX9-NEXT:    v_mad_f32 v1, -v2, v0, v1
 ; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
-; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v4, vcc
-; GFX9-NEXT:    global_store_short v3, v0, s[0:1]
+; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v3, vcc
+; GFX9-NEXT:    global_store_short v4, v0, s[0:1]
 ; GFX9-NEXT:    s_endpgm
   %r = udiv i16 %x, %y
   store i16 %r, i16 addrspace(1)* %out
@@ -685,20 +685,20 @@
 ; GFX6-NEXT:    v_cvt_f32_i32_e32 v0, s2
 ; GFX6-NEXT:    s_sext_i32_i16 s3, s4
 ; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s3
-; GFX6-NEXT:    s_xor_b32 s3, s3, s2
+; GFX6-NEXT:    s_xor_b32 s5, s3, s2
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
-; GFX6-NEXT:    s_ashr_i32 s3, s3, 30
+; GFX6-NEXT:    s_ashr_i32 s3, s5, 30
 ; GFX6-NEXT:    s_or_b32 s3, s3, 1
 ; GFX6-NEXT:    v_mov_b32_e32 v3, s3
 ; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
 ; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
+; GFX6-NEXT:    v_cvt_i32_f32_e32 v4, v2
 ; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
-; GFX6-NEXT:    v_cvt_i32_f32_e32 v2, v2
 ; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
 ; GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
-; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
 ; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s2
+; GFX6-NEXT:    s_mov_b32 s3, 0xf000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
 ; GFX6-NEXT:    buffer_store_short v0, off, s[0:3], 0
@@ -760,39 +760,39 @@
 ;
 ; GFX6-LABEL: udiv_i8:
 ; GFX6:       ; %bb.0:
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dword s2, s[0:1], 0xb
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX6-NEXT:    s_mov_b32 s3, 0xf000
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_cvt_f32_ubyte1_e32 v0, s0
+; GFX6-NEXT:    v_cvt_f32_ubyte1_e32 v0, s2
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v0
-; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v2, s0
+; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v2, s2
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    v_mul_f32_e32 v1, v2, v1
 ; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v1
 ; GFX6-NEXT:    v_mad_f32 v1, -v1, v0, v2
 ; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
 ; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
-; GFX6-NEXT:    buffer_store_byte v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_byte v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: udiv_i8:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x2c
-; GFX9-NEXT:    v_mov_b32_e32 v2, 0
+; GFX9-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    v_cvt_f32_ubyte1_e32 v0, s2
 ; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v0
-; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v3, s2
-; GFX9-NEXT:    v_mul_f32_e32 v1, v3, v1
+; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v2, s2
+; GFX9-NEXT:    v_mul_f32_e32 v1, v2, v1
 ; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
-; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v1
-; GFX9-NEXT:    v_mad_f32 v1, -v1, v0, v3
+; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v1
+; GFX9-NEXT:    v_mad_f32 v1, -v1, v0, v2
 ; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
-; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v4, vcc
-; GFX9-NEXT:    global_store_byte v2, v0, s[0:1]
+; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v3, vcc
+; GFX9-NEXT:    global_store_byte v4, v0, s[0:1]
 ; GFX9-NEXT:    s_endpgm
   %r = udiv i8 %x, %y
   store i8 %r, i8 addrspace(1)* %out
@@ -982,31 +982,31 @@
 ;
 ; GFX6-LABEL: srem_i8:
 ; GFX6:       ; %bb.0:
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    s_bfe_i32 s1, s0, 0x80008
-; GFX6-NEXT:    v_cvt_f32_i32_e32 v0, s1
-; GFX6-NEXT:    s_sext_i32_i8 s3, s0
-; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s3
-; GFX6-NEXT:    s_xor_b32 s1, s3, s1
+; GFX6-NEXT:    s_bfe_i32 s3, s4, 0x80008
+; GFX6-NEXT:    v_cvt_f32_i32_e32 v0, s3
+; GFX6-NEXT:    s_sext_i32_i8 s5, s4
+; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s5
+; GFX6-NEXT:    s_xor_b32 s3, s5, s3
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
-; GFX6-NEXT:    s_ashr_i32 s1, s1, 30
-; GFX6-NEXT:    s_or_b32 s1, s1, 1
-; GFX6-NEXT:    v_mov_b32_e32 v3, s1
+; GFX6-NEXT:    s_ashr_i32 s3, s3, 30
+; GFX6-NEXT:    s_or_b32 s3, s3, 1
+; GFX6-NEXT:    v_mov_b32_e32 v3, s3
 ; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
 ; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
+; GFX6-NEXT:    v_cvt_i32_f32_e32 v4, v2
 ; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
-; GFX6-NEXT:    v_cvt_i32_f32_e32 v2, v2
 ; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
 ; GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
-; GFX6-NEXT:    s_lshr_b32 s2, s0, 8
-; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT:    s_lshr_b32 s2, s4, 8
+; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
 ; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s2
-; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s0, v0
-; GFX6-NEXT:    buffer_store_byte v0, off, s[4:7], 0
+; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_mov_b32 s2, -1
+; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
+; GFX6-NEXT:    buffer_store_byte v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: srem_i8:
@@ -1178,7 +1178,7 @@
 ; GFX6-LABEL: udiv_v4i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0xd
-; GFX6-NEXT:    s_mov_b32 s3, 0x4f7ffffe
+; GFX6-NEXT:    s_mov_b32 s16, 0x4f7ffffe
 ; GFX6-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0x9
 ; GFX6-NEXT:    s_mov_b32 s15, 0xf000
 ; GFX6-NEXT:    s_mov_b32 s14, -1
@@ -1186,79 +1186,79 @@
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s8
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s9
 ; GFX6-NEXT:    s_sub_i32 s2, 0, s8
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, s10
+; GFX6-NEXT:    s_sub_i32 s3, 0, s9
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v1
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v6, s11
-; GFX6-NEXT:    v_mul_f32_e32 v0, s3, v0
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, s10
+; GFX6-NEXT:    v_mul_f32_e32 v0, s16, v0
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT:    v_mul_f32_e32 v1, s3, v1
+; GFX6-NEXT:    v_mul_f32_e32 v1, s16, v1
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v4
 ; GFX6-NEXT:    v_mul_lo_u32 v2, s2, v0
-; GFX6-NEXT:    s_sub_i32 s2, 0, s9
-; GFX6-NEXT:    v_mul_lo_u32 v3, s2, v1
-; GFX6-NEXT:    s_sub_i32 s2, 0, s10
+; GFX6-NEXT:    s_sub_i32 s2, 0, s11
+; GFX6-NEXT:    v_mul_lo_u32 v3, s3, v1
 ; GFX6-NEXT:    v_mul_hi_u32 v2, v0, v2
 ; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
 ; GFX6-NEXT:    v_mul_hi_u32 v0, s4, v0
 ; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
 ; GFX6-NEXT:    v_mul_hi_u32 v1, s5, v1
-; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s8
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, 1, v0
-; GFX6-NEXT:    v_mul_lo_u32 v5, v1, s9
-; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s4, v2
-; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s8, v2
-; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v3, s[0:1]
-; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s8, v2
-; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, v3, s[0:1]
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, 1, v0
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v2
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v4
-; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
-; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s5, v5
-; GFX6-NEXT:    v_add_i32_e32 v4, vcc, 1, v1
-; GFX6-NEXT:    v_mul_f32_e32 v2, s3, v2
+; GFX6-NEXT:    v_mul_f32_e32 v2, s16, v4
+; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s8
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v0
+; GFX6-NEXT:    v_mul_lo_u32 v4, v1, s9
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v2
-; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s9, v3
-; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v4, s[0:1]
-; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s9, v3
-; GFX6-NEXT:    v_mul_lo_u32 v4, s2, v2
+; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s4, v3
+; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s8, v3
+; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v5, s[0:1]
+; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s8, v3
 ; GFX6-NEXT:    v_cndmask_b32_e64 v3, v3, v5, s[0:1]
+; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s5, v4
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v0
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v3
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s11
+; GFX6-NEXT:    s_sub_i32 s0, 0, s10
+; GFX6-NEXT:    v_mul_lo_u32 v6, s0, v2
+; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v3, v3
 ; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v1
-; GFX6-NEXT:    s_sub_i32 s0, 0, s11
-; GFX6-NEXT:    v_mul_hi_u32 v4, v2, v4
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v6
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v3
-; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
+; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s9, v4
+; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v5, s[0:1]
+; GFX6-NEXT:    v_mul_f32_e32 v3, s16, v3
+; GFX6-NEXT:    v_mul_hi_u32 v5, v2, v6
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v3
+; GFX6-NEXT:    v_subrev_i32_e32 v6, vcc, s9, v4
+; GFX6-NEXT:    v_cndmask_b32_e64 v4, v4, v6, s[0:1]
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
+; GFX6-NEXT:    v_mul_lo_u32 v5, s2, v3
 ; GFX6-NEXT:    v_mul_hi_u32 v2, s6, v2
-; GFX6-NEXT:    v_mul_f32_e32 v4, s3, v4
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v4, v4
-; GFX6-NEXT:    v_mul_lo_u32 v3, v2, s10
+; GFX6-NEXT:    v_add_i32_e32 v6, vcc, 1, v1
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v4
+; GFX6-NEXT:    v_mul_hi_u32 v5, v3, v5
+; GFX6-NEXT:    v_mul_lo_u32 v7, v2, s10
+; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v6, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v6, vcc, 1, v2
-; GFX6-NEXT:    v_mul_lo_u32 v5, s0, v4
-; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s6, v3
-; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s10, v3
-; GFX6-NEXT:    v_mul_hi_u32 v5, v4, v5
-; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, v6, s[0:1]
-; GFX6-NEXT:    v_subrev_i32_e32 v6, vcc, s10, v3
-; GFX6-NEXT:    v_cndmask_b32_e64 v3, v3, v6, s[0:1]
-; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GFX6-NEXT:    v_mul_hi_u32 v4, s7, v4
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v2
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v3
-; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v6, v4, s11
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v4
-; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s7, v6
-; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s11, v3
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
+; GFX6-NEXT:    v_mul_hi_u32 v3, s7, v3
+; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s6, v7
+; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s10, v4
+; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s10, v4
 ; GFX6-NEXT:    v_cndmask_b32_e64 v4, v4, v5, s[0:1]
-; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s11, v3
+; GFX6-NEXT:    v_mul_lo_u32 v5, v3, s11
+; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, v6, s[0:1]
+; GFX6-NEXT:    v_add_i32_e32 v6, vcc, 1, v2
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v4
+; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc
+; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s7, v5
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v3
+; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s11, v4
 ; GFX6-NEXT:    v_cndmask_b32_e64 v3, v3, v5, s[0:1]
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v4
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s11, v3
-; GFX6-NEXT:    v_cndmask_b32_e32 v3, v4, v5, vcc
+; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s11, v4
+; GFX6-NEXT:    v_cndmask_b32_e64 v4, v4, v5, s[0:1]
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v3
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s11, v4
+; GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
 ; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[12:15], 0
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -1480,70 +1480,70 @@
 ; GFX6-LABEL: urem_v4i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0xd
-; GFX6-NEXT:    s_mov_b32 s13, 0x4f7ffffe
+; GFX6-NEXT:    s_mov_b32 s14, 0x4f7ffffe
 ; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
 ; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s8
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s9
-; GFX6-NEXT:    s_sub_i32 s2, 0, s8
-; GFX6-NEXT:    s_sub_i32 s12, 0, s9
+; GFX6-NEXT:    s_sub_i32 s12, 0, s8
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v2, s10
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v1
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s10
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v5, s11
-; GFX6-NEXT:    v_mul_f32_e32 v0, s13, v0
+; GFX6-NEXT:    s_sub_i32 s13, 0, s9
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v2
+; GFX6-NEXT:    v_mul_f32_e32 v0, s14, v0
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT:    v_mul_f32_e32 v1, s13, v1
+; GFX6-NEXT:    v_mul_f32_e32 v1, s14, v1
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v3, v3
-; GFX6-NEXT:    v_mul_lo_u32 v2, s2, v0
-; GFX6-NEXT:    s_mov_b32 s2, -1
-; GFX6-NEXT:    v_mul_lo_u32 v4, s12, v1
-; GFX6-NEXT:    v_mul_hi_u32 v2, v0, v2
+; GFX6-NEXT:    v_mul_f32_e32 v2, s14, v2
+; GFX6-NEXT:    v_mul_lo_u32 v3, s12, v0
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v5, s11
+; GFX6-NEXT:    v_mul_lo_u32 v4, s13, v1
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v2
+; GFX6-NEXT:    v_mul_hi_u32 v3, v0, v3
+; GFX6-NEXT:    s_sub_i32 s12, 0, s10
 ; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
+; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v3, v0
 ; GFX6-NEXT:    v_mul_hi_u32 v0, s4, v0
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v3, v5
 ; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v4, v1
-; GFX6-NEXT:    v_mul_hi_u32 v1, s5, v1
-; GFX6-NEXT:    v_mul_f32_e32 v2, s13, v3
+; GFX6-NEXT:    v_mul_lo_u32 v4, s12, v2
 ; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s8
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v2
-; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s9
+; GFX6-NEXT:    v_mul_hi_u32 v1, s5, v1
+; GFX6-NEXT:    v_mul_f32_e32 v3, s14, v3
+; GFX6-NEXT:    v_mul_hi_u32 v4, v2, v4
 ; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
-; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s8, v0
+; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s8, v0
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
-; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
-; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s8, v0
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v3
+; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
+; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s8, v0
+; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s9
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
-; GFX6-NEXT:    s_sub_i32 s4, 0, s10
-; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v3, s4, v2
-; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s5, v1
-; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s9, v1
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
-; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
-; GFX6-NEXT:    v_mul_hi_u32 v3, v2, v3
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v5
 ; GFX6-NEXT:    s_sub_i32 s4, 0, s11
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_mul_f32_e32 v3, s13, v4
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v3
-; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s9, v1
+; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
+; GFX6-NEXT:    v_mul_lo_u32 v4, s4, v3
+; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s5, v1
 ; GFX6-NEXT:    v_mul_hi_u32 v2, s6, v2
+; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s9, v1
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
+; GFX6-NEXT:    v_mul_hi_u32 v4, v3, v4
+; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
+; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s9, v1
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
-; GFX6-NEXT:    v_mul_lo_u32 v5, s4, v3
-; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v2, s10
-; GFX6-NEXT:    v_mul_hi_u32 v4, v3, v5
-; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s6, v2
-; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s10, v2
+; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
 ; GFX6-NEXT:    v_mul_hi_u32 v3, s7, v3
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v2
-; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
+; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s6, v2
 ; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s10, v2
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v2
 ; GFX6-NEXT:    v_mul_lo_u32 v3, v3, s11
+; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
+; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s10, v2
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v2
 ; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
 ; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s7, v3
@@ -1810,121 +1810,121 @@
 ; GFX6-LABEL: sdiv_v4i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_load_dwordx8 s[8:15], s[0:1], 0xd
-; GFX6-NEXT:    s_mov_b32 s16, 0x4f7ffffe
+; GFX6-NEXT:    s_mov_b32 s17, 0x4f7ffffe
 ; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
 ; GFX6-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX6-NEXT:    s_mov_b32 s6, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_ashr_i32 s2, s12, 31
 ; GFX6-NEXT:    s_add_i32 s3, s12, s2
-; GFX6-NEXT:    s_xor_b32 s12, s3, s2
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s12
-; GFX6-NEXT:    s_ashr_i32 s3, s13, 31
-; GFX6-NEXT:    s_add_i32 s0, s13, s3
-; GFX6-NEXT:    s_xor_b32 s13, s0, s3
+; GFX6-NEXT:    s_xor_b32 s16, s3, s2
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s16
+; GFX6-NEXT:    s_ashr_i32 s12, s13, 31
+; GFX6-NEXT:    s_add_i32 s1, s13, s12
+; GFX6-NEXT:    s_xor_b32 s13, s1, s12
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s13
-; GFX6-NEXT:    s_sub_i32 s1, 0, s12
+; GFX6-NEXT:    s_sub_i32 s1, 0, s16
 ; GFX6-NEXT:    s_ashr_i32 s0, s8, 31
-; GFX6-NEXT:    v_mul_f32_e32 v0, s16, v0
+; GFX6-NEXT:    v_mul_f32_e32 v0, s17, v0
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v1
 ; GFX6-NEXT:    s_xor_b32 s2, s0, s2
+; GFX6-NEXT:    s_ashr_i32 s3, s9, 31
 ; GFX6-NEXT:    v_mul_lo_u32 v2, s1, v0
 ; GFX6-NEXT:    s_add_i32 s1, s8, s0
-; GFX6-NEXT:    v_mul_f32_e32 v1, s16, v1
-; GFX6-NEXT:    s_xor_b32 s1, s1, s0
+; GFX6-NEXT:    v_mul_f32_e32 v1, s17, v1
+; GFX6-NEXT:    s_xor_b32 s0, s1, s0
 ; GFX6-NEXT:    v_mul_hi_u32 v2, v0, v2
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT:    s_sub_i32 s0, 0, s13
+; GFX6-NEXT:    s_sub_i32 s1, 0, s13
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
-; GFX6-NEXT:    v_mul_hi_u32 v0, s1, v0
-; GFX6-NEXT:    v_mul_lo_u32 v2, s0, v1
-; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s12
+; GFX6-NEXT:    v_mul_hi_u32 v0, s0, v0
+; GFX6-NEXT:    v_mul_lo_u32 v2, s1, v1
+; GFX6-NEXT:    s_add_i32 s1, s9, s3
+; GFX6-NEXT:    s_xor_b32 s8, s1, s3
+; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s16
 ; GFX6-NEXT:    v_mul_hi_u32 v2, v1, v2
 ; GFX6-NEXT:    v_add_i32_e32 v4, vcc, 1, v0
-; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s1, v3
-; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s12, v3
+; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s0, v3
+; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s16, v3
 ; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v4, s[0:1]
-; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s12, v3
-; GFX6-NEXT:    v_cndmask_b32_e64 v3, v3, v4, s[0:1]
-; GFX6-NEXT:    v_add_i32_e32 v4, vcc, 1, v0
+; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s16, v3
 ; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s12, v3
-; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
+; GFX6-NEXT:    v_cndmask_b32_e64 v3, v3, v4, s[0:1]
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, 1, v0
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s16, v3
+; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
 ; GFX6-NEXT:    v_xor_b32_e32 v0, s2, v0
-; GFX6-NEXT:    s_ashr_i32 s0, s9, 31
-; GFX6-NEXT:    s_add_i32 s1, s9, s0
 ; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s2, v0
-; GFX6-NEXT:    s_xor_b32 s2, s0, s3
+; GFX6-NEXT:    s_xor_b32 s2, s3, s12
 ; GFX6-NEXT:    s_ashr_i32 s3, s14, 31
-; GFX6-NEXT:    s_xor_b32 s1, s1, s0
 ; GFX6-NEXT:    s_add_i32 s0, s14, s3
-; GFX6-NEXT:    s_xor_b32 s9, s0, s3
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s9
-; GFX6-NEXT:    v_mul_hi_u32 v1, s1, v1
+; GFX6-NEXT:    s_xor_b32 s12, s0, s3
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s12
+; GFX6-NEXT:    v_mul_hi_u32 v1, s8, v1
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v3, v3
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s13
 ; GFX6-NEXT:    v_add_i32_e32 v4, vcc, 1, v1
-; GFX6-NEXT:    v_mul_f32_e32 v3, s16, v3
-; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s1, v2
+; GFX6-NEXT:    v_mul_f32_e32 v3, s17, v3
+; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s8, v2
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v3
 ; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s13, v2
 ; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v4, s[0:1]
 ; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s13, v2
 ; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, v4, s[0:1]
-; GFX6-NEXT:    s_sub_i32 s0, 0, s9
-; GFX6-NEXT:    v_mul_lo_u32 v5, s0, v3
 ; GFX6-NEXT:    v_add_i32_e32 v4, vcc, 1, v1
+; GFX6-NEXT:    s_sub_i32 s0, 0, s12
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s13, v2
+; GFX6-NEXT:    v_mul_lo_u32 v2, s0, v3
+; GFX6-NEXT:    s_ashr_i32 s8, s15, 31
+; GFX6-NEXT:    s_add_i32 s9, s15, s8
+; GFX6-NEXT:    s_xor_b32 s9, s9, s8
 ; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
-; GFX6-NEXT:    v_mul_hi_u32 v2, v3, v5
-; GFX6-NEXT:    v_xor_b32_e32 v1, s2, v1
-; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, s2, v1
-; GFX6-NEXT:    s_ashr_i32 s2, s15, 31
+; GFX6-NEXT:    v_mul_hi_u32 v2, v3, v2
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, s9
 ; GFX6-NEXT:    s_ashr_i32 s0, s10, 31
-; GFX6-NEXT:    s_add_i32 s8, s15, s2
 ; GFX6-NEXT:    s_add_i32 s1, s10, s0
-; GFX6-NEXT:    s_xor_b32 s8, s8, s2
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, s8
-; GFX6-NEXT:    s_xor_b32 s1, s1, s0
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v3, v4
+; GFX6-NEXT:    s_xor_b32 s1, s1, s0
 ; GFX6-NEXT:    v_mul_hi_u32 v2, s1, v2
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v4
-; GFX6-NEXT:    s_xor_b32 s3, s0, s3
-; GFX6-NEXT:    v_mul_lo_u32 v3, v2, s9
-; GFX6-NEXT:    v_mul_f32_e32 v4, s16, v4
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v4, v4
+; GFX6-NEXT:    v_xor_b32_e32 v1, s2, v1
+; GFX6-NEXT:    v_mul_f32_e32 v3, s17, v3
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v3
+; GFX6-NEXT:    v_mul_lo_u32 v4, v2, s12
+; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, s2, v1
+; GFX6-NEXT:    s_xor_b32 s2, s0, s3
+; GFX6-NEXT:    s_sub_i32 s0, 0, s9
+; GFX6-NEXT:    v_mul_lo_u32 v6, s0, v3
+; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s1, v4
 ; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v2
-; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s1, v3
-; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s9, v3
+; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s12, v4
 ; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, v5, s[0:1]
-; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s9, v3
-; GFX6-NEXT:    v_cndmask_b32_e64 v3, v3, v5, s[0:1]
-; GFX6-NEXT:    s_sub_i32 s0, 0, s8
-; GFX6-NEXT:    v_mul_lo_u32 v5, s0, v4
+; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s12, v4
+; GFX6-NEXT:    v_cndmask_b32_e64 v4, v4, v5, s[0:1]
+; GFX6-NEXT:    v_mul_hi_u32 v5, v3, v6
 ; GFX6-NEXT:    s_ashr_i32 s0, s11, 31
 ; GFX6-NEXT:    s_add_i32 s1, s11, s0
 ; GFX6-NEXT:    s_xor_b32 s1, s1, s0
-; GFX6-NEXT:    v_mul_hi_u32 v5, v4, v5
-; GFX6-NEXT:    v_add_i32_e32 v6, vcc, 1, v2
-; GFX6-NEXT:    s_xor_b32 s2, s0, s2
-; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GFX6-NEXT:    v_mul_hi_u32 v4, s1, v4
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v3
-; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc
-; GFX6-NEXT:    v_xor_b32_e32 v2, s3, v2
-; GFX6-NEXT:    v_mul_lo_u32 v3, v4, s8
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v4
-; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s3, v2
-; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s1, v3
-; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s8, v3
-; GFX6-NEXT:    v_cndmask_b32_e64 v4, v4, v5, s[0:1]
-; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s8, v3
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
+; GFX6-NEXT:    v_mul_hi_u32 v3, s1, v3
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v2
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s12, v4
+; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v4, v3, s9
+; GFX6-NEXT:    v_xor_b32_e32 v2, s2, v2
+; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s2, v2
+; GFX6-NEXT:    s_xor_b32 s2, s0, s8
+; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s1, v4
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v3
+; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s9, v4
 ; GFX6-NEXT:    v_cndmask_b32_e64 v3, v3, v5, s[0:1]
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v4
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v3
-; GFX6-NEXT:    v_cndmask_b32_e32 v3, v4, v5, vcc
+; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s9, v4
+; GFX6-NEXT:    v_cndmask_b32_e64 v4, v4, v5, s[0:1]
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v3
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v4
+; GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
 ; GFX6-NEXT:    v_xor_b32_e32 v3, s2, v3
 ; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s2, v3
 ; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
@@ -2219,10 +2219,11 @@
 ; GFX6-NEXT:    s_mov_b32 s13, 0x4f7ffffe
 ; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
 ; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    s_ashr_i32 s2, s8, 31
-; GFX6-NEXT:    s_add_i32 s8, s8, s2
-; GFX6-NEXT:    s_xor_b32 s12, s8, s2
+; GFX6-NEXT:    s_ashr_i32 s12, s8, 31
+; GFX6-NEXT:    s_add_i32 s8, s8, s12
+; GFX6-NEXT:    s_xor_b32 s12, s8, s12
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s12
 ; GFX6-NEXT:    s_ashr_i32 s8, s9, 31
 ; GFX6-NEXT:    s_add_i32 s9, s9, s8
@@ -2241,78 +2242,77 @@
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GFX6-NEXT:    s_sub_i32 s9, 0, s14
 ; GFX6-NEXT:    v_mul_hi_u32 v2, v0, v2
-; GFX6-NEXT:    s_mov_b32 s2, -1
+; GFX6-NEXT:    v_mul_lo_u32 v3, s9, v1
+; GFX6-NEXT:    s_ashr_i32 s9, s5, 31
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
 ; GFX6-NEXT:    v_mul_hi_u32 v0, s4, v0
-; GFX6-NEXT:    v_mul_lo_u32 v2, s9, v1
-; GFX6-NEXT:    s_ashr_i32 s9, s5, 31
+; GFX6-NEXT:    v_mul_hi_u32 v2, v1, v3
 ; GFX6-NEXT:    s_add_i32 s5, s5, s9
+; GFX6-NEXT:    s_xor_b32 s5, s5, s9
 ; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s12
-; GFX6-NEXT:    v_mul_hi_u32 v2, v1, v2
+; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
+; GFX6-NEXT:    v_mul_hi_u32 v1, s5, v1
 ; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
-; GFX6-NEXT:    s_xor_b32 s4, s5, s9
-; GFX6-NEXT:    s_ashr_i32 s5, s10, 31
-; GFX6-NEXT:    s_add_i32 s10, s10, s5
-; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s12, v0
+; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s12, v0
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s12, v0
-; GFX6-NEXT:    s_xor_b32 s10, s10, s5
-; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
-; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v2, s10
-; GFX6-NEXT:    v_mul_hi_u32 v1, s4, v1
-; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s12, v0
+; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX6-NEXT:    s_ashr_i32 s4, s10, 31
+; GFX6-NEXT:    s_add_i32 s10, s10, s4
+; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s12, v0
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s12, v0
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v2
+; GFX6-NEXT:    s_xor_b32 s10, s10, s4
+; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v2, s10
 ; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s14
-; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
 ; GFX6-NEXT:    v_xor_b32_e32 v0, s8, v0
-; GFX6-NEXT:    v_mul_f32_e32 v2, s13, v2
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v2
-; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s4, v1
-; GFX6-NEXT:    s_sub_i32 s4, 0, s10
 ; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s8, v0
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v2
+; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s5, v1
 ; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s14, v1
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s14, v1
-; GFX6-NEXT:    v_mul_lo_u32 v4, s4, v2
+; GFX6-NEXT:    v_mul_f32_e32 v2, s13, v2
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v2
 ; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
 ; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s14, v1
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s14, v1
+; GFX6-NEXT:    s_sub_i32 s4, 0, s10
 ; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
-; GFX6-NEXT:    v_mul_hi_u32 v3, v2, v4
+; GFX6-NEXT:    v_mul_lo_u32 v3, s4, v2
+; GFX6-NEXT:    s_ashr_i32 s4, s11, 31
+; GFX6-NEXT:    s_add_i32 s5, s11, s4
+; GFX6-NEXT:    s_xor_b32 s8, s5, s4
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, s8
+; GFX6-NEXT:    v_mul_hi_u32 v3, v2, v3
 ; GFX6-NEXT:    s_ashr_i32 s4, s6, 31
 ; GFX6-NEXT:    s_add_i32 s5, s6, s4
-; GFX6-NEXT:    s_ashr_i32 s6, s11, 31
-; GFX6-NEXT:    s_add_i32 s8, s11, s6
-; GFX6-NEXT:    s_xor_b32 s8, s8, s6
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v4
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s8
 ; GFX6-NEXT:    s_xor_b32 s5, s5, s4
 ; GFX6-NEXT:    v_mul_hi_u32 v2, s5, v2
+; GFX6-NEXT:    v_mul_f32_e32 v3, s13, v4
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v3
+; GFX6-NEXT:    s_sub_i32 s6, 0, s8
+; GFX6-NEXT:    v_mul_lo_u32 v2, v2, s10
 ; GFX6-NEXT:    v_xor_b32_e32 v1, s9, v1
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v3, v3
+; GFX6-NEXT:    v_mul_lo_u32 v4, s6, v3
 ; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, s9, v1
-; GFX6-NEXT:    v_mul_lo_u32 v2, v2, s10
-; GFX6-NEXT:    v_mul_f32_e32 v3, s13, v3
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v3
 ; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s5, v2
-; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s10, v2
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v2
-; GFX6-NEXT:    s_sub_i32 s5, 0, s8
-; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v4, s5, v3
 ; GFX6-NEXT:    s_ashr_i32 s5, s7, 31
+; GFX6-NEXT:    v_mul_hi_u32 v4, v3, v4
 ; GFX6-NEXT:    s_add_i32 s6, s7, s5
 ; GFX6-NEXT:    s_xor_b32 s6, s6, s5
-; GFX6-NEXT:    v_mul_hi_u32 v4, v3, v4
 ; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s10, v2
 ; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
 ; GFX6-NEXT:    v_mul_hi_u32 v3, s6, v3
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v2
 ; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
-; GFX6-NEXT:    v_xor_b32_e32 v2, s4, v2
+; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s10, v2
 ; GFX6-NEXT:    v_mul_lo_u32 v3, v3, s8
-; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s4, v2
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v2
+; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
+; GFX6-NEXT:    v_xor_b32_e32 v2, s4, v2
 ; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s6, v3
+; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s4, v2
 ; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s8, v3
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v3
 ; GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
@@ -2535,50 +2535,50 @@
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s9
 ; GFX6-NEXT:    s_lshr_b32 s9, s0, 16
 ; GFX6-NEXT:    s_and_b32 s0, s0, s8
-; GFX6-NEXT:    s_lshr_b32 s2, s2, 16
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s2
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s0
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, s9
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v5, v3
-; GFX6-NEXT:    s_and_b32 s2, s3, s8
+; GFX6-NEXT:    s_lshr_b32 s2, s2, 16
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s2
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v5, s9
 ; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
 ; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v4, v2
 ; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v2
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v6, v3
 ; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
-; GFX6-NEXT:    v_mul_f32_e32 v1, v4, v5
-; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
-; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
-; GFX6-NEXT:    v_mad_f32 v2, -v1, v3, v4
+; GFX6-NEXT:    s_and_b32 s2, s3, s8
+; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v4, vcc
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, s2
+; GFX6-NEXT:    v_mul_f32_e32 v1, v5, v6
 ; GFX6-NEXT:    s_lshr_b32 s0, s1, 16
-; GFX6-NEXT:    s_and_b32 s1, s1, s8
 ; GFX6-NEXT:    s_lshr_b32 s10, s3, 16
-; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v3
+; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
+; GFX6-NEXT:    s_and_b32 s1, s1, s8
+; GFX6-NEXT:    v_mad_f32 v2, -v1, v3, v5
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s10
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v5, s1
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v6, v4
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v7, s10
+; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v3
 ; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, 0, v1, vcc
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v7, v3
-; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
 ; GFX6-NEXT:    v_mul_f32_e32 v1, v5, v6
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v6, s0
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s0
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v6, v7
 ; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX6-NEXT:    v_mad_f32 v5, -v1, v4, v5
-; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v5|, v4
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT:    v_mul_f32_e32 v4, v6, v7
-; GFX6-NEXT:    v_trunc_f32_e32 v4, v4
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v5, v4
+; GFX6-NEXT:    v_mul_f32_e32 v6, v3, v6
+; GFX6-NEXT:    v_trunc_f32_e32 v6, v6
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v8, v6
+; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v5|, v4
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX6-NEXT:    v_mad_f32 v4, -v4, v3, v6
-; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v3
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
-; GFX6-NEXT:    v_and_b32_e32 v0, s8, v0
+; GFX6-NEXT:    v_mad_f32 v3, -v6, v7, v3
+; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v7
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v8, vcc
 ; GFX6-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
 ; GFX6-NEXT:    v_and_b32_e32 v1, s8, v1
+; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX6-NEXT:    v_and_b32_e32 v0, s8, v0
 ; GFX6-NEXT:    v_or_b32_e32 v1, v1, v3
 ; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
 ; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
@@ -2596,47 +2596,47 @@
 ; GFX9-NEXT:    s_lshr_b32 s0, s4, 16
 ; GFX9-NEXT:    s_and_b32 s4, s4, s8
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s4
-; GFX9-NEXT:    s_lshr_b32 s4, s6, 16
 ; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v0
+; GFX9-NEXT:    s_lshr_b32 s4, s6, 16
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, s4
-; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, s0
-; GFX9-NEXT:    s_and_b32 s0, s7, s8
+; GFX9-NEXT:    v_cvt_f32_u32_e32 v6, s0
 ; GFX9-NEXT:    v_mul_f32_e32 v3, v1, v3
-; GFX9-NEXT:    v_rcp_iflag_f32_e32 v6, v4
 ; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
+; GFX9-NEXT:    v_cvt_u32_f32_e32 v5, v3
 ; GFX9-NEXT:    v_mad_f32 v1, -v3, v0, v1
-; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
+; GFX9-NEXT:    v_rcp_iflag_f32_e32 v7, v4
 ; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
-; GFX9-NEXT:    v_mul_f32_e32 v1, v5, v6
-; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
-; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v3, vcc
-; GFX9-NEXT:    v_mad_f32 v3, -v1, v4, v5
+; GFX9-NEXT:    s_and_b32 s0, s7, s8
+; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v5, vcc
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, s0
-; GFX9-NEXT:    s_and_b32 s0, s5, s8
+; GFX9-NEXT:    v_mul_f32_e32 v1, v6, v7
 ; GFX9-NEXT:    s_lshr_b32 s6, s7, 16
-; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v4
+; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
+; GFX9-NEXT:    s_and_b32 s0, s5, s8
+; GFX9-NEXT:    v_mad_f32 v3, -v1, v4, v6
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, s6
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v6, s0
 ; GFX9-NEXT:    v_rcp_iflag_f32_e32 v7, v5
+; GFX9-NEXT:    v_cvt_f32_u32_e32 v8, s6
+; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v4
 ; GFX9-NEXT:    s_lshr_b32 s1, s5, 16
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v1, vcc
-; GFX9-NEXT:    v_rcp_iflag_f32_e32 v8, v4
 ; GFX9-NEXT:    v_mul_f32_e32 v1, v6, v7
-; GFX9-NEXT:    v_cvt_f32_u32_e32 v7, s1
+; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, s1
+; GFX9-NEXT:    v_rcp_iflag_f32_e32 v7, v8
 ; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX9-NEXT:    v_mad_f32 v6, -v1, v5, v6
-; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v6|, v5
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX9-NEXT:    v_mul_f32_e32 v5, v7, v8
-; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
-; GFX9-NEXT:    v_cvt_u32_f32_e32 v6, v5
+; GFX9-NEXT:    v_mul_f32_e32 v7, v4, v7
+; GFX9-NEXT:    v_trunc_f32_e32 v7, v7
+; GFX9-NEXT:    v_cvt_u32_f32_e32 v9, v7
+; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v6|, v5
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
-; GFX9-NEXT:    v_mad_f32 v5, -v5, v4, v7
-; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v5|, v4
+; GFX9-NEXT:    v_mad_f32 v4, -v7, v8, v4
+; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v8
 ; GFX9-NEXT:    v_mov_b32_e32 v5, 0xffff
 ; GFX9-NEXT:    v_and_b32_e32 v0, v5, v0
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v6, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v9, vcc
 ; GFX9-NEXT:    v_and_b32_e32 v1, v5, v1
 ; GFX9-NEXT:    v_lshl_or_b32 v1, v4, 16, v1
 ; GFX9-NEXT:    v_lshl_or_b32 v0, v3, 16, v0
@@ -2751,60 +2751,60 @@
 ; GFX6-NEXT:    s_and_b32 s9, s2, s8
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s9
 ; GFX6-NEXT:    s_and_b32 s10, s0, s8
-; GFX6-NEXT:    s_lshr_b32 s11, s2, 16
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s10
+; GFX6-NEXT:    s_lshr_b32 s11, s2, 16
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s11
 ; GFX6-NEXT:    s_lshr_b32 s9, s0, 16
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, s9
 ; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v5, v3
 ; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
 ; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v2
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v5, v3
 ; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
-; GFX6-NEXT:    v_mul_f32_e32 v1, v4, v5
-; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
+; GFX6-NEXT:    s_lshr_b32 s12, s3, 16
 ; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v1
-; GFX6-NEXT:    v_mad_f32 v1, -v1, v3, v4
-; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v3
+; GFX6-NEXT:    v_mul_f32_e32 v1, v4, v5
 ; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s2
+; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX6-NEXT:    s_and_b32 s2, s3, s8
-; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v2, s2
+; GFX6-NEXT:    v_mad_f32 v2, -v1, v3, v4
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, s2
 ; GFX6-NEXT:    s_and_b32 s2, s1, s8
-; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s11
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s2
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v2
-; GFX6-NEXT:    s_lshr_b32 s12, s3, 16
-; GFX6-NEXT:    v_sub_i32_e32 v5, vcc, s9, v1
-; GFX6-NEXT:    s_lshr_b32 s10, s1, 16
-; GFX6-NEXT:    v_mul_f32_e32 v1, v3, v4
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, s12
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v6, s10
-; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
-; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s0, v0
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v7, v4
-; GFX6-NEXT:    v_mad_f32 v3, -v1, v2, v3
-; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v2
+; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v3
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s12
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v5, s2
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v6, v4
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT:    v_mul_f32_e32 v2, v6, v7
+; GFX6-NEXT:    s_lshr_b32 s10, s1, 16
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v7, s10
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v8, v3
+; GFX6-NEXT:    v_mul_f32_e32 v2, v5, v6
 ; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX6-NEXT:    v_mad_f32 v2, -v2, v4, v6
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v6, v2
+; GFX6-NEXT:    v_mad_f32 v2, -v2, v4, v5
 ; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v4
-; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, 0, v3, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s3
-; GFX6-NEXT:    v_mul_lo_u32 v2, v2, s12
-; GFX6-NEXT:    v_and_b32_e32 v0, s8, v0
-; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s1, v1
-; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s10, v2
+; GFX6-NEXT:    v_mul_f32_e32 v4, v7, v8
+; GFX6-NEXT:    v_trunc_f32_e32 v4, v4
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v5, v4
+; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, 0, v6, vcc
+; GFX6-NEXT:    v_mad_f32 v4, -v4, v3, v7
+; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v3
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s11
+; GFX6-NEXT:    v_mul_lo_u32 v2, v2, s3
+; GFX6-NEXT:    v_mul_lo_u32 v3, v3, s12
+; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s0, v0
+; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s9, v1
+; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s1, v2
+; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s10, v3
 ; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
 ; GFX6-NEXT:    v_and_b32_e32 v1, s8, v1
 ; GFX6-NEXT:    v_or_b32_e32 v1, v1, v2
-; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v5
+; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v4
+; GFX6-NEXT:    v_and_b32_e32 v0, s8, v0
 ; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
 ; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; GFX6-NEXT:    s_endpgm
@@ -2846,19 +2846,19 @@
 ; GFX9-NEXT:    v_rcp_iflag_f32_e32 v7, v5
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GFX9-NEXT:    s_lshr_b32 s1, s5, 16
-; GFX9-NEXT:    v_rcp_iflag_f32_e32 v8, v4
+; GFX9-NEXT:    v_cvt_f32_u32_e32 v8, s1
+; GFX9-NEXT:    v_rcp_iflag_f32_e32 v9, v4
 ; GFX9-NEXT:    v_mul_f32_e32 v3, v6, v7
-; GFX9-NEXT:    v_cvt_f32_u32_e32 v7, s1
 ; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
-; GFX9-NEXT:    v_mad_f32 v6, -v3, v5, v6
-; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v6|, v5
-; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
-; GFX9-NEXT:    v_mul_f32_e32 v5, v7, v8
+; GFX9-NEXT:    v_cvt_u32_f32_e32 v7, v3
+; GFX9-NEXT:    v_mad_f32 v3, -v3, v5, v6
+; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v5
+; GFX9-NEXT:    v_mul_f32_e32 v5, v8, v9
 ; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v6, v5
-; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
-; GFX9-NEXT:    v_mad_f32 v5, -v5, v4, v7
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v7, vcc
+; GFX9-NEXT:    v_mad_f32 v5, -v5, v4, v8
 ; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v5|, v4
 ; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v6, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v1, v1, s9
@@ -3260,83 +3260,83 @@
 ; GFX6-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX6-NEXT:    s_mov_b32 s6, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    s_sext_i32_i16 s8, s2
-; GFX6-NEXT:    v_cvt_f32_i32_e32 v0, s8
-; GFX6-NEXT:    s_sext_i32_i16 s9, s0
-; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s9
-; GFX6-NEXT:    s_xor_b32 s8, s9, s8
+; GFX6-NEXT:    s_sext_i32_i16 s9, s2
+; GFX6-NEXT:    v_cvt_f32_i32_e32 v0, s9
+; GFX6-NEXT:    s_sext_i32_i16 s8, s0
+; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s8
+; GFX6-NEXT:    s_xor_b32 s9, s8, s9
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
-; GFX6-NEXT:    s_ashr_i32 s8, s8, 30
+; GFX6-NEXT:    s_ashr_i32 s8, s9, 30
 ; GFX6-NEXT:    s_or_b32 s8, s8, 1
-; GFX6-NEXT:    v_mov_b32_e32 v3, s8
+; GFX6-NEXT:    s_ashr_i32 s10, s2, 16
 ; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
 ; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
+; GFX6-NEXT:    v_cvt_i32_f32_e32 v4, v2
 ; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
-; GFX6-NEXT:    v_cvt_i32_f32_e32 v2, v2
 ; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
+; GFX6-NEXT:    v_mov_b32_e32 v3, s8
+; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s10
 ; GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
-; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
 ; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s2
-; GFX6-NEXT:    s_ashr_i32 s2, s2, 16
-; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s2
-; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s0, v0
-; GFX6-NEXT:    s_ashr_i32 s0, s0, 16
-; GFX6-NEXT:    v_cvt_f32_i32_e32 v2, s0
+; GFX6-NEXT:    s_ashr_i32 s2, s0, 16
+; GFX6-NEXT:    v_cvt_f32_i32_e32 v2, s2
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v3, v1
-; GFX6-NEXT:    s_xor_b32 s8, s0, s2
+; GFX6-NEXT:    s_xor_b32 s8, s2, s10
 ; GFX6-NEXT:    s_ashr_i32 s8, s8, 30
 ; GFX6-NEXT:    s_or_b32 s8, s8, 1
 ; GFX6-NEXT:    v_mul_f32_e32 v3, v2, v3
 ; GFX6-NEXT:    v_trunc_f32_e32 v3, v3
 ; GFX6-NEXT:    v_mad_f32 v2, -v3, v1, v2
-; GFX6-NEXT:    v_cvt_i32_f32_e32 v3, v3
 ; GFX6-NEXT:    v_mov_b32_e32 v4, s8
+; GFX6-NEXT:    s_sext_i32_i16 s8, s3
 ; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v1|
+; GFX6-NEXT:    v_cvt_i32_f32_e32 v3, v3
+; GFX6-NEXT:    v_cvt_f32_i32_e32 v2, s8
 ; GFX6-NEXT:    v_cndmask_b32_e32 v1, 0, v4, vcc
+; GFX6-NEXT:    s_sext_i32_i16 s9, s1
 ; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
-; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s2
-; GFX6-NEXT:    s_sext_i32_i16 s2, s3
-; GFX6-NEXT:    v_cvt_f32_i32_e32 v2, s2
-; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s0, v1
-; GFX6-NEXT:    s_sext_i32_i16 s0, s1
-; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s0
+; GFX6-NEXT:    v_cvt_f32_i32_e32 v3, s9
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v2
-; GFX6-NEXT:    s_xor_b32 s0, s0, s2
-; GFX6-NEXT:    s_ashr_i32 s0, s0, 30
-; GFX6-NEXT:    s_or_b32 s0, s0, 1
-; GFX6-NEXT:    v_mul_f32_e32 v4, v1, v4
+; GFX6-NEXT:    s_xor_b32 s8, s9, s8
+; GFX6-NEXT:    s_ashr_i32 s8, s8, 30
+; GFX6-NEXT:    s_or_b32 s8, s8, 1
+; GFX6-NEXT:    v_mul_f32_e32 v4, v3, v4
 ; GFX6-NEXT:    v_trunc_f32_e32 v4, v4
-; GFX6-NEXT:    v_mad_f32 v1, -v4, v2, v1
-; GFX6-NEXT:    v_mov_b32_e32 v5, s0
-; GFX6-NEXT:    s_ashr_i32 s0, s3, 16
-; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v2|
+; GFX6-NEXT:    v_mad_f32 v3, -v4, v2, v3
 ; GFX6-NEXT:    v_cvt_i32_f32_e32 v4, v4
-; GFX6-NEXT:    v_cvt_f32_i32_e32 v2, s0
-; GFX6-NEXT:    v_cndmask_b32_e32 v1, 0, v5, vcc
-; GFX6-NEXT:    s_ashr_i32 s2, s1, 16
-; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v4
-; GFX6-NEXT:    v_cvt_f32_i32_e32 v4, s2
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v5, v2
-; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s3
-; GFX6-NEXT:    s_xor_b32 s3, s2, s0
-; GFX6-NEXT:    s_ashr_i32 s3, s3, 30
+; GFX6-NEXT:    v_mov_b32_e32 v5, s8
+; GFX6-NEXT:    s_ashr_i32 s8, s3, 16
+; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v2|
+; GFX6-NEXT:    v_cvt_f32_i32_e32 v3, s8
+; GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v5, vcc
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
+; GFX6-NEXT:    v_mul_lo_u32 v2, v2, s3
+; GFX6-NEXT:    s_ashr_i32 s3, s1, 16
+; GFX6-NEXT:    v_cvt_f32_i32_e32 v4, s3
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v5, v3
+; GFX6-NEXT:    s_xor_b32 s9, s3, s8
+; GFX6-NEXT:    s_ashr_i32 s9, s9, 30
+; GFX6-NEXT:    s_or_b32 s9, s9, 1
 ; GFX6-NEXT:    v_mul_f32_e32 v5, v4, v5
 ; GFX6-NEXT:    v_trunc_f32_e32 v5, v5
-; GFX6-NEXT:    v_mad_f32 v4, -v5, v2, v4
+; GFX6-NEXT:    v_mad_f32 v4, -v5, v3, v4
 ; GFX6-NEXT:    v_cvt_i32_f32_e32 v5, v5
-; GFX6-NEXT:    s_or_b32 s3, s3, 1
-; GFX6-NEXT:    v_mov_b32_e32 v6, s3
-; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v2|
-; GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v6, vcc
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
-; GFX6-NEXT:    v_mul_lo_u32 v2, v2, s0
+; GFX6-NEXT:    v_mov_b32_e32 v6, s9
+; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v3|
+; GFX6-NEXT:    v_cndmask_b32_e32 v3, 0, v6, vcc
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
+; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s10
+; GFX6-NEXT:    v_mul_lo_u32 v3, v3, s8
+; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s0, v0
 ; GFX6-NEXT:    s_mov_b32 s0, 0xffff
-; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s1, v1
-; GFX6-NEXT:    v_and_b32_e32 v1, s0, v1
-; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s2, v2
+; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s2, v1
+; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s1, v2
+; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s3, v3
 ; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX6-NEXT:    v_and_b32_e32 v1, s0, v1
 ; GFX6-NEXT:    v_or_b32_e32 v1, v1, v2
-; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v3
+; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v4
 ; GFX6-NEXT:    v_and_b32_e32 v0, s0, v0
 ; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
 ; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
@@ -3478,23 +3478,23 @@
 ;
 ; GFX9-LABEL: udiv_i3:
 ; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
-; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
-; GFX9-NEXT:    v_mov_b32_e32 v2, 0
+; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; GFX9-NEXT:    v_mov_b32_e32 v4, 0
+; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    s_bfe_u32 s0, s4, 0x30008
-; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v0, s0
+; GFX9-NEXT:    s_bfe_u32 s3, s2, 0x30008
+; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v0, s3
 ; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v0
-; GFX9-NEXT:    s_and_b32 s0, s4, 7
-; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v3, s0
-; GFX9-NEXT:    v_mul_f32_e32 v1, v3, v1
+; GFX9-NEXT:    s_and_b32 s2, s2, 7
+; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v2, s2
+; GFX9-NEXT:    v_mul_f32_e32 v1, v2, v1
 ; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
-; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v1
-; GFX9-NEXT:    v_mad_f32 v1, -v1, v0, v3
+; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v1
+; GFX9-NEXT:    v_mad_f32 v1, -v1, v0, v2
 ; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
-; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v4, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v3, vcc
 ; GFX9-NEXT:    v_and_b32_e32 v0, 7, v0
-; GFX9-NEXT:    global_store_byte v2, v0, s[2:3]
+; GFX9-NEXT:    global_store_byte v4, v0, s[0:1]
 ; GFX9-NEXT:    s_endpgm
   %r = udiv i3 %x, %y
   store i3 %r, i3 addrspace(1)* %out
@@ -3527,27 +3527,27 @@
 ;
 ; GFX6-LABEL: urem_i3:
 ; GFX6:       ; %bb.0:
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX6-NEXT:    s_mov_b32 s3, 0xf000
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    s_bfe_u32 s1, s0, 0x30008
-; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v0, s1
+; GFX6-NEXT:    s_bfe_u32 s2, s4, 0x30008
+; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v0, s2
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v0
-; GFX6-NEXT:    s_and_b32 s2, s0, 7
+; GFX6-NEXT:    s_and_b32 s2, s4, 7
 ; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v2, s2
-; GFX6-NEXT:    s_lshr_b32 s1, s0, 8
+; GFX6-NEXT:    s_lshr_b32 s2, s4, 8
 ; GFX6-NEXT:    v_mul_f32_e32 v1, v2, v1
 ; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v1
 ; GFX6-NEXT:    v_mad_f32 v1, -v1, v0, v2
 ; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
 ; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s1
-; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s0, v0
+; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s2
+; GFX6-NEXT:    s_mov_b32 s2, -1
+; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
 ; GFX6-NEXT:    v_and_b32_e32 v0, 7, v0
-; GFX6-NEXT:    buffer_store_byte v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_byte v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: urem_i3:
@@ -3559,8 +3559,8 @@
 ; GFX9-NEXT:    s_bfe_u32 s3, s2, 0x30008
 ; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v0, s3
 ; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v0
-; GFX9-NEXT:    s_and_b32 s4, s2, 7
-; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v2, s4
+; GFX9-NEXT:    s_and_b32 s3, s2, 7
+; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v2, s3
 ; GFX9-NEXT:    s_lshr_b32 s3, s2, 8
 ; GFX9-NEXT:    v_mul_f32_e32 v1, v2, v1
 ; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
@@ -3692,32 +3692,32 @@
 ;
 ; GFX6-LABEL: srem_i3:
 ; GFX6:       ; %bb.0:
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    s_bfe_i32 s1, s0, 0x30008
-; GFX6-NEXT:    v_cvt_f32_i32_e32 v0, s1
-; GFX6-NEXT:    s_bfe_i32 s3, s0, 0x30000
-; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s3
-; GFX6-NEXT:    s_xor_b32 s1, s3, s1
+; GFX6-NEXT:    s_bfe_i32 s2, s4, 0x30008
+; GFX6-NEXT:    v_cvt_f32_i32_e32 v0, s2
+; GFX6-NEXT:    s_bfe_i32 s5, s4, 0x30000
+; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s5
+; GFX6-NEXT:    s_xor_b32 s2, s5, s2
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
-; GFX6-NEXT:    s_ashr_i32 s1, s1, 30
-; GFX6-NEXT:    s_or_b32 s1, s1, 1
-; GFX6-NEXT:    v_mov_b32_e32 v3, s1
+; GFX6-NEXT:    s_ashr_i32 s2, s2, 30
+; GFX6-NEXT:    s_or_b32 s2, s2, 1
+; GFX6-NEXT:    v_mov_b32_e32 v3, s2
 ; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
 ; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
 ; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
 ; GFX6-NEXT:    v_cvt_i32_f32_e32 v2, v2
 ; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
 ; GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
-; GFX6-NEXT:    s_lshr_b32 s2, s0, 8
+; GFX6-NEXT:    s_lshr_b32 s3, s4, 8
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
-; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s2
-; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s0, v0
+; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s3
+; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_mov_b32 s2, -1
+; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
 ; GFX6-NEXT:    v_and_b32_e32 v0, 7, v0
-; GFX6-NEXT:    buffer_store_byte v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_byte v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: srem_i3:
@@ -3830,41 +3830,41 @@
 ; GFX6-NEXT:    s_and_b32 s6, s0, s8
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s6
 ; GFX6-NEXT:    s_and_b32 s6, s2, s8
-; GFX6-NEXT:    s_lshr_b32 s0, s0, 16
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s0
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s6
+; GFX6-NEXT:    s_lshr_b32 s0, s0, 16
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s0
 ; GFX6-NEXT:    s_lshr_b32 s0, s2, 16
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, s0
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v5, v3
 ; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
 ; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
 ; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v2
-; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
-; GFX6-NEXT:    v_mul_f32_e32 v1, v4, v5
-; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX6-NEXT:    s_and_b32 s0, s1, s8
-; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
-; GFX6-NEXT:    v_mad_f32 v2, -v1, v3, v4
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, s0
+; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s0
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v2
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v5, v3
 ; GFX6-NEXT:    s_and_b32 s0, s3, s8
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v6, v1
+; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
+; GFX6-NEXT:    v_mul_f32_e32 v2, v4, v5
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v5, s0
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v6, v4
-; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v3
-; GFX6-NEXT:    s_mov_b32 s6, -1
-; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX6-NEXT:    v_mul_f32_e32 v2, v5, v6
 ; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v2
-; GFX6-NEXT:    v_mad_f32 v2, -v2, v4, v5
-; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v4
-; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX6-NEXT:    v_mad_f32 v4, -v2, v3, v4
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v2
+; GFX6-NEXT:    v_mul_f32_e32 v6, v5, v6
+; GFX6-NEXT:    v_trunc_f32_e32 v6, v6
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v7, v6
+; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v3
+; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc
+; GFX6-NEXT:    v_mad_f32 v3, -v6, v1, v5
+; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v1
+; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v7, vcc
+; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
 ; GFX6-NEXT:    v_and_b32_e32 v0, s8, v0
-; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, 0, v3, vcc
-; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX6-NEXT:    buffer_store_short v2, off, s[4:7], 0 offset:4
+; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
+; GFX6-NEXT:    buffer_store_short v1, off, s[4:7], 0 offset:4
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -3874,45 +3874,45 @@
 ; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
 ; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[0:1], 0x34
 ; GFX9-NEXT:    s_mov_b32 s8, 0xffff
-; GFX9-NEXT:    v_mov_b32_e32 v1, 0
+; GFX9-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NEXT:    s_lshr_b32 s1, s4, 16
 ; GFX9-NEXT:    s_and_b32 s0, s6, s8
-; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s0
+; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s0
 ; GFX9-NEXT:    s_and_b32 s0, s4, s8
-; GFX9-NEXT:    s_lshr_b32 s1, s6, 16
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v2, s0
-; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v0
-; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, s1
-; GFX9-NEXT:    s_lshr_b32 s0, s4, 16
+; GFX9-NEXT:    s_lshr_b32 s0, s6, 16
+; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v1
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, s0
+; GFX9-NEXT:    s_and_b32 s0, s7, s8
+; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, s1
 ; GFX9-NEXT:    v_mul_f32_e32 v3, v2, v3
-; GFX9-NEXT:    v_rcp_iflag_f32_e32 v6, v4
 ; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
-; GFX9-NEXT:    v_mad_f32 v2, -v3, v0, v2
-; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
-; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v0
-; GFX9-NEXT:    v_mul_f32_e32 v2, v5, v6
-; GFX9-NEXT:    v_trunc_f32_e32 v2, v2
-; GFX9-NEXT:    s_and_b32 s0, s7, s8
-; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v3, vcc
-; GFX9-NEXT:    v_mad_f32 v3, -v2, v4, v5
-; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, s0
+; GFX9-NEXT:    v_mad_f32 v2, -v3, v1, v2
+; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v1
+; GFX9-NEXT:    v_cvt_u32_f32_e32 v6, v3
+; GFX9-NEXT:    v_rcp_iflag_f32_e32 v7, v5
+; GFX9-NEXT:    v_cvt_f32_u32_e32 v2, s0
 ; GFX9-NEXT:    s_and_b32 s0, s5, s8
+; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v6, vcc
+; GFX9-NEXT:    v_mul_f32_e32 v3, v4, v7
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v6, s0
-; GFX9-NEXT:    v_cvt_u32_f32_e32 v2, v2
-; GFX9-NEXT:    v_rcp_iflag_f32_e32 v7, v5
-; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v4
-; GFX9-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, 0, v2, vcc
-; GFX9-NEXT:    v_mul_f32_e32 v3, v6, v7
+; GFX9-NEXT:    v_rcp_iflag_f32_e32 v7, v2
 ; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
-; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v3
-; GFX9-NEXT:    v_mad_f32 v3, -v3, v5, v6
-; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v5
-; GFX9-NEXT:    v_lshl_or_b32 v0, v2, 16, v0
-; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
-; GFX9-NEXT:    global_store_short v1, v3, s[2:3] offset:4
-; GFX9-NEXT:    global_store_dword v1, v0, s[2:3]
+; GFX9-NEXT:    v_mad_f32 v4, -v3, v5, v4
+; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
+; GFX9-NEXT:    v_mul_f32_e32 v7, v6, v7
+; GFX9-NEXT:    v_trunc_f32_e32 v7, v7
+; GFX9-NEXT:    v_cvt_u32_f32_e32 v8, v7
+; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v5
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
+; GFX9-NEXT:    v_mad_f32 v4, -v7, v2, v6
+; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v2
+; GFX9-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, 0, v8, vcc
+; GFX9-NEXT:    v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT:    global_store_short v0, v2, s[2:3] offset:4
+; GFX9-NEXT:    global_store_dword v0, v1, s[2:3]
 ; GFX9-NEXT:    s_endpgm
   %r = udiv <3 x i16> %x, %y
   store <3 x i16> %r, <3 x i16> addrspace(1)* %out
@@ -3998,52 +3998,52 @@
 ; GFX6-NEXT:    s_mov_b32 s8, 0xffff
 ; GFX6-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v1, s2
+; GFX6-NEXT:    v_mov_b32_e32 v3, s2
 ; GFX6-NEXT:    s_and_b32 s6, s0, s8
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s6
 ; GFX6-NEXT:    s_and_b32 s6, s2, s8
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v2, s6
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s6
 ; GFX6-NEXT:    v_mov_b32_e32 v4, s0
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v3, v0
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
 ; GFX6-NEXT:    v_alignbit_b32 v4, s1, v4, 16
 ; GFX6-NEXT:    v_and_b32_e32 v5, s8, v4
-; GFX6-NEXT:    v_alignbit_b32 v1, s3, v1, 16
-; GFX6-NEXT:    v_mul_f32_e32 v3, v2, v3
-; GFX6-NEXT:    v_trunc_f32_e32 v3, v3
-; GFX6-NEXT:    v_mad_f32 v2, -v3, v0, v2
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v6, v3
-; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v0
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v2, v5
-; GFX6-NEXT:    v_and_b32_e32 v3, s8, v1
-; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v6, vcc
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v5, v5
+; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
+; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
+; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v2
+; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
+; GFX6-NEXT:    v_alignbit_b32 v3, s3, v3, 16
+; GFX6-NEXT:    v_and_b32_e32 v6, s8, v3
+; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s0
 ; GFX6-NEXT:    s_and_b32 s0, s1, s8
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, v3
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v5, v2
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v6, s0
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v2, s0
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v6, v6
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v7, v5
 ; GFX6-NEXT:    s_and_b32 s0, s3, s8
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v7, s0
-; GFX6-NEXT:    v_mul_f32_e32 v5, v3, v5
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v8, s0
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v9, v2
+; GFX6-NEXT:    v_mul_f32_e32 v1, v6, v7
+; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v7, v1
+; GFX6-NEXT:    v_mad_f32 v1, -v1, v5, v6
+; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v5
+; GFX6-NEXT:    v_mul_f32_e32 v5, v8, v9
 ; GFX6-NEXT:    v_trunc_f32_e32 v5, v5
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v8, v6
-; GFX6-NEXT:    v_mad_f32 v3, -v5, v2, v3
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v5, v5
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v6, v5
+; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v7, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v1, v1, v4
+; GFX6-NEXT:    v_mad_f32 v4, -v5, v2, v8
+; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v2
+; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, 0, v6, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v2, v2, s1
 ; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
-; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v2
-; GFX6-NEXT:    v_mul_f32_e32 v3, v7, v8
-; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
-; GFX6-NEXT:    v_trunc_f32_e32 v3, v3
-; GFX6-NEXT:    v_mul_lo_u32 v2, v2, v4
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v4, v3
-; GFX6-NEXT:    v_mad_f32 v3, -v3, v6, v7
-; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v6
+; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v3, v1
 ; GFX6-NEXT:    s_mov_b32 s6, -1
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v3, v3, s1
-; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v2
+; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s3, v2
 ; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
 ; GFX6-NEXT:    v_and_b32_e32 v0, s8, v0
-; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s3, v3
 ; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX6-NEXT:    buffer_store_short v2, off, s[4:7], 0 offset:4
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
@@ -4071,28 +4071,28 @@
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v6, v3
 ; GFX9-NEXT:    v_mad_f32 v1, -v3, v0, v1
 ; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
-; GFX9-NEXT:    v_mul_f32_e32 v1, v4, v5
+; GFX9-NEXT:    s_and_b32 s5, s5, s8
 ; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v6, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s1
-; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX9-NEXT:    s_and_b32 s1, s7, s8
-; GFX9-NEXT:    v_mad_f32 v3, -v1, v2, v4
-; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, s1
-; GFX9-NEXT:    s_and_b32 s5, s5, s8
-; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, s5
-; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX9-NEXT:    v_rcp_iflag_f32_e32 v6, v4
-; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v2
-; GFX9-NEXT:    v_sub_u32_e32 v0, s0, v0
-; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
-; GFX9-NEXT:    v_mul_f32_e32 v2, v5, v6
+; GFX9-NEXT:    v_cvt_f32_u32_e32 v3, s1
+; GFX9-NEXT:    v_cvt_f32_u32_e32 v6, s5
+; GFX9-NEXT:    v_mul_f32_e32 v5, v4, v5
+; GFX9-NEXT:    v_trunc_f32_e32 v1, v5
+; GFX9-NEXT:    v_rcp_iflag_f32_e32 v7, v3
+; GFX9-NEXT:    v_cvt_u32_f32_e32 v5, v1
+; GFX9-NEXT:    v_mad_f32 v1, -v1, v2, v4
+; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v2
+; GFX9-NEXT:    v_mul_f32_e32 v2, v6, v7
 ; GFX9-NEXT:    v_trunc_f32_e32 v2, v2
-; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v2
-; GFX9-NEXT:    v_mad_f32 v2, -v2, v4, v5
-; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v4
+; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v2
+; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v5, vcc
+; GFX9-NEXT:    v_mad_f32 v2, -v2, v3, v6
+; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v3
+; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, 0, v4, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v1, v1, s6
-; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, 0, v3, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v2, s1
+; GFX9-NEXT:    v_sub_u32_e32 v0, s0, v0
 ; GFX9-NEXT:    v_mov_b32_e32 v3, 0
 ; GFX9-NEXT:    v_sub_u32_e32 v1, s4, v1
 ; GFX9-NEXT:    v_and_b32_e32 v0, 0xffff, v0
@@ -4401,51 +4401,49 @@
 ; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
 ; GFX6-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    s_sext_i32_i16 s8, s2
-; GFX6-NEXT:    s_sext_i32_i16 s6, s0
-; GFX6-NEXT:    v_cvt_f32_i32_e32 v0, s6
-; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s8
-; GFX6-NEXT:    s_xor_b32 s6, s8, s6
-; GFX6-NEXT:    s_ashr_i32 s6, s6, 30
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
+; GFX6-NEXT:    s_sext_i32_i16 s6, s2
+; GFX6-NEXT:    s_sext_i32_i16 s8, s0
+; GFX6-NEXT:    v_cvt_f32_i32_e32 v0, s8
+; GFX6-NEXT:    v_cvt_f32_i32_e32 v2, s6
+; GFX6-NEXT:    s_xor_b32 s8, s6, s8
+; GFX6-NEXT:    s_ashr_i32 s6, s8, 30
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v3, v0
 ; GFX6-NEXT:    s_or_b32 s6, s6, 1
-; GFX6-NEXT:    v_mov_b32_e32 v3, s6
-; GFX6-NEXT:    s_mov_b32 s6, -1
-; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
-; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
-; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
-; GFX6-NEXT:    v_cvt_i32_f32_e32 v2, v2
-; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
-; GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
+; GFX6-NEXT:    v_mov_b32_e32 v4, s6
 ; GFX6-NEXT:    v_mov_b32_e32 v1, s2
-; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT:    v_mul_f32_e32 v3, v2, v3
+; GFX6-NEXT:    v_trunc_f32_e32 v3, v3
+; GFX6-NEXT:    v_mad_f32 v2, -v3, v0, v2
+; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v0|
 ; GFX6-NEXT:    v_mov_b32_e32 v2, s0
 ; GFX6-NEXT:    v_alignbit_b32 v2, s1, v2, 16
+; GFX6-NEXT:    v_cvt_i32_f32_e32 v5, v3
 ; GFX6-NEXT:    v_bfe_i32 v3, v2, 0, 16
+; GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v4, vcc
 ; GFX6-NEXT:    v_cvt_f32_i32_e32 v4, v3
 ; GFX6-NEXT:    v_alignbit_b32 v1, s3, v1, 16
+; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v5
 ; GFX6-NEXT:    v_bfe_i32 v5, v1, 0, 16
 ; GFX6-NEXT:    v_cvt_f32_i32_e32 v6, v5
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v7, v4
-; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s0
 ; GFX6-NEXT:    v_xor_b32_e32 v3, v5, v3
+; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s0
 ; GFX6-NEXT:    s_sext_i32_i16 s0, s1
 ; GFX6-NEXT:    v_mul_f32_e32 v5, v6, v7
 ; GFX6-NEXT:    v_trunc_f32_e32 v5, v5
-; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
-; GFX6-NEXT:    v_mad_f32 v6, -v5, v4, v6
-; GFX6-NEXT:    v_cvt_i32_f32_e32 v5, v5
+; GFX6-NEXT:    v_cvt_i32_f32_e32 v7, v5
+; GFX6-NEXT:    v_mad_f32 v5, -v5, v4, v6
 ; GFX6-NEXT:    v_ashrrev_i32_e32 v3, 30, v3
-; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v6|, |v4|
+; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v5|, |v4|
 ; GFX6-NEXT:    v_cvt_f32_i32_e32 v4, s0
 ; GFX6-NEXT:    v_or_b32_e32 v3, 1, v3
 ; GFX6-NEXT:    v_cndmask_b32_e32 v3, 0, v3, vcc
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
-; GFX6-NEXT:    s_sext_i32_i16 s2, s3
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
+; GFX6-NEXT:    s_sext_i32_i16 s6, s3
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v3, v2
-; GFX6-NEXT:    v_cvt_f32_i32_e32 v3, s2
+; GFX6-NEXT:    v_cvt_f32_i32_e32 v3, s6
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v5, v4
-; GFX6-NEXT:    s_xor_b32 s0, s2, s0
+; GFX6-NEXT:    s_xor_b32 s0, s6, s0
 ; GFX6-NEXT:    s_ashr_i32 s0, s0, 30
 ; GFX6-NEXT:    s_or_b32 s0, s0, 1
 ; GFX6-NEXT:    v_mul_f32_e32 v5, v3, v5
@@ -4458,9 +4456,11 @@
 ; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
 ; GFX6-NEXT:    v_mul_lo_u32 v3, v3, s1
 ; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v2
+; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
+; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s3, v3
 ; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
 ; GFX6-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s3, v3
 ; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX6-NEXT:    buffer_store_short v2, off, s[4:7], 0 offset:4
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
@@ -4615,41 +4615,41 @@
 ; GFX6-NEXT:    s_movk_i32 s3, 0x7fff
 ; GFX6-NEXT:    s_and_b32 s9, s0, s3
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s9
-; GFX6-NEXT:    v_mov_b32_e32 v2, s0
 ; GFX6-NEXT:    s_and_b32 s8, s2, s3
-; GFX6-NEXT:    s_bfe_u32 s0, s0, 0xf000f
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v5, s0
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s8
+; GFX6-NEXT:    v_mov_b32_e32 v2, s0
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v1
-; GFX6-NEXT:    s_bfe_u32 s2, s2, 0xf000f
+; GFX6-NEXT:    s_bfe_u32 s0, s0, 0xf000f
 ; GFX6-NEXT:    v_alignbit_b32 v2, s1, v2, 30
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v6, s2
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v5, s0
 ; GFX6-NEXT:    v_mul_f32_e32 v4, v3, v4
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v7, v5
 ; GFX6-NEXT:    v_and_b32_e32 v2, s3, v2
 ; GFX6-NEXT:    v_trunc_f32_e32 v4, v4
 ; GFX6-NEXT:    v_mad_f32 v3, -v4, v1, v3
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v4, v4
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v2, v2
+; GFX6-NEXT:    s_bfe_u32 s2, s2, 0xf000f
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v6, s2
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v7, v5
 ; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v1
-; GFX6-NEXT:    v_mul_f32_e32 v1, v6, v7
 ; GFX6-NEXT:    v_and_b32_e32 v0, s3, v0
-; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
-; GFX6-NEXT:    v_mad_f32 v4, -v1, v5, v6
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, v0
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v6, v2
-; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v5
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v1, vcc
-; GFX6-NEXT:    v_mul_f32_e32 v1, v0, v6
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v2
+; GFX6-NEXT:    v_mul_f32_e32 v1, v6, v7
 ; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v5, v1
-; GFX6-NEXT:    v_mad_f32 v0, -v1, v2, v0
+; GFX6-NEXT:    v_mad_f32 v6, -v1, v5, v6
+; GFX6-NEXT:    v_mul_f32_e32 v4, v0, v4
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT:    v_trunc_f32_e32 v4, v4
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v7, v4
+; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v6|, v5
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v1, vcc
+; GFX6-NEXT:    v_mad_f32 v0, -v4, v2, v0
 ; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, v2
+; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v7, vcc
 ; GFX6-NEXT:    v_and_b32_e32 v2, s3, v3
-; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v5, vcc
-; GFX6-NEXT:    v_and_b32_e32 v3, s3, v4
+; GFX6-NEXT:    v_and_b32_e32 v3, s3, v5
 ; GFX6-NEXT:    v_lshlrev_b32_e32 v3, 15, v3
 ; GFX6-NEXT:    v_lshl_b64 v[0:1], v[0:1], 30
 ; GFX6-NEXT:    v_or_b32_e32 v2, v2, v3
@@ -4672,41 +4672,41 @@
 ; GFX9-NEXT:    s_and_b32 s1, s6, s8
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s1
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, s0
+; GFX9-NEXT:    v_mov_b32_e32 v3, s6
 ; GFX9-NEXT:    s_bfe_u32 s0, s6, 0xf000f
-; GFX9-NEXT:    v_cvt_f32_u32_e32 v6, s0
 ; GFX9-NEXT:    v_rcp_iflag_f32_e32 v5, v1
-; GFX9-NEXT:    v_mov_b32_e32 v3, s6
-; GFX9-NEXT:    s_bfe_u32 s1, s4, 0xf000f
 ; GFX9-NEXT:    v_alignbit_b32 v3, s7, v3, 30
-; GFX9-NEXT:    v_mul_f32_e32 v5, v4, v5
-; GFX9-NEXT:    v_cvt_f32_u32_e32 v7, s1
-; GFX9-NEXT:    v_rcp_iflag_f32_e32 v8, v6
+; GFX9-NEXT:    v_cvt_f32_u32_e32 v6, s0
 ; GFX9-NEXT:    v_and_b32_e32 v3, s8, v3
+; GFX9-NEXT:    v_mul_f32_e32 v5, v4, v5
 ; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
 ; GFX9-NEXT:    v_mad_f32 v4, -v5, v1, v4
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v5, v5
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v3, v3
 ; GFX9-NEXT:    v_mov_b32_e32 v0, s4
-; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v1
+; GFX9-NEXT:    s_bfe_u32 s1, s4, 0xf000f
 ; GFX9-NEXT:    v_alignbit_b32 v0, s5, v0, 30
-; GFX9-NEXT:    v_mul_f32_e32 v1, v7, v8
+; GFX9-NEXT:    v_cvt_f32_u32_e32 v7, s1
+; GFX9-NEXT:    v_rcp_iflag_f32_e32 v8, v6
+; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v1
 ; GFX9-NEXT:    v_and_b32_e32 v0, s8, v0
-; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
-; GFX9-NEXT:    v_mad_f32 v5, -v1, v6, v7
-; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, v0
-; GFX9-NEXT:    v_rcp_iflag_f32_e32 v7, v3
-; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v5|, v6
-; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v1, vcc
-; GFX9-NEXT:    v_mul_f32_e32 v1, v0, v7
+; GFX9-NEXT:    v_rcp_iflag_f32_e32 v5, v3
+; GFX9-NEXT:    v_mul_f32_e32 v1, v7, v8
 ; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
-; GFX9-NEXT:    v_cvt_u32_f32_e32 v6, v1
-; GFX9-NEXT:    v_mad_f32 v0, -v1, v3, v0
+; GFX9-NEXT:    v_mad_f32 v7, -v1, v6, v7
+; GFX9-NEXT:    v_mul_f32_e32 v5, v0, v5
+; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
+; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
+; GFX9-NEXT:    v_cvt_u32_f32_e32 v8, v5
+; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v7|, v6
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v1, vcc
+; GFX9-NEXT:    v_mad_f32 v0, -v5, v3, v0
 ; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, v3
+; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v8, vcc
 ; GFX9-NEXT:    v_and_b32_e32 v3, s8, v4
-; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v6, vcc
-; GFX9-NEXT:    v_and_b32_e32 v4, s8, v5
+; GFX9-NEXT:    v_and_b32_e32 v4, s8, v6
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v4, 15, v4
 ; GFX9-NEXT:    v_lshlrev_b64 v[0:1], 30, v[0:1]
 ; GFX9-NEXT:    v_or_b32_e32 v3, v3, v4
@@ -4804,50 +4804,50 @@
 ; GFX6-NEXT:    s_movk_i32 s3, 0x7fff
 ; GFX6-NEXT:    s_and_b32 s10, s0, s3
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s10
-; GFX6-NEXT:    s_and_b32 s9, s2, s3
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s9
-; GFX6-NEXT:    v_mov_b32_e32 v2, s0
+; GFX6-NEXT:    s_and_b32 s8, s2, s3
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s8
+; GFX6-NEXT:    s_bfe_u32 s8, s0, 0xf000f
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v1
+; GFX6-NEXT:    v_mov_b32_e32 v2, s0
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v5, s8
 ; GFX6-NEXT:    v_alignbit_b32 v2, s1, v2, 30
-; GFX6-NEXT:    s_bfe_u32 s1, s0, 0xf000f
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v5, s1
 ; GFX6-NEXT:    v_mul_f32_e32 v4, v3, v4
 ; GFX6-NEXT:    v_trunc_f32_e32 v4, v4
 ; GFX6-NEXT:    v_mad_f32 v3, -v4, v1, v3
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v4, v4
 ; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v1
-; GFX6-NEXT:    s_bfe_u32 s10, s2, 0xf000f
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s10
-; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v4, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s0
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v5
 ; GFX6-NEXT:    v_and_b32_e32 v2, s3, v2
-; GFX6-NEXT:    v_and_b32_e32 v0, s3, v0
-; GFX6-NEXT:    v_sub_i32_e32 v6, vcc, s2, v1
-; GFX6-NEXT:    v_mul_f32_e32 v1, v3, v4
+; GFX6-NEXT:    s_bfe_u32 s9, s2, 0xf000f
+; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v4, vcc
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, v2
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v7, v0
-; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
-; GFX6-NEXT:    v_mad_f32 v3, -v1, v5, v3
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v8, v4
-; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v5
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT:    s_lshr_b32 s0, s0, 15
-; GFX6-NEXT:    v_mul_f32_e32 v3, v7, v8
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v6, s9
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v7, v5
+; GFX6-NEXT:    v_and_b32_e32 v0, s3, v0
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v8, v0
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v9, v4
+; GFX6-NEXT:    v_mul_f32_e32 v3, v6, v7
 ; GFX6-NEXT:    v_trunc_f32_e32 v3, v3
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v5, v3
-; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX6-NEXT:    v_mad_f32 v3, -v3, v4, v7
-; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v4
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v7, v3
+; GFX6-NEXT:    v_mad_f32 v3, -v3, v5, v6
+; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v5
+; GFX6-NEXT:    v_mul_f32_e32 v5, v8, v9
+; GFX6-NEXT:    v_trunc_f32_e32 v5, v5
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v6, v5
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v7, vcc
+; GFX6-NEXT:    v_mad_f32 v5, -v5, v4, v8
+; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v5|, v4
+; GFX6-NEXT:    s_lshr_b32 s1, s0, 15
+; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v6, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v3, v3, s1
 ; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s0
-; GFX6-NEXT:    v_mul_lo_u32 v2, v3, v2
-; GFX6-NEXT:    s_lshr_b32 s8, s2, 15
-; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s8, v1
-; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, v2, v0
+; GFX6-NEXT:    v_mul_lo_u32 v2, v4, v2
+; GFX6-NEXT:    s_lshr_b32 s0, s2, 15
+; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s0, v3
 ; GFX6-NEXT:    v_and_b32_e32 v3, s3, v3
+; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s2, v1
+; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, v2, v0
 ; GFX6-NEXT:    v_lshl_b64 v[0:1], v[0:1], 30
-; GFX6-NEXT:    v_and_b32_e32 v2, s3, v6
+; GFX6-NEXT:    v_and_b32_e32 v2, s3, v4
 ; GFX6-NEXT:    v_lshlrev_b32_e32 v3, 15, v3
 ; GFX6-NEXT:    v_or_b32_e32 v2, v2, v3
 ; GFX6-NEXT:    v_or_b32_e32 v0, v2, v0
@@ -4873,35 +4873,35 @@
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, s0
 ; GFX9-NEXT:    s_bfe_u32 s5, s6, 0xf000f
 ; GFX9-NEXT:    v_rcp_iflag_f32_e32 v5, v1
-; GFX9-NEXT:    v_cvt_f32_u32_e32 v6, s5
 ; GFX9-NEXT:    v_mov_b32_e32 v3, s6
+; GFX9-NEXT:    v_cvt_f32_u32_e32 v6, s5
 ; GFX9-NEXT:    v_alignbit_b32 v3, s7, v3, 30
 ; GFX9-NEXT:    v_mul_f32_e32 v5, v4, v5
 ; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
 ; GFX9-NEXT:    v_mad_f32 v4, -v5, v1, v4
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v5, v5
 ; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v1
-; GFX9-NEXT:    s_bfe_u32 s1, s4, 0xf000f
 ; GFX9-NEXT:    v_and_b32_e32 v3, s8, v3
+; GFX9-NEXT:    s_bfe_u32 s1, s4, 0xf000f
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v5, vcc
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, v3
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v7, s1
 ; GFX9-NEXT:    v_rcp_iflag_f32_e32 v8, v6
 ; GFX9-NEXT:    v_and_b32_e32 v0, s8, v0
-; GFX9-NEXT:    v_rcp_iflag_f32_e32 v9, v5
-; GFX9-NEXT:    s_lshr_b32 s0, s6, 15
+; GFX9-NEXT:    v_cvt_f32_u32_e32 v9, v0
+; GFX9-NEXT:    v_rcp_iflag_f32_e32 v10, v5
 ; GFX9-NEXT:    v_mul_f32_e32 v4, v7, v8
-; GFX9-NEXT:    v_cvt_f32_u32_e32 v8, v0
 ; GFX9-NEXT:    v_trunc_f32_e32 v4, v4
-; GFX9-NEXT:    v_mad_f32 v7, -v4, v6, v7
-; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v7|, v6
-; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v4
-; GFX9-NEXT:    v_mul_f32_e32 v6, v8, v9
+; GFX9-NEXT:    v_cvt_u32_f32_e32 v8, v4
+; GFX9-NEXT:    v_mad_f32 v4, -v4, v6, v7
+; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v6
+; GFX9-NEXT:    v_mul_f32_e32 v6, v9, v10
 ; GFX9-NEXT:    v_trunc_f32_e32 v6, v6
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v7, v6
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
-; GFX9-NEXT:    v_mad_f32 v6, -v6, v5, v8
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v8, vcc
+; GFX9-NEXT:    v_mad_f32 v6, -v6, v5, v9
 ; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v6|, v5
+; GFX9-NEXT:    s_lshr_b32 s0, s6, 15
 ; GFX9-NEXT:    v_mul_lo_u32 v4, v4, s0
 ; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v3, v5, v3
@@ -5056,12 +5056,12 @@
 ; GFX6-NEXT:    v_or_b32_e32 v0, 1, v0
 ; GFX6-NEXT:    v_mul_f32_e32 v1, v5, v6
 ; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
-; GFX6-NEXT:    v_mad_f32 v5, -v1, v4, v5
-; GFX6-NEXT:    v_cvt_i32_f32_e32 v1, v1
-; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v5|, |v4|
+; GFX6-NEXT:    v_cvt_i32_f32_e32 v6, v1
+; GFX6-NEXT:    v_mad_f32 v1, -v1, v4, v5
+; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v4|
 ; GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
 ; GFX6-NEXT:    s_movk_i32 s0, 0x7fff
-; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
+; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v6
 ; GFX6-NEXT:    v_and_b32_e32 v3, s0, v3
 ; GFX6-NEXT:    v_lshl_b64 v[0:1], v[0:1], 30
 ; GFX6-NEXT:    v_and_b32_e32 v2, s0, v2
@@ -5242,47 +5242,45 @@
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
 ; GFX6-NEXT:    v_alignbit_b32 v0, s3, v0, 30
 ; GFX6-NEXT:    s_movk_i32 s3, 0x7fff
-; GFX6-NEXT:    s_and_b32 s11, s0, s3
-; GFX6-NEXT:    s_bfe_i32 s11, s11, 0xf0000
-; GFX6-NEXT:    v_cvt_f32_i32_e32 v2, s11
-; GFX6-NEXT:    s_and_b32 s9, s2, s3
-; GFX6-NEXT:    s_bfe_i32 s9, s9, 0xf0000
-; GFX6-NEXT:    v_cvt_f32_i32_e32 v3, s9
+; GFX6-NEXT:    s_and_b32 s10, s0, s3
+; GFX6-NEXT:    s_bfe_i32 s10, s10, 0xf0000
+; GFX6-NEXT:    v_cvt_f32_i32_e32 v2, s10
+; GFX6-NEXT:    s_and_b32 s8, s2, s3
+; GFX6-NEXT:    s_bfe_i32 s8, s8, 0xf0000
+; GFX6-NEXT:    v_cvt_f32_i32_e32 v3, s8
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v2
-; GFX6-NEXT:    s_xor_b32 s9, s9, s11
-; GFX6-NEXT:    s_ashr_i32 s9, s9, 30
-; GFX6-NEXT:    s_or_b32 s9, s9, 1
+; GFX6-NEXT:    s_xor_b32 s8, s8, s10
+; GFX6-NEXT:    s_ashr_i32 s8, s8, 30
+; GFX6-NEXT:    s_or_b32 s8, s8, 1
 ; GFX6-NEXT:    v_mul_f32_e32 v4, v3, v4
 ; GFX6-NEXT:    v_trunc_f32_e32 v4, v4
 ; GFX6-NEXT:    v_mad_f32 v3, -v4, v2, v3
+; GFX6-NEXT:    s_bfe_u32 s11, s0, 0xf000f
 ; GFX6-NEXT:    v_cvt_i32_f32_e32 v4, v4
-; GFX6-NEXT:    v_mov_b32_e32 v5, s9
+; GFX6-NEXT:    v_mov_b32_e32 v5, s8
+; GFX6-NEXT:    s_bfe_i32 s8, s11, 0xf0000
 ; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v2|
+; GFX6-NEXT:    v_cvt_f32_i32_e32 v3, s8
 ; GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v5, vcc
 ; GFX6-NEXT:    v_mov_b32_e32 v1, s0
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
-; GFX6-NEXT:    s_bfe_u32 s12, s0, 0xf000f
+; GFX6-NEXT:    s_bfe_u32 s9, s2, 0xf000f
 ; GFX6-NEXT:    v_alignbit_b32 v1, s1, v1, 30
-; GFX6-NEXT:    v_mul_lo_u32 v2, v2, s0
 ; GFX6-NEXT:    s_lshr_b32 s1, s0, 15
-; GFX6-NEXT:    s_bfe_i32 s0, s12, 0xf0000
-; GFX6-NEXT:    v_cvt_f32_i32_e32 v3, s0
-; GFX6-NEXT:    s_bfe_u32 s10, s2, 0xf000f
-; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s2, v2
-; GFX6-NEXT:    s_lshr_b32 s8, s2, 15
-; GFX6-NEXT:    s_bfe_i32 s2, s10, 0xf0000
-; GFX6-NEXT:    v_cvt_f32_i32_e32 v4, s2
+; GFX6-NEXT:    v_mul_lo_u32 v2, v2, s0
+; GFX6-NEXT:    s_bfe_i32 s0, s9, 0xf0000
+; GFX6-NEXT:    v_cvt_f32_i32_e32 v4, s0
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v5, v3
-; GFX6-NEXT:    s_xor_b32 s0, s2, s0
+; GFX6-NEXT:    s_xor_b32 s0, s0, s8
 ; GFX6-NEXT:    s_ashr_i32 s0, s0, 30
 ; GFX6-NEXT:    s_or_b32 s0, s0, 1
 ; GFX6-NEXT:    v_mul_f32_e32 v5, v4, v5
 ; GFX6-NEXT:    v_trunc_f32_e32 v5, v5
 ; GFX6-NEXT:    v_mad_f32 v4, -v5, v3, v4
 ; GFX6-NEXT:    v_cvt_i32_f32_e32 v5, v5
-; GFX6-NEXT:    v_and_b32_e32 v1, s3, v1
-; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v3|
 ; GFX6-NEXT:    v_mov_b32_e32 v6, s0
+; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v3|
+; GFX6-NEXT:    v_and_b32_e32 v1, s3, v1
 ; GFX6-NEXT:    v_cndmask_b32_e32 v3, 0, v6, vcc
 ; GFX6-NEXT:    v_bfe_i32 v4, v1, 0, 15
 ; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
@@ -5296,19 +5294,21 @@
 ; GFX6-NEXT:    v_or_b32_e32 v4, 1, v4
 ; GFX6-NEXT:    v_mul_f32_e32 v6, v7, v8
 ; GFX6-NEXT:    v_trunc_f32_e32 v6, v6
-; GFX6-NEXT:    v_mad_f32 v7, -v6, v5, v7
-; GFX6-NEXT:    v_cvt_i32_f32_e32 v6, v6
-; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v7|, |v5|
+; GFX6-NEXT:    v_cvt_i32_f32_e32 v8, v6
+; GFX6-NEXT:    v_mad_f32 v6, -v6, v5, v7
+; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v6|, |v5|
 ; GFX6-NEXT:    v_cndmask_b32_e32 v4, 0, v4, vcc
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
 ; GFX6-NEXT:    v_mul_lo_u32 v3, v3, s1
-; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
 ; GFX6-NEXT:    v_mul_lo_u32 v1, v4, v1
-; GFX6-NEXT:    v_and_b32_e32 v2, s3, v2
-; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s8, v3
-; GFX6-NEXT:    v_and_b32_e32 v3, s3, v3
+; GFX6-NEXT:    s_lshr_b32 s0, s2, 15
+; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s2, v2
+; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s0, v3
 ; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, v1, v0
-; GFX6-NEXT:    v_lshlrev_b32_e32 v3, 15, v3
+; GFX6-NEXT:    v_and_b32_e32 v3, s3, v3
 ; GFX6-NEXT:    v_lshl_b64 v[0:1], v[0:1], 30
+; GFX6-NEXT:    v_and_b32_e32 v2, s3, v2
+; GFX6-NEXT:    v_lshlrev_b32_e32 v3, 15, v3
 ; GFX6-NEXT:    v_or_b32_e32 v2, v2, v3
 ; GFX6-NEXT:    v_or_b32_e32 v0, v2, v0
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
@@ -5413,18 +5413,18 @@
 ;
 ; GFX6-LABEL: udiv_i32_oddk_denom:
 ; GFX6:       ; %bb.0:
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
+; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
 ; GFX6-NEXT:    v_mov_b32_e32 v0, 0xb2a50881
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mul_hi_u32 v0, s0, v0
-; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s0, v0
+; GFX6-NEXT:    v_mul_hi_u32 v0, s4, v0
+; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s4, v0
 ; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 1, v1
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
 ; GFX6-NEXT:    v_lshrrev_b32_e32 v0, 20, v0
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: udiv_i32_oddk_denom:
@@ -5685,49 +5685,49 @@
 ; GFX6-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX6-NEXT:    s_mov_b32 s6, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    s_lshl_b32 s8, s4, s2
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s8
-; GFX6-NEXT:    s_lshl_b32 s9, s4, s3
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s9
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
+; GFX6-NEXT:    s_lshl_b32 s9, s4, s2
+; GFX6-NEXT:    s_lshl_b32 s8, s4, s3
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s9
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s8
+; GFX6-NEXT:    s_mov_b32 s2, 0x4f7ffffe
+; GFX6-NEXT:    s_sub_i32 s3, 0, s8
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
-; GFX6-NEXT:    s_mov_b32 s0, 0x4f7ffffe
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v1
-; GFX6-NEXT:    v_mul_f32_e32 v0, s0, v0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
+; GFX6-NEXT:    v_mul_f32_e32 v0, s2, v0
+; GFX6-NEXT:    v_mul_f32_e32 v1, s2, v1
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT:    v_mul_f32_e32 v1, s0, v1
-; GFX6-NEXT:    s_sub_i32 s0, 0, s8
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT:    v_mul_lo_u32 v2, s0, v0
-; GFX6-NEXT:    s_sub_i32 s0, 0, s9
-; GFX6-NEXT:    v_mul_lo_u32 v3, s0, v1
+; GFX6-NEXT:    s_sub_i32 s2, 0, s9
+; GFX6-NEXT:    v_mul_lo_u32 v2, s2, v0
+; GFX6-NEXT:    v_mul_lo_u32 v3, s3, v1
 ; GFX6-NEXT:    v_mul_hi_u32 v2, v0, v2
 ; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
-; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mul_hi_u32 v0, s2, v0
 ; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
-; GFX6-NEXT:    v_mul_hi_u32 v1, s3, v1
-; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s8
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, 1, v0
-; GFX6-NEXT:    v_mul_lo_u32 v4, v1, s9
-; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s2, v2
-; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s8, v2
-; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v3, s[0:1]
-; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s8, v2
-; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, v3, s[0:1]
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, 1, v0
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v2
-; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
-; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s3, v4
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, 1, v1
+; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:    v_mul_hi_u32 v0, s0, v0
+; GFX6-NEXT:    v_mul_hi_u32 v1, s1, v1
+; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s9
+; GFX6-NEXT:    v_mul_lo_u32 v3, v1, s8
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, 1, v0
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v1
+; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s0, v2
+; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s1, v3
 ; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s9, v2
-; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[0:1]
-; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s9, v2
-; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, v3, s[0:1]
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, 1, v1
+; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v4, s[0:1]
+; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s9, v2
+; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, v4, s[0:1]
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, 1, v0
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v2
+; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s8, v3
+; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
+; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s8, v3
+; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v5, s[0:1]
+; GFX6-NEXT:    v_cndmask_b32_e64 v2, v3, v2, s[0:1]
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, 1, v1
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v2
 ; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
 ; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; GFX6-NEXT:    s_endpgm
@@ -6022,50 +6022,50 @@
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xd
 ; GFX6-NEXT:    s_movk_i32 s4, 0x1000
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    s_lshl_b32 s8, s4, s2
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s8
-; GFX6-NEXT:    s_lshl_b32 s3, s4, s3
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s3
-; GFX6-NEXT:    s_mov_b32 s4, 0x4f7ffffe
+; GFX6-NEXT:    s_lshl_b32 s6, s4, s3
+; GFX6-NEXT:    s_lshl_b32 s7, s4, s2
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s7
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s6
+; GFX6-NEXT:    s_mov_b32 s2, 0x4f7ffffe
+; GFX6-NEXT:    s_sub_i32 s3, 0, s6
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
-; GFX6-NEXT:    s_sub_i32 s2, 0, s8
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v1
-; GFX6-NEXT:    v_mul_f32_e32 v0, s4, v0
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT:    v_mul_f32_e32 v1, s4, v1
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xb
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX6-NEXT:    v_mul_f32_e32 v0, s2, v0
+; GFX6-NEXT:    v_mul_f32_e32 v1, s2, v1
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
+; GFX6-NEXT:    s_sub_i32 s2, 0, s7
+; GFX6-NEXT:    v_mul_lo_u32 v3, s3, v1
 ; GFX6-NEXT:    v_mul_lo_u32 v2, s2, v0
-; GFX6-NEXT:    s_sub_i32 s2, 0, s3
-; GFX6-NEXT:    v_mul_lo_u32 v3, s2, v1
-; GFX6-NEXT:    v_mul_hi_u32 v2, v0, v2
+; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
+; GFX6-NEXT:    v_mul_hi_u32 v2, v0, v2
+; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mul_hi_u32 v0, s0, v0
-; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
-; GFX6-NEXT:    v_mul_hi_u32 v1, s1, v1
-; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s8
-; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s3
-; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s0, v0
-; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s8, v0
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
+; GFX6-NEXT:    v_mul_hi_u32 v0, s4, v0
+; GFX6-NEXT:    v_mul_hi_u32 v1, s5, v1
+; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s7
+; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s6
+; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
+; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s5, v1
+; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s7, v0
+; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s6, v1
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s7, v0
 ; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s8, v0
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s6, v1
+; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s7, v0
+; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s6, v1
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s7, v0
 ; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s1, v1
-; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s3, v1
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s3, v1
-; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s3, v1
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s3, v1
-; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s6, v1
+; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: urem_v2i32_pow2_shl_denom:
@@ -6130,18 +6130,18 @@
 ;
 ; GFX6-LABEL: sdiv_i32_oddk_denom:
 ; GFX6:       ; %bb.0:
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
+; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
 ; GFX6-NEXT:    v_mov_b32_e32 v0, 0xd9528441
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mul_hi_i32 v0, s0, v0
-; GFX6-NEXT:    v_add_i32_e32 v0, vcc, s0, v0
+; GFX6-NEXT:    v_mul_hi_i32 v0, s4, v0
+; GFX6-NEXT:    v_add_i32_e32 v0, vcc, s4, v0
 ; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 31, v0
 ; GFX6-NEXT:    v_ashrrev_i32_e32 v0, 20, v0
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: sdiv_i32_oddk_denom:
@@ -6492,68 +6492,68 @@
 ; GFX6-LABEL: sdiv_v2i32_pow2_shl_denom:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xd
-; GFX6-NEXT:    s_movk_i32 s10, 0x1000
-; GFX6-NEXT:    s_mov_b32 s13, 0x4f7ffffe
+; GFX6-NEXT:    s_movk_i32 s6, 0x1000
+; GFX6-NEXT:    s_mov_b32 s12, 0x4f7ffffe
 ; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
 ; GFX6-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xb
 ; GFX6-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    s_lshl_b32 s2, s10, s2
-; GFX6-NEXT:    s_ashr_i32 s11, s2, 31
-; GFX6-NEXT:    s_add_i32 s2, s2, s11
-; GFX6-NEXT:    s_xor_b32 s12, s2, s11
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s12
-; GFX6-NEXT:    s_lshl_b32 s0, s10, s3
-; GFX6-NEXT:    s_sub_i32 s3, 0, s12
+; GFX6-NEXT:    s_lshl_b32 s2, s6, s2
+; GFX6-NEXT:    s_ashr_i32 s10, s2, 31
+; GFX6-NEXT:    s_add_i32 s2, s2, s10
+; GFX6-NEXT:    s_xor_b32 s11, s2, s10
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s11
+; GFX6-NEXT:    s_lshl_b32 s0, s6, s3
 ; GFX6-NEXT:    s_ashr_i32 s2, s0, 31
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
 ; GFX6-NEXT:    s_add_i32 s0, s0, s2
-; GFX6-NEXT:    s_xor_b32 s10, s0, s2
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v2, s10
-; GFX6-NEXT:    v_mul_f32_e32 v0, s13, v0
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
+; GFX6-NEXT:    s_xor_b32 s13, s0, s2
+; GFX6-NEXT:    s_sub_i32 s0, 0, s11
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s13
+; GFX6-NEXT:    v_mul_f32_e32 v0, s12, v0
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT:    s_ashr_i32 s1, s8, 31
-; GFX6-NEXT:    s_add_i32 s0, s8, s1
-; GFX6-NEXT:    s_xor_b32 s0, s0, s1
-; GFX6-NEXT:    v_mul_lo_u32 v1, s3, v0
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v2
-; GFX6-NEXT:    s_xor_b32 s3, s1, s11
+; GFX6-NEXT:    s_sub_i32 s3, 0, s13
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v1
 ; GFX6-NEXT:    s_mov_b32 s6, -1
-; GFX6-NEXT:    v_mul_hi_u32 v1, v0, v1
-; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
-; GFX6-NEXT:    v_mul_hi_u32 v0, s0, v0
-; GFX6-NEXT:    v_mul_f32_e32 v1, s13, v2
+; GFX6-NEXT:    v_mul_lo_u32 v2, s0, v0
+; GFX6-NEXT:    s_ashr_i32 s0, s8, 31
+; GFX6-NEXT:    s_add_i32 s1, s8, s0
+; GFX6-NEXT:    s_xor_b32 s1, s1, s0
+; GFX6-NEXT:    v_mul_hi_u32 v2, v0, v2
+; GFX6-NEXT:    v_mul_f32_e32 v1, s12, v1
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s12
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, 1, v0
-; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s0, v2
-; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s12, v2
-; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v3, s[0:1]
-; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s12, v2
-; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, v3, s[0:1]
-; GFX6-NEXT:    s_sub_i32 s0, 0, s10
-; GFX6-NEXT:    v_mul_lo_u32 v3, s0, v1
+; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
+; GFX6-NEXT:    v_mul_hi_u32 v0, s1, v0
+; GFX6-NEXT:    v_mul_lo_u32 v2, s3, v1
+; GFX6-NEXT:    s_xor_b32 s3, s0, s10
+; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s11
+; GFX6-NEXT:    v_mul_hi_u32 v2, v1, v2
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, 1, v0
+; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s1, v3
+; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s11, v3
+; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v4, s[0:1]
+; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s11, v3
+; GFX6-NEXT:    v_cndmask_b32_e64 v3, v3, v4, s[0:1]
 ; GFX6-NEXT:    s_ashr_i32 s0, s9, 31
 ; GFX6-NEXT:    s_add_i32 s1, s9, s0
+; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
 ; GFX6-NEXT:    s_xor_b32 s1, s1, s0
-; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
-; GFX6-NEXT:    v_add_i32_e32 v4, vcc, 1, v0
-; GFX6-NEXT:    s_xor_b32 s2, s0, s2
-; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
 ; GFX6-NEXT:    v_mul_hi_u32 v1, s1, v1
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s12, v2
-; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
-; GFX6-NEXT:    v_xor_b32_e32 v0, s3, v0
-; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s10
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, 1, v0
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s11, v3
+; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s13
+; GFX6-NEXT:    s_xor_b32 s2, s0, s2
 ; GFX6-NEXT:    v_add_i32_e32 v3, vcc, 1, v1
-; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s3, v0
+; GFX6-NEXT:    v_xor_b32_e32 v0, s3, v0
 ; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s1, v2
-; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s10, v2
+; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s13, v2
 ; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[0:1]
-; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s10, v2
+; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s13, v2
 ; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, v3, s[0:1]
+; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s3, v0
 ; GFX6-NEXT:    v_add_i32_e32 v3, vcc, 1, v1
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v2
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s13, v2
 ; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
 ; GFX6-NEXT:    v_xor_b32_e32 v1, s2, v1
 ; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, s2, v1
@@ -6950,67 +6950,66 @@
 ;
 ; GFX6-LABEL: srem_v2i32_pow2_shl_denom:
 ; GFX6:       ; %bb.0:
-; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xd
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
 ; GFX6-NEXT:    s_movk_i32 s6, 0x1000
-; GFX6-NEXT:    s_mov_b32 s10, 0x4f7ffffe
+; GFX6-NEXT:    s_mov_b32 s9, 0x4f7ffffe
 ; GFX6-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    s_lshl_b32 s2, s6, s2
-; GFX6-NEXT:    s_ashr_i32 s4, s2, 31
-; GFX6-NEXT:    s_add_i32 s2, s2, s4
-; GFX6-NEXT:    s_xor_b32 s9, s2, s4
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s9
-; GFX6-NEXT:    s_lshl_b32 s2, s6, s3
-; GFX6-NEXT:    s_ashr_i32 s6, s2, 31
-; GFX6-NEXT:    s_add_i32 s2, s2, s6
+; GFX6-NEXT:    s_lshl_b32 s0, s6, s0
+; GFX6-NEXT:    s_ashr_i32 s8, s0, 31
+; GFX6-NEXT:    s_add_i32 s0, s0, s8
+; GFX6-NEXT:    s_xor_b32 s8, s0, s8
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s8
+; GFX6-NEXT:    s_lshl_b32 s0, s6, s1
+; GFX6-NEXT:    s_ashr_i32 s1, s0, 31
+; GFX6-NEXT:    s_add_i32 s0, s0, s1
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
-; GFX6-NEXT:    s_sub_i32 s8, 0, s9
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    v_mul_f32_e32 v0, s10, v0
+; GFX6-NEXT:    s_xor_b32 s10, s0, s1
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s10
+; GFX6-NEXT:    s_sub_i32 s1, 0, s8
+; GFX6-NEXT:    v_mul_f32_e32 v0, s9, v0
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    s_ashr_i32 s3, s0, 31
-; GFX6-NEXT:    s_add_i32 s0, s0, s3
-; GFX6-NEXT:    v_mul_lo_u32 v1, s8, v0
-; GFX6-NEXT:    s_xor_b32 s8, s2, s6
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v2, s8
-; GFX6-NEXT:    s_xor_b32 s0, s0, s3
-; GFX6-NEXT:    v_mul_hi_u32 v1, v0, v1
-; GFX6-NEXT:    s_sub_i32 s2, 0, s8
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v2
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v1
+; GFX6-NEXT:    s_ashr_i32 s0, s2, 31
 ; GFX6-NEXT:    s_mov_b32 s6, -1
-; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
-; GFX6-NEXT:    v_mul_hi_u32 v0, s0, v0
-; GFX6-NEXT:    v_mul_f32_e32 v1, s10, v2
+; GFX6-NEXT:    v_mul_lo_u32 v2, s1, v0
+; GFX6-NEXT:    v_mul_f32_e32 v1, s9, v1
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s9
-; GFX6-NEXT:    v_mul_lo_u32 v2, s2, v1
-; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s0, v0
-; GFX6-NEXT:    s_ashr_i32 s0, s1, 31
-; GFX6-NEXT:    v_mul_hi_u32 v2, v1, v2
-; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s9, v0
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v0
-; GFX6-NEXT:    s_add_i32 s1, s1, s0
-; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX6-NEXT:    s_add_i32 s1, s2, s0
+; GFX6-NEXT:    v_mul_hi_u32 v2, v0, v2
+; GFX6-NEXT:    s_sub_i32 s2, 0, s10
+; GFX6-NEXT:    v_mul_lo_u32 v3, s2, v1
 ; GFX6-NEXT:    s_xor_b32 s1, s1, s0
+; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
+; GFX6-NEXT:    v_mul_hi_u32 v0, s1, v0
+; GFX6-NEXT:    v_mul_hi_u32 v2, v1, v3
+; GFX6-NEXT:    s_ashr_i32 s2, s3, 31
+; GFX6-NEXT:    s_add_i32 s3, s3, s2
+; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s8
+; GFX6-NEXT:    s_xor_b32 s3, s3, s2
 ; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
-; GFX6-NEXT:    v_mul_hi_u32 v1, s1, v1
-; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s9, v0
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v0
-; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s8
-; GFX6-NEXT:    v_xor_b32_e32 v0, s3, v0
-; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s3, v0
-; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s1, v1
-; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s8, v1
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v1
+; GFX6-NEXT:    v_mul_hi_u32 v1, s3, v1
+; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s1, v0
+; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s8, v0
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
+; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s10
+; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s8, v0
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
+; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX6-NEXT:    v_xor_b32_e32 v0, s0, v0
+; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s3, v1
+; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s0, v0
+; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s10, v1
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v1
 ; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s8, v1
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v1
+; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s10, v1
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v1
 ; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX6-NEXT:    v_xor_b32_e32 v1, s0, v1
-; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, s0, v1
+; GFX6-NEXT:    v_xor_b32_e32 v1, s2, v1
+; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, s2, v1
 ; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -7095,8 +7094,8 @@
 ; GFX6-NEXT:    v_mov_b32_e32 v1, 0x4f800000
 ; GFX6-NEXT:    v_madmk_f32 v0, v1, 0x438f8000, v0
 ; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
-; GFX6-NEXT:    s_movk_i32 s2, 0xfee0
-; GFX6-NEXT:    s_mov_b32 s3, 0x68958c89
+; GFX6-NEXT:    s_movk_i32 s4, 0xfee0
+; GFX6-NEXT:    s_mov_b32 s5, 0x68958c89
 ; GFX6-NEXT:    v_mov_b32_e32 v8, 0
 ; GFX6-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GFX6-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
@@ -7105,59 +7104,56 @@
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GFX6-NEXT:    v_mov_b32_e32 v7, 0
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s2
-; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s3
-; GFX6-NEXT:    v_mul_lo_u32 v4, v1, s3
 ; GFX6-NEXT:    s_mov_b32 s11, 0xf000
-; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    s_mov_b32 s8, s4
+; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s4
+; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s5
+; GFX6-NEXT:    v_mul_lo_u32 v5, v1, s5
+; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s5
+; GFX6-NEXT:    s_mov_b32 s10, -1
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s3
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
+; GFX6-NEXT:    v_mul_hi_u32 v3, v0, v4
 ; GFX6-NEXT:    v_mul_lo_u32 v5, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v4, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v3
+; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v2
 ; GFX6-NEXT:    v_mul_hi_u32 v9, v1, v2
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GFX6-NEXT:    s_movk_i32 s4, 0x11e
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v3
-; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v4, vcc
-; GFX6-NEXT:    s_mov_b32 s10, -1
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v4, v3, vcc
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v8, v6, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v4
+; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v4
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v4, vcc
 ; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v9, v7, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v2
+; GFX6-NEXT:    v_add_i32_e64 v0, s[2:3], v0, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v8, v4, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s2
-; GFX6-NEXT:    v_mul_hi_u32 v5, v0, s3
-; GFX6-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
-; GFX6-NEXT:    v_mul_lo_u32 v6, v2, s3
-; GFX6-NEXT:    s_mov_b32 s2, 0x976a7377
+; GFX6-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[2:3]
+; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s4
+; GFX6-NEXT:    v_mul_hi_u32 v5, v0, s5
+; GFX6-NEXT:    v_mul_lo_u32 v6, v2, s5
+; GFX6-NEXT:    v_mul_lo_u32 v9, v0, s5
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
 ; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GFX6-NEXT:    v_mul_lo_u32 v5, v0, s3
 ; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
-; GFX6-NEXT:    v_mul_lo_u32 v6, v0, v4
+; GFX6-NEXT:    v_mul_lo_u32 v5, v0, v4
+; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v9
 ; GFX6-NEXT:    v_mul_hi_u32 v10, v0, v4
-; GFX6-NEXT:    v_mul_hi_u32 v9, v0, v5
 ; GFX6-NEXT:    v_mul_hi_u32 v11, v2, v4
-; GFX6-NEXT:    s_movk_i32 s3, 0x11f
-; GFX6-NEXT:    s_mov_b32 s9, s5
-; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v9, v6
-; GFX6-NEXT:    v_addc_u32_e32 v9, vcc, v8, v10, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v10, v2, v5
-; GFX6-NEXT:    v_mul_hi_u32 v5, v2, v5
+; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:    s_mov_b32 s8, s4
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
+; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, v8, v10, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v10, v2, v9
+; GFX6-NEXT:    v_mul_hi_u32 v9, v2, v9
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v2, v4
-; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v6, v10
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v9, v5, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v11, v7, vcc
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v4, vcc
+; GFX6-NEXT:    s_movk_i32 s4, 0x11e
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v10
+; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v6, v9, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v11, v7, vcc
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
+; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v5, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
-; GFX6-NEXT:    v_addc_u32_e64 v1, vcc, v1, v4, s[0:1]
+; GFX6-NEXT:    v_addc_u32_e64 v1, vcc, v1, v4, s[2:3]
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, s6, v1
@@ -7169,6 +7165,8 @@
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v8, v4, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v4, s7, v0
 ; GFX6-NEXT:    v_mul_hi_u32 v0, s7, v0
+; GFX6-NEXT:    s_movk_i32 s3, 0x11f
+; GFX6-NEXT:    s_mov_b32 s2, 0x976a7377
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
 ; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v5, v7, vcc
@@ -7178,6 +7176,7 @@
 ; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s2
 ; GFX6-NEXT:    v_mul_lo_u32 v4, v1, s2
 ; GFX6-NEXT:    v_mov_b32_e32 v5, s3
+; GFX6-NEXT:    s_mov_b32 s9, s5
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s2
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
@@ -7222,7 +7221,7 @@
 ; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
 ; GFX9-NEXT:    s_movk_i32 s4, 0xfee0
 ; GFX9-NEXT:    s_mov_b32 s5, 0x68958c89
-; GFX9-NEXT:    v_mov_b32_e32 v6, 0
+; GFX9-NEXT:    v_mov_b32_e32 v7, 0
 ; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
@@ -7239,43 +7238,43 @@
 ; GFX9-NEXT:    v_add_u32_e32 v2, v2, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v3, v0, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v5, v0, v2
-; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v2
-; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
-; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
-; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v4
+; GFX9-NEXT:    v_mul_hi_u32 v6, v0, v2
+; GFX9-NEXT:    v_mul_lo_u32 v8, v1, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v7, v3
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
+; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v6, vcc
+; GFX9-NEXT:    v_mul_hi_u32 v6, v1, v2
+; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v8, v3
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v6, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v6, v7, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
 ; GFX9-NEXT:    v_mov_b32_e32 v5, 0
 ; GFX9-NEXT:    v_add_co_u32_e64 v0, s[2:3], v0, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
 ; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s4
-; GFX9-NEXT:    v_mul_hi_u32 v7, v0, s5
+; GFX9-NEXT:    v_mul_hi_u32 v6, v0, s5
 ; GFX9-NEXT:    v_mul_lo_u32 v8, v2, s5
 ; GFX9-NEXT:    v_mul_lo_u32 v9, v0, s5
 ; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX9-NEXT:    v_add_u32_e32 v4, v7, v4
+; GFX9-NEXT:    v_add_u32_e32 v4, v6, v4
 ; GFX9-NEXT:    v_add_u32_e32 v4, v4, v8
-; GFX9-NEXT:    v_mul_lo_u32 v7, v0, v4
+; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v9
 ; GFX9-NEXT:    v_mul_hi_u32 v10, v0, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v11, v2, v4
 ; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
-; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v8, v7
+; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v8, v6
 ; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v10, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v10, v2, v9
 ; GFX9-NEXT:    v_mul_hi_u32 v9, v2, v9
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v2, v4
-; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v7, v10
-; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v8, v9, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v11, v6, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v7, v2
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v5, v4, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v6, v10
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v9, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v11, v7, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v4, v2
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v5, v6, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e64 v1, vcc, v1, v4, s[2:3]
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
@@ -7283,7 +7282,7 @@
 ; GFX9-NEXT:    v_mul_lo_u32 v2, s6, v1
 ; GFX9-NEXT:    v_mul_hi_u32 v3, s6, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v4, s6, v1
-; GFX9-NEXT:    v_mul_hi_u32 v7, s7, v1
+; GFX9-NEXT:    v_mul_hi_u32 v6, s7, v1
 ; GFX9-NEXT:    v_mul_lo_u32 v1, s7, v1
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
@@ -7292,7 +7291,7 @@
 ; GFX9-NEXT:    s_mov_b32 s2, 0x976a7377
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v4, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v7, v6, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v6, v7, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v5, v2, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v0, s8
@@ -7309,30 +7308,30 @@
 ; GFX9-NEXT:    v_subbrev_co_u32_e32 v4, vcc, 0, v4, vcc
 ; GFX9-NEXT:    s_movk_i32 s6, 0x11e
 ; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s6, v4
-; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
+; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
 ; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s9, v5
 ; GFX9-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
 ; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s8, v4
-; GFX9-NEXT:    v_cndmask_b32_e32 v4, v7, v5, vcc
+; GFX9-NEXT:    v_cndmask_b32_e32 v4, v6, v5, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, 2, v0
-; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v1, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v1, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, 1, v0
 ; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, 0, v1, vcc
 ; GFX9-NEXT:    v_cmp_ne_u32_e64 s[2:3], 0, v4
-; GFX9-NEXT:    v_cndmask_b32_e64 v4, v9, v7, s[2:3]
-; GFX9-NEXT:    v_mov_b32_e32 v7, s7
-; GFX9-NEXT:    v_subb_co_u32_e64 v2, vcc, v7, v2, s[0:1]
+; GFX9-NEXT:    v_cndmask_b32_e64 v4, v9, v6, s[2:3]
+; GFX9-NEXT:    v_mov_b32_e32 v6, s7
+; GFX9-NEXT:    v_subb_co_u32_e64 v2, vcc, v6, v2, s[0:1]
 ; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s6, v2
-; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
+; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
 ; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s9, v3
 ; GFX9-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
 ; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s8, v2
-; GFX9-NEXT:    v_cndmask_b32_e32 v2, v7, v3, vcc
+; GFX9-NEXT:    v_cndmask_b32_e32 v2, v6, v3, vcc
 ; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
 ; GFX9-NEXT:    v_cndmask_b32_e64 v2, v8, v5, s[2:3]
 ; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX9-NEXT:    global_store_dwordx2 v6, v[0:1], s[4:5]
+; GFX9-NEXT:    global_store_dwordx2 v7, v[0:1], s[4:5]
 ; GFX9-NEXT:    s_endpgm
   %r = udiv i64 %x, 1235195949943
   store i64 %r, i64 addrspace(1)* %out
@@ -7477,8 +7476,8 @@
 ; GFX6-NEXT:    v_mov_b32_e32 v0, 0x4f800000
 ; GFX6-NEXT:    v_madak_f32 v0, 0, v0, 0x457ff000
 ; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
-; GFX6-NEXT:    s_movk_i32 s6, 0xf001
-; GFX6-NEXT:    v_mov_b32_e32 v7, 0
+; GFX6-NEXT:    s_movk_i32 s4, 0xf001
+; GFX6-NEXT:    v_mov_b32_e32 v6, 0
 ; GFX6-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX6-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GFX6-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
@@ -7486,77 +7485,77 @@
 ; GFX6-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
-; GFX6-NEXT:    s_movk_i32 s0, 0xfff
-; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s6
-; GFX6-NEXT:    v_mul_lo_u32 v5, v1, s6
-; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s6
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
+; GFX6-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x9
+; GFX6-NEXT:    s_mov_b32 s11, 0xf000
+; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s4
+; GFX6-NEXT:    v_mul_lo_u32 v5, v1, s4
+; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s4
+; GFX6-NEXT:    s_mov_b32 s10, -1
 ; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, v0, v3
 ; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
-; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v4
+; GFX6-NEXT:    v_mul_hi_u32 v7, v0, v4
 ; GFX6-NEXT:    v_mul_lo_u32 v5, v0, v3
 ; GFX6-NEXT:    v_mul_hi_u32 v8, v0, v3
-; GFX6-NEXT:    v_mul_hi_u32 v9, v1, v3
+; GFX6-NEXT:    v_mul_hi_u32 v9, v1, v4
+; GFX6-NEXT:    v_mul_lo_u32 v4, v1, v4
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
+; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v6, v8, vcc
+; GFX6-NEXT:    v_mul_hi_u32 v8, v1, v3
 ; GFX6-NEXT:    v_mul_lo_u32 v3, v1, v3
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, v7, v8, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v8, v1, v4
-; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v6, v4, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v9, v2, vcc
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
+; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v7, v9, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v8, v2, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
 ; GFX6-NEXT:    v_add_i32_e64 v0, s[2:3], v0, v3
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v7, v5, vcc
-; GFX6-NEXT:    v_mul_hi_u32 v5, v0, s6
+; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v6, v5, vcc
+; GFX6-NEXT:    v_mul_hi_u32 v5, v0, s4
 ; GFX6-NEXT:    v_addc_u32_e64 v3, vcc, v1, v4, s[2:3]
-; GFX6-NEXT:    v_mul_lo_u32 v6, v3, s6
-; GFX6-NEXT:    v_mul_lo_u32 v8, v0, s6
+; GFX6-NEXT:    v_mul_lo_u32 v7, v3, s4
+; GFX6-NEXT:    v_mul_lo_u32 v8, v0, s4
 ; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, v0, v5
-; GFX6-NEXT:    s_mov_b32 s6, -1
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
-; GFX6-NEXT:    v_mul_lo_u32 v6, v0, v5
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xd
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; GFX6-NEXT:    v_mul_lo_u32 v7, v0, v5
 ; GFX6-NEXT:    v_mul_hi_u32 v9, v0, v8
 ; GFX6-NEXT:    v_mul_hi_u32 v10, v0, v5
 ; GFX6-NEXT:    v_mul_hi_u32 v11, v3, v5
-; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v9, v6
-; GFX6-NEXT:    v_addc_u32_e32 v9, vcc, v7, v10, vcc
+; GFX6-NEXT:    s_movk_i32 s0, 0xfff
+; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v9, v7
+; GFX6-NEXT:    v_addc_u32_e32 v9, vcc, v6, v10, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v10, v3, v8
 ; GFX6-NEXT:    v_mul_hi_u32 v8, v3, v8
 ; GFX6-NEXT:    v_mul_lo_u32 v3, v3, v5
-; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v6, v10
-; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, v9, v8, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v11, v2, vcc
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v7, v5, vcc
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v7, v10
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v9, v8, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v11, v2, vcc
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v6, v7, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v4
 ; GFX6-NEXT:    v_addc_u32_e64 v1, vcc, v1, v5, s[2:3]
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mul_lo_u32 v3, s10, v1
-; GFX6-NEXT:    v_mul_hi_u32 v4, s10, v0
-; GFX6-NEXT:    v_mul_hi_u32 v5, s10, v1
-; GFX6-NEXT:    v_mul_hi_u32 v6, s11, v1
-; GFX6-NEXT:    v_mul_lo_u32 v1, s11, v1
+; GFX6-NEXT:    v_mul_lo_u32 v3, s6, v1
+; GFX6-NEXT:    v_mul_hi_u32 v4, s6, v0
+; GFX6-NEXT:    v_mul_hi_u32 v5, s6, v1
+; GFX6-NEXT:    v_mul_hi_u32 v7, s7, v1
+; GFX6-NEXT:    v_mul_lo_u32 v1, s7, v1
 ; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v7, v5, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v5, s11, v0
-; GFX6-NEXT:    v_mul_hi_u32 v0, s11, v0
-; GFX6-NEXT:    s_lshr_b64 s[2:3], s[8:9], 12
+; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v6, v5, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v5, s7, v0
+; GFX6-NEXT:    v_mul_hi_u32 v0, s7, v0
+; GFX6-NEXT:    s_lshr_b64 s[2:3], s[4:5], 12
 ; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
 ; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v4, v0, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v6, v2, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v7, v2, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
-; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v7, v2, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v6, v2, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s0
 ; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s0
 ; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s0
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_mov_b32_e32 v3, s11
-; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s10, v4
+; GFX6-NEXT:    v_mov_b32_e32 v3, s7
+; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s6, v4
 ; GFX6-NEXT:    v_subb_u32_e32 v2, vcc, v3, v2, vcc
 ; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s0, v4
 ; GFX6-NEXT:    v_subbrev_u32_e32 v5, vcc, 0, v2, vcc
@@ -7581,7 +7580,7 @@
 ; GFX6-NEXT:    v_cndmask_b32_e64 v2, v0, v1, s[0:1]
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
 ; GFX6-NEXT:    v_mov_b32_e32 v1, s3
-; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[8:11], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: udiv_v2i64_mixed_pow2k_denom:
@@ -7590,8 +7589,8 @@
 ; GFX9-NEXT:    v_madak_f32 v0, 0, v0, 0x457ff000
 ; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
 ; GFX9-NEXT:    s_movk_i32 s4, 0xf001
-; GFX9-NEXT:    v_mov_b32_e32 v7, 0
-; GFX9-NEXT:    v_mov_b32_e32 v5, 0
+; GFX9-NEXT:    v_mov_b32_e32 v6, 0
+; GFX9-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
@@ -7600,76 +7599,76 @@
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GFX9-NEXT:    s_movk_i32 s8, 0xfff
 ; GFX9-NEXT:    v_mul_hi_u32 v2, v0, s4
-; GFX9-NEXT:    v_mul_lo_u32 v4, v1, s4
+; GFX9-NEXT:    v_mul_lo_u32 v5, v1, s4
 ; GFX9-NEXT:    v_mul_lo_u32 v3, v0, s4
 ; GFX9-NEXT:    v_sub_u32_e32 v2, v2, v0
-; GFX9-NEXT:    v_add_u32_e32 v2, v2, v4
-; GFX9-NEXT:    v_mul_hi_u32 v6, v0, v3
-; GFX9-NEXT:    v_mul_lo_u32 v4, v0, v2
+; GFX9-NEXT:    v_add_u32_e32 v2, v2, v5
+; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v3
+; GFX9-NEXT:    v_mul_lo_u32 v5, v0, v2
 ; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v2
-; GFX9-NEXT:    v_mul_hi_u32 v9, v1, v2
+; GFX9-NEXT:    v_mul_hi_u32 v9, v1, v3
+; GFX9-NEXT:    v_mul_lo_u32 v3, v1, v3
+; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v7, v5
+; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v6, v8, vcc
+; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v6, v4
-; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v7, v8, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v8, v1, v3
-; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v3
-; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v8, v4
-; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v3, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v9, v5, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v7, v9, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v8, v4, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
 ; GFX9-NEXT:    v_add_co_u32_e64 v0, s[2:3], v0, v2
-; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v7, v4, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v5, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
-; GFX9-NEXT:    v_mul_hi_u32 v4, v0, s4
-; GFX9-NEXT:    v_mul_lo_u32 v6, v2, s4
+; GFX9-NEXT:    v_mul_hi_u32 v5, v0, s4
+; GFX9-NEXT:    v_mul_lo_u32 v7, v2, s4
 ; GFX9-NEXT:    v_mul_lo_u32 v8, v0, s4
 ; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
-; GFX9-NEXT:    v_sub_u32_e32 v4, v4, v0
-; GFX9-NEXT:    v_add_u32_e32 v4, v4, v6
-; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v4
+; GFX9-NEXT:    v_sub_u32_e32 v5, v5, v0
+; GFX9-NEXT:    v_add_u32_e32 v5, v5, v7
+; GFX9-NEXT:    v_mul_lo_u32 v7, v0, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v9, v0, v8
-; GFX9-NEXT:    v_mul_hi_u32 v10, v0, v4
-; GFX9-NEXT:    v_mul_hi_u32 v11, v2, v4
+; GFX9-NEXT:    v_mul_hi_u32 v10, v0, v5
+; GFX9-NEXT:    v_mul_hi_u32 v11, v2, v5
 ; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
-; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v9, v6
-; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v7, v10, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v9, v7
+; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v6, v10, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v10, v2, v8
 ; GFX9-NEXT:    v_mul_hi_u32 v8, v2, v8
-; GFX9-NEXT:    v_mul_lo_u32 v2, v2, v4
+; GFX9-NEXT:    v_mul_lo_u32 v2, v2, v5
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    s_lshr_b64 s[4:5], s[4:5], 12
-; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v10
-; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v9, v8, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v11, v5, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v6, v2
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v7, v4, vcc
-; GFX9-NEXT:    v_addc_co_u32_e64 v1, vcc, v1, v4, s[2:3]
+; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v7, v10
+; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v9, v8, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v11, v4, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v5, v2
+; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v6, v7, vcc
+; GFX9-NEXT:    v_addc_co_u32_e64 v1, vcc, v1, v5, s[2:3]
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v2, s6, v1
 ; GFX9-NEXT:    v_mul_hi_u32 v3, s6, v0
-; GFX9-NEXT:    v_mul_hi_u32 v4, s6, v1
-; GFX9-NEXT:    v_mul_hi_u32 v6, s7, v1
+; GFX9-NEXT:    v_mul_hi_u32 v5, s6, v1
+; GFX9-NEXT:    v_mul_hi_u32 v7, s7, v1
 ; GFX9-NEXT:    v_mul_lo_u32 v1, s7, v1
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
-; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v7, v4, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v4, s7, v0
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v5, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v5, s7, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v0, s7, v0
 ; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
-; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v4, v2
+; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v5, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v6, v5, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v7, v4, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
-; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v7, v2, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s8
+; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v6, v2, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v5, v0, s8
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v1, s8
 ; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s8
-; GFX9-NEXT:    v_sub_co_u32_e32 v4, vcc, s6, v4
+; GFX9-NEXT:    v_sub_co_u32_e32 v5, vcc, s6, v5
 ; GFX9-NEXT:    s_movk_i32 s6, 0xffe
 ; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
 ; GFX9-NEXT:    v_mov_b32_e32 v3, s7
 ; GFX9-NEXT:    v_subb_co_u32_e32 v2, vcc, v3, v2, vcc
-; GFX9-NEXT:    v_subrev_co_u32_e32 v3, vcc, s8, v4
+; GFX9-NEXT:    v_subrev_co_u32_e32 v3, vcc, s8, v5
 ; GFX9-NEXT:    v_subbrev_co_u32_e32 v6, vcc, 0, v2, vcc
 ; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s6, v3
 ; GFX9-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
@@ -7679,11 +7678,11 @@
 ; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v1, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, 1, v0
 ; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, 0, v1, vcc
-; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s6, v4
-; GFX9-NEXT:    v_cndmask_b32_e64 v4, 0, -1, vcc
+; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s6, v5
+; GFX9-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
 ; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v2
 ; GFX9-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v3
-; GFX9-NEXT:    v_cndmask_b32_e32 v2, -1, v4, vcc
+; GFX9-NEXT:    v_cndmask_b32_e32 v2, -1, v5, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e64 v3, v9, v7, s[0:1]
 ; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
 ; GFX9-NEXT:    v_cndmask_b32_e32 v3, v1, v3, vcc
@@ -7692,7 +7691,7 @@
 ; GFX9-NEXT:    v_mov_b32_e32 v0, s4
 ; GFX9-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    global_store_dwordx4 v5, v[0:3], s[2:3]
+; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[2:3]
 ; GFX9-NEXT:    s_endpgm
   %r = udiv <2 x i64> %x, <i64 4096, i64 4095>
   store <2 x i64> %r, <2 x i64> addrspace(1)* %out
@@ -7767,8 +7766,8 @@
 ; GFX6-NEXT:    v_mov_b32_e32 v1, 0x4f800000
 ; GFX6-NEXT:    v_madmk_f32 v0, v1, 0x438f8000, v0
 ; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
-; GFX6-NEXT:    s_movk_i32 s2, 0xfee0
-; GFX6-NEXT:    s_mov_b32 s3, 0x689e0837
+; GFX6-NEXT:    s_movk_i32 s4, 0xfee0
+; GFX6-NEXT:    s_mov_b32 s5, 0x689e0837
 ; GFX6-NEXT:    v_mov_b32_e32 v8, 0
 ; GFX6-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GFX6-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
@@ -7777,60 +7776,58 @@
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GFX6-NEXT:    v_mov_b32_e32 v7, 0
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s2
-; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s3
-; GFX6-NEXT:    v_mul_lo_u32 v4, v1, s3
 ; GFX6-NEXT:    s_movk_i32 s12, 0x11f
+; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s4
+; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s5
+; GFX6-NEXT:    v_mul_lo_u32 v5, v1, s5
+; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s5
 ; GFX6-NEXT:    s_mov_b32 s13, 0x9761f7c9
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s3
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
+; GFX6-NEXT:    v_mul_hi_u32 v3, v0, v4
 ; GFX6-NEXT:    v_mul_lo_u32 v5, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v4, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v3
+; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v2
 ; GFX6-NEXT:    v_mul_hi_u32 v9, v1, v2
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    s_mov_b32 s9, s5
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v3
-; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v4, vcc
-; GFX6-NEXT:    s_movk_i32 s5, 0x11e
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v4, v3, vcc
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v8, v6, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v4
+; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v4
+; GFX6-NEXT:    s_mov_b32 s11, 0xf000
+; GFX6-NEXT:    s_mov_b32 s10, -1
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v4, vcc
 ; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v9, v7, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v2
+; GFX6-NEXT:    v_add_i32_e64 v0, s[2:3], v0, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v8, v4, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s2
-; GFX6-NEXT:    v_mul_hi_u32 v5, v0, s3
-; GFX6-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
-; GFX6-NEXT:    v_mul_lo_u32 v6, v2, s3
-; GFX6-NEXT:    s_mov_b32 s8, s4
+; GFX6-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[2:3]
+; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s4
+; GFX6-NEXT:    v_mul_hi_u32 v5, v0, s5
+; GFX6-NEXT:    v_mul_lo_u32 v6, v2, s5
+; GFX6-NEXT:    v_mul_lo_u32 v9, v0, s5
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
 ; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GFX6-NEXT:    v_mul_lo_u32 v5, v0, s3
 ; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
-; GFX6-NEXT:    v_mul_lo_u32 v6, v0, v4
+; GFX6-NEXT:    v_mul_lo_u32 v5, v0, v4
+; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v9
 ; GFX6-NEXT:    v_mul_hi_u32 v10, v0, v4
-; GFX6-NEXT:    v_mul_hi_u32 v9, v0, v5
 ; GFX6-NEXT:    v_mul_hi_u32 v11, v2, v4
-; GFX6-NEXT:    s_mov_b32 s4, 0x9761f7c8
-; GFX6-NEXT:    s_mov_b32 s11, 0xf000
-; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v9, v6
-; GFX6-NEXT:    v_addc_u32_e32 v9, vcc, v8, v10, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v10, v2, v5
-; GFX6-NEXT:    v_mul_hi_u32 v5, v2, v5
+; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:    s_mov_b32 s9, s5
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
+; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, v8, v10, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v10, v2, v9
+; GFX6-NEXT:    v_mul_hi_u32 v9, v2, v9
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v2, v4
-; GFX6-NEXT:    s_mov_b32 s10, -1
-; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v6, v10
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v9, v5, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v11, v7, vcc
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v4, vcc
+; GFX6-NEXT:    s_movk_i32 s5, 0x11e
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v10
+; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v6, v9, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v11, v7, vcc
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
+; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v5, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
-; GFX6-NEXT:    v_addc_u32_e64 v1, vcc, v1, v4, s[0:1]
+; GFX6-NEXT:    v_addc_u32_e64 v1, vcc, v1, v4, s[2:3]
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, s6, v1
@@ -7842,6 +7839,8 @@
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v8, v4, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v4, s7, v0
 ; GFX6-NEXT:    v_mul_hi_u32 v0, s7, v0
+; GFX6-NEXT:    s_mov_b32 s8, s4
+; GFX6-NEXT:    s_mov_b32 s4, 0x9761f7c8
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
 ; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v5, v7, vcc
@@ -7893,7 +7892,7 @@
 ; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
 ; GFX9-NEXT:    s_movk_i32 s4, 0xfee0
 ; GFX9-NEXT:    s_mov_b32 s5, 0x689e0837
-; GFX9-NEXT:    v_mov_b32_e32 v6, 0
+; GFX9-NEXT:    v_mov_b32_e32 v7, 0
 ; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
@@ -7911,43 +7910,43 @@
 ; GFX9-NEXT:    v_add_u32_e32 v2, v2, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v3, v0, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v5, v0, v2
-; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v2
-; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
-; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
-; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v4
+; GFX9-NEXT:    v_mul_hi_u32 v6, v0, v2
+; GFX9-NEXT:    v_mul_lo_u32 v8, v1, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v7, v3
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
+; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v6, vcc
+; GFX9-NEXT:    v_mul_hi_u32 v6, v1, v2
+; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v8, v3
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v6, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v6, v7, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
 ; GFX9-NEXT:    v_mov_b32_e32 v5, 0
 ; GFX9-NEXT:    v_add_co_u32_e64 v0, s[2:3], v0, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
 ; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s4
-; GFX9-NEXT:    v_mul_hi_u32 v7, v0, s5
+; GFX9-NEXT:    v_mul_hi_u32 v6, v0, s5
 ; GFX9-NEXT:    v_mul_lo_u32 v8, v2, s5
 ; GFX9-NEXT:    v_mul_lo_u32 v9, v0, s5
 ; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX9-NEXT:    v_add_u32_e32 v4, v7, v4
+; GFX9-NEXT:    v_add_u32_e32 v4, v6, v4
 ; GFX9-NEXT:    v_add_u32_e32 v4, v4, v8
-; GFX9-NEXT:    v_mul_lo_u32 v7, v0, v4
+; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v9
 ; GFX9-NEXT:    v_mul_hi_u32 v10, v0, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v11, v2, v4
 ; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
-; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v8, v7
+; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v8, v6
 ; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v10, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v10, v2, v9
 ; GFX9-NEXT:    v_mul_hi_u32 v9, v2, v9
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v2, v4
-; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v7, v10
-; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v8, v9, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v11, v6, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v7, v2
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v5, v4, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v6, v10
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v9, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v11, v7, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v4, v2
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v5, v6, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e64 v1, vcc, v1, v4, s[2:3]
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
@@ -7955,7 +7954,7 @@
 ; GFX9-NEXT:    v_mul_lo_u32 v2, s6, v1
 ; GFX9-NEXT:    v_mul_hi_u32 v3, s6, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v4, s6, v1
-; GFX9-NEXT:    v_mul_hi_u32 v7, s7, v1
+; GFX9-NEXT:    v_mul_hi_u32 v6, s7, v1
 ; GFX9-NEXT:    v_mul_lo_u32 v1, s7, v1
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
@@ -7963,7 +7962,7 @@
 ; GFX9-NEXT:    v_mul_hi_u32 v0, s7, v0
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v4, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v7, v6, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v6, v7, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v5, v2, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v0, s8
@@ -7980,29 +7979,29 @@
 ; GFX9-NEXT:    v_subbrev_co_u32_e64 v5, vcc, 0, v2, s[2:3]
 ; GFX9-NEXT:    s_movk_i32 s6, 0x11e
 ; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s6, v5
-; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
+; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
 ; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s10, v4
 ; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
 ; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s8, v5
-; GFX9-NEXT:    v_cndmask_b32_e32 v7, v7, v8, vcc
+; GFX9-NEXT:    v_cndmask_b32_e32 v6, v6, v8, vcc
 ; GFX9-NEXT:    v_subb_co_u32_e64 v2, vcc, v2, v3, s[2:3]
 ; GFX9-NEXT:    v_subrev_co_u32_e32 v3, vcc, s9, v4
 ; GFX9-NEXT:    v_subbrev_co_u32_e32 v2, vcc, 0, v2, vcc
-; GFX9-NEXT:    v_cmp_ne_u32_e64 s[2:3], 0, v7
+; GFX9-NEXT:    v_cmp_ne_u32_e64 s[2:3], 0, v6
 ; GFX9-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[2:3]
 ; GFX9-NEXT:    v_mov_b32_e32 v5, s7
 ; GFX9-NEXT:    v_subb_co_u32_e64 v1, vcc, v5, v1, s[0:1]
 ; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s6, v1
 ; GFX9-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
 ; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s10, v0
-; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
+; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
 ; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s8, v1
-; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc
+; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
 ; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
 ; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[2:3]
 ; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX9-NEXT:    global_store_dwordx2 v6, v[0:1], s[4:5]
+; GFX9-NEXT:    global_store_dwordx2 v7, v[0:1], s[4:5]
 ; GFX9-NEXT:    s_endpgm
   %r = urem i64 %x, 1235195393993
   store i64 %r, i64 addrspace(1)* %out
@@ -8218,88 +8217,86 @@
 ; GFX6-NEXT:    v_mov_b32_e32 v0, 0x4f800000
 ; GFX6-NEXT:    v_madak_f32 v0, 0, v0, 0x4996c7d8
 ; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
-; GFX6-NEXT:    s_mov_b32 s2, 0xffed2705
-; GFX6-NEXT:    v_mov_b32_e32 v8, 0
-; GFX6-NEXT:    v_mov_b32_e32 v7, 0
+; GFX6-NEXT:    s_mov_b32 s8, 0xffed2705
+; GFX6-NEXT:    v_mov_b32_e32 v6, 0
+; GFX6-NEXT:    v_mov_b32_e32 v5, 0
 ; GFX6-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GFX6-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX6-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    v_mul_hi_u32 v3, s2, v0
-; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s2
-; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s2
-; GFX6-NEXT:    s_mov_b32 s6, -1
-; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    s_mov_b32 s4, s8
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GFX6-NEXT:    v_mul_hi_u32 v3, s8, v0
+; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s8
+; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s8
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
-; GFX6-NEXT:    v_mul_lo_u32 v5, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v4
-; GFX6-NEXT:    v_mul_hi_u32 v3, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v9, v1, v2
+; GFX6-NEXT:    v_mul_hi_u32 v3, v0, v4
+; GFX6-NEXT:    v_mul_lo_u32 v7, v0, v2
+; GFX6-NEXT:    v_mul_hi_u32 v8, v0, v2
+; GFX6-NEXT:    v_mul_hi_u32 v9, v1, v4
+; GFX6-NEXT:    v_mul_lo_u32 v4, v1, v4
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
+; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v6, v8, vcc
+; GFX6-NEXT:    v_mul_hi_u32 v8, v1, v2
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v4
-; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v8, v3, vcc
-; GFX6-NEXT:    s_mov_b32 s5, s9
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v3, v4, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v9, v7, vcc
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v7, v9, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v5, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v2
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v8, v4, vcc
-; GFX6-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
-; GFX6-NEXT:    v_mul_lo_u32 v4, v2, s2
-; GFX6-NEXT:    v_mul_hi_u32 v5, s2, v0
-; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GFX6-NEXT:    v_mul_lo_u32 v5, v0, s2
+; GFX6-NEXT:    v_add_i32_e64 v0, s[2:3], v0, v2
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v6, v4, vcc
+; GFX6-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[2:3]
+; GFX6-NEXT:    v_mul_lo_u32 v4, v2, s8
+; GFX6-NEXT:    v_mul_hi_u32 v7, s8, v0
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
+; GFX6-NEXT:    v_mul_lo_u32 v7, v0, s8
 ; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, v0, v4
-; GFX6-NEXT:    v_mul_lo_u32 v10, v0, v4
-; GFX6-NEXT:    v_mul_hi_u32 v12, v0, v4
-; GFX6-NEXT:    v_mul_hi_u32 v11, v0, v5
-; GFX6-NEXT:    v_mul_hi_u32 v9, v2, v5
-; GFX6-NEXT:    v_mul_lo_u32 v5, v2, v5
-; GFX6-NEXT:    v_mul_hi_u32 v6, v2, v4
-; GFX6-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; GFX6-NEXT:    v_addc_u32_e32 v11, vcc, v8, v12, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v9, v0, v4
+; GFX6-NEXT:    v_mul_hi_u32 v11, v0, v4
+; GFX6-NEXT:    v_mul_hi_u32 v10, v0, v7
+; GFX6-NEXT:    v_mul_hi_u32 v12, v2, v7
+; GFX6-NEXT:    v_mul_lo_u32 v7, v2, v7
+; GFX6-NEXT:    v_mul_hi_u32 v8, v2, v4
+; GFX6-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
+; GFX6-NEXT:    v_addc_u32_e32 v10, vcc, v6, v11, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v2, v4
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v10, v5
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v11, v9, vcc
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v9, v7
+; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v10, v12, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v8, v5, vcc
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v6, v7, vcc
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v4, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
-; GFX6-NEXT:    s_ashr_i32 s2, s11, 31
-; GFX6-NEXT:    v_addc_u32_e64 v1, vcc, v1, v4, s[0:1]
-; GFX6-NEXT:    s_add_u32 s0, s10, s2
+; GFX6-NEXT:    v_addc_u32_e64 v1, vcc, v1, v4, s[2:3]
+; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:    s_ashr_i32 s2, s7, 31
+; GFX6-NEXT:    s_add_u32 s0, s6, s2
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT:    s_addc_u32 s1, s7, s2
 ; GFX6-NEXT:    s_mov_b32 s3, s2
-; GFX6-NEXT:    s_addc_u32 s1, s11, s2
 ; GFX6-NEXT:    s_xor_b64 s[0:1], s[0:1], s[2:3]
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, s0, v1
 ; GFX6-NEXT:    v_mul_hi_u32 v3, s0, v0
 ; GFX6-NEXT:    v_mul_hi_u32 v4, s0, v1
-; GFX6-NEXT:    v_mul_hi_u32 v5, s1, v1
+; GFX6-NEXT:    v_mul_hi_u32 v7, s1, v1
 ; GFX6-NEXT:    v_mul_lo_u32 v1, s1, v1
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v8, v4, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v6, v4, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v4, s1, v0
 ; GFX6-NEXT:    v_mul_hi_u32 v0, s1, v0
 ; GFX6-NEXT:    s_mov_b32 s3, 0x12d8fb
+; GFX6-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v5, v7, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v7, v5, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
-; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v8, v2, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v6, v2, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s3
 ; GFX6-NEXT:    v_mul_hi_u32 v3, s3, v0
 ; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s3
+; GFX6-NEXT:    s_mov_b32 s6, -1
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s0, v4
 ; GFX6-NEXT:    v_mov_b32_e32 v3, s1
@@ -8339,7 +8336,7 @@
 ; GFX9-NEXT:    v_madak_f32 v0, 0, v0, 0x4996c7d8
 ; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
 ; GFX9-NEXT:    s_mov_b32 s8, 0xffed2705
-; GFX9-NEXT:    v_mov_b32_e32 v7, 0
+; GFX9-NEXT:    v_mov_b32_e32 v6, 0
 ; GFX9-NEXT:    v_mov_b32_e32 v5, 0
 ; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
@@ -8354,41 +8351,41 @@
 ; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
 ; GFX9-NEXT:    v_sub_u32_e32 v2, v2, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v3, v0, v4
-; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v2
+; GFX9-NEXT:    v_mul_lo_u32 v7, v0, v2
 ; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v2
-; GFX9-NEXT:    v_mul_hi_u32 v9, v1, v2
+; GFX9-NEXT:    v_mul_hi_u32 v9, v1, v4
+; GFX9-NEXT:    v_mul_lo_u32 v4, v1, v4
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v7
+; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v6, v8, vcc
+; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v6
-; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v7, v8, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v8, v1, v4
-; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v8, v3
-; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v4, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v9, v5, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v7, v9, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v5, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
 ; GFX9-NEXT:    v_add_co_u32_e64 v0, s[2:3], v0, v2
-; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v7, v4, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v4, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
 ; GFX9-NEXT:    v_mul_lo_u32 v4, v2, s8
-; GFX9-NEXT:    v_mul_hi_u32 v6, s8, v0
-; GFX9-NEXT:    v_mul_lo_u32 v8, v0, s8
+; GFX9-NEXT:    v_mul_hi_u32 v7, s8, v0
 ; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
-; GFX9-NEXT:    v_add_u32_e32 v4, v6, v4
+; GFX9-NEXT:    v_add_u32_e32 v4, v7, v4
+; GFX9-NEXT:    v_mul_lo_u32 v7, v0, s8
 ; GFX9-NEXT:    v_sub_u32_e32 v4, v4, v0
-; GFX9-NEXT:    v_mul_lo_u32 v10, v0, v4
-; GFX9-NEXT:    v_mul_hi_u32 v11, v0, v8
-; GFX9-NEXT:    v_mul_hi_u32 v12, v0, v4
-; GFX9-NEXT:    v_mul_hi_u32 v9, v2, v8
-; GFX9-NEXT:    v_mul_lo_u32 v8, v2, v8
-; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
-; GFX9-NEXT:    v_mul_hi_u32 v6, v2, v4
-; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, v7, v12, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v9, v0, v4
+; GFX9-NEXT:    v_mul_hi_u32 v11, v0, v4
+; GFX9-NEXT:    v_mul_hi_u32 v10, v0, v7
+; GFX9-NEXT:    v_mul_hi_u32 v12, v2, v7
+; GFX9-NEXT:    v_mul_lo_u32 v7, v2, v7
+; GFX9-NEXT:    v_mul_hi_u32 v8, v2, v4
+; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v10, v9
+; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v6, v11, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v2, v4
-; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v10, v8
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v11, v9, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v6, v5, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v8, v2
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v7, v4, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v9, v7
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v10, v12, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v8, v5, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v4, v2
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v6, v7, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e64 v1, vcc, v1, v4, s[2:3]
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    s_ashr_i32 s2, s7, 31
@@ -8401,18 +8398,18 @@
 ; GFX9-NEXT:    v_mul_lo_u32 v2, s0, v1
 ; GFX9-NEXT:    v_mul_hi_u32 v3, s0, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v4, s0, v1
-; GFX9-NEXT:    v_mul_hi_u32 v6, s1, v1
+; GFX9-NEXT:    v_mul_hi_u32 v7, s1, v1
 ; GFX9-NEXT:    v_mul_lo_u32 v1, s1, v1
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
-; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v7, v4, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v4, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v4, s1, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v0, s1, v0
 ; GFX9-NEXT:    s_mov_b32 s3, 0x12d8fb
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v4, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v6, v5, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v7, v5, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
-; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v7, v2, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v6, v2, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s3
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v1, s3
 ; GFX9-NEXT:    v_mul_hi_u32 v3, s3, v0
@@ -8508,114 +8505,113 @@
 ; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xd
 ; GFX6-NEXT:    s_mov_b32 s3, 0
 ; GFX6-NEXT:    s_movk_i32 s2, 0x1000
-; GFX6-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
+; GFX6-NEXT:    v_mov_b32_e32 v3, 0
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_lshl_b64 s[2:3], s[2:3], s4
-; GFX6-NEXT:    s_ashr_i32 s12, s3, 31
-; GFX6-NEXT:    s_add_u32 s2, s2, s12
-; GFX6-NEXT:    s_mov_b32 s13, s12
-; GFX6-NEXT:    s_addc_u32 s3, s3, s12
-; GFX6-NEXT:    s_xor_b64 s[2:3], s[2:3], s[12:13]
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s2
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s3
-; GFX6-NEXT:    s_sub_u32 s4, 0, s2
-; GFX6-NEXT:    s_subb_u32 s5, 0, s3
-; GFX6-NEXT:    s_ashr_i32 s14, s11, 31
+; GFX6-NEXT:    s_ashr_i32 s8, s3, 31
+; GFX6-NEXT:    s_add_u32 s2, s2, s8
+; GFX6-NEXT:    s_mov_b32 s9, s8
+; GFX6-NEXT:    s_addc_u32 s3, s3, s8
+; GFX6-NEXT:    s_xor_b64 s[10:11], s[2:3], s[8:9]
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s10
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s11
+; GFX6-NEXT:    s_sub_u32 s12, 0, s10
+; GFX6-NEXT:    s_subb_u32 s4, 0, s11
 ; GFX6-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
 ; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
-; GFX6-NEXT:    s_mov_b32 s15, s14
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX6-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GFX6-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
-; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
-; GFX6-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
+; GFX6-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
+; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
+; GFX6-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT:    v_mul_hi_u32 v3, s4, v0
-; GFX6-NEXT:    v_mul_lo_u32 v2, s4, v1
-; GFX6-NEXT:    v_mul_lo_u32 v5, s5, v0
-; GFX6-NEXT:    v_mul_lo_u32 v4, s4, v0
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v2
+; GFX6-NEXT:    v_mul_hi_u32 v5, s12, v0
+; GFX6-NEXT:    v_mul_lo_u32 v4, s12, v2
+; GFX6-NEXT:    v_mul_lo_u32 v7, s4, v0
+; GFX6-NEXT:    v_mul_lo_u32 v6, s12, v0
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; GFX6-NEXT:    v_mul_hi_u32 v5, v0, v6
+; GFX6-NEXT:    v_mul_lo_u32 v7, v0, v4
+; GFX6-NEXT:    v_mul_hi_u32 v9, v0, v4
+; GFX6-NEXT:    v_mul_hi_u32 v8, v2, v6
+; GFX6-NEXT:    v_mul_lo_u32 v6, v2, v6
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; GFX6-NEXT:    v_mul_hi_u32 v10, v2, v4
+; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, 0, v9, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v4, v2, v4
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v7, v8, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, v10, v1, vcc
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; GFX6-NEXT:    v_add_i32_e64 v0, s[2:3], v0, v4
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v3, v6, vcc
+; GFX6-NEXT:    v_addc_u32_e64 v4, vcc, v2, v5, s[2:3]
+; GFX6-NEXT:    v_mul_lo_u32 v6, s12, v4
+; GFX6-NEXT:    v_mul_hi_u32 v7, s12, v0
+; GFX6-NEXT:    v_mul_lo_u32 v8, s4, v0
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GFX6-NEXT:    v_mul_lo_u32 v7, s12, v0
+; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
+; GFX6-NEXT:    v_mul_lo_u32 v9, v0, v6
+; GFX6-NEXT:    v_mul_hi_u32 v11, v0, v6
+; GFX6-NEXT:    v_mul_hi_u32 v10, v0, v7
+; GFX6-NEXT:    v_mul_hi_u32 v12, v4, v7
+; GFX6-NEXT:    v_mul_lo_u32 v7, v4, v7
+; GFX6-NEXT:    v_mul_hi_u32 v8, v4, v6
+; GFX6-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
+; GFX6-NEXT:    v_addc_u32_e32 v10, vcc, 0, v11, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v4, v4, v6
+; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v9, v7
+; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, v10, v12, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v8, v1, vcc
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
+; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, v3, v7, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
-; GFX6-NEXT:    v_mul_hi_u32 v3, v0, v4
-; GFX6-NEXT:    v_mul_lo_u32 v5, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v7, v1, v2
-; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
+; GFX6-NEXT:    v_addc_u32_e64 v2, vcc, v2, v6, s[2:3]
+; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:    s_ashr_i32 s2, s7, 31
+; GFX6-NEXT:    s_add_u32 s0, s6, s2
+; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
+; GFX6-NEXT:    s_addc_u32 s1, s7, s2
+; GFX6-NEXT:    s_mov_b32 s3, s2
+; GFX6-NEXT:    s_xor_b64 s[12:13], s[0:1], s[2:3]
+; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v4, s12, v2
+; GFX6-NEXT:    v_mul_hi_u32 v5, s12, v0
+; GFX6-NEXT:    v_mul_hi_u32 v6, s12, v2
+; GFX6-NEXT:    v_mul_hi_u32 v7, s13, v2
+; GFX6-NEXT:    v_mul_lo_u32 v2, s13, v2
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v4
-; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v4, vcc
-; GFX6-NEXT:    v_mov_b32_e32 v4, 0
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v7, v4, vcc
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_mov_b32_e32 v6, 0
-; GFX6-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v2
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v6, v5, vcc
-; GFX6-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
-; GFX6-NEXT:    v_mul_lo_u32 v5, s4, v2
-; GFX6-NEXT:    v_mul_hi_u32 v7, s4, v0
-; GFX6-NEXT:    v_mul_lo_u32 v8, s5, v0
-; GFX6-NEXT:    s_mov_b32 s5, s9
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
-; GFX6-NEXT:    v_mul_lo_u32 v7, s4, v0
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; GFX6-NEXT:    v_mul_lo_u32 v10, v0, v5
-; GFX6-NEXT:    v_mul_hi_u32 v12, v0, v5
-; GFX6-NEXT:    v_mul_hi_u32 v11, v0, v7
-; GFX6-NEXT:    v_mul_hi_u32 v9, v2, v7
-; GFX6-NEXT:    v_mul_lo_u32 v7, v2, v7
-; GFX6-NEXT:    v_mul_hi_u32 v8, v2, v5
-; GFX6-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; GFX6-NEXT:    v_addc_u32_e32 v11, vcc, 0, v12, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v2, v2, v5
-; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
-; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v11, v9, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v8, v4, vcc
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v7, v2
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v6, v5, vcc
-; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
-; GFX6-NEXT:    v_addc_u32_e64 v1, vcc, v1, v5, s[0:1]
-; GFX6-NEXT:    s_add_u32 s0, s10, s14
-; GFX6-NEXT:    s_addc_u32 s1, s11, s14
+; GFX6-NEXT:    v_mul_lo_u32 v6, s13, v0
+; GFX6-NEXT:    v_mul_hi_u32 v0, s13, v0
+; GFX6-NEXT:    s_mov_b32 s7, 0xf000
+; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
+; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v5, v0, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v7, v1, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
-; GFX6-NEXT:    s_xor_b64 s[10:11], s[0:1], s[14:15]
-; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v3, v1, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, s10, v1
 ; GFX6-NEXT:    v_mul_hi_u32 v3, s10, v0
-; GFX6-NEXT:    v_mul_hi_u32 v5, s10, v1
-; GFX6-NEXT:    v_mul_hi_u32 v7, s11, v1
-; GFX6-NEXT:    v_mul_lo_u32 v1, s11, v1
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v5, s11, v0
-; GFX6-NEXT:    v_mul_hi_u32 v0, s11, v0
-; GFX6-NEXT:    s_mov_b32 s4, s8
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
-; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v7, v4, vcc
-; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
-; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v6, v2, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v2, s2, v1
-; GFX6-NEXT:    v_mul_hi_u32 v3, s2, v0
-; GFX6-NEXT:    v_mul_lo_u32 v4, s3, v0
-; GFX6-NEXT:    v_mov_b32_e32 v5, s3
+; GFX6-NEXT:    v_mul_lo_u32 v4, s11, v0
+; GFX6-NEXT:    v_mov_b32_e32 v5, s11
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_mul_lo_u32 v3, s2, v0
+; GFX6-NEXT:    v_mul_lo_u32 v3, s10, v0
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
-; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s11, v2
-; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s10, v3
+; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s13, v2
+; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s12, v3
 ; GFX6-NEXT:    v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
-; GFX6-NEXT:    v_subrev_i32_e64 v5, s[0:1], s2, v3
+; GFX6-NEXT:    v_subrev_i32_e64 v5, s[0:1], s10, v3
 ; GFX6-NEXT:    v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
-; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s3, v4
+; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s11, v4
 ; GFX6-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
-; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s2, v5
+; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s10, v5
 ; GFX6-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
-; GFX6-NEXT:    v_cmp_eq_u32_e64 s[0:1], s3, v4
+; GFX6-NEXT:    v_cmp_eq_u32_e64 s[0:1], s11, v4
 ; GFX6-NEXT:    v_cndmask_b32_e64 v4, v6, v5, s[0:1]
 ; GFX6-NEXT:    v_add_i32_e64 v5, s[0:1], 2, v0
 ; GFX6-NEXT:    v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1]
@@ -8623,18 +8619,18 @@
 ; GFX6-NEXT:    v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1]
 ; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v4
 ; GFX6-NEXT:    v_cndmask_b32_e64 v4, v8, v6, s[0:1]
-; GFX6-NEXT:    v_mov_b32_e32 v6, s11
+; GFX6-NEXT:    v_mov_b32_e32 v6, s13
 ; GFX6-NEXT:    v_subb_u32_e32 v2, vcc, v6, v2, vcc
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s3, v2
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s11, v2
 ; GFX6-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s2, v3
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v3
 ; GFX6-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
-; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s3, v2
+; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s11, v2
 ; GFX6-NEXT:    v_cndmask_b32_e32 v2, v6, v3, vcc
 ; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
 ; GFX6-NEXT:    v_cndmask_b32_e64 v2, v7, v5, s[0:1]
 ; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX6-NEXT:    s_xor_b64 s[0:1], s[14:15], s[12:13]
+; GFX6-NEXT:    s_xor_b64 s[0:1], s[2:3], s[8:9]
 ; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
 ; GFX6-NEXT:    v_xor_b32_e32 v0, s0, v0
 ; GFX6-NEXT:    v_xor_b32_e32 v1, s1, v1
@@ -8650,6 +8646,7 @@
 ; GFX9-NEXT:    s_mov_b32 s3, 0
 ; GFX9-NEXT:    s_movk_i32 s2, 0x1000
 ; GFX9-NEXT:    v_mov_b32_e32 v2, 0
+; GFX9-NEXT:    v_mov_b32_e32 v3, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    s_lshl_b64 s[2:3], s[2:3], s4
 ; GFX9-NEXT:    s_ashr_i32 s8, s3, 31
@@ -8669,74 +8666,73 @@
 ; GFX9-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX9-NEXT:    v_mul_hi_u32 v4, s12, v0
-; GFX9-NEXT:    v_mul_lo_u32 v3, s12, v1
-; GFX9-NEXT:    v_mul_lo_u32 v6, s4, v0
-; GFX9-NEXT:    v_mul_lo_u32 v5, s12, v0
-; GFX9-NEXT:    v_add_u32_e32 v3, v4, v3
-; GFX9-NEXT:    v_add_u32_e32 v3, v3, v6
-; GFX9-NEXT:    v_mul_hi_u32 v4, v0, v5
-; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v3
-; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v3
-; GFX9-NEXT:    v_mul_hi_u32 v7, v1, v5
-; GFX9-NEXT:    v_mul_lo_u32 v5, v1, v5
-; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v6
-; GFX9-NEXT:    v_mul_hi_u32 v9, v1, v3
-; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v8, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v3, v1, v3
+; GFX9-NEXT:    v_mul_hi_u32 v5, s12, v0
+; GFX9-NEXT:    v_mul_lo_u32 v4, s12, v1
+; GFX9-NEXT:    v_mul_lo_u32 v7, s4, v0
+; GFX9-NEXT:    v_mul_lo_u32 v6, s12, v0
+; GFX9-NEXT:    v_add_u32_e32 v4, v5, v4
+; GFX9-NEXT:    v_add_u32_e32 v4, v4, v7
+; GFX9-NEXT:    v_mul_hi_u32 v5, v0, v6
+; GFX9-NEXT:    v_mul_lo_u32 v7, v0, v4
+; GFX9-NEXT:    v_mul_hi_u32 v9, v0, v4
+; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v6
+; GFX9-NEXT:    v_mul_lo_u32 v6, v1, v6
+; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v7
+; GFX9-NEXT:    v_mul_hi_u32 v10, v1, v4
+; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v9, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v4, v1, v4
+; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v6, v5
+; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v7, v8, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v10, v2, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v5, v4
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v6, v7, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v9, v2, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
-; GFX9-NEXT:    v_mov_b32_e32 v6, 0
-; GFX9-NEXT:    v_add_co_u32_e64 v0, s[2:3], v0, v3
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v6, v5, vcc
-; GFX9-NEXT:    v_addc_co_u32_e64 v3, vcc, v1, v4, s[2:3]
-; GFX9-NEXT:    v_mul_lo_u32 v5, s12, v3
+; GFX9-NEXT:    v_add_co_u32_e64 v0, s[2:3], v0, v4
+; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v3, v6, vcc
+; GFX9-NEXT:    v_addc_co_u32_e64 v4, vcc, v1, v5, s[2:3]
+; GFX9-NEXT:    v_mul_lo_u32 v6, s12, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v7, s12, v0
 ; GFX9-NEXT:    v_mul_lo_u32 v8, s4, v0
-; GFX9-NEXT:    v_mul_lo_u32 v9, s12, v0
 ; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX9-NEXT:    v_add_u32_e32 v5, v7, v5
-; GFX9-NEXT:    v_add_u32_e32 v5, v5, v8
-; GFX9-NEXT:    v_mul_lo_u32 v10, v0, v5
-; GFX9-NEXT:    v_mul_hi_u32 v11, v0, v9
-; GFX9-NEXT:    v_mul_hi_u32 v12, v0, v5
-; GFX9-NEXT:    v_mul_hi_u32 v8, v3, v9
-; GFX9-NEXT:    v_mul_lo_u32 v9, v3, v9
-; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
-; GFX9-NEXT:    v_mul_hi_u32 v7, v3, v5
-; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, 0, v12, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v3, v3, v5
+; GFX9-NEXT:    v_add_u32_e32 v1, v1, v5
+; GFX9-NEXT:    v_add_u32_e32 v6, v7, v6
+; GFX9-NEXT:    v_mul_lo_u32 v7, s12, v0
+; GFX9-NEXT:    v_add_u32_e32 v6, v6, v8
+; GFX9-NEXT:    v_mul_lo_u32 v9, v0, v6
+; GFX9-NEXT:    v_mul_hi_u32 v11, v0, v6
+; GFX9-NEXT:    v_mul_hi_u32 v10, v0, v7
+; GFX9-NEXT:    v_mul_hi_u32 v12, v4, v7
+; GFX9-NEXT:    v_mul_lo_u32 v7, v4, v7
+; GFX9-NEXT:    v_mul_hi_u32 v8, v4, v6
 ; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v10, v9
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v11, v8, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v7, v2, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v8, v3
+; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, 0, v11, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v4, v4, v6
+; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v9, v7
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v10, v12, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v8, v2, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v6, v4
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    s_ashr_i32 s12, s7, 31
-; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v6, v5, vcc
-; GFX9-NEXT:    v_add_u32_e32 v1, v1, v4
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v3, v7, vcc
 ; GFX9-NEXT:    s_add_u32 s0, s6, s12
-; GFX9-NEXT:    v_addc_co_u32_e64 v1, vcc, v1, v5, s[2:3]
-; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v3
+; GFX9-NEXT:    v_addc_co_u32_e64 v1, vcc, v1, v6, s[2:3]
+; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v4
 ; GFX9-NEXT:    s_mov_b32 s13, s12
 ; GFX9-NEXT:    s_addc_u32 s1, s7, s12
 ; GFX9-NEXT:    s_xor_b64 s[6:7], s[0:1], s[12:13]
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v3, s6, v1
-; GFX9-NEXT:    v_mul_hi_u32 v4, s6, v0
-; GFX9-NEXT:    v_mul_hi_u32 v5, s6, v1
+; GFX9-NEXT:    v_mul_lo_u32 v4, s6, v1
+; GFX9-NEXT:    v_mul_hi_u32 v5, s6, v0
+; GFX9-NEXT:    v_mul_hi_u32 v6, s6, v1
 ; GFX9-NEXT:    v_mul_hi_u32 v7, s7, v1
 ; GFX9-NEXT:    v_mul_lo_u32 v1, s7, v1
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v5, s7, v0
+; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v5, v4
+; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v6, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v6, s7, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v0, s7, v0
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v5, v3
-; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v4, v0, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v7, v2, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v6, v4
+; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v5, v0, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v7, v2, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
-; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v6, v3, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v3, v4, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v3, s10, v1
 ; GFX9-NEXT:    v_mul_hi_u32 v4, s10, v0
 ; GFX9-NEXT:    v_mul_lo_u32 v5, s11, v0
@@ -8866,10 +8862,8 @@
 ; GFX6-NEXT:    v_mov_b32_e32 v1, 0x4f800000
 ; GFX6-NEXT:    v_mac_f32_e32 v0, 0, v1
 ; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
-; GFX6-NEXT:    s_movk_i32 s6, 0xf001
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
+; GFX6-NEXT:    s_movk_i32 s10, 0xf001
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xd
 ; GFX6-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GFX6-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
@@ -8877,86 +8871,88 @@
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    s_ashr_i32 s0, s9, 31
-; GFX6-NEXT:    s_lshr_b32 s0, s0, 20
-; GFX6-NEXT:    v_mul_hi_u32 v2, s6, v0
-; GFX6-NEXT:    v_mul_lo_u32 v3, v1, s6
-; GFX6-NEXT:    s_add_u32 s2, s8, s0
-; GFX6-NEXT:    s_addc_u32 s3, s9, 0
-; GFX6-NEXT:    s_ashr_i32 s8, s11, 31
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
-; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s6
+; GFX6-NEXT:    s_ashr_i32 s2, s5, 31
+; GFX6-NEXT:    s_lshr_b32 s8, s2, 20
+; GFX6-NEXT:    v_mul_hi_u32 v3, s10, v0
+; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s10
+; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s10
+; GFX6-NEXT:    s_add_u32 s4, s4, s8
+; GFX6-NEXT:    s_addc_u32 s5, s5, 0
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
-; GFX6-NEXT:    v_mul_lo_u32 v4, v0, v2
+; GFX6-NEXT:    v_mul_lo_u32 v3, v0, v2
+; GFX6-NEXT:    v_mul_hi_u32 v5, v0, v4
 ; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v5, v0, v3
-; GFX6-NEXT:    v_mul_hi_u32 v7, v1, v2
-; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GFX6-NEXT:    s_ashr_i64 s[2:3], s[2:3], 12
-; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; GFX6-NEXT:    v_mul_hi_u32 v7, v1, v4
+; GFX6-NEXT:    v_mul_lo_u32 v4, v1, v4
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
 ; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v3
-; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
-; GFX6-NEXT:    s_mov_b32 s9, s8
-; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v3, vcc
+; GFX6-NEXT:    v_mul_hi_u32 v6, v1, v2
+; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v7, vcc
 ; GFX6-NEXT:    v_mov_b32_e32 v4, 0
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v7, v4, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v6, v4, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_mov_b32_e32 v6, 0
-; GFX6-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v2
+; GFX6-NEXT:    v_add_i32_e64 v0, s[2:3], v0, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v6, v5, vcc
-; GFX6-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
-; GFX6-NEXT:    v_mul_lo_u32 v5, v2, s6
-; GFX6-NEXT:    v_mul_hi_u32 v7, s6, v0
+; GFX6-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[2:3]
+; GFX6-NEXT:    v_mul_lo_u32 v5, v2, s10
+; GFX6-NEXT:    v_mul_hi_u32 v7, s10, v0
+; GFX6-NEXT:    s_ashr_i64 s[8:9], s[4:5], 12
 ; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
-; GFX6-NEXT:    v_mul_lo_u32 v7, v0, s6
+; GFX6-NEXT:    v_mul_lo_u32 v7, v0, s10
 ; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, v0, v5
-; GFX6-NEXT:    v_mul_lo_u32 v10, v0, v5
-; GFX6-NEXT:    v_mul_hi_u32 v12, v0, v5
-; GFX6-NEXT:    v_mul_hi_u32 v11, v0, v7
-; GFX6-NEXT:    v_mul_hi_u32 v9, v2, v7
+; GFX6-NEXT:    v_mul_lo_u32 v9, v0, v5
+; GFX6-NEXT:    v_mul_hi_u32 v11, v0, v5
+; GFX6-NEXT:    v_mul_hi_u32 v10, v0, v7
+; GFX6-NEXT:    v_mul_hi_u32 v12, v2, v7
 ; GFX6-NEXT:    v_mul_lo_u32 v7, v2, v7
 ; GFX6-NEXT:    v_mul_hi_u32 v8, v2, v5
-; GFX6-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; GFX6-NEXT:    v_addc_u32_e32 v11, vcc, 0, v12, vcc
+; GFX6-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
+; GFX6-NEXT:    v_addc_u32_e32 v10, vcc, 0, v11, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v2, v5
-; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
-; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v11, v9, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v8, v4, vcc
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v7, v2
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v6, v5, vcc
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v9, v7
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v10, v12, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v8, v4, vcc
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v6, v7, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
-; GFX6-NEXT:    v_addc_u32_e64 v1, vcc, v1, v5, s[0:1]
-; GFX6-NEXT:    s_add_u32 s0, s10, s8
-; GFX6-NEXT:    s_addc_u32 s1, s11, s8
+; GFX6-NEXT:    v_addc_u32_e64 v1, vcc, v1, v5, s[2:3]
+; GFX6-NEXT:    s_ashr_i32 s2, s7, 31
+; GFX6-NEXT:    s_add_u32 s4, s6, s2
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
-; GFX6-NEXT:    s_xor_b64 s[0:1], s[0:1], s[8:9]
+; GFX6-NEXT:    s_addc_u32 s5, s7, s2
+; GFX6-NEXT:    s_mov_b32 s3, s2
+; GFX6-NEXT:    s_xor_b64 s[10:11], s[4:5], s[2:3]
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v2, s0, v1
-; GFX6-NEXT:    v_mul_hi_u32 v3, s0, v0
-; GFX6-NEXT:    v_mul_hi_u32 v5, s0, v1
-; GFX6-NEXT:    v_mul_hi_u32 v7, s1, v1
-; GFX6-NEXT:    v_mul_lo_u32 v1, s1, v1
+; GFX6-NEXT:    v_mul_lo_u32 v2, s10, v1
+; GFX6-NEXT:    v_mul_hi_u32 v3, s10, v0
+; GFX6-NEXT:    v_mul_hi_u32 v5, s10, v1
+; GFX6-NEXT:    v_mul_hi_u32 v7, s11, v1
+; GFX6-NEXT:    v_mul_lo_u32 v1, s11, v1
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v5, s1, v0
-; GFX6-NEXT:    v_mul_hi_u32 v0, s1, v0
-; GFX6-NEXT:    s_movk_i32 s9, 0xfff
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    v_mul_lo_u32 v5, s11, v0
+; GFX6-NEXT:    v_mul_hi_u32 v0, s11, v0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT:    s_movk_i32 s0, 0xfff
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
 ; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v7, v4, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v6, v2, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s9
-; GFX6-NEXT:    v_mul_hi_u32 v3, s9, v0
-; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s9
+; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s0
+; GFX6-NEXT:    v_mul_hi_u32 v3, s0, v0
+; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s0
+; GFX6-NEXT:    s_mov_b32 s7, 0xf000
+; GFX6-NEXT:    s_mov_b32 s6, -1
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s0, v4
-; GFX6-NEXT:    v_mov_b32_e32 v3, s1
+; GFX6-NEXT:    v_mov_b32_e32 v3, s11
+; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s10, v4
 ; GFX6-NEXT:    v_subb_u32_e32 v2, vcc, v3, v2, vcc
-; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s9, v4
+; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s0, v4
 ; GFX6-NEXT:    v_subbrev_u32_e32 v5, vcc, 0, v2, vcc
 ; GFX6-NEXT:    s_movk_i32 s0, 0xffe
 ; GFX6-NEXT:    v_cmp_lt_u32_e32 vcc, s0, v3
@@ -8977,13 +8973,14 @@
 ; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
 ; GFX6-NEXT:    v_cndmask_b32_e32 v3, v8, v6, vcc
 ; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[0:1]
-; GFX6-NEXT:    v_xor_b32_e32 v0, s8, v0
-; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s8, v0
-; GFX6-NEXT:    v_xor_b32_e32 v1, s8, v1
-; GFX6-NEXT:    v_mov_b32_e32 v3, s8
+; GFX6-NEXT:    v_xor_b32_e32 v0, s2, v0
+; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s2, v0
+; GFX6-NEXT:    v_xor_b32_e32 v1, s2, v1
+; GFX6-NEXT:    v_mov_b32_e32 v3, s2
 ; GFX6-NEXT:    v_subb_u32_e32 v3, vcc, v1, v3, vcc
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s3
+; GFX6-NEXT:    v_mov_b32_e32 v0, s8
+; GFX6-NEXT:    v_mov_b32_e32 v1, s9
+; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -9004,27 +9001,26 @@
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    s_ashr_i32 s2, s5, 31
-; GFX9-NEXT:    s_lshr_b32 s2, s2, 20
-; GFX9-NEXT:    v_mul_hi_u32 v2, s8, v0
-; GFX9-NEXT:    v_mul_lo_u32 v3, v1, s8
+; GFX9-NEXT:    s_lshr_b32 s9, s2, 20
+; GFX9-NEXT:    v_mul_hi_u32 v3, s8, v0
+; GFX9-NEXT:    v_mul_lo_u32 v2, v1, s8
 ; GFX9-NEXT:    v_mul_lo_u32 v5, v0, s8
-; GFX9-NEXT:    s_add_u32 s4, s4, s2
+; GFX9-NEXT:    s_add_u32 s4, s4, s9
 ; GFX9-NEXT:    s_addc_u32 s5, s5, 0
-; GFX9-NEXT:    v_add_u32_e32 v2, v2, v3
+; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
 ; GFX9-NEXT:    v_sub_u32_e32 v2, v2, v0
 ; GFX9-NEXT:    v_mul_lo_u32 v3, v0, v2
 ; GFX9-NEXT:    v_mul_hi_u32 v6, v0, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v2
-; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
-; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
+; GFX9-NEXT:    v_mul_lo_u32 v8, v1, v5
+; GFX9-NEXT:    v_mul_hi_u32 v5, v1, v5
 ; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v6, v3
 ; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v7, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v5
-; GFX9-NEXT:    v_mul_hi_u32 v5, v1, v5
-; GFX9-NEXT:    s_ashr_i64 s[4:5], s[4:5], 12
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v7, v3
+; GFX9-NEXT:    v_mul_hi_u32 v7, v1, v2
+; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v8, v3
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v5, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v8, v4, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v7, v4, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
 ; GFX9-NEXT:    v_mov_b32_e32 v6, 0
 ; GFX9-NEXT:    v_add_co_u32_e64 v0, s[2:3], v0, v2
@@ -9032,25 +9028,25 @@
 ; GFX9-NEXT:    v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
 ; GFX9-NEXT:    v_mul_lo_u32 v5, v2, s8
 ; GFX9-NEXT:    v_mul_hi_u32 v7, s8, v0
-; GFX9-NEXT:    v_mul_lo_u32 v8, v0, s8
 ; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
-; GFX9-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x24
+; GFX9-NEXT:    s_ashr_i64 s[4:5], s[4:5], 12
 ; GFX9-NEXT:    v_add_u32_e32 v5, v7, v5
+; GFX9-NEXT:    v_mul_lo_u32 v7, v0, s8
 ; GFX9-NEXT:    v_sub_u32_e32 v5, v5, v0
-; GFX9-NEXT:    v_mul_lo_u32 v10, v0, v5
-; GFX9-NEXT:    v_mul_hi_u32 v11, v0, v8
-; GFX9-NEXT:    v_mul_hi_u32 v12, v0, v5
-; GFX9-NEXT:    v_mul_hi_u32 v9, v2, v8
-; GFX9-NEXT:    v_mul_lo_u32 v8, v2, v8
-; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
-; GFX9-NEXT:    v_mul_hi_u32 v7, v2, v5
-; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, 0, v12, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v9, v0, v5
+; GFX9-NEXT:    v_mul_hi_u32 v11, v0, v5
+; GFX9-NEXT:    v_mul_hi_u32 v10, v0, v7
+; GFX9-NEXT:    v_mul_hi_u32 v12, v2, v7
+; GFX9-NEXT:    v_mul_lo_u32 v7, v2, v7
+; GFX9-NEXT:    v_mul_hi_u32 v8, v2, v5
+; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v10, v9
+; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, 0, v11, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v2, v5
-; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v10, v8
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v11, v9, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v7, v4, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v8, v2
-; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v6, v5, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v9, v7
+; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v10, v12, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v8, v4, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v5, v2
+; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v6, v7, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e64 v1, vcc, v1, v5, s[2:3]
 ; GFX9-NEXT:    s_ashr_i32 s2, s7, 31
 ; GFX9-NEXT:    s_add_u32 s6, s6, s2
@@ -9069,6 +9065,7 @@
 ; GFX9-NEXT:    v_mul_lo_u32 v5, s7, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v0, s7, v0
 ; GFX9-NEXT:    s_movk_i32 s3, 0xfff
+; GFX9-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x24
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v5, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v7, v4, vcc
@@ -9136,243 +9133,243 @@
 ; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x11
 ; GFX6-NEXT:    s_mov_b32 s3, 0
 ; GFX6-NEXT:    s_movk_i32 s2, 0x1000
-; GFX6-NEXT:    s_mov_b32 s18, 0x4f800000
-; GFX6-NEXT:    s_mov_b32 s19, 0x5f7ffffc
+; GFX6-NEXT:    s_mov_b32 s20, 0x4f800000
+; GFX6-NEXT:    s_mov_b32 s21, 0x5f7ffffc
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    s_lshl_b64 s[12:13], s[2:3], s6
+; GFX6-NEXT:    s_lshl_b64 s[10:11], s[2:3], s6
 ; GFX6-NEXT:    s_lshl_b64 s[2:3], s[2:3], s4
 ; GFX6-NEXT:    s_ashr_i32 s16, s3, 31
 ; GFX6-NEXT:    s_add_u32 s2, s2, s16
 ; GFX6-NEXT:    s_mov_b32 s17, s16
 ; GFX6-NEXT:    s_addc_u32 s3, s3, s16
-; GFX6-NEXT:    s_xor_b64 s[14:15], s[2:3], s[16:17]
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s14
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s15
-; GFX6-NEXT:    s_mov_b32 s20, 0x2f800000
-; GFX6-NEXT:    s_mov_b32 s21, 0xcf800000
-; GFX6-NEXT:    s_sub_u32 s6, 0, s14
-; GFX6-NEXT:    v_mac_f32_e32 v0, s18, v1
+; GFX6-NEXT:    s_xor_b64 s[8:9], s[2:3], s[16:17]
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s8
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s9
+; GFX6-NEXT:    s_mov_b32 s22, 0x2f800000
+; GFX6-NEXT:    s_mov_b32 s23, 0xcf800000
+; GFX6-NEXT:    s_sub_u32 s4, 0, s8
+; GFX6-NEXT:    v_mac_f32_e32 v0, s20, v1
 ; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
-; GFX6-NEXT:    s_subb_u32 s7, 0, s15
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
-; GFX6-NEXT:    v_mul_f32_e32 v0, s19, v0
-; GFX6-NEXT:    v_mul_f32_e32 v1, s20, v0
+; GFX6-NEXT:    s_subb_u32 s5, 0, s9
+; GFX6-NEXT:    s_load_dwordx4 s[12:15], s[0:1], 0xd
+; GFX6-NEXT:    s_mov_b32 s7, 0xf000
+; GFX6-NEXT:    v_mul_f32_e32 v0, s21, v0
+; GFX6-NEXT:    v_mul_f32_e32 v1, s22, v0
 ; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
-; GFX6-NEXT:    v_mac_f32_e32 v0, s21, v1
+; GFX6-NEXT:    v_mac_f32_e32 v0, s23, v1
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT:    v_mul_hi_u32 v3, s6, v0
-; GFX6-NEXT:    v_mul_lo_u32 v2, s6, v1
-; GFX6-NEXT:    v_mul_lo_u32 v4, s7, v0
-; GFX6-NEXT:    v_mul_lo_u32 v5, s6, v0
+; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    v_mul_hi_u32 v3, s4, v0
+; GFX6-NEXT:    v_mul_lo_u32 v2, s4, v1
+; GFX6-NEXT:    v_mul_lo_u32 v5, s5, v0
+; GFX6-NEXT:    v_mul_lo_u32 v4, s4, v0
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
-; GFX6-NEXT:    v_mul_lo_u32 v3, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v4, v0, v5
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; GFX6-NEXT:    v_mul_hi_u32 v3, v0, v4
+; GFX6-NEXT:    v_mul_lo_u32 v5, v0, v2
 ; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v7, v1, v2
+; GFX6-NEXT:    v_mul_hi_u32 v7, v1, v4
+; GFX6-NEXT:    v_mul_lo_u32 v4, v1, v4
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
+; GFX6-NEXT:    v_mul_hi_u32 v6, v1, v2
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
 ; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v6, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v5
-; GFX6-NEXT:    v_mul_hi_u32 v5, v1, v5
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v4, v5, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v7, vcc
 ; GFX6-NEXT:    v_mov_b32_e32 v4, 0
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v7, v4, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v6, v4, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_mov_b32_e32 v6, 0
 ; GFX6-NEXT:    v_add_i32_e64 v0, s[2:3], v0, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v6, v5, vcc
 ; GFX6-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[2:3]
-; GFX6-NEXT:    v_mul_lo_u32 v5, s6, v2
-; GFX6-NEXT:    v_mul_hi_u32 v7, s6, v0
-; GFX6-NEXT:    v_mul_lo_u32 v8, s7, v0
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
+; GFX6-NEXT:    v_mul_lo_u32 v5, s4, v2
+; GFX6-NEXT:    v_mul_hi_u32 v7, s4, v0
+; GFX6-NEXT:    v_mul_lo_u32 v8, s5, v0
 ; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
-; GFX6-NEXT:    v_mul_lo_u32 v7, s6, v0
+; GFX6-NEXT:    v_mul_lo_u32 v7, s4, v0
 ; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; GFX6-NEXT:    v_mul_lo_u32 v10, v0, v5
-; GFX6-NEXT:    v_mul_hi_u32 v12, v0, v5
-; GFX6-NEXT:    v_mul_hi_u32 v11, v0, v7
-; GFX6-NEXT:    v_mul_hi_u32 v9, v2, v7
+; GFX6-NEXT:    v_mul_lo_u32 v9, v0, v5
+; GFX6-NEXT:    v_mul_hi_u32 v11, v0, v5
+; GFX6-NEXT:    v_mul_hi_u32 v10, v0, v7
+; GFX6-NEXT:    v_mul_hi_u32 v12, v2, v7
 ; GFX6-NEXT:    v_mul_lo_u32 v7, v2, v7
 ; GFX6-NEXT:    v_mul_hi_u32 v8, v2, v5
-; GFX6-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; GFX6-NEXT:    v_addc_u32_e32 v11, vcc, 0, v12, vcc
+; GFX6-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
+; GFX6-NEXT:    v_addc_u32_e32 v10, vcc, 0, v11, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v2, v5
-; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
-; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v11, v9, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v8, v4, vcc
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v7, v2
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v6, v5, vcc
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v9, v7
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v10, v12, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v8, v4, vcc
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v6, v7, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
 ; GFX6-NEXT:    v_addc_u32_e64 v1, vcc, v1, v5, s[2:3]
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    s_ashr_i32 s2, s9, 31
-; GFX6-NEXT:    s_add_u32 s0, s8, s2
+; GFX6-NEXT:    s_ashr_i32 s2, s13, 31
+; GFX6-NEXT:    s_add_u32 s4, s12, s2
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT:    s_addc_u32 s5, s13, s2
 ; GFX6-NEXT:    s_mov_b32 s3, s2
-; GFX6-NEXT:    s_addc_u32 s1, s9, s2
-; GFX6-NEXT:    s_xor_b64 s[8:9], s[0:1], s[2:3]
+; GFX6-NEXT:    s_xor_b64 s[12:13], s[4:5], s[2:3]
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v2, s8, v1
-; GFX6-NEXT:    v_mul_hi_u32 v3, s8, v0
-; GFX6-NEXT:    v_mul_hi_u32 v5, s8, v1
-; GFX6-NEXT:    v_mul_hi_u32 v7, s9, v1
-; GFX6-NEXT:    v_mul_lo_u32 v1, s9, v1
+; GFX6-NEXT:    v_mul_lo_u32 v2, s12, v1
+; GFX6-NEXT:    v_mul_hi_u32 v3, s12, v0
+; GFX6-NEXT:    v_mul_hi_u32 v5, s12, v1
+; GFX6-NEXT:    v_mul_hi_u32 v7, s13, v1
+; GFX6-NEXT:    v_mul_lo_u32 v1, s13, v1
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v5, s9, v0
-; GFX6-NEXT:    v_mul_hi_u32 v0, s9, v0
-; GFX6-NEXT:    s_xor_b64 s[2:3], s[2:3], s[16:17]
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    v_mul_lo_u32 v5, s13, v0
+; GFX6-NEXT:    v_mul_hi_u32 v0, s13, v0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT:    s_ashr_i32 s18, s11, 31
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
 ; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v7, v4, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v6, v2, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v2, s14, v1
-; GFX6-NEXT:    v_mul_hi_u32 v3, s14, v0
-; GFX6-NEXT:    v_mul_lo_u32 v5, s15, v0
-; GFX6-NEXT:    v_mov_b32_e32 v7, s15
+; GFX6-NEXT:    v_mul_lo_u32 v2, s8, v1
+; GFX6-NEXT:    v_mul_hi_u32 v3, s8, v0
+; GFX6-NEXT:    v_mul_lo_u32 v5, s9, v0
+; GFX6-NEXT:    v_mov_b32_e32 v7, s9
+; GFX6-NEXT:    s_xor_b64 s[16:17], s[2:3], s[16:17]
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_mul_lo_u32 v3, s14, v0
+; GFX6-NEXT:    v_mul_lo_u32 v3, s8, v0
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
-; GFX6-NEXT:    v_sub_i32_e32 v5, vcc, s9, v2
-; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s8, v3
+; GFX6-NEXT:    v_sub_i32_e32 v5, vcc, s13, v2
+; GFX6-NEXT:    s_mov_b32 s19, s18
+; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s12, v3
 ; GFX6-NEXT:    v_subb_u32_e64 v5, s[0:1], v5, v7, vcc
-; GFX6-NEXT:    v_subrev_i32_e64 v7, s[0:1], s14, v3
+; GFX6-NEXT:    v_subrev_i32_e64 v7, s[0:1], s8, v3
 ; GFX6-NEXT:    v_subbrev_u32_e64 v5, s[0:1], 0, v5, s[0:1]
-; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s15, v5
+; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s9, v5
 ; GFX6-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[0:1]
-; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s14, v7
+; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s8, v7
 ; GFX6-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[0:1]
-; GFX6-NEXT:    v_cmp_eq_u32_e64 s[0:1], s15, v5
+; GFX6-NEXT:    v_cmp_eq_u32_e64 s[0:1], s9, v5
 ; GFX6-NEXT:    v_cndmask_b32_e64 v5, v8, v7, s[0:1]
 ; GFX6-NEXT:    v_add_i32_e64 v7, s[0:1], 2, v0
 ; GFX6-NEXT:    v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1]
 ; GFX6-NEXT:    v_add_i32_e64 v9, s[0:1], 1, v0
 ; GFX6-NEXT:    v_addc_u32_e64 v10, s[0:1], 0, v1, s[0:1]
-; GFX6-NEXT:    s_ashr_i32 s8, s13, 31
+; GFX6-NEXT:    s_add_u32 s0, s10, s18
+; GFX6-NEXT:    s_addc_u32 s1, s11, s18
+; GFX6-NEXT:    s_xor_b64 s[10:11], s[0:1], s[18:19]
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v11, s10
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v12, s11
 ; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v5
-; GFX6-NEXT:    s_add_u32 s12, s12, s8
 ; GFX6-NEXT:    v_cndmask_b32_e64 v5, v10, v8, s[0:1]
-; GFX6-NEXT:    v_mov_b32_e32 v8, s9
-; GFX6-NEXT:    s_mov_b32 s9, s8
-; GFX6-NEXT:    s_addc_u32 s13, s13, s8
-; GFX6-NEXT:    s_xor_b64 s[12:13], s[12:13], s[8:9]
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v10, s12
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v11, s13
+; GFX6-NEXT:    v_mov_b32_e32 v8, s13
+; GFX6-NEXT:    v_mac_f32_e32 v11, s20, v12
 ; GFX6-NEXT:    v_subb_u32_e32 v2, vcc, v8, v2, vcc
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s15, v2
-; GFX6-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s14, v3
+; GFX6-NEXT:    v_rcp_f32_e32 v8, v11
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v2
+; GFX6-NEXT:    v_cndmask_b32_e64 v10, 0, -1, vcc
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v3
+; GFX6-NEXT:    v_mul_f32_e32 v8, s21, v8
+; GFX6-NEXT:    v_mul_f32_e32 v11, s22, v8
+; GFX6-NEXT:    v_trunc_f32_e32 v11, v11
+; GFX6-NEXT:    v_mac_f32_e32 v8, s23, v11
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v8, v8
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v11, v11
+; GFX6-NEXT:    s_sub_u32 s8, 0, s10
+; GFX6-NEXT:    s_subb_u32 s12, 0, s11
+; GFX6-NEXT:    v_mul_hi_u32 v12, s8, v8
+; GFX6-NEXT:    v_mul_lo_u32 v13, s8, v11
 ; GFX6-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
-; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s15, v2
-; GFX6-NEXT:    v_mac_f32_e32 v10, s18, v11
-; GFX6-NEXT:    v_cndmask_b32_e32 v2, v8, v3, vcc
-; GFX6-NEXT:    v_rcp_f32_e32 v3, v10
-; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
-; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
-; GFX6-NEXT:    s_sub_u32 s14, 0, s12
-; GFX6-NEXT:    v_mul_f32_e32 v3, s19, v3
-; GFX6-NEXT:    v_mul_f32_e32 v5, s20, v3
-; GFX6-NEXT:    v_trunc_f32_e32 v5, v5
-; GFX6-NEXT:    v_mac_f32_e32 v3, s21, v5
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v3
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v5, v5
+; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v2
+; GFX6-NEXT:    v_mul_lo_u32 v14, s12, v8
+; GFX6-NEXT:    v_cndmask_b32_e32 v2, v10, v3, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v10, s8, v8
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v12, v13
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v14
+; GFX6-NEXT:    v_mul_lo_u32 v13, v8, v3
+; GFX6-NEXT:    v_mul_hi_u32 v14, v8, v10
+; GFX6-NEXT:    v_mul_hi_u32 v12, v8, v3
+; GFX6-NEXT:    v_cmp_ne_u32_e64 s[2:3], 0, v2
 ; GFX6-NEXT:    v_cndmask_b32_e64 v2, v9, v7, s[0:1]
-; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX6-NEXT:    v_mul_hi_u32 v2, s14, v3
-; GFX6-NEXT:    v_mul_lo_u32 v7, s14, v5
-; GFX6-NEXT:    s_subb_u32 s15, 0, s13
-; GFX6-NEXT:    v_mul_lo_u32 v8, s15, v3
-; GFX6-NEXT:    v_xor_b32_e32 v0, s2, v0
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v7
-; GFX6-NEXT:    v_mul_lo_u32 v7, s14, v3
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v8
-; GFX6-NEXT:    v_mul_lo_u32 v8, v3, v2
-; GFX6-NEXT:    v_mul_hi_u32 v10, v3, v2
-; GFX6-NEXT:    v_mul_hi_u32 v9, v3, v7
-; GFX6-NEXT:    v_mul_hi_u32 v11, v5, v2
-; GFX6-NEXT:    v_mul_lo_u32 v2, v5, v2
-; GFX6-NEXT:    v_xor_b32_e32 v1, s3, v1
+; GFX6-NEXT:    v_mul_lo_u32 v9, v11, v10
+; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v5, s[2:3]
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v14, v13
+; GFX6-NEXT:    v_mul_hi_u32 v10, v11, v10
+; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, 0, v12, vcc
+; GFX6-NEXT:    v_mul_hi_u32 v12, v11, v3
+; GFX6-NEXT:    v_mul_lo_u32 v3, v11, v3
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v9, v5
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v7, v10, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v12, v4, vcc
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
+; GFX6-NEXT:    v_add_i32_e64 v3, s[0:1], v8, v3
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v6, v7, vcc
+; GFX6-NEXT:    v_addc_u32_e64 v7, vcc, v11, v5, s[0:1]
+; GFX6-NEXT:    v_mul_lo_u32 v8, s8, v7
+; GFX6-NEXT:    v_mul_hi_u32 v9, s8, v3
+; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[2:3]
+; GFX6-NEXT:    v_mul_lo_u32 v2, s12, v3
+; GFX6-NEXT:    s_ashr_i32 s2, s15, 31
 ; GFX6-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
-; GFX6-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v10, v5, v7
-; GFX6-NEXT:    v_mul_hi_u32 v7, v5, v7
-; GFX6-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
-; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v9, v7, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, v11, v4, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v9, s8, v3
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v8
+; GFX6-NEXT:    v_mul_lo_u32 v10, v3, v2
+; GFX6-NEXT:    v_mul_hi_u32 v13, v3, v2
+; GFX6-NEXT:    v_mul_hi_u32 v12, v3, v9
+; GFX6-NEXT:    v_mul_hi_u32 v14, v7, v9
+; GFX6-NEXT:    v_mul_lo_u32 v9, v7, v9
+; GFX6-NEXT:    v_mul_hi_u32 v8, v7, v2
+; GFX6-NEXT:    v_add_i32_e32 v10, vcc, v12, v10
+; GFX6-NEXT:    v_addc_u32_e32 v12, vcc, 0, v13, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v2, v7, v2
+; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v10, v9
+; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v12, v14, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, v8, v4, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v7, v2
-; GFX6-NEXT:    v_add_i32_e64 v2, s[0:1], v3, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v6, v8, vcc
-; GFX6-NEXT:    v_addc_u32_e64 v3, vcc, v5, v7, s[0:1]
-; GFX6-NEXT:    v_mul_lo_u32 v8, s14, v3
-; GFX6-NEXT:    v_mul_hi_u32 v9, s14, v2
-; GFX6-NEXT:    v_mul_lo_u32 v10, s15, v2
-; GFX6-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
-; GFX6-NEXT:    v_mul_lo_u32 v9, s14, v2
-; GFX6-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
-; GFX6-NEXT:    v_mul_lo_u32 v12, v2, v8
-; GFX6-NEXT:    v_mul_hi_u32 v14, v2, v8
-; GFX6-NEXT:    v_mul_hi_u32 v13, v2, v9
-; GFX6-NEXT:    v_mul_hi_u32 v11, v3, v9
-; GFX6-NEXT:    v_mul_lo_u32 v9, v3, v9
-; GFX6-NEXT:    v_mul_hi_u32 v10, v3, v8
-; GFX6-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
-; GFX6-NEXT:    v_addc_u32_e32 v13, vcc, 0, v14, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v3, v3, v8
-; GFX6-NEXT:    v_add_i32_e32 v9, vcc, v12, v9
-; GFX6-NEXT:    v_addc_u32_e32 v9, vcc, v13, v11, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, v10, v4, vcc
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v9, v3
-; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, v6, v8, vcc
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; GFX6-NEXT:    s_ashr_i32 s14, s11, 31
-; GFX6-NEXT:    v_addc_u32_e64 v5, vcc, v5, v8, s[0:1]
-; GFX6-NEXT:    s_add_u32 s0, s10, s14
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
-; GFX6-NEXT:    s_mov_b32 s15, s14
-; GFX6-NEXT:    s_addc_u32 s1, s11, s14
-; GFX6-NEXT:    s_xor_b64 s[10:11], s[0:1], s[14:15]
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v11, v5
+; GFX6-NEXT:    v_addc_u32_e64 v5, vcc, v5, v7, s[0:1]
+; GFX6-NEXT:    s_add_u32 s0, s14, s2
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT:    s_mov_b32 s3, s2
+; GFX6-NEXT:    s_addc_u32 s1, s15, s2
+; GFX6-NEXT:    s_xor_b64 s[8:9], s[0:1], s[2:3]
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v5, s10, v3
-; GFX6-NEXT:    v_mul_hi_u32 v7, s10, v2
-; GFX6-NEXT:    v_mul_hi_u32 v9, s10, v3
-; GFX6-NEXT:    v_mul_hi_u32 v10, s11, v3
-; GFX6-NEXT:    v_mul_lo_u32 v3, s11, v3
+; GFX6-NEXT:    v_mul_lo_u32 v5, s8, v3
+; GFX6-NEXT:    v_mul_hi_u32 v7, s8, v2
+; GFX6-NEXT:    v_mul_hi_u32 v8, s8, v3
+; GFX6-NEXT:    v_mul_hi_u32 v10, s9, v3
+; GFX6-NEXT:    v_mul_lo_u32 v3, s9, v3
 ; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
-; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, 0, v9, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v9, s11, v2
-; GFX6-NEXT:    v_mul_hi_u32 v2, s11, v2
-; GFX6-NEXT:    v_mov_b32_e32 v8, s3
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v9, v5
+; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v8, s9, v2
+; GFX6-NEXT:    v_mul_hi_u32 v2, s9, v2
+; GFX6-NEXT:    v_xor_b32_e32 v0, s16, v0
+; GFX6-NEXT:    v_xor_b32_e32 v1, s17, v1
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
 ; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v7, v2, vcc
 ; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v10, v4, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v6, v4, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v4, s12, v3
-; GFX6-NEXT:    v_mul_hi_u32 v5, s12, v2
-; GFX6-NEXT:    v_mul_lo_u32 v6, s13, v2
-; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s2, v0
-; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v1, v8, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v4, s10, v3
+; GFX6-NEXT:    v_mul_hi_u32 v5, s10, v2
+; GFX6-NEXT:    v_mul_lo_u32 v6, s11, v2
+; GFX6-NEXT:    v_mov_b32_e32 v9, s17
+; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s16, v0
+; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v1, v9, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GFX6-NEXT:    v_mul_lo_u32 v5, s12, v2
+; GFX6-NEXT:    v_mul_lo_u32 v5, s10, v2
 ; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
-; GFX6-NEXT:    v_sub_i32_e32 v6, vcc, s11, v4
-; GFX6-NEXT:    v_mov_b32_e32 v7, s13
-; GFX6-NEXT:    v_sub_i32_e32 v5, vcc, s10, v5
+; GFX6-NEXT:    v_sub_i32_e32 v6, vcc, s9, v4
+; GFX6-NEXT:    v_mov_b32_e32 v7, s11
+; GFX6-NEXT:    v_sub_i32_e32 v5, vcc, s8, v5
 ; GFX6-NEXT:    v_subb_u32_e64 v6, s[0:1], v6, v7, vcc
-; GFX6-NEXT:    v_subrev_i32_e64 v7, s[0:1], s12, v5
+; GFX6-NEXT:    v_subrev_i32_e64 v7, s[0:1], s10, v5
 ; GFX6-NEXT:    v_subbrev_u32_e64 v6, s[0:1], 0, v6, s[0:1]
-; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s13, v6
+; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s11, v6
 ; GFX6-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[0:1]
-; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s12, v7
+; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s10, v7
 ; GFX6-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[0:1]
-; GFX6-NEXT:    v_cmp_eq_u32_e64 s[0:1], s13, v6
+; GFX6-NEXT:    v_cmp_eq_u32_e64 s[0:1], s11, v6
 ; GFX6-NEXT:    v_cndmask_b32_e64 v6, v8, v7, s[0:1]
 ; GFX6-NEXT:    v_add_i32_e64 v7, s[0:1], 2, v2
 ; GFX6-NEXT:    v_addc_u32_e64 v8, s[0:1], 0, v3, s[0:1]
@@ -9380,24 +9377,25 @@
 ; GFX6-NEXT:    v_addc_u32_e64 v10, s[0:1], 0, v3, s[0:1]
 ; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
 ; GFX6-NEXT:    v_cndmask_b32_e64 v6, v10, v8, s[0:1]
-; GFX6-NEXT:    v_mov_b32_e32 v8, s11
+; GFX6-NEXT:    v_mov_b32_e32 v8, s9
 ; GFX6-NEXT:    v_subb_u32_e32 v4, vcc, v8, v4, vcc
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s13, v4
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s11, v4
 ; GFX6-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s12, v5
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v5
 ; GFX6-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
-; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s13, v4
+; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s11, v4
 ; GFX6-NEXT:    v_cndmask_b32_e32 v4, v8, v5, vcc
 ; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
 ; GFX6-NEXT:    v_cndmask_b32_e64 v4, v9, v7, s[0:1]
 ; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
-; GFX6-NEXT:    s_xor_b64 s[0:1], s[14:15], s[8:9]
+; GFX6-NEXT:    s_xor_b64 s[0:1], s[2:3], s[18:19]
 ; GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v6, vcc
 ; GFX6-NEXT:    v_xor_b32_e32 v2, s0, v2
 ; GFX6-NEXT:    v_xor_b32_e32 v3, s1, v3
 ; GFX6-NEXT:    v_mov_b32_e32 v4, s1
 ; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s0, v2
 ; GFX6-NEXT:    v_subb_u32_e32 v3, vcc, v3, v4, vcc
+; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -9409,22 +9407,22 @@
 ; GFX9-NEXT:    s_mov_b32 s18, 0x4f800000
 ; GFX9-NEXT:    s_mov_b32 s19, 0x5f7ffffc
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    s_lshl_b64 s[8:9], s[2:3], s6
+; GFX9-NEXT:    s_lshl_b64 s[10:11], s[2:3], s6
 ; GFX9-NEXT:    s_lshl_b64 s[2:3], s[2:3], s4
 ; GFX9-NEXT:    s_ashr_i32 s12, s3, 31
 ; GFX9-NEXT:    s_add_u32 s2, s2, s12
 ; GFX9-NEXT:    s_mov_b32 s13, s12
 ; GFX9-NEXT:    s_addc_u32 s3, s3, s12
-; GFX9-NEXT:    s_xor_b64 s[10:11], s[2:3], s[12:13]
-; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s10
-; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s11
+; GFX9-NEXT:    s_xor_b64 s[8:9], s[2:3], s[12:13]
+; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s8
+; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s9
 ; GFX9-NEXT:    s_mov_b32 s20, 0x2f800000
 ; GFX9-NEXT:    s_mov_b32 s21, 0xcf800000
-; GFX9-NEXT:    s_sub_u32 s14, 0, s10
+; GFX9-NEXT:    s_sub_u32 s14, 0, s8
 ; GFX9-NEXT:    v_mac_f32_e32 v0, s18, v1
 ; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
-; GFX9-NEXT:    s_subb_u32 s4, 0, s11
-; GFX9-NEXT:    v_mov_b32_e32 v6, 0
+; GFX9-NEXT:    s_subb_u32 s4, 0, s9
+; GFX9-NEXT:    v_mov_b32_e32 v7, 0
 ; GFX9-NEXT:    v_mul_f32_e32 v0, s19, v0
 ; GFX9-NEXT:    v_mul_f32_e32 v1, s20, v0
 ; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
@@ -9439,45 +9437,45 @@
 ; GFX9-NEXT:    v_add_u32_e32 v2, v2, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v3, v0, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v5, v0, v2
-; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v2
-; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
-; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
-; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v4
+; GFX9-NEXT:    v_mul_hi_u32 v6, v0, v2
+; GFX9-NEXT:    v_mul_lo_u32 v8, v1, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v7, v3
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
+; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v6, vcc
+; GFX9-NEXT:    v_mul_hi_u32 v6, v1, v2
+; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v8, v3
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v6, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v6, v7, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
 ; GFX9-NEXT:    v_mov_b32_e32 v5, 0
 ; GFX9-NEXT:    v_add_co_u32_e64 v0, s[2:3], v0, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
 ; GFX9-NEXT:    v_mul_lo_u32 v4, s14, v2
-; GFX9-NEXT:    v_mul_hi_u32 v7, s14, v0
+; GFX9-NEXT:    v_mul_hi_u32 v6, s14, v0
 ; GFX9-NEXT:    v_mul_lo_u32 v8, s4, v0
-; GFX9-NEXT:    v_mul_lo_u32 v9, s14, v0
 ; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
-; GFX9-NEXT:    v_add_u32_e32 v4, v7, v4
+; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
+; GFX9-NEXT:    v_add_u32_e32 v4, v6, v4
+; GFX9-NEXT:    v_mul_lo_u32 v6, s14, v0
 ; GFX9-NEXT:    v_add_u32_e32 v4, v4, v8
-; GFX9-NEXT:    v_mul_lo_u32 v10, v0, v4
-; GFX9-NEXT:    v_mul_hi_u32 v11, v0, v9
-; GFX9-NEXT:    v_mul_hi_u32 v12, v0, v4
-; GFX9-NEXT:    v_mul_hi_u32 v8, v2, v9
-; GFX9-NEXT:    v_mul_lo_u32 v9, v2, v9
-; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
-; GFX9-NEXT:    v_mul_hi_u32 v7, v2, v4
-; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, 0, v12, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v2, v2, v4
+; GFX9-NEXT:    v_mul_lo_u32 v9, v0, v4
+; GFX9-NEXT:    v_mul_hi_u32 v11, v0, v4
+; GFX9-NEXT:    v_mul_hi_u32 v10, v0, v6
+; GFX9-NEXT:    v_mul_hi_u32 v12, v2, v6
+; GFX9-NEXT:    v_mul_lo_u32 v6, v2, v6
+; GFX9-NEXT:    v_mul_hi_u32 v8, v2, v4
 ; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v10, v9
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v11, v8, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v7, v6, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v8, v2
+; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, 0, v11, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v2, v2, v4
+; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v9, v6
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v10, v12, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v8, v7, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v4, v2
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v5, v6, vcc
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    s_ashr_i32 s14, s5, 31
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v5, v4, vcc
-; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
 ; GFX9-NEXT:    v_addc_co_u32_e64 v1, vcc, v1, v4, s[2:3]
 ; GFX9-NEXT:    s_add_u32 s2, s4, s14
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
@@ -9488,7 +9486,7 @@
 ; GFX9-NEXT:    v_mul_lo_u32 v2, s16, v1
 ; GFX9-NEXT:    v_mul_hi_u32 v3, s16, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v4, s16, v1
-; GFX9-NEXT:    v_mul_hi_u32 v7, s17, v1
+; GFX9-NEXT:    v_mul_hi_u32 v6, s17, v1
 ; GFX9-NEXT:    v_mul_lo_u32 v1, s17, v1
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
@@ -9498,30 +9496,30 @@
 ; GFX9-NEXT:    s_xor_b64 s[12:13], s[14:15], s[12:13]
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v4, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v7, v6, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v6, v7, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v5, v2, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v2, s10, v1
-; GFX9-NEXT:    v_mul_hi_u32 v3, s10, v0
-; GFX9-NEXT:    v_mul_lo_u32 v4, s11, v0
-; GFX9-NEXT:    v_mov_b32_e32 v7, s11
-; GFX9-NEXT:    s_ashr_i32 s14, s9, 31
+; GFX9-NEXT:    v_mul_lo_u32 v2, s8, v1
+; GFX9-NEXT:    v_mul_hi_u32 v3, s8, v0
+; GFX9-NEXT:    v_mul_lo_u32 v4, s9, v0
+; GFX9-NEXT:    v_mov_b32_e32 v6, s9
+; GFX9-NEXT:    s_ashr_i32 s14, s11, 31
 ; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
-; GFX9-NEXT:    v_mul_lo_u32 v3, s10, v0
+; GFX9-NEXT:    v_mul_lo_u32 v3, s8, v0
 ; GFX9-NEXT:    v_add_u32_e32 v2, v2, v4
 ; GFX9-NEXT:    v_sub_u32_e32 v4, s17, v2
 ; GFX9-NEXT:    s_mov_b32 s15, s14
 ; GFX9-NEXT:    v_sub_co_u32_e64 v3, s[0:1], s16, v3
-; GFX9-NEXT:    v_subb_co_u32_e64 v4, vcc, v4, v7, s[0:1]
-; GFX9-NEXT:    v_subrev_co_u32_e32 v7, vcc, s10, v3
+; GFX9-NEXT:    v_subb_co_u32_e64 v4, vcc, v4, v6, s[0:1]
+; GFX9-NEXT:    v_subrev_co_u32_e32 v6, vcc, s8, v3
 ; GFX9-NEXT:    v_subbrev_co_u32_e32 v4, vcc, 0, v4, vcc
-; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s11, v4
+; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v4
 ; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
-; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s10, v7
-; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
-; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s11, v4
-; GFX9-NEXT:    v_cndmask_b32_e32 v4, v8, v7, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, 2, v0
+; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s8, v6
+; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
+; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v4
+; GFX9-NEXT:    v_cndmask_b32_e32 v4, v8, v6, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, 2, v0
 ; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v1, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, 1, v0
 ; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, 0, v1, vcc
@@ -9529,145 +9527,145 @@
 ; GFX9-NEXT:    v_cndmask_b32_e64 v4, v10, v8, s[2:3]
 ; GFX9-NEXT:    v_mov_b32_e32 v8, s17
 ; GFX9-NEXT:    v_subb_co_u32_e64 v2, vcc, v8, v2, s[0:1]
-; GFX9-NEXT:    s_add_u32 s0, s8, s14
-; GFX9-NEXT:    s_addc_u32 s1, s9, s14
-; GFX9-NEXT:    s_xor_b64 s[8:9], s[0:1], s[14:15]
-; GFX9-NEXT:    v_cvt_f32_u32_e32 v10, s8
-; GFX9-NEXT:    v_cvt_f32_u32_e32 v11, s9
-; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s11, v2
+; GFX9-NEXT:    s_add_u32 s0, s10, s14
+; GFX9-NEXT:    s_addc_u32 s1, s11, s14
+; GFX9-NEXT:    s_xor_b64 s[10:11], s[0:1], s[14:15]
+; GFX9-NEXT:    v_cvt_f32_u32_e32 v8, s10
+; GFX9-NEXT:    v_cvt_f32_u32_e32 v10, s11
+; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v2
+; GFX9-NEXT:    v_cndmask_b32_e64 v11, 0, -1, vcc
+; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s8, v3
+; GFX9-NEXT:    v_mac_f32_e32 v8, s18, v10
+; GFX9-NEXT:    v_rcp_f32_e32 v3, v8
 ; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
-; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s10, v3
-; GFX9-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
-; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s11, v2
-; GFX9-NEXT:    v_mac_f32_e32 v10, s18, v11
-; GFX9-NEXT:    v_cndmask_b32_e32 v2, v8, v3, vcc
-; GFX9-NEXT:    v_rcp_f32_e32 v3, v10
-; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
-; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
-; GFX9-NEXT:    v_cndmask_b32_e64 v2, v9, v7, s[2:3]
-; GFX9-NEXT:    v_mul_f32_e32 v3, s19, v3
-; GFX9-NEXT:    v_mul_f32_e32 v4, s20, v3
-; GFX9-NEXT:    v_trunc_f32_e32 v4, v4
-; GFX9-NEXT:    v_mac_f32_e32 v3, s21, v4
+; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v2
+; GFX9-NEXT:    s_sub_u32 s8, 0, s10
+; GFX9-NEXT:    v_mul_f32_e32 v2, s19, v3
+; GFX9-NEXT:    v_mul_f32_e32 v3, s20, v2
+; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
+; GFX9-NEXT:    v_mac_f32_e32 v2, s21, v3
+; GFX9-NEXT:    v_cvt_u32_f32_e32 v2, v2
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
-; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v4
-; GFX9-NEXT:    s_sub_u32 s2, 0, s8
-; GFX9-NEXT:    s_subb_u32 s3, 0, s9
-; GFX9-NEXT:    v_mul_hi_u32 v7, s2, v3
-; GFX9-NEXT:    v_mul_lo_u32 v8, s2, v4
-; GFX9-NEXT:    v_mul_lo_u32 v9, s3, v3
-; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v2, s2, v3
-; GFX9-NEXT:    v_add_u32_e32 v7, v7, v8
-; GFX9-NEXT:    v_add_u32_e32 v7, v7, v9
-; GFX9-NEXT:    v_mul_lo_u32 v8, v3, v7
-; GFX9-NEXT:    v_mul_hi_u32 v9, v3, v2
-; GFX9-NEXT:    v_mul_hi_u32 v10, v3, v7
-; GFX9-NEXT:    v_mul_hi_u32 v11, v4, v7
-; GFX9-NEXT:    v_mul_lo_u32 v7, v4, v7
-; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v9, v8
-; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, 0, v10, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v10, v4, v2
-; GFX9-NEXT:    v_mul_hi_u32 v2, v4, v2
-; GFX9-NEXT:    s_ashr_i32 s10, s7, 31
-; GFX9-NEXT:    s_mov_b32 s11, s10
-; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v10, v8
-; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v9, v2, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v11, v6, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v7
-; GFX9-NEXT:    v_add_co_u32_e64 v2, s[0:1], v3, v2
-; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v5, v8, vcc
-; GFX9-NEXT:    v_addc_co_u32_e64 v3, vcc, v4, v7, s[0:1]
-; GFX9-NEXT:    v_mul_lo_u32 v8, s2, v3
-; GFX9-NEXT:    v_mul_hi_u32 v9, s2, v2
-; GFX9-NEXT:    v_mul_lo_u32 v10, s3, v2
-; GFX9-NEXT:    v_mul_lo_u32 v11, s2, v2
-; GFX9-NEXT:    v_add_u32_e32 v4, v4, v7
-; GFX9-NEXT:    v_add_u32_e32 v8, v9, v8
-; GFX9-NEXT:    v_add_u32_e32 v8, v8, v10
-; GFX9-NEXT:    v_mul_lo_u32 v12, v2, v8
-; GFX9-NEXT:    v_mul_hi_u32 v13, v2, v11
-; GFX9-NEXT:    v_mul_hi_u32 v14, v2, v8
-; GFX9-NEXT:    v_mul_hi_u32 v10, v3, v11
-; GFX9-NEXT:    v_mul_lo_u32 v11, v3, v11
-; GFX9-NEXT:    v_add_co_u32_e32 v12, vcc, v13, v12
-; GFX9-NEXT:    v_mul_hi_u32 v9, v3, v8
-; GFX9-NEXT:    v_addc_co_u32_e32 v13, vcc, 0, v14, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v3, v3, v8
-; GFX9-NEXT:    v_add_co_u32_e32 v11, vcc, v12, v11
-; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v13, v10, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v9, v6, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v10, v3
+; GFX9-NEXT:    s_subb_u32 s9, 0, s11
+; GFX9-NEXT:    v_cndmask_b32_e32 v8, v11, v8, vcc
+; GFX9-NEXT:    v_mul_hi_u32 v10, s8, v2
+; GFX9-NEXT:    v_mul_lo_u32 v12, s8, v3
+; GFX9-NEXT:    v_mul_lo_u32 v13, s9, v2
+; GFX9-NEXT:    v_mul_lo_u32 v11, s8, v2
+; GFX9-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v8
+; GFX9-NEXT:    v_add_u32_e32 v10, v10, v12
+; GFX9-NEXT:    v_add_u32_e32 v10, v10, v13
+; GFX9-NEXT:    v_mul_lo_u32 v13, v2, v10
+; GFX9-NEXT:    v_mul_hi_u32 v14, v2, v11
+; GFX9-NEXT:    v_mul_hi_u32 v12, v2, v10
+; GFX9-NEXT:    v_cndmask_b32_e64 v1, v1, v4, s[0:1]
+; GFX9-NEXT:    v_cndmask_b32_e64 v4, v9, v6, s[2:3]
+; GFX9-NEXT:    v_mul_lo_u32 v9, v3, v11
+; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v14, v13
+; GFX9-NEXT:    v_mul_hi_u32 v11, v3, v11
+; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v12, vcc
+; GFX9-NEXT:    v_mul_hi_u32 v12, v3, v10
+; GFX9-NEXT:    v_mul_lo_u32 v10, v3, v10
+; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v9, v6
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v8, v11, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v12, v7, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v10
+; GFX9-NEXT:    v_add_co_u32_e64 v2, s[2:3], v2, v6
 ; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v5, v8, vcc
-; GFX9-NEXT:    v_addc_co_u32_e64 v4, vcc, v4, v8, s[0:1]
-; GFX9-NEXT:    s_add_u32 s0, s6, s10
-; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v3
-; GFX9-NEXT:    s_addc_u32 s1, s7, s10
-; GFX9-NEXT:    s_xor_b64 s[6:7], s[0:1], s[10:11]
-; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
+; GFX9-NEXT:    v_addc_co_u32_e64 v6, vcc, v3, v8, s[2:3]
+; GFX9-NEXT:    v_mul_lo_u32 v9, s8, v6
+; GFX9-NEXT:    v_mul_hi_u32 v10, s8, v2
+; GFX9-NEXT:    v_cndmask_b32_e64 v0, v0, v4, s[0:1]
+; GFX9-NEXT:    v_mul_lo_u32 v4, s9, v2
+; GFX9-NEXT:    v_add_u32_e32 v3, v3, v8
+; GFX9-NEXT:    v_add_u32_e32 v9, v10, v9
+; GFX9-NEXT:    v_mul_lo_u32 v10, s8, v2
+; GFX9-NEXT:    v_add_u32_e32 v4, v9, v4
+; GFX9-NEXT:    v_mul_lo_u32 v11, v2, v4
+; GFX9-NEXT:    v_mul_hi_u32 v13, v2, v4
+; GFX9-NEXT:    v_mul_hi_u32 v12, v2, v10
+; GFX9-NEXT:    v_mul_hi_u32 v14, v6, v10
+; GFX9-NEXT:    v_mul_lo_u32 v10, v6, v10
+; GFX9-NEXT:    v_mul_hi_u32 v9, v6, v4
+; GFX9-NEXT:    v_add_co_u32_e32 v11, vcc, v12, v11
+; GFX9-NEXT:    v_addc_co_u32_e32 v12, vcc, 0, v13, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v4, v6, v4
+; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v11, v10
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v12, v14, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v9, v7, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v6, v4
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v5, v9, vcc
+; GFX9-NEXT:    s_ashr_i32 s8, s7, 31
+; GFX9-NEXT:    s_add_u32 s0, s6, s8
+; GFX9-NEXT:    v_addc_co_u32_e64 v3, vcc, v3, v6, s[2:3]
+; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v4
+; GFX9-NEXT:    s_mov_b32 s9, s8
+; GFX9-NEXT:    s_addc_u32 s1, s7, s8
+; GFX9-NEXT:    s_xor_b64 s[6:7], s[0:1], s[8:9]
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v4, s6, v3
-; GFX9-NEXT:    v_mul_hi_u32 v7, s6, v2
-; GFX9-NEXT:    v_mul_hi_u32 v9, s6, v3
+; GFX9-NEXT:    v_mul_hi_u32 v6, s6, v2
+; GFX9-NEXT:    v_mul_hi_u32 v8, s6, v3
 ; GFX9-NEXT:    v_mul_hi_u32 v10, s7, v3
 ; GFX9-NEXT:    v_mul_lo_u32 v3, s7, v3
-; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v7, v4
-; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v9, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v9, s7, v2
+; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v6, v4
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v8, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v8, s7, v2
 ; GFX9-NEXT:    v_mul_hi_u32 v2, s7, v2
 ; GFX9-NEXT:    v_xor_b32_e32 v0, s12, v0
 ; GFX9-NEXT:    v_xor_b32_e32 v1, s13, v1
-; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v9, v4
-; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v7, v2, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v10, v6, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v8, v4
+; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v6, v2, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v10, v7, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v3
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v4, s8, v3
-; GFX9-NEXT:    v_mul_hi_u32 v5, s8, v2
-; GFX9-NEXT:    v_mul_lo_u32 v7, s9, v2
-; GFX9-NEXT:    v_mov_b32_e32 v8, s13
+; GFX9-NEXT:    v_mul_lo_u32 v4, s10, v3
+; GFX9-NEXT:    v_mul_hi_u32 v5, s10, v2
+; GFX9-NEXT:    v_mul_lo_u32 v6, s11, v2
+; GFX9-NEXT:    v_mov_b32_e32 v9, s13
 ; GFX9-NEXT:    v_subrev_co_u32_e32 v0, vcc, s12, v0
 ; GFX9-NEXT:    v_add_u32_e32 v4, v5, v4
-; GFX9-NEXT:    v_mul_lo_u32 v5, s8, v2
-; GFX9-NEXT:    v_add_u32_e32 v4, v4, v7
-; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v8, vcc
-; GFX9-NEXT:    v_sub_u32_e32 v7, s7, v4
-; GFX9-NEXT:    v_mov_b32_e32 v8, s9
+; GFX9-NEXT:    v_mul_lo_u32 v5, s10, v2
+; GFX9-NEXT:    v_add_u32_e32 v4, v4, v6
+; GFX9-NEXT:    v_sub_u32_e32 v6, s7, v4
+; GFX9-NEXT:    v_mov_b32_e32 v8, s11
 ; GFX9-NEXT:    v_sub_co_u32_e64 v5, s[0:1], s6, v5
-; GFX9-NEXT:    v_subb_co_u32_e64 v7, vcc, v7, v8, s[0:1]
-; GFX9-NEXT:    v_subrev_co_u32_e32 v8, vcc, s8, v5
-; GFX9-NEXT:    v_subbrev_co_u32_e32 v7, vcc, 0, v7, vcc
-; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v7
+; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v9, vcc
+; GFX9-NEXT:    v_subb_co_u32_e64 v6, vcc, v6, v8, s[0:1]
+; GFX9-NEXT:    v_subrev_co_u32_e32 v8, vcc, s10, v5
+; GFX9-NEXT:    v_subbrev_co_u32_e32 v6, vcc, 0, v6, vcc
+; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s11, v6
 ; GFX9-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
-; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s8, v8
+; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s10, v8
 ; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
-; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v7
-; GFX9-NEXT:    v_cndmask_b32_e32 v7, v9, v8, vcc
+; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s11, v6
+; GFX9-NEXT:    v_cndmask_b32_e32 v6, v9, v8, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, 2, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, 0, v3, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, 1, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, 0, v3, vcc
-; GFX9-NEXT:    v_cmp_ne_u32_e64 s[2:3], 0, v7
-; GFX9-NEXT:    v_cndmask_b32_e64 v7, v11, v9, s[2:3]
+; GFX9-NEXT:    v_cmp_ne_u32_e64 s[2:3], 0, v6
+; GFX9-NEXT:    v_cndmask_b32_e64 v6, v11, v9, s[2:3]
 ; GFX9-NEXT:    v_mov_b32_e32 v9, s7
 ; GFX9-NEXT:    v_subb_co_u32_e64 v4, vcc, v9, v4, s[0:1]
-; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v4
+; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s11, v4
 ; GFX9-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
-; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s8, v5
+; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s10, v5
 ; GFX9-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
-; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v4
+; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s11, v4
 ; GFX9-NEXT:    v_cndmask_b32_e32 v4, v9, v5, vcc
 ; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
 ; GFX9-NEXT:    v_cndmask_b32_e64 v4, v10, v8, s[2:3]
 ; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
-; GFX9-NEXT:    s_xor_b64 s[0:1], s[10:11], s[14:15]
-; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v7, vcc
+; GFX9-NEXT:    s_xor_b64 s[0:1], s[8:9], s[14:15]
+; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v6, vcc
 ; GFX9-NEXT:    v_xor_b32_e32 v2, s0, v2
 ; GFX9-NEXT:    v_xor_b32_e32 v3, s1, v3
 ; GFX9-NEXT:    v_mov_b32_e32 v4, s1
 ; GFX9-NEXT:    v_subrev_co_u32_e32 v2, vcc, s0, v2
 ; GFX9-NEXT:    v_subb_co_u32_e32 v3, vcc, v3, v4, vcc
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    global_store_dwordx4 v6, v[0:3], s[4:5]
+; GFX9-NEXT:    global_store_dwordx4 v7, v[0:3], s[4:5]
 ; GFX9-NEXT:    s_endpgm
   %shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y
   %r = sdiv <2 x i64> %x, %shl.y
@@ -9686,88 +9684,86 @@
 ; GFX6-NEXT:    v_mov_b32_e32 v0, 0x4f800000
 ; GFX6-NEXT:    v_madak_f32 v0, 0, v0, 0x4996c7d8
 ; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
-; GFX6-NEXT:    s_mov_b32 s2, 0xffed2705
-; GFX6-NEXT:    v_mov_b32_e32 v8, 0
-; GFX6-NEXT:    v_mov_b32_e32 v7, 0
+; GFX6-NEXT:    s_mov_b32 s8, 0xffed2705
+; GFX6-NEXT:    v_mov_b32_e32 v6, 0
+; GFX6-NEXT:    v_mov_b32_e32 v5, 0
 ; GFX6-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GFX6-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX6-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    v_mul_hi_u32 v3, s2, v0
-; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s2
-; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s2
-; GFX6-NEXT:    s_mov_b32 s6, -1
-; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    s_mov_b32 s4, s8
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GFX6-NEXT:    v_mul_hi_u32 v3, s8, v0
+; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s8
+; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s8
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
-; GFX6-NEXT:    v_mul_lo_u32 v5, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v4
-; GFX6-NEXT:    v_mul_hi_u32 v3, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v9, v1, v2
+; GFX6-NEXT:    v_mul_hi_u32 v3, v0, v4
+; GFX6-NEXT:    v_mul_lo_u32 v7, v0, v2
+; GFX6-NEXT:    v_mul_hi_u32 v8, v0, v2
+; GFX6-NEXT:    v_mul_hi_u32 v9, v1, v4
+; GFX6-NEXT:    v_mul_lo_u32 v4, v1, v4
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
+; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v6, v8, vcc
+; GFX6-NEXT:    v_mul_hi_u32 v8, v1, v2
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v4
-; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v8, v3, vcc
-; GFX6-NEXT:    s_mov_b32 s5, s9
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v3, v4, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v9, v7, vcc
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v7, v9, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v5, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v2
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v8, v4, vcc
-; GFX6-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
-; GFX6-NEXT:    v_mul_lo_u32 v4, v2, s2
-; GFX6-NEXT:    v_mul_hi_u32 v5, s2, v0
-; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GFX6-NEXT:    v_mul_lo_u32 v5, v0, s2
+; GFX6-NEXT:    v_add_i32_e64 v0, s[2:3], v0, v2
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v6, v4, vcc
+; GFX6-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[2:3]
+; GFX6-NEXT:    v_mul_lo_u32 v4, v2, s8
+; GFX6-NEXT:    v_mul_hi_u32 v7, s8, v0
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
+; GFX6-NEXT:    v_mul_lo_u32 v7, v0, s8
 ; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, v0, v4
-; GFX6-NEXT:    v_mul_lo_u32 v10, v0, v4
-; GFX6-NEXT:    v_mul_hi_u32 v12, v0, v4
-; GFX6-NEXT:    v_mul_hi_u32 v11, v0, v5
-; GFX6-NEXT:    v_mul_hi_u32 v9, v2, v5
-; GFX6-NEXT:    v_mul_lo_u32 v5, v2, v5
-; GFX6-NEXT:    v_mul_hi_u32 v6, v2, v4
-; GFX6-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; GFX6-NEXT:    v_addc_u32_e32 v11, vcc, v8, v12, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v9, v0, v4
+; GFX6-NEXT:    v_mul_hi_u32 v11, v0, v4
+; GFX6-NEXT:    v_mul_hi_u32 v10, v0, v7
+; GFX6-NEXT:    v_mul_hi_u32 v12, v2, v7
+; GFX6-NEXT:    v_mul_lo_u32 v7, v2, v7
+; GFX6-NEXT:    v_mul_hi_u32 v8, v2, v4
+; GFX6-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
+; GFX6-NEXT:    v_addc_u32_e32 v10, vcc, v6, v11, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v2, v4
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v10, v5
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v11, v9, vcc
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v9, v7
+; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v10, v12, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v8, v5, vcc
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v6, v7, vcc
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v4, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
-; GFX6-NEXT:    s_ashr_i32 s2, s11, 31
-; GFX6-NEXT:    v_addc_u32_e64 v1, vcc, v1, v4, s[0:1]
-; GFX6-NEXT:    s_add_u32 s0, s10, s2
+; GFX6-NEXT:    v_addc_u32_e64 v1, vcc, v1, v4, s[2:3]
+; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:    s_ashr_i32 s2, s7, 31
+; GFX6-NEXT:    s_add_u32 s0, s6, s2
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT:    s_addc_u32 s1, s7, s2
 ; GFX6-NEXT:    s_mov_b32 s3, s2
-; GFX6-NEXT:    s_addc_u32 s1, s11, s2
 ; GFX6-NEXT:    s_xor_b64 s[0:1], s[0:1], s[2:3]
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, s0, v1
 ; GFX6-NEXT:    v_mul_hi_u32 v3, s0, v0
 ; GFX6-NEXT:    v_mul_hi_u32 v4, s0, v1
-; GFX6-NEXT:    v_mul_hi_u32 v5, s1, v1
+; GFX6-NEXT:    v_mul_hi_u32 v7, s1, v1
 ; GFX6-NEXT:    v_mul_lo_u32 v1, s1, v1
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v8, v4, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v6, v4, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v4, s1, v0
 ; GFX6-NEXT:    v_mul_hi_u32 v0, s1, v0
 ; GFX6-NEXT:    s_mov_b32 s3, 0x12d8fb
+; GFX6-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v5, v7, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v7, v5, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
-; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v8, v2, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v6, v2, vcc
 ; GFX6-NEXT:    v_mul_hi_u32 v2, s3, v0
 ; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s3
 ; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s3
+; GFX6-NEXT:    s_mov_b32 s6, -1
 ; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
 ; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s0, v0
 ; GFX6-NEXT:    v_mov_b32_e32 v2, s1
@@ -9805,7 +9801,7 @@
 ; GFX9-NEXT:    v_madak_f32 v0, 0, v0, 0x4996c7d8
 ; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
 ; GFX9-NEXT:    s_mov_b32 s8, 0xffed2705
-; GFX9-NEXT:    v_mov_b32_e32 v7, 0
+; GFX9-NEXT:    v_mov_b32_e32 v6, 0
 ; GFX9-NEXT:    v_mov_b32_e32 v5, 0
 ; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
@@ -9820,41 +9816,41 @@
 ; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
 ; GFX9-NEXT:    v_sub_u32_e32 v2, v2, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v3, v0, v4
-; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v2
+; GFX9-NEXT:    v_mul_lo_u32 v7, v0, v2
 ; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v2
-; GFX9-NEXT:    v_mul_hi_u32 v9, v1, v2
+; GFX9-NEXT:    v_mul_hi_u32 v9, v1, v4
+; GFX9-NEXT:    v_mul_lo_u32 v4, v1, v4
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v7
+; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v6, v8, vcc
+; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v6
-; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v7, v8, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v8, v1, v4
-; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v8, v3
-; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v4, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v9, v5, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v7, v9, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v5, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
 ; GFX9-NEXT:    v_add_co_u32_e64 v0, s[2:3], v0, v2
-; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v7, v4, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v4, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
 ; GFX9-NEXT:    v_mul_lo_u32 v4, v2, s8
-; GFX9-NEXT:    v_mul_hi_u32 v6, s8, v0
-; GFX9-NEXT:    v_mul_lo_u32 v8, v0, s8
+; GFX9-NEXT:    v_mul_hi_u32 v7, s8, v0
 ; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
-; GFX9-NEXT:    v_add_u32_e32 v4, v6, v4
+; GFX9-NEXT:    v_add_u32_e32 v4, v7, v4
+; GFX9-NEXT:    v_mul_lo_u32 v7, v0, s8
 ; GFX9-NEXT:    v_sub_u32_e32 v4, v4, v0
-; GFX9-NEXT:    v_mul_lo_u32 v10, v0, v4
-; GFX9-NEXT:    v_mul_hi_u32 v11, v0, v8
-; GFX9-NEXT:    v_mul_hi_u32 v12, v0, v4
-; GFX9-NEXT:    v_mul_hi_u32 v9, v2, v8
-; GFX9-NEXT:    v_mul_lo_u32 v8, v2, v8
-; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
-; GFX9-NEXT:    v_mul_hi_u32 v6, v2, v4
-; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, v7, v12, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v9, v0, v4
+; GFX9-NEXT:    v_mul_hi_u32 v11, v0, v4
+; GFX9-NEXT:    v_mul_hi_u32 v10, v0, v7
+; GFX9-NEXT:    v_mul_hi_u32 v12, v2, v7
+; GFX9-NEXT:    v_mul_lo_u32 v7, v2, v7
+; GFX9-NEXT:    v_mul_hi_u32 v8, v2, v4
+; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v10, v9
+; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v6, v11, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v2, v4
-; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v10, v8
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v11, v9, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v6, v5, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v8, v2
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v7, v4, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v9, v7
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v10, v12, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v8, v5, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v4, v2
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v6, v7, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e64 v1, vcc, v1, v4, s[2:3]
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    s_ashr_i32 s2, s7, 31
@@ -9867,18 +9863,18 @@
 ; GFX9-NEXT:    v_mul_lo_u32 v2, s0, v1
 ; GFX9-NEXT:    v_mul_hi_u32 v3, s0, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v4, s0, v1
-; GFX9-NEXT:    v_mul_hi_u32 v6, s1, v1
+; GFX9-NEXT:    v_mul_hi_u32 v7, s1, v1
 ; GFX9-NEXT:    v_mul_lo_u32 v1, s1, v1
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
-; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v7, v4, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v4, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v4, s1, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v0, s1, v0
 ; GFX9-NEXT:    s_mov_b32 s3, 0x12d8fb
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v4, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v6, v5, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v7, v5, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
-; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v7, v2, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v6, v2, vcc
 ; GFX9-NEXT:    v_mul_hi_u32 v2, s3, v0
 ; GFX9-NEXT:    v_mul_lo_u32 v1, v1, s3
 ; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s3
@@ -9976,136 +9972,135 @@
 ; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xd
 ; GFX6-NEXT:    s_mov_b32 s3, 0
 ; GFX6-NEXT:    s_movk_i32 s2, 0x1000
-; GFX6-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
+; GFX6-NEXT:    v_mov_b32_e32 v3, 0
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_lshl_b64 s[2:3], s[2:3], s4
 ; GFX6-NEXT:    s_ashr_i32 s4, s3, 31
 ; GFX6-NEXT:    s_add_u32 s2, s2, s4
 ; GFX6-NEXT:    s_mov_b32 s5, s4
 ; GFX6-NEXT:    s_addc_u32 s3, s3, s4
-; GFX6-NEXT:    s_xor_b64 s[12:13], s[2:3], s[4:5]
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s12
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s13
-; GFX6-NEXT:    s_sub_u32 s2, 0, s12
-; GFX6-NEXT:    s_subb_u32 s3, 0, s13
-; GFX6-NEXT:    s_ashr_i32 s14, s11, 31
+; GFX6-NEXT:    s_xor_b64 s[8:9], s[2:3], s[4:5]
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s8
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s9
+; GFX6-NEXT:    s_sub_u32 s10, 0, s8
+; GFX6-NEXT:    s_subb_u32 s4, 0, s9
 ; GFX6-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
 ; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
-; GFX6-NEXT:    s_mov_b32 s15, s14
-; GFX6-NEXT:    s_mov_b32 s6, -1
-; GFX6-NEXT:    s_mov_b32 s4, s8
+; GFX6-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX6-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GFX6-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
-; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
-; GFX6-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
+; GFX6-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
+; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
+; GFX6-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT:    s_mov_b32 s5, s9
-; GFX6-NEXT:    v_mul_hi_u32 v3, s2, v0
-; GFX6-NEXT:    v_mul_lo_u32 v2, s2, v1
-; GFX6-NEXT:    v_mul_lo_u32 v5, s3, v0
-; GFX6-NEXT:    v_mul_lo_u32 v4, s2, v0
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v2
+; GFX6-NEXT:    v_mul_hi_u32 v5, s10, v0
+; GFX6-NEXT:    v_mul_lo_u32 v4, s10, v2
+; GFX6-NEXT:    v_mul_lo_u32 v7, s4, v0
+; GFX6-NEXT:    v_mul_lo_u32 v6, s10, v0
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; GFX6-NEXT:    v_mul_hi_u32 v5, v0, v6
+; GFX6-NEXT:    v_mul_lo_u32 v7, v0, v4
+; GFX6-NEXT:    v_mul_hi_u32 v9, v0, v4
+; GFX6-NEXT:    v_mul_hi_u32 v8, v2, v6
+; GFX6-NEXT:    v_mul_lo_u32 v6, v2, v6
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; GFX6-NEXT:    v_mul_hi_u32 v10, v2, v4
+; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, 0, v9, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v4, v2, v4
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v7, v8, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, v10, v1, vcc
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; GFX6-NEXT:    v_add_i32_e64 v0, s[2:3], v0, v4
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v3, v6, vcc
+; GFX6-NEXT:    v_addc_u32_e64 v4, vcc, v2, v5, s[2:3]
+; GFX6-NEXT:    v_mul_lo_u32 v6, s10, v4
+; GFX6-NEXT:    v_mul_hi_u32 v7, s10, v0
+; GFX6-NEXT:    v_mul_lo_u32 v8, s4, v0
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GFX6-NEXT:    v_mul_lo_u32 v7, s10, v0
+; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
+; GFX6-NEXT:    v_mul_lo_u32 v9, v0, v6
+; GFX6-NEXT:    v_mul_hi_u32 v11, v0, v6
+; GFX6-NEXT:    v_mul_hi_u32 v10, v0, v7
+; GFX6-NEXT:    v_mul_hi_u32 v12, v4, v7
+; GFX6-NEXT:    v_mul_lo_u32 v7, v4, v7
+; GFX6-NEXT:    v_mul_hi_u32 v8, v4, v6
+; GFX6-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
+; GFX6-NEXT:    v_addc_u32_e32 v10, vcc, 0, v11, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v4, v4, v6
+; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v9, v7
+; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, v10, v12, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v8, v1, vcc
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
+; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:    s_ashr_i32 s10, s7, 31
+; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, v3, v7, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
-; GFX6-NEXT:    v_mul_hi_u32 v3, v0, v4
-; GFX6-NEXT:    v_mul_lo_u32 v5, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v7, v1, v2
-; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
+; GFX6-NEXT:    s_add_u32 s0, s6, s10
+; GFX6-NEXT:    v_addc_u32_e64 v2, vcc, v2, v6, s[2:3]
+; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
+; GFX6-NEXT:    s_addc_u32 s1, s7, s10
+; GFX6-NEXT:    s_mov_b32 s11, s10
+; GFX6-NEXT:    s_xor_b64 s[12:13], s[0:1], s[10:11]
+; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v4, s12, v2
+; GFX6-NEXT:    v_mul_hi_u32 v5, s12, v0
+; GFX6-NEXT:    v_mul_hi_u32 v6, s12, v2
+; GFX6-NEXT:    v_mul_hi_u32 v7, s13, v2
+; GFX6-NEXT:    v_mul_lo_u32 v2, s13, v2
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v4
-; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v4, vcc
-; GFX6-NEXT:    v_mov_b32_e32 v4, 0
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v7, v4, vcc
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_mov_b32_e32 v6, 0
-; GFX6-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v2
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v6, v5, vcc
-; GFX6-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
-; GFX6-NEXT:    v_mul_lo_u32 v5, s2, v2
-; GFX6-NEXT:    v_mul_hi_u32 v7, s2, v0
-; GFX6-NEXT:    v_mul_lo_u32 v8, s3, v0
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
-; GFX6-NEXT:    v_mul_lo_u32 v7, s2, v0
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; GFX6-NEXT:    v_mul_lo_u32 v10, v0, v5
-; GFX6-NEXT:    v_mul_hi_u32 v12, v0, v5
-; GFX6-NEXT:    v_mul_hi_u32 v11, v0, v7
-; GFX6-NEXT:    v_mul_hi_u32 v9, v2, v7
-; GFX6-NEXT:    v_mul_lo_u32 v7, v2, v7
-; GFX6-NEXT:    v_mul_hi_u32 v8, v2, v5
-; GFX6-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; GFX6-NEXT:    v_addc_u32_e32 v11, vcc, 0, v12, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v2, v2, v5
-; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
-; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v11, v9, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v8, v4, vcc
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v7, v2
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v6, v5, vcc
-; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
-; GFX6-NEXT:    v_addc_u32_e64 v1, vcc, v1, v5, s[0:1]
-; GFX6-NEXT:    s_add_u32 s0, s10, s14
-; GFX6-NEXT:    s_addc_u32 s1, s11, s14
+; GFX6-NEXT:    v_mul_lo_u32 v6, s13, v0
+; GFX6-NEXT:    v_mul_hi_u32 v0, s13, v0
+; GFX6-NEXT:    s_mov_b32 s7, 0xf000
+; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
+; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v5, v0, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v7, v1, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
-; GFX6-NEXT:    s_xor_b64 s[10:11], s[0:1], s[14:15]
-; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v2, s10, v1
-; GFX6-NEXT:    v_mul_hi_u32 v3, s10, v0
-; GFX6-NEXT:    v_mul_hi_u32 v5, s10, v1
-; GFX6-NEXT:    v_mul_hi_u32 v7, s11, v1
-; GFX6-NEXT:    v_mul_lo_u32 v1, s11, v1
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v5, s11, v0
-; GFX6-NEXT:    v_mul_hi_u32 v0, s11, v0
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
-; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v7, v4, vcc
-; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
-; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v6, v2, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v1, s12, v1
-; GFX6-NEXT:    v_mul_hi_u32 v2, s12, v0
-; GFX6-NEXT:    v_mul_lo_u32 v3, s13, v0
-; GFX6-NEXT:    v_mul_lo_u32 v0, s12, v0
+; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v3, v1, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v1, s8, v1
+; GFX6-NEXT:    v_mul_hi_u32 v2, s8, v0
+; GFX6-NEXT:    v_mul_lo_u32 v3, s9, v0
+; GFX6-NEXT:    v_mul_lo_u32 v0, s8, v0
 ; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
 ; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
-; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s11, v1
-; GFX6-NEXT:    v_mov_b32_e32 v3, s13
-; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s10, v0
+; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s13, v1
+; GFX6-NEXT:    v_mov_b32_e32 v3, s9
+; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s12, v0
 ; GFX6-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
-; GFX6-NEXT:    v_subrev_i32_e64 v4, s[0:1], s12, v0
+; GFX6-NEXT:    v_subrev_i32_e64 v4, s[0:1], s8, v0
 ; GFX6-NEXT:    v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
-; GFX6-NEXT:    v_cmp_le_u32_e64 s[2:3], s13, v5
+; GFX6-NEXT:    v_cmp_le_u32_e64 s[2:3], s9, v5
 ; GFX6-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
 ; GFX6-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[2:3]
-; GFX6-NEXT:    v_cmp_le_u32_e64 s[2:3], s12, v4
-; GFX6-NEXT:    v_subrev_i32_e64 v3, s[0:1], s12, v4
+; GFX6-NEXT:    v_cmp_le_u32_e64 s[2:3], s8, v4
+; GFX6-NEXT:    v_subrev_i32_e64 v3, s[0:1], s8, v4
 ; GFX6-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
-; GFX6-NEXT:    v_cmp_eq_u32_e64 s[2:3], s13, v5
+; GFX6-NEXT:    v_cmp_eq_u32_e64 s[2:3], s9, v5
 ; GFX6-NEXT:    v_cndmask_b32_e64 v6, v6, v7, s[2:3]
 ; GFX6-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
 ; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
 ; GFX6-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[0:1]
-; GFX6-NEXT:    v_mov_b32_e32 v5, s11
+; GFX6-NEXT:    v_mov_b32_e32 v5, s13
 ; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v5, v1, vcc
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s13, v1
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
 ; GFX6-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s12, v0
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
 ; GFX6-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
-; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s13, v1
+; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v1
 ; GFX6-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
 ; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
 ; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
 ; GFX6-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[0:1]
 ; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX6-NEXT:    v_xor_b32_e32 v0, s14, v0
-; GFX6-NEXT:    v_xor_b32_e32 v1, s14, v1
-; GFX6-NEXT:    v_mov_b32_e32 v2, s14
-; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s14, v0
+; GFX6-NEXT:    v_xor_b32_e32 v0, s10, v0
+; GFX6-NEXT:    v_xor_b32_e32 v1, s10, v1
+; GFX6-NEXT:    v_mov_b32_e32 v2, s10
+; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s10, v0
 ; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
 ; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; GFX6-NEXT:    s_endpgm
@@ -10116,6 +10111,7 @@
 ; GFX9-NEXT:    s_mov_b32 s3, 0
 ; GFX9-NEXT:    s_movk_i32 s2, 0x1000
 ; GFX9-NEXT:    v_mov_b32_e32 v2, 0
+; GFX9-NEXT:    v_mov_b32_e32 v3, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    s_lshl_b64 s[2:3], s[2:3], s4
 ; GFX9-NEXT:    s_ashr_i32 s4, s3, 31
@@ -10135,74 +10131,73 @@
 ; GFX9-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX9-NEXT:    v_mul_hi_u32 v4, s10, v0
-; GFX9-NEXT:    v_mul_lo_u32 v3, s10, v1
-; GFX9-NEXT:    v_mul_lo_u32 v6, s4, v0
-; GFX9-NEXT:    v_mul_lo_u32 v5, s10, v0
-; GFX9-NEXT:    v_add_u32_e32 v3, v4, v3
-; GFX9-NEXT:    v_add_u32_e32 v3, v3, v6
-; GFX9-NEXT:    v_mul_hi_u32 v4, v0, v5
-; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v3
-; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v3
-; GFX9-NEXT:    v_mul_hi_u32 v7, v1, v5
-; GFX9-NEXT:    v_mul_lo_u32 v5, v1, v5
-; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v6
-; GFX9-NEXT:    v_mul_hi_u32 v9, v1, v3
-; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v8, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v3, v1, v3
+; GFX9-NEXT:    v_mul_hi_u32 v5, s10, v0
+; GFX9-NEXT:    v_mul_lo_u32 v4, s10, v1
+; GFX9-NEXT:    v_mul_lo_u32 v7, s4, v0
+; GFX9-NEXT:    v_mul_lo_u32 v6, s10, v0
+; GFX9-NEXT:    v_add_u32_e32 v4, v5, v4
+; GFX9-NEXT:    v_add_u32_e32 v4, v4, v7
+; GFX9-NEXT:    v_mul_hi_u32 v5, v0, v6
+; GFX9-NEXT:    v_mul_lo_u32 v7, v0, v4
+; GFX9-NEXT:    v_mul_hi_u32 v9, v0, v4
+; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v6
+; GFX9-NEXT:    v_mul_lo_u32 v6, v1, v6
+; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v7
+; GFX9-NEXT:    v_mul_hi_u32 v10, v1, v4
+; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v9, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v4, v1, v4
+; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v6, v5
+; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v7, v8, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v10, v2, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v5, v4
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v6, v7, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v9, v2, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
-; GFX9-NEXT:    v_mov_b32_e32 v6, 0
-; GFX9-NEXT:    v_add_co_u32_e64 v0, s[2:3], v0, v3
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v6, v5, vcc
-; GFX9-NEXT:    v_addc_co_u32_e64 v3, vcc, v1, v4, s[2:3]
-; GFX9-NEXT:    v_mul_lo_u32 v5, s10, v3
+; GFX9-NEXT:    v_add_co_u32_e64 v0, s[2:3], v0, v4
+; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v3, v6, vcc
+; GFX9-NEXT:    v_addc_co_u32_e64 v4, vcc, v1, v5, s[2:3]
+; GFX9-NEXT:    v_mul_lo_u32 v6, s10, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v7, s10, v0
 ; GFX9-NEXT:    v_mul_lo_u32 v8, s4, v0
-; GFX9-NEXT:    v_mul_lo_u32 v9, s10, v0
 ; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX9-NEXT:    v_add_u32_e32 v5, v7, v5
-; GFX9-NEXT:    v_add_u32_e32 v5, v5, v8
-; GFX9-NEXT:    v_mul_lo_u32 v10, v0, v5
-; GFX9-NEXT:    v_mul_hi_u32 v11, v0, v9
-; GFX9-NEXT:    v_mul_hi_u32 v12, v0, v5
-; GFX9-NEXT:    v_mul_hi_u32 v8, v3, v9
-; GFX9-NEXT:    v_mul_lo_u32 v9, v3, v9
-; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
-; GFX9-NEXT:    v_mul_hi_u32 v7, v3, v5
-; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, 0, v12, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v3, v3, v5
+; GFX9-NEXT:    v_add_u32_e32 v1, v1, v5
+; GFX9-NEXT:    v_add_u32_e32 v6, v7, v6
+; GFX9-NEXT:    v_mul_lo_u32 v7, s10, v0
+; GFX9-NEXT:    v_add_u32_e32 v6, v6, v8
+; GFX9-NEXT:    v_mul_lo_u32 v9, v0, v6
+; GFX9-NEXT:    v_mul_hi_u32 v11, v0, v6
+; GFX9-NEXT:    v_mul_hi_u32 v10, v0, v7
+; GFX9-NEXT:    v_mul_hi_u32 v12, v4, v7
+; GFX9-NEXT:    v_mul_lo_u32 v7, v4, v7
+; GFX9-NEXT:    v_mul_hi_u32 v8, v4, v6
 ; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v10, v9
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v11, v8, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v7, v2, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v8, v3
+; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, 0, v11, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v4, v4, v6
+; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v9, v7
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v10, v12, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v8, v2, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v6, v4
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    s_ashr_i32 s10, s7, 31
-; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v6, v5, vcc
-; GFX9-NEXT:    v_add_u32_e32 v1, v1, v4
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v3, v7, vcc
 ; GFX9-NEXT:    s_add_u32 s0, s6, s10
-; GFX9-NEXT:    v_addc_co_u32_e64 v1, vcc, v1, v5, s[2:3]
-; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v3
+; GFX9-NEXT:    v_addc_co_u32_e64 v1, vcc, v1, v6, s[2:3]
+; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v4
 ; GFX9-NEXT:    s_mov_b32 s11, s10
 ; GFX9-NEXT:    s_addc_u32 s1, s7, s10
 ; GFX9-NEXT:    s_xor_b64 s[6:7], s[0:1], s[10:11]
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v3, s6, v1
-; GFX9-NEXT:    v_mul_hi_u32 v4, s6, v0
-; GFX9-NEXT:    v_mul_hi_u32 v5, s6, v1
+; GFX9-NEXT:    v_mul_lo_u32 v4, s6, v1
+; GFX9-NEXT:    v_mul_hi_u32 v5, s6, v0
+; GFX9-NEXT:    v_mul_hi_u32 v6, s6, v1
 ; GFX9-NEXT:    v_mul_hi_u32 v7, s7, v1
 ; GFX9-NEXT:    v_mul_lo_u32 v1, s7, v1
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v5, s7, v0
+; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v5, v4
+; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v6, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v6, s7, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v0, s7, v0
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v5, v3
-; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v4, v0, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v7, v2, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v6, v4
+; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v5, v0, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v7, v2, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
-; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v6, v3, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v3, v4, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v1, s8, v1
 ; GFX9-NEXT:    v_mul_hi_u32 v3, s8, v0
 ; GFX9-NEXT:    v_mul_lo_u32 v4, s9, v0
@@ -10345,23 +10340,23 @@
 ; GFX6-NEXT:    s_mov_b32 s18, 0x4f800000
 ; GFX6-NEXT:    s_mov_b32 s19, 0x5f7ffffc
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    s_lshl_b64 s[14:15], s[2:3], s6
+; GFX6-NEXT:    s_lshl_b64 s[16:17], s[2:3], s6
 ; GFX6-NEXT:    s_lshl_b64 s[2:3], s[2:3], s4
 ; GFX6-NEXT:    s_ashr_i32 s4, s3, 31
 ; GFX6-NEXT:    s_add_u32 s2, s2, s4
 ; GFX6-NEXT:    s_mov_b32 s5, s4
 ; GFX6-NEXT:    s_addc_u32 s3, s3, s4
-; GFX6-NEXT:    s_xor_b64 s[16:17], s[2:3], s[4:5]
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s16
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s17
+; GFX6-NEXT:    s_xor_b64 s[10:11], s[2:3], s[4:5]
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s10
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s11
 ; GFX6-NEXT:    s_mov_b32 s20, 0x2f800000
 ; GFX6-NEXT:    s_mov_b32 s21, 0xcf800000
-; GFX6-NEXT:    s_sub_u32 s6, 0, s16
+; GFX6-NEXT:    s_sub_u32 s4, 0, s10
 ; GFX6-NEXT:    v_mac_f32_e32 v0, s18, v1
 ; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
-; GFX6-NEXT:    s_subb_u32 s7, 0, s17
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
+; GFX6-NEXT:    s_subb_u32 s5, 0, s11
+; GFX6-NEXT:    s_load_dwordx4 s[12:15], s[0:1], 0xd
+; GFX6-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX6-NEXT:    v_mul_f32_e32 v0, s19, v0
 ; GFX6-NEXT:    v_mul_f32_e32 v1, s20, v0
 ; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
@@ -10369,237 +10364,238 @@
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    s_ashr_i32 s12, s9, 31
-; GFX6-NEXT:    s_add_u32 s0, s8, s12
-; GFX6-NEXT:    v_mul_hi_u32 v3, s6, v0
-; GFX6-NEXT:    v_mul_lo_u32 v2, s6, v1
-; GFX6-NEXT:    v_mul_lo_u32 v4, s7, v0
-; GFX6-NEXT:    v_mul_lo_u32 v5, s6, v0
-; GFX6-NEXT:    s_mov_b32 s13, s12
+; GFX6-NEXT:    s_ashr_i32 s8, s13, 31
+; GFX6-NEXT:    s_mov_b32 s9, s8
+; GFX6-NEXT:    v_mul_hi_u32 v3, s4, v0
+; GFX6-NEXT:    v_mul_lo_u32 v2, s4, v1
+; GFX6-NEXT:    v_mul_lo_u32 v5, s5, v0
+; GFX6-NEXT:    v_mul_lo_u32 v4, s4, v0
+; GFX6-NEXT:    s_mov_b32 s6, -1
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
-; GFX6-NEXT:    v_mul_lo_u32 v3, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v4, v0, v5
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; GFX6-NEXT:    v_mul_hi_u32 v3, v0, v4
+; GFX6-NEXT:    v_mul_lo_u32 v5, v0, v2
 ; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v7, v1, v2
+; GFX6-NEXT:    v_mul_hi_u32 v7, v1, v4
+; GFX6-NEXT:    v_mul_lo_u32 v4, v1, v4
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
+; GFX6-NEXT:    v_mul_hi_u32 v6, v1, v2
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
 ; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v6, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v5
-; GFX6-NEXT:    v_mul_hi_u32 v5, v1, v5
-; GFX6-NEXT:    s_addc_u32 s1, s9, s12
-; GFX6-NEXT:    s_xor_b64 s[8:9], s[0:1], s[12:13]
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v4, v5, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v7, vcc
 ; GFX6-NEXT:    v_mov_b32_e32 v4, 0
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v7, v4, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v6, v4, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_mov_b32_e32 v6, 0
 ; GFX6-NEXT:    v_add_i32_e64 v0, s[2:3], v0, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v6, v5, vcc
 ; GFX6-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[2:3]
-; GFX6-NEXT:    v_mul_lo_u32 v5, s6, v2
-; GFX6-NEXT:    v_mul_hi_u32 v7, s6, v0
-; GFX6-NEXT:    v_mul_lo_u32 v8, s7, v0
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
+; GFX6-NEXT:    v_mul_lo_u32 v5, s4, v2
+; GFX6-NEXT:    v_mul_hi_u32 v7, s4, v0
+; GFX6-NEXT:    v_mul_lo_u32 v8, s5, v0
 ; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
-; GFX6-NEXT:    v_mul_lo_u32 v7, s6, v0
+; GFX6-NEXT:    v_mul_lo_u32 v7, s4, v0
 ; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; GFX6-NEXT:    v_mul_lo_u32 v10, v0, v5
-; GFX6-NEXT:    v_mul_hi_u32 v12, v0, v5
-; GFX6-NEXT:    v_mul_hi_u32 v11, v0, v7
-; GFX6-NEXT:    v_mul_hi_u32 v9, v2, v7
+; GFX6-NEXT:    v_mul_lo_u32 v9, v0, v5
+; GFX6-NEXT:    v_mul_hi_u32 v11, v0, v5
+; GFX6-NEXT:    v_mul_hi_u32 v10, v0, v7
+; GFX6-NEXT:    v_mul_hi_u32 v12, v2, v7
 ; GFX6-NEXT:    v_mul_lo_u32 v7, v2, v7
 ; GFX6-NEXT:    v_mul_hi_u32 v8, v2, v5
-; GFX6-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; GFX6-NEXT:    v_addc_u32_e32 v11, vcc, 0, v12, vcc
+; GFX6-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
+; GFX6-NEXT:    v_addc_u32_e32 v10, vcc, 0, v11, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v2, v5
-; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
-; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v11, v9, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v8, v4, vcc
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v7, v2
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v6, v5, vcc
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v9, v7
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v10, v12, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v8, v4, vcc
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v6, v7, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
 ; GFX6-NEXT:    v_addc_u32_e64 v1, vcc, v1, v5, s[2:3]
+; GFX6-NEXT:    s_add_u32 s2, s12, s8
+; GFX6-NEXT:    s_addc_u32 s3, s13, s8
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT:    s_xor_b64 s[12:13], s[2:3], s[8:9]
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v2, s8, v1
-; GFX6-NEXT:    v_mul_hi_u32 v3, s8, v0
-; GFX6-NEXT:    v_mul_hi_u32 v5, s8, v1
-; GFX6-NEXT:    v_mul_hi_u32 v7, s9, v1
-; GFX6-NEXT:    v_mul_lo_u32 v1, s9, v1
+; GFX6-NEXT:    v_mul_lo_u32 v2, s12, v1
+; GFX6-NEXT:    v_mul_hi_u32 v3, s12, v0
+; GFX6-NEXT:    v_mul_hi_u32 v5, s12, v1
+; GFX6-NEXT:    v_mul_hi_u32 v7, s13, v1
+; GFX6-NEXT:    v_mul_lo_u32 v1, s13, v1
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v5, s9, v0
-; GFX6-NEXT:    v_mul_hi_u32 v0, s9, v0
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    v_mul_lo_u32 v5, s13, v0
+; GFX6-NEXT:    v_mul_hi_u32 v0, s13, v0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
 ; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v7, v4, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v6, v2, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v1, s16, v1
-; GFX6-NEXT:    v_mul_hi_u32 v2, s16, v0
-; GFX6-NEXT:    v_mul_lo_u32 v3, s17, v0
-; GFX6-NEXT:    v_mul_lo_u32 v0, s16, v0
+; GFX6-NEXT:    v_mul_lo_u32 v1, s10, v1
+; GFX6-NEXT:    v_mul_hi_u32 v2, s10, v0
+; GFX6-NEXT:    v_mul_lo_u32 v3, s11, v0
+; GFX6-NEXT:    v_mul_lo_u32 v0, s10, v0
 ; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
 ; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
-; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s9, v1
-; GFX6-NEXT:    v_mov_b32_e32 v3, s17
-; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s8, v0
+; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s13, v1
+; GFX6-NEXT:    v_mov_b32_e32 v3, s11
+; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s12, v0
 ; GFX6-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
-; GFX6-NEXT:    v_subrev_i32_e64 v5, s[0:1], s16, v0
+; GFX6-NEXT:    v_subrev_i32_e64 v5, s[0:1], s10, v0
 ; GFX6-NEXT:    v_subbrev_u32_e64 v7, s[2:3], 0, v2, s[0:1]
-; GFX6-NEXT:    v_cmp_le_u32_e64 s[2:3], s17, v7
 ; GFX6-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
+; GFX6-NEXT:    v_subrev_i32_e64 v3, s[0:1], s10, v5
+; GFX6-NEXT:    v_cmp_le_u32_e64 s[2:3], s11, v7
+; GFX6-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
 ; GFX6-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[2:3]
-; GFX6-NEXT:    v_cmp_le_u32_e64 s[2:3], s16, v5
-; GFX6-NEXT:    v_subrev_i32_e64 v3, s[0:1], s16, v5
+; GFX6-NEXT:    v_cmp_le_u32_e64 s[2:3], s10, v5
 ; GFX6-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[2:3]
-; GFX6-NEXT:    v_cmp_eq_u32_e64 s[2:3], s17, v7
+; GFX6-NEXT:    v_cmp_eq_u32_e64 s[2:3], s11, v7
+; GFX6-NEXT:    s_ashr_i32 s0, s17, 31
 ; GFX6-NEXT:    v_cndmask_b32_e64 v8, v8, v9, s[2:3]
-; GFX6-NEXT:    s_ashr_i32 s2, s15, 31
-; GFX6-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
+; GFX6-NEXT:    s_add_u32 s2, s16, s0
+; GFX6-NEXT:    s_mov_b32 s1, s0
+; GFX6-NEXT:    s_addc_u32 s3, s17, s0
+; GFX6-NEXT:    s_xor_b64 s[16:17], s[2:3], s[0:1]
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v9, s16
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v10, s17
 ; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v8
-; GFX6-NEXT:    s_add_u32 s8, s14, s2
 ; GFX6-NEXT:    v_cndmask_b32_e64 v2, v7, v2, s[0:1]
-; GFX6-NEXT:    v_mov_b32_e32 v7, s9
-; GFX6-NEXT:    s_mov_b32 s3, s2
-; GFX6-NEXT:    s_addc_u32 s9, s15, s2
-; GFX6-NEXT:    s_xor_b64 s[8:9], s[8:9], s[2:3]
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v8, s8
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v9, s9
+; GFX6-NEXT:    v_mov_b32_e32 v7, s13
+; GFX6-NEXT:    v_mac_f32_e32 v9, s18, v10
 ; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v7, v1, vcc
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s17, v1
-; GFX6-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
-; GFX6-NEXT:    v_mac_f32_e32 v8, s18, v9
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s16, v0
-; GFX6-NEXT:    v_rcp_f32_e32 v8, v8
-; GFX6-NEXT:    v_cndmask_b32_e64 v10, 0, -1, vcc
-; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s17, v1
-; GFX6-NEXT:    v_cndmask_b32_e32 v7, v7, v10, vcc
-; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
-; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX6-NEXT:    v_rcp_f32_e32 v7, v9
+; GFX6-NEXT:    s_sub_u32 s9, 0, s16
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s11, v1
+; GFX6-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
+; GFX6-NEXT:    v_mul_f32_e32 v7, s19, v7
+; GFX6-NEXT:    v_mul_f32_e32 v10, s20, v7
+; GFX6-NEXT:    v_trunc_f32_e32 v10, v10
+; GFX6-NEXT:    v_mac_f32_e32 v7, s21, v10
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v7, v7
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v10, v10
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v0
+; GFX6-NEXT:    s_subb_u32 s10, 0, s17
+; GFX6-NEXT:    v_mul_hi_u32 v11, s9, v7
+; GFX6-NEXT:    v_mul_lo_u32 v12, s9, v10
+; GFX6-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
+; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s11, v1
+; GFX6-NEXT:    v_mul_lo_u32 v13, s10, v7
+; GFX6-NEXT:    v_cndmask_b32_e32 v8, v8, v9, vcc
+; GFX6-NEXT:    v_add_i32_e32 v9, vcc, v11, v12
+; GFX6-NEXT:    v_mul_lo_u32 v11, s9, v7
+; GFX6-NEXT:    v_add_i32_e32 v9, vcc, v9, v13
+; GFX6-NEXT:    v_mul_lo_u32 v13, v7, v9
+; GFX6-NEXT:    v_mul_hi_u32 v12, v7, v9
+; GFX6-NEXT:    v_mul_hi_u32 v14, v7, v11
+; GFX6-NEXT:    v_cmp_ne_u32_e64 s[2:3], 0, v8
+; GFX6-NEXT:    v_mul_lo_u32 v8, v10, v11
+; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v2, s[2:3]
 ; GFX6-NEXT:    v_cndmask_b32_e64 v2, v5, v3, s[0:1]
-; GFX6-NEXT:    v_mul_f32_e32 v3, s19, v8
-; GFX6-NEXT:    v_mul_f32_e32 v5, s20, v3
-; GFX6-NEXT:    v_trunc_f32_e32 v5, v5
-; GFX6-NEXT:    v_mac_f32_e32 v3, s21, v5
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v3
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v5, v5
-; GFX6-NEXT:    s_sub_u32 s2, 0, s8
-; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX6-NEXT:    v_mul_hi_u32 v2, s2, v3
-; GFX6-NEXT:    v_mul_lo_u32 v7, s2, v5
-; GFX6-NEXT:    s_subb_u32 s3, 0, s9
-; GFX6-NEXT:    v_mul_lo_u32 v8, s3, v3
-; GFX6-NEXT:    s_ashr_i32 s14, s11, 31
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v7
-; GFX6-NEXT:    v_mul_lo_u32 v7, s2, v3
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v8
-; GFX6-NEXT:    v_mul_lo_u32 v8, v3, v2
-; GFX6-NEXT:    v_mul_hi_u32 v10, v3, v2
-; GFX6-NEXT:    v_mul_hi_u32 v9, v3, v7
-; GFX6-NEXT:    v_mul_hi_u32 v11, v5, v2
-; GFX6-NEXT:    v_mul_lo_u32 v2, v5, v2
-; GFX6-NEXT:    s_mov_b32 s15, s14
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v14, v13
+; GFX6-NEXT:    v_mul_hi_u32 v11, v10, v11
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v12, vcc
+; GFX6-NEXT:    v_mul_hi_u32 v12, v10, v9
+; GFX6-NEXT:    v_mul_lo_u32 v9, v10, v9
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v8, v3
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v11, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v12, v4, vcc
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v9
+; GFX6-NEXT:    v_add_i32_e64 v3, s[0:1], v7, v3
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v6, v5, vcc
+; GFX6-NEXT:    v_addc_u32_e64 v7, vcc, v10, v5, s[0:1]
+; GFX6-NEXT:    v_mul_lo_u32 v8, s9, v7
+; GFX6-NEXT:    v_mul_hi_u32 v9, s9, v3
+; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[2:3]
+; GFX6-NEXT:    v_mul_lo_u32 v2, s10, v3
+; GFX6-NEXT:    s_ashr_i32 s10, s15, 31
 ; GFX6-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
-; GFX6-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v10, v5, v7
-; GFX6-NEXT:    v_mul_hi_u32 v7, v5, v7
-; GFX6-NEXT:    v_xor_b32_e32 v0, s12, v0
-; GFX6-NEXT:    v_xor_b32_e32 v1, s12, v1
-; GFX6-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
-; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v9, v7, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, v11, v4, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v9, s9, v3
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v8
+; GFX6-NEXT:    v_mul_lo_u32 v11, v3, v2
+; GFX6-NEXT:    v_mul_hi_u32 v13, v3, v2
+; GFX6-NEXT:    v_mul_hi_u32 v12, v3, v9
+; GFX6-NEXT:    v_mul_hi_u32 v14, v7, v9
+; GFX6-NEXT:    v_mul_lo_u32 v9, v7, v9
+; GFX6-NEXT:    v_mul_hi_u32 v8, v7, v2
+; GFX6-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
+; GFX6-NEXT:    v_addc_u32_e32 v12, vcc, 0, v13, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v2, v7, v2
+; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v11, v9
+; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v12, v14, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, v8, v4, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v7, v2
-; GFX6-NEXT:    v_add_i32_e64 v2, s[0:1], v3, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v6, v8, vcc
-; GFX6-NEXT:    v_addc_u32_e64 v3, vcc, v5, v7, s[0:1]
-; GFX6-NEXT:    v_mul_lo_u32 v8, s2, v3
-; GFX6-NEXT:    v_mul_hi_u32 v9, s2, v2
-; GFX6-NEXT:    v_mul_lo_u32 v10, s3, v2
-; GFX6-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
-; GFX6-NEXT:    v_mul_lo_u32 v9, s2, v2
-; GFX6-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
-; GFX6-NEXT:    v_mul_lo_u32 v12, v2, v8
-; GFX6-NEXT:    v_mul_hi_u32 v14, v2, v8
-; GFX6-NEXT:    v_mul_hi_u32 v13, v2, v9
-; GFX6-NEXT:    v_mul_hi_u32 v11, v3, v9
-; GFX6-NEXT:    v_mul_lo_u32 v9, v3, v9
-; GFX6-NEXT:    v_mul_hi_u32 v10, v3, v8
-; GFX6-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
-; GFX6-NEXT:    v_addc_u32_e32 v13, vcc, 0, v14, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v3, v3, v8
-; GFX6-NEXT:    v_add_i32_e32 v9, vcc, v12, v9
-; GFX6-NEXT:    v_addc_u32_e32 v9, vcc, v13, v11, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, v10, v4, vcc
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v9, v3
-; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, v6, v8, vcc
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; GFX6-NEXT:    v_addc_u32_e64 v5, vcc, v5, v8, s[0:1]
-; GFX6-NEXT:    s_add_u32 s0, s10, s14
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
-; GFX6-NEXT:    s_addc_u32 s1, s11, s14
-; GFX6-NEXT:    s_xor_b64 s[10:11], s[0:1], s[14:15]
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v10, v5
+; GFX6-NEXT:    v_addc_u32_e64 v5, vcc, v5, v7, s[0:1]
+; GFX6-NEXT:    s_add_u32 s0, s14, s10
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT:    s_mov_b32 s11, s10
+; GFX6-NEXT:    s_addc_u32 s1, s15, s10
+; GFX6-NEXT:    s_xor_b64 s[12:13], s[0:1], s[10:11]
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v5, s10, v3
-; GFX6-NEXT:    v_mul_hi_u32 v7, s10, v2
-; GFX6-NEXT:    v_mul_hi_u32 v9, s10, v3
-; GFX6-NEXT:    v_mul_hi_u32 v10, s11, v3
-; GFX6-NEXT:    v_mul_lo_u32 v3, s11, v3
+; GFX6-NEXT:    v_mul_lo_u32 v5, s12, v3
+; GFX6-NEXT:    v_mul_hi_u32 v7, s12, v2
+; GFX6-NEXT:    v_mul_hi_u32 v8, s12, v3
+; GFX6-NEXT:    v_mul_hi_u32 v10, s13, v3
+; GFX6-NEXT:    v_mul_lo_u32 v3, s13, v3
 ; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
-; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, 0, v9, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v9, s11, v2
-; GFX6-NEXT:    v_mul_hi_u32 v2, s11, v2
-; GFX6-NEXT:    v_mov_b32_e32 v8, s12
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v9, v5
+; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v8, s13, v2
+; GFX6-NEXT:    v_mul_hi_u32 v2, s13, v2
+; GFX6-NEXT:    v_xor_b32_e32 v0, s8, v0
+; GFX6-NEXT:    v_xor_b32_e32 v1, s8, v1
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
 ; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v7, v2, vcc
 ; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v10, v4, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v6, v4, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v3, s8, v3
-; GFX6-NEXT:    v_mul_hi_u32 v4, s8, v2
-; GFX6-NEXT:    v_mul_lo_u32 v5, s9, v2
-; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s12, v0
-; GFX6-NEXT:    v_mul_lo_u32 v2, s8, v2
-; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v1, v8, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v3, s16, v3
+; GFX6-NEXT:    v_mul_hi_u32 v4, s16, v2
+; GFX6-NEXT:    v_mul_lo_u32 v5, s17, v2
+; GFX6-NEXT:    v_mov_b32_e32 v9, s8
+; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s8, v0
+; GFX6-NEXT:    v_mul_lo_u32 v2, s16, v2
+; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v1, v9, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
 ; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
-; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s11, v3
-; GFX6-NEXT:    v_mov_b32_e32 v5, s9
-; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s10, v2
+; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s13, v3
+; GFX6-NEXT:    v_mov_b32_e32 v5, s17
+; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s12, v2
 ; GFX6-NEXT:    v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
-; GFX6-NEXT:    v_subrev_i32_e64 v6, s[0:1], s8, v2
+; GFX6-NEXT:    v_subrev_i32_e64 v6, s[0:1], s16, v2
 ; GFX6-NEXT:    v_subbrev_u32_e64 v7, s[2:3], 0, v4, s[0:1]
-; GFX6-NEXT:    v_cmp_le_u32_e64 s[2:3], s9, v7
+; GFX6-NEXT:    v_cmp_le_u32_e64 s[2:3], s17, v7
 ; GFX6-NEXT:    v_subb_u32_e64 v4, s[0:1], v4, v5, s[0:1]
 ; GFX6-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[2:3]
-; GFX6-NEXT:    v_cmp_le_u32_e64 s[2:3], s8, v6
-; GFX6-NEXT:    v_subrev_i32_e64 v5, s[0:1], s8, v6
+; GFX6-NEXT:    v_cmp_le_u32_e64 s[2:3], s16, v6
+; GFX6-NEXT:    v_subrev_i32_e64 v5, s[0:1], s16, v6
 ; GFX6-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[2:3]
-; GFX6-NEXT:    v_cmp_eq_u32_e64 s[2:3], s9, v7
+; GFX6-NEXT:    v_cmp_eq_u32_e64 s[2:3], s17, v7
 ; GFX6-NEXT:    v_cndmask_b32_e64 v8, v8, v9, s[2:3]
 ; GFX6-NEXT:    v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
 ; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v8
 ; GFX6-NEXT:    v_cndmask_b32_e64 v4, v7, v4, s[0:1]
-; GFX6-NEXT:    v_mov_b32_e32 v7, s11
+; GFX6-NEXT:    v_mov_b32_e32 v7, s13
 ; GFX6-NEXT:    v_subb_u32_e32 v3, vcc, v7, v3, vcc
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v3
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s17, v3
 ; GFX6-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v2
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s16, v2
 ; GFX6-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
-; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v3
+; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s17, v3
 ; GFX6-NEXT:    v_cndmask_b32_e32 v7, v7, v8, vcc
 ; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
 ; GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
 ; GFX6-NEXT:    v_cndmask_b32_e64 v4, v6, v5, s[0:1]
 ; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
-; GFX6-NEXT:    v_xor_b32_e32 v2, s14, v2
-; GFX6-NEXT:    v_xor_b32_e32 v3, s14, v3
-; GFX6-NEXT:    v_mov_b32_e32 v4, s14
-; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s14, v2
+; GFX6-NEXT:    v_xor_b32_e32 v2, s10, v2
+; GFX6-NEXT:    v_xor_b32_e32 v3, s10, v3
+; GFX6-NEXT:    v_mov_b32_e32 v4, s10
+; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s10, v2
 ; GFX6-NEXT:    v_subb_u32_e32 v3, vcc, v3, v4, vcc
+; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -10611,22 +10607,22 @@
 ; GFX9-NEXT:    s_mov_b32 s16, 0x4f800000
 ; GFX9-NEXT:    s_mov_b32 s17, 0x5f7ffffc
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    s_lshl_b64 s[12:13], s[2:3], s6
+; GFX9-NEXT:    s_lshl_b64 s[14:15], s[2:3], s6
 ; GFX9-NEXT:    s_lshl_b64 s[2:3], s[2:3], s4
 ; GFX9-NEXT:    s_ashr_i32 s4, s3, 31
 ; GFX9-NEXT:    s_add_u32 s2, s2, s4
 ; GFX9-NEXT:    s_mov_b32 s5, s4
 ; GFX9-NEXT:    s_addc_u32 s3, s3, s4
-; GFX9-NEXT:    s_xor_b64 s[14:15], s[2:3], s[4:5]
-; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s14
-; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s15
+; GFX9-NEXT:    s_xor_b64 s[12:13], s[2:3], s[4:5]
+; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s12
+; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s13
 ; GFX9-NEXT:    s_mov_b32 s18, 0x2f800000
 ; GFX9-NEXT:    s_mov_b32 s19, 0xcf800000
-; GFX9-NEXT:    s_sub_u32 s4, 0, s14
+; GFX9-NEXT:    s_sub_u32 s4, 0, s12
 ; GFX9-NEXT:    v_mac_f32_e32 v0, s16, v1
 ; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
-; GFX9-NEXT:    s_subb_u32 s5, 0, s15
-; GFX9-NEXT:    v_mov_b32_e32 v6, 0
+; GFX9-NEXT:    s_subb_u32 s5, 0, s13
+; GFX9-NEXT:    v_mov_b32_e32 v7, 0
 ; GFX9-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x34
 ; GFX9-NEXT:    v_mul_f32_e32 v0, s17, v0
 ; GFX9-NEXT:    v_mul_f32_e32 v1, s18, v0
@@ -10645,42 +10641,42 @@
 ; GFX9-NEXT:    v_add_u32_e32 v2, v2, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v3, v0, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v5, v0, v2
-; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v2
-; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
-; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
-; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v4
+; GFX9-NEXT:    v_mul_hi_u32 v6, v0, v2
+; GFX9-NEXT:    v_mul_lo_u32 v8, v1, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v7, v3
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
+; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v6, vcc
+; GFX9-NEXT:    v_mul_hi_u32 v6, v1, v2
+; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v8, v3
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v6, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v6, v7, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
 ; GFX9-NEXT:    v_mov_b32_e32 v5, 0
 ; GFX9-NEXT:    v_add_co_u32_e64 v0, s[2:3], v0, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
 ; GFX9-NEXT:    v_mul_lo_u32 v4, s4, v2
-; GFX9-NEXT:    v_mul_hi_u32 v7, s4, v0
+; GFX9-NEXT:    v_mul_hi_u32 v6, s4, v0
 ; GFX9-NEXT:    v_mul_lo_u32 v8, s5, v0
-; GFX9-NEXT:    v_mul_lo_u32 v9, s4, v0
 ; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
-; GFX9-NEXT:    v_add_u32_e32 v4, v7, v4
+; GFX9-NEXT:    v_add_u32_e32 v4, v6, v4
+; GFX9-NEXT:    v_mul_lo_u32 v6, s4, v0
 ; GFX9-NEXT:    v_add_u32_e32 v4, v4, v8
-; GFX9-NEXT:    v_mul_lo_u32 v10, v0, v4
-; GFX9-NEXT:    v_mul_hi_u32 v11, v0, v9
-; GFX9-NEXT:    v_mul_hi_u32 v12, v0, v4
-; GFX9-NEXT:    v_mul_hi_u32 v8, v2, v9
-; GFX9-NEXT:    v_mul_lo_u32 v9, v2, v9
-; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
-; GFX9-NEXT:    v_mul_hi_u32 v7, v2, v4
-; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, 0, v12, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v2, v2, v4
+; GFX9-NEXT:    v_mul_lo_u32 v9, v0, v4
+; GFX9-NEXT:    v_mul_hi_u32 v11, v0, v4
+; GFX9-NEXT:    v_mul_hi_u32 v10, v0, v6
+; GFX9-NEXT:    v_mul_hi_u32 v12, v2, v6
+; GFX9-NEXT:    v_mul_lo_u32 v6, v2, v6
+; GFX9-NEXT:    v_mul_hi_u32 v8, v2, v4
 ; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v10, v9
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v11, v8, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v7, v6, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v8, v2
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v5, v4, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, 0, v11, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v2, v2, v4
+; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v9, v6
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v10, v12, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v8, v7, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v4, v2
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v5, v6, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e64 v1, vcc, v1, v4, s[2:3]
 ; GFX9-NEXT:    s_add_u32 s2, s8, s6
 ; GFX9-NEXT:    s_addc_u32 s3, s9, s6
@@ -10690,7 +10686,7 @@
 ; GFX9-NEXT:    v_mul_lo_u32 v2, s8, v1
 ; GFX9-NEXT:    v_mul_hi_u32 v3, s8, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v4, s8, v1
-; GFX9-NEXT:    v_mul_hi_u32 v7, s9, v1
+; GFX9-NEXT:    v_mul_hi_u32 v6, s9, v1
 ; GFX9-NEXT:    v_mul_lo_u32 v1, s9, v1
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
@@ -10699,151 +10695,151 @@
 ; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v4, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v7, v6, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v6, v7, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v5, v2, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v1, s14, v1
-; GFX9-NEXT:    v_mul_hi_u32 v2, s14, v0
-; GFX9-NEXT:    v_mul_lo_u32 v3, s15, v0
-; GFX9-NEXT:    v_mul_lo_u32 v0, s14, v0
+; GFX9-NEXT:    v_mul_lo_u32 v1, s12, v1
+; GFX9-NEXT:    v_mul_hi_u32 v2, s12, v0
+; GFX9-NEXT:    v_mul_lo_u32 v3, s13, v0
+; GFX9-NEXT:    v_mul_lo_u32 v0, s12, v0
 ; GFX9-NEXT:    v_add_u32_e32 v1, v2, v1
 ; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
 ; GFX9-NEXT:    v_sub_co_u32_e64 v0, s[0:1], s8, v0
 ; GFX9-NEXT:    v_sub_u32_e32 v2, s9, v1
-; GFX9-NEXT:    v_mov_b32_e32 v3, s15
+; GFX9-NEXT:    v_mov_b32_e32 v3, s13
 ; GFX9-NEXT:    v_subb_co_u32_e64 v2, vcc, v2, v3, s[0:1]
-; GFX9-NEXT:    v_subrev_co_u32_e64 v4, s[2:3], s14, v0
-; GFX9-NEXT:    v_subbrev_co_u32_e64 v7, vcc, 0, v2, s[2:3]
-; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s15, v7
+; GFX9-NEXT:    v_subrev_co_u32_e64 v4, s[2:3], s12, v0
+; GFX9-NEXT:    v_subbrev_co_u32_e64 v6, vcc, 0, v2, s[2:3]
+; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s13, v6
 ; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
-; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s14, v4
+; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s12, v4
 ; GFX9-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
-; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s15, v7
+; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s13, v6
 ; GFX9-NEXT:    v_cndmask_b32_e32 v8, v8, v9, vcc
 ; GFX9-NEXT:    v_subb_co_u32_e64 v2, vcc, v2, v3, s[2:3]
-; GFX9-NEXT:    v_subrev_co_u32_e32 v3, vcc, s14, v4
+; GFX9-NEXT:    v_subrev_co_u32_e32 v3, vcc, s12, v4
 ; GFX9-NEXT:    v_subbrev_co_u32_e32 v2, vcc, 0, v2, vcc
 ; GFX9-NEXT:    v_cmp_ne_u32_e64 s[2:3], 0, v8
-; GFX9-NEXT:    v_cndmask_b32_e64 v2, v7, v2, s[2:3]
-; GFX9-NEXT:    v_mov_b32_e32 v7, s9
-; GFX9-NEXT:    v_subb_co_u32_e64 v1, vcc, v7, v1, s[0:1]
-; GFX9-NEXT:    s_ashr_i32 s0, s13, 31
-; GFX9-NEXT:    s_add_u32 s8, s12, s0
+; GFX9-NEXT:    v_cndmask_b32_e64 v2, v6, v2, s[2:3]
+; GFX9-NEXT:    v_mov_b32_e32 v6, s9
+; GFX9-NEXT:    v_subb_co_u32_e64 v1, vcc, v6, v1, s[0:1]
+; GFX9-NEXT:    s_ashr_i32 s0, s15, 31
+; GFX9-NEXT:    s_add_u32 s8, s14, s0
 ; GFX9-NEXT:    s_mov_b32 s1, s0
-; GFX9-NEXT:    s_addc_u32 s9, s13, s0
+; GFX9-NEXT:    s_addc_u32 s9, s15, s0
 ; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[0:1]
-; GFX9-NEXT:    v_cvt_f32_u32_e32 v9, s8
-; GFX9-NEXT:    v_cvt_f32_u32_e32 v10, s9
-; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s15, v1
-; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
-; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s14, v0
+; GFX9-NEXT:    v_cvt_f32_u32_e32 v6, s8
+; GFX9-NEXT:    v_cvt_f32_u32_e32 v8, s9
+; GFX9-NEXT:    s_sub_u32 s7, 0, s8
+; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s13, v1
+; GFX9-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
+; GFX9-NEXT:    v_mac_f32_e32 v6, s16, v8
+; GFX9-NEXT:    v_rcp_f32_e32 v6, v6
+; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s12, v0
+; GFX9-NEXT:    s_subb_u32 s12, 0, s9
 ; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
-; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s15, v1
-; GFX9-NEXT:    v_mac_f32_e32 v9, s16, v10
-; GFX9-NEXT:    v_cndmask_b32_e32 v7, v7, v8, vcc
-; GFX9-NEXT:    v_rcp_f32_e32 v8, v9
-; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
-; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX9-NEXT:    v_mul_f32_e32 v6, s17, v6
+; GFX9-NEXT:    v_mul_f32_e32 v10, s18, v6
+; GFX9-NEXT:    v_trunc_f32_e32 v10, v10
+; GFX9-NEXT:    v_mac_f32_e32 v6, s19, v10
+; GFX9-NEXT:    v_cvt_u32_f32_e32 v6, v6
+; GFX9-NEXT:    v_cvt_u32_f32_e32 v10, v10
+; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s13, v1
+; GFX9-NEXT:    v_cndmask_b32_e32 v8, v9, v8, vcc
+; GFX9-NEXT:    v_mul_hi_u32 v11, s7, v6
+; GFX9-NEXT:    v_mul_lo_u32 v12, s7, v10
+; GFX9-NEXT:    v_mul_lo_u32 v13, s12, v6
+; GFX9-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v8
+; GFX9-NEXT:    v_cndmask_b32_e64 v1, v1, v2, s[0:1]
+; GFX9-NEXT:    v_add_u32_e32 v9, v11, v12
+; GFX9-NEXT:    v_mul_lo_u32 v11, s7, v6
+; GFX9-NEXT:    v_add_u32_e32 v9, v9, v13
+; GFX9-NEXT:    v_mul_lo_u32 v13, v6, v9
+; GFX9-NEXT:    v_mul_hi_u32 v12, v6, v9
+; GFX9-NEXT:    v_mul_hi_u32 v14, v6, v11
+; GFX9-NEXT:    v_mul_lo_u32 v8, v10, v11
 ; GFX9-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[2:3]
-; GFX9-NEXT:    v_mul_f32_e32 v3, s17, v8
-; GFX9-NEXT:    v_mul_f32_e32 v4, s18, v3
-; GFX9-NEXT:    v_trunc_f32_e32 v4, v4
-; GFX9-NEXT:    v_mac_f32_e32 v3, s19, v4
-; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
-; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v4
-; GFX9-NEXT:    s_sub_u32 s2, 0, s8
-; GFX9-NEXT:    s_subb_u32 s3, 0, s9
-; GFX9-NEXT:    v_mul_hi_u32 v7, s2, v3
-; GFX9-NEXT:    v_mul_lo_u32 v8, s2, v4
-; GFX9-NEXT:    v_mul_lo_u32 v9, s3, v3
-; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v2, s2, v3
-; GFX9-NEXT:    v_add_u32_e32 v7, v7, v8
-; GFX9-NEXT:    v_add_u32_e32 v7, v7, v9
-; GFX9-NEXT:    v_mul_lo_u32 v8, v3, v7
-; GFX9-NEXT:    v_mul_hi_u32 v9, v3, v2
-; GFX9-NEXT:    v_mul_hi_u32 v10, v3, v7
-; GFX9-NEXT:    v_mul_hi_u32 v11, v4, v7
-; GFX9-NEXT:    v_mul_lo_u32 v7, v4, v7
-; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v9, v8
-; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, 0, v10, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v10, v4, v2
-; GFX9-NEXT:    v_mul_hi_u32 v2, v4, v2
+; GFX9-NEXT:    v_mul_hi_u32 v11, v10, v11
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v14, v13
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v12, vcc
+; GFX9-NEXT:    v_mul_hi_u32 v12, v10, v9
+; GFX9-NEXT:    v_mul_lo_u32 v9, v10, v9
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v8, v3
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v4, v11, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v12, v7, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v9
+; GFX9-NEXT:    v_add_co_u32_e64 v3, s[2:3], v6, v3
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v5, v4, vcc
+; GFX9-NEXT:    v_addc_co_u32_e64 v6, vcc, v10, v4, s[2:3]
+; GFX9-NEXT:    v_mul_lo_u32 v8, s7, v6
+; GFX9-NEXT:    v_mul_hi_u32 v9, s7, v3
+; GFX9-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
+; GFX9-NEXT:    v_mul_lo_u32 v2, s12, v3
 ; GFX9-NEXT:    s_ashr_i32 s12, s11, 31
-; GFX9-NEXT:    s_mov_b32 s13, s12
-; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v10, v8
-; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v9, v2, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v11, v6, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v7
-; GFX9-NEXT:    v_add_co_u32_e64 v2, s[0:1], v3, v2
-; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v5, v8, vcc
-; GFX9-NEXT:    v_addc_co_u32_e64 v3, vcc, v4, v7, s[0:1]
-; GFX9-NEXT:    v_mul_lo_u32 v8, s2, v3
-; GFX9-NEXT:    v_mul_hi_u32 v9, s2, v2
-; GFX9-NEXT:    v_mul_lo_u32 v10, s3, v2
-; GFX9-NEXT:    v_mul_lo_u32 v11, s2, v2
-; GFX9-NEXT:    v_add_u32_e32 v4, v4, v7
 ; GFX9-NEXT:    v_add_u32_e32 v8, v9, v8
-; GFX9-NEXT:    v_add_u32_e32 v8, v8, v10
-; GFX9-NEXT:    v_mul_lo_u32 v12, v2, v8
-; GFX9-NEXT:    v_mul_hi_u32 v13, v2, v11
-; GFX9-NEXT:    v_mul_hi_u32 v14, v2, v8
-; GFX9-NEXT:    v_mul_hi_u32 v10, v3, v11
-; GFX9-NEXT:    v_mul_lo_u32 v11, v3, v11
-; GFX9-NEXT:    v_add_co_u32_e32 v12, vcc, v13, v12
-; GFX9-NEXT:    v_mul_hi_u32 v9, v3, v8
-; GFX9-NEXT:    v_addc_co_u32_e32 v13, vcc, 0, v14, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v3, v3, v8
+; GFX9-NEXT:    v_mul_lo_u32 v9, s7, v3
+; GFX9-NEXT:    v_add_u32_e32 v2, v8, v2
+; GFX9-NEXT:    v_mul_lo_u32 v11, v3, v2
+; GFX9-NEXT:    v_mul_hi_u32 v13, v3, v2
+; GFX9-NEXT:    v_mul_hi_u32 v12, v3, v9
+; GFX9-NEXT:    v_mul_hi_u32 v14, v6, v9
+; GFX9-NEXT:    v_mul_lo_u32 v9, v6, v9
+; GFX9-NEXT:    v_mul_hi_u32 v8, v6, v2
 ; GFX9-NEXT:    v_add_co_u32_e32 v11, vcc, v12, v11
-; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v13, v10, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v9, v6, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v10, v3
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v5, v8, vcc
-; GFX9-NEXT:    v_addc_co_u32_e64 v4, vcc, v4, v8, s[0:1]
+; GFX9-NEXT:    v_addc_co_u32_e32 v12, vcc, 0, v13, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v2, v6, v2
+; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v11, v9
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v12, v14, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v8, v7, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v6, v2
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v5, v8, vcc
+; GFX9-NEXT:    v_add_u32_e32 v4, v10, v4
 ; GFX9-NEXT:    s_add_u32 s0, s10, s12
-; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v3
+; GFX9-NEXT:    v_addc_co_u32_e64 v4, vcc, v4, v6, s[2:3]
+; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
+; GFX9-NEXT:    s_mov_b32 s13, s12
 ; GFX9-NEXT:    s_addc_u32 s1, s11, s12
 ; GFX9-NEXT:    s_xor_b64 s[10:11], s[0:1], s[12:13]
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v4, s10, v3
-; GFX9-NEXT:    v_mul_hi_u32 v7, s10, v2
-; GFX9-NEXT:    v_mul_hi_u32 v9, s10, v3
+; GFX9-NEXT:    v_mul_hi_u32 v6, s10, v2
+; GFX9-NEXT:    v_mul_hi_u32 v8, s10, v3
 ; GFX9-NEXT:    v_mul_hi_u32 v10, s11, v3
 ; GFX9-NEXT:    v_mul_lo_u32 v3, s11, v3
-; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v7, v4
-; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v9, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v9, s11, v2
+; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v6, v4
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v8, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v8, s11, v2
 ; GFX9-NEXT:    v_mul_hi_u32 v2, s11, v2
 ; GFX9-NEXT:    v_xor_b32_e32 v0, s6, v0
 ; GFX9-NEXT:    v_xor_b32_e32 v1, s6, v1
-; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v9, v4
-; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v7, v2, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v10, v6, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v8, v4
+; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v6, v2, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v10, v7, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v3
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v3, s8, v3
 ; GFX9-NEXT:    v_mul_hi_u32 v4, s8, v2
 ; GFX9-NEXT:    v_mul_lo_u32 v5, s9, v2
 ; GFX9-NEXT:    v_mul_lo_u32 v2, s8, v2
-; GFX9-NEXT:    v_mov_b32_e32 v8, s6
+; GFX9-NEXT:    v_mov_b32_e32 v9, s6
 ; GFX9-NEXT:    v_add_u32_e32 v3, v4, v3
 ; GFX9-NEXT:    v_add_u32_e32 v3, v3, v5
 ; GFX9-NEXT:    v_subrev_co_u32_e32 v0, vcc, s6, v0
 ; GFX9-NEXT:    v_sub_co_u32_e64 v2, s[0:1], s10, v2
 ; GFX9-NEXT:    v_sub_u32_e32 v4, s11, v3
 ; GFX9-NEXT:    v_mov_b32_e32 v5, s9
-; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v8, vcc
+; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v9, vcc
 ; GFX9-NEXT:    v_subb_co_u32_e64 v4, vcc, v4, v5, s[0:1]
-; GFX9-NEXT:    v_subrev_co_u32_e64 v7, s[2:3], s8, v2
+; GFX9-NEXT:    v_subrev_co_u32_e64 v6, s[2:3], s8, v2
 ; GFX9-NEXT:    v_subbrev_co_u32_e64 v8, vcc, 0, v4, s[2:3]
 ; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v8
 ; GFX9-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
-; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s8, v7
+; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s8, v6
 ; GFX9-NEXT:    v_cndmask_b32_e64 v10, 0, -1, vcc
 ; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v8
 ; GFX9-NEXT:    v_cndmask_b32_e32 v9, v9, v10, vcc
 ; GFX9-NEXT:    v_subb_co_u32_e64 v4, vcc, v4, v5, s[2:3]
-; GFX9-NEXT:    v_subrev_co_u32_e32 v5, vcc, s8, v7
+; GFX9-NEXT:    v_subrev_co_u32_e32 v5, vcc, s8, v6
 ; GFX9-NEXT:    v_subbrev_co_u32_e32 v4, vcc, 0, v4, vcc
 ; GFX9-NEXT:    v_cmp_ne_u32_e64 s[2:3], 0, v9
 ; GFX9-NEXT:    v_cndmask_b32_e64 v4, v8, v4, s[2:3]
@@ -10857,7 +10853,7 @@
 ; GFX9-NEXT:    v_cndmask_b32_e32 v8, v8, v9, vcc
 ; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v8
 ; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
-; GFX9-NEXT:    v_cndmask_b32_e64 v4, v7, v5, s[2:3]
+; GFX9-NEXT:    v_cndmask_b32_e64 v4, v6, v5, s[2:3]
 ; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
 ; GFX9-NEXT:    v_xor_b32_e32 v2, s12, v2
 ; GFX9-NEXT:    v_xor_b32_e32 v3, s12, v3
@@ -10865,7 +10861,7 @@
 ; GFX9-NEXT:    v_subrev_co_u32_e32 v2, vcc, s12, v2
 ; GFX9-NEXT:    v_subb_co_u32_e32 v3, vcc, v3, v4, vcc
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    global_store_dwordx4 v6, v[0:3], s[4:5]
+; GFX9-NEXT:    global_store_dwordx4 v7, v[0:3], s[4:5]
 ; GFX9-NEXT:    s_endpgm
   %shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y
   %r = srem <2 x i64> %x, %shl.y
diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
--- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
@@ -814,33 +814,33 @@
 ; GFX8-NEXT:    s_and_saveexec_b64 s[2:3], vcc
 ; GFX8-NEXT:    s_cbranch_execz BB4_2
 ; GFX8-NEXT:  ; %bb.1:
+; GFX8-NEXT:    s_bcnt1_i32_b64 s12, s[8:9]
+; GFX8-NEXT:    v_mov_b32_e32 v1, s12
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX8-NEXT:    s_mov_b32 s12, s6
-; GFX8-NEXT:    s_bcnt1_i32_b64 s6, s[8:9]
-; GFX8-NEXT:    v_mov_b32_e32 v1, s6
 ; GFX8-NEXT:    v_mul_hi_u32 v1, s0, v1
-; GFX8-NEXT:    s_mov_b32 s13, s7
-; GFX8-NEXT:    s_mul_i32 s7, s1, s6
-; GFX8-NEXT:    s_mul_i32 s6, s0, s6
-; GFX8-NEXT:    v_add_u32_e32 v2, vcc, s7, v1
-; GFX8-NEXT:    s_mov_b32 s15, 0xf000
-; GFX8-NEXT:    s_mov_b32 s14, -1
+; GFX8-NEXT:    s_mov_b32 s8, s6
+; GFX8-NEXT:    s_mul_i32 s6, s1, s12
+; GFX8-NEXT:    s_mov_b32 s11, 0xf000
+; GFX8-NEXT:    v_add_u32_e32 v2, vcc, s6, v1
+; GFX8-NEXT:    s_mul_i32 s6, s0, s12
+; GFX8-NEXT:    s_mov_b32 s10, -1
+; GFX8-NEXT:    s_mov_b32 s9, s7
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s6
 ; GFX8-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX8-NEXT:    buffer_atomic_add_x2 v[1:2], off, s[12:15], 0 glc
+; GFX8-NEXT:    buffer_atomic_add_x2 v[1:2], off, s[8:11], 0 glc
 ; GFX8-NEXT:    s_waitcnt vmcnt(0)
 ; GFX8-NEXT:    buffer_wbinvl1_vol
 ; GFX8-NEXT:  BB4_2:
 ; GFX8-NEXT:    s_or_b64 exec, exec, s[2:3]
-; GFX8-NEXT:    v_readfirstlane_b32 s2, v1
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX8-NEXT:    v_mul_lo_u32 v1, s1, v0
-; GFX8-NEXT:    v_mul_hi_u32 v3, s0, v0
+; GFX8-NEXT:    v_mul_lo_u32 v3, s1, v0
+; GFX8-NEXT:    v_mul_hi_u32 v4, s0, v0
 ; GFX8-NEXT:    v_mul_lo_u32 v0, s0, v0
-; GFX8-NEXT:    v_readfirstlane_b32 s1, v2
-; GFX8-NEXT:    v_mov_b32_e32 v2, s1
-; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v3, v1
-; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s2, v0
+; GFX8-NEXT:    v_readfirstlane_b32 s0, v2
+; GFX8-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v4, v3
+; GFX8-NEXT:    v_mov_b32_e32 v2, s0
+; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s1, v0
 ; GFX8-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX8-NEXT:    s_mov_b32 s6, -1
 ; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, v2, v1, vcc
@@ -1951,33 +1951,33 @@
 ; GFX8-NEXT:    s_and_saveexec_b64 s[2:3], vcc
 ; GFX8-NEXT:    s_cbranch_execz BB10_2
 ; GFX8-NEXT:  ; %bb.1:
+; GFX8-NEXT:    s_bcnt1_i32_b64 s12, s[8:9]
+; GFX8-NEXT:    v_mov_b32_e32 v1, s12
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX8-NEXT:    s_mov_b32 s12, s6
-; GFX8-NEXT:    s_bcnt1_i32_b64 s6, s[8:9]
-; GFX8-NEXT:    v_mov_b32_e32 v1, s6
 ; GFX8-NEXT:    v_mul_hi_u32 v1, s0, v1
-; GFX8-NEXT:    s_mov_b32 s13, s7
-; GFX8-NEXT:    s_mul_i32 s7, s1, s6
-; GFX8-NEXT:    s_mul_i32 s6, s0, s6
-; GFX8-NEXT:    v_add_u32_e32 v2, vcc, s7, v1
-; GFX8-NEXT:    s_mov_b32 s15, 0xf000
-; GFX8-NEXT:    s_mov_b32 s14, -1
+; GFX8-NEXT:    s_mov_b32 s8, s6
+; GFX8-NEXT:    s_mul_i32 s6, s1, s12
+; GFX8-NEXT:    s_mov_b32 s11, 0xf000
+; GFX8-NEXT:    v_add_u32_e32 v2, vcc, s6, v1
+; GFX8-NEXT:    s_mul_i32 s6, s0, s12
+; GFX8-NEXT:    s_mov_b32 s10, -1
+; GFX8-NEXT:    s_mov_b32 s9, s7
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s6
 ; GFX8-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX8-NEXT:    buffer_atomic_sub_x2 v[1:2], off, s[12:15], 0 glc
+; GFX8-NEXT:    buffer_atomic_sub_x2 v[1:2], off, s[8:11], 0 glc
 ; GFX8-NEXT:    s_waitcnt vmcnt(0)
 ; GFX8-NEXT:    buffer_wbinvl1_vol
 ; GFX8-NEXT:  BB10_2:
 ; GFX8-NEXT:    s_or_b64 exec, exec, s[2:3]
-; GFX8-NEXT:    v_readfirstlane_b32 s2, v1
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX8-NEXT:    v_mul_lo_u32 v1, s1, v0
-; GFX8-NEXT:    v_mul_hi_u32 v3, s0, v0
+; GFX8-NEXT:    v_mul_lo_u32 v3, s1, v0
+; GFX8-NEXT:    v_mul_hi_u32 v4, s0, v0
 ; GFX8-NEXT:    v_mul_lo_u32 v0, s0, v0
-; GFX8-NEXT:    v_readfirstlane_b32 s1, v2
-; GFX8-NEXT:    v_mov_b32_e32 v2, s1
-; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v3, v1
-; GFX8-NEXT:    v_sub_u32_e32 v0, vcc, s2, v0
+; GFX8-NEXT:    v_readfirstlane_b32 s0, v2
+; GFX8-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v4, v3
+; GFX8-NEXT:    v_mov_b32_e32 v2, s0
+; GFX8-NEXT:    v_sub_u32_e32 v0, vcc, s1, v0
 ; GFX8-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX8-NEXT:    s_mov_b32 s6, -1
 ; GFX8-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
--- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
@@ -966,12 +966,12 @@
 ; GFX8-NEXT:    s_bcnt1_i32_b64 s6, s[6:7]
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s6
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX8-NEXT:    v_mul_hi_u32 v1, s2, v1
+; GFX8-NEXT:    v_mul_hi_u32 v2, s2, v1
 ; GFX8-NEXT:    s_mul_i32 s7, s3, s6
 ; GFX8-NEXT:    s_mul_i32 s6, s2, s6
-; GFX8-NEXT:    v_mov_b32_e32 v3, local_var64@abs32@lo
-; GFX8-NEXT:    v_add_u32_e32 v2, vcc, s7, v1
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s6
+; GFX8-NEXT:    v_add_u32_e32 v2, vcc, s7, v2
+; GFX8-NEXT:    v_mov_b32_e32 v3, local_var64@abs32@lo
 ; GFX8-NEXT:    s_mov_b32 m0, -1
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NEXT:    ds_add_rtn_u64 v[1:2], v3, v[1:2]
@@ -979,14 +979,14 @@
 ; GFX8-NEXT:  BB5_2:
 ; GFX8-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX8-NEXT:    s_mov_b32 s4, s0
-; GFX8-NEXT:    v_readfirstlane_b32 s0, v1
-; GFX8-NEXT:    v_mul_lo_u32 v1, s3, v0
-; GFX8-NEXT:    v_mul_hi_u32 v3, s2, v0
+; GFX8-NEXT:    v_mul_lo_u32 v3, s3, v0
+; GFX8-NEXT:    v_mul_hi_u32 v4, s2, v0
 ; GFX8-NEXT:    v_mul_lo_u32 v0, s2, v0
+; GFX8-NEXT:    s_mov_b32 s4, s0
 ; GFX8-NEXT:    s_mov_b32 s5, s1
 ; GFX8-NEXT:    v_readfirstlane_b32 s1, v2
-; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v3, v1
+; GFX8-NEXT:    v_readfirstlane_b32 s0, v1
+; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v4, v3
 ; GFX8-NEXT:    v_mov_b32_e32 v2, s1
 ; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s0, v0
 ; GFX8-NEXT:    s_mov_b32 s7, 0xf000
@@ -2158,12 +2158,12 @@
 ; GFX8-NEXT:    s_bcnt1_i32_b64 s6, s[6:7]
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s6
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX8-NEXT:    v_mul_hi_u32 v1, s2, v1
+; GFX8-NEXT:    v_mul_hi_u32 v2, s2, v1
 ; GFX8-NEXT:    s_mul_i32 s7, s3, s6
 ; GFX8-NEXT:    s_mul_i32 s6, s2, s6
-; GFX8-NEXT:    v_mov_b32_e32 v3, local_var64@abs32@lo
-; GFX8-NEXT:    v_add_u32_e32 v2, vcc, s7, v1
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s6
+; GFX8-NEXT:    v_add_u32_e32 v2, vcc, s7, v2
+; GFX8-NEXT:    v_mov_b32_e32 v3, local_var64@abs32@lo
 ; GFX8-NEXT:    s_mov_b32 m0, -1
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NEXT:    ds_sub_rtn_u64 v[1:2], v3, v[1:2]
@@ -2171,14 +2171,14 @@
 ; GFX8-NEXT:  BB12_2:
 ; GFX8-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX8-NEXT:    s_mov_b32 s4, s0
-; GFX8-NEXT:    v_readfirstlane_b32 s0, v1
-; GFX8-NEXT:    v_mul_lo_u32 v1, s3, v0
-; GFX8-NEXT:    v_mul_hi_u32 v3, s2, v0
+; GFX8-NEXT:    v_mul_lo_u32 v3, s3, v0
+; GFX8-NEXT:    v_mul_hi_u32 v4, s2, v0
 ; GFX8-NEXT:    v_mul_lo_u32 v0, s2, v0
+; GFX8-NEXT:    s_mov_b32 s4, s0
 ; GFX8-NEXT:    s_mov_b32 s5, s1
 ; GFX8-NEXT:    v_readfirstlane_b32 s1, v2
-; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v3, v1
+; GFX8-NEXT:    v_readfirstlane_b32 s0, v1
+; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v4, v3
 ; GFX8-NEXT:    v_mov_b32_e32 v2, s1
 ; GFX8-NEXT:    v_sub_u32_e32 v0, vcc, s0, v0
 ; GFX8-NEXT:    s_mov_b32 s7, 0xf000
diff --git a/llvm/test/CodeGen/AMDGPU/bypass-div.ll b/llvm/test/CodeGen/AMDGPU/bypass-div.ll
--- a/llvm/test/CodeGen/AMDGPU/bypass-div.ll
+++ b/llvm/test/CodeGen/AMDGPU/bypass-div.ll
@@ -26,79 +26,79 @@
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v7, v5
 ; GFX9-NEXT:    v_sub_co_u32_e32 v8, vcc, 0, v4
 ; GFX9-NEXT:    v_subb_co_u32_e32 v9, vcc, 0, v5, vcc
-; GFX9-NEXT:    v_mov_b32_e32 v16, 0
+; GFX9-NEXT:    v_mov_b32_e32 v14, 0
 ; GFX9-NEXT:    v_mac_f32_e32 v6, 0x4f800000, v7
 ; GFX9-NEXT:    v_rcp_f32_e32 v6, v6
-; GFX9-NEXT:    v_mov_b32_e32 v15, 0
 ; GFX9-NEXT:    v_mul_f32_e32 v6, 0x5f7ffffc, v6
 ; GFX9-NEXT:    v_mul_f32_e32 v7, 0x2f800000, v6
 ; GFX9-NEXT:    v_trunc_f32_e32 v7, v7
 ; GFX9-NEXT:    v_mac_f32_e32 v6, 0xcf800000, v7
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v6, v6
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v7, v7
-; GFX9-NEXT:    v_mul_lo_u32 v10, v9, v6
-; GFX9-NEXT:    v_mul_hi_u32 v11, v8, v6
-; GFX9-NEXT:    v_mul_lo_u32 v12, v8, v7
+; GFX9-NEXT:    v_mul_lo_u32 v11, v9, v6
+; GFX9-NEXT:    v_mul_lo_u32 v10, v8, v7
+; GFX9-NEXT:    v_mul_hi_u32 v12, v8, v6
 ; GFX9-NEXT:    v_mul_lo_u32 v13, v8, v6
-; GFX9-NEXT:    v_add3_u32 v10, v11, v12, v10
+; GFX9-NEXT:    v_add3_u32 v10, v12, v10, v11
+; GFX9-NEXT:    v_mul_hi_u32 v11, v6, v13
 ; GFX9-NEXT:    v_mul_lo_u32 v12, v6, v10
-; GFX9-NEXT:    v_mul_hi_u32 v14, v6, v13
-; GFX9-NEXT:    v_mul_hi_u32 v11, v6, v10
-; GFX9-NEXT:    v_add_co_u32_e32 v12, vcc, v14, v12
-; GFX9-NEXT:    v_mul_lo_u32 v14, v7, v13
-; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, v16, v11, vcc
+; GFX9-NEXT:    v_mul_hi_u32 v15, v6, v10
+; GFX9-NEXT:    v_mul_lo_u32 v16, v7, v13
 ; GFX9-NEXT:    v_mul_hi_u32 v13, v7, v13
-; GFX9-NEXT:    v_add_co_u32_e32 v12, vcc, v12, v14
+; GFX9-NEXT:    v_add_co_u32_e32 v11, vcc, v11, v12
 ; GFX9-NEXT:    v_mul_hi_u32 v12, v7, v10
+; GFX9-NEXT:    v_addc_co_u32_e32 v15, vcc, v14, v15, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v10, v7, v10
-; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, v11, v13, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v12, vcc, v12, v15, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
+; GFX9-NEXT:    v_add_co_u32_e32 v11, vcc, v11, v16
+; GFX9-NEXT:    v_mov_b32_e32 v11, 0
+; GFX9-NEXT:    v_addc_co_u32_e32 v13, vcc, v15, v13, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v12, vcc, v12, v11, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v13, v10
 ; GFX9-NEXT:    v_add_co_u32_e64 v6, s[4:5], v6, v10
-; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, v16, v12, vcc
-; GFX9-NEXT:    v_addc_co_u32_e64 v10, vcc, v7, v11, s[4:5]
-; GFX9-NEXT:    v_mul_lo_u32 v12, v8, v10
-; GFX9-NEXT:    v_mul_hi_u32 v13, v8, v6
+; GFX9-NEXT:    v_addc_co_u32_e32 v12, vcc, v14, v12, vcc
+; GFX9-NEXT:    v_addc_co_u32_e64 v10, vcc, v7, v12, s[4:5]
+; GFX9-NEXT:    v_mul_lo_u32 v13, v8, v10
+; GFX9-NEXT:    v_mul_hi_u32 v15, v8, v6
 ; GFX9-NEXT:    v_mul_lo_u32 v9, v9, v6
 ; GFX9-NEXT:    v_mul_lo_u32 v8, v8, v6
-; GFX9-NEXT:    v_add_u32_e32 v7, v7, v11
-; GFX9-NEXT:    v_add3_u32 v9, v13, v12, v9
-; GFX9-NEXT:    v_mul_lo_u32 v12, v6, v9
-; GFX9-NEXT:    v_mul_hi_u32 v13, v6, v8
-; GFX9-NEXT:    v_mul_hi_u32 v14, v6, v9
-; GFX9-NEXT:    v_add_co_u32_e32 v12, vcc, v13, v12
-; GFX9-NEXT:    v_mul_hi_u32 v13, v10, v8
-; GFX9-NEXT:    v_mul_lo_u32 v8, v10, v8
-; GFX9-NEXT:    v_addc_co_u32_e32 v14, vcc, v16, v14, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v12, v8
-; GFX9-NEXT:    v_mul_hi_u32 v8, v10, v9
-; GFX9-NEXT:    v_mul_lo_u32 v9, v10, v9
-; GFX9-NEXT:    v_addc_co_u32_e32 v12, vcc, v14, v13, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v8, v15, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v12, v9
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v16, v8, vcc
-; GFX9-NEXT:    v_addc_co_u32_e64 v7, vcc, v7, v8, s[4:5]
-; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v9
+; GFX9-NEXT:    v_add_u32_e32 v7, v7, v12
+; GFX9-NEXT:    v_add3_u32 v9, v15, v13, v9
+; GFX9-NEXT:    v_mul_hi_u32 v15, v10, v8
+; GFX9-NEXT:    v_mul_lo_u32 v16, v10, v8
+; GFX9-NEXT:    v_mul_hi_u32 v8, v6, v8
+; GFX9-NEXT:    v_mul_lo_u32 v17, v6, v9
+; GFX9-NEXT:    v_mul_hi_u32 v13, v10, v9
+; GFX9-NEXT:    v_mul_lo_u32 v10, v10, v9
+; GFX9-NEXT:    v_mul_hi_u32 v9, v6, v9
+; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v8, v17
+; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v14, v9, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v8, v16
+; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v9, v15, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v13, v11, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v8, v10
+; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v14, v9, vcc
+; GFX9-NEXT:    v_addc_co_u32_e64 v7, vcc, v7, v9, s[4:5]
+; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v8
 ; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v7, vcc
 ; GFX9-NEXT:    v_ashrrev_i32_e32 v8, 31, v1
 ; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v0, v8
 ; GFX9-NEXT:    v_xor_b32_e32 v9, v9, v8
 ; GFX9-NEXT:    v_mul_lo_u32 v10, v9, v7
-; GFX9-NEXT:    v_mul_hi_u32 v11, v9, v6
-; GFX9-NEXT:    v_mul_hi_u32 v12, v9, v7
+; GFX9-NEXT:    v_mul_hi_u32 v12, v9, v6
+; GFX9-NEXT:    v_mul_hi_u32 v13, v9, v7
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v8, vcc
 ; GFX9-NEXT:    v_xor_b32_e32 v1, v1, v8
-; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
-; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, v16, v12, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v12, v1, v6
+; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v12, v10
+; GFX9-NEXT:    v_addc_co_u32_e32 v12, vcc, v14, v13, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v13, v1, v6
 ; GFX9-NEXT:    v_mul_hi_u32 v6, v1, v6
-; GFX9-NEXT:    v_mul_hi_u32 v13, v1, v7
+; GFX9-NEXT:    v_mul_hi_u32 v15, v1, v7
 ; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v7
-; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v10, v12
-; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v11, v6, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v13, v15, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v10, v13
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v12, v6, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v15, v11, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v7
-; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v16, v10, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v14, v10, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v10, v5, v6
 ; GFX9-NEXT:    v_mul_lo_u32 v11, v4, v7
 ; GFX9-NEXT:    v_mul_hi_u32 v12, v4, v6
@@ -204,16 +204,16 @@
 ; GFX9-NEXT:    v_add3_u32 v8, v10, v8, v9
 ; GFX9-NEXT:    v_mul_hi_u32 v9, v4, v11
 ; GFX9-NEXT:    v_mul_lo_u32 v10, v4, v8
-; GFX9-NEXT:    v_mul_hi_u32 v14, v4, v8
-; GFX9-NEXT:    v_mul_hi_u32 v15, v5, v8
-; GFX9-NEXT:    v_mul_lo_u32 v8, v5, v8
+; GFX9-NEXT:    v_mul_hi_u32 v15, v4, v8
+; GFX9-NEXT:    v_mul_hi_u32 v14, v5, v11
+; GFX9-NEXT:    v_mul_lo_u32 v11, v5, v11
 ; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v10
-; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v13, v14, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v14, v5, v11
-; GFX9-NEXT:    v_mul_hi_u32 v11, v5, v11
-; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v14
-; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v10, v11, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v15, v12, vcc
+; GFX9-NEXT:    v_mul_hi_u32 v10, v5, v8
+; GFX9-NEXT:    v_addc_co_u32_e32 v15, vcc, v13, v15, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v8, v5, v8
+; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v11
+; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v15, v14, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v10, v12, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v9, v8
 ; GFX9-NEXT:    v_add_co_u32_e64 v4, s[4:5], v4, v8
 ; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v13, v10, vcc
@@ -230,11 +230,11 @@
 ; GFX9-NEXT:    v_mul_hi_u32 v14, v8, v7
 ; GFX9-NEXT:    v_mul_lo_u32 v7, v8, v7
 ; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
-; GFX9-NEXT:    v_mul_hi_u32 v11, v8, v6
-; GFX9-NEXT:    v_mul_lo_u32 v6, v8, v6
+; GFX9-NEXT:    v_mul_lo_u32 v11, v8, v6
+; GFX9-NEXT:    v_mul_hi_u32 v6, v8, v6
 ; GFX9-NEXT:    v_addc_co_u32_e32 v15, vcc, v13, v15, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v10, v6
-; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v15, v11, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v10, v11
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v15, v6, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v14, v12, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v7
 ; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v13, v8, vcc
@@ -347,30 +347,30 @@
 ; GFX9-NEXT:    v_mov_b32_e32 v15, 0
 ; GFX9-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v6
 ; GFX9-NEXT:    v_rcp_f32_e32 v4, v4
-; GFX9-NEXT:    v_mov_b32_e32 v14, 0
+; GFX9-NEXT:    v_mov_b32_e32 v13, 0
 ; GFX9-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
 ; GFX9-NEXT:    v_mul_f32_e32 v6, 0x2f800000, v4
 ; GFX9-NEXT:    v_trunc_f32_e32 v6, v6
 ; GFX9-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v6
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v4
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v6, v6
-; GFX9-NEXT:    v_mul_lo_u32 v9, v8, v4
-; GFX9-NEXT:    v_mul_hi_u32 v10, v7, v4
-; GFX9-NEXT:    v_mul_lo_u32 v11, v7, v6
+; GFX9-NEXT:    v_mul_lo_u32 v10, v8, v4
+; GFX9-NEXT:    v_mul_lo_u32 v9, v7, v6
+; GFX9-NEXT:    v_mul_hi_u32 v11, v7, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v12, v7, v4
-; GFX9-NEXT:    v_add3_u32 v9, v10, v11, v9
+; GFX9-NEXT:    v_add3_u32 v9, v11, v9, v10
+; GFX9-NEXT:    v_mul_hi_u32 v10, v4, v12
 ; GFX9-NEXT:    v_mul_lo_u32 v11, v4, v9
-; GFX9-NEXT:    v_mul_hi_u32 v13, v4, v12
-; GFX9-NEXT:    v_mul_hi_u32 v10, v4, v9
-; GFX9-NEXT:    v_mul_hi_u32 v16, v6, v9
-; GFX9-NEXT:    v_mul_lo_u32 v9, v6, v9
-; GFX9-NEXT:    v_add_co_u32_e32 v11, vcc, v13, v11
-; GFX9-NEXT:    v_mul_lo_u32 v13, v6, v12
+; GFX9-NEXT:    v_mul_hi_u32 v14, v4, v9
+; GFX9-NEXT:    v_mul_lo_u32 v16, v6, v12
 ; GFX9-NEXT:    v_mul_hi_u32 v12, v6, v12
-; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v15, v10, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v11, vcc, v11, v13
-; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v10, v12, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, v16, v14, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v10, v11
+; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, v15, v14, vcc
+; GFX9-NEXT:    v_mul_hi_u32 v14, v6, v9
+; GFX9-NEXT:    v_mul_lo_u32 v9, v6, v9
+; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v10, v16
+; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v11, v12, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, v14, v13, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v10, v9
 ; GFX9-NEXT:    v_add_co_u32_e64 v4, s[4:5], v4, v9
 ; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v15, v11, vcc
@@ -384,15 +384,15 @@
 ; GFX9-NEXT:    v_mul_lo_u32 v11, v4, v8
 ; GFX9-NEXT:    v_mul_hi_u32 v12, v4, v7
 ; GFX9-NEXT:    v_mul_hi_u32 v16, v4, v8
-; GFX9-NEXT:    v_mul_hi_u32 v13, v9, v8
+; GFX9-NEXT:    v_mul_hi_u32 v14, v9, v8
 ; GFX9-NEXT:    v_mul_lo_u32 v8, v9, v8
 ; GFX9-NEXT:    v_add_co_u32_e32 v11, vcc, v12, v11
-; GFX9-NEXT:    v_mul_hi_u32 v12, v9, v7
-; GFX9-NEXT:    v_mul_lo_u32 v7, v9, v7
+; GFX9-NEXT:    v_mul_lo_u32 v12, v9, v7
+; GFX9-NEXT:    v_mul_hi_u32 v7, v9, v7
 ; GFX9-NEXT:    v_addc_co_u32_e32 v16, vcc, v15, v16, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v11, v7
-; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v16, v12, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v13, v14, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v11, v12
+; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v16, v7, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v14, v13, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v7, v8
 ; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v15, v9, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e64 v6, vcc, v6, v8, s[4:5]
@@ -414,7 +414,7 @@
 ; GFX9-NEXT:    v_mul_lo_u32 v6, v1, v6
 ; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v11
 ; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v10, v4, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v12, v14, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v12, v13, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v6
 ; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v15, v9, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v9, v5, v4
@@ -518,16 +518,16 @@
 ; GFX9-NEXT:    v_add3_u32 v8, v10, v8, v9
 ; GFX9-NEXT:    v_mul_hi_u32 v9, v4, v11
 ; GFX9-NEXT:    v_mul_lo_u32 v10, v4, v8
-; GFX9-NEXT:    v_mul_hi_u32 v14, v4, v8
-; GFX9-NEXT:    v_mul_hi_u32 v15, v5, v8
-; GFX9-NEXT:    v_mul_lo_u32 v8, v5, v8
+; GFX9-NEXT:    v_mul_hi_u32 v15, v4, v8
+; GFX9-NEXT:    v_mul_hi_u32 v14, v5, v11
+; GFX9-NEXT:    v_mul_lo_u32 v11, v5, v11
 ; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v10
-; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v13, v14, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v14, v5, v11
-; GFX9-NEXT:    v_mul_hi_u32 v11, v5, v11
-; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v14
-; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v10, v11, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v15, v12, vcc
+; GFX9-NEXT:    v_mul_hi_u32 v10, v5, v8
+; GFX9-NEXT:    v_addc_co_u32_e32 v15, vcc, v13, v15, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v8, v5, v8
+; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v11
+; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v15, v14, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v10, v12, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v9, v8
 ; GFX9-NEXT:    v_add_co_u32_e64 v4, s[4:5], v4, v8
 ; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v13, v10, vcc
@@ -544,11 +544,11 @@
 ; GFX9-NEXT:    v_mul_hi_u32 v14, v8, v7
 ; GFX9-NEXT:    v_mul_lo_u32 v7, v8, v7
 ; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
-; GFX9-NEXT:    v_mul_hi_u32 v11, v8, v6
-; GFX9-NEXT:    v_mul_lo_u32 v6, v8, v6
+; GFX9-NEXT:    v_mul_lo_u32 v11, v8, v6
+; GFX9-NEXT:    v_mul_hi_u32 v6, v8, v6
 ; GFX9-NEXT:    v_addc_co_u32_e32 v15, vcc, v13, v15, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v10, v6
-; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v15, v11, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v10, v11
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v15, v6, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v14, v12, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v7
 ; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v13, v8, vcc
@@ -781,79 +781,79 @@
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v7, v5
 ; GFX9-NEXT:    v_sub_co_u32_e32 v8, vcc, 0, v6
 ; GFX9-NEXT:    v_subb_co_u32_e32 v9, vcc, 0, v5, vcc
-; GFX9-NEXT:    v_mov_b32_e32 v16, 0
+; GFX9-NEXT:    v_mov_b32_e32 v14, 0
 ; GFX9-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v7
 ; GFX9-NEXT:    v_rcp_f32_e32 v4, v4
-; GFX9-NEXT:    v_mov_b32_e32 v15, 0
 ; GFX9-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
 ; GFX9-NEXT:    v_mul_f32_e32 v7, 0x2f800000, v4
 ; GFX9-NEXT:    v_trunc_f32_e32 v7, v7
 ; GFX9-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v7
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v4
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v7, v7
-; GFX9-NEXT:    v_mul_lo_u32 v10, v9, v4
-; GFX9-NEXT:    v_mul_hi_u32 v11, v8, v4
-; GFX9-NEXT:    v_mul_lo_u32 v12, v8, v7
+; GFX9-NEXT:    v_mul_lo_u32 v11, v9, v4
+; GFX9-NEXT:    v_mul_lo_u32 v10, v8, v7
+; GFX9-NEXT:    v_mul_hi_u32 v12, v8, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v13, v8, v4
-; GFX9-NEXT:    v_add3_u32 v10, v11, v12, v10
+; GFX9-NEXT:    v_add3_u32 v10, v12, v10, v11
+; GFX9-NEXT:    v_mul_hi_u32 v11, v4, v13
 ; GFX9-NEXT:    v_mul_lo_u32 v12, v4, v10
-; GFX9-NEXT:    v_mul_hi_u32 v14, v4, v13
-; GFX9-NEXT:    v_mul_hi_u32 v11, v4, v10
-; GFX9-NEXT:    v_add_co_u32_e32 v12, vcc, v14, v12
-; GFX9-NEXT:    v_mul_lo_u32 v14, v7, v13
-; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, v16, v11, vcc
+; GFX9-NEXT:    v_mul_hi_u32 v15, v4, v10
+; GFX9-NEXT:    v_mul_lo_u32 v16, v7, v13
 ; GFX9-NEXT:    v_mul_hi_u32 v13, v7, v13
-; GFX9-NEXT:    v_add_co_u32_e32 v12, vcc, v12, v14
+; GFX9-NEXT:    v_add_co_u32_e32 v11, vcc, v11, v12
 ; GFX9-NEXT:    v_mul_hi_u32 v12, v7, v10
+; GFX9-NEXT:    v_addc_co_u32_e32 v15, vcc, v14, v15, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v10, v7, v10
-; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, v11, v13, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v12, vcc, v12, v15, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
+; GFX9-NEXT:    v_add_co_u32_e32 v11, vcc, v11, v16
+; GFX9-NEXT:    v_mov_b32_e32 v11, 0
+; GFX9-NEXT:    v_addc_co_u32_e32 v13, vcc, v15, v13, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v12, vcc, v12, v11, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v13, v10
 ; GFX9-NEXT:    v_add_co_u32_e64 v4, s[4:5], v4, v10
-; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, v16, v12, vcc
-; GFX9-NEXT:    v_addc_co_u32_e64 v10, vcc, v7, v11, s[4:5]
-; GFX9-NEXT:    v_mul_lo_u32 v12, v8, v10
-; GFX9-NEXT:    v_mul_hi_u32 v13, v8, v4
+; GFX9-NEXT:    v_addc_co_u32_e32 v12, vcc, v14, v12, vcc
+; GFX9-NEXT:    v_addc_co_u32_e64 v10, vcc, v7, v12, s[4:5]
+; GFX9-NEXT:    v_mul_lo_u32 v13, v8, v10
+; GFX9-NEXT:    v_mul_hi_u32 v15, v8, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v9, v9, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v8, v8, v4
-; GFX9-NEXT:    v_add_u32_e32 v7, v7, v11
-; GFX9-NEXT:    v_add3_u32 v9, v13, v12, v9
-; GFX9-NEXT:    v_mul_lo_u32 v12, v4, v9
-; GFX9-NEXT:    v_mul_hi_u32 v13, v4, v8
-; GFX9-NEXT:    v_mul_hi_u32 v14, v4, v9
-; GFX9-NEXT:    v_add_co_u32_e32 v12, vcc, v13, v12
-; GFX9-NEXT:    v_mul_hi_u32 v13, v10, v8
-; GFX9-NEXT:    v_mul_lo_u32 v8, v10, v8
-; GFX9-NEXT:    v_addc_co_u32_e32 v14, vcc, v16, v14, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v12, v8
-; GFX9-NEXT:    v_mul_hi_u32 v8, v10, v9
-; GFX9-NEXT:    v_mul_lo_u32 v9, v10, v9
-; GFX9-NEXT:    v_addc_co_u32_e32 v12, vcc, v14, v13, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v8, v15, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v12, v9
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v16, v8, vcc
-; GFX9-NEXT:    v_addc_co_u32_e64 v7, vcc, v7, v8, s[4:5]
-; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v9
+; GFX9-NEXT:    v_add_u32_e32 v7, v7, v12
+; GFX9-NEXT:    v_add3_u32 v9, v15, v13, v9
+; GFX9-NEXT:    v_mul_hi_u32 v15, v10, v8
+; GFX9-NEXT:    v_mul_lo_u32 v16, v10, v8
+; GFX9-NEXT:    v_mul_hi_u32 v8, v4, v8
+; GFX9-NEXT:    v_mul_lo_u32 v17, v4, v9
+; GFX9-NEXT:    v_mul_hi_u32 v13, v10, v9
+; GFX9-NEXT:    v_mul_lo_u32 v10, v10, v9
+; GFX9-NEXT:    v_mul_hi_u32 v9, v4, v9
+; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v8, v17
+; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v14, v9, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v8, v16
+; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v9, v15, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v13, v11, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v8, v10
+; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v14, v9, vcc
+; GFX9-NEXT:    v_addc_co_u32_e64 v7, vcc, v7, v9, s[4:5]
+; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v8
 ; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v7, vcc
 ; GFX9-NEXT:    v_ashrrev_i32_e32 v8, 31, v1
 ; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v0, v8
 ; GFX9-NEXT:    v_xor_b32_e32 v9, v9, v8
 ; GFX9-NEXT:    v_mul_lo_u32 v10, v9, v7
-; GFX9-NEXT:    v_mul_hi_u32 v11, v9, v4
-; GFX9-NEXT:    v_mul_hi_u32 v12, v9, v7
+; GFX9-NEXT:    v_mul_hi_u32 v12, v9, v4
+; GFX9-NEXT:    v_mul_hi_u32 v13, v9, v7
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v8, vcc
 ; GFX9-NEXT:    v_xor_b32_e32 v1, v1, v8
-; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
-; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, v16, v12, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v12, v1, v4
+; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v12, v10
+; GFX9-NEXT:    v_addc_co_u32_e32 v12, vcc, v14, v13, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v13, v1, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GFX9-NEXT:    v_mul_hi_u32 v13, v1, v7
+; GFX9-NEXT:    v_mul_hi_u32 v15, v1, v7
 ; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v7
-; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v10, v12
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v11, v4, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v13, v15, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v10, v13
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v12, v4, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v15, v11, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v7
-; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v16, v10, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v14, v10, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v10, v5, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v11, v6, v7
 ; GFX9-NEXT:    v_mul_hi_u32 v12, v6, v4
@@ -979,16 +979,16 @@
 ; GFX9-NEXT:    v_add3_u32 v8, v10, v8, v9
 ; GFX9-NEXT:    v_mul_hi_u32 v9, v4, v11
 ; GFX9-NEXT:    v_mul_lo_u32 v10, v4, v8
-; GFX9-NEXT:    v_mul_hi_u32 v14, v4, v8
-; GFX9-NEXT:    v_mul_hi_u32 v15, v5, v8
-; GFX9-NEXT:    v_mul_lo_u32 v8, v5, v8
+; GFX9-NEXT:    v_mul_hi_u32 v15, v4, v8
+; GFX9-NEXT:    v_mul_hi_u32 v14, v5, v11
+; GFX9-NEXT:    v_mul_lo_u32 v11, v5, v11
 ; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v10
-; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v13, v14, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v14, v5, v11
-; GFX9-NEXT:    v_mul_hi_u32 v11, v5, v11
-; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v14
-; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v10, v11, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v15, v12, vcc
+; GFX9-NEXT:    v_mul_hi_u32 v10, v5, v8
+; GFX9-NEXT:    v_addc_co_u32_e32 v15, vcc, v13, v15, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v8, v5, v8
+; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v11
+; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v15, v14, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v10, v12, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v9, v8
 ; GFX9-NEXT:    v_add_co_u32_e64 v4, s[4:5], v4, v8
 ; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v13, v10, vcc
@@ -1005,11 +1005,11 @@
 ; GFX9-NEXT:    v_mul_hi_u32 v14, v8, v7
 ; GFX9-NEXT:    v_mul_lo_u32 v7, v8, v7
 ; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
-; GFX9-NEXT:    v_mul_hi_u32 v11, v8, v6
-; GFX9-NEXT:    v_mul_lo_u32 v6, v8, v6
+; GFX9-NEXT:    v_mul_lo_u32 v11, v8, v6
+; GFX9-NEXT:    v_mul_hi_u32 v6, v8, v6
 ; GFX9-NEXT:    v_addc_co_u32_e32 v15, vcc, v13, v15, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v10, v6
-; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v15, v11, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v10, v11
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v15, v6, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v14, v12, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v7
 ; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v13, v8, vcc
diff --git a/llvm/test/CodeGen/AMDGPU/ds_write2.ll b/llvm/test/CodeGen/AMDGPU/ds_write2.ll
--- a/llvm/test/CodeGen/AMDGPU/ds_write2.ll
+++ b/llvm/test/CodeGen/AMDGPU/ds_write2.ll
@@ -969,10 +969,10 @@
 ; CI-NEXT:    s_waitcnt lgkmcnt(0)
 ; CI-NEXT:    v_mov_b32_e32 v1, s0
 ; CI-NEXT:    v_mov_b32_e32 v2, s1
-; CI-NEXT:    ds_write2_b32 v0, v1, v2 offset1:1
 ; CI-NEXT:    v_mov_b32_e32 v3, s2
-; CI-NEXT:    v_mov_b32_e32 v1, s3
-; CI-NEXT:    ds_write2_b32 v0, v3, v1 offset0:2 offset1:3
+; CI-NEXT:    v_mov_b32_e32 v4, s3
+; CI-NEXT:    ds_write2_b32 v0, v1, v2 offset1:1
+; CI-NEXT:    ds_write2_b32 v0, v3, v4 offset0:2 offset1:3
 ; CI-NEXT:    s_endpgm
 ;
 ; GFX9-ALIGNED-LABEL: simple_write2_v4f32_superreg_align4:
diff --git a/llvm/test/CodeGen/AMDGPU/idot2.ll b/llvm/test/CodeGen/AMDGPU/idot2.ll
--- a/llvm/test/CodeGen/AMDGPU/idot2.ll
+++ b/llvm/test/CodeGen/AMDGPU/idot2.ll
@@ -163,7 +163,6 @@
 ; GFX7-NEXT:    buffer_load_dword v2, v[0:1], s[8:11], 0 addr64
 ; GFX7-NEXT:    s_mov_b64 s[8:9], s[6:7]
 ; GFX7-NEXT:    buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
-; GFX7-NEXT:    s_load_dword s5, s[0:1], 0x0
 ; GFX7-NEXT:    s_mov_b32 s4, 0xffff
 ; GFX7-NEXT:    s_mov_b32 s2, -1
 ; GFX7-NEXT:    s_waitcnt vmcnt(1)
@@ -172,10 +171,11 @@
 ; GFX7-NEXT:    s_waitcnt vmcnt(0)
 ; GFX7-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
 ; GFX7-NEXT:    v_and_b32_e32 v0, s4, v0
+; GFX7-NEXT:    s_load_dword s4, s[0:1], 0x0
 ; GFX7-NEXT:    v_mul_u32_u24_e32 v0, v0, v2
 ; GFX7-NEXT:    v_mad_u32_u24 v0, v3, v1, v0
 ; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX7-NEXT:    v_add_i32_e32 v0, vcc, s5, v0
+; GFX7-NEXT:    v_add_i32_e32 v0, vcc, s4, v0
 ; GFX7-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX7-NEXT:    s_endpgm
 ;
@@ -1702,7 +1702,6 @@
 ; GFX7-NEXT:    buffer_load_dword v2, v[0:1], s[8:11], 0 addr64
 ; GFX7-NEXT:    s_mov_b64 s[8:9], s[6:7]
 ; GFX7-NEXT:    buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
-; GFX7-NEXT:    s_load_dword s5, s[0:1], 0x0
 ; GFX7-NEXT:    s_mov_b32 s4, 0xffff
 ; GFX7-NEXT:    s_mov_b32 s2, -1
 ; GFX7-NEXT:    s_waitcnt vmcnt(1)
@@ -1711,8 +1710,9 @@
 ; GFX7-NEXT:    s_waitcnt vmcnt(0)
 ; GFX7-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
 ; GFX7-NEXT:    v_and_b32_e32 v0, s4, v0
+; GFX7-NEXT:    s_load_dword s4, s[0:1], 0x0
 ; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX7-NEXT:    v_mad_u32_u24 v1, v3, v1, s5
+; GFX7-NEXT:    v_mad_u32_u24 v1, v3, v1, s4
 ; GFX7-NEXT:    v_mad_u32_u24 v0, v0, v2, v1
 ; GFX7-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
 ; GFX7-NEXT:    buffer_store_dword v0, off, s[0:3], 0
diff --git a/llvm/test/CodeGen/AMDGPU/idot8s.ll b/llvm/test/CodeGen/AMDGPU/idot8s.ll
--- a/llvm/test/CodeGen/AMDGPU/idot8s.ll
+++ b/llvm/test/CodeGen/AMDGPU/idot8s.ll
@@ -404,37 +404,37 @@
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s4, v2
 ; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT:    flat_load_dword v3, v[0:1]
-; GFX8-NEXT:    v_mov_b32_e32 v1, s7
-; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s6, v2
-; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT:    flat_load_dword v2, v[0:1]
+; GFX8-NEXT:    v_mov_b32_e32 v3, s7
+; GFX8-NEXT:    v_add_u32_e32 v2, vcc, s6, v2
+; GFX8-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; GFX8-NEXT:    flat_load_dword v4, v[0:1]
+; GFX8-NEXT:    flat_load_dword v2, v[2:3]
 ; GFX8-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s1
-; GFX8-NEXT:    flat_load_ushort v4, v[0:1]
+; GFX8-NEXT:    flat_load_ushort v3, v[0:1]
 ; GFX8-NEXT:    s_mov_b32 s9, SCRATCH_RSRC_DWORD1
 ; GFX8-NEXT:    s_mov_b32 s10, -1
 ; GFX8-NEXT:    s_mov_b32 s11, 0xe80000
 ; GFX8-NEXT:    s_add_u32 s8, s8, s3
 ; GFX8-NEXT:    s_addc_u32 s9, s9, 0
 ; GFX8-NEXT:    s_waitcnt vmcnt(2)
-; GFX8-NEXT:    v_lshrrev_b32_e32 v10, 4, v3
-; GFX8-NEXT:    v_lshlrev_b16_e32 v16, 12, v3
-; GFX8-NEXT:    v_lshrrev_b32_e32 v6, 28, v3
-; GFX8-NEXT:    v_lshrrev_b32_e32 v7, 20, v3
+; GFX8-NEXT:    v_lshrrev_b32_e32 v10, 4, v4
 ; GFX8-NEXT:    s_waitcnt vmcnt(1)
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v15, 4, v2
+; GFX8-NEXT:    v_lshlrev_b16_e32 v16, 12, v4
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v17, 12, v2
-; GFX8-NEXT:    v_lshrrev_b32_e32 v8, 12, v3
-; GFX8-NEXT:    v_lshrrev_b32_e32 v9, 8, v3
+; GFX8-NEXT:    v_lshrrev_b32_e32 v6, 28, v4
+; GFX8-NEXT:    v_lshrrev_b32_e32 v7, 20, v4
+; GFX8-NEXT:    v_lshrrev_b32_e32 v8, 12, v4
+; GFX8-NEXT:    v_lshrrev_b32_e32 v9, 8, v4
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v11, 28, v2
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v12, 20, v2
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v13, 12, v2
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v14, 8, v2
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v10, 12, v10
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v15, 12, v15
-; GFX8-NEXT:    v_lshlrev_b16_sdwa v18, v5, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT:    v_lshlrev_b16_sdwa v3, v5, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+; GFX8-NEXT:    v_lshlrev_b16_sdwa v18, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT:    v_lshlrev_b16_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
 ; GFX8-NEXT:    v_lshlrev_b16_sdwa v19, v5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
 ; GFX8-NEXT:    v_lshlrev_b16_sdwa v2, v5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v5, 12, v16
@@ -444,31 +444,31 @@
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v10, 12, v10
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v15, 12, v15
 ; GFX8-NEXT:    s_waitcnt vmcnt(0)
-; GFX8-NEXT:    v_mad_u16 v4, v5, v16, v4
+; GFX8-NEXT:    v_mad_u16 v3, v5, v16, v3
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v8, 12, v8
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v13, 12, v13
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v9, 12, v9
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v14, 12, v14
-; GFX8-NEXT:    v_mad_u16 v4, v10, v15, v4
+; GFX8-NEXT:    v_mad_u16 v3, v10, v15, v3
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v8, 12, v8
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v13, 12, v13
-; GFX8-NEXT:    v_mad_u16 v4, v9, v14, v4
+; GFX8-NEXT:    v_mad_u16 v3, v9, v14, v3
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v7, 12, v7
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v12, 12, v12
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v17, 12, v18
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v18, 12, v19
-; GFX8-NEXT:    v_mad_u16 v4, v8, v13, v4
+; GFX8-NEXT:    v_mad_u16 v3, v8, v13, v3
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v7, 12, v7
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v12, 12, v12
-; GFX8-NEXT:    v_mad_u16 v4, v17, v18, v4
+; GFX8-NEXT:    v_mad_u16 v3, v17, v18, v3
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v6, 12, v6
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v11, 12, v11
-; GFX8-NEXT:    v_ashrrev_i16_e32 v3, 12, v3
+; GFX8-NEXT:    v_ashrrev_i16_e32 v4, 12, v4
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v2, 12, v2
-; GFX8-NEXT:    v_mad_u16 v4, v7, v12, v4
+; GFX8-NEXT:    v_mad_u16 v3, v7, v12, v3
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v6, 12, v6
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v11, 12, v11
-; GFX8-NEXT:    v_mad_u16 v2, v3, v2, v4
+; GFX8-NEXT:    v_mad_u16 v2, v4, v2, v3
 ; GFX8-NEXT:    v_mad_u16 v2, v6, v11, v2
 ; GFX8-NEXT:    flat_store_short v[0:1], v2
 ; GFX8-NEXT:    s_endpgm
@@ -978,37 +978,37 @@
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s4, v2
 ; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT:    flat_load_dword v3, v[0:1]
-; GFX8-NEXT:    v_mov_b32_e32 v1, s7
-; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s6, v2
-; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT:    flat_load_dword v2, v[0:1]
+; GFX8-NEXT:    v_mov_b32_e32 v3, s7
+; GFX8-NEXT:    v_add_u32_e32 v2, vcc, s6, v2
+; GFX8-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; GFX8-NEXT:    flat_load_dword v4, v[0:1]
+; GFX8-NEXT:    flat_load_dword v2, v[2:3]
 ; GFX8-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s1
-; GFX8-NEXT:    flat_load_ubyte v4, v[0:1]
+; GFX8-NEXT:    flat_load_ubyte v3, v[0:1]
 ; GFX8-NEXT:    s_mov_b32 s9, SCRATCH_RSRC_DWORD1
 ; GFX8-NEXT:    s_mov_b32 s10, -1
 ; GFX8-NEXT:    s_mov_b32 s11, 0xe80000
 ; GFX8-NEXT:    s_add_u32 s8, s8, s3
 ; GFX8-NEXT:    s_addc_u32 s9, s9, 0
 ; GFX8-NEXT:    s_waitcnt vmcnt(2)
-; GFX8-NEXT:    v_lshrrev_b32_e32 v10, 4, v3
-; GFX8-NEXT:    v_lshlrev_b16_e32 v16, 12, v3
-; GFX8-NEXT:    v_lshrrev_b32_e32 v6, 28, v3
-; GFX8-NEXT:    v_lshrrev_b32_e32 v7, 20, v3
+; GFX8-NEXT:    v_lshrrev_b32_e32 v10, 4, v4
 ; GFX8-NEXT:    s_waitcnt vmcnt(1)
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v15, 4, v2
+; GFX8-NEXT:    v_lshlrev_b16_e32 v16, 12, v4
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v17, 12, v2
-; GFX8-NEXT:    v_lshrrev_b32_e32 v8, 12, v3
-; GFX8-NEXT:    v_lshrrev_b32_e32 v9, 8, v3
+; GFX8-NEXT:    v_lshrrev_b32_e32 v6, 28, v4
+; GFX8-NEXT:    v_lshrrev_b32_e32 v7, 20, v4
+; GFX8-NEXT:    v_lshrrev_b32_e32 v8, 12, v4
+; GFX8-NEXT:    v_lshrrev_b32_e32 v9, 8, v4
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v11, 28, v2
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v12, 20, v2
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v13, 12, v2
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v14, 8, v2
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v10, 12, v10
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v15, 12, v15
-; GFX8-NEXT:    v_lshlrev_b16_sdwa v18, v5, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT:    v_lshlrev_b16_sdwa v3, v5, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+; GFX8-NEXT:    v_lshlrev_b16_sdwa v18, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT:    v_lshlrev_b16_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
 ; GFX8-NEXT:    v_lshlrev_b16_sdwa v19, v5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
 ; GFX8-NEXT:    v_lshlrev_b16_sdwa v2, v5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v5, 12, v16
@@ -1018,31 +1018,31 @@
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v10, 12, v10
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v15, 12, v15
 ; GFX8-NEXT:    s_waitcnt vmcnt(0)
-; GFX8-NEXT:    v_mad_u16 v4, v5, v16, v4
+; GFX8-NEXT:    v_mad_u16 v3, v5, v16, v3
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v8, 12, v8
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v13, 12, v13
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v9, 12, v9
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v14, 12, v14
-; GFX8-NEXT:    v_mad_u16 v4, v10, v15, v4
+; GFX8-NEXT:    v_mad_u16 v3, v10, v15, v3
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v8, 12, v8
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v13, 12, v13
-; GFX8-NEXT:    v_mad_u16 v4, v9, v14, v4
+; GFX8-NEXT:    v_mad_u16 v3, v9, v14, v3
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v7, 12, v7
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v12, 12, v12
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v17, 12, v18
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v18, 12, v19
-; GFX8-NEXT:    v_mad_u16 v4, v8, v13, v4
+; GFX8-NEXT:    v_mad_u16 v3, v8, v13, v3
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v7, 12, v7
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v12, 12, v12
-; GFX8-NEXT:    v_mad_u16 v4, v17, v18, v4
+; GFX8-NEXT:    v_mad_u16 v3, v17, v18, v3
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v6, 12, v6
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v11, 12, v11
-; GFX8-NEXT:    v_ashrrev_i16_e32 v3, 12, v3
+; GFX8-NEXT:    v_ashrrev_i16_e32 v4, 12, v4
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v2, 12, v2
-; GFX8-NEXT:    v_mad_u16 v4, v7, v12, v4
+; GFX8-NEXT:    v_mad_u16 v3, v7, v12, v3
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v6, 12, v6
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v11, 12, v11
-; GFX8-NEXT:    v_mad_u16 v2, v3, v2, v4
+; GFX8-NEXT:    v_mad_u16 v2, v4, v2, v3
 ; GFX8-NEXT:    v_mad_u16 v2, v6, v11, v2
 ; GFX8-NEXT:    flat_store_byte v[0:1], v2
 ; GFX8-NEXT:    s_endpgm
@@ -2278,47 +2278,47 @@
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s4, v2
 ; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT:    flat_load_dword v3, v[0:1]
-; GFX8-NEXT:    v_mov_b32_e32 v1, s7
-; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s6, v2
-; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT:    flat_load_dword v2, v[0:1]
+; GFX8-NEXT:    v_mov_b32_e32 v3, s7
+; GFX8-NEXT:    v_add_u32_e32 v2, vcc, s6, v2
+; GFX8-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; GFX8-NEXT:    flat_load_dword v4, v[0:1]
+; GFX8-NEXT:    flat_load_dword v2, v[2:3]
 ; GFX8-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s1
-; GFX8-NEXT:    flat_load_ushort v4, v[0:1]
+; GFX8-NEXT:    flat_load_ushort v3, v[0:1]
 ; GFX8-NEXT:    s_mov_b32 s9, SCRATCH_RSRC_DWORD1
 ; GFX8-NEXT:    s_mov_b32 s10, -1
 ; GFX8-NEXT:    s_mov_b32 s11, 0xe80000
 ; GFX8-NEXT:    s_add_u32 s8, s8, s3
 ; GFX8-NEXT:    s_addc_u32 s9, s9, 0
 ; GFX8-NEXT:    s_waitcnt vmcnt(2)
-; GFX8-NEXT:    v_lshrrev_b32_e32 v6, 4, v3
-; GFX8-NEXT:    v_lshrrev_b32_e32 v7, 8, v3
-; GFX8-NEXT:    v_lshrrev_b32_e32 v8, 12, v3
-; GFX8-NEXT:    v_lshrrev_b32_e32 v9, 20, v3
-; GFX8-NEXT:    v_lshrrev_b32_e32 v10, 28, v3
+; GFX8-NEXT:    v_lshrrev_b32_e32 v6, 4, v4
+; GFX8-NEXT:    v_lshrrev_b32_e32 v7, 8, v4
+; GFX8-NEXT:    v_lshrrev_b32_e32 v8, 12, v4
+; GFX8-NEXT:    v_lshrrev_b32_e32 v9, 20, v4
+; GFX8-NEXT:    v_lshrrev_b32_e32 v10, 28, v4
 ; GFX8-NEXT:    s_waitcnt vmcnt(1)
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v11, 4, v2
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v12, 8, v2
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v13, 12, v2
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v14, 20, v2
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v15, 28, v2
-; GFX8-NEXT:    v_lshlrev_b16_sdwa v16, v5, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-; GFX8-NEXT:    v_lshlrev_b16_sdwa v17, v5, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT:    v_lshlrev_b16_sdwa v16, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+; GFX8-NEXT:    v_lshlrev_b16_sdwa v17, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
 ; GFX8-NEXT:    v_lshlrev_b16_sdwa v18, v5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
 ; GFX8-NEXT:    v_lshlrev_b16_sdwa v5, v5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT:    v_lshlrev_b16_e32 v3, 12, v3
+; GFX8-NEXT:    v_lshlrev_b16_e32 v4, 12, v4
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v2, 12, v2
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v6, 12, v6
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v11, 12, v11
-; GFX8-NEXT:    v_ashrrev_i16_e32 v3, 12, v3
+; GFX8-NEXT:    v_ashrrev_i16_e32 v4, 12, v4
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v2, 12, v2
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v7, 12, v7
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v12, 12, v12
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v6, 12, v6
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v11, 12, v11
 ; GFX8-NEXT:    s_waitcnt vmcnt(0)
-; GFX8-NEXT:    v_mad_u16 v2, v3, v2, v4
+; GFX8-NEXT:    v_mad_u16 v2, v4, v2, v3
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v8, 12, v8
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v13, 12, v13
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v7, 12, v7
@@ -2910,98 +2910,98 @@
 ; GFX8-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
 ; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
-; GFX8-NEXT:    v_mov_b32_e32 v5, 12
 ; GFX8-NEXT:    s_mov_b32 s8, SCRATCH_RSRC_DWORD0
+; GFX8-NEXT:    s_mov_b32 s9, SCRATCH_RSRC_DWORD1
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s4, v2
 ; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT:    flat_load_dword v3, v[0:1]
-; GFX8-NEXT:    v_mov_b32_e32 v1, s7
-; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s6, v2
-; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT:    flat_load_dword v2, v[0:1]
+; GFX8-NEXT:    v_mov_b32_e32 v3, s7
+; GFX8-NEXT:    v_add_u32_e32 v2, vcc, s6, v2
+; GFX8-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; GFX8-NEXT:    flat_load_dword v4, v[0:1]
+; GFX8-NEXT:    flat_load_dword v2, v[2:3]
 ; GFX8-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s1
-; GFX8-NEXT:    flat_load_ubyte v4, v[0:1]
-; GFX8-NEXT:    s_mov_b32 s9, SCRATCH_RSRC_DWORD1
+; GFX8-NEXT:    flat_load_ubyte v5, v[0:1]
+; GFX8-NEXT:    v_mov_b32_e32 v3, 12
 ; GFX8-NEXT:    s_mov_b32 s10, -1
 ; GFX8-NEXT:    s_mov_b32 s11, 0xe80000
 ; GFX8-NEXT:    s_add_u32 s8, s8, s3
 ; GFX8-NEXT:    s_addc_u32 s9, s9, 0
 ; GFX8-NEXT:    s_waitcnt vmcnt(2)
-; GFX8-NEXT:    v_lshrrev_b32_e32 v7, 28, v3
-; GFX8-NEXT:    v_lshrrev_b32_e32 v8, 12, v3
-; GFX8-NEXT:    v_lshrrev_b32_e32 v9, 8, v3
-; GFX8-NEXT:    v_lshrrev_b32_e32 v6, 20, v3
+; GFX8-NEXT:    v_lshrrev_b32_e32 v6, 20, v4
+; GFX8-NEXT:    v_lshrrev_b32_e32 v7, 28, v4
 ; GFX8-NEXT:    s_waitcnt vmcnt(1)
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v12, 28, v2
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v13, 12, v2
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v14, 8, v2
-; GFX8-NEXT:    v_lshrrev_b32_e32 v10, 4, v3
-; GFX8-NEXT:    v_lshrrev_b32_e32 v11, 20, v2
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v15, 4, v2
-; GFX8-NEXT:    v_lshlrev_b16_e32 v16, 12, v3
-; GFX8-NEXT:    v_lshlrev_b16_sdwa v17, v5, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-; GFX8-NEXT:    v_lshlrev_b16_sdwa v3, v5, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT:    v_lshrrev_b32_e32 v10, 4, v4
+; GFX8-NEXT:    v_lshrrev_b32_e32 v11, 20, v2
+; GFX8-NEXT:    v_lshlrev_b16_e32 v16, 12, v4
+; GFX8-NEXT:    v_lshlrev_b16_sdwa v17, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v18, 12, v2
-; GFX8-NEXT:    v_lshlrev_b16_sdwa v19, v5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-; GFX8-NEXT:    v_lshlrev_b16_sdwa v2, v5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT:    v_lshlrev_b16_e32 v5, 12, v10
+; GFX8-NEXT:    v_lshlrev_b16_sdwa v19, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+; GFX8-NEXT:    v_lshlrev_b16_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT:    v_lshrrev_b32_e32 v8, 12, v4
+; GFX8-NEXT:    v_lshrrev_b32_e32 v9, 8, v4
+; GFX8-NEXT:    v_lshlrev_b16_sdwa v4, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT:    v_lshlrev_b16_e32 v3, 12, v10
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v7, 12, v7
+; GFX8-NEXT:    v_lshlrev_b16_e32 v6, 12, v6
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v12, 12, v12
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v10, 12, v16
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v16, 12, v17
-; GFX8-NEXT:    v_ashrrev_i16_e32 v17, 12, v3
-; GFX8-NEXT:    v_lshlrev_b16_e32 v3, 12, v6
-; GFX8-NEXT:    v_lshlrev_b16_e32 v6, 12, v15
-; GFX8-NEXT:    v_ashrrev_i16_e32 v15, 12, v18
+; GFX8-NEXT:    v_ashrrev_i16_e32 v17, 12, v18
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v18, 12, v19
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v19, 12, v2
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v2, 12, v11
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v9, 12, v9
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v8, 12, v8
-; GFX8-NEXT:    v_lshlrev_b16_e32 v13, 12, v13
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v14, 12, v14
+; GFX8-NEXT:    v_lshlrev_b16_e32 v13, 12, v13
+; GFX8-NEXT:    v_lshlrev_b16_e32 v15, 12, v15
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v7, 12, v7
-; GFX8-NEXT:    v_ashrrev_i16_e32 v3, 12, v3
+; GFX8-NEXT:    v_ashrrev_i16_e32 v6, 12, v6
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v2, 12, v2
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v12, 12, v12
-; GFX8-NEXT:    v_ashrrev_i16_e32 v11, 12, v14
-; GFX8-NEXT:    v_mul_lo_u16_e32 v10, v10, v15
-; GFX8-NEXT:    v_mul_lo_u16_sdwa v2, v3, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX8-NEXT:    v_mul_lo_u16_e32 v10, v10, v17
+; GFX8-NEXT:    v_mul_lo_u16_sdwa v2, v6, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX8-NEXT:    v_ashrrev_i16_e32 v4, 12, v4
+; GFX8-NEXT:    v_ashrrev_i16_e32 v11, 12, v15
+; GFX8-NEXT:    v_ashrrev_i16_e32 v3, 12, v3
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v9, 12, v9
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v8, 12, v8
+; GFX8-NEXT:    v_ashrrev_i16_e32 v14, 12, v14
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v13, 12, v13
-; GFX8-NEXT:    v_mul_lo_u16_sdwa v3, v7, v12 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX8-NEXT:    v_mul_lo_u16_e32 v15, v16, v18
+; GFX8-NEXT:    v_mul_lo_u16_sdwa v6, v7, v12 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX8-NEXT:    v_mul_lo_u16_e32 v17, v16, v18
 ; GFX8-NEXT:    v_mul_lo_u16_sdwa v7, v8, v13 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX8-NEXT:    v_mul_lo_u16_e32 v8, v9, v11
-; GFX8-NEXT:    v_or_b32_sdwa v3, v15, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX8-NEXT:    v_ashrrev_i16_e32 v5, 12, v5
-; GFX8-NEXT:    v_ashrrev_i16_e32 v6, 12, v6
-; GFX8-NEXT:    v_mul_lo_u16_e32 v14, v17, v19
-; GFX8-NEXT:    v_mul_lo_u16_sdwa v5, v5, v6 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX8-NEXT:    v_mul_lo_u16_e32 v8, v9, v14
+; GFX8-NEXT:    v_mul_lo_u16_e32 v15, v4, v19
+; GFX8-NEXT:    v_mul_lo_u16_sdwa v9, v3, v11 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX8-NEXT:    v_or_b32_sdwa v6, v17, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 ; GFX8-NEXT:    v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX8-NEXT:    v_or_b32_sdwa v6, v14, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX8-NEXT:    v_lshlrev_b32_e32 v9, 16, v3
-; GFX8-NEXT:    v_or_b32_sdwa v8, v10, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX8-NEXT:    v_or_b32_sdwa v3, v15, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX8-NEXT:    v_or_b32_sdwa v8, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX8-NEXT:    v_lshlrev_b32_e32 v10, 16, v6
+; GFX8-NEXT:    v_or_b32_sdwa v3, v3, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
 ; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 16, v7
+; GFX8-NEXT:    v_or_b32_e32 v9, v9, v2
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v10, 8, v3
-; GFX8-NEXT:    v_or_b32_sdwa v3, v6, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT:    v_or_b32_e32 v5, v5, v2
-; GFX8-NEXT:    v_lshrrev_b32_e32 v6, 8, v3
 ; GFX8-NEXT:    v_lshrrev_b64 v[2:3], 24, v[2:3]
-; GFX8-NEXT:    v_lshrrev_b32_e32 v5, 8, v5
+; GFX8-NEXT:    v_lshrrev_b32_e32 v9, 8, v9
 ; GFX8-NEXT:    s_waitcnt vmcnt(0)
-; GFX8-NEXT:    v_add_u16_e32 v3, v8, v4
-; GFX8-NEXT:    v_add_u16_e32 v3, v3, v5
+; GFX8-NEXT:    v_add_u16_e32 v3, v8, v5
+; GFX8-NEXT:    v_add_u16_e32 v3, v3, v9
 ; GFX8-NEXT:    v_add_u16_e32 v3, v3, v7
 ; GFX8-NEXT:    v_add_u16_e32 v2, v3, v2
-; GFX8-NEXT:    v_mad_u16 v2, v17, v19, v2
-; GFX8-NEXT:    v_add_u16_e32 v2, v2, v6
-; GFX8-NEXT:    v_mad_u16 v2, v16, v18, v2
+; GFX8-NEXT:    v_mad_u16 v2, v4, v19, v2
 ; GFX8-NEXT:    v_add_u16_e32 v2, v2, v10
+; GFX8-NEXT:    v_lshrrev_b32_e32 v6, 8, v6
+; GFX8-NEXT:    v_mad_u16 v2, v16, v18, v2
+; GFX8-NEXT:    v_add_u16_e32 v2, v2, v6
 ; GFX8-NEXT:    flat_store_byte v[0:1], v2
 ; GFX8-NEXT:    s_endpgm
 ;
diff --git a/llvm/test/CodeGen/AMDGPU/idot8u.ll b/llvm/test/CodeGen/AMDGPU/idot8u.ll
--- a/llvm/test/CodeGen/AMDGPU/idot8u.ll
+++ b/llvm/test/CodeGen/AMDGPU/idot8u.ll
@@ -341,46 +341,46 @@
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s4, v2
 ; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT:    flat_load_dword v4, v[0:1]
-; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s6, v2
-; GFX8-NEXT:    v_mov_b32_e32 v1, s7
-; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT:    v_mov_b32_e32 v3, s1
+; GFX8-NEXT:    v_mov_b32_e32 v5, s1
+; GFX8-NEXT:    v_mov_b32_e32 v3, s7
+; GFX8-NEXT:    v_add_u32_e32 v2, vcc, s6, v2
+; GFX8-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
 ; GFX8-NEXT:    flat_load_dword v0, v[0:1]
-; GFX8-NEXT:    v_mov_b32_e32 v2, s0
-; GFX8-NEXT:    flat_load_ushort v18, v[2:3]
+; GFX8-NEXT:    flat_load_dword v1, v[2:3]
+; GFX8-NEXT:    v_mov_b32_e32 v4, s0
+; GFX8-NEXT:    flat_load_ushort v18, v[4:5]
 ; GFX8-NEXT:    s_mov_b32 s10, -1
 ; GFX8-NEXT:    s_mov_b32 s11, 0xe80000
 ; GFX8-NEXT:    s_add_u32 s8, s8, s3
 ; GFX8-NEXT:    s_addc_u32 s9, s9, 0
 ; GFX8-NEXT:    s_waitcnt vmcnt(2)
-; GFX8-NEXT:    v_lshrrev_b32_e32 v1, 28, v4
-; GFX8-NEXT:    v_bfe_u32 v5, v4, 24, 4
-; GFX8-NEXT:    v_bfe_u32 v6, v4, 20, 4
-; GFX8-NEXT:    v_bfe_u32 v7, v4, 16, 4
-; GFX8-NEXT:    v_bfe_u32 v8, v4, 12, 4
-; GFX8-NEXT:    v_bfe_u32 v9, v4, 8, 4
-; GFX8-NEXT:    v_bfe_u32 v10, v4, 4, 4
-; GFX8-NEXT:    v_and_b32_e32 v4, 15, v4
-; GFX8-NEXT:    s_waitcnt vmcnt(1)
-; GFX8-NEXT:    v_lshrrev_b32_e32 v11, 28, v0
-; GFX8-NEXT:    v_bfe_u32 v12, v0, 24, 4
-; GFX8-NEXT:    v_bfe_u32 v13, v0, 20, 4
-; GFX8-NEXT:    v_bfe_u32 v14, v0, 16, 4
-; GFX8-NEXT:    v_bfe_u32 v15, v0, 12, 4
-; GFX8-NEXT:    v_bfe_u32 v16, v0, 8, 4
-; GFX8-NEXT:    v_bfe_u32 v17, v0, 4, 4
+; GFX8-NEXT:    v_lshrrev_b32_e32 v2, 28, v0
+; GFX8-NEXT:    v_bfe_u32 v3, v0, 24, 4
+; GFX8-NEXT:    v_bfe_u32 v6, v0, 20, 4
+; GFX8-NEXT:    v_bfe_u32 v7, v0, 16, 4
+; GFX8-NEXT:    v_bfe_u32 v8, v0, 12, 4
+; GFX8-NEXT:    v_bfe_u32 v9, v0, 8, 4
+; GFX8-NEXT:    v_bfe_u32 v10, v0, 4, 4
 ; GFX8-NEXT:    v_and_b32_e32 v0, 15, v0
+; GFX8-NEXT:    s_waitcnt vmcnt(1)
+; GFX8-NEXT:    v_lshrrev_b32_e32 v11, 28, v1
+; GFX8-NEXT:    v_bfe_u32 v12, v1, 24, 4
+; GFX8-NEXT:    v_bfe_u32 v13, v1, 20, 4
+; GFX8-NEXT:    v_bfe_u32 v14, v1, 16, 4
+; GFX8-NEXT:    v_bfe_u32 v15, v1, 12, 4
+; GFX8-NEXT:    v_bfe_u32 v16, v1, 8, 4
+; GFX8-NEXT:    v_bfe_u32 v17, v1, 4, 4
+; GFX8-NEXT:    v_and_b32_e32 v1, 15, v1
 ; GFX8-NEXT:    s_waitcnt vmcnt(0)
-; GFX8-NEXT:    v_mad_u16 v0, v4, v0, v18
+; GFX8-NEXT:    v_mad_u16 v0, v0, v1, v18
 ; GFX8-NEXT:    v_mad_u16 v0, v10, v17, v0
 ; GFX8-NEXT:    v_mad_u16 v0, v9, v16, v0
 ; GFX8-NEXT:    v_mad_u16 v0, v8, v15, v0
 ; GFX8-NEXT:    v_mad_u16 v0, v7, v14, v0
 ; GFX8-NEXT:    v_mad_u16 v0, v6, v13, v0
-; GFX8-NEXT:    v_mad_u16 v0, v5, v12, v0
-; GFX8-NEXT:    v_mad_u16 v0, v1, v11, v0
-; GFX8-NEXT:    flat_store_short v[2:3], v0
+; GFX8-NEXT:    v_mad_u16 v0, v3, v12, v0
+; GFX8-NEXT:    v_mad_u16 v0, v2, v11, v0
+; GFX8-NEXT:    flat_store_short v[4:5], v0
 ; GFX8-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: udot8_acc16:
@@ -659,46 +659,46 @@
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s4, v2
 ; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT:    flat_load_dword v4, v[0:1]
-; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s6, v2
-; GFX8-NEXT:    v_mov_b32_e32 v1, s7
-; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT:    v_mov_b32_e32 v3, s1
+; GFX8-NEXT:    v_mov_b32_e32 v5, s1
+; GFX8-NEXT:    v_mov_b32_e32 v3, s7
+; GFX8-NEXT:    v_add_u32_e32 v2, vcc, s6, v2
+; GFX8-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
 ; GFX8-NEXT:    flat_load_dword v0, v[0:1]
-; GFX8-NEXT:    v_mov_b32_e32 v2, s0
-; GFX8-NEXT:    flat_load_ubyte v18, v[2:3]
+; GFX8-NEXT:    flat_load_dword v1, v[2:3]
+; GFX8-NEXT:    v_mov_b32_e32 v4, s0
+; GFX8-NEXT:    flat_load_ubyte v18, v[4:5]
 ; GFX8-NEXT:    s_mov_b32 s10, -1
 ; GFX8-NEXT:    s_mov_b32 s11, 0xe80000
 ; GFX8-NEXT:    s_add_u32 s8, s8, s3
 ; GFX8-NEXT:    s_addc_u32 s9, s9, 0
 ; GFX8-NEXT:    s_waitcnt vmcnt(2)
-; GFX8-NEXT:    v_lshrrev_b32_e32 v1, 28, v4
-; GFX8-NEXT:    v_bfe_u32 v5, v4, 24, 4
-; GFX8-NEXT:    v_bfe_u32 v6, v4, 20, 4
-; GFX8-NEXT:    v_bfe_u32 v7, v4, 16, 4
-; GFX8-NEXT:    v_bfe_u32 v8, v4, 12, 4
-; GFX8-NEXT:    v_bfe_u32 v9, v4, 8, 4
-; GFX8-NEXT:    v_bfe_u32 v10, v4, 4, 4
-; GFX8-NEXT:    v_and_b32_e32 v4, 15, v4
-; GFX8-NEXT:    s_waitcnt vmcnt(1)
-; GFX8-NEXT:    v_lshrrev_b32_e32 v11, 28, v0
-; GFX8-NEXT:    v_bfe_u32 v12, v0, 24, 4
-; GFX8-NEXT:    v_bfe_u32 v13, v0, 20, 4
-; GFX8-NEXT:    v_bfe_u32 v14, v0, 16, 4
-; GFX8-NEXT:    v_bfe_u32 v15, v0, 12, 4
-; GFX8-NEXT:    v_bfe_u32 v16, v0, 8, 4
-; GFX8-NEXT:    v_bfe_u32 v17, v0, 4, 4
+; GFX8-NEXT:    v_lshrrev_b32_e32 v2, 28, v0
+; GFX8-NEXT:    v_bfe_u32 v3, v0, 24, 4
+; GFX8-NEXT:    v_bfe_u32 v6, v0, 20, 4
+; GFX8-NEXT:    v_bfe_u32 v7, v0, 16, 4
+; GFX8-NEXT:    v_bfe_u32 v8, v0, 12, 4
+; GFX8-NEXT:    v_bfe_u32 v9, v0, 8, 4
+; GFX8-NEXT:    v_bfe_u32 v10, v0, 4, 4
 ; GFX8-NEXT:    v_and_b32_e32 v0, 15, v0
+; GFX8-NEXT:    s_waitcnt vmcnt(1)
+; GFX8-NEXT:    v_lshrrev_b32_e32 v11, 28, v1
+; GFX8-NEXT:    v_bfe_u32 v12, v1, 24, 4
+; GFX8-NEXT:    v_bfe_u32 v13, v1, 20, 4
+; GFX8-NEXT:    v_bfe_u32 v14, v1, 16, 4
+; GFX8-NEXT:    v_bfe_u32 v15, v1, 12, 4
+; GFX8-NEXT:    v_bfe_u32 v16, v1, 8, 4
+; GFX8-NEXT:    v_bfe_u32 v17, v1, 4, 4
+; GFX8-NEXT:    v_and_b32_e32 v1, 15, v1
 ; GFX8-NEXT:    s_waitcnt vmcnt(0)
-; GFX8-NEXT:    v_mad_u16 v0, v4, v0, v18
+; GFX8-NEXT:    v_mad_u16 v0, v0, v1, v18
 ; GFX8-NEXT:    v_mad_u16 v0, v10, v17, v0
 ; GFX8-NEXT:    v_mad_u16 v0, v9, v16, v0
 ; GFX8-NEXT:    v_mad_u16 v0, v8, v15, v0
 ; GFX8-NEXT:    v_mad_u16 v0, v7, v14, v0
 ; GFX8-NEXT:    v_mad_u16 v0, v6, v13, v0
-; GFX8-NEXT:    v_mad_u16 v0, v5, v12, v0
-; GFX8-NEXT:    v_mad_u16 v0, v1, v11, v0
-; GFX8-NEXT:    flat_store_byte v[2:3], v0
+; GFX8-NEXT:    v_mad_u16 v0, v3, v12, v0
+; GFX8-NEXT:    v_mad_u16 v0, v2, v11, v0
+; GFX8-NEXT:    flat_store_byte v[4:5], v0
 ; GFX8-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: udot8_acc8:
@@ -978,47 +978,47 @@
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s4, v2
 ; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT:    flat_load_dword v4, v[0:1]
-; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s6, v2
-; GFX8-NEXT:    v_mov_b32_e32 v1, s7
-; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT:    v_mov_b32_e32 v3, s1
+; GFX8-NEXT:    v_mov_b32_e32 v5, s1
+; GFX8-NEXT:    v_mov_b32_e32 v3, s7
+; GFX8-NEXT:    v_add_u32_e32 v2, vcc, s6, v2
+; GFX8-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
 ; GFX8-NEXT:    flat_load_dword v0, v[0:1]
-; GFX8-NEXT:    v_mov_b32_e32 v2, s0
-; GFX8-NEXT:    flat_load_ubyte v18, v[2:3]
+; GFX8-NEXT:    flat_load_dword v1, v[2:3]
+; GFX8-NEXT:    v_mov_b32_e32 v4, s0
+; GFX8-NEXT:    flat_load_ubyte v18, v[4:5]
 ; GFX8-NEXT:    s_mov_b32 s10, -1
 ; GFX8-NEXT:    s_mov_b32 s11, 0xe80000
 ; GFX8-NEXT:    s_add_u32 s8, s8, s3
 ; GFX8-NEXT:    s_addc_u32 s9, s9, 0
 ; GFX8-NEXT:    s_waitcnt vmcnt(2)
-; GFX8-NEXT:    v_lshrrev_b32_e32 v1, 28, v4
-; GFX8-NEXT:    v_lshrrev_b32_e32 v5, 24, v4
-; GFX8-NEXT:    v_bfe_u32 v6, v4, 20, 4
-; GFX8-NEXT:    v_bfe_u32 v7, v4, 16, 4
-; GFX8-NEXT:    v_bfe_u32 v8, v4, 12, 4
-; GFX8-NEXT:    v_bfe_u32 v9, v4, 8, 4
-; GFX8-NEXT:    v_bfe_u32 v10, v4, 4, 4
-; GFX8-NEXT:    v_and_b32_e32 v4, 15, v4
-; GFX8-NEXT:    s_waitcnt vmcnt(1)
-; GFX8-NEXT:    v_lshrrev_b32_e32 v11, 28, v0
-; GFX8-NEXT:    v_lshrrev_b32_e32 v12, 24, v0
-; GFX8-NEXT:    v_bfe_u32 v13, v0, 20, 4
-; GFX8-NEXT:    v_bfe_u32 v14, v0, 16, 4
-; GFX8-NEXT:    v_bfe_u32 v15, v0, 12, 4
-; GFX8-NEXT:    v_bfe_u32 v16, v0, 8, 4
-; GFX8-NEXT:    v_bfe_u32 v17, v0, 4, 4
+; GFX8-NEXT:    v_lshrrev_b32_e32 v2, 28, v0
+; GFX8-NEXT:    v_lshrrev_b32_e32 v3, 24, v0
+; GFX8-NEXT:    v_bfe_u32 v6, v0, 20, 4
+; GFX8-NEXT:    v_bfe_u32 v7, v0, 16, 4
+; GFX8-NEXT:    v_bfe_u32 v8, v0, 12, 4
+; GFX8-NEXT:    v_bfe_u32 v9, v0, 8, 4
+; GFX8-NEXT:    v_bfe_u32 v10, v0, 4, 4
 ; GFX8-NEXT:    v_and_b32_e32 v0, 15, v0
+; GFX8-NEXT:    s_waitcnt vmcnt(1)
+; GFX8-NEXT:    v_lshrrev_b32_e32 v11, 28, v1
+; GFX8-NEXT:    v_lshrrev_b32_e32 v12, 24, v1
+; GFX8-NEXT:    v_bfe_u32 v13, v1, 20, 4
+; GFX8-NEXT:    v_bfe_u32 v14, v1, 16, 4
+; GFX8-NEXT:    v_bfe_u32 v15, v1, 12, 4
+; GFX8-NEXT:    v_bfe_u32 v16, v1, 8, 4
+; GFX8-NEXT:    v_bfe_u32 v17, v1, 4, 4
+; GFX8-NEXT:    v_and_b32_e32 v1, 15, v1
 ; GFX8-NEXT:    s_waitcnt vmcnt(0)
-; GFX8-NEXT:    v_mad_u16 v0, v4, v0, v18
+; GFX8-NEXT:    v_mad_u16 v0, v0, v1, v18
 ; GFX8-NEXT:    v_mad_u16 v0, v10, v17, v0
 ; GFX8-NEXT:    v_mad_u16 v0, v9, v16, v0
 ; GFX8-NEXT:    v_mad_u16 v0, v8, v15, v0
 ; GFX8-NEXT:    v_mad_u16 v0, v7, v14, v0
 ; GFX8-NEXT:    v_mad_u16 v0, v6, v13, v0
-; GFX8-NEXT:    v_mad_u16 v0, v5, v12, v0
-; GFX8-NEXT:    v_mad_u16 v0, v1, v11, v0
+; GFX8-NEXT:    v_mad_u16 v0, v3, v12, v0
+; GFX8-NEXT:    v_mad_u16 v0, v2, v11, v0
 ; GFX8-NEXT:    v_and_b32_e32 v0, 15, v0
-; GFX8-NEXT:    flat_store_byte v[2:3], v0
+; GFX8-NEXT:    flat_store_byte v[4:5], v0
 ; GFX8-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: udot8_acc4:
@@ -1285,47 +1285,47 @@
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s4, v2
 ; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT:    flat_load_dword v4, v[0:1]
-; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s6, v2
-; GFX8-NEXT:    v_mov_b32_e32 v1, s7
-; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT:    v_mov_b32_e32 v3, s1
+; GFX8-NEXT:    v_mov_b32_e32 v5, s1
+; GFX8-NEXT:    v_mov_b32_e32 v3, s7
+; GFX8-NEXT:    v_add_u32_e32 v2, vcc, s6, v2
+; GFX8-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
 ; GFX8-NEXT:    flat_load_dword v0, v[0:1]
-; GFX8-NEXT:    v_mov_b32_e32 v2, s0
-; GFX8-NEXT:    flat_load_ubyte v18, v[2:3]
+; GFX8-NEXT:    flat_load_dword v1, v[2:3]
+; GFX8-NEXT:    v_mov_b32_e32 v4, s0
+; GFX8-NEXT:    flat_load_ubyte v18, v[4:5]
 ; GFX8-NEXT:    s_mov_b32 s10, -1
 ; GFX8-NEXT:    s_mov_b32 s11, 0xe80000
 ; GFX8-NEXT:    s_add_u32 s8, s8, s3
 ; GFX8-NEXT:    s_addc_u32 s9, s9, 0
 ; GFX8-NEXT:    s_waitcnt vmcnt(2)
-; GFX8-NEXT:    v_lshrrev_b32_e32 v1, 28, v4
-; GFX8-NEXT:    v_lshrrev_b32_e32 v5, 24, v4
-; GFX8-NEXT:    v_bfe_u32 v6, v4, 20, 4
-; GFX8-NEXT:    v_bfe_u32 v7, v4, 16, 4
-; GFX8-NEXT:    v_bfe_u32 v8, v4, 12, 4
-; GFX8-NEXT:    v_bfe_u32 v9, v4, 8, 4
-; GFX8-NEXT:    v_bfe_u32 v10, v4, 4, 4
-; GFX8-NEXT:    v_and_b32_e32 v4, 15, v4
-; GFX8-NEXT:    s_waitcnt vmcnt(1)
-; GFX8-NEXT:    v_lshrrev_b32_e32 v11, 28, v0
-; GFX8-NEXT:    v_lshrrev_b32_e32 v12, 24, v0
-; GFX8-NEXT:    v_bfe_u32 v13, v0, 20, 4
-; GFX8-NEXT:    v_bfe_u32 v14, v0, 16, 4
-; GFX8-NEXT:    v_bfe_u32 v15, v0, 12, 4
-; GFX8-NEXT:    v_bfe_u32 v16, v0, 8, 4
-; GFX8-NEXT:    v_bfe_u32 v17, v0, 4, 4
+; GFX8-NEXT:    v_lshrrev_b32_e32 v2, 28, v0
+; GFX8-NEXT:    v_lshrrev_b32_e32 v3, 24, v0
+; GFX8-NEXT:    v_bfe_u32 v6, v0, 20, 4
+; GFX8-NEXT:    v_bfe_u32 v7, v0, 16, 4
+; GFX8-NEXT:    v_bfe_u32 v8, v0, 12, 4
+; GFX8-NEXT:    v_bfe_u32 v9, v0, 8, 4
+; GFX8-NEXT:    v_bfe_u32 v10, v0, 4, 4
 ; GFX8-NEXT:    v_and_b32_e32 v0, 15, v0
+; GFX8-NEXT:    s_waitcnt vmcnt(1)
+; GFX8-NEXT:    v_lshrrev_b32_e32 v11, 28, v1
+; GFX8-NEXT:    v_lshrrev_b32_e32 v12, 24, v1
+; GFX8-NEXT:    v_bfe_u32 v13, v1, 20, 4
+; GFX8-NEXT:    v_bfe_u32 v14, v1, 16, 4
+; GFX8-NEXT:    v_bfe_u32 v15, v1, 12, 4
+; GFX8-NEXT:    v_bfe_u32 v16, v1, 8, 4
+; GFX8-NEXT:    v_bfe_u32 v17, v1, 4, 4
+; GFX8-NEXT:    v_and_b32_e32 v1, 15, v1
 ; GFX8-NEXT:    s_waitcnt vmcnt(0)
-; GFX8-NEXT:    v_mad_u16 v0, v4, v0, v18
+; GFX8-NEXT:    v_mad_u16 v0, v0, v1, v18
 ; GFX8-NEXT:    v_mad_u16 v0, v10, v17, v0
 ; GFX8-NEXT:    v_mad_u16 v0, v9, v16, v0
 ; GFX8-NEXT:    v_mad_u16 v0, v8, v15, v0
 ; GFX8-NEXT:    v_mad_u16 v0, v7, v14, v0
 ; GFX8-NEXT:    v_mad_u16 v0, v6, v13, v0
-; GFX8-NEXT:    v_mad_u16 v0, v5, v12, v0
-; GFX8-NEXT:    v_mad_u16 v0, v1, v11, v0
+; GFX8-NEXT:    v_mad_u16 v0, v3, v12, v0
+; GFX8-NEXT:    v_mad_u16 v0, v2, v11, v0
 ; GFX8-NEXT:    v_and_b32_e32 v0, 15, v0
-; GFX8-NEXT:    flat_store_byte v[2:3], v0
+; GFX8-NEXT:    flat_store_byte v[4:5], v0
 ; GFX8-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: udot8_CommutationInsideMAD:
@@ -2174,46 +2174,46 @@
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s4, v2
 ; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT:    flat_load_dword v4, v[0:1]
-; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s6, v2
-; GFX8-NEXT:    v_mov_b32_e32 v1, s7
-; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT:    v_mov_b32_e32 v3, s1
+; GFX8-NEXT:    v_mov_b32_e32 v5, s1
+; GFX8-NEXT:    v_mov_b32_e32 v3, s7
+; GFX8-NEXT:    v_add_u32_e32 v2, vcc, s6, v2
+; GFX8-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
 ; GFX8-NEXT:    flat_load_dword v0, v[0:1]
-; GFX8-NEXT:    v_mov_b32_e32 v2, s0
-; GFX8-NEXT:    flat_load_ushort v18, v[2:3]
+; GFX8-NEXT:    flat_load_dword v1, v[2:3]
+; GFX8-NEXT:    v_mov_b32_e32 v4, s0
+; GFX8-NEXT:    flat_load_ushort v18, v[4:5]
 ; GFX8-NEXT:    s_mov_b32 s10, -1
 ; GFX8-NEXT:    s_mov_b32 s11, 0xe80000
 ; GFX8-NEXT:    s_add_u32 s8, s8, s3
 ; GFX8-NEXT:    s_addc_u32 s9, s9, 0
 ; GFX8-NEXT:    s_waitcnt vmcnt(2)
-; GFX8-NEXT:    v_and_b32_e32 v1, 15, v4
-; GFX8-NEXT:    v_bfe_u32 v5, v4, 4, 4
-; GFX8-NEXT:    v_bfe_u32 v6, v4, 8, 4
-; GFX8-NEXT:    v_bfe_u32 v7, v4, 12, 4
-; GFX8-NEXT:    v_bfe_u32 v8, v4, 16, 4
+; GFX8-NEXT:    v_and_b32_e32 v2, 15, v0
 ; GFX8-NEXT:    s_waitcnt vmcnt(1)
-; GFX8-NEXT:    v_and_b32_e32 v11, 15, v0
-; GFX8-NEXT:    v_bfe_u32 v12, v0, 4, 4
+; GFX8-NEXT:    v_and_b32_e32 v11, 15, v1
+; GFX8-NEXT:    v_bfe_u32 v3, v0, 4, 4
+; GFX8-NEXT:    v_bfe_u32 v12, v1, 4, 4
 ; GFX8-NEXT:    s_waitcnt vmcnt(0)
-; GFX8-NEXT:    v_mad_u16 v1, v1, v11, v18
-; GFX8-NEXT:    v_bfe_u32 v13, v0, 8, 4
-; GFX8-NEXT:    v_mad_u16 v1, v5, v12, v1
-; GFX8-NEXT:    v_bfe_u32 v14, v0, 12, 4
-; GFX8-NEXT:    v_mad_u16 v1, v6, v13, v1
-; GFX8-NEXT:    v_bfe_u32 v15, v0, 16, 4
-; GFX8-NEXT:    v_mad_u16 v1, v7, v14, v1
-; GFX8-NEXT:    v_bfe_u32 v9, v4, 20, 4
-; GFX8-NEXT:    v_bfe_u32 v16, v0, 20, 4
-; GFX8-NEXT:    v_mad_u16 v1, v8, v15, v1
-; GFX8-NEXT:    v_bfe_u32 v10, v4, 24, 4
-; GFX8-NEXT:    v_bfe_u32 v17, v0, 24, 4
-; GFX8-NEXT:    v_mad_u16 v1, v9, v16, v1
-; GFX8-NEXT:    v_lshrrev_b32_e32 v4, 28, v4
+; GFX8-NEXT:    v_mad_u16 v2, v2, v11, v18
+; GFX8-NEXT:    v_bfe_u32 v6, v0, 8, 4
+; GFX8-NEXT:    v_bfe_u32 v13, v1, 8, 4
+; GFX8-NEXT:    v_mad_u16 v2, v3, v12, v2
+; GFX8-NEXT:    v_bfe_u32 v7, v0, 12, 4
+; GFX8-NEXT:    v_bfe_u32 v14, v1, 12, 4
+; GFX8-NEXT:    v_mad_u16 v2, v6, v13, v2
+; GFX8-NEXT:    v_bfe_u32 v8, v0, 16, 4
+; GFX8-NEXT:    v_bfe_u32 v15, v1, 16, 4
+; GFX8-NEXT:    v_mad_u16 v2, v7, v14, v2
+; GFX8-NEXT:    v_bfe_u32 v9, v0, 20, 4
+; GFX8-NEXT:    v_bfe_u32 v16, v1, 20, 4
+; GFX8-NEXT:    v_mad_u16 v2, v8, v15, v2
+; GFX8-NEXT:    v_bfe_u32 v10, v0, 24, 4
+; GFX8-NEXT:    v_bfe_u32 v17, v1, 24, 4
+; GFX8-NEXT:    v_mad_u16 v2, v9, v16, v2
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v0, 28, v0
-; GFX8-NEXT:    v_mad_u16 v1, v10, v17, v1
-; GFX8-NEXT:    v_mad_u16 v0, v4, v0, v1
-; GFX8-NEXT:    flat_store_short v[2:3], v0
+; GFX8-NEXT:    v_lshrrev_b32_e32 v1, 28, v1
+; GFX8-NEXT:    v_mad_u16 v2, v10, v17, v2
+; GFX8-NEXT:    v_mad_u16 v0, v0, v1, v2
+; GFX8-NEXT:    flat_store_short v[4:5], v0
 ; GFX8-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: udot8_acc16_vecMul:
@@ -2929,55 +2929,55 @@
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s4, v2
 ; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT:    flat_load_dword v4, v[0:1]
-; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s6, v2
-; GFX8-NEXT:    v_mov_b32_e32 v1, s7
-; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; GFX8-NEXT:    v_mov_b32_e32 v3, s7
+; GFX8-NEXT:    v_add_u32_e32 v2, vcc, s6, v2
+; GFX8-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
 ; GFX8-NEXT:    flat_load_dword v0, v[0:1]
-; GFX8-NEXT:    v_mov_b32_e32 v3, s1
-; GFX8-NEXT:    v_mov_b32_e32 v2, s0
+; GFX8-NEXT:    flat_load_dword v1, v[2:3]
+; GFX8-NEXT:    v_mov_b32_e32 v5, s1
+; GFX8-NEXT:    v_mov_b32_e32 v4, s0
 ; GFX8-NEXT:    s_mov_b32 s10, -1
 ; GFX8-NEXT:    s_mov_b32 s11, 0xe80000
 ; GFX8-NEXT:    s_add_u32 s8, s8, s3
 ; GFX8-NEXT:    s_addc_u32 s9, s9, 0
 ; GFX8-NEXT:    s_waitcnt vmcnt(1)
-; GFX8-NEXT:    v_and_b32_e32 v1, 15, v4
-; GFX8-NEXT:    v_bfe_u32 v5, v4, 4, 4
-; GFX8-NEXT:    v_bfe_u32 v6, v4, 8, 4
-; GFX8-NEXT:    v_bfe_u32 v7, v4, 12, 4
+; GFX8-NEXT:    v_and_b32_e32 v2, 15, v0
 ; GFX8-NEXT:    s_waitcnt vmcnt(0)
-; GFX8-NEXT:    v_and_b32_e32 v11, 15, v0
-; GFX8-NEXT:    v_bfe_u32 v12, v0, 4, 4
-; GFX8-NEXT:    v_bfe_u32 v13, v0, 8, 4
-; GFX8-NEXT:    v_bfe_u32 v14, v0, 12, 4
-; GFX8-NEXT:    v_bfe_u32 v8, v4, 16, 4
-; GFX8-NEXT:    v_bfe_u32 v15, v0, 16, 4
-; GFX8-NEXT:    v_bfe_u32 v9, v4, 20, 4
-; GFX8-NEXT:    v_bfe_u32 v10, v4, 24, 4
-; GFX8-NEXT:    v_bfe_u32 v16, v0, 20, 4
-; GFX8-NEXT:    v_bfe_u32 v17, v0, 24, 4
-; GFX8-NEXT:    v_lshrrev_b32_e32 v4, 28, v4
+; GFX8-NEXT:    v_and_b32_e32 v11, 15, v1
+; GFX8-NEXT:    v_bfe_u32 v3, v0, 4, 4
+; GFX8-NEXT:    v_bfe_u32 v12, v1, 4, 4
+; GFX8-NEXT:    v_bfe_u32 v6, v0, 8, 4
+; GFX8-NEXT:    v_bfe_u32 v13, v1, 8, 4
+; GFX8-NEXT:    v_bfe_u32 v7, v0, 12, 4
+; GFX8-NEXT:    v_bfe_u32 v14, v1, 12, 4
+; GFX8-NEXT:    v_bfe_u32 v8, v0, 16, 4
+; GFX8-NEXT:    v_bfe_u32 v15, v1, 16, 4
+; GFX8-NEXT:    v_bfe_u32 v9, v0, 20, 4
+; GFX8-NEXT:    v_bfe_u32 v10, v0, 24, 4
+; GFX8-NEXT:    v_bfe_u32 v16, v1, 20, 4
+; GFX8-NEXT:    v_bfe_u32 v17, v1, 24, 4
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v0, 28, v0
-; GFX8-NEXT:    v_mul_u32_u24_e32 v0, v4, v0
-; GFX8-NEXT:    v_mul_u32_u24_e32 v4, v10, v17
-; GFX8-NEXT:    flat_load_ubyte v10, v[2:3]
-; GFX8-NEXT:    v_mul_u32_u24_e32 v1, v1, v11
-; GFX8-NEXT:    v_mul_u32_u24_e32 v5, v5, v12
+; GFX8-NEXT:    v_lshrrev_b32_e32 v1, 28, v1
+; GFX8-NEXT:    v_mul_u32_u24_e32 v0, v0, v1
+; GFX8-NEXT:    v_mul_u32_u24_e32 v1, v10, v17
+; GFX8-NEXT:    flat_load_ubyte v10, v[4:5]
+; GFX8-NEXT:    v_mul_u32_u24_e32 v2, v2, v11
+; GFX8-NEXT:    v_mul_u32_u24_e32 v3, v3, v12
 ; GFX8-NEXT:    v_mul_u32_u24_e32 v6, v6, v13
 ; GFX8-NEXT:    v_mul_u32_u24_e32 v7, v7, v14
 ; GFX8-NEXT:    v_mul_u32_u24_e32 v8, v8, v15
 ; GFX8-NEXT:    v_mul_u32_u24_e32 v9, v9, v16
 ; GFX8-NEXT:    s_waitcnt vmcnt(0)
-; GFX8-NEXT:    v_add_u16_e32 v1, v1, v10
-; GFX8-NEXT:    v_add_u16_e32 v1, v1, v5
-; GFX8-NEXT:    v_add_u16_e32 v1, v1, v6
-; GFX8-NEXT:    v_add_u16_e32 v1, v1, v7
-; GFX8-NEXT:    v_add_u16_e32 v1, v1, v8
-; GFX8-NEXT:    v_add_u16_e32 v1, v1, v9
-; GFX8-NEXT:    v_add_u16_e32 v1, v1, v4
+; GFX8-NEXT:    v_add_u16_e32 v2, v2, v10
+; GFX8-NEXT:    v_add_u16_e32 v2, v2, v3
+; GFX8-NEXT:    v_add_u16_e32 v2, v2, v6
+; GFX8-NEXT:    v_add_u16_e32 v2, v2, v7
+; GFX8-NEXT:    v_add_u16_e32 v2, v2, v8
+; GFX8-NEXT:    v_add_u16_e32 v2, v2, v9
+; GFX8-NEXT:    v_add_u16_e32 v1, v2, v1
 ; GFX8-NEXT:    v_add_u16_e32 v0, v1, v0
 ; GFX8-NEXT:    v_and_b32_e32 v0, 15, v0
-; GFX8-NEXT:    flat_store_byte v[2:3], v0
+; GFX8-NEXT:    flat_store_byte v[4:5], v0
 ; GFX8-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: udot8_acc4_vecMul:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.mulo.ll b/llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
--- a/llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
@@ -31,21 +31,21 @@
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_mul_lo_u32 v5, v0, v3
 ; GFX9-NEXT:    v_mul_hi_u32 v6, v0, v2
-; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v3
-; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v2
-; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v2
+; GFX9-NEXT:    v_mul_hi_u32 v4, v0, v3
+; GFX9-NEXT:    v_mul_lo_u32 v8, v1, v2
+; GFX9-NEXT:    v_mul_hi_u32 v7, v1, v2
 ; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v6, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v10, v1, v3
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v8, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v1, v1, v3
-; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v7
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v4, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v10, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v1
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v8, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v9, v8
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v4, v7, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v10, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v1
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v0, v0, v2
 ; GFX9-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[3:4]
-; GFX9-NEXT:    v_add3_u32 v1, v6, v5, v7
+; GFX9-NEXT:    v_add3_u32 v1, v6, v5, v8
 ; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 bb:
@@ -97,31 +97,31 @@
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_mul_lo_u32 v5, v0, v3
 ; GFX9-NEXT:    v_mul_hi_u32 v6, v0, v2
-; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v3
-; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v2
-; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v2
+; GFX9-NEXT:    v_mul_hi_u32 v4, v0, v3
+; GFX9-NEXT:    v_mul_lo_u32 v8, v1, v2
+; GFX9-NEXT:    v_mul_hi_u32 v7, v1, v2
 ; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v6, v5
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v8, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v7
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v8
 ; GFX9-NEXT:    v_mul_hi_i32 v10, v1, v3
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v4, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v8, v1, v3
-; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, 0, v10, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v9, v1, v3
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v4, v7, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v10, vcc
 ; GFX9-NEXT:    v_mov_b32_e32 v10, 0
-; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v8
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v10, v9, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v9
+; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v10, v7, vcc
 ; GFX9-NEXT:    v_sub_co_u32_e32 v9, vcc, v4, v2
-; GFX9-NEXT:    v_subb_co_u32_e32 v11, vcc, v8, v10, vcc
+; GFX9-NEXT:    v_subb_co_u32_e32 v11, vcc, v7, v10, vcc
 ; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 0, v1
-; GFX9-NEXT:    v_cndmask_b32_e32 v1, v8, v11, vcc
-; GFX9-NEXT:    v_cndmask_b32_e32 v8, v4, v9, vcc
-; GFX9-NEXT:    v_sub_co_u32_e32 v9, vcc, v8, v0
+; GFX9-NEXT:    v_cndmask_b32_e32 v1, v7, v11, vcc
+; GFX9-NEXT:    v_cndmask_b32_e32 v7, v4, v9, vcc
+; GFX9-NEXT:    v_sub_co_u32_e32 v9, vcc, v7, v0
 ; GFX9-NEXT:    v_subb_co_u32_e32 v4, vcc, v1, v10, vcc
 ; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 0, v3
 ; GFX9-NEXT:    v_cndmask_b32_e32 v4, v1, v4, vcc
-; GFX9-NEXT:    v_add3_u32 v1, v6, v5, v7
+; GFX9-NEXT:    v_add3_u32 v1, v6, v5, v8
 ; GFX9-NEXT:    v_ashrrev_i32_e32 v5, 31, v1
-; GFX9-NEXT:    v_cndmask_b32_e32 v3, v8, v9, vcc
+; GFX9-NEXT:    v_cndmask_b32_e32 v3, v7, v9, vcc
 ; GFX9-NEXT:    v_mov_b32_e32 v6, v5
 ; GFX9-NEXT:    v_mul_lo_u32 v0, v0, v2
 ; GFX9-NEXT:    v_cmp_ne_u64_e32 vcc, v[3:4], v[5:6]
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.powi.ll b/llvm/test/CodeGen/AMDGPU/llvm.powi.ll
--- a/llvm/test/CodeGen/AMDGPU/llvm.powi.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.powi.ll
@@ -57,9 +57,9 @@
 ; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX7-NEXT:    v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
 ; GFX7-NEXT:    v_rcp_f32_e32 v2, v1
-; GFX7-NEXT:    v_fma_f32 v3, -v1, v2, 1.0
-; GFX7-NEXT:    v_fma_f32 v2, v3, v2, v2
 ; GFX7-NEXT:    v_div_scale_f32 v3, vcc, 1.0, v0, 1.0
+; GFX7-NEXT:    v_fma_f32 v4, -v1, v2, 1.0
+; GFX7-NEXT:    v_fma_f32 v2, v4, v2, v2
 ; GFX7-NEXT:    v_mul_f32_e32 v4, v3, v2
 ; GFX7-NEXT:    v_fma_f32 v5, -v1, v4, v3
 ; GFX7-NEXT:    v_fma_f32 v4, v5, v2, v4
@@ -104,9 +104,9 @@
 ; GFX7-NEXT:    v_mul_f32_e32 v0, v0, v0
 ; GFX7-NEXT:    v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
 ; GFX7-NEXT:    v_rcp_f32_e32 v2, v1
-; GFX7-NEXT:    v_fma_f32 v3, -v1, v2, 1.0
-; GFX7-NEXT:    v_fma_f32 v2, v3, v2, v2
 ; GFX7-NEXT:    v_div_scale_f32 v3, vcc, 1.0, v0, 1.0
+; GFX7-NEXT:    v_fma_f32 v4, -v1, v2, 1.0
+; GFX7-NEXT:    v_fma_f32 v2, v4, v2, v2
 ; GFX7-NEXT:    v_mul_f32_e32 v4, v3, v2
 ; GFX7-NEXT:    v_fma_f32 v5, -v1, v4, v3
 ; GFX7-NEXT:    v_fma_f32 v4, v5, v2, v4
@@ -200,9 +200,9 @@
 ; GFX7-NEXT:    v_mul_f32_e32 v0, v0, v0
 ; GFX7-NEXT:    v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
 ; GFX7-NEXT:    v_rcp_f32_e32 v2, v1
-; GFX7-NEXT:    v_fma_f32 v3, -v1, v2, 1.0
-; GFX7-NEXT:    v_fma_f32 v2, v3, v2, v2
 ; GFX7-NEXT:    v_div_scale_f32 v3, vcc, 1.0, v0, 1.0
+; GFX7-NEXT:    v_fma_f32 v4, -v1, v2, 1.0
+; GFX7-NEXT:    v_fma_f32 v2, v4, v2, v2
 ; GFX7-NEXT:    v_mul_f32_e32 v4, v3, v2
 ; GFX7-NEXT:    v_fma_f32 v5, -v1, v4, v3
 ; GFX7-NEXT:    v_fma_f32 v4, v5, v2, v4
diff --git a/llvm/test/CodeGen/AMDGPU/mul.ll b/llvm/test/CodeGen/AMDGPU/mul.ll
--- a/llvm/test/CodeGen/AMDGPU/mul.ll
+++ b/llvm/test/CodeGen/AMDGPU/mul.ll
@@ -230,9 +230,9 @@
 ; VI: s_mul_i32
 ; VI: v_mul_hi_u32
 ; VI: v_mul_hi_u32
-; VI: s_mul_i32
 ; VI: v_mad_u64_u32
 ; VI: s_mul_i32
+; VI: s_mul_i32
 ; VI: v_mad_u64_u32
 ; VI: s_mul_i32
 ; VI: s_mul_i32
diff --git a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
--- a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
+++ b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
@@ -86,9 +86,8 @@
 ; GFX8:    flat_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]
 ; GFX8:    flat_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]
 ;
-; GFX9:    global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-4096
-; GFX9:    global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048
 ; GFX9:    global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}}
+; GFX9:    global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-4096
 ; GFX9:    global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048
 ; GFX9:    global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}}
 ; GFX9:    global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048
@@ -96,6 +95,7 @@
 ; GFX9:    global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048
 ; GFX9:    global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-4096
 ; GFX9:    global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048
+; GFX9:    global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048
 ; GFX9:    global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}}
 ;
 ; GFX10:   global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048
diff --git a/llvm/test/CodeGen/AMDGPU/salu-to-valu.ll b/llvm/test/CodeGen/AMDGPU/salu-to-valu.ll
--- a/llvm/test/CodeGen/AMDGPU/salu-to-valu.ll
+++ b/llvm/test/CodeGen/AMDGPU/salu-to-valu.ll
@@ -203,10 +203,10 @@
 ; GCN-LABEL: {{^}}smrd_valu_ci_offset_x16:
 
 ; SI: s_mov_b32 {{s[0-9]+}}, 0x13480
-; SI: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:16
-; SI: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:32
-; SI: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], {{s[0-9]+}} addr64
-; SI: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:48
+; SI-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:16
+; SI-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:32
+; SI-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], {{s[0-9]+}} addr64
+; SI-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:48
 ; CI-NOHSA-DAG: s_mov_b32 [[OFFSET0:s[0-9]+]], 0x13480{{$}}
 ; CI-NOHSA-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET0]] addr64{{$}}
 ; CI-NOHSA-DAG: s_mov_b32 [[OFFSET1:s[0-9]+]], 0x13490{{$}}
diff --git a/llvm/test/CodeGen/AMDGPU/sdiv.ll b/llvm/test/CodeGen/AMDGPU/sdiv.ll
--- a/llvm/test/CodeGen/AMDGPU/sdiv.ll
+++ b/llvm/test/CodeGen/AMDGPU/sdiv.ll
@@ -203,14 +203,14 @@
 ; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
 ; GCN-NEXT:    s_mov_b32 s3, 0xf000
 ; GCN-NEXT:    s_mov_b32 s2, -1
-; GCN-NEXT:    s_mov_b32 s10, s2
-; GCN-NEXT:    s_mov_b32 s11, s3
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-NEXT:    s_mov_b32 s8, s6
-; GCN-NEXT:    s_mov_b32 s9, s7
-; GCN-NEXT:    buffer_load_dword v0, off, s[8:11], 0
 ; GCN-NEXT:    s_mov_b32 s0, s4
 ; GCN-NEXT:    s_mov_b32 s1, s5
+; GCN-NEXT:    s_mov_b32 s4, s6
+; GCN-NEXT:    s_mov_b32 s5, s7
+; GCN-NEXT:    s_mov_b32 s6, s2
+; GCN-NEXT:    s_mov_b32 s7, s3
+; GCN-NEXT:    buffer_load_dword v0, off, s[4:7], 0
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
 ; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
 ; GCN-NEXT:    v_lshrrev_b32_e32 v1, 30, v1
@@ -224,14 +224,14 @@
 ; TONGA-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; TONGA-NEXT:    s_mov_b32 s3, 0xf000
 ; TONGA-NEXT:    s_mov_b32 s2, -1
-; TONGA-NEXT:    s_mov_b32 s10, s2
-; TONGA-NEXT:    s_mov_b32 s11, s3
 ; TONGA-NEXT:    s_waitcnt lgkmcnt(0)
-; TONGA-NEXT:    s_mov_b32 s8, s6
-; TONGA-NEXT:    s_mov_b32 s9, s7
-; TONGA-NEXT:    buffer_load_dword v0, off, s[8:11], 0
 ; TONGA-NEXT:    s_mov_b32 s0, s4
 ; TONGA-NEXT:    s_mov_b32 s1, s5
+; TONGA-NEXT:    s_mov_b32 s4, s6
+; TONGA-NEXT:    s_mov_b32 s5, s7
+; TONGA-NEXT:    s_mov_b32 s6, s2
+; TONGA-NEXT:    s_mov_b32 s7, s3
+; TONGA-NEXT:    buffer_load_dword v0, off, s[4:7], 0
 ; TONGA-NEXT:    s_waitcnt vmcnt(0)
 ; TONGA-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
 ; TONGA-NEXT:    v_lshrrev_b32_e32 v1, 30, v1
@@ -405,62 +405,62 @@
 ; GCN-NEXT:    s_mov_b32 s4, s0
 ; GCN-NEXT:    s_mov_b32 s5, s1
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    v_ashrrev_i32_e32 v5, 31, v2
-; GCN-NEXT:    v_ashrrev_i32_e32 v7, 31, v3
-; GCN-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v7, v3
-; GCN-NEXT:    v_ashrrev_i32_e32 v4, 31, v0
-; GCN-NEXT:    v_ashrrev_i32_e32 v6, 31, v1
-; GCN-NEXT:    v_xor_b32_e32 v2, v2, v5
-; GCN-NEXT:    v_xor_b32_e32 v3, v3, v7
-; GCN-NEXT:    v_xor_b32_e32 v8, v4, v5
-; GCN-NEXT:    v_cvt_f32_u32_e32 v5, v2
-; GCN-NEXT:    v_xor_b32_e32 v9, v6, v7
+; GCN-NEXT:    v_ashrrev_i32_e32 v4, 31, v2
+; GCN-NEXT:    v_ashrrev_i32_e32 v5, 31, v3
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
+; GCN-NEXT:    v_xor_b32_e32 v2, v2, v4
+; GCN-NEXT:    v_xor_b32_e32 v3, v3, v5
+; GCN-NEXT:    v_cvt_f32_u32_e32 v6, v2
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v7, v3
 ; GCN-NEXT:    v_sub_i32_e32 v10, vcc, 0, v2
-; GCN-NEXT:    v_rcp_iflag_f32_e32 v5, v5
 ; GCN-NEXT:    v_sub_i32_e32 v11, vcc, 0, v3
+; GCN-NEXT:    v_rcp_iflag_f32_e32 v6, v6
 ; GCN-NEXT:    v_rcp_iflag_f32_e32 v7, v7
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v4, v0
-; GCN-NEXT:    v_mul_f32_e32 v5, s2, v5
-; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v5
+; GCN-NEXT:    v_ashrrev_i32_e32 v8, 31, v0
+; GCN-NEXT:    v_ashrrev_i32_e32 v9, 31, v1
+; GCN-NEXT:    v_mul_f32_e32 v6, s2, v6
 ; GCN-NEXT:    v_mul_f32_e32 v7, s2, v7
+; GCN-NEXT:    v_cvt_u32_f32_e32 v6, v6
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v7, v7
-; GCN-NEXT:    v_add_i32_e32 v1, vcc, v6, v1
-; GCN-NEXT:    v_mul_lo_u32 v10, v10, v5
-; GCN-NEXT:    v_xor_b32_e32 v0, v0, v4
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v8, v0
+; GCN-NEXT:    v_add_i32_e32 v1, vcc, v9, v1
+; GCN-NEXT:    v_mul_lo_u32 v10, v10, v6
 ; GCN-NEXT:    v_mul_lo_u32 v11, v11, v7
-; GCN-NEXT:    v_xor_b32_e32 v1, v1, v6
-; GCN-NEXT:    v_mul_hi_u32 v4, v5, v10
-; GCN-NEXT:    v_mul_hi_u32 v6, v7, v11
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
-; GCN-NEXT:    v_mul_hi_u32 v4, v0, v4
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v7
-; GCN-NEXT:    v_mul_hi_u32 v5, v1, v5
-; GCN-NEXT:    v_mul_lo_u32 v6, v4, v2
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, 1, v4
-; GCN-NEXT:    v_mul_lo_u32 v10, v5, v3
-; GCN-NEXT:    v_add_i32_e32 v11, vcc, 1, v5
-; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, v6, v0
+; GCN-NEXT:    v_xor_b32_e32 v0, v0, v8
+; GCN-NEXT:    v_xor_b32_e32 v1, v1, v9
+; GCN-NEXT:    v_mul_hi_u32 v10, v6, v10
+; GCN-NEXT:    v_mul_hi_u32 v11, v7, v11
+; GCN-NEXT:    v_xor_b32_e32 v4, v8, v4
+; GCN-NEXT:    v_xor_b32_e32 v5, v9, v5
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v10, v6
+; GCN-NEXT:    v_add_i32_e32 v7, vcc, v11, v7
+; GCN-NEXT:    v_mul_hi_u32 v6, v0, v6
+; GCN-NEXT:    v_mul_hi_u32 v7, v1, v7
+; GCN-NEXT:    v_mul_lo_u32 v8, v6, v2
+; GCN-NEXT:    v_mul_lo_u32 v9, v7, v3
+; GCN-NEXT:    v_add_i32_e32 v10, vcc, 1, v6
+; GCN-NEXT:    v_add_i32_e32 v11, vcc, 1, v7
+; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, v8, v0
+; GCN-NEXT:    v_subrev_i32_e32 v1, vcc, v9, v1
 ; GCN-NEXT:    v_cmp_ge_u32_e64 s[0:1], v0, v2
-; GCN-NEXT:    v_subrev_i32_e32 v1, vcc, v10, v1
 ; GCN-NEXT:    v_cmp_ge_u32_e64 s[2:3], v1, v3
-; GCN-NEXT:    v_subrev_i32_e32 v6, vcc, v2, v0
-; GCN-NEXT:    v_cndmask_b32_e64 v4, v4, v7, s[0:1]
-; GCN-NEXT:    v_subrev_i32_e32 v7, vcc, v3, v1
-; GCN-NEXT:    v_cndmask_b32_e64 v5, v5, v11, s[2:3]
-; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v6, s[0:1]
-; GCN-NEXT:    v_cndmask_b32_e64 v1, v1, v7, s[2:3]
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, 1, v4
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, 1, v5
+; GCN-NEXT:    v_subrev_i32_e32 v8, vcc, v2, v0
+; GCN-NEXT:    v_subrev_i32_e32 v9, vcc, v3, v1
+; GCN-NEXT:    v_cndmask_b32_e64 v6, v6, v10, s[0:1]
+; GCN-NEXT:    v_cndmask_b32_e64 v7, v7, v11, s[2:3]
+; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v8, s[0:1]
+; GCN-NEXT:    v_cndmask_b32_e64 v1, v1, v9, s[2:3]
+; GCN-NEXT:    v_add_i32_e32 v8, vcc, 1, v6
+; GCN-NEXT:    v_add_i32_e32 v9, vcc, 1, v7
 ; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
-; GCN-NEXT:    v_cndmask_b32_e32 v0, v4, v6, vcc
+; GCN-NEXT:    v_cndmask_b32_e32 v0, v6, v8, vcc
 ; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v3
-; GCN-NEXT:    v_cndmask_b32_e32 v1, v5, v7, vcc
-; GCN-NEXT:    v_xor_b32_e32 v0, v0, v8
-; GCN-NEXT:    v_xor_b32_e32 v1, v1, v9
-; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v8
-; GCN-NEXT:    v_sub_i32_e32 v1, vcc, v1, v9
+; GCN-NEXT:    v_cndmask_b32_e32 v1, v7, v9, vcc
+; GCN-NEXT:    v_xor_b32_e32 v0, v0, v4
+; GCN-NEXT:    v_xor_b32_e32 v1, v1, v5
+; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
+; GCN-NEXT:    v_sub_i32_e32 v1, vcc, v1, v5
 ; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; GCN-NEXT:    s_endpgm
 ;
@@ -488,54 +488,54 @@
 ; TONGA-NEXT:    v_add_u32_e32 v0, vcc, v7, v0
 ; TONGA-NEXT:    v_rcp_iflag_f32_e32 v5, v5
 ; TONGA-NEXT:    v_xor_b32_e32 v0, v0, v7
-; TONGA-NEXT:    v_xor_b32_e32 v4, v7, v4
+; TONGA-NEXT:    v_ashrrev_i32_e32 v8, 31, v3
 ; TONGA-NEXT:    v_mul_f32_e32 v5, s2, v5
 ; TONGA-NEXT:    v_cvt_u32_f32_e32 v5, v5
 ; TONGA-NEXT:    v_mul_lo_u32 v6, v6, v5
 ; TONGA-NEXT:    v_mul_hi_u32 v6, v5, v6
 ; TONGA-NEXT:    v_add_u32_e32 v5, vcc, v6, v5
 ; TONGA-NEXT:    v_mul_hi_u32 v5, v0, v5
-; TONGA-NEXT:    v_ashrrev_i32_e32 v6, 31, v3
-; TONGA-NEXT:    v_mul_lo_u32 v8, v5, v2
+; TONGA-NEXT:    v_mul_lo_u32 v6, v5, v2
 ; TONGA-NEXT:    v_add_u32_e32 v9, vcc, 1, v5
-; TONGA-NEXT:    v_subrev_u32_e32 v0, vcc, v8, v0
+; TONGA-NEXT:    v_subrev_u32_e32 v0, vcc, v6, v0
 ; TONGA-NEXT:    v_cmp_ge_u32_e64 s[0:1], v0, v2
-; TONGA-NEXT:    v_subrev_u32_e32 v8, vcc, v2, v0
+; TONGA-NEXT:    v_subrev_u32_e32 v6, vcc, v2, v0
 ; TONGA-NEXT:    v_cndmask_b32_e64 v5, v5, v9, s[0:1]
-; TONGA-NEXT:    v_cndmask_b32_e64 v0, v0, v8, s[0:1]
-; TONGA-NEXT:    v_add_u32_e32 v8, vcc, 1, v5
+; TONGA-NEXT:    v_cndmask_b32_e64 v0, v0, v6, s[0:1]
+; TONGA-NEXT:    v_add_u32_e32 v6, vcc, 1, v5
 ; TONGA-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
 ; TONGA-NEXT:    s_mov_b64 s[0:1], vcc
-; TONGA-NEXT:    v_add_u32_e32 v0, vcc, v6, v3
-; TONGA-NEXT:    v_xor_b32_e32 v2, v0, v6
+; TONGA-NEXT:    v_add_u32_e32 v0, vcc, v8, v3
+; TONGA-NEXT:    v_xor_b32_e32 v2, v0, v8
 ; TONGA-NEXT:    v_cvt_f32_u32_e32 v0, v2
-; TONGA-NEXT:    v_sub_u32_e32 v9, vcc, 0, v2
-; TONGA-NEXT:    v_ashrrev_i32_e32 v3, 31, v1
-; TONGA-NEXT:    v_add_u32_e32 v1, vcc, v3, v1
+; TONGA-NEXT:    v_sub_u32_e32 v3, vcc, 0, v2
+; TONGA-NEXT:    v_ashrrev_i32_e32 v9, 31, v1
+; TONGA-NEXT:    v_add_u32_e32 v1, vcc, v9, v1
 ; TONGA-NEXT:    v_rcp_iflag_f32_e32 v0, v0
-; TONGA-NEXT:    v_xor_b32_e32 v1, v1, v3
-; TONGA-NEXT:    v_xor_b32_e32 v6, v3, v6
-; TONGA-NEXT:    v_cndmask_b32_e64 v5, v5, v8, s[0:1]
+; TONGA-NEXT:    v_xor_b32_e32 v1, v1, v9
+; TONGA-NEXT:    v_cndmask_b32_e64 v5, v5, v6, s[0:1]
 ; TONGA-NEXT:    v_mul_f32_e32 v0, s2, v0
 ; TONGA-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; TONGA-NEXT:    v_mul_lo_u32 v9, v9, v0
-; TONGA-NEXT:    v_mul_hi_u32 v7, v0, v9
-; TONGA-NEXT:    v_add_u32_e32 v0, vcc, v7, v0
+; TONGA-NEXT:    v_mul_lo_u32 v3, v3, v0
+; TONGA-NEXT:    v_mul_hi_u32 v3, v0, v3
+; TONGA-NEXT:    v_add_u32_e32 v0, vcc, v3, v0
 ; TONGA-NEXT:    v_mul_hi_u32 v3, v1, v0
-; TONGA-NEXT:    v_xor_b32_e32 v0, v5, v4
-; TONGA-NEXT:    v_sub_u32_e32 v0, vcc, v0, v4
-; TONGA-NEXT:    v_mul_lo_u32 v4, v3, v2
+; TONGA-NEXT:    v_xor_b32_e32 v0, v7, v4
+; TONGA-NEXT:    v_xor_b32_e32 v5, v5, v0
+; TONGA-NEXT:    v_sub_u32_e32 v0, vcc, v5, v0
+; TONGA-NEXT:    v_mul_lo_u32 v6, v3, v2
 ; TONGA-NEXT:    v_add_u32_e32 v5, vcc, 1, v3
-; TONGA-NEXT:    v_subrev_u32_e32 v1, vcc, v4, v1
+; TONGA-NEXT:    v_xor_b32_e32 v4, v9, v8
+; TONGA-NEXT:    v_subrev_u32_e32 v1, vcc, v6, v1
 ; TONGA-NEXT:    v_cmp_ge_u32_e64 s[0:1], v1, v2
-; TONGA-NEXT:    v_subrev_u32_e32 v4, vcc, v2, v1
 ; TONGA-NEXT:    v_cndmask_b32_e64 v3, v3, v5, s[0:1]
-; TONGA-NEXT:    v_cndmask_b32_e64 v1, v1, v4, s[0:1]
-; TONGA-NEXT:    v_add_u32_e32 v4, vcc, 1, v3
+; TONGA-NEXT:    v_subrev_u32_e32 v5, vcc, v2, v1
+; TONGA-NEXT:    v_cndmask_b32_e64 v1, v1, v5, s[0:1]
+; TONGA-NEXT:    v_add_u32_e32 v5, vcc, 1, v3
 ; TONGA-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v2
-; TONGA-NEXT:    v_cndmask_b32_e32 v1, v3, v4, vcc
-; TONGA-NEXT:    v_xor_b32_e32 v1, v1, v6
-; TONGA-NEXT:    v_sub_u32_e32 v1, vcc, v1, v6
+; TONGA-NEXT:    v_cndmask_b32_e32 v1, v3, v5, vcc
+; TONGA-NEXT:    v_xor_b32_e32 v1, v1, v4
+; TONGA-NEXT:    v_sub_u32_e32 v1, vcc, v1, v4
 ; TONGA-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; TONGA-NEXT:    s_endpgm
 ;
@@ -815,117 +815,117 @@
 ; GCN-NEXT:    s_waitcnt vmcnt(1)
 ; GCN-NEXT:    v_ashrrev_i32_e32 v8, 31, v0
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    v_ashrrev_i32_e32 v11, 31, v5
 ; GCN-NEXT:    v_ashrrev_i32_e32 v9, 31, v4
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, v11, v5
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v9, v4
-; GCN-NEXT:    v_xor_b32_e32 v5, v5, v11
-; GCN-NEXT:    v_xor_b32_e32 v15, v8, v9
-; GCN-NEXT:    v_xor_b32_e32 v4, v4, v9
-; GCN-NEXT:    v_cvt_f32_u32_e32 v9, v5
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, v8, v0
+; GCN-NEXT:    v_xor_b32_e32 v4, v4, v9
+; GCN-NEXT:    v_xor_b32_e32 v16, v8, v9
 ; GCN-NEXT:    v_xor_b32_e32 v0, v0, v8
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v8, v4
-; GCN-NEXT:    v_rcp_iflag_f32_e32 v9, v9
+; GCN-NEXT:    v_ashrrev_i32_e32 v11, 31, v5
 ; GCN-NEXT:    v_ashrrev_i32_e32 v13, 31, v6
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, v13, v6
+; GCN-NEXT:    v_ashrrev_i32_e32 v15, 31, v7
 ; GCN-NEXT:    v_ashrrev_i32_e32 v10, 31, v1
-; GCN-NEXT:    v_rcp_iflag_f32_e32 v8, v8
-; GCN-NEXT:    v_mul_f32_e32 v9, s2, v9
-; GCN-NEXT:    v_xor_b32_e32 v6, v6, v13
-; GCN-NEXT:    v_xor_b32_e32 v16, v10, v11
-; GCN-NEXT:    v_cvt_f32_u32_e32 v11, v6
-; GCN-NEXT:    v_cvt_u32_f32_e32 v9, v9
 ; GCN-NEXT:    v_ashrrev_i32_e32 v12, 31, v2
+; GCN-NEXT:    v_ashrrev_i32_e32 v14, 31, v3
+; GCN-NEXT:    v_add_i32_e32 v5, vcc, v11, v5
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v13, v6
+; GCN-NEXT:    v_add_i32_e32 v7, vcc, v15, v7
+; GCN-NEXT:    v_add_i32_e32 v1, vcc, v10, v1
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v12, v2
-; GCN-NEXT:    v_mul_f32_e32 v8, s2, v8
-; GCN-NEXT:    v_xor_b32_e32 v17, v12, v13
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v14, v3
+; GCN-NEXT:    v_xor_b32_e32 v5, v5, v11
+; GCN-NEXT:    v_xor_b32_e32 v6, v6, v13
+; GCN-NEXT:    v_xor_b32_e32 v7, v7, v15
+; GCN-NEXT:    v_rcp_iflag_f32_e32 v8, v8
+; GCN-NEXT:    v_xor_b32_e32 v17, v10, v11
+; GCN-NEXT:    v_xor_b32_e32 v18, v12, v13
+; GCN-NEXT:    v_xor_b32_e32 v19, v14, v15
+; GCN-NEXT:    v_xor_b32_e32 v1, v1, v10
+; GCN-NEXT:    v_cvt_f32_u32_e32 v10, v5
 ; GCN-NEXT:    v_xor_b32_e32 v2, v2, v12
-; GCN-NEXT:    v_sub_i32_e32 v12, vcc, 0, v5
-; GCN-NEXT:    v_rcp_iflag_f32_e32 v11, v11
-; GCN-NEXT:    v_mul_lo_u32 v12, v12, v9
+; GCN-NEXT:    v_cvt_f32_u32_e32 v12, v6
+; GCN-NEXT:    v_xor_b32_e32 v3, v3, v14
+; GCN-NEXT:    v_cvt_f32_u32_e32 v14, v7
+; GCN-NEXT:    v_rcp_iflag_f32_e32 v10, v10
+; GCN-NEXT:    v_rcp_iflag_f32_e32 v12, v12
+; GCN-NEXT:    v_mul_f32_e32 v8, s2, v8
+; GCN-NEXT:    v_rcp_iflag_f32_e32 v14, v14
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v8, v8
-; GCN-NEXT:    v_add_i32_e32 v1, vcc, v10, v1
-; GCN-NEXT:    v_xor_b32_e32 v1, v1, v10
-; GCN-NEXT:    v_sub_i32_e32 v10, vcc, 0, v4
-; GCN-NEXT:    v_mul_lo_u32 v10, v10, v8
-; GCN-NEXT:    v_mul_hi_u32 v12, v9, v12
-; GCN-NEXT:    v_mul_f32_e32 v11, s2, v11
-; GCN-NEXT:    v_cvt_u32_f32_e32 v11, v11
-; GCN-NEXT:    v_mul_hi_u32 v10, v8, v10
-; GCN-NEXT:    v_add_i32_e32 v9, vcc, v12, v9
-; GCN-NEXT:    v_sub_i32_e32 v12, vcc, 0, v6
-; GCN-NEXT:    v_mul_lo_u32 v12, v12, v11
-; GCN-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
+; GCN-NEXT:    v_sub_i32_e32 v9, vcc, 0, v4
+; GCN-NEXT:    v_mul_f32_e32 v10, s2, v10
+; GCN-NEXT:    v_mul_f32_e32 v12, s2, v12
+; GCN-NEXT:    v_mul_f32_e32 v14, s2, v14
+; GCN-NEXT:    v_mul_lo_u32 v9, v9, v8
+; GCN-NEXT:    v_cvt_u32_f32_e32 v10, v10
+; GCN-NEXT:    v_cvt_u32_f32_e32 v12, v12
+; GCN-NEXT:    v_cvt_u32_f32_e32 v14, v14
+; GCN-NEXT:    v_sub_i32_e32 v11, vcc, 0, v5
+; GCN-NEXT:    v_sub_i32_e32 v13, vcc, 0, v6
+; GCN-NEXT:    v_sub_i32_e32 v15, vcc, 0, v7
+; GCN-NEXT:    v_mul_lo_u32 v11, v11, v10
+; GCN-NEXT:    v_mul_lo_u32 v13, v13, v12
+; GCN-NEXT:    v_mul_lo_u32 v15, v15, v14
+; GCN-NEXT:    v_mul_hi_u32 v9, v8, v9
+; GCN-NEXT:    v_mul_hi_u32 v11, v10, v11
+; GCN-NEXT:    v_mul_hi_u32 v13, v12, v13
+; GCN-NEXT:    v_mul_hi_u32 v15, v14, v15
+; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
 ; GCN-NEXT:    v_mul_hi_u32 v8, v0, v8
-; GCN-NEXT:    v_ashrrev_i32_e32 v14, 31, v7
-; GCN-NEXT:    v_mul_hi_u32 v12, v11, v12
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, v14, v7
-; GCN-NEXT:    v_xor_b32_e32 v7, v7, v14
-; GCN-NEXT:    v_cvt_f32_u32_e32 v10, v7
-; GCN-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
-; GCN-NEXT:    v_mul_lo_u32 v12, v8, v4
+; GCN-NEXT:    v_add_i32_e32 v9, vcc, v11, v10
+; GCN-NEXT:    v_add_i32_e32 v10, vcc, v13, v12
+; GCN-NEXT:    v_add_i32_e32 v11, vcc, v15, v14
 ; GCN-NEXT:    v_mul_hi_u32 v9, v1, v9
-; GCN-NEXT:    v_rcp_iflag_f32_e32 v10, v10
-; GCN-NEXT:    v_mul_hi_u32 v11, v2, v11
+; GCN-NEXT:    v_mul_hi_u32 v10, v2, v10
+; GCN-NEXT:    v_mul_lo_u32 v12, v8, v4
+; GCN-NEXT:    v_mul_hi_u32 v11, v3, v11
+; GCN-NEXT:    v_mul_lo_u32 v14, v9, v5
+; GCN-NEXT:    v_mul_lo_u32 v15, v10, v6
 ; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v12
-; GCN-NEXT:    v_add_i32_e32 v12, vcc, 1, v8
-; GCN-NEXT:    v_cmp_ge_u32_e64 s[0:1], v0, v4
-; GCN-NEXT:    v_cndmask_b32_e64 v8, v8, v12, s[0:1]
-; GCN-NEXT:    v_sub_i32_e32 v12, vcc, v0, v4
-; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v12, s[0:1]
+; GCN-NEXT:    v_mul_lo_u32 v12, v11, v7
+; GCN-NEXT:    v_sub_i32_e32 v1, vcc, v1, v14
+; GCN-NEXT:    v_sub_i32_e32 v2, vcc, v2, v15
+; GCN-NEXT:    v_add_i32_e32 v13, vcc, 1, v8
+; GCN-NEXT:    v_sub_i32_e32 v3, vcc, v3, v12
 ; GCN-NEXT:    v_cmp_ge_u32_e64 s[0:1], v0, v4
-; GCN-NEXT:    v_mul_lo_u32 v0, v9, v5
-; GCN-NEXT:    v_mul_f32_e32 v10, s2, v10
-; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v10
-; GCN-NEXT:    v_mul_lo_u32 v10, v11, v6
-; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v1, v0
-; GCN-NEXT:    v_add_i32_e32 v1, vcc, 1, v9
-; GCN-NEXT:    v_cmp_ge_u32_e64 s[2:3], v0, v5
-; GCN-NEXT:    v_sub_i32_e32 v2, vcc, v2, v10
-; GCN-NEXT:    v_cndmask_b32_e64 v1, v9, v1, s[2:3]
-; GCN-NEXT:    v_sub_i32_e32 v9, vcc, v0, v5
-; GCN-NEXT:    v_add_i32_e32 v10, vcc, 1, v11
+; GCN-NEXT:    v_add_i32_e32 v14, vcc, 1, v9
+; GCN-NEXT:    v_cmp_ge_u32_e64 s[2:3], v1, v5
+; GCN-NEXT:    v_add_i32_e32 v15, vcc, 1, v10
 ; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v2, v6
-; GCN-NEXT:    v_add_i32_e32 v12, vcc, 1, v8
-; GCN-NEXT:    v_cndmask_b32_e64 v10, v11, v10, s[4:5]
-; GCN-NEXT:    v_sub_i32_e32 v11, vcc, v2, v6
-; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v9, s[2:3]
-; GCN-NEXT:    v_add_i32_e32 v9, vcc, 1, v1
-; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v5
-; GCN-NEXT:    v_cndmask_b32_e32 v0, v1, v9, vcc
-; GCN-NEXT:    v_cndmask_b32_e64 v8, v8, v12, s[0:1]
-; GCN-NEXT:    v_xor_b32_e32 v1, v8, v15
-; GCN-NEXT:    v_xor_b32_e32 v5, v0, v16
-; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v1, v15
-; GCN-NEXT:    v_sub_i32_e32 v1, vcc, v5, v16
-; GCN-NEXT:    v_sub_i32_e32 v5, vcc, 0, v7
-; GCN-NEXT:    v_mul_lo_u32 v5, v5, v4
-; GCN-NEXT:    v_ashrrev_i32_e32 v9, 31, v3
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v9, v3
-; GCN-NEXT:    v_xor_b32_e32 v3, v3, v9
-; GCN-NEXT:    v_mul_hi_u32 v5, v4, v5
-; GCN-NEXT:    v_cndmask_b32_e64 v2, v2, v11, s[4:5]
-; GCN-NEXT:    v_add_i32_e32 v8, vcc, 1, v10
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GCN-NEXT:    v_mul_hi_u32 v4, v3, v4
+; GCN-NEXT:    v_add_i32_e32 v12, vcc, 1, v11
+; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v3, v7
+; GCN-NEXT:    v_cndmask_b32_e64 v8, v8, v13, s[0:1]
+; GCN-NEXT:    v_sub_i32_e32 v13, vcc, v0, v4
+; GCN-NEXT:    v_cndmask_b32_e64 v9, v9, v14, s[2:3]
+; GCN-NEXT:    v_sub_i32_e32 v14, vcc, v1, v5
+; GCN-NEXT:    v_cndmask_b32_e64 v10, v10, v15, s[4:5]
+; GCN-NEXT:    v_sub_i32_e32 v15, vcc, v2, v6
+; GCN-NEXT:    v_cndmask_b32_e64 v11, v11, v12, s[6:7]
+; GCN-NEXT:    v_sub_i32_e32 v12, vcc, v3, v7
+; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v13, s[0:1]
+; GCN-NEXT:    v_cndmask_b32_e64 v1, v1, v14, s[2:3]
+; GCN-NEXT:    v_cndmask_b32_e64 v2, v2, v15, s[4:5]
+; GCN-NEXT:    v_cndmask_b32_e64 v3, v3, v12, s[6:7]
+; GCN-NEXT:    v_add_i32_e32 v13, vcc, 1, v8
+; GCN-NEXT:    v_add_i32_e32 v14, vcc, 1, v9
+; GCN-NEXT:    v_add_i32_e32 v15, vcc, 1, v10
+; GCN-NEXT:    v_add_i32_e32 v12, vcc, 1, v11
+; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v4
+; GCN-NEXT:    v_cndmask_b32_e32 v0, v8, v13, vcc
+; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v5
+; GCN-NEXT:    v_cndmask_b32_e32 v1, v9, v14, vcc
 ; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v2, v6
-; GCN-NEXT:    v_cndmask_b32_e32 v2, v10, v8, vcc
-; GCN-NEXT:    v_xor_b32_e32 v2, v2, v17
-; GCN-NEXT:    v_mul_lo_u32 v5, v4, v7
-; GCN-NEXT:    v_sub_i32_e32 v2, vcc, v2, v17
-; GCN-NEXT:    v_xor_b32_e32 v6, v9, v14
-; GCN-NEXT:    v_sub_i32_e32 v3, vcc, v3, v5
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, 1, v4
-; GCN-NEXT:    v_cmp_ge_u32_e64 s[0:1], v3, v7
-; GCN-NEXT:    v_cndmask_b32_e64 v4, v4, v5, s[0:1]
-; GCN-NEXT:    v_sub_i32_e32 v5, vcc, v3, v7
-; GCN-NEXT:    v_cndmask_b32_e64 v3, v3, v5, s[0:1]
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, 1, v4
+; GCN-NEXT:    v_cndmask_b32_e32 v2, v10, v15, vcc
 ; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v3, v7
-; GCN-NEXT:    v_cndmask_b32_e32 v3, v4, v5, vcc
-; GCN-NEXT:    v_xor_b32_e32 v3, v3, v6
-; GCN-NEXT:    v_sub_i32_e32 v3, vcc, v3, v6
+; GCN-NEXT:    v_cndmask_b32_e32 v3, v11, v12, vcc
+; GCN-NEXT:    v_xor_b32_e32 v0, v0, v16
+; GCN-NEXT:    v_xor_b32_e32 v1, v1, v17
+; GCN-NEXT:    v_xor_b32_e32 v2, v2, v18
+; GCN-NEXT:    v_xor_b32_e32 v3, v3, v19
+; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v16
+; GCN-NEXT:    v_sub_i32_e32 v1, vcc, v1, v17
+; GCN-NEXT:    v_sub_i32_e32 v2, vcc, v2, v18
+; GCN-NEXT:    v_sub_i32_e32 v3, vcc, v3, v19
 ; GCN-NEXT:    buffer_store_dwordx4 v[0:3], off, s[8:11], 0
 ; GCN-NEXT:    s_endpgm
 ;
@@ -940,77 +940,74 @@
 ; TONGA-NEXT:    s_mov_b32 s0, s10
 ; TONGA-NEXT:    s_mov_b32 s1, s11
 ; TONGA-NEXT:    buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:16
-; TONGA-NEXT:    s_mov_b32 s10, 0x4f7ffffe
-; TONGA-NEXT:    s_mov_b32 s4, s8
+; TONGA-NEXT:    s_mov_b32 s4, 0x4f7ffffe
 ; TONGA-NEXT:    s_mov_b32 s5, s9
 ; TONGA-NEXT:    s_waitcnt vmcnt(0)
 ; TONGA-NEXT:    v_ashrrev_i32_e32 v8, 31, v0
 ; TONGA-NEXT:    v_add_u32_e32 v0, vcc, v8, v0
 ; TONGA-NEXT:    v_xor_b32_e32 v0, v0, v8
 ; TONGA-NEXT:    v_cvt_f32_u32_e32 v4, v0
+; TONGA-NEXT:    v_ashrrev_i32_e32 v12, 31, v1
 ; TONGA-NEXT:    v_ashrrev_i32_e32 v14, 31, v2
 ; TONGA-NEXT:    v_rcp_iflag_f32_e32 v4, v4
-; TONGA-NEXT:    v_mul_f32_e32 v4, s10, v4
+; TONGA-NEXT:    v_mul_f32_e32 v4, s4, v4
 ; TONGA-NEXT:    v_cvt_u32_f32_e32 v9, v4
 ; TONGA-NEXT:    v_sub_u32_e32 v4, vcc, 0, v0
 ; TONGA-NEXT:    v_mul_lo_u32 v10, v4, v9
 ; TONGA-NEXT:    buffer_load_dwordx4 v[4:7], off, s[0:3], 0
 ; TONGA-NEXT:    v_mul_hi_u32 v10, v9, v10
 ; TONGA-NEXT:    v_add_u32_e32 v9, vcc, v10, v9
-; TONGA-NEXT:    v_ashrrev_i32_e32 v10, 31, v1
 ; TONGA-NEXT:    s_waitcnt vmcnt(0)
 ; TONGA-NEXT:    v_ashrrev_i32_e32 v11, 31, v4
 ; TONGA-NEXT:    v_add_u32_e32 v4, vcc, v11, v4
 ; TONGA-NEXT:    v_xor_b32_e32 v4, v4, v11
 ; TONGA-NEXT:    v_mul_hi_u32 v9, v4, v9
-; TONGA-NEXT:    v_xor_b32_e32 v8, v11, v8
-; TONGA-NEXT:    v_mul_lo_u32 v12, v9, v0
+; TONGA-NEXT:    v_mul_lo_u32 v10, v9, v0
 ; TONGA-NEXT:    v_add_u32_e32 v13, vcc, 1, v9
-; TONGA-NEXT:    v_sub_u32_e32 v4, vcc, v4, v12
+; TONGA-NEXT:    v_sub_u32_e32 v4, vcc, v4, v10
 ; TONGA-NEXT:    v_cmp_ge_u32_e64 s[0:1], v4, v0
-; TONGA-NEXT:    v_sub_u32_e32 v12, vcc, v4, v0
+; TONGA-NEXT:    v_sub_u32_e32 v10, vcc, v4, v0
 ; TONGA-NEXT:    v_cndmask_b32_e64 v9, v9, v13, s[0:1]
-; TONGA-NEXT:    v_cndmask_b32_e64 v4, v4, v12, s[0:1]
-; TONGA-NEXT:    v_add_u32_e32 v12, vcc, 1, v9
+; TONGA-NEXT:    v_cndmask_b32_e64 v4, v4, v10, s[0:1]
+; TONGA-NEXT:    v_add_u32_e32 v10, vcc, 1, v9
 ; TONGA-NEXT:    v_cmp_ge_u32_e32 vcc, v4, v0
 ; TONGA-NEXT:    s_mov_b64 s[0:1], vcc
-; TONGA-NEXT:    v_add_u32_e32 v0, vcc, v10, v1
-; TONGA-NEXT:    v_xor_b32_e32 v1, v0, v10
+; TONGA-NEXT:    v_add_u32_e32 v0, vcc, v12, v1
+; TONGA-NEXT:    v_xor_b32_e32 v1, v0, v12
 ; TONGA-NEXT:    v_cvt_f32_u32_e32 v0, v1
-; TONGA-NEXT:    v_sub_u32_e32 v13, vcc, 0, v1
-; TONGA-NEXT:    v_ashrrev_i32_e32 v4, 31, v5
-; TONGA-NEXT:    v_add_u32_e32 v5, vcc, v4, v5
+; TONGA-NEXT:    v_sub_u32_e32 v4, vcc, 0, v1
+; TONGA-NEXT:    v_ashrrev_i32_e32 v13, 31, v5
+; TONGA-NEXT:    v_add_u32_e32 v5, vcc, v13, v5
 ; TONGA-NEXT:    v_rcp_iflag_f32_e32 v0, v0
-; TONGA-NEXT:    v_xor_b32_e32 v5, v5, v4
-; TONGA-NEXT:    v_cndmask_b32_e64 v9, v9, v12, s[0:1]
-; TONGA-NEXT:    v_xor_b32_e32 v4, v4, v10
-; TONGA-NEXT:    v_mul_f32_e32 v0, s10, v0
+; TONGA-NEXT:    v_xor_b32_e32 v5, v5, v13
+; TONGA-NEXT:    v_mul_f32_e32 v0, s4, v0
 ; TONGA-NEXT:    v_cvt_u32_f32_e32 v0, v0
+; TONGA-NEXT:    v_mul_lo_u32 v4, v4, v0
+; TONGA-NEXT:    v_mul_hi_u32 v4, v0, v4
+; TONGA-NEXT:    v_add_u32_e32 v0, vcc, v4, v0
+; TONGA-NEXT:    v_mul_hi_u32 v4, v5, v0
+; TONGA-NEXT:    v_xor_b32_e32 v0, v11, v8
+; TONGA-NEXT:    v_cndmask_b32_e64 v8, v9, v10, s[0:1]
+; TONGA-NEXT:    v_xor_b32_e32 v8, v8, v0
+; TONGA-NEXT:    v_mul_lo_u32 v9, v4, v1
+; TONGA-NEXT:    v_subrev_u32_e32 v0, vcc, v0, v8
+; TONGA-NEXT:    v_add_u32_e32 v8, vcc, 1, v4
 ; TONGA-NEXT:    v_ashrrev_i32_e32 v10, 31, v6
-; TONGA-NEXT:    v_mul_lo_u32 v13, v13, v0
-; TONGA-NEXT:    v_mul_hi_u32 v11, v0, v13
-; TONGA-NEXT:    v_add_u32_e32 v0, vcc, v11, v0
-; TONGA-NEXT:    v_mul_hi_u32 v11, v5, v0
-; TONGA-NEXT:    v_xor_b32_e32 v0, v9, v8
-; TONGA-NEXT:    v_subrev_u32_e32 v0, vcc, v8, v0
-; TONGA-NEXT:    v_mul_lo_u32 v8, v11, v1
-; TONGA-NEXT:    v_add_u32_e32 v9, vcc, 1, v11
-; TONGA-NEXT:    v_sub_u32_e32 v5, vcc, v5, v8
+; TONGA-NEXT:    v_sub_u32_e32 v5, vcc, v5, v9
 ; TONGA-NEXT:    v_cmp_ge_u32_e64 s[0:1], v5, v1
-; TONGA-NEXT:    v_cndmask_b32_e64 v8, v11, v9, s[0:1]
-; TONGA-NEXT:    v_sub_u32_e32 v9, vcc, v5, v1
-; TONGA-NEXT:    v_cndmask_b32_e64 v5, v5, v9, s[0:1]
-; TONGA-NEXT:    v_add_u32_e32 v9, vcc, 1, v8
+; TONGA-NEXT:    v_cndmask_b32_e64 v4, v4, v8, s[0:1]
+; TONGA-NEXT:    v_sub_u32_e32 v8, vcc, v5, v1
+; TONGA-NEXT:    v_cndmask_b32_e64 v5, v5, v8, s[0:1]
+; TONGA-NEXT:    v_add_u32_e32 v8, vcc, 1, v4
 ; TONGA-NEXT:    v_cmp_ge_u32_e32 vcc, v5, v1
 ; TONGA-NEXT:    s_mov_b64 s[0:1], vcc
 ; TONGA-NEXT:    v_add_u32_e32 v1, vcc, v14, v2
 ; TONGA-NEXT:    v_xor_b32_e32 v2, v1, v14
 ; TONGA-NEXT:    v_cvt_f32_u32_e32 v1, v2
 ; TONGA-NEXT:    v_sub_u32_e32 v5, vcc, 0, v2
-; TONGA-NEXT:    v_cndmask_b32_e64 v8, v8, v9, s[0:1]
-; TONGA-NEXT:    v_ashrrev_i32_e32 v9, 31, v3
+; TONGA-NEXT:    v_xor_b32_e32 v9, v13, v12
 ; TONGA-NEXT:    v_rcp_iflag_f32_e32 v1, v1
-; TONGA-NEXT:    v_mul_f32_e32 v1, s10, v1
+; TONGA-NEXT:    v_mul_f32_e32 v1, s4, v1
 ; TONGA-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; TONGA-NEXT:    v_mul_lo_u32 v5, v5, v1
 ; TONGA-NEXT:    v_mul_hi_u32 v5, v1, v5
@@ -1018,49 +1015,52 @@
 ; TONGA-NEXT:    v_add_u32_e32 v5, vcc, v10, v6
 ; TONGA-NEXT:    v_xor_b32_e32 v5, v5, v10
 ; TONGA-NEXT:    v_mul_hi_u32 v6, v5, v1
-; TONGA-NEXT:    v_xor_b32_e32 v1, v8, v4
-; TONGA-NEXT:    v_subrev_u32_e32 v1, vcc, v4, v1
-; TONGA-NEXT:    v_xor_b32_e32 v10, v10, v14
+; TONGA-NEXT:    v_cndmask_b32_e64 v1, v4, v8, s[0:1]
+; TONGA-NEXT:    v_xor_b32_e32 v1, v1, v9
+; TONGA-NEXT:    v_subrev_u32_e32 v1, vcc, v9, v1
 ; TONGA-NEXT:    v_mul_lo_u32 v4, v6, v2
-; TONGA-NEXT:    v_add_u32_e32 v8, vcc, 1, v6
+; TONGA-NEXT:    v_add_u32_e32 v9, vcc, 1, v6
+; TONGA-NEXT:    v_ashrrev_i32_e32 v8, 31, v3
 ; TONGA-NEXT:    v_sub_u32_e32 v4, vcc, v5, v4
 ; TONGA-NEXT:    v_cmp_ge_u32_e64 s[0:1], v4, v2
-; TONGA-NEXT:    v_cndmask_b32_e64 v5, v6, v8, s[0:1]
+; TONGA-NEXT:    v_cndmask_b32_e64 v5, v6, v9, s[0:1]
 ; TONGA-NEXT:    v_sub_u32_e32 v6, vcc, v4, v2
 ; TONGA-NEXT:    v_cndmask_b32_e64 v4, v4, v6, s[0:1]
 ; TONGA-NEXT:    v_add_u32_e32 v6, vcc, 1, v5
 ; TONGA-NEXT:    v_cmp_ge_u32_e32 vcc, v4, v2
 ; TONGA-NEXT:    s_mov_b64 s[0:1], vcc
-; TONGA-NEXT:    v_add_u32_e32 v2, vcc, v9, v3
-; TONGA-NEXT:    v_xor_b32_e32 v3, v2, v9
+; TONGA-NEXT:    v_add_u32_e32 v2, vcc, v8, v3
+; TONGA-NEXT:    v_xor_b32_e32 v3, v2, v8
 ; TONGA-NEXT:    v_cvt_f32_u32_e32 v2, v3
-; TONGA-NEXT:    v_sub_u32_e32 v8, vcc, 0, v3
-; TONGA-NEXT:    v_cndmask_b32_e64 v5, v5, v6, s[0:1]
-; TONGA-NEXT:    v_ashrrev_i32_e32 v4, 31, v7
+; TONGA-NEXT:    v_sub_u32_e32 v4, vcc, 0, v3
+; TONGA-NEXT:    v_ashrrev_i32_e32 v9, 31, v7
+; TONGA-NEXT:    v_add_u32_e32 v7, vcc, v9, v7
 ; TONGA-NEXT:    v_rcp_iflag_f32_e32 v2, v2
-; TONGA-NEXT:    v_add_u32_e32 v7, vcc, v4, v7
-; TONGA-NEXT:    v_xor_b32_e32 v9, v4, v9
-; TONGA-NEXT:    v_xor_b32_e32 v4, v7, v4
-; TONGA-NEXT:    v_mul_f32_e32 v2, s10, v2
+; TONGA-NEXT:    v_xor_b32_e32 v7, v7, v9
+; TONGA-NEXT:    v_cndmask_b32_e64 v5, v5, v6, s[0:1]
+; TONGA-NEXT:    v_xor_b32_e32 v8, v9, v8
+; TONGA-NEXT:    v_mul_f32_e32 v2, s4, v2
 ; TONGA-NEXT:    v_cvt_u32_f32_e32 v2, v2
-; TONGA-NEXT:    v_mul_lo_u32 v8, v8, v2
-; TONGA-NEXT:    v_mul_hi_u32 v6, v2, v8
-; TONGA-NEXT:    v_add_u32_e32 v2, vcc, v6, v2
-; TONGA-NEXT:    v_mul_hi_u32 v6, v4, v2
-; TONGA-NEXT:    v_xor_b32_e32 v2, v5, v10
-; TONGA-NEXT:    v_subrev_u32_e32 v2, vcc, v10, v2
-; TONGA-NEXT:    v_mul_lo_u32 v5, v6, v3
-; TONGA-NEXT:    v_add_u32_e32 v7, vcc, 1, v6
-; TONGA-NEXT:    v_sub_u32_e32 v4, vcc, v4, v5
-; TONGA-NEXT:    v_cmp_ge_u32_e64 s[0:1], v4, v3
-; TONGA-NEXT:    v_cndmask_b32_e64 v5, v6, v7, s[0:1]
-; TONGA-NEXT:    v_sub_u32_e32 v6, vcc, v4, v3
-; TONGA-NEXT:    v_cndmask_b32_e64 v4, v4, v6, s[0:1]
-; TONGA-NEXT:    v_add_u32_e32 v6, vcc, 1, v5
-; TONGA-NEXT:    v_cmp_ge_u32_e32 vcc, v4, v3
-; TONGA-NEXT:    v_cndmask_b32_e32 v3, v5, v6, vcc
-; TONGA-NEXT:    v_xor_b32_e32 v3, v3, v9
-; TONGA-NEXT:    v_subrev_u32_e32 v3, vcc, v9, v3
+; TONGA-NEXT:    s_mov_b32 s4, s8
+; TONGA-NEXT:    v_mul_lo_u32 v4, v4, v2
+; TONGA-NEXT:    v_mul_hi_u32 v4, v2, v4
+; TONGA-NEXT:    v_add_u32_e32 v2, vcc, v4, v2
+; TONGA-NEXT:    v_mul_hi_u32 v4, v7, v2
+; TONGA-NEXT:    v_xor_b32_e32 v2, v10, v14
+; TONGA-NEXT:    v_xor_b32_e32 v5, v5, v2
+; TONGA-NEXT:    v_subrev_u32_e32 v2, vcc, v2, v5
+; TONGA-NEXT:    v_mul_lo_u32 v6, v4, v3
+; TONGA-NEXT:    v_add_u32_e32 v5, vcc, 1, v4
+; TONGA-NEXT:    v_sub_u32_e32 v6, vcc, v7, v6
+; TONGA-NEXT:    v_cmp_ge_u32_e64 s[0:1], v6, v3
+; TONGA-NEXT:    v_cndmask_b32_e64 v4, v4, v5, s[0:1]
+; TONGA-NEXT:    v_sub_u32_e32 v5, vcc, v6, v3
+; TONGA-NEXT:    v_cndmask_b32_e64 v5, v6, v5, s[0:1]
+; TONGA-NEXT:    v_add_u32_e32 v6, vcc, 1, v4
+; TONGA-NEXT:    v_cmp_ge_u32_e32 vcc, v5, v3
+; TONGA-NEXT:    v_cndmask_b32_e32 v3, v4, v6, vcc
+; TONGA-NEXT:    v_xor_b32_e32 v3, v3, v8
+; TONGA-NEXT:    v_subrev_u32_e32 v3, vcc, v8, v3
 ; TONGA-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
 ; TONGA-NEXT:    s_endpgm
 ;
@@ -1489,11 +1489,11 @@
 ; GCN-NEXT:    v_rcp_iflag_f32_e32 v4, v2
 ; GCN-NEXT:    v_mul_f32_e32 v1, v3, v4
 ; GCN-NEXT:    v_trunc_f32_e32 v1, v1
-; GCN-NEXT:    v_mad_f32 v3, -v1, v2, v3
-; GCN-NEXT:    v_cvt_i32_f32_e32 v1, v1
-; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v2|
+; GCN-NEXT:    v_cvt_i32_f32_e32 v4, v1
+; GCN-NEXT:    v_mad_f32 v1, -v1, v2, v3
+; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v2|
 ; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
 ; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 8
 ; GCN-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GCN-NEXT:    s_endpgm
@@ -1522,11 +1522,11 @@
 ; TONGA-NEXT:    v_rcp_iflag_f32_e32 v4, v2
 ; TONGA-NEXT:    v_mul_f32_e32 v1, v3, v4
 ; TONGA-NEXT:    v_trunc_f32_e32 v1, v1
-; TONGA-NEXT:    v_mad_f32 v3, -v1, v2, v3
-; TONGA-NEXT:    v_cvt_i32_f32_e32 v1, v1
-; TONGA-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v2|
+; TONGA-NEXT:    v_cvt_i32_f32_e32 v4, v1
+; TONGA-NEXT:    v_mad_f32 v1, -v1, v2, v3
+; TONGA-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v2|
 ; TONGA-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
-; TONGA-NEXT:    v_add_u32_e32 v0, vcc, v1, v0
+; TONGA-NEXT:    v_add_u32_e32 v0, vcc, v4, v0
 ; TONGA-NEXT:    v_bfe_i32 v0, v0, 0, 8
 ; TONGA-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; TONGA-NEXT:    s_endpgm
@@ -1642,11 +1642,11 @@
 ; GCN-NEXT:    v_or_b32_e32 v0, 1, v0
 ; GCN-NEXT:    v_mul_f32_e32 v2, v1, v4
 ; GCN-NEXT:    v_trunc_f32_e32 v2, v2
+; GCN-NEXT:    v_cvt_i32_f32_e32 v4, v2
 ; GCN-NEXT:    v_mad_f32 v1, -v2, v3, v1
-; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
 ; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v3|
 ; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
 ; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 23
 ; GCN-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GCN-NEXT:    s_endpgm
@@ -1683,11 +1683,11 @@
 ; TONGA-NEXT:    v_or_b32_e32 v0, 1, v0
 ; TONGA-NEXT:    v_mul_f32_e32 v2, v1, v4
 ; TONGA-NEXT:    v_trunc_f32_e32 v2, v2
+; TONGA-NEXT:    v_cvt_i32_f32_e32 v4, v2
 ; TONGA-NEXT:    v_mad_f32 v1, -v2, v3, v1
-; TONGA-NEXT:    v_cvt_i32_f32_e32 v2, v2
 ; TONGA-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v3|
 ; TONGA-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
-; TONGA-NEXT:    v_add_u32_e32 v0, vcc, v2, v0
+; TONGA-NEXT:    v_add_u32_e32 v0, vcc, v4, v0
 ; TONGA-NEXT:    v_bfe_i32 v0, v0, 0, 23
 ; TONGA-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; TONGA-NEXT:    s_endpgm
@@ -1798,17 +1798,17 @@
 ; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
 ; GCN-NEXT:    s_mov_b32 s3, 0xf000
 ; GCN-NEXT:    s_mov_b32 s2, -1
-; GCN-NEXT:    s_mov_b32 s10, s2
-; GCN-NEXT:    s_mov_b32 s11, s3
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-NEXT:    s_mov_b32 s8, s6
-; GCN-NEXT:    s_mov_b32 s9, s7
-; GCN-NEXT:    buffer_load_ushort v0, off, s[8:11], 0
-; GCN-NEXT:    buffer_load_sbyte v1, off, s[8:11], 0 offset:2
-; GCN-NEXT:    buffer_load_ushort v2, off, s[8:11], 0 offset:4
-; GCN-NEXT:    buffer_load_sbyte v3, off, s[8:11], 0 offset:6
 ; GCN-NEXT:    s_mov_b32 s0, s4
 ; GCN-NEXT:    s_mov_b32 s1, s5
+; GCN-NEXT:    s_mov_b32 s4, s6
+; GCN-NEXT:    s_mov_b32 s5, s7
+; GCN-NEXT:    s_mov_b32 s6, s2
+; GCN-NEXT:    s_mov_b32 s7, s3
+; GCN-NEXT:    buffer_load_ushort v0, off, s[4:7], 0
+; GCN-NEXT:    buffer_load_sbyte v1, off, s[4:7], 0 offset:2
+; GCN-NEXT:    buffer_load_ushort v2, off, s[4:7], 0 offset:4
+; GCN-NEXT:    buffer_load_sbyte v3, off, s[4:7], 0 offset:6
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
 ; GCN-NEXT:    v_lshlrev_b32_e32 v4, 16, v3
 ; GCN-NEXT:    v_or_b32_e32 v2, v2, v4
@@ -1822,11 +1822,11 @@
 ; GCN-NEXT:    v_or_b32_e32 v1, 1, v1
 ; GCN-NEXT:    v_mul_f32_e32 v3, v0, v4
 ; GCN-NEXT:    v_trunc_f32_e32 v3, v3
+; GCN-NEXT:    v_cvt_i32_f32_e32 v4, v3
 ; GCN-NEXT:    v_mad_f32 v0, -v3, v2, v0
-; GCN-NEXT:    v_cvt_i32_f32_e32 v3, v3
 ; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, |v2|
 ; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
 ; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
 ; GCN-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GCN-NEXT:    s_endpgm
@@ -1836,17 +1836,17 @@
 ; TONGA-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; TONGA-NEXT:    s_mov_b32 s3, 0xf000
 ; TONGA-NEXT:    s_mov_b32 s2, -1
-; TONGA-NEXT:    s_mov_b32 s10, s2
-; TONGA-NEXT:    s_mov_b32 s11, s3
 ; TONGA-NEXT:    s_waitcnt lgkmcnt(0)
-; TONGA-NEXT:    s_mov_b32 s8, s6
-; TONGA-NEXT:    s_mov_b32 s9, s7
-; TONGA-NEXT:    buffer_load_ushort v0, off, s[8:11], 0
-; TONGA-NEXT:    buffer_load_sbyte v1, off, s[8:11], 0 offset:2
-; TONGA-NEXT:    buffer_load_ushort v2, off, s[8:11], 0 offset:4
-; TONGA-NEXT:    buffer_load_sbyte v3, off, s[8:11], 0 offset:6
 ; TONGA-NEXT:    s_mov_b32 s0, s4
 ; TONGA-NEXT:    s_mov_b32 s1, s5
+; TONGA-NEXT:    s_mov_b32 s4, s6
+; TONGA-NEXT:    s_mov_b32 s5, s7
+; TONGA-NEXT:    s_mov_b32 s6, s2
+; TONGA-NEXT:    s_mov_b32 s7, s3
+; TONGA-NEXT:    buffer_load_ushort v0, off, s[4:7], 0
+; TONGA-NEXT:    buffer_load_sbyte v1, off, s[4:7], 0 offset:2
+; TONGA-NEXT:    buffer_load_ushort v2, off, s[4:7], 0 offset:4
+; TONGA-NEXT:    buffer_load_sbyte v3, off, s[4:7], 0 offset:6
 ; TONGA-NEXT:    s_waitcnt vmcnt(0)
 ; TONGA-NEXT:    v_lshlrev_b32_e32 v4, 16, v3
 ; TONGA-NEXT:    v_or_b32_e32 v2, v2, v4
@@ -1860,11 +1860,11 @@
 ; TONGA-NEXT:    v_or_b32_e32 v1, 1, v1
 ; TONGA-NEXT:    v_mul_f32_e32 v3, v0, v4
 ; TONGA-NEXT:    v_trunc_f32_e32 v3, v3
+; TONGA-NEXT:    v_cvt_i32_f32_e32 v4, v3
 ; TONGA-NEXT:    v_mad_f32 v0, -v3, v2, v0
-; TONGA-NEXT:    v_cvt_i32_f32_e32 v3, v3
 ; TONGA-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, |v2|
 ; TONGA-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
-; TONGA-NEXT:    v_add_u32_e32 v0, vcc, v3, v0
+; TONGA-NEXT:    v_add_u32_e32 v0, vcc, v4, v0
 ; TONGA-NEXT:    v_bfe_i32 v0, v0, 0, 24
 ; TONGA-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; TONGA-NEXT:    s_endpgm
@@ -2005,16 +2005,16 @@
 ; GCN-NEXT:    v_mul_hi_u32 v4, v3, v4
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
 ; GCN-NEXT:    v_mul_hi_u32 v3, v5, v3
-; GCN-NEXT:    v_mul_lo_u32 v1, v3, v2
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, 1, v3
-; GCN-NEXT:    v_subrev_i32_e32 v1, vcc, v1, v5
-; GCN-NEXT:    v_cmp_ge_u32_e64 s[0:1], v1, v2
-; GCN-NEXT:    v_cndmask_b32_e64 v3, v3, v4, s[0:1]
-; GCN-NEXT:    v_subrev_i32_e32 v4, vcc, v2, v1
-; GCN-NEXT:    v_cndmask_b32_e64 v1, v1, v4, s[0:1]
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, 1, v3
-; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v2
-; GCN-NEXT:    v_cndmask_b32_e32 v1, v3, v4, vcc
+; GCN-NEXT:    v_mul_lo_u32 v4, v3, v2
+; GCN-NEXT:    v_add_i32_e32 v1, vcc, 1, v3
+; GCN-NEXT:    v_subrev_i32_e32 v4, vcc, v4, v5
+; GCN-NEXT:    v_cmp_ge_u32_e64 s[0:1], v4, v2
+; GCN-NEXT:    v_cndmask_b32_e64 v1, v3, v1, s[0:1]
+; GCN-NEXT:    v_subrev_i32_e32 v3, vcc, v2, v4
+; GCN-NEXT:    v_cndmask_b32_e64 v3, v4, v3, s[0:1]
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, 1, v1
+; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v3, v2
+; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
 ; GCN-NEXT:    v_xor_b32_e32 v1, v1, v0
 ; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v1, v0
 ; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 25
@@ -2053,16 +2053,16 @@
 ; TONGA-NEXT:    v_mul_hi_u32 v4, v3, v4
 ; TONGA-NEXT:    v_add_u32_e32 v3, vcc, v4, v3
 ; TONGA-NEXT:    v_mul_hi_u32 v3, v5, v3
-; TONGA-NEXT:    v_mul_lo_u32 v1, v3, v2
-; TONGA-NEXT:    v_add_u32_e32 v4, vcc, 1, v3
-; TONGA-NEXT:    v_subrev_u32_e32 v1, vcc, v1, v5
-; TONGA-NEXT:    v_cmp_ge_u32_e64 s[0:1], v1, v2
-; TONGA-NEXT:    v_cndmask_b32_e64 v3, v3, v4, s[0:1]
-; TONGA-NEXT:    v_subrev_u32_e32 v4, vcc, v2, v1
-; TONGA-NEXT:    v_cndmask_b32_e64 v1, v1, v4, s[0:1]
-; TONGA-NEXT:    v_add_u32_e32 v4, vcc, 1, v3
-; TONGA-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v2
-; TONGA-NEXT:    v_cndmask_b32_e32 v1, v3, v4, vcc
+; TONGA-NEXT:    v_mul_lo_u32 v4, v3, v2
+; TONGA-NEXT:    v_add_u32_e32 v1, vcc, 1, v3
+; TONGA-NEXT:    v_subrev_u32_e32 v4, vcc, v4, v5
+; TONGA-NEXT:    v_cmp_ge_u32_e64 s[0:1], v4, v2
+; TONGA-NEXT:    v_cndmask_b32_e64 v1, v3, v1, s[0:1]
+; TONGA-NEXT:    v_subrev_u32_e32 v3, vcc, v2, v4
+; TONGA-NEXT:    v_cndmask_b32_e64 v3, v4, v3, s[0:1]
+; TONGA-NEXT:    v_add_u32_e32 v4, vcc, 1, v1
+; TONGA-NEXT:    v_cmp_ge_u32_e32 vcc, v3, v2
+; TONGA-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
 ; TONGA-NEXT:    v_xor_b32_e32 v1, v1, v0
 ; TONGA-NEXT:    v_subrev_u32_e32 v0, vcc, v0, v1
 ; TONGA-NEXT:    v_bfe_i32 v0, v0, 0, 25
diff --git a/llvm/test/CodeGen/AMDGPU/sdiv64.ll b/llvm/test/CodeGen/AMDGPU/sdiv64.ll
--- a/llvm/test/CodeGen/AMDGPU/sdiv64.ll
+++ b/llvm/test/CodeGen/AMDGPU/sdiv64.ll
@@ -6,113 +6,112 @@
 ; GCN-LABEL: s_test_sdiv:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xd
-; GCN-NEXT:    v_mov_b32_e32 v7, 0
-; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
-; GCN-NEXT:    s_mov_b32 s7, 0xf000
-; GCN-NEXT:    s_mov_b32 s6, -1
+; GCN-NEXT:    v_mov_b32_e32 v3, 0
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-NEXT:    s_ashr_i32 s12, s3, 31
-; GCN-NEXT:    s_add_u32 s2, s2, s12
-; GCN-NEXT:    s_mov_b32 s13, s12
-; GCN-NEXT:    s_addc_u32 s3, s3, s12
-; GCN-NEXT:    s_xor_b64 s[2:3], s[2:3], s[12:13]
-; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
-; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s3
-; GCN-NEXT:    s_sub_u32 s4, 0, s2
-; GCN-NEXT:    s_subb_u32 s5, 0, s3
-; GCN-NEXT:    s_ashr_i32 s14, s11, 31
+; GCN-NEXT:    s_ashr_i32 s8, s3, 31
+; GCN-NEXT:    s_add_u32 s2, s2, s8
+; GCN-NEXT:    s_mov_b32 s9, s8
+; GCN-NEXT:    s_addc_u32 s3, s3, s8
+; GCN-NEXT:    s_xor_b64 s[10:11], s[2:3], s[8:9]
+; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s10
+; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s11
+; GCN-NEXT:    s_sub_u32 s12, 0, s10
+; GCN-NEXT:    s_subb_u32 s4, 0, s11
 ; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
 ; GCN-NEXT:    v_rcp_f32_e32 v0, v0
 ; GCN-NEXT:    v_mov_b32_e32 v1, 0
-; GCN-NEXT:    s_mov_b32 s15, s14
 ; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
 ; GCN-NEXT:    v_trunc_f32_e32 v2, v2
 ; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
-; GCN-NEXT:    v_mul_hi_u32 v4, s4, v0
-; GCN-NEXT:    v_mul_lo_u32 v3, s4, v2
-; GCN-NEXT:    v_mul_lo_u32 v6, s5, v0
-; GCN-NEXT:    v_mul_lo_u32 v5, s4, v0
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
-; GCN-NEXT:    v_mul_hi_u32 v4, v0, v5
-; GCN-NEXT:    v_mul_lo_u32 v6, v0, v3
-; GCN-NEXT:    v_mul_hi_u32 v8, v0, v3
-; GCN-NEXT:    v_mul_hi_u32 v9, v2, v3
-; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v7, v8, vcc
-; GCN-NEXT:    v_mul_lo_u32 v8, v2, v5
-; GCN-NEXT:    v_mul_hi_u32 v5, v2, v5
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v8, v4
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v5, vcc
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v3
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v7, v5, vcc
-; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v2, v4, s[0:1]
-; GCN-NEXT:    v_mul_lo_u32 v5, s4, v3
-; GCN-NEXT:    v_mul_hi_u32 v6, s4, v0
-; GCN-NEXT:    v_mul_lo_u32 v8, s5, v0
-; GCN-NEXT:    s_mov_b32 s5, s9
+; GCN-NEXT:    v_mul_hi_u32 v5, s12, v0
+; GCN-NEXT:    v_mul_lo_u32 v4, s12, v2
+; GCN-NEXT:    v_mul_lo_u32 v7, s4, v0
+; GCN-NEXT:    v_mul_lo_u32 v6, s12, v0
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; GCN-NEXT:    v_mul_hi_u32 v5, v0, v6
+; GCN-NEXT:    v_mul_lo_u32 v7, v0, v4
+; GCN-NEXT:    v_mul_hi_u32 v9, v0, v4
+; GCN-NEXT:    v_mul_hi_u32 v8, v2, v6
+; GCN-NEXT:    v_mul_lo_u32 v6, v2, v6
+; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; GCN-NEXT:    v_mul_hi_u32 v10, v2, v4
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v3, v9, vcc
+; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; GCN-NEXT:    v_mul_lo_u32 v6, s4, v0
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; GCN-NEXT:    v_mul_lo_u32 v10, v0, v5
-; GCN-NEXT:    v_mul_hi_u32 v12, v0, v5
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v8, vcc
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v1, vcc
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; GCN-NEXT:    v_add_i32_e64 v0, s[2:3], v0, v4
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v3, v6, vcc
+; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v2, v5, s[2:3]
+; GCN-NEXT:    v_mul_hi_u32 v6, s12, v0
+; GCN-NEXT:    v_mul_lo_u32 v7, s12, v4
+; GCN-NEXT:    v_mul_lo_u32 v8, s4, v0
+; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; GCN-NEXT:    v_mul_lo_u32 v7, s12, v0
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
+; GCN-NEXT:    v_mul_lo_u32 v9, v0, v6
 ; GCN-NEXT:    v_mul_hi_u32 v11, v0, v6
-; GCN-NEXT:    v_mul_hi_u32 v9, v3, v6
-; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
-; GCN-NEXT:    v_mul_hi_u32 v8, v3, v5
-; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v7, v12, vcc
-; GCN-NEXT:    v_mul_lo_u32 v3, v3, v5
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, v10, v6
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v11, v9, vcc
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v8, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v5, vcc
-; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
-; GCN-NEXT:    v_addc_u32_e64 v2, vcc, v2, v5, s[0:1]
-; GCN-NEXT:    s_add_u32 s0, s10, s14
-; GCN-NEXT:    s_addc_u32 s1, s11, s14
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
-; GCN-NEXT:    s_xor_b64 s[10:11], s[0:1], s[14:15]
+; GCN-NEXT:    v_mul_hi_u32 v10, v0, v7
+; GCN-NEXT:    v_mul_hi_u32 v12, v4, v7
+; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
+; GCN-NEXT:    v_mul_hi_u32 v8, v4, v6
+; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
+; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v3, v11, vcc
+; GCN-NEXT:    v_mul_lo_u32 v4, v4, v6
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v9, v7
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v12, vcc
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v8, v1, vcc
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v3, v7, vcc
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; GCN-NEXT:    v_addc_u32_e64 v2, vcc, v2, v6, s[2:3]
+; GCN-NEXT:    s_waitcnt lgkmcnt(0)
+; GCN-NEXT:    s_ashr_i32 s2, s7, 31
+; GCN-NEXT:    s_add_u32 s0, s6, s2
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
+; GCN-NEXT:    s_addc_u32 s1, s7, s2
+; GCN-NEXT:    s_mov_b32 s3, s2
+; GCN-NEXT:    s_xor_b64 s[12:13], s[0:1], s[2:3]
 ; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc
-; GCN-NEXT:    v_mul_lo_u32 v3, s10, v2
-; GCN-NEXT:    v_mul_hi_u32 v4, s10, v0
-; GCN-NEXT:    v_mul_hi_u32 v5, s10, v2
-; GCN-NEXT:    v_mul_hi_u32 v6, s11, v2
-; GCN-NEXT:    v_mul_lo_u32 v2, s11, v2
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v7, v5, vcc
-; GCN-NEXT:    v_mul_lo_u32 v5, s11, v0
-; GCN-NEXT:    v_mul_hi_u32 v0, s11, v0
-; GCN-NEXT:    s_mov_b32 s4, s8
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
-; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v4, v0, vcc
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v6, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT:    v_mul_lo_u32 v4, s12, v2
+; GCN-NEXT:    v_mul_hi_u32 v5, s12, v0
+; GCN-NEXT:    v_mul_hi_u32 v6, s12, v2
+; GCN-NEXT:    v_mul_hi_u32 v7, s13, v2
+; GCN-NEXT:    v_mul_lo_u32 v2, s13, v2
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v3, v6, vcc
+; GCN-NEXT:    v_mul_lo_u32 v6, s13, v0
+; GCN-NEXT:    v_mul_hi_u32 v0, s13, v0
+; GCN-NEXT:    s_mov_b32 s7, 0xf000
+; GCN-NEXT:    s_mov_b32 s6, -1
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
+; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v5, v0, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v7, v1, vcc
-; GCN-NEXT:    v_mul_lo_u32 v2, s2, v1
-; GCN-NEXT:    v_mul_hi_u32 v3, s2, v0
-; GCN-NEXT:    v_mul_lo_u32 v4, s3, v0
-; GCN-NEXT:    v_mov_b32_e32 v5, s3
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v3, v1, vcc
+; GCN-NEXT:    v_mul_lo_u32 v2, s10, v1
+; GCN-NEXT:    v_mul_hi_u32 v3, s10, v0
+; GCN-NEXT:    v_mul_lo_u32 v4, s11, v0
+; GCN-NEXT:    v_mov_b32_e32 v5, s11
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT:    v_mul_lo_u32 v3, s2, v0
+; GCN-NEXT:    v_mul_lo_u32 v3, s10, v0
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
-; GCN-NEXT:    v_sub_i32_e32 v4, vcc, s11, v2
-; GCN-NEXT:    v_sub_i32_e32 v3, vcc, s10, v3
+; GCN-NEXT:    v_sub_i32_e32 v4, vcc, s13, v2
+; GCN-NEXT:    v_sub_i32_e32 v3, vcc, s12, v3
 ; GCN-NEXT:    v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
-; GCN-NEXT:    v_subrev_i32_e64 v5, s[0:1], s2, v3
+; GCN-NEXT:    v_subrev_i32_e64 v5, s[0:1], s10, v3
 ; GCN-NEXT:    v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
-; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s3, v4
+; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s11, v4
 ; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
-; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s2, v5
+; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s10, v5
 ; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
-; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], s3, v4
+; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], s11, v4
 ; GCN-NEXT:    v_cndmask_b32_e64 v4, v6, v5, s[0:1]
 ; GCN-NEXT:    v_add_i32_e64 v5, s[0:1], 2, v0
 ; GCN-NEXT:    v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1]
@@ -120,18 +119,18 @@
 ; GCN-NEXT:    v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1]
 ; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v4
 ; GCN-NEXT:    v_cndmask_b32_e64 v4, v8, v6, s[0:1]
-; GCN-NEXT:    v_mov_b32_e32 v6, s11
+; GCN-NEXT:    v_mov_b32_e32 v6, s13
 ; GCN-NEXT:    v_subb_u32_e32 v2, vcc, v6, v2, vcc
-; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s3, v2
+; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s11, v2
 ; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
-; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s2, v3
+; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s10, v3
 ; GCN-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
-; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s3, v2
+; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s11, v2
 ; GCN-NEXT:    v_cndmask_b32_e32 v2, v6, v3, vcc
 ; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
 ; GCN-NEXT:    v_cndmask_b32_e64 v2, v7, v5, s[0:1]
 ; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
-; GCN-NEXT:    s_xor_b64 s[0:1], s[14:15], s[12:13]
+; GCN-NEXT:    s_xor_b64 s[0:1], s[2:3], s[8:9]
 ; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
 ; GCN-NEXT:    v_xor_b32_e32 v0, s0, v0
 ; GCN-NEXT:    v_xor_b32_e32 v1, s1, v1
@@ -282,20 +281,20 @@
 ; GCN-NEXT:    v_mul_hi_u32 v9, v7, v5
 ; GCN-NEXT:    v_mul_lo_u32 v10, v7, v6
 ; GCN-NEXT:    v_mul_lo_u32 v11, v8, v5
+; GCN-NEXT:    v_mul_lo_u32 v12, v7, v5
 ; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; GCN-NEXT:    v_mul_lo_u32 v10, v7, v5
 ; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
-; GCN-NEXT:    v_mul_lo_u32 v12, v5, v9
-; GCN-NEXT:    v_mul_hi_u32 v11, v5, v9
-; GCN-NEXT:    v_mul_hi_u32 v13, v5, v10
+; GCN-NEXT:    v_mul_lo_u32 v10, v5, v9
+; GCN-NEXT:    v_mul_hi_u32 v11, v5, v12
+; GCN-NEXT:    v_mul_hi_u32 v13, v5, v9
 ; GCN-NEXT:    v_mul_hi_u32 v16, v6, v9
 ; GCN-NEXT:    v_mul_lo_u32 v9, v6, v9
-; GCN-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
-; GCN-NEXT:    v_mul_lo_u32 v13, v6, v10
-; GCN-NEXT:    v_mul_hi_u32 v10, v6, v10
-; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v15, v11, vcc
-; GCN-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
-; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v11, v10, vcc
+; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v15, v13, vcc
+; GCN-NEXT:    v_mul_lo_u32 v13, v6, v12
+; GCN-NEXT:    v_mul_hi_u32 v12, v6, v12
+; GCN-NEXT:    v_add_i32_e32 v10, vcc, v10, v13
+; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v11, v12, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v16, v14, vcc
 ; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
 ; GCN-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v9
@@ -307,17 +306,17 @@
 ; GCN-NEXT:    v_mul_lo_u32 v7, v7, v5
 ; GCN-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v11, v8
-; GCN-NEXT:    v_mul_lo_u32 v13, v5, v8
-; GCN-NEXT:    v_mul_hi_u32 v16, v5, v7
-; GCN-NEXT:    v_mul_hi_u32 v17, v5, v8
-; GCN-NEXT:    v_mul_hi_u32 v12, v9, v7
+; GCN-NEXT:    v_mul_lo_u32 v12, v5, v8
+; GCN-NEXT:    v_mul_hi_u32 v13, v5, v7
+; GCN-NEXT:    v_mul_hi_u32 v16, v5, v8
+; GCN-NEXT:    v_mul_hi_u32 v17, v9, v7
 ; GCN-NEXT:    v_mul_lo_u32 v7, v9, v7
-; GCN-NEXT:    v_add_i32_e32 v13, vcc, v16, v13
+; GCN-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
 ; GCN-NEXT:    v_mul_hi_u32 v11, v9, v8
-; GCN-NEXT:    v_addc_u32_e32 v16, vcc, v15, v17, vcc
+; GCN-NEXT:    v_addc_u32_e32 v13, vcc, v15, v16, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v8, v9, v8
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, v13, v7
-; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v16, v12, vcc
+; GCN-NEXT:    v_add_i32_e32 v7, vcc, v12, v7
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v13, v17, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v11, v14, vcc
 ; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
 ; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v15, v9, vcc
@@ -347,12 +346,12 @@
 ; GCN-NEXT:    v_mul_lo_u32 v8, v2, v6
 ; GCN-NEXT:    v_mul_hi_u32 v9, v2, v5
 ; GCN-NEXT:    v_mul_lo_u32 v10, v3, v5
+; GCN-NEXT:    v_mul_lo_u32 v11, v2, v5
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
-; GCN-NEXT:    v_mul_lo_u32 v9, v2, v5
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
-; GCN-NEXT:    v_sub_i32_e32 v10, vcc, v1, v8
-; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v9
-; GCN-NEXT:    v_subb_u32_e64 v9, s[4:5], v10, v3, vcc
+; GCN-NEXT:    v_sub_i32_e32 v9, vcc, v1, v8
+; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v11
+; GCN-NEXT:    v_subb_u32_e64 v9, s[4:5], v9, v3, vcc
 ; GCN-NEXT:    v_sub_i32_e64 v10, s[4:5], v0, v2
 ; GCN-NEXT:    v_subbrev_u32_e64 v9, s[4:5], 0, v9, s[4:5]
 ; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v9, v3
@@ -994,11 +993,11 @@
 ; GCN-NEXT:    s_mov_b32 s6, -1
 ; GCN-NEXT:    v_mul_f32_e32 v2, v3, v4
 ; GCN-NEXT:    v_trunc_f32_e32 v2, v2
-; GCN-NEXT:    v_mad_f32 v3, -v2, v1, v3
-; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
-; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
+; GCN-NEXT:    v_cvt_i32_f32_e32 v4, v2
+; GCN-NEXT:    v_mad_f32 v2, -v2, v1, v3
+; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v1|
 ; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
 ; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
 ; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
 ; GCN-NEXT:    buffer_store_dword v0, off, s[4:7], 0
@@ -1134,7 +1133,7 @@
 ; GCN-LABEL: s_test_sdiv_k_num_i64:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GCN-NEXT:    v_mov_b32_e32 v2, 0
+; GCN-NEXT:    v_mov_b32_e32 v3, 0
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
 ; GCN-NEXT:    s_ashr_i32 s2, s7, 31
 ; GCN-NEXT:    s_add_u32 s0, s6, s2
@@ -1144,73 +1143,73 @@
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s8
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s9
 ; GCN-NEXT:    s_sub_u32 s3, 0, s8
-; GCN-NEXT:    s_subb_u32 s10, 0, s9
+; GCN-NEXT:    s_subb_u32 s6, 0, s9
 ; GCN-NEXT:    s_mov_b32 s7, 0xf000
 ; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
 ; GCN-NEXT:    v_rcp_f32_e32 v0, v0
 ; GCN-NEXT:    v_mov_b32_e32 v1, 0
-; GCN-NEXT:    s_mov_b32 s6, -1
 ; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v0
-; GCN-NEXT:    v_trunc_f32_e32 v3, v3
-; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v3
+; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
+; GCN-NEXT:    v_trunc_f32_e32 v2, v2
+; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
+; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
 ; GCN-NEXT:    v_mul_hi_u32 v5, s3, v0
-; GCN-NEXT:    v_mul_lo_u32 v4, s3, v3
-; GCN-NEXT:    v_mul_lo_u32 v7, s10, v0
+; GCN-NEXT:    v_mul_lo_u32 v4, s3, v2
+; GCN-NEXT:    v_mul_lo_u32 v7, s6, v0
 ; GCN-NEXT:    v_mul_lo_u32 v6, s3, v0
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
 ; GCN-NEXT:    v_mul_hi_u32 v5, v0, v6
 ; GCN-NEXT:    v_mul_lo_u32 v7, v0, v4
 ; GCN-NEXT:    v_mul_hi_u32 v9, v0, v4
-; GCN-NEXT:    v_mul_lo_u32 v8, v3, v6
-; GCN-NEXT:    v_mul_hi_u32 v6, v3, v6
+; GCN-NEXT:    v_mul_hi_u32 v8, v2, v6
+; GCN-NEXT:    v_mul_lo_u32 v6, v2, v6
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v2, v9, vcc
-; GCN-NEXT:    v_mul_hi_u32 v9, v3, v4
-; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v6, vcc
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v9, v1, vcc
+; GCN-NEXT:    v_mul_hi_u32 v10, v2, v4
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v3, v9, vcc
+; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
+; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v8, vcc
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v1, vcc
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v4
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v2, v6, vcc
-; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v3, v5, s[0:1]
-; GCN-NEXT:    v_mul_lo_u32 v6, s3, v4
-; GCN-NEXT:    v_mul_hi_u32 v7, s3, v0
-; GCN-NEXT:    v_mul_lo_u32 v8, s10, v0
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v3, v6, vcc
+; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v2, v5, s[0:1]
+; GCN-NEXT:    v_mul_hi_u32 v6, s3, v0
+; GCN-NEXT:    v_mul_lo_u32 v7, s3, v4
+; GCN-NEXT:    v_mul_lo_u32 v8, s6, v0
+; GCN-NEXT:    s_mov_b32 s6, -1
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
 ; GCN-NEXT:    v_mul_lo_u32 v7, s3, v0
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
-; GCN-NEXT:    v_mul_lo_u32 v10, v0, v6
-; GCN-NEXT:    v_mul_hi_u32 v12, v0, v6
-; GCN-NEXT:    v_mul_hi_u32 v11, v0, v7
-; GCN-NEXT:    v_mul_hi_u32 v9, v4, v7
+; GCN-NEXT:    v_mul_lo_u32 v9, v0, v6
+; GCN-NEXT:    v_mul_hi_u32 v11, v0, v6
+; GCN-NEXT:    v_mul_hi_u32 v10, v0, v7
+; GCN-NEXT:    v_mul_hi_u32 v12, v4, v7
 ; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
 ; GCN-NEXT:    v_mul_hi_u32 v8, v4, v6
-; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v2, v12, vcc
+; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
+; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v3, v11, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v4, v4, v6
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
-; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v11, v9, vcc
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v8, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v2, v6, vcc
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
-; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v6, s[0:1]
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v9, v7
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v12, vcc
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v8, v1, vcc
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v3, v7, vcc
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; GCN-NEXT:    v_addc_u32_e64 v2, vcc, v2, v6, s[0:1]
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
-; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; GCN-NEXT:    v_mul_lo_u32 v4, v3, 24
+; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc
+; GCN-NEXT:    v_mul_lo_u32 v4, v2, 24
 ; GCN-NEXT:    v_mul_hi_u32 v0, 24, v0
-; GCN-NEXT:    v_mul_hi_u32 v5, 24, v3
-; GCN-NEXT:    v_mul_hi_u32 v3, 0, v3
+; GCN-NEXT:    v_mul_hi_u32 v5, 24, v2
+; GCN-NEXT:    v_mul_hi_u32 v2, 0, v2
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
-; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v5, vcc
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v5, vcc
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, 0, v0
-; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v3, v1, vcc
+; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v2, v1, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v2, s8, v1
 ; GCN-NEXT:    v_mul_hi_u32 v3, s8, v0
 ; GCN-NEXT:    v_mul_lo_u32 v4, s9, v0
@@ -1373,23 +1372,23 @@
 ; GCN-NEXT:    v_mac_f32_e32 v3, 0xcf800000, v4
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
-; GCN-NEXT:    v_mul_hi_u32 v7, v5, v3
-; GCN-NEXT:    v_mul_lo_u32 v8, v5, v4
-; GCN-NEXT:    v_mul_lo_u32 v9, v6, v3
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; GCN-NEXT:    v_mul_lo_u32 v8, v5, v3
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; GCN-NEXT:    v_mul_hi_u32 v8, v5, v3
+; GCN-NEXT:    v_mul_lo_u32 v7, v5, v4
+; GCN-NEXT:    v_mul_lo_u32 v10, v6, v3
+; GCN-NEXT:    v_mul_lo_u32 v9, v5, v3
+; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
+; GCN-NEXT:    v_mul_hi_u32 v8, v3, v9
 ; GCN-NEXT:    v_mul_lo_u32 v10, v3, v7
-; GCN-NEXT:    v_mul_hi_u32 v9, v3, v7
-; GCN-NEXT:    v_mul_hi_u32 v11, v3, v8
+; GCN-NEXT:    v_mul_hi_u32 v11, v3, v7
 ; GCN-NEXT:    v_mul_hi_u32 v14, v4, v7
 ; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
-; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; GCN-NEXT:    v_mul_lo_u32 v11, v4, v8
-; GCN-NEXT:    v_mul_hi_u32 v8, v4, v8
-; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v13, v9, vcc
-; GCN-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
-; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v9, v8, vcc
+; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v13, v11, vcc
+; GCN-NEXT:    v_mul_lo_u32 v11, v4, v9
+; GCN-NEXT:    v_mul_hi_u32 v9, v4, v9
+; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
+; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v10, v9, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v14, v12, vcc
 ; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
 ; GCN-NEXT:    v_add_i32_e64 v3, s[4:5], v3, v7
@@ -1401,17 +1400,17 @@
 ; GCN-NEXT:    v_mul_lo_u32 v5, v5, v3
 ; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v9, v6
-; GCN-NEXT:    v_mul_lo_u32 v11, v3, v6
-; GCN-NEXT:    v_mul_hi_u32 v14, v3, v5
-; GCN-NEXT:    v_mul_hi_u32 v15, v3, v6
-; GCN-NEXT:    v_mul_hi_u32 v10, v7, v5
+; GCN-NEXT:    v_mul_lo_u32 v10, v3, v6
+; GCN-NEXT:    v_mul_hi_u32 v11, v3, v5
+; GCN-NEXT:    v_mul_hi_u32 v14, v3, v6
+; GCN-NEXT:    v_mul_hi_u32 v15, v7, v5
 ; GCN-NEXT:    v_mul_lo_u32 v5, v7, v5
-; GCN-NEXT:    v_add_i32_e32 v11, vcc, v14, v11
+; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
 ; GCN-NEXT:    v_mul_hi_u32 v9, v7, v6
-; GCN-NEXT:    v_addc_u32_e32 v14, vcc, v13, v15, vcc
+; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v13, v14, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v6, v7, v6
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, v11, v5
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v14, v10, vcc
+; GCN-NEXT:    v_add_i32_e32 v5, vcc, v10, v5
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v11, v15, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v9, v12, vcc
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
 ; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v13, v7, vcc
@@ -1431,36 +1430,36 @@
 ; GCN-NEXT:    v_mul_lo_u32 v5, v0, v4
 ; GCN-NEXT:    v_mul_hi_u32 v6, v0, v3
 ; GCN-NEXT:    v_mul_lo_u32 v7, v1, v3
+; GCN-NEXT:    v_mul_lo_u32 v8, v0, v3
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; GCN-NEXT:    v_mul_lo_u32 v6, v0, v3
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; GCN-NEXT:    v_sub_i32_e32 v7, vcc, 0, v5
-; GCN-NEXT:    v_sub_i32_e32 v6, vcc, 24, v6
-; GCN-NEXT:    v_subb_u32_e64 v7, s[4:5], v7, v1, vcc
-; GCN-NEXT:    v_sub_i32_e64 v8, s[4:5], v6, v0
-; GCN-NEXT:    v_subbrev_u32_e64 v7, s[4:5], 0, v7, s[4:5]
-; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v1
+; GCN-NEXT:    v_sub_i32_e32 v6, vcc, 0, v5
+; GCN-NEXT:    v_sub_i32_e32 v7, vcc, 24, v8
+; GCN-NEXT:    v_subb_u32_e64 v6, s[4:5], v6, v1, vcc
+; GCN-NEXT:    v_sub_i32_e64 v8, s[4:5], v7, v0
+; GCN-NEXT:    v_subbrev_u32_e64 v6, s[4:5], 0, v6, s[4:5]
+; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v6, v1
 ; GCN-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
 ; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v8, v0
 ; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
-; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], v7, v1
-; GCN-NEXT:    v_cndmask_b32_e64 v7, v9, v8, s[4:5]
+; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], v6, v1
+; GCN-NEXT:    v_cndmask_b32_e64 v6, v9, v8, s[4:5]
 ; GCN-NEXT:    v_add_i32_e64 v8, s[4:5], 2, v3
 ; GCN-NEXT:    v_addc_u32_e64 v9, s[4:5], 0, v4, s[4:5]
 ; GCN-NEXT:    v_add_i32_e64 v10, s[4:5], 1, v3
 ; GCN-NEXT:    v_subb_u32_e32 v5, vcc, 0, v5, vcc
 ; GCN-NEXT:    v_addc_u32_e64 v11, s[4:5], 0, v4, s[4:5]
-; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v7
+; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v6
 ; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v5, v1
-; GCN-NEXT:    v_cndmask_b32_e64 v7, v11, v9, s[4:5]
+; GCN-NEXT:    v_cndmask_b32_e64 v6, v11, v9, s[4:5]
 ; GCN-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
-; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v6, v0
+; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v7, v0
 ; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
 ; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v5, v1
 ; GCN-NEXT:    v_cndmask_b32_e32 v0, v9, v0, vcc
 ; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
 ; GCN-NEXT:    v_cndmask_b32_e64 v1, v10, v8, s[4:5]
-; GCN-NEXT:    v_cndmask_b32_e32 v0, v4, v7, vcc
+; GCN-NEXT:    v_cndmask_b32_e32 v0, v4, v6, vcc
 ; GCN-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
 ; GCN-NEXT:    v_xor_b32_e32 v3, v0, v2
 ; GCN-NEXT:    v_xor_b32_e32 v0, v1, v2
@@ -1584,23 +1583,23 @@
 ; GCN-NEXT:    v_mac_f32_e32 v3, 0xcf800000, v4
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
-; GCN-NEXT:    v_mul_hi_u32 v7, v5, v3
-; GCN-NEXT:    v_mul_lo_u32 v8, v5, v4
-; GCN-NEXT:    v_mul_lo_u32 v9, v6, v3
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; GCN-NEXT:    v_mul_lo_u32 v8, v5, v3
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; GCN-NEXT:    v_mul_hi_u32 v8, v5, v3
+; GCN-NEXT:    v_mul_lo_u32 v7, v5, v4
+; GCN-NEXT:    v_mul_lo_u32 v10, v6, v3
+; GCN-NEXT:    v_mul_lo_u32 v9, v5, v3
+; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
+; GCN-NEXT:    v_mul_hi_u32 v8, v3, v9
 ; GCN-NEXT:    v_mul_lo_u32 v10, v3, v7
-; GCN-NEXT:    v_mul_hi_u32 v9, v3, v7
-; GCN-NEXT:    v_mul_hi_u32 v11, v3, v8
+; GCN-NEXT:    v_mul_hi_u32 v11, v3, v7
 ; GCN-NEXT:    v_mul_hi_u32 v14, v4, v7
 ; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
-; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; GCN-NEXT:    v_mul_lo_u32 v11, v4, v8
-; GCN-NEXT:    v_mul_hi_u32 v8, v4, v8
-; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v13, v9, vcc
-; GCN-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
-; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v9, v8, vcc
+; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v13, v11, vcc
+; GCN-NEXT:    v_mul_lo_u32 v11, v4, v9
+; GCN-NEXT:    v_mul_hi_u32 v9, v4, v9
+; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
+; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v10, v9, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v14, v12, vcc
 ; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
 ; GCN-NEXT:    v_add_i32_e64 v3, s[4:5], v3, v7
@@ -1612,17 +1611,17 @@
 ; GCN-NEXT:    v_mul_lo_u32 v5, v5, v3
 ; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v9, v6
-; GCN-NEXT:    v_mul_lo_u32 v11, v3, v6
-; GCN-NEXT:    v_mul_hi_u32 v14, v3, v5
-; GCN-NEXT:    v_mul_hi_u32 v15, v3, v6
-; GCN-NEXT:    v_mul_hi_u32 v10, v7, v5
+; GCN-NEXT:    v_mul_lo_u32 v10, v3, v6
+; GCN-NEXT:    v_mul_hi_u32 v11, v3, v5
+; GCN-NEXT:    v_mul_hi_u32 v14, v3, v6
+; GCN-NEXT:    v_mul_hi_u32 v15, v7, v5
 ; GCN-NEXT:    v_mul_lo_u32 v5, v7, v5
-; GCN-NEXT:    v_add_i32_e32 v11, vcc, v14, v11
+; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
 ; GCN-NEXT:    v_mul_hi_u32 v9, v7, v6
-; GCN-NEXT:    v_addc_u32_e32 v14, vcc, v13, v15, vcc
+; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v13, v14, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v6, v7, v6
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, v11, v5
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v14, v10, vcc
+; GCN-NEXT:    v_add_i32_e32 v5, vcc, v10, v5
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v11, v15, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v9, v12, vcc
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
 ; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v13, v7, vcc
@@ -1643,36 +1642,36 @@
 ; GCN-NEXT:    v_mul_lo_u32 v5, v0, v4
 ; GCN-NEXT:    v_mul_hi_u32 v6, v0, v3
 ; GCN-NEXT:    v_mul_lo_u32 v7, v1, v3
+; GCN-NEXT:    v_mul_lo_u32 v8, v0, v3
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; GCN-NEXT:    v_mul_lo_u32 v6, v0, v3
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; GCN-NEXT:    v_sub_i32_e32 v7, vcc, 0, v5
-; GCN-NEXT:    v_sub_i32_e32 v6, vcc, s4, v6
-; GCN-NEXT:    v_subb_u32_e64 v7, s[4:5], v7, v1, vcc
-; GCN-NEXT:    v_sub_i32_e64 v8, s[4:5], v6, v0
-; GCN-NEXT:    v_subbrev_u32_e64 v7, s[4:5], 0, v7, s[4:5]
-; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v1
+; GCN-NEXT:    v_sub_i32_e32 v6, vcc, 0, v5
+; GCN-NEXT:    v_sub_i32_e32 v7, vcc, s4, v8
+; GCN-NEXT:    v_subb_u32_e64 v6, s[4:5], v6, v1, vcc
+; GCN-NEXT:    v_sub_i32_e64 v8, s[4:5], v7, v0
+; GCN-NEXT:    v_subbrev_u32_e64 v6, s[4:5], 0, v6, s[4:5]
+; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v6, v1
 ; GCN-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
 ; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v8, v0
 ; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
-; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], v7, v1
-; GCN-NEXT:    v_cndmask_b32_e64 v7, v9, v8, s[4:5]
+; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], v6, v1
+; GCN-NEXT:    v_cndmask_b32_e64 v6, v9, v8, s[4:5]
 ; GCN-NEXT:    v_add_i32_e64 v8, s[4:5], 2, v3
 ; GCN-NEXT:    v_addc_u32_e64 v9, s[4:5], 0, v4, s[4:5]
 ; GCN-NEXT:    v_add_i32_e64 v10, s[4:5], 1, v3
 ; GCN-NEXT:    v_subb_u32_e32 v5, vcc, 0, v5, vcc
 ; GCN-NEXT:    v_addc_u32_e64 v11, s[4:5], 0, v4, s[4:5]
-; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v7
+; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v6
 ; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v5, v1
-; GCN-NEXT:    v_cndmask_b32_e64 v7, v11, v9, s[4:5]
+; GCN-NEXT:    v_cndmask_b32_e64 v6, v11, v9, s[4:5]
 ; GCN-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
-; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v6, v0
+; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v7, v0
 ; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
 ; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v5, v1
 ; GCN-NEXT:    v_cndmask_b32_e32 v0, v9, v0, vcc
 ; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
 ; GCN-NEXT:    v_cndmask_b32_e64 v1, v10, v8, s[4:5]
-; GCN-NEXT:    v_cndmask_b32_e32 v0, v4, v7, vcc
+; GCN-NEXT:    v_cndmask_b32_e32 v0, v4, v6, vcc
 ; GCN-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
 ; GCN-NEXT:    v_xor_b32_e32 v3, v0, v2
 ; GCN-NEXT:    v_xor_b32_e32 v0, v1, v2
@@ -2009,11 +2008,11 @@
 ; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
 ; GCN-NEXT:    v_mul_f32_e32 v2, s4, v2
 ; GCN-NEXT:    v_trunc_f32_e32 v2, v2
-; GCN-NEXT:    v_mad_f32 v3, -v2, v1, s4
-; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
-; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
+; GCN-NEXT:    v_cvt_i32_f32_e32 v3, v2
+; GCN-NEXT:    v_mad_f32 v2, -v2, v1, s4
+; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v1|
 ; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v3, v0
 ; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
 ; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
@@ -2029,11 +2028,11 @@
 ; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
 ; GCN-IR-NEXT:    v_mul_f32_e32 v2, s4, v2
 ; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
-; GCN-IR-NEXT:    v_mad_f32 v3, -v2, v1, s4
-; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
-; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
+; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v3, v2
+; GCN-IR-NEXT:    v_mad_f32 v2, -v2, v1, s4
+; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v1|
 ; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
-; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
+; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v3, v0
 ; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
 ; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
 ; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
@@ -2054,11 +2053,11 @@
 ; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
 ; GCN-NEXT:    v_mul_f32_e32 v2, s4, v2
 ; GCN-NEXT:    v_trunc_f32_e32 v2, v2
-; GCN-NEXT:    v_mad_f32 v3, -v2, v1, s4
-; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
-; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
+; GCN-NEXT:    v_cvt_i32_f32_e32 v3, v2
+; GCN-NEXT:    v_mad_f32 v2, -v2, v1, s4
+; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v1|
 ; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v3, v0
 ; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
 ; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
@@ -2074,11 +2073,11 @@
 ; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
 ; GCN-IR-NEXT:    v_mul_f32_e32 v2, s4, v2
 ; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
-; GCN-IR-NEXT:    v_mad_f32 v3, -v2, v1, s4
-; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
-; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
+; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v3, v2
+; GCN-IR-NEXT:    v_mad_f32 v2, -v2, v1, s4
+; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v1|
 ; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
-; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
+; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v3, v0
 ; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
 ; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
 ; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
@@ -2108,11 +2107,11 @@
 ; GCN-IR-NEXT:    v_or_b32_e32 v0, 1, v0
 ; GCN-IR-NEXT:    v_mul_f32_e32 v2, 0x38000000, v1
 ; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
+; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v3, v2
 ; GCN-IR-NEXT:    v_mad_f32 v1, -v2, s4, v1
-; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
 ; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, s4
 ; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
-; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
+; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v3, v0
 ; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
 ; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
 ; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/shl_add_ptr_csub.ll b/llvm/test/CodeGen/AMDGPU/shl_add_ptr_csub.ll
--- a/llvm/test/CodeGen/AMDGPU/shl_add_ptr_csub.ll
+++ b/llvm/test/CodeGen/AMDGPU/shl_add_ptr_csub.ll
@@ -4,8 +4,8 @@
 ; GCN-DAG: v_lshlrev_b64 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}, 2, v[4:5]
 ; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 43
 ; GCN: v_add_co_u32_e64 v[[EXTRA_LO:[0-9]+]], vcc_lo, 0x80, v4
-; GCN: v_add_co_ci_u32_e32 v[[EXTRA_HI:[0-9]+]], vcc_lo, 0, v5, vcc_lo
-; GCN: global_atomic_csub v{{[0-9]+}}, v{{\[}}[[LO]]:[[HI]]{{\]}}, [[K]], off offset:512 glc
+; GCN-DAG: v_add_co_ci_u32_e32 v[[EXTRA_HI:[0-9]+]], vcc_lo, 0, v5, vcc_lo
+; GCN-DAG: global_atomic_csub v{{[0-9]+}}, v{{\[}}[[LO]]:[[HI]]{{\]}}, [[K]], off offset:512 glc
 ; GCN: global_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[EXTRA_LO]]:[[EXTRA_HI]]{{\]}}
 define i32 @shl_base_atomicrmw_global_atomic_csub_ptr(i32 addrspace(1)* %out, i64 addrspace(1)* %extra.use, [512 x i32] addrspace(1)* %ptr) #0 {
   %arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(1)* %ptr, i64 0, i64 32
diff --git a/llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll b/llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
--- a/llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
+++ b/llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
@@ -752,18 +752,18 @@
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; VI-NEXT:    v_lshlrev_b32_e32 v1, 1, v0
-; VI-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
+; VI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_mov_b32_e32 v2, s3
-; VI-NEXT:    v_add_u32_e32 v1, vcc, s2, v1
-; VI-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc
-; VI-NEXT:    v_add_u32_e32 v3, vcc, s0, v0
-; VI-NEXT:    flat_load_ushort v0, v[1:2]
-; VI-NEXT:    v_mov_b32_e32 v4, s1
-; VI-NEXT:    v_addc_u32_e32 v4, vcc, 0, v4, vcc
+; VI-NEXT:    v_mov_b32_e32 v3, s3
+; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v1
+; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
+; VI-NEXT:    flat_load_ushort v0, v[0:1]
+; VI-NEXT:    v_mov_b32_e32 v3, s1
+; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v2
+; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
 ; VI-NEXT:    s_waitcnt vmcnt(0)
 ; VI-NEXT:    v_subrev_u16_e32 v0, 64, v0
-; VI-NEXT:    flat_store_dword v[3:4], v0
+; VI-NEXT:    flat_store_dword v[2:3], v0
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: v_test_i16_x_sub_64_zext_to_i32:
diff --git a/llvm/test/CodeGen/AMDGPU/srem64.ll b/llvm/test/CodeGen/AMDGPU/srem64.ll
--- a/llvm/test/CodeGen/AMDGPU/srem64.ll
+++ b/llvm/test/CodeGen/AMDGPU/srem64.ll
@@ -6,95 +6,96 @@
 ; GCN-LABEL: s_test_srem:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0xd
-; GCN-NEXT:    v_mov_b32_e32 v2, 0
-; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
-; GCN-NEXT:    s_mov_b32 s7, 0xf000
-; GCN-NEXT:    s_mov_b32 s6, -1
+; GCN-NEXT:    v_mov_b32_e32 v3, 0
+; GCN-NEXT:    s_mov_b32 s11, 0xf000
+; GCN-NEXT:    s_mov_b32 s10, -1
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s12
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s13
-; GCN-NEXT:    s_sub_u32 s2, 0, s12
-; GCN-NEXT:    s_subb_u32 s3, 0, s13
-; GCN-NEXT:    s_mov_b32 s4, s8
+; GCN-NEXT:    s_sub_u32 s8, 0, s12
+; GCN-NEXT:    s_subb_u32 s4, 0, s13
 ; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
 ; GCN-NEXT:    v_rcp_f32_e32 v0, v0
 ; GCN-NEXT:    v_mov_b32_e32 v1, 0
-; GCN-NEXT:    s_mov_b32 s5, s9
 ; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v0
-; GCN-NEXT:    v_trunc_f32_e32 v3, v3
-; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v3
+; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
+; GCN-NEXT:    v_trunc_f32_e32 v2, v2
+; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
-; GCN-NEXT:    v_mul_hi_u32 v5, s2, v0
-; GCN-NEXT:    v_mul_lo_u32 v4, s2, v3
-; GCN-NEXT:    v_mul_lo_u32 v7, s3, v0
-; GCN-NEXT:    v_mul_lo_u32 v6, s2, v0
+; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
+; GCN-NEXT:    v_mul_hi_u32 v5, s8, v0
+; GCN-NEXT:    v_mul_lo_u32 v4, s8, v2
+; GCN-NEXT:    v_mul_lo_u32 v7, s4, v0
+; GCN-NEXT:    v_mul_lo_u32 v6, s8, v0
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
 ; GCN-NEXT:    v_mul_hi_u32 v5, v0, v6
 ; GCN-NEXT:    v_mul_lo_u32 v7, v0, v4
 ; GCN-NEXT:    v_mul_hi_u32 v9, v0, v4
-; GCN-NEXT:    v_mul_lo_u32 v8, v3, v6
-; GCN-NEXT:    v_mul_hi_u32 v6, v3, v6
+; GCN-NEXT:    v_mul_hi_u32 v8, v2, v6
+; GCN-NEXT:    v_mul_lo_u32 v6, v2, v6
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v2, v9, vcc
-; GCN-NEXT:    v_mul_hi_u32 v9, v3, v4
-; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v6, vcc
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v9, v1, vcc
+; GCN-NEXT:    v_mul_hi_u32 v10, v2, v4
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v3, v9, vcc
+; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
+; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v8, vcc
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v1, vcc
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v4
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v2, v6, vcc
-; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v3, v5, s[0:1]
-; GCN-NEXT:    v_mul_lo_u32 v6, s2, v4
-; GCN-NEXT:    v_mul_hi_u32 v7, s2, v0
-; GCN-NEXT:    v_mul_lo_u32 v8, s3, v0
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; GCN-NEXT:    v_mul_lo_u32 v7, s2, v0
+; GCN-NEXT:    v_add_i32_e64 v0, s[2:3], v0, v4
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v3, v6, vcc
+; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v2, v5, s[2:3]
+; GCN-NEXT:    v_mul_hi_u32 v6, s8, v0
+; GCN-NEXT:    v_mul_lo_u32 v7, s8, v4
+; GCN-NEXT:    v_mul_lo_u32 v8, s4, v0
+; GCN-NEXT:    v_mul_lo_u32 v9, s8, v0
+; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
-; GCN-NEXT:    v_mul_lo_u32 v10, v0, v6
-; GCN-NEXT:    v_mul_hi_u32 v12, v0, v6
-; GCN-NEXT:    v_mul_hi_u32 v11, v0, v7
-; GCN-NEXT:    v_mul_hi_u32 v9, v4, v7
-; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
-; GCN-NEXT:    v_mul_hi_u32 v8, v4, v6
-; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v2, v12, vcc
+; GCN-NEXT:    v_mul_lo_u32 v8, v0, v6
+; GCN-NEXT:    v_mul_hi_u32 v10, v0, v9
+; GCN-NEXT:    v_mul_hi_u32 v11, v0, v6
+; GCN-NEXT:    v_mul_hi_u32 v12, v4, v9
+; GCN-NEXT:    v_mul_lo_u32 v9, v4, v9
+; GCN-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
+; GCN-NEXT:    v_mul_hi_u32 v7, v4, v6
+; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v3, v11, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v4, v4, v6
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
-; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v11, v9, vcc
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v8, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v2, v6, vcc
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
-; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v6, s[0:1]
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v9
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v12, vcc
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v7, v1, vcc
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v3, v7, vcc
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; GCN-NEXT:    v_addc_u32_e64 v2, vcc, v2, v6, s[2:3]
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
-; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; GCN-NEXT:    v_mul_lo_u32 v4, s10, v3
-; GCN-NEXT:    v_mul_hi_u32 v5, s10, v0
-; GCN-NEXT:    v_mul_hi_u32 v6, s10, v3
-; GCN-NEXT:    v_mul_hi_u32 v7, s11, v3
-; GCN-NEXT:    v_mul_lo_u32 v3, s11, v3
+; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc
+; GCN-NEXT:    s_waitcnt lgkmcnt(0)
+; GCN-NEXT:    v_mul_lo_u32 v4, s6, v2
+; GCN-NEXT:    v_mul_hi_u32 v5, s6, v0
+; GCN-NEXT:    v_mul_hi_u32 v6, s6, v2
+; GCN-NEXT:    v_mul_hi_u32 v7, s7, v2
+; GCN-NEXT:    v_mul_lo_u32 v2, s7, v2
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v2, v6, vcc
-; GCN-NEXT:    v_mul_lo_u32 v6, s11, v0
-; GCN-NEXT:    v_mul_hi_u32 v0, s11, v0
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v3, v6, vcc
+; GCN-NEXT:    v_mul_lo_u32 v6, s7, v0
+; GCN-NEXT:    v_mul_hi_u32 v0, s7, v0
+; GCN-NEXT:    s_mov_b32 s8, s4
+; GCN-NEXT:    s_mov_b32 s9, s5
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
 ; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v5, v0, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v7, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v2, v1, vcc
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v3, v1, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v1, s12, v1
 ; GCN-NEXT:    v_mul_hi_u32 v2, s12, v0
 ; GCN-NEXT:    v_mul_lo_u32 v3, s13, v0
 ; GCN-NEXT:    v_mul_lo_u32 v0, s12, v0
 ; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
 ; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
-; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s11, v1
+; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s7, v1
 ; GCN-NEXT:    v_mov_b32_e32 v3, s13
-; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s10, v0
+; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
 ; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
 ; GCN-NEXT:    v_subrev_i32_e64 v4, s[0:1], s12, v0
 ; GCN-NEXT:    v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
@@ -109,7 +110,7 @@
 ; GCN-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
 ; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
 ; GCN-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[0:1]
-; GCN-NEXT:    v_mov_b32_e32 v5, s11
+; GCN-NEXT:    v_mov_b32_e32 v5, s7
 ; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v5, v1, vcc
 ; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s13, v1
 ; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
@@ -121,7 +122,7 @@
 ; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
 ; GCN-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[0:1]
 ; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
-; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
 ; GCN-NEXT:    s_endpgm
 ;
 ; GCN-IR-LABEL: s_test_srem:
@@ -260,20 +261,20 @@
 ; GCN-NEXT:    v_mul_hi_u32 v8, v6, v4
 ; GCN-NEXT:    v_mul_lo_u32 v9, v6, v5
 ; GCN-NEXT:    v_mul_lo_u32 v10, v7, v4
+; GCN-NEXT:    v_mul_lo_u32 v11, v6, v4
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
-; GCN-NEXT:    v_mul_lo_u32 v9, v6, v4
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
-; GCN-NEXT:    v_mul_lo_u32 v11, v4, v8
-; GCN-NEXT:    v_mul_hi_u32 v10, v4, v8
-; GCN-NEXT:    v_mul_hi_u32 v12, v4, v9
+; GCN-NEXT:    v_mul_lo_u32 v9, v4, v8
+; GCN-NEXT:    v_mul_hi_u32 v10, v4, v11
+; GCN-NEXT:    v_mul_hi_u32 v12, v4, v8
 ; GCN-NEXT:    v_mul_hi_u32 v15, v5, v8
 ; GCN-NEXT:    v_mul_lo_u32 v8, v5, v8
-; GCN-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
-; GCN-NEXT:    v_mul_lo_u32 v12, v5, v9
-; GCN-NEXT:    v_mul_hi_u32 v9, v5, v9
-; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v14, v10, vcc
-; GCN-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
-; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v10, v9, vcc
+; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
+; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v14, v12, vcc
+; GCN-NEXT:    v_mul_lo_u32 v12, v5, v11
+; GCN-NEXT:    v_mul_hi_u32 v11, v5, v11
+; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
+; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v10, v11, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v15, v13, vcc
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
 ; GCN-NEXT:    v_add_i32_e64 v4, s[4:5], v4, v8
@@ -285,17 +286,17 @@
 ; GCN-NEXT:    v_mul_lo_u32 v6, v6, v4
 ; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
 ; GCN-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
-; GCN-NEXT:    v_mul_lo_u32 v12, v4, v7
-; GCN-NEXT:    v_mul_hi_u32 v15, v4, v6
-; GCN-NEXT:    v_mul_hi_u32 v16, v4, v7
-; GCN-NEXT:    v_mul_hi_u32 v11, v8, v6
+; GCN-NEXT:    v_mul_lo_u32 v11, v4, v7
+; GCN-NEXT:    v_mul_hi_u32 v12, v4, v6
+; GCN-NEXT:    v_mul_hi_u32 v15, v4, v7
+; GCN-NEXT:    v_mul_hi_u32 v16, v8, v6
 ; GCN-NEXT:    v_mul_lo_u32 v6, v8, v6
-; GCN-NEXT:    v_add_i32_e32 v12, vcc, v15, v12
+; GCN-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
 ; GCN-NEXT:    v_mul_hi_u32 v10, v8, v7
-; GCN-NEXT:    v_addc_u32_e32 v15, vcc, v14, v16, vcc
+; GCN-NEXT:    v_addc_u32_e32 v12, vcc, v14, v15, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v7, v8, v7
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, v12, v6
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v15, v11, vcc
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v11, v6
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v12, v16, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v10, v13, vcc
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
 ; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v14, v8, vcc
@@ -632,11 +633,11 @@
 ; GCN-NEXT:    v_or_b32_e32 v5, 1, v5
 ; GCN-NEXT:    v_mul_f32_e32 v4, v1, v4
 ; GCN-NEXT:    v_trunc_f32_e32 v4, v4
+; GCN-NEXT:    v_cvt_i32_f32_e32 v6, v4
 ; GCN-NEXT:    v_mad_f32 v1, -v4, v3, v1
-; GCN-NEXT:    v_cvt_i32_f32_e32 v4, v4
 ; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v3|
 ; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v5, vcc
-; GCN-NEXT:    v_add_i32_e32 v1, vcc, v4, v1
+; GCN-NEXT:    v_add_i32_e32 v1, vcc, v6, v1
 ; GCN-NEXT:    v_mul_lo_u32 v1, v1, v2
 ; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
 ; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
@@ -656,11 +657,11 @@
 ; GCN-IR-NEXT:    v_or_b32_e32 v5, 1, v5
 ; GCN-IR-NEXT:    v_mul_f32_e32 v4, v1, v4
 ; GCN-IR-NEXT:    v_trunc_f32_e32 v4, v4
+; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v6, v4
 ; GCN-IR-NEXT:    v_mad_f32 v1, -v4, v3, v1
-; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v4, v4
 ; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v3|
 ; GCN-IR-NEXT:    v_cndmask_b32_e32 v1, 0, v5, vcc
-; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v4, v1
+; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v6, v1
 ; GCN-IR-NEXT:    v_mul_lo_u32 v1, v1, v2
 ; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
 ; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
@@ -818,19 +819,19 @@
 define amdgpu_kernel void @s_test_srem32_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
 ; GCN-LABEL: s_test_srem32_64:
 ; GCN:       ; %bb.0:
-; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GCN-NEXT:    s_load_dword s0, s[0:1], 0xe
-; GCN-NEXT:    s_mov_b32 s3, 0xf000
-; GCN-NEXT:    s_mov_b32 s2, -1
+; GCN-NEXT:    s_load_dword s4, s[0:1], 0xe
+; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GCN-NEXT:    s_mov_b32 s7, 0xf000
+; GCN-NEXT:    s_mov_b32 s6, -1
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s7
-; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s0
-; GCN-NEXT:    s_xor_b32 s1, s7, s0
-; GCN-NEXT:    s_ashr_i32 s1, s1, 30
-; GCN-NEXT:    s_or_b32 s1, s1, 1
+; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s4
+; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s3
+; GCN-NEXT:    s_xor_b32 s2, s3, s4
+; GCN-NEXT:    s_ashr_i32 s2, s2, 30
 ; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
-; GCN-NEXT:    v_mov_b32_e32 v3, s1
-; GCN-NEXT:    s_mov_b32 s1, s5
+; GCN-NEXT:    s_or_b32 s2, s2, 1
+; GCN-NEXT:    v_mov_b32_e32 v3, s2
+; GCN-NEXT:    s_mov_b32 s5, s1
 ; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
 ; GCN-NEXT:    v_trunc_f32_e32 v2, v2
 ; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
@@ -838,28 +839,28 @@
 ; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
 ; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
-; GCN-NEXT:    v_mul_lo_u32 v0, v0, s0
-; GCN-NEXT:    s_mov_b32 s0, s4
-; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s7, v0
+; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
+; GCN-NEXT:    s_mov_b32 s4, s0
+; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s3, v0
 ; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
-; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; GCN-NEXT:    s_endpgm
 ;
 ; GCN-IR-LABEL: s_test_srem32_64:
 ; GCN-IR:       ; %bb.0:
-; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GCN-IR-NEXT:    s_load_dword s0, s[0:1], 0xe
-; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
-; GCN-IR-NEXT:    s_mov_b32 s2, -1
+; GCN-IR-NEXT:    s_load_dword s4, s[0:1], 0xe
+; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
+; GCN-IR-NEXT:    s_mov_b32 s6, -1
 ; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s7
-; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s0
-; GCN-IR-NEXT:    s_xor_b32 s1, s7, s0
-; GCN-IR-NEXT:    s_ashr_i32 s1, s1, 30
-; GCN-IR-NEXT:    s_or_b32 s1, s1, 1
+; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s4
+; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s3
+; GCN-IR-NEXT:    s_xor_b32 s2, s3, s4
+; GCN-IR-NEXT:    s_ashr_i32 s2, s2, 30
 ; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
-; GCN-IR-NEXT:    v_mov_b32_e32 v3, s1
-; GCN-IR-NEXT:    s_mov_b32 s1, s5
+; GCN-IR-NEXT:    s_or_b32 s2, s2, 1
+; GCN-IR-NEXT:    v_mov_b32_e32 v3, s2
+; GCN-IR-NEXT:    s_mov_b32 s5, s1
 ; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
 ; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
 ; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
@@ -867,11 +868,11 @@
 ; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
 ; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
 ; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
-; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s0
-; GCN-IR-NEXT:    s_mov_b32 s0, s4
-; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s7, v0
+; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
+; GCN-IR-NEXT:    s_mov_b32 s4, s0
+; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s3, v0
 ; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
-; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; GCN-IR-NEXT:    s_endpgm
   %1 = ashr i64 %x, 32
   %2 = ashr i64 %y, 32
@@ -884,129 +885,127 @@
 define amdgpu_kernel void @s_test_srem33_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
 ; GCN-LABEL: s_test_srem33_64:
 ; GCN:       ; %bb.0:
-; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
+; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
 ; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
-; GCN-NEXT:    v_mov_b32_e32 v7, 0
-; GCN-NEXT:    s_mov_b32 s7, 0xf000
-; GCN-NEXT:    s_mov_b32 s6, -1
+; GCN-NEXT:    v_mov_b32_e32 v3, 0
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-NEXT:    s_ashr_i64 s[2:3], s[10:11], 31
-; GCN-NEXT:    s_ashr_i64 s[4:5], s[0:1], 31
+; GCN-NEXT:    s_ashr_i64 s[2:3], s[6:7], 31
+; GCN-NEXT:    s_ashr_i64 s[8:9], s[0:1], 31
 ; GCN-NEXT:    s_ashr_i32 s0, s1, 31
-; GCN-NEXT:    s_add_u32 s4, s4, s0
+; GCN-NEXT:    s_add_u32 s8, s8, s0
 ; GCN-NEXT:    s_mov_b32 s1, s0
-; GCN-NEXT:    s_addc_u32 s5, s5, s0
-; GCN-NEXT:    s_xor_b64 s[12:13], s[4:5], s[0:1]
-; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s12
-; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s13
-; GCN-NEXT:    s_sub_u32 s4, 0, s12
-; GCN-NEXT:    s_subb_u32 s5, 0, s13
-; GCN-NEXT:    s_ashr_i32 s10, s11, 31
+; GCN-NEXT:    s_addc_u32 s9, s9, s0
+; GCN-NEXT:    s_xor_b64 s[8:9], s[8:9], s[0:1]
+; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s8
+; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s9
+; GCN-NEXT:    s_sub_u32 s6, 0, s8
+; GCN-NEXT:    s_subb_u32 s10, 0, s9
 ; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
 ; GCN-NEXT:    v_rcp_f32_e32 v0, v0
 ; GCN-NEXT:    v_mov_b32_e32 v1, 0
-; GCN-NEXT:    s_mov_b32 s11, s10
 ; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
 ; GCN-NEXT:    v_trunc_f32_e32 v2, v2
 ; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
-; GCN-NEXT:    v_mul_hi_u32 v4, s4, v0
-; GCN-NEXT:    v_mul_lo_u32 v3, s4, v2
-; GCN-NEXT:    v_mul_lo_u32 v6, s5, v0
-; GCN-NEXT:    v_mul_lo_u32 v5, s4, v0
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
-; GCN-NEXT:    v_mul_hi_u32 v4, v0, v5
-; GCN-NEXT:    v_mul_lo_u32 v6, v0, v3
-; GCN-NEXT:    v_mul_hi_u32 v8, v0, v3
-; GCN-NEXT:    v_mul_hi_u32 v9, v2, v3
-; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v7, v8, vcc
-; GCN-NEXT:    v_mul_lo_u32 v8, v2, v5
-; GCN-NEXT:    v_mul_hi_u32 v5, v2, v5
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v8, v4
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v5, vcc
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v3
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v7, v5, vcc
-; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v2, v4, s[0:1]
-; GCN-NEXT:    v_mul_lo_u32 v5, s4, v3
-; GCN-NEXT:    v_mul_hi_u32 v6, s4, v0
-; GCN-NEXT:    v_mul_lo_u32 v8, s5, v0
-; GCN-NEXT:    s_mov_b32 s5, s9
+; GCN-NEXT:    v_mul_hi_u32 v5, s6, v0
+; GCN-NEXT:    v_mul_lo_u32 v4, s6, v2
+; GCN-NEXT:    v_mul_lo_u32 v7, s10, v0
+; GCN-NEXT:    v_mul_lo_u32 v6, s6, v0
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; GCN-NEXT:    v_mul_hi_u32 v5, v0, v6
+; GCN-NEXT:    v_mul_lo_u32 v7, v0, v4
+; GCN-NEXT:    v_mul_hi_u32 v9, v0, v4
+; GCN-NEXT:    v_mul_hi_u32 v8, v2, v6
+; GCN-NEXT:    v_mul_lo_u32 v6, v2, v6
+; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; GCN-NEXT:    v_mul_hi_u32 v10, v2, v4
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v3, v9, vcc
+; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; GCN-NEXT:    v_mul_lo_u32 v6, s4, v0
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; GCN-NEXT:    v_mul_lo_u32 v10, v0, v5
-; GCN-NEXT:    v_mul_hi_u32 v12, v0, v5
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v8, vcc
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v1, vcc
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v4
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v3, v6, vcc
+; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v2, v5, s[0:1]
+; GCN-NEXT:    v_mul_lo_u32 v6, s6, v4
+; GCN-NEXT:    v_mul_hi_u32 v7, s6, v0
+; GCN-NEXT:    v_mul_lo_u32 v8, s10, v0
+; GCN-NEXT:    s_ashr_i32 s10, s7, 31
+; GCN-NEXT:    s_mov_b32 s11, s10
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GCN-NEXT:    v_mul_lo_u32 v7, s6, v0
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
+; GCN-NEXT:    v_mul_lo_u32 v9, v0, v6
 ; GCN-NEXT:    v_mul_hi_u32 v11, v0, v6
-; GCN-NEXT:    v_mul_hi_u32 v9, v3, v6
-; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
-; GCN-NEXT:    v_mul_hi_u32 v8, v3, v5
-; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v7, v12, vcc
-; GCN-NEXT:    v_mul_lo_u32 v3, v3, v5
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, v10, v6
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v11, v9, vcc
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v8, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v5, vcc
-; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
-; GCN-NEXT:    v_addc_u32_e64 v2, vcc, v2, v5, s[0:1]
+; GCN-NEXT:    v_mul_hi_u32 v10, v0, v7
+; GCN-NEXT:    v_mul_hi_u32 v12, v4, v7
+; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
+; GCN-NEXT:    v_mul_hi_u32 v8, v4, v6
+; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
+; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v3, v11, vcc
+; GCN-NEXT:    v_mul_lo_u32 v4, v4, v6
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v9, v7
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v12, vcc
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v8, v1, vcc
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v3, v7, vcc
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; GCN-NEXT:    v_addc_u32_e64 v2, vcc, v2, v6, s[0:1]
 ; GCN-NEXT:    s_add_u32 s0, s2, s10
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
 ; GCN-NEXT:    s_addc_u32 s1, s3, s10
-; GCN-NEXT:    s_xor_b64 s[14:15], s[0:1], s[10:11]
+; GCN-NEXT:    s_xor_b64 s[12:13], s[0:1], s[10:11]
 ; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc
-; GCN-NEXT:    v_mul_lo_u32 v3, s14, v2
-; GCN-NEXT:    v_mul_hi_u32 v4, s14, v0
-; GCN-NEXT:    v_mul_hi_u32 v5, s14, v2
-; GCN-NEXT:    v_mul_hi_u32 v6, s15, v2
-; GCN-NEXT:    v_mul_lo_u32 v2, s15, v2
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v7, v5, vcc
-; GCN-NEXT:    v_mul_lo_u32 v5, s15, v0
-; GCN-NEXT:    v_mul_hi_u32 v0, s15, v0
-; GCN-NEXT:    s_mov_b32 s4, s8
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
-; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v4, v0, vcc
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v6, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT:    v_mul_lo_u32 v4, s12, v2
+; GCN-NEXT:    v_mul_hi_u32 v5, s12, v0
+; GCN-NEXT:    v_mul_hi_u32 v6, s12, v2
+; GCN-NEXT:    v_mul_hi_u32 v7, s13, v2
+; GCN-NEXT:    v_mul_lo_u32 v2, s13, v2
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v3, v6, vcc
+; GCN-NEXT:    v_mul_lo_u32 v6, s13, v0
+; GCN-NEXT:    v_mul_hi_u32 v0, s13, v0
+; GCN-NEXT:    s_mov_b32 s7, 0xf000
+; GCN-NEXT:    s_mov_b32 s6, -1
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
+; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v5, v0, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v7, v1, vcc
-; GCN-NEXT:    v_mul_lo_u32 v1, s12, v1
-; GCN-NEXT:    v_mul_hi_u32 v2, s12, v0
-; GCN-NEXT:    v_mul_lo_u32 v3, s13, v0
-; GCN-NEXT:    v_mul_lo_u32 v0, s12, v0
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v3, v1, vcc
+; GCN-NEXT:    v_mul_lo_u32 v1, s8, v1
+; GCN-NEXT:    v_mul_hi_u32 v2, s8, v0
+; GCN-NEXT:    v_mul_lo_u32 v3, s9, v0
+; GCN-NEXT:    v_mul_lo_u32 v0, s8, v0
 ; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
 ; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
-; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s15, v1
-; GCN-NEXT:    v_mov_b32_e32 v3, s13
-; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s14, v0
+; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s13, v1
+; GCN-NEXT:    v_mov_b32_e32 v3, s9
+; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s12, v0
 ; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
-; GCN-NEXT:    v_subrev_i32_e64 v4, s[0:1], s12, v0
+; GCN-NEXT:    v_subrev_i32_e64 v4, s[0:1], s8, v0
 ; GCN-NEXT:    v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
-; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s13, v5
+; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s9, v5
 ; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
 ; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[2:3]
-; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s12, v4
-; GCN-NEXT:    v_subrev_i32_e64 v3, s[0:1], s12, v4
+; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s8, v4
+; GCN-NEXT:    v_subrev_i32_e64 v3, s[0:1], s8, v4
 ; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
-; GCN-NEXT:    v_cmp_eq_u32_e64 s[2:3], s13, v5
+; GCN-NEXT:    v_cmp_eq_u32_e64 s[2:3], s9, v5
 ; GCN-NEXT:    v_cndmask_b32_e64 v6, v6, v7, s[2:3]
 ; GCN-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
 ; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
 ; GCN-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[0:1]
-; GCN-NEXT:    v_mov_b32_e32 v5, s15
+; GCN-NEXT:    v_mov_b32_e32 v5, s13
 ; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v5, v1, vcc
-; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s13, v1
+; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
 ; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
-; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s12, v0
+; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
 ; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
-; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s13, v1
+; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v1
 ; GCN-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
 ; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
 ; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
@@ -1150,39 +1149,39 @@
 define amdgpu_kernel void @s_test_srem24_48(i48 addrspace(1)* %out, i48 %x, i48 %y) {
 ; GCN-LABEL: s_test_srem24_48:
 ; GCN:       ; %bb.0:
-; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
 ; GCN-NEXT:    s_load_dword s2, s[0:1], 0xb
 ; GCN-NEXT:    s_load_dword s3, s[0:1], 0xc
-; GCN-NEXT:    s_load_dword s6, s[0:1], 0xd
-; GCN-NEXT:    s_load_dword s0, s[0:1], 0xe
-; GCN-NEXT:    s_mov_b32 s7, 0xf000
+; GCN-NEXT:    s_load_dword s4, s[0:1], 0xd
+; GCN-NEXT:    s_load_dword s5, s[0:1], 0xe
+; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
 ; GCN-NEXT:    v_mov_b32_e32 v2, s2
-; GCN-NEXT:    s_sext_i32_i16 s1, s3
-; GCN-NEXT:    v_mov_b32_e32 v0, s6
-; GCN-NEXT:    s_sext_i32_i16 s0, s0
-; GCN-NEXT:    v_alignbit_b32 v0, s0, v0, 24
+; GCN-NEXT:    s_sext_i32_i16 s3, s3
+; GCN-NEXT:    v_mov_b32_e32 v0, s4
+; GCN-NEXT:    s_sext_i32_i16 s5, s5
+; GCN-NEXT:    v_alignbit_b32 v0, s5, v0, 24
 ; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
-; GCN-NEXT:    v_alignbit_b32 v2, s1, v2, 24
+; GCN-NEXT:    v_alignbit_b32 v2, s3, v2, 24
 ; GCN-NEXT:    v_cvt_f32_i32_e32 v3, v2
 ; GCN-NEXT:    v_xor_b32_e32 v5, v2, v0
 ; GCN-NEXT:    v_rcp_iflag_f32_e32 v4, v1
 ; GCN-NEXT:    v_ashrrev_i32_e32 v5, 30, v5
 ; GCN-NEXT:    v_or_b32_e32 v5, 1, v5
-; GCN-NEXT:    s_mov_b32 s6, -1
+; GCN-NEXT:    s_mov_b32 s3, 0xf000
 ; GCN-NEXT:    v_mul_f32_e32 v4, v3, v4
 ; GCN-NEXT:    v_trunc_f32_e32 v4, v4
+; GCN-NEXT:    v_cvt_i32_f32_e32 v6, v4
 ; GCN-NEXT:    v_mad_f32 v3, -v4, v1, v3
-; GCN-NEXT:    v_cvt_i32_f32_e32 v4, v4
 ; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
 ; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v5, vcc
-; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v4
+; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v6
 ; GCN-NEXT:    v_mul_lo_u32 v0, v1, v0
+; GCN-NEXT:    s_mov_b32 s2, -1
 ; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v2, v0
 ; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
 ; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
-; GCN-NEXT:    buffer_store_dword v0, off, s[4:7], 0
-; GCN-NEXT:    buffer_store_short v1, off, s[4:7], 0 offset:4
+; GCN-NEXT:    buffer_store_dword v0, off, s[0:3], 0
+; GCN-NEXT:    buffer_store_short v1, off, s[0:3], 0 offset:4
 ; GCN-NEXT:    s_endpgm
 ;
 ; GCN-IR-LABEL: s_test_srem24_48:
@@ -1322,7 +1321,7 @@
 ; GCN-LABEL: s_test_srem_k_num_i64:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GCN-NEXT:    v_mov_b32_e32 v2, 0
+; GCN-NEXT:    v_mov_b32_e32 v3, 0
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
 ; GCN-NEXT:    s_ashr_i32 s0, s7, 31
 ; GCN-NEXT:    s_add_u32 s2, s6, s0
@@ -1339,13 +1338,13 @@
 ; GCN-NEXT:    v_mov_b32_e32 v1, 0
 ; GCN-NEXT:    s_mov_b32 s6, -1
 ; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v0
-; GCN-NEXT:    v_trunc_f32_e32 v3, v3
-; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v3
+; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
+; GCN-NEXT:    v_trunc_f32_e32 v2, v2
+; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
+; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
 ; GCN-NEXT:    v_mul_hi_u32 v5, s2, v0
-; GCN-NEXT:    v_mul_lo_u32 v4, s2, v3
+; GCN-NEXT:    v_mul_lo_u32 v4, s2, v2
 ; GCN-NEXT:    v_mul_lo_u32 v7, s3, v0
 ; GCN-NEXT:    v_mul_lo_u32 v6, s2, v0
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
@@ -1353,52 +1352,52 @@
 ; GCN-NEXT:    v_mul_hi_u32 v5, v0, v6
 ; GCN-NEXT:    v_mul_lo_u32 v7, v0, v4
 ; GCN-NEXT:    v_mul_hi_u32 v9, v0, v4
-; GCN-NEXT:    v_mul_lo_u32 v8, v3, v6
-; GCN-NEXT:    v_mul_hi_u32 v6, v3, v6
+; GCN-NEXT:    v_mul_hi_u32 v8, v2, v6
+; GCN-NEXT:    v_mul_lo_u32 v6, v2, v6
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v2, v9, vcc
-; GCN-NEXT:    v_mul_hi_u32 v9, v3, v4
-; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v6, vcc
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v9, v1, vcc
+; GCN-NEXT:    v_mul_hi_u32 v10, v2, v4
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v3, v9, vcc
+; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
+; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v8, vcc
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v1, vcc
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v4
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v2, v6, vcc
-; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v3, v5, s[0:1]
-; GCN-NEXT:    v_mul_lo_u32 v6, s2, v4
-; GCN-NEXT:    v_mul_hi_u32 v7, s2, v0
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v3, v6, vcc
+; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v2, v5, s[0:1]
+; GCN-NEXT:    v_mul_hi_u32 v6, s2, v0
+; GCN-NEXT:    v_mul_lo_u32 v7, s2, v4
 ; GCN-NEXT:    v_mul_lo_u32 v8, s3, v0
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
 ; GCN-NEXT:    v_mul_lo_u32 v7, s2, v0
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
-; GCN-NEXT:    v_mul_lo_u32 v10, v0, v6
-; GCN-NEXT:    v_mul_hi_u32 v12, v0, v6
-; GCN-NEXT:    v_mul_hi_u32 v11, v0, v7
-; GCN-NEXT:    v_mul_hi_u32 v9, v4, v7
+; GCN-NEXT:    v_mul_lo_u32 v9, v0, v6
+; GCN-NEXT:    v_mul_hi_u32 v11, v0, v6
+; GCN-NEXT:    v_mul_hi_u32 v10, v0, v7
+; GCN-NEXT:    v_mul_hi_u32 v12, v4, v7
 ; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
 ; GCN-NEXT:    v_mul_hi_u32 v8, v4, v6
-; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v2, v12, vcc
+; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
+; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v3, v11, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v4, v4, v6
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
-; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v11, v9, vcc
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v8, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v2, v6, vcc
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
-; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v6, s[0:1]
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v9, v7
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v12, vcc
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v8, v1, vcc
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v3, v7, vcc
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; GCN-NEXT:    v_addc_u32_e64 v2, vcc, v2, v6, s[0:1]
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
-; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; GCN-NEXT:    v_mul_lo_u32 v4, v3, 24
+; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc
+; GCN-NEXT:    v_mul_lo_u32 v4, v2, 24
 ; GCN-NEXT:    v_mul_hi_u32 v0, 24, v0
-; GCN-NEXT:    v_mul_hi_u32 v5, 24, v3
-; GCN-NEXT:    v_mul_hi_u32 v3, 0, v3
+; GCN-NEXT:    v_mul_hi_u32 v5, 24, v2
+; GCN-NEXT:    v_mul_hi_u32 v2, 0, v2
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
-; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v5, vcc
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v5, vcc
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, 0, v0
-; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v3, v1, vcc
+; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v2, v1, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v1, s8, v1
 ; GCN-NEXT:    v_mul_hi_u32 v2, s8, v0
 ; GCN-NEXT:    v_mul_lo_u32 v3, s9, v0
@@ -1558,23 +1557,23 @@
 ; GCN-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
-; GCN-NEXT:    v_mul_hi_u32 v6, v4, v2
-; GCN-NEXT:    v_mul_lo_u32 v7, v4, v3
-; GCN-NEXT:    v_mul_lo_u32 v8, v5, v2
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
-; GCN-NEXT:    v_mul_lo_u32 v7, v4, v2
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; GCN-NEXT:    v_mul_hi_u32 v7, v4, v2
+; GCN-NEXT:    v_mul_lo_u32 v6, v4, v3
+; GCN-NEXT:    v_mul_lo_u32 v9, v5, v2
+; GCN-NEXT:    v_mul_lo_u32 v8, v4, v2
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
+; GCN-NEXT:    v_mul_hi_u32 v7, v2, v8
 ; GCN-NEXT:    v_mul_lo_u32 v9, v2, v6
-; GCN-NEXT:    v_mul_hi_u32 v8, v2, v6
-; GCN-NEXT:    v_mul_hi_u32 v10, v2, v7
+; GCN-NEXT:    v_mul_hi_u32 v10, v2, v6
 ; GCN-NEXT:    v_mul_hi_u32 v13, v3, v6
 ; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
-; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
-; GCN-NEXT:    v_mul_lo_u32 v10, v3, v7
-; GCN-NEXT:    v_mul_hi_u32 v7, v3, v7
-; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v12, v8, vcc
-; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v8, v7, vcc
+; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v12, v10, vcc
+; GCN-NEXT:    v_mul_lo_u32 v10, v3, v8
+; GCN-NEXT:    v_mul_hi_u32 v8, v3, v8
+; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v9, v8, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v13, v11, vcc
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
 ; GCN-NEXT:    v_add_i32_e64 v2, s[4:5], v2, v6
@@ -1586,17 +1585,17 @@
 ; GCN-NEXT:    v_mul_lo_u32 v4, v4, v2
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; GCN-NEXT:    v_mul_lo_u32 v10, v2, v5
-; GCN-NEXT:    v_mul_hi_u32 v13, v2, v4
-; GCN-NEXT:    v_mul_hi_u32 v14, v2, v5
-; GCN-NEXT:    v_mul_hi_u32 v9, v6, v4
+; GCN-NEXT:    v_mul_lo_u32 v9, v2, v5
+; GCN-NEXT:    v_mul_hi_u32 v10, v2, v4
+; GCN-NEXT:    v_mul_hi_u32 v13, v2, v5
+; GCN-NEXT:    v_mul_hi_u32 v14, v6, v4
 ; GCN-NEXT:    v_mul_lo_u32 v4, v6, v4
-; GCN-NEXT:    v_add_i32_e32 v10, vcc, v13, v10
+; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
 ; GCN-NEXT:    v_mul_hi_u32 v8, v6, v5
-; GCN-NEXT:    v_addc_u32_e32 v13, vcc, v12, v14, vcc
+; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v12, v13, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v5, v6, v5
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v10, v4
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v13, v9, vcc
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v9, v4
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v10, v14, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v8, v11, vcc
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v12, v6, vcc
@@ -1735,8 +1734,8 @@
 ; GCN-IR-NEXT:    v_mul_hi_u32 v4, v0, v2
 ; GCN-IR-NEXT:    v_mul_lo_u32 v1, v1, v2
 ; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, v2
-; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
+; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, v4, v3
+; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
 ; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
 ; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
 ; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
@@ -1767,23 +1766,23 @@
 ; GCN-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
-; GCN-NEXT:    v_mul_hi_u32 v6, v4, v2
-; GCN-NEXT:    v_mul_lo_u32 v7, v4, v3
-; GCN-NEXT:    v_mul_lo_u32 v8, v5, v2
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
-; GCN-NEXT:    v_mul_lo_u32 v7, v4, v2
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; GCN-NEXT:    v_mul_hi_u32 v7, v4, v2
+; GCN-NEXT:    v_mul_lo_u32 v6, v4, v3
+; GCN-NEXT:    v_mul_lo_u32 v9, v5, v2
+; GCN-NEXT:    v_mul_lo_u32 v8, v4, v2
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
+; GCN-NEXT:    v_mul_hi_u32 v7, v2, v8
 ; GCN-NEXT:    v_mul_lo_u32 v9, v2, v6
-; GCN-NEXT:    v_mul_hi_u32 v8, v2, v6
-; GCN-NEXT:    v_mul_hi_u32 v10, v2, v7
+; GCN-NEXT:    v_mul_hi_u32 v10, v2, v6
 ; GCN-NEXT:    v_mul_hi_u32 v13, v3, v6
 ; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
-; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
-; GCN-NEXT:    v_mul_lo_u32 v10, v3, v7
-; GCN-NEXT:    v_mul_hi_u32 v7, v3, v7
-; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v12, v8, vcc
-; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v8, v7, vcc
+; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v12, v10, vcc
+; GCN-NEXT:    v_mul_lo_u32 v10, v3, v8
+; GCN-NEXT:    v_mul_hi_u32 v8, v3, v8
+; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v9, v8, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v13, v11, vcc
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
 ; GCN-NEXT:    v_add_i32_e64 v2, s[4:5], v2, v6
@@ -1795,17 +1794,17 @@
 ; GCN-NEXT:    v_mul_lo_u32 v4, v4, v2
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; GCN-NEXT:    v_mul_lo_u32 v10, v2, v5
-; GCN-NEXT:    v_mul_hi_u32 v13, v2, v4
-; GCN-NEXT:    v_mul_hi_u32 v14, v2, v5
-; GCN-NEXT:    v_mul_hi_u32 v9, v6, v4
+; GCN-NEXT:    v_mul_lo_u32 v9, v2, v5
+; GCN-NEXT:    v_mul_hi_u32 v10, v2, v4
+; GCN-NEXT:    v_mul_hi_u32 v13, v2, v5
+; GCN-NEXT:    v_mul_hi_u32 v14, v6, v4
 ; GCN-NEXT:    v_mul_lo_u32 v4, v6, v4
-; GCN-NEXT:    v_add_i32_e32 v10, vcc, v13, v10
+; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
 ; GCN-NEXT:    v_mul_hi_u32 v8, v6, v5
-; GCN-NEXT:    v_addc_u32_e32 v13, vcc, v12, v14, vcc
+; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v12, v13, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v5, v6, v5
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v10, v4
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v13, v9, vcc
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v9, v4
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v10, v14, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v8, v11, vcc
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v12, v6, vcc
@@ -2069,24 +2068,24 @@
 ; GCN-LABEL: s_test_srem24_k_num_i64:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
-; GCN-NEXT:    s_mov_b32 s6, 0x41c00000
+; GCN-NEXT:    s_mov_b32 s5, 0x41c00000
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-NEXT:    s_ashr_i64 s[4:5], s[2:3], 40
-; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s4
-; GCN-NEXT:    s_ashr_i32 s5, s4, 30
-; GCN-NEXT:    s_or_b32 s5, s5, 1
-; GCN-NEXT:    v_mov_b32_e32 v3, s5
+; GCN-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
+; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s2
+; GCN-NEXT:    s_ashr_i32 s4, s2, 30
+; GCN-NEXT:    s_or_b32 s4, s4, 1
+; GCN-NEXT:    v_mov_b32_e32 v3, s4
 ; GCN-NEXT:    v_rcp_iflag_f32_e32 v1, v0
 ; GCN-NEXT:    s_mov_b32 s3, 0xf000
-; GCN-NEXT:    s_mov_b32 s2, -1
-; GCN-NEXT:    v_mul_f32_e32 v1, s6, v1
+; GCN-NEXT:    v_mul_f32_e32 v1, s5, v1
 ; GCN-NEXT:    v_trunc_f32_e32 v1, v1
-; GCN-NEXT:    v_mad_f32 v2, -v1, v0, s6
+; GCN-NEXT:    v_mad_f32 v2, -v1, v0, s5
 ; GCN-NEXT:    v_cvt_i32_f32_e32 v1, v1
 ; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v0|
 ; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
-; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
+; GCN-NEXT:    v_mul_lo_u32 v0, v0, s2
+; GCN-NEXT:    s_mov_b32 s2, -1
 ; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
 ; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
 ; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
@@ -2096,24 +2095,24 @@
 ; GCN-IR-LABEL: s_test_srem24_k_num_i64:
 ; GCN-IR:       ; %bb.0:
 ; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
-; GCN-IR-NEXT:    s_mov_b32 s6, 0x41c00000
+; GCN-IR-NEXT:    s_mov_b32 s5, 0x41c00000
 ; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[2:3], 40
-; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s4
-; GCN-IR-NEXT:    s_ashr_i32 s5, s4, 30
-; GCN-IR-NEXT:    s_or_b32 s5, s5, 1
-; GCN-IR-NEXT:    v_mov_b32_e32 v3, s5
+; GCN-IR-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
+; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s2
+; GCN-IR-NEXT:    s_ashr_i32 s4, s2, 30
+; GCN-IR-NEXT:    s_or_b32 s4, s4, 1
+; GCN-IR-NEXT:    v_mov_b32_e32 v3, s4
 ; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v1, v0
 ; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
-; GCN-IR-NEXT:    s_mov_b32 s2, -1
-; GCN-IR-NEXT:    v_mul_f32_e32 v1, s6, v1
+; GCN-IR-NEXT:    v_mul_f32_e32 v1, s5, v1
 ; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
-; GCN-IR-NEXT:    v_mad_f32 v2, -v1, v0, s6
+; GCN-IR-NEXT:    v_mad_f32 v2, -v1, v0, s5
 ; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v1, v1
 ; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v0|
 ; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
 ; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
-; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
+; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s2
+; GCN-IR-NEXT:    s_mov_b32 s2, -1
 ; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
 ; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
 ; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
@@ -2128,60 +2127,60 @@
 define amdgpu_kernel void @s_test_srem24_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
 ; GCN-LABEL: s_test_srem24_k_den_i64:
 ; GCN:       ; %bb.0:
-; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GCN-NEXT:    s_mov_b32 s1, 0x46b6fe00
-; GCN-NEXT:    s_mov_b32 s3, 0xf000
-; GCN-NEXT:    s_mov_b32 s2, -1
+; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GCN-NEXT:    s_mov_b32 s4, 0x46b6fe00
+; GCN-NEXT:    s_mov_b32 s7, 0xf000
+; GCN-NEXT:    s_mov_b32 s6, -1
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-NEXT:    s_ashr_i64 s[6:7], s[6:7], 40
-; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s6
-; GCN-NEXT:    s_ashr_i32 s0, s6, 30
-; GCN-NEXT:    s_or_b32 s0, s0, 1
-; GCN-NEXT:    v_mov_b32_e32 v1, s0
+; GCN-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
+; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s2
+; GCN-NEXT:    s_ashr_i32 s3, s2, 30
+; GCN-NEXT:    s_or_b32 s3, s3, 1
+; GCN-NEXT:    v_mov_b32_e32 v1, s3
 ; GCN-NEXT:    v_mul_f32_e32 v2, 0x38331158, v0
 ; GCN-NEXT:    v_trunc_f32_e32 v2, v2
-; GCN-NEXT:    v_mad_f32 v0, -v2, s1, v0
-; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
-; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s1
+; GCN-NEXT:    v_cvt_i32_f32_e32 v3, v2
+; GCN-NEXT:    v_mad_f32 v0, -v2, s4, v0
+; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s4
 ; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
-; GCN-NEXT:    s_movk_i32 s0, 0x5b7f
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
-; GCN-NEXT:    v_mul_lo_u32 v0, v0, s0
-; GCN-NEXT:    s_mov_b32 s0, s4
-; GCN-NEXT:    s_mov_b32 s1, s5
-; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
+; GCN-NEXT:    s_movk_i32 s3, 0x5b7f
+; GCN-NEXT:    v_mul_lo_u32 v0, v0, s3
+; GCN-NEXT:    s_mov_b32 s4, s0
+; GCN-NEXT:    s_mov_b32 s5, s1
+; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
 ; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
 ; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
-; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; GCN-NEXT:    s_endpgm
 ;
 ; GCN-IR-LABEL: s_test_srem24_k_den_i64:
 ; GCN-IR:       ; %bb.0:
-; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GCN-IR-NEXT:    s_mov_b32 s1, 0x46b6fe00
-; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
-; GCN-IR-NEXT:    s_mov_b32 s2, -1
+; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GCN-IR-NEXT:    s_mov_b32 s4, 0x46b6fe00
+; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
+; GCN-IR-NEXT:    s_mov_b32 s6, -1
 ; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-IR-NEXT:    s_ashr_i64 s[6:7], s[6:7], 40
-; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s6
-; GCN-IR-NEXT:    s_ashr_i32 s0, s6, 30
-; GCN-IR-NEXT:    s_or_b32 s0, s0, 1
-; GCN-IR-NEXT:    v_mov_b32_e32 v1, s0
+; GCN-IR-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
+; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s2
+; GCN-IR-NEXT:    s_ashr_i32 s3, s2, 30
+; GCN-IR-NEXT:    s_or_b32 s3, s3, 1
+; GCN-IR-NEXT:    v_mov_b32_e32 v1, s3
 ; GCN-IR-NEXT:    v_mul_f32_e32 v2, 0x38331158, v0
 ; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
-; GCN-IR-NEXT:    v_mad_f32 v0, -v2, s1, v0
-; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
-; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s1
+; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v3, v2
+; GCN-IR-NEXT:    v_mad_f32 v0, -v2, s4, v0
+; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s4
 ; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
-; GCN-IR-NEXT:    s_movk_i32 s0, 0x5b7f
-; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
-; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s0
-; GCN-IR-NEXT:    s_mov_b32 s0, s4
-; GCN-IR-NEXT:    s_mov_b32 s1, s5
-; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
+; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
+; GCN-IR-NEXT:    s_movk_i32 s3, 0x5b7f
+; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s3
+; GCN-IR-NEXT:    s_mov_b32 s4, s0
+; GCN-IR-NEXT:    s_mov_b32 s5, s1
+; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
 ; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
 ; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
-; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; GCN-IR-NEXT:    s_endpgm
   %x.shr = ashr i64 %x, 40
   %result = srem i64 %x.shr, 23423
@@ -2201,11 +2200,11 @@
 ; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
 ; GCN-NEXT:    v_mul_f32_e32 v2, s4, v2
 ; GCN-NEXT:    v_trunc_f32_e32 v2, v2
-; GCN-NEXT:    v_mad_f32 v4, -v2, v1, s4
-; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
-; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v1|
+; GCN-NEXT:    v_cvt_i32_f32_e32 v4, v2
+; GCN-NEXT:    v_mad_f32 v2, -v2, v1, s4
+; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v1|
 ; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
-; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
+; GCN-NEXT:    v_add_i32_e32 v1, vcc, v4, v1
 ; GCN-NEXT:    v_mul_lo_u32 v0, v1, v0
 ; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
 ; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
@@ -2223,11 +2222,11 @@
 ; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
 ; GCN-IR-NEXT:    v_mul_f32_e32 v2, s4, v2
 ; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
-; GCN-IR-NEXT:    v_mad_f32 v4, -v2, v1, s4
-; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
-; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v1|
+; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v4, v2
+; GCN-IR-NEXT:    v_mad_f32 v2, -v2, v1, s4
+; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v1|
 ; GCN-IR-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
-; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
+; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v4, v1
 ; GCN-IR-NEXT:    v_mul_lo_u32 v0, v1, v0
 ; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
 ; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
@@ -2250,11 +2249,11 @@
 ; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
 ; GCN-NEXT:    v_mul_f32_e32 v2, s4, v2
 ; GCN-NEXT:    v_trunc_f32_e32 v2, v2
-; GCN-NEXT:    v_mad_f32 v4, -v2, v1, s4
-; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
-; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v1|
+; GCN-NEXT:    v_cvt_i32_f32_e32 v4, v2
+; GCN-NEXT:    v_mad_f32 v2, -v2, v1, s4
+; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v1|
 ; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
-; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
+; GCN-NEXT:    v_add_i32_e32 v1, vcc, v4, v1
 ; GCN-NEXT:    v_mul_lo_u32 v0, v1, v0
 ; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 0x8000, v0
 ; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
@@ -2272,11 +2271,11 @@
 ; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
 ; GCN-IR-NEXT:    v_mul_f32_e32 v2, s4, v2
 ; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
-; GCN-IR-NEXT:    v_mad_f32 v4, -v2, v1, s4
-; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
-; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v1|
+; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v4, v2
+; GCN-IR-NEXT:    v_mad_f32 v2, -v2, v1, s4
+; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v1|
 ; GCN-IR-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
-; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
+; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v4, v1
 ; GCN-IR-NEXT:    v_mul_lo_u32 v0, v1, v0
 ; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 0x8000, v0
 ; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
@@ -2310,11 +2309,11 @@
 ; GCN-IR-NEXT:    v_or_b32_e32 v2, 1, v2
 ; GCN-IR-NEXT:    v_mul_f32_e32 v3, 0x38000000, v1
 ; GCN-IR-NEXT:    v_trunc_f32_e32 v3, v3
+; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v4, v3
 ; GCN-IR-NEXT:    v_mad_f32 v1, -v3, s4, v1
-; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v3, v3
 ; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, s4
 ; GCN-IR-NEXT:    v_cndmask_b32_e32 v1, 0, v2, vcc
-; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
+; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v4, v1
 ; GCN-IR-NEXT:    v_lshlrev_b32_e32 v1, 15, v1
 ; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
 ; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
diff --git a/llvm/test/CodeGen/AMDGPU/udiv64.ll b/llvm/test/CodeGen/AMDGPU/udiv64.ll
--- a/llvm/test/CodeGen/AMDGPU/udiv64.ll
+++ b/llvm/test/CodeGen/AMDGPU/udiv64.ll
@@ -5,104 +5,105 @@
 define amdgpu_kernel void @s_test_udiv_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
 ; GCN-LABEL: s_test_udiv_i64:
 ; GCN:       ; %bb.0:
-; GCN-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xd
-; GCN-NEXT:    v_mov_b32_e32 v2, 0
-; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
-; GCN-NEXT:    s_mov_b32 s7, 0xf000
-; GCN-NEXT:    s_mov_b32 s6, -1
+; GCN-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0xd
+; GCN-NEXT:    v_mov_b32_e32 v3, 0
+; GCN-NEXT:    s_mov_b32 s11, 0xf000
+; GCN-NEXT:    s_mov_b32 s10, -1
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
-; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s3
-; GCN-NEXT:    s_sub_u32 s4, 0, s2
-; GCN-NEXT:    s_subb_u32 s5, 0, s3
+; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s12
+; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s13
+; GCN-NEXT:    s_sub_u32 s8, 0, s12
+; GCN-NEXT:    s_subb_u32 s4, 0, s13
 ; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
 ; GCN-NEXT:    v_rcp_f32_e32 v0, v0
 ; GCN-NEXT:    v_mov_b32_e32 v1, 0
 ; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v0
-; GCN-NEXT:    v_trunc_f32_e32 v3, v3
-; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v3
+; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
+; GCN-NEXT:    v_trunc_f32_e32 v2, v2
+; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
-; GCN-NEXT:    v_mul_hi_u32 v5, s4, v0
-; GCN-NEXT:    v_mul_lo_u32 v4, s4, v3
-; GCN-NEXT:    v_mul_lo_u32 v7, s5, v0
-; GCN-NEXT:    v_mul_lo_u32 v6, s4, v0
+; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
+; GCN-NEXT:    v_mul_hi_u32 v5, s8, v0
+; GCN-NEXT:    v_mul_lo_u32 v4, s8, v2
+; GCN-NEXT:    v_mul_lo_u32 v7, s4, v0
+; GCN-NEXT:    v_mul_lo_u32 v6, s8, v0
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
 ; GCN-NEXT:    v_mul_hi_u32 v5, v0, v6
 ; GCN-NEXT:    v_mul_lo_u32 v7, v0, v4
 ; GCN-NEXT:    v_mul_hi_u32 v9, v0, v4
-; GCN-NEXT:    v_mul_lo_u32 v8, v3, v6
-; GCN-NEXT:    v_mul_hi_u32 v6, v3, v6
+; GCN-NEXT:    v_mul_hi_u32 v8, v2, v6
+; GCN-NEXT:    v_mul_lo_u32 v6, v2, v6
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v2, v9, vcc
-; GCN-NEXT:    v_mul_hi_u32 v9, v3, v4
-; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v6, vcc
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v9, v1, vcc
+; GCN-NEXT:    v_mul_hi_u32 v10, v2, v4
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v3, v9, vcc
+; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
+; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v8, vcc
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v1, vcc
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v4
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v2, v6, vcc
-; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v3, v5, s[0:1]
-; GCN-NEXT:    v_mul_lo_u32 v6, s4, v4
-; GCN-NEXT:    v_mul_hi_u32 v7, s4, v0
-; GCN-NEXT:    v_mul_lo_u32 v8, s5, v0
-; GCN-NEXT:    s_mov_b32 s5, s9
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; GCN-NEXT:    v_mul_lo_u32 v7, s4, v0
+; GCN-NEXT:    v_add_i32_e64 v0, s[2:3], v0, v4
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v3, v6, vcc
+; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v2, v5, s[2:3]
+; GCN-NEXT:    v_mul_hi_u32 v6, s8, v0
+; GCN-NEXT:    v_mul_lo_u32 v7, s8, v4
+; GCN-NEXT:    v_mul_lo_u32 v8, s4, v0
+; GCN-NEXT:    v_mul_lo_u32 v9, s8, v0
+; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
-; GCN-NEXT:    v_mul_lo_u32 v10, v0, v6
-; GCN-NEXT:    v_mul_hi_u32 v12, v0, v6
-; GCN-NEXT:    v_mul_hi_u32 v11, v0, v7
-; GCN-NEXT:    v_mul_hi_u32 v9, v4, v7
-; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
-; GCN-NEXT:    v_mul_hi_u32 v8, v4, v6
-; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v2, v12, vcc
+; GCN-NEXT:    v_mul_lo_u32 v8, v0, v6
+; GCN-NEXT:    v_mul_hi_u32 v10, v0, v9
+; GCN-NEXT:    v_mul_hi_u32 v11, v0, v6
+; GCN-NEXT:    v_mul_hi_u32 v12, v4, v9
+; GCN-NEXT:    v_mul_lo_u32 v9, v4, v9
+; GCN-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
+; GCN-NEXT:    v_mul_hi_u32 v7, v4, v6
+; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v3, v11, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v4, v4, v6
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
-; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v11, v9, vcc
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v8, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v2, v6, vcc
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
-; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v6, s[0:1]
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v9
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v12, vcc
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v7, v1, vcc
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v3, v7, vcc
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; GCN-NEXT:    v_addc_u32_e64 v2, vcc, v2, v6, s[2:3]
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
-; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; GCN-NEXT:    v_mul_lo_u32 v4, s10, v3
-; GCN-NEXT:    v_mul_hi_u32 v5, s10, v0
-; GCN-NEXT:    v_mul_hi_u32 v6, s10, v3
-; GCN-NEXT:    v_mul_hi_u32 v7, s11, v3
-; GCN-NEXT:    v_mul_lo_u32 v3, s11, v3
+; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc
+; GCN-NEXT:    s_waitcnt lgkmcnt(0)
+; GCN-NEXT:    v_mul_lo_u32 v4, s6, v2
+; GCN-NEXT:    v_mul_hi_u32 v5, s6, v0
+; GCN-NEXT:    v_mul_hi_u32 v6, s6, v2
+; GCN-NEXT:    v_mul_hi_u32 v7, s7, v2
+; GCN-NEXT:    v_mul_lo_u32 v2, s7, v2
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v2, v6, vcc
-; GCN-NEXT:    v_mul_lo_u32 v6, s11, v0
-; GCN-NEXT:    v_mul_hi_u32 v0, s11, v0
-; GCN-NEXT:    s_mov_b32 s4, s8
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v3, v6, vcc
+; GCN-NEXT:    v_mul_lo_u32 v6, s7, v0
+; GCN-NEXT:    v_mul_hi_u32 v0, s7, v0
+; GCN-NEXT:    s_mov_b32 s8, s4
+; GCN-NEXT:    s_mov_b32 s9, s5
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
 ; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v5, v0, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v7, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v2, v1, vcc
-; GCN-NEXT:    v_mul_lo_u32 v2, s2, v1
-; GCN-NEXT:    v_mul_hi_u32 v3, s2, v0
-; GCN-NEXT:    v_mul_lo_u32 v4, s3, v0
-; GCN-NEXT:    v_mov_b32_e32 v5, s3
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v3, v1, vcc
+; GCN-NEXT:    v_mul_lo_u32 v2, s12, v1
+; GCN-NEXT:    v_mul_hi_u32 v3, s12, v0
+; GCN-NEXT:    v_mul_lo_u32 v4, s13, v0
+; GCN-NEXT:    v_mov_b32_e32 v5, s13
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT:    v_mul_lo_u32 v3, s2, v0
+; GCN-NEXT:    v_mul_lo_u32 v3, s12, v0
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
-; GCN-NEXT:    v_sub_i32_e32 v4, vcc, s11, v2
-; GCN-NEXT:    v_sub_i32_e32 v3, vcc, s10, v3
+; GCN-NEXT:    v_sub_i32_e32 v4, vcc, s7, v2
+; GCN-NEXT:    v_sub_i32_e32 v3, vcc, s6, v3
 ; GCN-NEXT:    v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
-; GCN-NEXT:    v_subrev_i32_e64 v5, s[0:1], s2, v3
+; GCN-NEXT:    v_subrev_i32_e64 v5, s[0:1], s12, v3
 ; GCN-NEXT:    v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
-; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s3, v4
+; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s13, v4
 ; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
-; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s2, v5
+; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s12, v5
 ; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
-; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], s3, v4
+; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], s13, v4
 ; GCN-NEXT:    v_cndmask_b32_e64 v4, v6, v5, s[0:1]
 ; GCN-NEXT:    v_add_i32_e64 v5, s[0:1], 2, v0
 ; GCN-NEXT:    v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1]
@@ -110,19 +111,19 @@
 ; GCN-NEXT:    v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1]
 ; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v4
 ; GCN-NEXT:    v_cndmask_b32_e64 v4, v8, v6, s[0:1]
-; GCN-NEXT:    v_mov_b32_e32 v6, s11
+; GCN-NEXT:    v_mov_b32_e32 v6, s7
 ; GCN-NEXT:    v_subb_u32_e32 v2, vcc, v6, v2, vcc
-; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s3, v2
+; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s13, v2
 ; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
-; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s2, v3
+; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s12, v3
 ; GCN-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
-; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s3, v2
+; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s13, v2
 ; GCN-NEXT:    v_cndmask_b32_e32 v2, v6, v3, vcc
 ; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
 ; GCN-NEXT:    v_cndmask_b32_e64 v2, v7, v5, s[0:1]
 ; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
 ; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
-; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
 ; GCN-NEXT:    s_endpgm
 ;
 ; GCN-IR-LABEL: s_test_udiv_i64:
@@ -242,23 +243,23 @@
 ; GCN-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v5
-; GCN-NEXT:    v_mul_hi_u32 v8, v6, v4
-; GCN-NEXT:    v_mul_lo_u32 v9, v6, v5
-; GCN-NEXT:    v_mul_lo_u32 v10, v7, v4
-; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
-; GCN-NEXT:    v_mul_lo_u32 v9, v6, v4
-; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; GCN-NEXT:    v_mul_hi_u32 v9, v6, v4
+; GCN-NEXT:    v_mul_lo_u32 v8, v6, v5
+; GCN-NEXT:    v_mul_lo_u32 v11, v7, v4
+; GCN-NEXT:    v_mul_lo_u32 v10, v6, v4
+; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
+; GCN-NEXT:    v_mul_hi_u32 v9, v4, v10
 ; GCN-NEXT:    v_mul_lo_u32 v11, v4, v8
-; GCN-NEXT:    v_mul_hi_u32 v10, v4, v8
-; GCN-NEXT:    v_mul_hi_u32 v12, v4, v9
+; GCN-NEXT:    v_mul_hi_u32 v12, v4, v8
 ; GCN-NEXT:    v_mul_hi_u32 v15, v5, v8
 ; GCN-NEXT:    v_mul_lo_u32 v8, v5, v8
-; GCN-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
-; GCN-NEXT:    v_mul_lo_u32 v12, v5, v9
-; GCN-NEXT:    v_mul_hi_u32 v9, v5, v9
-; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v14, v10, vcc
-; GCN-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
-; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v10, v9, vcc
+; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v14, v12, vcc
+; GCN-NEXT:    v_mul_lo_u32 v12, v5, v10
+; GCN-NEXT:    v_mul_hi_u32 v10, v5, v10
+; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
+; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v11, v10, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v15, v13, vcc
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
 ; GCN-NEXT:    v_add_i32_e64 v4, s[4:5], v4, v8
@@ -270,17 +271,17 @@
 ; GCN-NEXT:    v_mul_lo_u32 v6, v6, v4
 ; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
 ; GCN-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
-; GCN-NEXT:    v_mul_lo_u32 v12, v4, v7
-; GCN-NEXT:    v_mul_hi_u32 v15, v4, v6
-; GCN-NEXT:    v_mul_hi_u32 v16, v4, v7
-; GCN-NEXT:    v_mul_hi_u32 v11, v8, v6
+; GCN-NEXT:    v_mul_lo_u32 v11, v4, v7
+; GCN-NEXT:    v_mul_hi_u32 v12, v4, v6
+; GCN-NEXT:    v_mul_hi_u32 v15, v4, v7
+; GCN-NEXT:    v_mul_hi_u32 v16, v8, v6
 ; GCN-NEXT:    v_mul_lo_u32 v6, v8, v6
-; GCN-NEXT:    v_add_i32_e32 v12, vcc, v15, v12
+; GCN-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
 ; GCN-NEXT:    v_mul_hi_u32 v10, v8, v7
-; GCN-NEXT:    v_addc_u32_e32 v15, vcc, v14, v16, vcc
+; GCN-NEXT:    v_addc_u32_e32 v12, vcc, v14, v15, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v7, v8, v7
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, v12, v6
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v15, v11, vcc
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v11, v6
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v12, v16, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v10, v13, vcc
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
 ; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v14, v8, vcc
@@ -305,12 +306,12 @@
 ; GCN-NEXT:    v_mul_lo_u32 v6, v2, v5
 ; GCN-NEXT:    v_mul_hi_u32 v7, v2, v4
 ; GCN-NEXT:    v_mul_lo_u32 v8, v3, v4
+; GCN-NEXT:    v_mul_lo_u32 v9, v2, v4
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; GCN-NEXT:    v_mul_lo_u32 v7, v2, v4
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
-; GCN-NEXT:    v_sub_i32_e32 v8, vcc, v1, v6
-; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v7
-; GCN-NEXT:    v_subb_u32_e64 v7, s[4:5], v8, v3, vcc
+; GCN-NEXT:    v_sub_i32_e32 v7, vcc, v1, v6
+; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v9
+; GCN-NEXT:    v_subb_u32_e64 v7, s[4:5], v7, v3, vcc
 ; GCN-NEXT:    v_sub_i32_e64 v8, s[4:5], v0, v2
 ; GCN-NEXT:    v_subbrev_u32_e64 v7, s[4:5], 0, v7, s[4:5]
 ; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v3
@@ -435,18 +436,17 @@
 define amdgpu_kernel void @s_test_udiv24_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
 ; GCN-LABEL: s_test_udiv24_64:
 ; GCN:       ; %bb.0:
-; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GCN-NEXT:    s_load_dword s0, s[0:1], 0xe
-; GCN-NEXT:    s_mov_b32 s3, 0xf000
-; GCN-NEXT:    s_mov_b32 s2, -1
+; GCN-NEXT:    s_load_dword s2, s[0:1], 0xe
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-NEXT:    s_mov_b32 s1, s5
-; GCN-NEXT:    s_lshr_b32 s0, s0, 8
-; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s0
-; GCN-NEXT:    s_lshr_b32 s0, s7, 8
-; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s0
-; GCN-NEXT:    s_mov_b32 s0, s4
+; GCN-NEXT:    s_lshr_b32 s2, s2, 8
+; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
+; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
 ; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
+; GCN-NEXT:    s_waitcnt lgkmcnt(0)
+; GCN-NEXT:    s_lshr_b32 s2, s3, 8
+; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s2
+; GCN-NEXT:    s_mov_b32 s3, 0xf000
+; GCN-NEXT:    s_mov_b32 s2, -1
 ; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
 ; GCN-NEXT:    v_trunc_f32_e32 v2, v2
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
@@ -460,18 +460,17 @@
 ;
 ; GCN-IR-LABEL: s_test_udiv24_64:
 ; GCN-IR:       ; %bb.0:
-; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GCN-IR-NEXT:    s_load_dword s0, s[0:1], 0xe
-; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
-; GCN-IR-NEXT:    s_mov_b32 s2, -1
+; GCN-IR-NEXT:    s_load_dword s2, s[0:1], 0xe
 ; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-IR-NEXT:    s_mov_b32 s1, s5
-; GCN-IR-NEXT:    s_lshr_b32 s0, s0, 8
-; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s0
-; GCN-IR-NEXT:    s_lshr_b32 s0, s7, 8
-; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s0
-; GCN-IR-NEXT:    s_mov_b32 s0, s4
+; GCN-IR-NEXT:    s_lshr_b32 s2, s2, 8
+; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s2
+; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
 ; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
+; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
+; GCN-IR-NEXT:    s_lshr_b32 s2, s3, 8
+; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s2
+; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
+; GCN-IR-NEXT:    s_mov_b32 s2, -1
 ; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
 ; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
 ; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
@@ -535,16 +534,14 @@
 ; GCN-LABEL: s_test_udiv32_i64:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_load_dword s2, s[0:1], 0xe
-; GCN-NEXT:    s_mov_b32 s7, 0xf000
-; GCN-NEXT:    s_mov_b32 s6, -1
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
 ; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
-; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
+; GCN-NEXT:    s_mov_b32 s2, -1
+; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s3
-; GCN-NEXT:    s_mov_b32 s4, s0
-; GCN-NEXT:    s_mov_b32 s5, s1
+; GCN-NEXT:    s_mov_b32 s3, 0xf000
 ; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
 ; GCN-NEXT:    v_trunc_f32_e32 v2, v2
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
@@ -552,22 +549,20 @@
 ; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
 ; GCN-NEXT:    v_mov_b32_e32 v1, 0
 ; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
-; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; GCN-NEXT:    s_endpgm
 ;
 ; GCN-IR-LABEL: s_test_udiv32_i64:
 ; GCN-IR:       ; %bb.0:
 ; GCN-IR-NEXT:    s_load_dword s2, s[0:1], 0xe
-; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
-; GCN-IR-NEXT:    s_mov_b32 s6, -1
 ; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
 ; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s2
 ; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
-; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
 ; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
+; GCN-IR-NEXT:    s_mov_b32 s2, -1
+; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
 ; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s3
-; GCN-IR-NEXT:    s_mov_b32 s4, s0
-; GCN-IR-NEXT:    s_mov_b32 s5, s1
+; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
 ; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
 ; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
 ; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
@@ -575,7 +570,7 @@
 ; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
 ; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
 ; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
-; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; GCN-IR-NEXT:    s_endpgm
   %1 = lshr i64 %x, 32
   %2 = lshr i64 %y, 32
@@ -587,18 +582,17 @@
 define amdgpu_kernel void @s_test_udiv31_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
 ; GCN-LABEL: s_test_udiv31_i64:
 ; GCN:       ; %bb.0:
-; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GCN-NEXT:    s_load_dword s0, s[0:1], 0xe
-; GCN-NEXT:    s_mov_b32 s3, 0xf000
-; GCN-NEXT:    s_mov_b32 s2, -1
+; GCN-NEXT:    s_load_dword s2, s[0:1], 0xe
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-NEXT:    s_mov_b32 s1, s5
-; GCN-NEXT:    s_lshr_b32 s0, s0, 1
-; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s0
-; GCN-NEXT:    s_lshr_b32 s0, s7, 1
-; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s0
-; GCN-NEXT:    s_mov_b32 s0, s4
+; GCN-NEXT:    s_lshr_b32 s2, s2, 1
+; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
+; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
 ; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
+; GCN-NEXT:    s_waitcnt lgkmcnt(0)
+; GCN-NEXT:    s_lshr_b32 s2, s3, 1
+; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s2
+; GCN-NEXT:    s_mov_b32 s3, 0xf000
+; GCN-NEXT:    s_mov_b32 s2, -1
 ; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
 ; GCN-NEXT:    v_trunc_f32_e32 v2, v2
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
@@ -612,18 +606,17 @@
 ;
 ; GCN-IR-LABEL: s_test_udiv31_i64:
 ; GCN-IR:       ; %bb.0:
-; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GCN-IR-NEXT:    s_load_dword s0, s[0:1], 0xe
-; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
-; GCN-IR-NEXT:    s_mov_b32 s2, -1
+; GCN-IR-NEXT:    s_load_dword s2, s[0:1], 0xe
 ; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-IR-NEXT:    s_mov_b32 s1, s5
-; GCN-IR-NEXT:    s_lshr_b32 s0, s0, 1
-; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s0
-; GCN-IR-NEXT:    s_lshr_b32 s0, s7, 1
-; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s0
-; GCN-IR-NEXT:    s_mov_b32 s0, s4
+; GCN-IR-NEXT:    s_lshr_b32 s2, s2, 1
+; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s2
+; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
 ; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
+; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
+; GCN-IR-NEXT:    s_lshr_b32 s2, s3, 1
+; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s2
+; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
+; GCN-IR-NEXT:    s_mov_b32 s2, -1
 ; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
 ; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
 ; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
@@ -644,18 +637,17 @@
 define amdgpu_kernel void @s_test_udiv23_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
 ; GCN-LABEL: s_test_udiv23_i64:
 ; GCN:       ; %bb.0:
-; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GCN-NEXT:    s_load_dword s0, s[0:1], 0xe
-; GCN-NEXT:    s_mov_b32 s3, 0xf000
-; GCN-NEXT:    s_mov_b32 s2, -1
+; GCN-NEXT:    s_load_dword s2, s[0:1], 0xe
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-NEXT:    s_mov_b32 s1, s5
-; GCN-NEXT:    s_lshr_b32 s0, s0, 9
-; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s0
-; GCN-NEXT:    s_lshr_b32 s0, s7, 9
-; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s0
-; GCN-NEXT:    s_mov_b32 s0, s4
+; GCN-NEXT:    s_lshr_b32 s2, s2, 9
+; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
+; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
 ; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
+; GCN-NEXT:    s_waitcnt lgkmcnt(0)
+; GCN-NEXT:    s_lshr_b32 s2, s3, 9
+; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s2
+; GCN-NEXT:    s_mov_b32 s3, 0xf000
+; GCN-NEXT:    s_mov_b32 s2, -1
 ; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
 ; GCN-NEXT:    v_trunc_f32_e32 v2, v2
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
@@ -669,18 +661,17 @@
 ;
 ; GCN-IR-LABEL: s_test_udiv23_i64:
 ; GCN-IR:       ; %bb.0:
-; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GCN-IR-NEXT:    s_load_dword s0, s[0:1], 0xe
-; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
-; GCN-IR-NEXT:    s_mov_b32 s2, -1
+; GCN-IR-NEXT:    s_load_dword s2, s[0:1], 0xe
 ; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-IR-NEXT:    s_mov_b32 s1, s5
-; GCN-IR-NEXT:    s_lshr_b32 s0, s0, 9
-; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s0
-; GCN-IR-NEXT:    s_lshr_b32 s0, s7, 9
-; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s0
-; GCN-IR-NEXT:    s_mov_b32 s0, s4
+; GCN-IR-NEXT:    s_lshr_b32 s2, s2, 9
+; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s2
+; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
 ; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
+; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
+; GCN-IR-NEXT:    s_lshr_b32 s2, s3, 9
+; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s2
+; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
+; GCN-IR-NEXT:    s_mov_b32 s2, -1
 ; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
 ; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
 ; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
@@ -726,28 +717,27 @@
 ; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v1
 ; GCN-NEXT:    v_trunc_f32_e32 v2, v2
 ; GCN-NEXT:    v_mac_f32_e32 v1, 0xcf800000, v2
-; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GCN-NEXT:    s_subb_u32 s9, 0, s3
+; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
+; GCN-NEXT:    s_subb_u32 s4, 0, s3
 ; GCN-NEXT:    v_mov_b32_e32 v8, 0
-; GCN-NEXT:    v_mul_lo_u32 v3, s8, v2
-; GCN-NEXT:    v_mul_hi_u32 v4, s8, v1
-; GCN-NEXT:    v_mul_lo_u32 v5, s9, v1
-; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT:    v_mul_lo_u32 v4, s8, v1
+; GCN-NEXT:    v_mul_hi_u32 v3, s8, v1
+; GCN-NEXT:    v_mul_lo_u32 v4, s8, v2
+; GCN-NEXT:    v_mul_lo_u32 v5, s4, v1
+; GCN-NEXT:    v_mul_lo_u32 v6, s8, v1
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v4
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
-; GCN-NEXT:    v_mul_lo_u32 v6, v1, v3
-; GCN-NEXT:    v_mul_hi_u32 v5, v1, v3
-; GCN-NEXT:    v_mul_hi_u32 v7, v1, v4
+; GCN-NEXT:    v_mul_lo_u32 v4, v1, v3
+; GCN-NEXT:    v_mul_hi_u32 v5, v1, v6
+; GCN-NEXT:    v_mul_hi_u32 v7, v1, v3
 ; GCN-NEXT:    v_mul_hi_u32 v10, v2, v3
 ; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; GCN-NEXT:    v_mul_lo_u32 v7, v2, v4
-; GCN-NEXT:    v_mul_hi_u32 v4, v2, v4
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v5, vcc
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v5, v4, vcc
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v7, vcc
+; GCN-NEXT:    v_mul_lo_u32 v7, v2, v6
+; GCN-NEXT:    v_mul_hi_u32 v6, v2, v6
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v5, v6, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v10, v8, vcc
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
 ; GCN-NEXT:    v_add_i32_e64 v1, s[2:3], v1, v3
@@ -755,24 +745,25 @@
 ; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v2, v4, s[2:3]
 ; GCN-NEXT:    v_mul_lo_u32 v5, s8, v3
 ; GCN-NEXT:    v_mul_hi_u32 v6, s8, v1
-; GCN-NEXT:    v_mul_lo_u32 v7, s9, v1
+; GCN-NEXT:    v_mul_lo_u32 v7, s4, v1
+; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
 ; GCN-NEXT:    v_mul_lo_u32 v6, s8, v1
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
-; GCN-NEXT:    v_mul_lo_u32 v11, v1, v5
-; GCN-NEXT:    v_mul_hi_u32 v13, v1, v5
-; GCN-NEXT:    v_mul_hi_u32 v12, v1, v6
-; GCN-NEXT:    v_mul_hi_u32 v10, v3, v6
+; GCN-NEXT:    v_mul_lo_u32 v10, v1, v5
+; GCN-NEXT:    v_mul_hi_u32 v12, v1, v5
+; GCN-NEXT:    v_mul_hi_u32 v11, v1, v6
+; GCN-NEXT:    v_mul_hi_u32 v13, v3, v6
 ; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
 ; GCN-NEXT:    v_mul_hi_u32 v7, v3, v5
-; GCN-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
-; GCN-NEXT:    v_addc_u32_e32 v12, vcc, v9, v13, vcc
+; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v9, v12, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v3, v3, v5
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, v11, v6
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v12, v10, vcc
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v8, vcc
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v5, vcc
+; GCN-NEXT:    v_add_i32_e32 v5, vcc, v10, v6
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v11, v13, vcc
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v7, v8, vcc
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v6, vcc
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
 ; GCN-NEXT:    v_addc_u32_e64 v2, vcc, v2, v5, s[2:3]
 ; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
@@ -941,7 +932,7 @@
 ; GCN-LABEL: s_test_udiv_k_num_i64:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GCN-NEXT:    v_mov_b32_e32 v2, 0
+; GCN-NEXT:    v_mov_b32_e32 v3, 0
 ; GCN-NEXT:    s_mov_b32 s11, 0xf000
 ; GCN-NEXT:    s_mov_b32 s10, -1
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
@@ -955,13 +946,13 @@
 ; GCN-NEXT:    v_mov_b32_e32 v1, 0
 ; GCN-NEXT:    s_mov_b32 s9, s5
 ; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v0
-; GCN-NEXT:    v_trunc_f32_e32 v3, v3
-; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v3
+; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
+; GCN-NEXT:    v_trunc_f32_e32 v2, v2
+; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
+; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
 ; GCN-NEXT:    v_mul_hi_u32 v5, s2, v0
-; GCN-NEXT:    v_mul_lo_u32 v4, s2, v3
+; GCN-NEXT:    v_mul_lo_u32 v4, s2, v2
 ; GCN-NEXT:    v_mul_lo_u32 v7, s3, v0
 ; GCN-NEXT:    v_mul_lo_u32 v6, s2, v0
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
@@ -969,77 +960,77 @@
 ; GCN-NEXT:    v_mul_hi_u32 v5, v0, v6
 ; GCN-NEXT:    v_mul_lo_u32 v7, v0, v4
 ; GCN-NEXT:    v_mul_hi_u32 v9, v0, v4
-; GCN-NEXT:    v_mul_hi_u32 v8, v3, v6
-; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
+; GCN-NEXT:    v_mul_hi_u32 v8, v2, v6
+; GCN-NEXT:    v_mul_lo_u32 v6, v2, v6
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; GCN-NEXT:    v_mul_hi_u32 v10, v3, v4
-; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v2, v9, vcc
-; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
+; GCN-NEXT:    v_mul_hi_u32 v10, v2, v4
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v3, v9, vcc
+; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v8, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v1, vcc
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v4
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v2, v6, vcc
-; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v3, v5, s[0:1]
-; GCN-NEXT:    v_mul_lo_u32 v6, s2, v4
-; GCN-NEXT:    v_mul_hi_u32 v7, s2, v0
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v3, v6, vcc
+; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v2, v5, s[0:1]
+; GCN-NEXT:    v_mul_hi_u32 v6, s2, v0
+; GCN-NEXT:    v_mul_lo_u32 v7, s2, v4
 ; GCN-NEXT:    v_mul_lo_u32 v8, s3, v0
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; GCN-NEXT:    v_mul_lo_u32 v7, s2, v0
+; GCN-NEXT:    v_mul_lo_u32 v9, s2, v0
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
-; GCN-NEXT:    v_mul_lo_u32 v10, v0, v6
-; GCN-NEXT:    v_mul_hi_u32 v12, v0, v6
-; GCN-NEXT:    v_mul_hi_u32 v11, v0, v7
-; GCN-NEXT:    v_mul_hi_u32 v9, v4, v7
-; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
-; GCN-NEXT:    v_mul_hi_u32 v8, v4, v6
-; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v2, v12, vcc
+; GCN-NEXT:    v_mul_lo_u32 v8, v0, v6
+; GCN-NEXT:    v_mul_hi_u32 v10, v0, v9
+; GCN-NEXT:    v_mul_hi_u32 v11, v0, v6
+; GCN-NEXT:    v_mul_hi_u32 v12, v4, v9
+; GCN-NEXT:    v_mul_lo_u32 v9, v4, v9
+; GCN-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
+; GCN-NEXT:    v_mul_hi_u32 v7, v4, v6
+; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v3, v11, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v4, v4, v6
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
-; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v11, v9, vcc
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v8, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v2, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
-; GCN-NEXT:    v_addc_u32_e64 v1, vcc, v3, v1, s[0:1]
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v9
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v12, vcc
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v7, v1, vcc
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v3, v1, vcc
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; GCN-NEXT:    v_addc_u32_e64 v1, vcc, v2, v1, s[0:1]
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
 ; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GCN-NEXT:    v_mul_lo_u32 v3, v1, 24
+; GCN-NEXT:    v_mul_lo_u32 v2, v1, 24
 ; GCN-NEXT:    v_mul_hi_u32 v0, v0, 24
 ; GCN-NEXT:    v_mul_hi_u32 v1, v1, 24
 ; GCN-NEXT:    v_mov_b32_e32 v5, s7
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
-; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v2, v1, vcc
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v3, v1, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v1, s7, v0
-; GCN-NEXT:    v_mul_hi_u32 v3, s6, v0
-; GCN-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
-; GCN-NEXT:    v_mul_lo_u32 v3, s6, v0
-; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v1
-; GCN-NEXT:    v_sub_i32_e32 v3, vcc, 24, v3
-; GCN-NEXT:    v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
-; GCN-NEXT:    v_subrev_i32_e64 v5, s[0:1], s6, v3
-; GCN-NEXT:    v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
-; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s7, v4
+; GCN-NEXT:    v_mul_hi_u32 v2, s6, v0
+; GCN-NEXT:    v_mul_lo_u32 v4, s6, v0
+; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
+; GCN-NEXT:    v_sub_i32_e32 v2, vcc, 0, v1
+; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 24, v4
+; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v5, vcc
+; GCN-NEXT:    v_subrev_i32_e64 v5, s[0:1], s6, v4
+; GCN-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
+; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s7, v2
 ; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
 ; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s6, v5
 ; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
-; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], s7, v4
-; GCN-NEXT:    v_cndmask_b32_e64 v4, v6, v5, s[0:1]
+; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], s7, v2
+; GCN-NEXT:    v_cndmask_b32_e64 v2, v6, v5, s[0:1]
 ; GCN-NEXT:    v_add_i32_e64 v5, s[0:1], 2, v0
-; GCN-NEXT:    v_addc_u32_e64 v6, s[0:1], 0, v2, s[0:1]
-; GCN-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
+; GCN-NEXT:    v_addc_u32_e64 v6, s[0:1], 0, v3, s[0:1]
 ; GCN-NEXT:    v_add_i32_e64 v7, s[0:1], 1, v0
-; GCN-NEXT:    v_addc_u32_e64 v2, s[0:1], 0, v2, s[0:1]
+; GCN-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
+; GCN-NEXT:    v_addc_u32_e64 v3, s[0:1], 0, v3, s[0:1]
+; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v2
 ; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s7, v1
-; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v4
-; GCN-NEXT:    v_cndmask_b32_e64 v4, 0, -1, vcc
-; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s6, v3
+; GCN-NEXT:    v_cndmask_b32_e64 v2, v3, v6, s[0:1]
 ; GCN-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
+; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s6, v4
+; GCN-NEXT:    v_cndmask_b32_e64 v4, 0, -1, vcc
 ; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s7, v1
-; GCN-NEXT:    v_cndmask_b32_e32 v1, v4, v3, vcc
-; GCN-NEXT:    v_cndmask_b32_e64 v2, v2, v6, s[0:1]
+; GCN-NEXT:    v_cndmask_b32_e32 v1, v3, v4, vcc
 ; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1
 ; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v2, vcc
 ; GCN-NEXT:    v_cndmask_b32_e64 v2, v7, v5, s[0:1]
@@ -1149,7 +1140,7 @@
 ; GCN-NEXT:    v_mov_b32_e32 v12, 0
 ; GCN-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
 ; GCN-NEXT:    v_rcp_f32_e32 v2, v2
-; GCN-NEXT:    v_mov_b32_e32 v11, 0
+; GCN-NEXT:    v_mov_b32_e32 v10, 0
 ; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
 ; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
 ; GCN-NEXT:    v_trunc_f32_e32 v3, v3
@@ -1158,22 +1149,22 @@
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
 ; GCN-NEXT:    v_mul_hi_u32 v7, v4, v2
 ; GCN-NEXT:    v_mul_lo_u32 v6, v4, v3
-; GCN-NEXT:    v_mul_lo_u32 v8, v5, v2
-; GCN-NEXT:    v_mul_lo_u32 v9, v4, v2
+; GCN-NEXT:    v_mul_lo_u32 v9, v5, v2
+; GCN-NEXT:    v_mul_lo_u32 v8, v4, v2
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
-; GCN-NEXT:    v_mul_lo_u32 v8, v2, v6
-; GCN-NEXT:    v_mul_hi_u32 v10, v2, v9
-; GCN-NEXT:    v_mul_hi_u32 v7, v2, v6
-; GCN-NEXT:    v_mul_hi_u32 v13, v3, v6
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
+; GCN-NEXT:    v_mul_hi_u32 v7, v2, v8
+; GCN-NEXT:    v_mul_lo_u32 v9, v2, v6
+; GCN-NEXT:    v_mul_hi_u32 v11, v2, v6
+; GCN-NEXT:    v_mul_lo_u32 v13, v3, v8
+; GCN-NEXT:    v_mul_hi_u32 v8, v3, v8
+; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v12, v11, vcc
+; GCN-NEXT:    v_mul_hi_u32 v11, v3, v6
 ; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
-; GCN-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
-; GCN-NEXT:    v_mul_lo_u32 v10, v3, v9
-; GCN-NEXT:    v_mul_hi_u32 v9, v3, v9
-; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v12, v7, vcc
-; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
-; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v7, v9, vcc
-; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v13, v11, vcc
+; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v13
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v9, v8, vcc
+; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v11, v10, vcc
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
 ; GCN-NEXT:    v_add_i32_e64 v2, s[4:5], v2, v6
 ; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v12, v8, vcc
@@ -1184,18 +1175,18 @@
 ; GCN-NEXT:    v_mul_lo_u32 v4, v4, v2
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; GCN-NEXT:    v_mul_lo_u32 v10, v2, v5
-; GCN-NEXT:    v_mul_hi_u32 v13, v2, v4
-; GCN-NEXT:    v_mul_hi_u32 v14, v2, v5
-; GCN-NEXT:    v_mul_hi_u32 v9, v6, v4
+; GCN-NEXT:    v_mul_lo_u32 v9, v2, v5
+; GCN-NEXT:    v_mul_hi_u32 v11, v2, v4
+; GCN-NEXT:    v_mul_hi_u32 v13, v2, v5
+; GCN-NEXT:    v_mul_hi_u32 v14, v6, v4
 ; GCN-NEXT:    v_mul_lo_u32 v4, v6, v4
-; GCN-NEXT:    v_add_i32_e32 v10, vcc, v13, v10
+; GCN-NEXT:    v_add_i32_e32 v9, vcc, v11, v9
 ; GCN-NEXT:    v_mul_hi_u32 v8, v6, v5
-; GCN-NEXT:    v_addc_u32_e32 v13, vcc, v12, v14, vcc
+; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v12, v13, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v5, v6, v5
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v10, v4
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v13, v9, vcc
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v8, v11, vcc
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v9, v4
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v11, v14, vcc
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v8, v10, vcc
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v12, v6, vcc
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
@@ -1205,36 +1196,36 @@
 ; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v2
 ; GCN-NEXT:    v_mul_lo_u32 v3, v1, v2
 ; GCN-NEXT:    v_mul_hi_u32 v4, v0, v2
+; GCN-NEXT:    v_mul_lo_u32 v5, v0, v2
 ; GCN-NEXT:    s_mov_b32 s4, 0x8000
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT:    v_mul_lo_u32 v4, v0, v2
-; GCN-NEXT:    v_sub_i32_e32 v5, vcc, 0, v3
-; GCN-NEXT:    v_sub_i32_e32 v4, vcc, s4, v4
-; GCN-NEXT:    v_subb_u32_e64 v5, s[4:5], v5, v1, vcc
-; GCN-NEXT:    v_sub_i32_e64 v6, s[4:5], v4, v0
-; GCN-NEXT:    v_subbrev_u32_e64 v5, s[4:5], 0, v5, s[4:5]
-; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v5, v1
+; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v3
+; GCN-NEXT:    v_sub_i32_e32 v5, vcc, s4, v5
+; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v1, vcc
+; GCN-NEXT:    v_sub_i32_e64 v6, s[4:5], v5, v0
+; GCN-NEXT:    v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5]
+; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v4, v1
 ; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
 ; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v6, v0
 ; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[4:5]
-; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], v5, v1
-; GCN-NEXT:    v_cndmask_b32_e64 v5, v7, v6, s[4:5]
+; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], v4, v1
+; GCN-NEXT:    v_cndmask_b32_e64 v4, v7, v6, s[4:5]
 ; GCN-NEXT:    v_add_i32_e64 v6, s[4:5], 2, v2
 ; GCN-NEXT:    v_addc_u32_e64 v7, s[4:5], 0, v12, s[4:5]
 ; GCN-NEXT:    v_add_i32_e64 v8, s[4:5], 1, v2
 ; GCN-NEXT:    v_subb_u32_e32 v3, vcc, 0, v3, vcc
 ; GCN-NEXT:    v_addc_u32_e64 v9, s[4:5], 0, v12, s[4:5]
-; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v5
+; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v4
 ; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v3, v1
-; GCN-NEXT:    v_cndmask_b32_e64 v5, v8, v6, s[4:5]
+; GCN-NEXT:    v_cndmask_b32_e64 v4, v8, v6, s[4:5]
 ; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
-; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v4, v0
+; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v5, v0
 ; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
 ; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v1
 ; GCN-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc
 ; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
 ; GCN-NEXT:    v_cndmask_b32_e64 v1, v9, v7, s[4:5]
-; GCN-NEXT:    v_cndmask_b32_e32 v0, v2, v5, vcc
+; GCN-NEXT:    v_cndmask_b32_e32 v0, v2, v4, vcc
 ; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
 ;
@@ -1424,85 +1415,85 @@
 ; GCN-NEXT:    v_mov_b32_e32 v0, 0x4f800000
 ; GCN-NEXT:    v_madak_f32 v0, 0, v0, 0x41c00000
 ; GCN-NEXT:    v_rcp_f32_e32 v0, v0
-; GCN-NEXT:    s_movk_i32 s2, 0xffe8
-; GCN-NEXT:    v_mov_b32_e32 v8, 0
-; GCN-NEXT:    v_mov_b32_e32 v7, 0
+; GCN-NEXT:    s_movk_i32 s4, 0xffe8
+; GCN-NEXT:    v_mov_b32_e32 v6, 0
+; GCN-NEXT:    v_mov_b32_e32 v2, 0
 ; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GCN-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GCN-NEXT:    v_trunc_f32_e32 v1, v1
 ; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
-; GCN-NEXT:    s_mov_b32 s7, 0xf000
-; GCN-NEXT:    v_mul_hi_u32 v2, v0, s2
-; GCN-NEXT:    v_mul_lo_u32 v3, v1, s2
-; GCN-NEXT:    v_mul_lo_u32 v4, v0, s2
-; GCN-NEXT:    s_mov_b32 s6, -1
-; GCN-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
-; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT:    v_mul_lo_u32 v5, v0, v2
-; GCN-NEXT:    v_mul_hi_u32 v6, v0, v4
-; GCN-NEXT:    v_mul_hi_u32 v3, v0, v2
-; GCN-NEXT:    v_mul_hi_u32 v9, v1, v2
-; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; GCN-NEXT:    v_mul_lo_u32 v6, v1, v4
-; GCN-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v8, v3, vcc
-; GCN-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-NEXT:    s_mov_b32 s4, s8
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v4, vcc
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v9, v7, vcc
-; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v2
-; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v8, v4, vcc
-; GCN-NEXT:    v_mul_hi_u32 v4, v0, s2
-; GCN-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
-; GCN-NEXT:    v_mul_lo_u32 v5, v2, s2
-; GCN-NEXT:    v_mul_lo_u32 v6, v0, s2
-; GCN-NEXT:    v_subrev_i32_e32 v4, vcc, v0, v4
-; GCN-NEXT:    s_mov_b32 s5, s9
+; GCN-NEXT:    s_mov_b32 s11, 0xf000
+; GCN-NEXT:    s_mov_b32 s10, -1
+; GCN-NEXT:    v_mul_hi_u32 v3, v0, s4
+; GCN-NEXT:    v_mul_lo_u32 v5, v1, s4
+; GCN-NEXT:    v_mul_lo_u32 v4, v0, s4
+; GCN-NEXT:    v_subrev_i32_e32 v3, vcc, v0, v3
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
+; GCN-NEXT:    v_mul_hi_u32 v7, v0, v4
+; GCN-NEXT:    v_mul_lo_u32 v5, v0, v3
+; GCN-NEXT:    v_mul_hi_u32 v8, v0, v3
+; GCN-NEXT:    v_mul_hi_u32 v9, v1, v4
+; GCN-NEXT:    v_mul_lo_u32 v4, v1, v4
+; GCN-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v6, v8, vcc
+; GCN-NEXT:    v_mul_hi_u32 v8, v1, v3
+; GCN-NEXT:    v_mul_lo_u32 v3, v1, v3
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
-; GCN-NEXT:    v_mul_lo_u32 v5, v0, v4
-; GCN-NEXT:    v_mul_hi_u32 v9, v0, v6
-; GCN-NEXT:    v_mul_hi_u32 v10, v0, v4
-; GCN-NEXT:    v_mul_hi_u32 v11, v2, v4
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, v9, v5
-; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v8, v10, vcc
-; GCN-NEXT:    v_mul_lo_u32 v10, v2, v6
-; GCN-NEXT:    v_mul_hi_u32 v6, v2, v6
-; GCN-NEXT:    v_mul_lo_u32 v2, v2, v4
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v10
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v6, vcc
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v11, v7, vcc
-; GCN-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v4, vcc
-; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
-; GCN-NEXT:    v_addc_u32_e64 v1, vcc, v1, v4, s[0:1]
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v7, v9, vcc
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v8, v2, vcc
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
+; GCN-NEXT:    v_add_i32_e64 v0, s[2:3], v0, v3
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v5, vcc
+; GCN-NEXT:    v_mul_hi_u32 v5, v0, s4
+; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v1, v4, s[2:3]
+; GCN-NEXT:    v_mul_lo_u32 v7, v3, s4
+; GCN-NEXT:    v_mul_lo_u32 v8, v0, s4
+; GCN-NEXT:    v_subrev_i32_e32 v5, vcc, v0, v5
+; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; GCN-NEXT:    v_mul_lo_u32 v7, v0, v5
+; GCN-NEXT:    v_mul_hi_u32 v9, v0, v8
+; GCN-NEXT:    v_mul_hi_u32 v10, v0, v5
+; GCN-NEXT:    v_mul_hi_u32 v11, v3, v5
+; GCN-NEXT:    s_waitcnt lgkmcnt(0)
+; GCN-NEXT:    s_mov_b32 s8, s4
+; GCN-NEXT:    v_add_i32_e32 v7, vcc, v9, v7
+; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v6, v10, vcc
+; GCN-NEXT:    v_mul_lo_u32 v10, v3, v8
+; GCN-NEXT:    v_mul_hi_u32 v8, v3, v8
+; GCN-NEXT:    v_mul_lo_u32 v3, v3, v5
+; GCN-NEXT:    s_mov_b32 s9, s5
+; GCN-NEXT:    v_add_i32_e32 v5, vcc, v7, v10
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v8, vcc
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v11, v2, vcc
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v6, v7, vcc
+; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v4
+; GCN-NEXT:    v_addc_u32_e64 v1, vcc, v1, v5, s[2:3]
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
 ; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GCN-NEXT:    v_mul_lo_u32 v2, s10, v1
-; GCN-NEXT:    v_mul_hi_u32 v3, s10, v0
-; GCN-NEXT:    v_mul_hi_u32 v4, s10, v1
-; GCN-NEXT:    v_mul_hi_u32 v5, s11, v1
-; GCN-NEXT:    v_mul_lo_u32 v1, s11, v1
-; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v8, v4, vcc
-; GCN-NEXT:    v_mul_lo_u32 v4, s11, v0
-; GCN-NEXT:    v_mul_hi_u32 v0, s11, v0
-; GCN-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
-; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
-; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v5, v7, vcc
+; GCN-NEXT:    v_mul_lo_u32 v3, s6, v1
+; GCN-NEXT:    v_mul_hi_u32 v4, s6, v0
+; GCN-NEXT:    v_mul_hi_u32 v5, s6, v1
+; GCN-NEXT:    v_mul_hi_u32 v7, s7, v1
+; GCN-NEXT:    v_mul_lo_u32 v1, s7, v1
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v5, vcc
+; GCN-NEXT:    v_mul_lo_u32 v5, s7, v0
+; GCN-NEXT:    v_mul_hi_u32 v0, s7, v0
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
+; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v4, v0, vcc
+; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v7, v2, vcc
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v8, v2, vcc
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v6, v2, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v2, v1, 24
 ; GCN-NEXT:    v_mul_hi_u32 v3, v0, 24
 ; GCN-NEXT:    v_mul_lo_u32 v4, v0, 24
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT:    v_sub_i32_e32 v4, vcc, s10, v4
-; GCN-NEXT:    v_mov_b32_e32 v3, s11
+; GCN-NEXT:    v_sub_i32_e32 v4, vcc, s6, v4
+; GCN-NEXT:    v_mov_b32_e32 v3, s7
 ; GCN-NEXT:    v_subb_u32_e32 v2, vcc, v3, v2, vcc
 ; GCN-NEXT:    v_subrev_i32_e32 v3, vcc, 24, v4
 ; GCN-NEXT:    v_subbrev_u32_e32 v5, vcc, 0, v2, vcc
@@ -1524,7 +1515,7 @@
 ; GCN-NEXT:    v_cndmask_b32_e32 v2, v7, v5, vcc
 ; GCN-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[0:1]
 ; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
-; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
 ; GCN-NEXT:    s_endpgm
 ;
 ; GCN-IR-LABEL: s_test_udiv_k_den_i64:
@@ -1628,21 +1619,21 @@
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
 ; GCN-NEXT:    v_mul_hi_u32 v4, v2, s6
-; GCN-NEXT:    v_mul_lo_u32 v5, v3, s6
-; GCN-NEXT:    v_mul_lo_u32 v6, v2, s6
+; GCN-NEXT:    v_mul_lo_u32 v6, v3, s6
+; GCN-NEXT:    v_mul_lo_u32 v5, v2, s6
 ; GCN-NEXT:    v_subrev_i32_e32 v4, vcc, v2, v4
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GCN-NEXT:    v_mul_lo_u32 v7, v2, v4
-; GCN-NEXT:    v_mul_hi_u32 v8, v2, v6
-; GCN-NEXT:    v_mul_hi_u32 v5, v2, v4
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
+; GCN-NEXT:    v_mul_hi_u32 v7, v2, v5
+; GCN-NEXT:    v_mul_lo_u32 v6, v2, v4
+; GCN-NEXT:    v_mul_hi_u32 v8, v2, v4
 ; GCN-NEXT:    v_mul_hi_u32 v11, v3, v4
 ; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; GCN-NEXT:    v_mul_lo_u32 v8, v3, v6
-; GCN-NEXT:    v_mul_hi_u32 v6, v3, v6
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v10, v5, vcc
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v6, vcc
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v10, v8, vcc
+; GCN-NEXT:    v_mul_lo_u32 v8, v3, v5
+; GCN-NEXT:    v_mul_hi_u32 v5, v3, v5
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v5, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v11, v9, vcc
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; GCN-NEXT:    v_add_i32_e64 v2, s[4:5], v2, v4
@@ -1662,11 +1653,11 @@
 ; GCN-NEXT:    v_mul_lo_u32 v12, v4, v8
 ; GCN-NEXT:    v_mul_hi_u32 v8, v4, v8
 ; GCN-NEXT:    v_mul_lo_u32 v4, v4, v6
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v12
-; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v11, v8, vcc
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v13, v9, vcc
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v6, vcc
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v12
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v11, v8, vcc
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v13, v9, vcc
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v7, vcc
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
 ; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v6, s[4:5]
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
diff --git a/llvm/test/CodeGen/AMDGPU/udivrem.ll b/llvm/test/CodeGen/AMDGPU/udivrem.ll
--- a/llvm/test/CodeGen/AMDGPU/udivrem.ll
+++ b/llvm/test/CodeGen/AMDGPU/udivrem.ll
@@ -39,7 +39,6 @@
 ; GFX6-NEXT:    s_load_dword s3, s[0:1], 0x26
 ; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
 ; GFX6-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x13
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0x1d
 ; GFX6-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX6-NEXT:    s_mov_b32 s6, -1
 ; GFX6-NEXT:    s_mov_b32 s10, s6
@@ -51,12 +50,14 @@
 ; GFX6-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX6-NEXT:    v_mul_lo_u32 v1, s2, v0
+; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x1d
 ; GFX6-NEXT:    v_mul_hi_u32 v1, v0, v1
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
-; GFX6-NEXT:    v_mul_hi_u32 v0, s0, v0
+; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:    v_mul_hi_u32 v0, s2, v0
 ; GFX6-NEXT:    v_mul_lo_u32 v1, v0, s3
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, 1, v0
-; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s0, v1
+; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s2, v1
 ; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s3, v1
 ; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
 ; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s3, v1
@@ -158,43 +159,43 @@
 ; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xb
 ; GFX6-NEXT:    s_mov_b32 s2, 0x4f7ffffe
 ; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s6
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s7
+; GFX6-NEXT:    s_sub_i32 s3, 0, s7
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v1
 ; GFX6-NEXT:    v_mul_f32_e32 v0, s2, v0
 ; GFX6-NEXT:    v_mul_f32_e32 v1, s2, v1
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX6-NEXT:    s_sub_i32 s2, 0, s6
+; GFX6-NEXT:    v_mul_lo_u32 v3, s3, v1
 ; GFX6-NEXT:    v_mul_lo_u32 v2, s2, v0
-; GFX6-NEXT:    s_sub_i32 s2, 0, s7
-; GFX6-NEXT:    v_mul_lo_u32 v3, s2, v1
+; GFX6-NEXT:    s_mov_b32 s3, 0xf000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
-; GFX6-NEXT:    v_mul_hi_u32 v2, v0, v2
 ; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
+; GFX6-NEXT:    v_mul_hi_u32 v2, v0, v2
+; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
 ; GFX6-NEXT:    v_mul_hi_u32 v0, s4, v0
-; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
 ; GFX6-NEXT:    v_mul_hi_u32 v1, s5, v1
 ; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s6
 ; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s7
 ; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
-; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s6, v0
 ; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s5, v1
+; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s6, v0
+; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s7, v1
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s6, v0
 ; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s7, v1
+; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
 ; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s6, v0
+; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s7, v1
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s6, v0
 ; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s7, v1
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s7, v1
-; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s7, v1
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s7, v1
-; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
 ; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -319,70 +320,70 @@
 ; GFX6-LABEL: test_udivrem_v4:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0xd
-; GFX6-NEXT:    s_mov_b32 s13, 0x4f7ffffe
+; GFX6-NEXT:    s_mov_b32 s14, 0x4f7ffffe
 ; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
 ; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s8
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s9
-; GFX6-NEXT:    s_sub_i32 s2, 0, s8
-; GFX6-NEXT:    s_sub_i32 s12, 0, s9
+; GFX6-NEXT:    s_sub_i32 s12, 0, s8
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v2, s10
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v1
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s10
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v5, s11
-; GFX6-NEXT:    v_mul_f32_e32 v0, s13, v0
+; GFX6-NEXT:    s_sub_i32 s13, 0, s9
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v2
+; GFX6-NEXT:    v_mul_f32_e32 v0, s14, v0
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT:    v_mul_f32_e32 v1, s13, v1
+; GFX6-NEXT:    v_mul_f32_e32 v1, s14, v1
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v3, v3
-; GFX6-NEXT:    v_mul_lo_u32 v2, s2, v0
-; GFX6-NEXT:    s_mov_b32 s2, -1
-; GFX6-NEXT:    v_mul_lo_u32 v4, s12, v1
-; GFX6-NEXT:    v_mul_hi_u32 v2, v0, v2
+; GFX6-NEXT:    v_mul_f32_e32 v2, s14, v2
+; GFX6-NEXT:    v_mul_lo_u32 v3, s12, v0
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v5, s11
+; GFX6-NEXT:    v_mul_lo_u32 v4, s13, v1
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v2
+; GFX6-NEXT:    v_mul_hi_u32 v3, v0, v3
+; GFX6-NEXT:    s_sub_i32 s12, 0, s10
 ; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
+; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v3, v0
 ; GFX6-NEXT:    v_mul_hi_u32 v0, s4, v0
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v3, v5
 ; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v4, v1
-; GFX6-NEXT:    v_mul_hi_u32 v1, s5, v1
-; GFX6-NEXT:    v_mul_f32_e32 v2, s13, v3
+; GFX6-NEXT:    v_mul_lo_u32 v4, s12, v2
 ; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s8
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v2
-; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s9
+; GFX6-NEXT:    v_mul_hi_u32 v1, s5, v1
+; GFX6-NEXT:    v_mul_f32_e32 v3, s14, v3
+; GFX6-NEXT:    v_mul_hi_u32 v4, v2, v4
 ; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
-; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s8, v0
+; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s8, v0
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
-; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
-; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s8, v0
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v3
+; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
+; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s8, v0
+; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s9
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
-; GFX6-NEXT:    s_sub_i32 s4, 0, s10
-; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v3, s4, v2
-; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s5, v1
-; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s9, v1
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
-; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
-; GFX6-NEXT:    v_mul_hi_u32 v3, v2, v3
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v5
 ; GFX6-NEXT:    s_sub_i32 s4, 0, s11
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_mul_f32_e32 v3, s13, v4
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v3
-; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s9, v1
+; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
+; GFX6-NEXT:    v_mul_lo_u32 v4, s4, v3
+; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s5, v1
 ; GFX6-NEXT:    v_mul_hi_u32 v2, s6, v2
+; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s9, v1
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
+; GFX6-NEXT:    v_mul_hi_u32 v4, v3, v4
+; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
+; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s9, v1
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
-; GFX6-NEXT:    v_mul_lo_u32 v5, s4, v3
-; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v2, s10
-; GFX6-NEXT:    v_mul_hi_u32 v4, v3, v5
-; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s6, v2
-; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s10, v2
+; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
 ; GFX6-NEXT:    v_mul_hi_u32 v3, s7, v3
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v2
-; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
+; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s6, v2
 ; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s10, v2
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v2
 ; GFX6-NEXT:    v_mul_lo_u32 v3, v3, s11
+; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
+; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s10, v2
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v2
 ; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
 ; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s7, v3
@@ -398,35 +399,33 @@
 ; GFX8-LABEL: test_udivrem_v4:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x34
-; GFX8-NEXT:    s_mov_b32 s12, 0x4f7ffffe
+; GFX8-NEXT:    s_mov_b32 s3, 0x4f7ffffe
 ; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NEXT:    v_cvt_f32_u32_e32 v0, s8
 ; GFX8-NEXT:    s_sub_i32 s2, 0, s8
 ; GFX8-NEXT:    v_cvt_f32_u32_e32 v1, s9
-; GFX8-NEXT:    v_cvt_f32_u32_e32 v4, s11
+; GFX8-NEXT:    v_cvt_f32_u32_e32 v3, s10
 ; GFX8-NEXT:    v_rcp_iflag_f32_e32 v0, v0
-; GFX8-NEXT:    s_sub_i32 s3, 0, s9
 ; GFX8-NEXT:    v_rcp_iflag_f32_e32 v1, v1
-; GFX8-NEXT:    v_cvt_f32_u32_e32 v2, s10
-; GFX8-NEXT:    v_mul_f32_e32 v0, s12, v0
+; GFX8-NEXT:    v_mul_f32_e32 v0, s3, v0
 ; GFX8-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; GFX8-NEXT:    v_mul_f32_e32 v1, s12, v1
+; GFX8-NEXT:    v_mul_f32_e32 v1, s3, v1
 ; GFX8-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX8-NEXT:    v_rcp_iflag_f32_e32 v2, v2
-; GFX8-NEXT:    v_mul_lo_u32 v3, s2, v0
+; GFX8-NEXT:    v_mul_lo_u32 v2, s2, v0
+; GFX8-NEXT:    s_sub_i32 s2, 0, s9
+; GFX8-NEXT:    v_mul_lo_u32 v4, s2, v1
 ; GFX8-NEXT:    s_sub_i32 s2, 0, s10
-; GFX8-NEXT:    v_mul_f32_e32 v2, s12, v2
-; GFX8-NEXT:    v_mul_hi_u32 v3, v0, v3
-; GFX8-NEXT:    v_cvt_u32_f32_e32 v2, v2
-; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v3, v0
+; GFX8-NEXT:    v_mul_hi_u32 v2, v0, v2
+; GFX8-NEXT:    v_mul_hi_u32 v4, v1, v4
+; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v2, v0
 ; GFX8-NEXT:    v_mul_hi_u32 v0, s4, v0
-; GFX8-NEXT:    v_rcp_iflag_f32_e32 v3, v4
-; GFX8-NEXT:    v_mul_lo_u32 v4, s3, v1
+; GFX8-NEXT:    v_rcp_iflag_f32_e32 v2, v3
+; GFX8-NEXT:    v_cvt_f32_u32_e32 v3, s11
 ; GFX8-NEXT:    v_mul_lo_u32 v0, v0, s8
-; GFX8-NEXT:    v_mul_f32_e32 v3, s12, v3
-; GFX8-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GFX8-NEXT:    v_cvt_u32_f32_e32 v3, v3
+; GFX8-NEXT:    v_mul_f32_e32 v2, s3, v2
+; GFX8-NEXT:    v_cvt_u32_f32_e32 v2, v2
+; GFX8-NEXT:    v_rcp_iflag_f32_e32 v3, v3
 ; GFX8-NEXT:    v_sub_u32_e32 v0, vcc, s4, v0
 ; GFX8-NEXT:    v_subrev_u32_e32 v5, vcc, s8, v0
 ; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
@@ -437,9 +436,11 @@
 ; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v4, v1
 ; GFX8-NEXT:    v_mul_hi_u32 v1, s5, v1
 ; GFX8-NEXT:    v_mul_lo_u32 v4, s2, v2
-; GFX8-NEXT:    s_sub_i32 s2, 0, s11
+; GFX8-NEXT:    v_mul_f32_e32 v3, s3, v3
+; GFX8-NEXT:    v_cvt_u32_f32_e32 v3, v3
 ; GFX8-NEXT:    v_mul_lo_u32 v1, v1, s9
 ; GFX8-NEXT:    v_mul_hi_u32 v4, v2, v4
+; GFX8-NEXT:    s_sub_i32 s2, 0, s11
 ; GFX8-NEXT:    v_sub_u32_e32 v1, vcc, s5, v1
 ; GFX8-NEXT:    v_subrev_u32_e32 v5, vcc, s9, v1
 ; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
diff --git a/llvm/test/CodeGen/AMDGPU/urem64.ll b/llvm/test/CodeGen/AMDGPU/urem64.ll
--- a/llvm/test/CodeGen/AMDGPU/urem64.ll
+++ b/llvm/test/CodeGen/AMDGPU/urem64.ll
@@ -6,95 +6,96 @@
 ; GCN-LABEL: s_test_urem_i64:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0xd
-; GCN-NEXT:    v_mov_b32_e32 v2, 0
-; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
-; GCN-NEXT:    s_mov_b32 s7, 0xf000
-; GCN-NEXT:    s_mov_b32 s6, -1
+; GCN-NEXT:    v_mov_b32_e32 v3, 0
+; GCN-NEXT:    s_mov_b32 s11, 0xf000
+; GCN-NEXT:    s_mov_b32 s10, -1
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s12
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s13
-; GCN-NEXT:    s_sub_u32 s2, 0, s12
-; GCN-NEXT:    s_subb_u32 s3, 0, s13
-; GCN-NEXT:    s_mov_b32 s4, s8
+; GCN-NEXT:    s_sub_u32 s8, 0, s12
+; GCN-NEXT:    s_subb_u32 s4, 0, s13
 ; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
 ; GCN-NEXT:    v_rcp_f32_e32 v0, v0
 ; GCN-NEXT:    v_mov_b32_e32 v1, 0
-; GCN-NEXT:    s_mov_b32 s5, s9
 ; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v0
-; GCN-NEXT:    v_trunc_f32_e32 v3, v3
-; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v3
+; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
+; GCN-NEXT:    v_trunc_f32_e32 v2, v2
+; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
-; GCN-NEXT:    v_mul_hi_u32 v5, s2, v0
-; GCN-NEXT:    v_mul_lo_u32 v4, s2, v3
-; GCN-NEXT:    v_mul_lo_u32 v7, s3, v0
-; GCN-NEXT:    v_mul_lo_u32 v6, s2, v0
+; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
+; GCN-NEXT:    v_mul_hi_u32 v5, s8, v0
+; GCN-NEXT:    v_mul_lo_u32 v4, s8, v2
+; GCN-NEXT:    v_mul_lo_u32 v7, s4, v0
+; GCN-NEXT:    v_mul_lo_u32 v6, s8, v0
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
 ; GCN-NEXT:    v_mul_hi_u32 v5, v0, v6
 ; GCN-NEXT:    v_mul_lo_u32 v7, v0, v4
 ; GCN-NEXT:    v_mul_hi_u32 v9, v0, v4
-; GCN-NEXT:    v_mul_lo_u32 v8, v3, v6
-; GCN-NEXT:    v_mul_hi_u32 v6, v3, v6
+; GCN-NEXT:    v_mul_hi_u32 v8, v2, v6
+; GCN-NEXT:    v_mul_lo_u32 v6, v2, v6
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v2, v9, vcc
-; GCN-NEXT:    v_mul_hi_u32 v9, v3, v4
-; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v6, vcc
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v9, v1, vcc
+; GCN-NEXT:    v_mul_hi_u32 v10, v2, v4
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v3, v9, vcc
+; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
+; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v8, vcc
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v1, vcc
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v4
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v2, v6, vcc
-; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v3, v5, s[0:1]
-; GCN-NEXT:    v_mul_lo_u32 v6, s2, v4
-; GCN-NEXT:    v_mul_hi_u32 v7, s2, v0
-; GCN-NEXT:    v_mul_lo_u32 v8, s3, v0
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; GCN-NEXT:    v_mul_lo_u32 v7, s2, v0
+; GCN-NEXT:    v_add_i32_e64 v0, s[2:3], v0, v4
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v3, v6, vcc
+; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v2, v5, s[2:3]
+; GCN-NEXT:    v_mul_hi_u32 v6, s8, v0
+; GCN-NEXT:    v_mul_lo_u32 v7, s8, v4
+; GCN-NEXT:    v_mul_lo_u32 v8, s4, v0
+; GCN-NEXT:    v_mul_lo_u32 v9, s8, v0
+; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
-; GCN-NEXT:    v_mul_lo_u32 v10, v0, v6
-; GCN-NEXT:    v_mul_hi_u32 v12, v0, v6
-; GCN-NEXT:    v_mul_hi_u32 v11, v0, v7
-; GCN-NEXT:    v_mul_hi_u32 v9, v4, v7
-; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
-; GCN-NEXT:    v_mul_hi_u32 v8, v4, v6
-; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v2, v12, vcc
+; GCN-NEXT:    v_mul_lo_u32 v8, v0, v6
+; GCN-NEXT:    v_mul_hi_u32 v10, v0, v9
+; GCN-NEXT:    v_mul_hi_u32 v11, v0, v6
+; GCN-NEXT:    v_mul_hi_u32 v12, v4, v9
+; GCN-NEXT:    v_mul_lo_u32 v9, v4, v9
+; GCN-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
+; GCN-NEXT:    v_mul_hi_u32 v7, v4, v6
+; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v3, v11, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v4, v4, v6
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
-; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v11, v9, vcc
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v8, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v2, v6, vcc
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
-; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v6, s[0:1]
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v9
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v12, vcc
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v7, v1, vcc
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v3, v7, vcc
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; GCN-NEXT:    v_addc_u32_e64 v2, vcc, v2, v6, s[2:3]
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
-; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; GCN-NEXT:    v_mul_lo_u32 v4, s10, v3
-; GCN-NEXT:    v_mul_hi_u32 v5, s10, v0
-; GCN-NEXT:    v_mul_hi_u32 v6, s10, v3
-; GCN-NEXT:    v_mul_hi_u32 v7, s11, v3
-; GCN-NEXT:    v_mul_lo_u32 v3, s11, v3
+; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc
+; GCN-NEXT:    s_waitcnt lgkmcnt(0)
+; GCN-NEXT:    v_mul_lo_u32 v4, s6, v2
+; GCN-NEXT:    v_mul_hi_u32 v5, s6, v0
+; GCN-NEXT:    v_mul_hi_u32 v6, s6, v2
+; GCN-NEXT:    v_mul_hi_u32 v7, s7, v2
+; GCN-NEXT:    v_mul_lo_u32 v2, s7, v2
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v2, v6, vcc
-; GCN-NEXT:    v_mul_lo_u32 v6, s11, v0
-; GCN-NEXT:    v_mul_hi_u32 v0, s11, v0
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v3, v6, vcc
+; GCN-NEXT:    v_mul_lo_u32 v6, s7, v0
+; GCN-NEXT:    v_mul_hi_u32 v0, s7, v0
+; GCN-NEXT:    s_mov_b32 s8, s4
+; GCN-NEXT:    s_mov_b32 s9, s5
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
 ; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v5, v0, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v7, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v2, v1, vcc
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v3, v1, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v1, s12, v1
 ; GCN-NEXT:    v_mul_hi_u32 v2, s12, v0
 ; GCN-NEXT:    v_mul_lo_u32 v3, s13, v0
 ; GCN-NEXT:    v_mul_lo_u32 v0, s12, v0
 ; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
 ; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
-; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s11, v1
+; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s7, v1
 ; GCN-NEXT:    v_mov_b32_e32 v3, s13
-; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s10, v0
+; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
 ; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
 ; GCN-NEXT:    v_subrev_i32_e64 v4, s[0:1], s12, v0
 ; GCN-NEXT:    v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
@@ -109,7 +110,7 @@
 ; GCN-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
 ; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
 ; GCN-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[0:1]
-; GCN-NEXT:    v_mov_b32_e32 v5, s11
+; GCN-NEXT:    v_mov_b32_e32 v5, s7
 ; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v5, v1, vcc
 ; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s13, v1
 ; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
@@ -121,7 +122,7 @@
 ; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
 ; GCN-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[0:1]
 ; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
-; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
 ; GCN-NEXT:    s_endpgm
 ;
 ; GCN-IR-LABEL: s_test_urem_i64:
@@ -252,23 +253,23 @@
 ; GCN-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v5
-; GCN-NEXT:    v_mul_hi_u32 v8, v6, v4
-; GCN-NEXT:    v_mul_lo_u32 v9, v6, v5
-; GCN-NEXT:    v_mul_lo_u32 v10, v7, v4
-; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
-; GCN-NEXT:    v_mul_lo_u32 v9, v6, v4
-; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; GCN-NEXT:    v_mul_hi_u32 v9, v6, v4
+; GCN-NEXT:    v_mul_lo_u32 v8, v6, v5
+; GCN-NEXT:    v_mul_lo_u32 v11, v7, v4
+; GCN-NEXT:    v_mul_lo_u32 v10, v6, v4
+; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
+; GCN-NEXT:    v_mul_hi_u32 v9, v4, v10
 ; GCN-NEXT:    v_mul_lo_u32 v11, v4, v8
-; GCN-NEXT:    v_mul_hi_u32 v10, v4, v8
-; GCN-NEXT:    v_mul_hi_u32 v12, v4, v9
+; GCN-NEXT:    v_mul_hi_u32 v12, v4, v8
 ; GCN-NEXT:    v_mul_hi_u32 v15, v5, v8
 ; GCN-NEXT:    v_mul_lo_u32 v8, v5, v8
-; GCN-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
-; GCN-NEXT:    v_mul_lo_u32 v12, v5, v9
-; GCN-NEXT:    v_mul_hi_u32 v9, v5, v9
-; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v14, v10, vcc
-; GCN-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
-; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v10, v9, vcc
+; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v14, v12, vcc
+; GCN-NEXT:    v_mul_lo_u32 v12, v5, v10
+; GCN-NEXT:    v_mul_hi_u32 v10, v5, v10
+; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
+; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v11, v10, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v15, v13, vcc
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
 ; GCN-NEXT:    v_add_i32_e64 v4, s[4:5], v4, v8
@@ -280,17 +281,17 @@
 ; GCN-NEXT:    v_mul_lo_u32 v6, v6, v4
 ; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
 ; GCN-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
-; GCN-NEXT:    v_mul_lo_u32 v12, v4, v7
-; GCN-NEXT:    v_mul_hi_u32 v15, v4, v6
-; GCN-NEXT:    v_mul_hi_u32 v16, v4, v7
-; GCN-NEXT:    v_mul_hi_u32 v11, v8, v6
+; GCN-NEXT:    v_mul_lo_u32 v11, v4, v7
+; GCN-NEXT:    v_mul_hi_u32 v12, v4, v6
+; GCN-NEXT:    v_mul_hi_u32 v15, v4, v7
+; GCN-NEXT:    v_mul_hi_u32 v16, v8, v6
 ; GCN-NEXT:    v_mul_lo_u32 v6, v8, v6
-; GCN-NEXT:    v_add_i32_e32 v12, vcc, v15, v12
+; GCN-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
 ; GCN-NEXT:    v_mul_hi_u32 v10, v8, v7
-; GCN-NEXT:    v_addc_u32_e32 v15, vcc, v14, v16, vcc
+; GCN-NEXT:    v_addc_u32_e32 v12, vcc, v14, v15, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v7, v8, v7
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, v12, v6
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v15, v11, vcc
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v11, v6
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v12, v16, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v10, v13, vcc
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
 ; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v14, v8, vcc
@@ -438,8 +439,8 @@
 ; GCN-IR-NEXT:    v_mul_hi_u32 v6, v2, v4
 ; GCN-IR-NEXT:    v_mul_lo_u32 v3, v3, v4
 ; GCN-IR-NEXT:    v_mul_lo_u32 v2, v2, v4
-; GCN-IR-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
+; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, v6, v5
+; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
 ; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
 ; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
 ; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
@@ -509,85 +510,85 @@
 define amdgpu_kernel void @s_test_urem31_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
 ; GCN-LABEL: s_test_urem31_v2i64:
 ; GCN:       ; %bb.0:
+; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x11
 ; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
-; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x11
+; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xd
 ; GCN-NEXT:    s_mov_b32 s7, 0xf000
 ; GCN-NEXT:    s_mov_b32 s6, -1
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-NEXT:    s_lshr_b32 s2, s9, 1
+; GCN-NEXT:    s_lshr_b32 s8, s9, 1
+; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s8
 ; GCN-NEXT:    s_lshr_b32 s0, s1, 1
-; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s0
-; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s2
-; GCN-NEXT:    s_lshr_b32 s3, s3, 1
-; GCN-NEXT:    v_cvt_f32_u32_e32 v4, s3
+; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s0
+; GCN-NEXT:    s_lshr_b32 s2, s11, 1
 ; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
-; GCN-NEXT:    s_lshr_b32 s1, s11, 1
-; GCN-NEXT:    v_cvt_f32_u32_e32 v3, s1
+; GCN-NEXT:    v_cvt_f32_u32_e32 v3, s2
+; GCN-NEXT:    s_lshr_b32 s1, s3, 1
+; GCN-NEXT:    v_cvt_f32_u32_e32 v5, s1
 ; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
 ; GCN-NEXT:    v_trunc_f32_e32 v2, v2
-; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v2
-; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
-; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v4
-; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
-; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v5, vcc
-; GCN-NEXT:    v_mul_lo_u32 v0, v0, s0
-; GCN-NEXT:    v_mul_f32_e32 v2, v3, v2
-; GCN-NEXT:    v_trunc_f32_e32 v2, v2
-; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v2
-; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
-; GCN-NEXT:    v_mad_f32 v2, -v2, v4, v3
-; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v4
-; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
-; GCN-NEXT:    v_mul_lo_u32 v2, v2, s3
+; GCN-NEXT:    v_mad_f32 v4, -v2, v0, v1
+; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
+; GCN-NEXT:    v_rcp_iflag_f32_e32 v6, v3
+; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v0
 ; GCN-NEXT:    v_mov_b32_e32 v1, 0
+; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
+; GCN-NEXT:    v_mul_f32_e32 v2, v5, v6
+; GCN-NEXT:    v_trunc_f32_e32 v2, v2
+; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v2
+; GCN-NEXT:    v_mad_f32 v2, -v2, v3, v5
+; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v3
+; GCN-NEXT:    v_mul_lo_u32 v0, v0, s8
+; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v4, vcc
+; GCN-NEXT:    v_mul_lo_u32 v2, v2, s2
+; GCN-NEXT:    v_mov_b32_e32 v3, v1
+; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s0, v0
 ; GCN-NEXT:    s_brev_b32 s0, -2
-; GCN-NEXT:    v_and_b32_e32 v0, s0, v0
 ; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s1, v2
+; GCN-NEXT:    v_and_b32_e32 v0, s0, v0
 ; GCN-NEXT:    v_and_b32_e32 v2, s0, v2
-; GCN-NEXT:    v_mov_b32_e32 v3, v1
 ; GCN-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
 ; GCN-NEXT:    s_endpgm
 ;
 ; GCN-IR-LABEL: s_test_urem31_v2i64:
 ; GCN-IR:       ; %bb.0:
+; GCN-IR-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x11
 ; GCN-IR-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-IR-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
-; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x11
+; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xd
 ; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
 ; GCN-IR-NEXT:    s_mov_b32 s6, -1
 ; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-IR-NEXT:    s_lshr_b32 s2, s9, 1
+; GCN-IR-NEXT:    s_lshr_b32 s8, s9, 1
+; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s8
 ; GCN-IR-NEXT:    s_lshr_b32 s0, s1, 1
-; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s0
-; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s2
-; GCN-IR-NEXT:    s_lshr_b32 s3, s3, 1
-; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v4, s3
+; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s0
+; GCN-IR-NEXT:    s_lshr_b32 s2, s11, 1
 ; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
-; GCN-IR-NEXT:    s_lshr_b32 s1, s11, 1
-; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v3, s1
+; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v3, s2
+; GCN-IR-NEXT:    s_lshr_b32 s1, s3, 1
+; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v5, s1
 ; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
 ; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
-; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v5, v2
-; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
-; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v4
-; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
-; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v5, vcc
-; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s0
-; GCN-IR-NEXT:    v_mul_f32_e32 v2, v3, v2
-; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
-; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v5, v2
-; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
-; GCN-IR-NEXT:    v_mad_f32 v2, -v2, v4, v3
-; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v4
-; GCN-IR-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
-; GCN-IR-NEXT:    v_mul_lo_u32 v2, v2, s3
+; GCN-IR-NEXT:    v_mad_f32 v4, -v2, v0, v1
+; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v2, v2
+; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v6, v3
+; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v0
 ; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
+; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
+; GCN-IR-NEXT:    v_mul_f32_e32 v2, v5, v6
+; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
+; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v4, v2
+; GCN-IR-NEXT:    v_mad_f32 v2, -v2, v3, v5
+; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v3
+; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s8
+; GCN-IR-NEXT:    v_addc_u32_e32 v2, vcc, 0, v4, vcc
+; GCN-IR-NEXT:    v_mul_lo_u32 v2, v2, s2
+; GCN-IR-NEXT:    v_mov_b32_e32 v3, v1
+; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s0, v0
 ; GCN-IR-NEXT:    s_brev_b32 s0, -2
-; GCN-IR-NEXT:    v_and_b32_e32 v0, s0, v0
 ; GCN-IR-NEXT:    v_sub_i32_e32 v2, vcc, s1, v2
+; GCN-IR-NEXT:    v_and_b32_e32 v0, s0, v0
 ; GCN-IR-NEXT:    v_and_b32_e32 v2, s0, v2
-; GCN-IR-NEXT:    v_mov_b32_e32 v3, v1
 ; GCN-IR-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
 ; GCN-IR-NEXT:    s_endpgm
   %1 = lshr <2 x i64> %x, <i64 33, i64 33>
@@ -659,85 +660,85 @@
 define amdgpu_kernel void @s_test_urem23_64_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
 ; GCN-LABEL: s_test_urem23_64_v2i64:
 ; GCN:       ; %bb.0:
+; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x11
 ; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
-; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x11
+; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xd
 ; GCN-NEXT:    s_mov_b32 s7, 0xf000
 ; GCN-NEXT:    s_mov_b32 s6, -1
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-NEXT:    s_lshr_b32 s2, s9, 1
+; GCN-NEXT:    s_lshr_b32 s8, s9, 1
+; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s8
 ; GCN-NEXT:    s_lshr_b32 s0, s1, 1
-; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s0
-; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s2
-; GCN-NEXT:    s_lshr_b32 s3, s3, 9
-; GCN-NEXT:    v_cvt_f32_u32_e32 v4, s3
+; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s0
+; GCN-NEXT:    s_lshr_b32 s2, s11, 9
 ; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
-; GCN-NEXT:    s_lshr_b32 s1, s11, 9
-; GCN-NEXT:    v_cvt_f32_u32_e32 v3, s1
+; GCN-NEXT:    v_cvt_f32_u32_e32 v3, s2
+; GCN-NEXT:    s_lshr_b32 s1, s3, 9
+; GCN-NEXT:    v_cvt_f32_u32_e32 v5, s1
 ; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
 ; GCN-NEXT:    v_trunc_f32_e32 v2, v2
-; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v2
-; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
-; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v4
-; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
-; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v5, vcc
-; GCN-NEXT:    v_mul_lo_u32 v0, v0, s0
-; GCN-NEXT:    v_mul_f32_e32 v2, v3, v2
-; GCN-NEXT:    v_trunc_f32_e32 v2, v2
-; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v2
-; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
-; GCN-NEXT:    v_mad_f32 v2, -v2, v4, v3
-; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v4
-; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
-; GCN-NEXT:    v_mul_lo_u32 v2, v2, s3
+; GCN-NEXT:    v_mad_f32 v4, -v2, v0, v1
+; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
+; GCN-NEXT:    v_rcp_iflag_f32_e32 v6, v3
+; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v0
 ; GCN-NEXT:    v_mov_b32_e32 v1, 0
+; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
+; GCN-NEXT:    v_mul_f32_e32 v2, v5, v6
+; GCN-NEXT:    v_trunc_f32_e32 v2, v2
+; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v2
+; GCN-NEXT:    v_mad_f32 v2, -v2, v3, v5
+; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v3
+; GCN-NEXT:    v_mul_lo_u32 v0, v0, s8
+; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v4, vcc
+; GCN-NEXT:    v_mul_lo_u32 v2, v2, s2
+; GCN-NEXT:    v_mov_b32_e32 v3, v1
+; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s0, v0
 ; GCN-NEXT:    s_brev_b32 s0, -2
-; GCN-NEXT:    v_and_b32_e32 v0, s0, v0
 ; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s1, v2
+; GCN-NEXT:    v_and_b32_e32 v0, s0, v0
 ; GCN-NEXT:    v_and_b32_e32 v2, s0, v2
-; GCN-NEXT:    v_mov_b32_e32 v3, v1
 ; GCN-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
 ; GCN-NEXT:    s_endpgm
 ;
 ; GCN-IR-LABEL: s_test_urem23_64_v2i64:
 ; GCN-IR:       ; %bb.0:
+; GCN-IR-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x11
 ; GCN-IR-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-IR-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
-; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x11
+; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xd
 ; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
 ; GCN-IR-NEXT:    s_mov_b32 s6, -1
 ; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-IR-NEXT:    s_lshr_b32 s2, s9, 1
+; GCN-IR-NEXT:    s_lshr_b32 s8, s9, 1
+; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s8
 ; GCN-IR-NEXT:    s_lshr_b32 s0, s1, 1
-; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s0
-; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s2
-; GCN-IR-NEXT:    s_lshr_b32 s3, s3, 9
-; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v4, s3
+; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s0
+; GCN-IR-NEXT:    s_lshr_b32 s2, s11, 9
 ; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
-; GCN-IR-NEXT:    s_lshr_b32 s1, s11, 9
-; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v3, s1
+; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v3, s2
+; GCN-IR-NEXT:    s_lshr_b32 s1, s3, 9
+; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v5, s1
 ; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
 ; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
-; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v5, v2
-; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
-; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v4
-; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
-; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v5, vcc
-; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s0
-; GCN-IR-NEXT:    v_mul_f32_e32 v2, v3, v2
-; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
-; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v5, v2
-; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
-; GCN-IR-NEXT:    v_mad_f32 v2, -v2, v4, v3
-; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v4
-; GCN-IR-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
-; GCN-IR-NEXT:    v_mul_lo_u32 v2, v2, s3
+; GCN-IR-NEXT:    v_mad_f32 v4, -v2, v0, v1
+; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v2, v2
+; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v6, v3
+; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v0
 ; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
+; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
+; GCN-IR-NEXT:    v_mul_f32_e32 v2, v5, v6
+; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
+; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v4, v2
+; GCN-IR-NEXT:    v_mad_f32 v2, -v2, v3, v5
+; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v3
+; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s8
+; GCN-IR-NEXT:    v_addc_u32_e32 v2, vcc, 0, v4, vcc
+; GCN-IR-NEXT:    v_mul_lo_u32 v2, v2, s2
+; GCN-IR-NEXT:    v_mov_b32_e32 v3, v1
+; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s0, v0
 ; GCN-IR-NEXT:    s_brev_b32 s0, -2
-; GCN-IR-NEXT:    v_and_b32_e32 v0, s0, v0
 ; GCN-IR-NEXT:    v_sub_i32_e32 v2, vcc, s1, v2
+; GCN-IR-NEXT:    v_and_b32_e32 v0, s0, v0
 ; GCN-IR-NEXT:    v_and_b32_e32 v2, s0, v2
-; GCN-IR-NEXT:    v_mov_b32_e32 v3, v1
 ; GCN-IR-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
 ; GCN-IR-NEXT:    s_endpgm
   %1 = lshr <2 x i64> %x, <i64 33, i64 41>
@@ -751,7 +752,7 @@
 ; GCN-LABEL: s_test_urem_k_num_i64:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GCN-NEXT:    v_mov_b32_e32 v2, 0
+; GCN-NEXT:    v_mov_b32_e32 v3, 0
 ; GCN-NEXT:    s_mov_b32 s11, 0xf000
 ; GCN-NEXT:    s_mov_b32 s10, -1
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
@@ -765,13 +766,13 @@
 ; GCN-NEXT:    v_mov_b32_e32 v1, 0
 ; GCN-NEXT:    s_mov_b32 s9, s5
 ; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v0
-; GCN-NEXT:    v_trunc_f32_e32 v3, v3
-; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v3
+; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
+; GCN-NEXT:    v_trunc_f32_e32 v2, v2
+; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
+; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
 ; GCN-NEXT:    v_mul_hi_u32 v5, s2, v0
-; GCN-NEXT:    v_mul_lo_u32 v4, s2, v3
+; GCN-NEXT:    v_mul_lo_u32 v4, s2, v2
 ; GCN-NEXT:    v_mul_lo_u32 v7, s3, v0
 ; GCN-NEXT:    v_mul_lo_u32 v6, s2, v0
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
@@ -779,48 +780,48 @@
 ; GCN-NEXT:    v_mul_hi_u32 v5, v0, v6
 ; GCN-NEXT:    v_mul_lo_u32 v7, v0, v4
 ; GCN-NEXT:    v_mul_hi_u32 v9, v0, v4
-; GCN-NEXT:    v_mul_hi_u32 v8, v3, v6
-; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
+; GCN-NEXT:    v_mul_hi_u32 v8, v2, v6
+; GCN-NEXT:    v_mul_lo_u32 v6, v2, v6
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; GCN-NEXT:    v_mul_hi_u32 v10, v3, v4
-; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v2, v9, vcc
-; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
+; GCN-NEXT:    v_mul_hi_u32 v10, v2, v4
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v3, v9, vcc
+; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v8, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v1, vcc
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v4
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v2, v6, vcc
-; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v3, v5, s[0:1]
-; GCN-NEXT:    v_mul_lo_u32 v6, s2, v4
-; GCN-NEXT:    v_mul_hi_u32 v7, s2, v0
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v3, v6, vcc
+; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v2, v5, s[0:1]
+; GCN-NEXT:    v_mul_hi_u32 v6, s2, v0
+; GCN-NEXT:    v_mul_lo_u32 v7, s2, v4
 ; GCN-NEXT:    v_mul_lo_u32 v8, s3, v0
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; GCN-NEXT:    v_mul_lo_u32 v7, s2, v0
+; GCN-NEXT:    v_mul_lo_u32 v9, s2, v0
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
-; GCN-NEXT:    v_mul_lo_u32 v10, v0, v6
-; GCN-NEXT:    v_mul_hi_u32 v12, v0, v6
-; GCN-NEXT:    v_mul_hi_u32 v11, v0, v7
-; GCN-NEXT:    v_mul_hi_u32 v9, v4, v7
-; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
-; GCN-NEXT:    v_mul_hi_u32 v8, v4, v6
-; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v2, v12, vcc
+; GCN-NEXT:    v_mul_lo_u32 v8, v0, v6
+; GCN-NEXT:    v_mul_hi_u32 v10, v0, v9
+; GCN-NEXT:    v_mul_hi_u32 v11, v0, v6
+; GCN-NEXT:    v_mul_hi_u32 v12, v4, v9
+; GCN-NEXT:    v_mul_lo_u32 v9, v4, v9
+; GCN-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
+; GCN-NEXT:    v_mul_hi_u32 v7, v4, v6
+; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v3, v11, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v4, v4, v6
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
-; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v11, v9, vcc
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v8, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v2, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
-; GCN-NEXT:    v_addc_u32_e64 v1, vcc, v3, v1, s[0:1]
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v9
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v12, vcc
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v7, v1, vcc
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v3, v1, vcc
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; GCN-NEXT:    v_addc_u32_e64 v1, vcc, v2, v1, s[0:1]
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
 ; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GCN-NEXT:    v_mul_lo_u32 v3, v1, 24
+; GCN-NEXT:    v_mul_lo_u32 v2, v1, 24
 ; GCN-NEXT:    v_mul_hi_u32 v0, v0, 24
 ; GCN-NEXT:    v_mul_hi_u32 v1, v1, 24
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
-; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v2, v1, vcc
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v3, v1, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v1, s7, v0
 ; GCN-NEXT:    v_mul_hi_u32 v2, s6, v0
 ; GCN-NEXT:    v_mul_lo_u32 v0, s6, v0
@@ -958,79 +959,79 @@
 ; GCN-NEXT:    v_mov_b32_e32 v0, 0x4f800000
 ; GCN-NEXT:    v_madak_f32 v0, 0, v0, 0x41c00000
 ; GCN-NEXT:    v_rcp_f32_e32 v0, v0
-; GCN-NEXT:    s_movk_i32 s2, 0xffe8
-; GCN-NEXT:    v_mov_b32_e32 v8, 0
-; GCN-NEXT:    v_mov_b32_e32 v7, 0
+; GCN-NEXT:    s_movk_i32 s4, 0xffe8
+; GCN-NEXT:    v_mov_b32_e32 v6, 0
+; GCN-NEXT:    v_mov_b32_e32 v2, 0
 ; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GCN-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GCN-NEXT:    v_trunc_f32_e32 v1, v1
 ; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
 ; GCN-NEXT:    s_mov_b32 s11, 0xf000
-; GCN-NEXT:    v_mul_hi_u32 v2, v0, s2
-; GCN-NEXT:    v_mul_lo_u32 v3, v1, s2
-; GCN-NEXT:    v_mul_lo_u32 v4, v0, s2
 ; GCN-NEXT:    s_mov_b32 s10, -1
-; GCN-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
-; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT:    v_mul_lo_u32 v5, v0, v2
-; GCN-NEXT:    v_mul_hi_u32 v6, v0, v4
-; GCN-NEXT:    v_mul_hi_u32 v3, v0, v2
-; GCN-NEXT:    v_mul_hi_u32 v9, v1, v2
-; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; GCN-NEXT:    v_mul_lo_u32 v6, v1, v4
-; GCN-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v8, v3, vcc
+; GCN-NEXT:    v_mul_hi_u32 v3, v0, s4
+; GCN-NEXT:    v_mul_lo_u32 v5, v1, s4
+; GCN-NEXT:    v_mul_lo_u32 v4, v0, s4
+; GCN-NEXT:    v_subrev_i32_e32 v3, vcc, v0, v3
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
+; GCN-NEXT:    v_mul_hi_u32 v7, v0, v4
+; GCN-NEXT:    v_mul_lo_u32 v5, v0, v3
+; GCN-NEXT:    v_mul_hi_u32 v8, v0, v3
+; GCN-NEXT:    v_mul_hi_u32 v9, v1, v4
+; GCN-NEXT:    v_mul_lo_u32 v4, v1, v4
+; GCN-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v6, v8, vcc
+; GCN-NEXT:    v_mul_hi_u32 v8, v1, v3
+; GCN-NEXT:    v_mul_lo_u32 v3, v1, v3
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v7, v9, vcc
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v8, v2, vcc
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
+; GCN-NEXT:    v_add_i32_e64 v0, s[2:3], v0, v3
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v5, vcc
+; GCN-NEXT:    v_mul_hi_u32 v5, v0, s4
+; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v1, v4, s[2:3]
+; GCN-NEXT:    v_mul_lo_u32 v7, v3, s4
+; GCN-NEXT:    v_mul_lo_u32 v8, v0, s4
+; GCN-NEXT:    v_subrev_i32_e32 v5, vcc, v0, v5
+; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; GCN-NEXT:    v_mul_lo_u32 v7, v0, v5
+; GCN-NEXT:    v_mul_hi_u32 v9, v0, v8
+; GCN-NEXT:    v_mul_hi_u32 v10, v0, v5
+; GCN-NEXT:    v_mul_hi_u32 v11, v3, v5
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
 ; GCN-NEXT:    s_mov_b32 s8, s4
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v4, vcc
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v9, v7, vcc
-; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v2
-; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v8, v4, vcc
-; GCN-NEXT:    v_mul_hi_u32 v4, v0, s2
-; GCN-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
-; GCN-NEXT:    v_mul_lo_u32 v5, v2, s2
-; GCN-NEXT:    v_mul_lo_u32 v6, v0, s2
-; GCN-NEXT:    v_subrev_i32_e32 v4, vcc, v0, v4
+; GCN-NEXT:    v_add_i32_e32 v7, vcc, v9, v7
+; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v6, v10, vcc
+; GCN-NEXT:    v_mul_lo_u32 v10, v3, v8
+; GCN-NEXT:    v_mul_hi_u32 v8, v3, v8
+; GCN-NEXT:    v_mul_lo_u32 v3, v3, v5
 ; GCN-NEXT:    s_mov_b32 s9, s5
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
-; GCN-NEXT:    v_mul_lo_u32 v5, v0, v4
-; GCN-NEXT:    v_mul_hi_u32 v9, v0, v6
-; GCN-NEXT:    v_mul_hi_u32 v10, v0, v4
-; GCN-NEXT:    v_mul_hi_u32 v11, v2, v4
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, v9, v5
-; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v8, v10, vcc
-; GCN-NEXT:    v_mul_lo_u32 v10, v2, v6
-; GCN-NEXT:    v_mul_hi_u32 v6, v2, v6
-; GCN-NEXT:    v_mul_lo_u32 v2, v2, v4
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v10
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v6, vcc
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v11, v7, vcc
-; GCN-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v4, vcc
-; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
-; GCN-NEXT:    v_addc_u32_e64 v1, vcc, v1, v4, s[0:1]
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT:    v_add_i32_e32 v5, vcc, v7, v10
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v8, vcc
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v11, v2, vcc
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v6, v7, vcc
+; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v4
+; GCN-NEXT:    v_addc_u32_e64 v1, vcc, v1, v5, s[2:3]
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
 ; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GCN-NEXT:    v_mul_lo_u32 v2, s6, v1
-; GCN-NEXT:    v_mul_hi_u32 v3, s6, v0
-; GCN-NEXT:    v_mul_hi_u32 v4, s6, v1
-; GCN-NEXT:    v_mul_hi_u32 v5, s7, v1
+; GCN-NEXT:    v_mul_lo_u32 v3, s6, v1
+; GCN-NEXT:    v_mul_hi_u32 v4, s6, v0
+; GCN-NEXT:    v_mul_hi_u32 v5, s6, v1
+; GCN-NEXT:    v_mul_hi_u32 v7, s7, v1
 ; GCN-NEXT:    v_mul_lo_u32 v1, s7, v1
-; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v8, v4, vcc
-; GCN-NEXT:    v_mul_lo_u32 v4, s7, v0
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v5, vcc
+; GCN-NEXT:    v_mul_lo_u32 v5, s7, v0
 ; GCN-NEXT:    v_mul_hi_u32 v0, s7, v0
-; GCN-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
-; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
-; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v5, v7, vcc
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
+; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v4, v0, vcc
+; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v7, v2, vcc
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v8, v2, vcc
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v6, v2, vcc
 ; GCN-NEXT:    v_mul_hi_u32 v2, v0, 24
 ; GCN-NEXT:    v_mul_lo_u32 v1, v1, 24
 ; GCN-NEXT:    v_mul_lo_u32 v0, v0, 24
@@ -1169,7 +1170,7 @@
 ; GCN-NEXT:    v_mov_b32_e32 v12, 0
 ; GCN-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
 ; GCN-NEXT:    v_rcp_f32_e32 v2, v2
-; GCN-NEXT:    v_mov_b32_e32 v11, 0
+; GCN-NEXT:    v_mov_b32_e32 v10, 0
 ; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
 ; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
 ; GCN-NEXT:    v_trunc_f32_e32 v3, v3
@@ -1178,22 +1179,22 @@
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
 ; GCN-NEXT:    v_mul_hi_u32 v7, v4, v2
 ; GCN-NEXT:    v_mul_lo_u32 v6, v4, v3
-; GCN-NEXT:    v_mul_lo_u32 v8, v5, v2
-; GCN-NEXT:    v_mul_lo_u32 v9, v4, v2
+; GCN-NEXT:    v_mul_lo_u32 v9, v5, v2
+; GCN-NEXT:    v_mul_lo_u32 v8, v4, v2
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
-; GCN-NEXT:    v_mul_lo_u32 v8, v2, v6
-; GCN-NEXT:    v_mul_hi_u32 v10, v2, v9
-; GCN-NEXT:    v_mul_hi_u32 v7, v2, v6
-; GCN-NEXT:    v_mul_hi_u32 v13, v3, v6
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
+; GCN-NEXT:    v_mul_hi_u32 v7, v2, v8
+; GCN-NEXT:    v_mul_lo_u32 v9, v2, v6
+; GCN-NEXT:    v_mul_hi_u32 v11, v2, v6
+; GCN-NEXT:    v_mul_lo_u32 v13, v3, v8
+; GCN-NEXT:    v_mul_hi_u32 v8, v3, v8
+; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v12, v11, vcc
+; GCN-NEXT:    v_mul_hi_u32 v11, v3, v6
 ; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
-; GCN-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
-; GCN-NEXT:    v_mul_lo_u32 v10, v3, v9
-; GCN-NEXT:    v_mul_hi_u32 v9, v3, v9
-; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v12, v7, vcc
-; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
-; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v7, v9, vcc
-; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v13, v11, vcc
+; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v13
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v9, v8, vcc
+; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v11, v10, vcc
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
 ; GCN-NEXT:    v_add_i32_e64 v2, s[4:5], v2, v6
 ; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v12, v8, vcc
@@ -1204,18 +1205,18 @@
 ; GCN-NEXT:    v_mul_lo_u32 v4, v4, v2
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; GCN-NEXT:    v_mul_lo_u32 v10, v2, v5
-; GCN-NEXT:    v_mul_hi_u32 v13, v2, v4
-; GCN-NEXT:    v_mul_hi_u32 v14, v2, v5
-; GCN-NEXT:    v_mul_hi_u32 v9, v6, v4
+; GCN-NEXT:    v_mul_lo_u32 v9, v2, v5
+; GCN-NEXT:    v_mul_hi_u32 v11, v2, v4
+; GCN-NEXT:    v_mul_hi_u32 v13, v2, v5
+; GCN-NEXT:    v_mul_hi_u32 v14, v6, v4
 ; GCN-NEXT:    v_mul_lo_u32 v4, v6, v4
-; GCN-NEXT:    v_add_i32_e32 v10, vcc, v13, v10
+; GCN-NEXT:    v_add_i32_e32 v9, vcc, v11, v9
 ; GCN-NEXT:    v_mul_hi_u32 v8, v6, v5
-; GCN-NEXT:    v_addc_u32_e32 v13, vcc, v12, v14, vcc
+; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v12, v13, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v5, v6, v5
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v10, v4
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v13, v9, vcc
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v8, v11, vcc
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v9, v4
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v11, v14, vcc
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v8, v10, vcc
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v12, v6, vcc
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
@@ -1448,21 +1449,21 @@
 ; GCN-LABEL: s_test_urem24_k_num_i64:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
-; GCN-NEXT:    s_mov_b32 s5, 0x41c00000
+; GCN-NEXT:    s_mov_b32 s4, 0x41c00000
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-NEXT:    s_mov_b32 s2, -1
-; GCN-NEXT:    s_lshr_b32 s4, s3, 8
-; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s4
+; GCN-NEXT:    s_lshr_b32 s2, s3, 8
+; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
 ; GCN-NEXT:    s_mov_b32 s3, 0xf000
 ; GCN-NEXT:    v_rcp_iflag_f32_e32 v1, v0
-; GCN-NEXT:    v_mul_f32_e32 v1, s5, v1
+; GCN-NEXT:    v_mul_f32_e32 v1, s4, v1
 ; GCN-NEXT:    v_trunc_f32_e32 v1, v1
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v1
-; GCN-NEXT:    v_mad_f32 v1, -v1, v0, s5
+; GCN-NEXT:    v_mad_f32 v1, -v1, v0, s4
 ; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
 ; GCN-NEXT:    v_mov_b32_e32 v1, 0
 ; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
-; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
+; GCN-NEXT:    v_mul_lo_u32 v0, v0, s2
+; GCN-NEXT:    s_mov_b32 s2, -1
 ; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
 ; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
 ; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
@@ -1471,21 +1472,21 @@
 ; GCN-IR-LABEL: s_test_urem24_k_num_i64:
 ; GCN-IR:       ; %bb.0:
 ; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
-; GCN-IR-NEXT:    s_mov_b32 s5, 0x41c00000
+; GCN-IR-NEXT:    s_mov_b32 s4, 0x41c00000
 ; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-IR-NEXT:    s_mov_b32 s2, -1
-; GCN-IR-NEXT:    s_lshr_b32 s4, s3, 8
-; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s4
+; GCN-IR-NEXT:    s_lshr_b32 s2, s3, 8
+; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s2
 ; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
 ; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v1, v0
-; GCN-IR-NEXT:    v_mul_f32_e32 v1, s5, v1
+; GCN-IR-NEXT:    v_mul_f32_e32 v1, s4, v1
 ; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
 ; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v2, v1
-; GCN-IR-NEXT:    v_mad_f32 v1, -v1, v0, s5
+; GCN-IR-NEXT:    v_mad_f32 v1, -v1, v0, s4
 ; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
 ; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
 ; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
-; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
+; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s2
+; GCN-IR-NEXT:    s_mov_b32 s2, -1
 ; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
 ; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
 ; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
@@ -1500,51 +1501,47 @@
 ; GCN-LABEL: s_test_urem24_k_den_i64:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
-; GCN-NEXT:    s_mov_b32 s4, 0x46b6fe00
-; GCN-NEXT:    s_mov_b32 s7, 0xf000
-; GCN-NEXT:    s_mov_b32 s6, -1
+; GCN-NEXT:    s_mov_b32 s5, 0x46b6fe00
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-NEXT:    s_lshr_b32 s2, s3, 8
-; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
-; GCN-NEXT:    s_movk_i32 s3, 0x5b7f
-; GCN-NEXT:    s_mov_b32 s5, s1
+; GCN-NEXT:    s_movk_i32 s2, 0x5b7f
+; GCN-NEXT:    s_lshr_b32 s4, s3, 8
+; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s4
+; GCN-NEXT:    s_mov_b32 s3, 0xf000
 ; GCN-NEXT:    v_mul_f32_e32 v1, 0x38331158, v0
 ; GCN-NEXT:    v_trunc_f32_e32 v1, v1
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v1
-; GCN-NEXT:    v_mad_f32 v0, -v1, s4, v0
-; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s4
-; GCN-NEXT:    s_mov_b32 s4, s0
-; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
-; GCN-NEXT:    v_mul_lo_u32 v0, v0, s3
+; GCN-NEXT:    v_mad_f32 v0, -v1, s5, v0
+; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s5
 ; GCN-NEXT:    v_mov_b32_e32 v1, 0
-; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
+; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
+; GCN-NEXT:    v_mul_lo_u32 v0, v0, s2
+; GCN-NEXT:    s_mov_b32 s2, -1
+; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
 ; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
-; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; GCN-NEXT:    s_endpgm
 ;
 ; GCN-IR-LABEL: s_test_urem24_k_den_i64:
 ; GCN-IR:       ; %bb.0:
 ; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
-; GCN-IR-NEXT:    s_mov_b32 s4, 0x46b6fe00
-; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
-; GCN-IR-NEXT:    s_mov_b32 s6, -1
+; GCN-IR-NEXT:    s_mov_b32 s5, 0x46b6fe00
 ; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-IR-NEXT:    s_lshr_b32 s2, s3, 8
-; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s2
-; GCN-IR-NEXT:    s_movk_i32 s3, 0x5b7f
-; GCN-IR-NEXT:    s_mov_b32 s5, s1
+; GCN-IR-NEXT:    s_movk_i32 s2, 0x5b7f
+; GCN-IR-NEXT:    s_lshr_b32 s4, s3, 8
+; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s4
+; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
 ; GCN-IR-NEXT:    v_mul_f32_e32 v1, 0x38331158, v0
 ; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
 ; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v2, v1
-; GCN-IR-NEXT:    v_mad_f32 v0, -v1, s4, v0
-; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s4
-; GCN-IR-NEXT:    s_mov_b32 s4, s0
-; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
-; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s3
+; GCN-IR-NEXT:    v_mad_f32 v0, -v1, s5, v0
+; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s5
 ; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
-; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
+; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
+; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s2
+; GCN-IR-NEXT:    s_mov_b32 s2, -1
+; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
 ; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
-; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; GCN-IR-NEXT:    s_endpgm
   %x.shr = lshr i64 %x, 40
   %result = urem i64 %x.shr, 23423