[RISCV][GlobalISel] Add lowerCall for calling convention

[nitinjohnraj]

Summary

This patch implements minimal support for lowering function calls to callees with arguments and/or return values according to the RISC-V calling convention. Integer, pointer and aggregate types are supported.

Feedback is very much appreciated.

[lewis-revill]

Rebase, update test structure. Correct missing defs by adding CallReturnHandler.

[Joe]

If you're supporting a pointer value return type, should there be a test for this?

Other than that, this looks fine to me - although should wait until somebody more experienced looks at it.

Side note: Would it be worth, in the future, to outline the process of finding In/OutputArgs and ArgInfos to something like a computeOutgoingArgs/computeIncomingArgs that fills a list of ISD::In/OutputArg and ArgInfos? Or would this just obfuscate things?

[lewis-revill]

Add test for pointer return type

[lewis-revill]

Bug fix - add target flags to call instruction.

[lewis-revill]

Rebased, and updated where appropriate to continue to build correctly.

[arsenm]

llvm/lib/Target/RISCV/RISCVCallLowering.cpp

330

Same comment on the other half of the call lowering patches

[lewis-revill]

Use ValueAssigners to avoid rewriting generic infrastructure and use determineAndHandleAssignments instead.

[arsenm]

llvm/lib/Target/RISCV/RISCVCallLowering.cpp

256

Not sure why you're bothering to filter these out. splitToValueTypes should handle near everything (I'm aware of some assertions on weird non-byte element sized vectors)

[nitinjohnraj]

Rebased

[arsenm]

llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calls.ll

266

Use opaque pointers

268

Could use sret/byval tests. Also cases where the argument/return list is too long and needs to go to the stack

[eopXD]

llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp

305 ↗

(On Diff #511197)

This seems to contradict with the description of this patch, "Simple non-aggregate types are supported."

[nitinjohnraj]

Added tests for aggregate types, sret and byval

[nitinjohnraj]

llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp

305 ↗

(On Diff #511197)

You're right. I've updated the description and added a test accordingly.

llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calls.ll

266

Updated.

268

Could use sret/byval tests.

I've added these.

Also cases where the argument/return list is too long and needs to go to the stack

Are there other examples of a test like this?

[nitinjohnraj]

As stated in the parent revision, we will correctly handle byval, sret and cases where the number of arguments exceed the number of available registers in a future patch.

[arsenm]

llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp

259 ↗

(On Diff #524377)

Should add some tail call cases. You should set IsTailCall to false if you aren’t handling them

[nitinjohnraj]

Set IsTailCall to false. We will handle tail calls in a future patch.

llvm/lib/Target/RISCV/RISCVCallLowering.h

bool lowerReturnVal(MachineIRBuilder &MIRBuilder, const Value *Val,
                       ArrayRef<Register> VRegs, MachineInstrBuilder &Ret) const;
 
   /// A function of this type is used to perform value split action.
   using SplitArgTy = std::function<void(ArrayRef<Register>, int)>;
 
   template <typename T>
   void setISDArgsForCallingConv(const Function &F, const ArgInfo &OrigArg,
                                 SmallVectorImpl<EVT> &SplitVTs,
-                                SmallVectorImpl<T> &ISDArgs, bool isRet) const;
+                                SmallVectorImpl<T> &ISDArgs, CallingConv::ID CC,
+                                bool isRet) const;
 
   void splitToValueTypes(const ArgInfo &OrigArg,
                          SmallVectorImpl<ArgInfo> &SplitArgs,
                          SmallVectorImpl<EVT> &SplitVTs, MachineFunction &MF,
                          SplitArgTy PerformArgSplit) const;
 
   template <typename T>
   void updateArgLocInfo(SmallVectorImpl<CCValAssign> &ArgLocs,
                         const SmallVectorImpl<T> &Arguments) const;
 };
 
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_RISCV_RISCVCALLLOWERING_H

llvm/lib/Target/RISCV/RISCVCallLowering.cpp

bool assignArg(unsigned ValNo, MVT ValVT, MVT LocVT,
                  const CallLowering::ArgInfo &Info, ISD::ArgFlagsTy Flags,
                  CCState &State) override {
     if (AssignFn)
       return AssignFn(ValNo, ValVT, LocVT, LocInfo, Flags, State);
     return false;
   }
 };
 
+struct CallReturnHandler : public IncomingValueHandler {
+  CallReturnHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI,
+                    CCAssignFn *AssignFn, MachineInstrBuilder &MIB)
+      : IncomingValueHandler(B, MRI, AssignFn), MIB(MIB) {}
+
+  MachineInstrBuilder MIB;
+
+  void assignValueToReg(Register ValVReg, Register PhysReg,
+                        CCValAssign &VA) override {
+    // Copy argument received in physical register to desired VReg.
+    MIB.addDef(PhysReg, RegState::Implicit);
+    MIRBuilder.buildCopy(ValVReg, PhysReg);
+  }
+};
+
 } // namespace
 
 RISCVCallLowering::RISCVCallLowering(const RISCVTargetLowering &TLI)
     : CallLowering(&TLI) {}
 
 bool RISCVCallLowering::lowerReturnVal(MachineIRBuilder &MIRBuilder,
                                        const Value *Val,
                                        ArrayRef<Register> VRegs,
bool RISCVCallLowering::lowerReturnVal(MachineIRBuilder &MIRBuilder,
 
   SmallVector<ArgInfo, 4> SplitRetInfos;
   splitToValueTypes(OrigRetInfo, SplitRetInfos, SplitEVTs, MF,
                     [&](ArrayRef<Register> Regs, int SplitIdx) {
                       MIRBuilder.buildUnmerge(Regs, VRegs[SplitIdx]);
                     });
 
   SmallVector<ISD::OutputArg, 8> Outs;
-  setISDArgsForCallingConv(F, OrigRetInfo, SplitEVTs, Outs, true);
+  setISDArgsForCallingConv(F, OrigRetInfo, SplitEVTs, Outs, F.getCallingConv(),
+                           true);
 
   SmallVector<CCValAssign, 16> ArgLocs;
   CCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs, F.getContext());
 
   TLI.analyzeOutputArgs(MF, CCInfo, Outs, /*IsRet=*/true, nullptr);
   updateArgLocInfo(ArgLocs, Outs);
 
   OutgoingValueHandler Handler(MIRBuilder, MF.getRegInfo(), Ret, nullptr);
for (auto &Arg : F.args()) {
     ArgInfo AInfo(VRegs[Index], Arg.getType());
     setArgFlags(AInfo, Index + AttributeList::FirstArgIndex, DL, F);
 
     SmallVector<EVT, 4> SplitEVTs;
     ComputeValueVTs(TLI, DL, Arg.getType(), SplitEVTs);
     assert(VRegs[Index].size() == SplitEVTs.size() &&
            "For each split Type there should be exactly one VReg.");
 
-    setISDArgsForCallingConv(F, AInfo, SplitEVTs, Ins, /*isRet=*/false);
+    setISDArgsForCallingConv(F, AInfo, SplitEVTs, Ins, F.getCallingConv(),
+                             /*isRet=*/false);
 
     // Handle any required merging from split value types - as indicated in
     // SplitEVTs - from physical registers into the desired VReg. ArgInfo
     // objects are constructed correspondingly and appended to SplitArgInfos.
     splitToValueTypes(AInfo, SplitArgInfos, SplitEVTs, MF,
                       [&](ArrayRef<Register> Regs, int SplitIdx) {
                         auto MIB =
                             MIRBuilder.buildMerge(VRegs[Index][SplitIdx], Regs);
bool RISCVCallLowering::lowerFormalArguments(
   if (!handleAssignments(CCInfo, ArgLocs, MIRBuilder, SplitArgInfos, Handler))
     return false;
 
   return true;
 }
 
 bool RISCVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
                                   CallLoweringInfo &Info) const {
+
+  MachineFunction &MF = MIRBuilder.getMF();
+  const Function &F = MF.getFunction();
+  const DataLayout &DL = MF.getDataLayout();
+  const RISCVTargetLowering &TLI = *getTLI<RISCVTargetLowering>();
+
+  // TODO: Support vararg functions.
+  if (Info.IsVarArg)
+    return false;
+
+  // TODO: Support all argument types.
+  for (auto &AInfo : Info.OrigArgs) {
+    if (AInfo.Ty->isIntegerTy())
+      continue;
+    if (AInfo.Ty->isPointerTy())
+      continue;
+    if (AInfo.Ty->isFloatingPointTy())
+      continue;
+    return false;
+  }
+
+  SmallVector<ArgInfo, 32> SplitArgInfos;
+  SmallVector<ISD::OutputArg, 8> Outs;
+  unsigned Index = 0;
+  for (auto &AInfo : Info.OrigArgs) {
+    SmallVector<EVT, 4> SplitEVTs;
+    ComputeValueVTs(TLI, DL, AInfo.Ty, SplitEVTs);
+    assert(AInfo.Regs.size() == SplitEVTs.size() &&
+           "For each split Type there should be exactly one VReg.");
+
+    setISDArgsForCallingConv(F, AInfo, SplitEVTs, Outs, Info.CallConv,
+                             /*isRet=*/false);
+
+    // Handle any required unmerging of split value types - as indicated in
+    // SplitEVTs - from a given VReg into physical registers. ArgInfo objects
+    // are constructed correspondingly and appended to SplitArgInfos.
+    splitToValueTypes(AInfo, SplitArgInfos, SplitEVTs, MF,
+                      [&](ArrayRef<Register> Regs, int SplitIdx) {
+                        MIRBuilder.buildUnmerge(Regs, AInfo.Regs[SplitIdx]);
+                      });
+
+    ++Index;
+  }
+
+  SmallVector<CCValAssign, 16> ArgLocs;
+  CCState CCInfo(Info.CallConv, Info.IsVarArg, MF, ArgLocs, F.getContext());
+
+  // TODO: Access CC_RISCV_FastCC when using CallingConv::Fast. Preferrably
+  // TLI.CCAssignFnForCall will be implemented and the approach for both CCs
+  // will be unified.
+  if (Info.CallConv == CallingConv::Fast)
+    return false;
+  TLI.analyzeOutputArgs(MF, CCInfo, Outs, /*IsRet=*/false, nullptr);
+  updateArgLocInfo(ArgLocs, Outs);
+
+  if (!Info.Callee.isReg())
+    Info.Callee.setTargetFlags(RISCVII::MO_CALL);
+
+  MachineInstrBuilder Call =
+      MIRBuilder
+          .buildInstrNoInsert(Info.Callee.isReg() ? RISCV::PseudoCALLIndirect
+                                                  : RISCV::PseudoCALL)
+          .add(Info.Callee);
+
+  OutgoingValueHandler ArgHandler(MIRBuilder, MF.getRegInfo(), Call, nullptr);
+  if (!handleAssignments(CCInfo, ArgLocs, MIRBuilder, SplitArgInfos,
+                         ArgHandler))
+    return false;
+
+  MIRBuilder.insertInstr(Call);
+
+  if (Info.OrigRet.Ty->isVoidTy())
+    return true;
+
+  // TODO: Only integer, pointer and aggregate types are supported now.
+  if (!Info.OrigRet.Ty->isIntOrPtrTy() && !Info.OrigRet.Ty->isAggregateType())
+    return false;
+
+  SmallVector<EVT, 4> SplitRetEVTs;
+  ComputeValueVTs(TLI, DL, Info.OrigRet.Ty, SplitRetEVTs);
+  assert(Info.OrigRet.Regs.size() == SplitRetEVTs.size() &&
+         "For each split Type there should be exactly one VReg.");
+
+  SmallVector<ArgInfo, 4> SplitRetInfos;
+  splitToValueTypes(Info.OrigRet, SplitRetInfos, SplitRetEVTs, MF,
+                    [&](ArrayRef<Register> Regs, int SplitIdx) {
+                      MIRBuilder.buildMerge(Info.OrigRet.Regs[SplitIdx], Regs);
+                    });
+
+  SmallVector<ISD::InputArg, 8> Ins;
+  setISDArgsForCallingConv(F, Info.OrigRet, SplitRetEVTs, Ins, Info.CallConv,
+                           /*isRet=*/true);
+
+  SmallVector<CCValAssign, 16> RVLocs;
+  CCState RetCCInfo(Info.CallConv, Info.IsVarArg, MF, RVLocs, F.getContext());
+
+  TLI.analyzeInputArgs(MF, RetCCInfo, Ins, /*IsRet=*/true);
+  updateArgLocInfo(RVLocs, Ins);
+
+  // Assignments should be handled *before* the merging of values takes place.
+  // To ensure this, the insert point is temporarily adjusted to just after the
+  // call instruction.
+  MachineBasicBlock::iterator CallInsertPt = Call;
+  MIRBuilder.setInsertPt(MIRBuilder.getMBB(), std::next(CallInsertPt));
+
+  CallReturnHandler Handler(MIRBuilder, MF.getRegInfo(), nullptr, Call);
+  if (!handleAssignments(RetCCInfo, RVLocs, MIRBuilder, SplitRetInfos, Handler))
     return false;
+
+  // Readjust insert point to end of basic block.
+  MIRBuilder.setMBB(MIRBuilder.getMBB());
+
+  return true;
 }
 
 template <typename T>
-void RISCVCallLowering::setISDArgsForCallingConv(const Function &F,
-                                                 const ArgInfo &OrigArg,
-                                                 SmallVectorImpl<EVT> &SplitVTs,
-                                                 SmallVectorImpl<T> &ISDArgs,
-                                                 bool isRet) const {
+void RISCVCallLowering::setISDArgsForCallingConv(
+    const Function &F, const ArgInfo &OrigArg, SmallVectorImpl<EVT> &SplitVTs,
+    SmallVectorImpl<T> &ISDArgs, CallingConv::ID CC, bool isRet) const {
   const DataLayout &DL = F.getParent()->getDataLayout();
   LLVMContext &Ctx = F.getContext();
-  CallingConv::ID CC = F.getCallingConv();
   const RISCVTargetLowering &TLI = *getTLI<RISCVTargetLowering>();
 
   for (unsigned i = 0, e = SplitVTs.size(); i != e; ++i) {
     EVT VT = SplitVTs[i];
     Type *SplitTy = VT.getTypeForEVT(Ctx);
     MVT RegisterVT = TLI.getRegisterTypeForCallingConv(Ctx, CC, VT);
     unsigned NumParts = TLI.getNumRegistersForCallingConv(Ctx, CC, VT);
 

llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calls.ll

+; RUN: llc -mtriple=riscv32 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV32I %s
+; RUN: llc -mtriple=riscv64 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV64I %s
+
+declare void @void_noargs()
+
+define void @test_call_void_noargs() {
+  ; RV32I-LABEL: name: test_call_void_noargs
+  ; RV32I: bb.1.entry:
+  ; RV32I-NEXT:   PseudoCALL target-flags(riscv-call) @void_noargs, implicit-def $x1
+  ; RV32I-NEXT:   PseudoRET
+
+  ; RV64I-LABEL: name: test_call_void_noargs
+  ; RV64I: bb.1.entry:
+  ; RV64I-NEXT:   PseudoCALL target-flags(riscv-call) @void_noargs, implicit-def $x1
+  ; RV64I-NEXT:   PseudoRET
+entry:
+  call void @void_noargs()
+  ret void
+}
+
+declare void @void_args_i8(i8, i8)
+
+define void @test_call_void_args_i8() {
+  ; RV32I-LABEL: name: test_call_void_args_i8
+  ; RV32I: bb.1.entry:
+  ; RV32I-NEXT:   [[CST1:%[0-9]+]]:_(s8) = G_CONSTANT i8 0
+  ; RV32I-NEXT:   [[CST2:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
+  ; RV32I-NEXT:   [[AEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[CST1]](s8)
+  ; RV32I-NEXT:   $x10 = COPY [[AEXT1]](s32)
+  ; RV32I-NEXT:   [[AEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[CST2]](s8)
+  ; RV32I-NEXT:   $x11 = COPY [[AEXT2]](s32)
+  ; RV32I-NEXT:   PseudoCALL target-flags(riscv-call) @void_args_i8, implicit-def $x1, implicit $x10, implicit $x11
+  ; RV32I-NEXT:   PseudoRET
+
+  ; RV64I-LABEL: name: test_call_void_args_i8
+  ; RV64I: bb.1.entry:
+  ; RV64I-NEXT:   [[CST1:%[0-9]+]]:_(s8) = G_CONSTANT i8 0
+  ; RV64I-NEXT:   [[CST2:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
+  ; RV64I-NEXT:   [[AEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[CST1]](s8)
+  ; RV64I-NEXT:   $x10 = COPY [[AEXT1]](s64)
+  ; RV64I-NEXT:   [[AEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[CST2]](s8)
+  ; RV64I-NEXT:   $x11 = COPY [[AEXT2]](s64)
+  ; RV64I-NEXT:   PseudoCALL target-flags(riscv-call) @void_args_i8, implicit-def $x1, implicit $x10, implicit $x11
+  ; RV64I-NEXT:   PseudoRET
+entry:
+  call void @void_args_i8(i8 0, i8 1)
+  ret void
+}
+
+declare void @void_args_i8_zext(i8 zeroext, i8 zeroext)
+
+define void @test_call_void_args_i8_zext() {
+  ; RV32I-LABEL: name: test_call_void_args_i8_zext
+  ; RV32I: bb.1.entry:
+  ; RV32I-NEXT:   [[CST1:%[0-9]+]]:_(s8) = G_CONSTANT i8 0
+  ; RV32I-NEXT:   [[CST2:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
+  ; RV32I-NEXT:   [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[CST1]](s8)
+  ; RV32I-NEXT:   $x10 = COPY [[ZEXT1]](s32)
+  ; RV32I-NEXT:   [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[CST2]](s8)
+  ; RV32I-NEXT:   $x11 = COPY [[ZEXT2]](s32)
+  ; RV32I-NEXT:   PseudoCALL target-flags(riscv-call) @void_args_i8_zext, implicit-def $x1, implicit $x10, implicit $x11
+  ; RV32I-NEXT:   PseudoRET
+
+  ; RV64I-LABEL: name: test_call_void_args_i8_zext
+  ; RV64I: bb.1.entry:
+  ; RV64I-NEXT:   [[CST1:%[0-9]+]]:_(s8) = G_CONSTANT i8 0
+  ; RV64I-NEXT:   [[CST2:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
+  ; RV64I-NEXT:   [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[CST1]](s8)
+  ; RV64I-NEXT:   $x10 = COPY [[ZEXT1]](s64)
+  ; RV64I-NEXT:   [[ZEXT2:%[0-9]+]]:_(s64) = G_ZEXT [[CST2]](s8)
+  ; RV64I-NEXT:   $x11 = COPY [[ZEXT2]](s64)
+  ; RV64I-NEXT:   PseudoCALL target-flags(riscv-call) @void_args_i8_zext, implicit-def $x1, implicit $x10, implicit $x11
+  ; RV64I-NEXT:   PseudoRET
+entry:
+  call void @void_args_i8_zext(i8 zeroext 0, i8 zeroext 1)
+  ret void
+}
+
+declare void @void_args_i16_sext(i16 signext, i16 signext)
+
+define void @test_call_void_args_i16_sext() {
+  ; RV32I-LABEL: name: test_call_void_args_i16_sext
+  ; RV32I: bb.1.entry:
+  ; RV32I-NEXT:   [[CST1:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
+  ; RV32I-NEXT:   [[CST2:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
+  ; RV32I-NEXT:   [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[CST1]](s16)
+  ; RV32I-NEXT:   $x10 = COPY [[SEXT1]](s32)
+  ; RV32I-NEXT:   [[SEXT2:%[0-9]+]]:_(s32) = G_SEXT [[CST2]](s16)
+  ; RV32I-NEXT:   $x11 = COPY [[SEXT2]](s32)
+  ; RV32I-NEXT:   PseudoCALL target-flags(riscv-call) @void_args_i16_sext, implicit-def $x1, implicit $x10, implicit $x11
+  ; RV32I-NEXT:   PseudoRET
+
+  ; RV64I-LABEL: name: test_call_void_args_i16_sext
+  ; RV64I: bb.1.entry:
+  ; RV64I-NEXT:   [[CST1:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
+  ; RV64I-NEXT:   [[CST2:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
+  ; RV64I-NEXT:   [[SEXT1:%[0-9]+]]:_(s64) = G_SEXT [[CST1]](s16)
+  ; RV64I-NEXT:   $x10 = COPY [[SEXT1]](s64)
+  ; RV64I-NEXT:   [[SEXT2:%[0-9]+]]:_(s64) = G_SEXT [[CST2]](s16)
+  ; RV64I-NEXT:   $x11 = COPY [[SEXT2]](s64)
+  ; RV64I-NEXT:   PseudoCALL target-flags(riscv-call) @void_args_i16_sext, implicit-def $x1, implicit $x10, implicit $x11
+  ; RV64I-NEXT:   PseudoRET
+entry:
+  call void @void_args_i16_sext(i16 signext 0, i16 signext 1)
+  ret void
+}
+
+declare void @void_args_i32(i32, i32)
+
+define void @test_call_void_args_i32() {
+  ; RV32I-LABEL: name: test_call_void_args_i32
+  ; RV32I: bb.1.entry:
+  ; RV32I-NEXT:   [[CST1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+  ; RV32I-NEXT:   [[CST2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+  ; RV32I-NEXT:   $x10 = COPY [[CST1]](s32)
+  ; RV32I-NEXT:   $x11 = COPY [[CST2]](s32)
+  ; RV32I-NEXT:   PseudoCALL target-flags(riscv-call) @void_args_i32, implicit-def $x1, implicit $x10, implicit $x11
+  ; RV32I-NEXT:   PseudoRET
+
+  ; RV64I-LABEL: name: test_call_void_args_i32
+  ; RV64I: bb.1.entry:
+  ; RV64I-NEXT:   [[CST1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+  ; RV64I-NEXT:   [[CST2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+  ; RV64I-NEXT:   [[AEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[CST1]](s32)
+  ; RV64I-NEXT:   $x10 = COPY [[AEXT1]](s64)
+  ; RV64I-NEXT:   [[AEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[CST2]](s32)
+  ; RV64I-NEXT:   $x11 = COPY [[AEXT2]](s64)
+  ; RV64I-NEXT:   PseudoCALL target-flags(riscv-call) @void_args_i32, implicit-def $x1, implicit $x10, implicit $x11
+  ; RV64I-NEXT:   PseudoRET
+entry:
+  call void @void_args_i32(i32 0, i32 1)
+  ret void
+}
+
+declare void @void_args_i64(i64, i64)
+
+define void @test_call_void_args_i64() {
+  ; RV32I-LABEL: name: test_call_void_args_i64
+  ; RV32I: bb.1.entry:
+  ; RV32I-NEXT:   [[CST1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+  ; RV32I-NEXT:   [[CST2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+  ; RV32I-NEXT:   [[CST1_1:%[0-9]+]]:_(s32), [[CST1_2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[CST1]](s64)
+  ; RV32I-NEXT:   [[CST2_1:%[0-9]+]]:_(s32), [[CST2_2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[CST2]](s64)
+  ; RV32I-NEXT:   $x10 = COPY [[CST1_1]](s32)
+  ; RV32I-NEXT:   $x11 = COPY [[CST1_2]](s32)
+  ; RV32I-NEXT:   $x12 = COPY [[CST2_1]](s32)
+  ; RV32I-NEXT:   $x13 = COPY [[CST2_2]](s32)
+  ; RV32I-NEXT:   PseudoCALL target-flags(riscv-call) @void_args_i64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13
+  ; RV32I-NEXT:   PseudoRET
+
+  ; RV64I-LABEL: name: test_call_void_args_i64
+  ; RV64I: bb.1.entry:
+  ; RV64I-NEXT:   [[CST1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+  ; RV64I-NEXT:   [[CST2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+  ; RV64I-NEXT:   $x10 = COPY [[CST1]](s64)
+  ; RV64I-NEXT:   $x11 = COPY [[CST2]](s64)
+  ; RV64I-NEXT:   PseudoCALL target-flags(riscv-call) @void_args_i64, implicit-def $x1, implicit $x10, implicit $x11
+  ; RV64I-NEXT:   PseudoRET
+entry:
+  call void @void_args_i64(i64 0, i64 1)
+  ret void
+}
+
+declare i8 @i8_noargs()
+
+define void @test_call_i8_noargs() {
+  ; RV32I-LABEL: name: test_call_i8_noargs
+  ; RV32I: bb.1.entry:
+  ; RV32I-NEXT:   PseudoCALL target-flags(riscv-call) @i8_noargs, implicit-def $x1
+  ; RV32I-NEXT:   [[VREG1:%[0-9]+]]:_(s32) = COPY $x10
+  ; RV32I-NEXT:   [[VREG:%[0-9]+]]:_(s8) = G_TRUNC [[VREG1]](s32)
+  ; RV32I-NEXT:   PseudoRET
+
+  ; RV64I-LABEL: name: test_call_i8_noargs
+  ; RV64I: bb.1.entry:
+  ; RV64I-NEXT:   PseudoCALL target-flags(riscv-call) @i8_noargs, implicit-def $x1
+  ; RV64I-NEXT:   [[VREG1:%[0-9]+]]:_(s64) = COPY $x10
+  ; RV64I-NEXT:   [[VREG:%[0-9]+]]:_(s8) = G_TRUNC [[VREG1]](s64)
+  ; RV64I-NEXT:   PseudoRET
+entry:
+  %a = call i8 @i8_noargs()
+  ret void
+}
+
+declare i16 @i16_noargs()
+
+define void @test_call_i16_noargs() {
+  ; RV32I-LABEL: name: test_call_i16_noargs
+  ; RV32I: bb.1.entry:
+  ; RV32I-NEXT:   PseudoCALL target-flags(riscv-call) @i16_noargs, implicit-def $x1
+  ; RV32I-NEXT:   [[VREG1:%[0-9]+]]:_(s32) = COPY $x10
+  ; RV32I-NEXT:   [[VREG:%[0-9]+]]:_(s16) = G_TRUNC [[VREG1]](s32)
+  ; RV32I-NEXT:   PseudoRET
+
+  ; RV64I-LABEL: name: test_call_i16_noargs
+  ; RV64I: bb.1.entry:
+  ; RV64I-NEXT:   PseudoCALL target-flags(riscv-call) @i16_noargs, implicit-def $x1
+  ; RV64I-NEXT:   [[VREG1:%[0-9]+]]:_(s64) = COPY $x10
+  ; RV64I-NEXT:   [[VREG:%[0-9]+]]:_(s16) = G_TRUNC [[VREG1]](s64)
+  ; RV64I-NEXT:   PseudoRET
+entry:
+  %a = call i16 @i16_noargs()
+  ret void
+}
+
+declare i32 @i32_noargs()
+
+define void @test_call_i32_noargs() {
+  ; RV32I-LABEL: name: test_call_i32_noargs
+  ; RV32I:        PseudoCALL target-flags(riscv-call) @i32_noargs, implicit-def $x1
+  ; RV32I-NEXT:   [[VREG:%[0-9]+]]:_(s32) = COPY $x10
+  ; RV32I-NEXT:   PseudoRET
+
+  ; RV64I-LABEL: name: test_call_i32_noargs
+  ; RV64I: bb.1.entry:
+  ; RV64I-NEXT:   PseudoCALL target-flags(riscv-call) @i32_noargs, implicit-def $x1
+  ; RV64I-NEXT:   [[VREG1:%[0-9]+]]:_(s64) = COPY $x10
+  ; RV64I-NEXT:   [[VREG:%[0-9]+]]:_(s32) = G_TRUNC [[VREG1]](s64)
+  ; RV64I-NEXT:   PseudoRET
+entry:
+  %a = call i32 @i32_noargs()
+  ret void
+}
+
+declare i64 @i64_noargs()
+
+define void @test_call_i64_noargs() {
+  ; RV32I-LABEL: name: test_call_i64_noargs
+  ; RV32I: bb.1.entry:
+  ; RV32I-NEXT:   PseudoCALL target-flags(riscv-call) @i64_noargs, implicit-def $x1
+  ; RV32I-NEXT:   [[VREG1:%[0-9]+]]:_(s32) = COPY $x10
+  ; RV32I-NEXT:   [[VREG2:%[0-9]+]]:_(s32) = COPY $x11
+  ; RV32I-NEXT:   [[VREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[VREG1]](s32), [[VREG2]](s32)
+  ; RV32I-NEXT:   PseudoRET
+
+  ; RV64I-LABEL: name: test_call_i64_noargs
+  ; RV64I: bb.1.entry:
+  ; RV64I-NEXT:   PseudoCALL target-flags(riscv-call) @i64_noargs, implicit-def $x1
+  ; RV64I-NEXT:   [[VREG:%[0-9]+]]:_(s64) = COPY $x10
+  ; RV64I-NEXT:   PseudoRET
+entry:
+  %a = call i64 @i64_noargs()
+  ret void
+}
+
+declare i32* @i32_ptr_noargs()
+
+define void @test_call_i32_ptr_noargs() {
+entry:
+  ; RV32I-LABEL: name: test_call_i32_ptr_noargs
+  ; RV32I: bb.1.entry:
+  ; RV32I-NEXT:   PseudoCALL target-flags(riscv-call) @i32_ptr_noargs, implicit-def $x1
+  ; RV32I-NEXT:   [[VREG:%[0-9]+]]:_(p0) = COPY $x10
+  ; RV32I-NEXT:   PseudoRET
+
+  ; RV64I-LABEL: name: test_call_i32_ptr_noargs
+  ; RV64I: bb.1.entry:
+  ; RV64I-NEXT:   PseudoCALL target-flags(riscv-call) @i32_ptr_noargs, implicit-def $x1
+  ; RV64I-NEXT:   [[VREG:%[0-9]+]]:_(p0) = COPY $x10
+  ; RV64I-NEXT:   PseudoRET
+  %a = call i32* @i32_ptr_noargs()
+  ret void
+}