Index: X86ISelLowering.cpp
===================================================================
--- X86ISelLowering.cpp
+++ X86ISelLowering.cpp
@@ -15237,8 +15237,22 @@
       RHS = AndLHS.getOperand(1);
     }
 
-    // Use BT if the immediate can't be encoded in a TEST instruction.
-    if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
+    // choosing between BT and TEST for reg,imm
+    //               bit 0-7    bit 8-31     bit 32-63
+    // TEST reg,imm  24b        48b          N/A
+    // BT   reg,imm  32b        32b          40b
+    // TEST AL, AX, EAX and RAX use 8b less
+    // extended registers + bits 32-63 require the REX prefix
+    // for bits 32-63, there is no TESTQ and so BTQ is required
+    const Function *F = DAG.getMachineFunction().getFunction();
+    bool  OptForSize  = F->getAttributes().hasAttribute(
+            AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
+    bool  OptForCold  = F->getAttributes().hasAttribute(
+            AttributeSet::FunctionIndex, Attribute::Cold);
+
+    if (isPowerOf2_64(AndRHSVal) &&
+        (!isUInt<32>(AndRHSVal) ||
+        (!isUInt<16>(AndRHSVal) && (OptForSize | OptForCold)))) {
       LHS = AndLHS;
       RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
     }