diff --git a/llvm/include/llvm/MC/MCExpr.h b/llvm/include/llvm/MC/MCExpr.h --- a/llvm/include/llvm/MC/MCExpr.h +++ b/llvm/include/llvm/MC/MCExpr.h @@ -131,6 +131,7 @@ class MCConstantExpr : public MCExpr { int64_t Value; bool PrintInHex = false; + unsigned SizeInBytes = 0; explicit MCConstantExpr(int64_t Value) : MCExpr(MCExpr::Constant, SMLoc()), Value(Value) {} @@ -139,18 +140,24 @@ : MCExpr(MCExpr::Constant, SMLoc()), Value(Value), PrintInHex(PrintInHex) {} + MCConstantExpr(int64_t Value, bool PrintInHex, unsigned SizeInBytes) + : MCExpr(MCExpr::Constant, SMLoc()), Value(Value), PrintInHex(PrintInHex), + SizeInBytes(SizeInBytes) {} + public: /// \name Construction /// @{ static const MCConstantExpr *create(int64_t Value, MCContext &Ctx, - bool PrintInHex = false); + bool PrintInHex = false, + unsigned SizeInBytes = 0); /// @} /// \name Accessors /// @{ int64_t getValue() const { return Value; } + unsigned getSizeInBytes() const { return SizeInBytes; } bool useHexFormat() const { return PrintInHex; } diff --git a/llvm/include/llvm/MC/MCStreamer.h b/llvm/include/llvm/MC/MCStreamer.h --- a/llvm/include/llvm/MC/MCStreamer.h +++ b/llvm/include/llvm/MC/MCStreamer.h @@ -663,6 +663,13 @@ EmitIntValue(Value, Size); } + /// Special case of EmitValue that avoids the client having to pass + /// in a MCExpr for constant integers & prints in Hex format for certain + /// modes, pads the field with leading zeros to Size width + virtual void EmitIntValueInHexWithPadding(uint64_t Value, unsigned Size) { + EmitIntValue(Value, Size); + } + virtual void EmitULEB128Value(const MCExpr *Value); virtual void EmitSLEB128Value(const MCExpr *Value); diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp --- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp @@ -2563,17 +2563,17 @@ int Chunk = API.getNumWords() - 1; if (TrailingBytes) - AP.OutStreamer->EmitIntValue(p[Chunk--], TrailingBytes); + AP.OutStreamer->EmitIntValueInHexWithPadding(p[Chunk--], TrailingBytes); for (; Chunk >= 0; --Chunk) - AP.OutStreamer->EmitIntValue(p[Chunk], sizeof(uint64_t)); + AP.OutStreamer->EmitIntValueInHexWithPadding(p[Chunk], sizeof(uint64_t)); } else { unsigned Chunk; for (Chunk = 0; Chunk < NumBytes / sizeof(uint64_t); ++Chunk) - AP.OutStreamer->EmitIntValue(p[Chunk], sizeof(uint64_t)); + AP.OutStreamer->EmitIntValueInHexWithPadding(p[Chunk], sizeof(uint64_t)); if (TrailingBytes) - AP.OutStreamer->EmitIntValue(p[Chunk], TrailingBytes); + AP.OutStreamer->EmitIntValueInHexWithPadding(p[Chunk], TrailingBytes); } // Emit the tail padding for the long double. diff --git a/llvm/lib/MC/MCAsmStreamer.cpp b/llvm/lib/MC/MCAsmStreamer.cpp --- a/llvm/lib/MC/MCAsmStreamer.cpp +++ b/llvm/lib/MC/MCAsmStreamer.cpp @@ -196,6 +196,7 @@ SMLoc Loc = SMLoc()) override; void EmitIntValue(uint64_t Value, unsigned Size) override; void EmitIntValueInHex(uint64_t Value, unsigned Size) override; + void EmitIntValueInHexWithPadding(uint64_t Value, unsigned Size) override; void EmitULEB128Value(const MCExpr *Value) override; @@ -973,6 +974,11 @@ EmitValue(MCConstantExpr::create(Value, getContext(), true), Size); } +void MCAsmStreamer::EmitIntValueInHexWithPadding(uint64_t Value, + unsigned Size) { + EmitValue(MCConstantExpr::create(Value, getContext(), true, Size), Size); +} + void MCAsmStreamer::EmitValueImpl(const MCExpr *Value, unsigned Size, SMLoc Loc) { assert(Size <= 8 && "Invalid size"); diff --git a/llvm/lib/MC/MCExpr.cpp b/llvm/lib/MC/MCExpr.cpp --- a/llvm/lib/MC/MCExpr.cpp +++ b/llvm/lib/MC/MCExpr.cpp @@ -46,8 +46,25 @@ case MCExpr::Constant: { auto Value = cast(*this).getValue(); auto PrintInHex = cast(*this).useHexFormat(); + auto SizeInBytes = cast(*this).getSizeInBytes(); if (PrintInHex) - OS << "0x" << Twine::utohexstr(Value); + switch (SizeInBytes) { + default: + OS << "0x" << Twine::utohexstr(Value); + break; + case 1: + OS << format("0x%02" PRIx64, Value); + break; + case 2: + OS << format("0x%04" PRIx64, Value); + break; + case 4: + OS << format("0x%08" PRIx64, Value); + break; + case 8: + OS << format("0x%016" PRIx64, Value); + break; + } else OS << Value; return; @@ -167,8 +184,9 @@ } const MCConstantExpr *MCConstantExpr::create(int64_t Value, MCContext &Ctx, - bool PrintInHex) { - return new (Ctx) MCConstantExpr(Value, PrintInHex); + bool PrintInHex, + unsigned SizeInBytes) { + return new (Ctx) MCConstantExpr(Value, PrintInHex, SizeInBytes); } /* *** */ diff --git a/llvm/test/CodeGen/AArch64/arm64-fp-imm-size.ll b/llvm/test/CodeGen/AArch64/arm64-fp-imm-size.ll --- a/llvm/test/CodeGen/AArch64/arm64-fp-imm-size.ll +++ b/llvm/test/CodeGen/AArch64/arm64-fp-imm-size.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -mtriple=arm64-apple-darwin | FileCheck %s ; CHECK: literal8 -; CHECK: .quad 4614256656552045848 +; CHECK: .quad 0x400921fb54442d18 define double @foo() optsize { ; CHECK: _foo: ; CHECK: adrp x[[REG:[0-9]+]], lCPI0_0@PAGE @@ -11,7 +11,7 @@ } ; CHECK: literal8 -; CHECK: .quad 137438953409 +; CHECK: .quad 0x0000001fffffffc define double @foo2() optsize { ; CHECK: _foo2: ; CHECK: adrp x[[REG:[0-9]+]], lCPI1_0@PAGE diff --git a/llvm/test/CodeGen/AArch64/arm64-fp-imm.ll b/llvm/test/CodeGen/AArch64/arm64-fp-imm.ll --- a/llvm/test/CodeGen/AArch64/arm64-fp-imm.ll +++ b/llvm/test/CodeGen/AArch64/arm64-fp-imm.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -mtriple=arm64-apple-darwin | FileCheck %s ; CHECK: literal8 -; CHECK: .quad 4614256656552045848 +; CHECK: .quad 0x400921fb54442d18 define double @foo() { ; CHECK: _foo: ; CHECK: adrp x[[REG:[0-9]+]], lCPI0_0@PAGE diff --git a/llvm/test/CodeGen/AArch64/f16-imm.ll b/llvm/test/CodeGen/AArch64/f16-imm.ll --- a/llvm/test/CodeGen/AArch64/f16-imm.ll +++ b/llvm/test/CodeGen/AArch64/f16-imm.ll @@ -23,7 +23,7 @@ ; CHECK-DAG-NEXT: ret ; CHECK-NOFP16: .[[LBL1:LCPI1_[0-9]]]: -; CHECK-NOFP16-NEXT: .hword 15360 // half 1 +; CHECK-NOFP16-NEXT: .hword 0x3c00 // half 1 ; CHECK-NOFP16-LABEL: Const1: ; CHECK-NOFP16: adrp x[[NUM:[0-9]+]], .[[LBL1]] ; CHECK-NOFP16-NEXT: ldr h0, [x[[NUM]], :lo12:.[[LBL1]]] @@ -37,7 +37,7 @@ ; CHECK-DAG-NEXT: ret ; CHECK-NOFP16: .[[LBL2:LCPI2_[0-9]]]: -; CHECK-NOFP16-NEXT: .hword 12288 // half 0.125 +; CHECK-NOFP16-NEXT: .hword 0x3000 // half 0.125 ; CHECK-NOFP16-LABEL: Const2: ; CHECK-NOFP16: adrp x[[NUM:[0-9]+]], .[[LBL2]] ; CHECK-NOFP16-NEXT: ldr h0, [x[[NUM]], :lo12:.[[LBL2]]] @@ -51,7 +51,7 @@ ; CHECK-DAG-NEXT: ret ; CHECK-NOFP16: .[[LBL3:LCPI3_[0-9]]]: -; CHECK-NOFP16-NEXT: .hword 20352 // half 30 +; CHECK-NOFP16-NEXT: .hword 0x4f80 // half 30 ; CHECK-NOFP16-LABEL: Const3: ; CHECK-NOFP16: adrp x[[NUM:[0-9]+]], .[[LBL3]] ; CHECK-NOFP16-NEXT: ldr h0, [x[[NUM]], :lo12:.[[LBL3]]] @@ -66,7 +66,7 @@ ; CHECK-DAG-NEXT: ret ; CHECK-NOFP16: .[[LBL4:LCPI4_[0-9]]]: -; CHECK-NOFP16-NEXT: .hword 20416 // half 31 +; CHECK-NOFP16-NEXT: .hword 0x4fc0 // half 31 ; CHECK-NOFP16-LABEL: Const4: ; CHECK-NOFP16: adrp x[[NUM:[0-9]+]], .[[LBL4]] ; CHECK-NOFP16-NEXT: ldr h0, [x[[NUM]], :lo12:.[[LBL4]]] @@ -76,7 +76,7 @@ ret half 0xH2FF0 } ; CHECK-ILLEGAL: .[[LBL5:LCPI5_[0-9]]]: -; CHECK-ILLEGAL-NEXT: .hword 12272 // half 0.12402 +; CHECK-ILLEGAL-NEXT: .hword 0x2ff0 // half 0.12402 ; CHECK-ILLEGAL-LABEL: Const5: ; CHECK-ILLEGAL: adrp x[[NUM:[0-9]+]], .[[LBL5]] ; CHECK-ILLEGAL-NEXT: ldr h0, [x[[NUM]], :lo12:.[[LBL5]]] @@ -86,7 +86,7 @@ ret half 0xH4FC1 } ; CHECK-ILLEGAL: .[[LBL6:LCPI6_[0-9]]]: -; CHECK-ILLEGAL-NEXT: .hword 20417 // half 31.016 +; CHECK-ILLEGAL-NEXT: .hword 0x4fc1 // half 31.016 ; CHECK-ILLEGAL-LABEL: Const6: ; CHECK-ILLEGAL: adrp x[[NUM:[0-9]+]], .[[LBL6]] ; CHECK-ILLEGAL-NEXT: ldr h0, [x[[NUM]], :lo12:.[[LBL6]]] @@ -97,7 +97,7 @@ ret half 0xH5000 } ; CHECK-ILLEGAL: .[[LBL7:LCPI7_[0-9]]]: -; CHECK-ILLEGAL-NEXT: .hword 20480 // half 32 +; CHECK-ILLEGAL-NEXT: .hword 0x5000 // half 32 ; CHECK-ILLEGAL-LABEL: Const7: ; CHECK-ILLEGAL: adrp x[[NUM:[0-9]+]], .[[LBL7]] ; CHECK-ILLEGAL-NEXT: ldr h0, [x[[NUM]], :lo12:.[[LBL7]]] diff --git a/llvm/test/CodeGen/AArch64/win_cst_pool.ll b/llvm/test/CodeGen/AArch64/win_cst_pool.ll --- a/llvm/test/CodeGen/AArch64/win_cst_pool.ll +++ b/llvm/test/CodeGen/AArch64/win_cst_pool.ll @@ -8,7 +8,7 @@ ; CHECK-NEXT: .section .rdata,"dr",discard,__real@2000000000800001 ; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: __real@2000000000800001: -; CHECK-NEXT: .xword 2305843009222082561 +; CHECK-NEXT: .xword 0x2000000000800001 ; CHECK: double: ; CHECK: adrp x8, __real@2000000000800001 ; CHECK-NEXT: ldr d0, [x8, __real@2000000000800001] @@ -17,7 +17,7 @@ ; MINGW: .section .rdata,"dr" ; MINGW-NEXT: .p2align 3 ; MINGW-NEXT: [[LABEL:\.LC.*]]: -; MINGW-NEXT: .xword 2305843009222082561 +; MINGW-NEXT: .xword 0x2000000000800001 ; MINGW: double: ; MINGW: adrp x8, [[LABEL]] ; MINGW-NEXT: ldr d0, [x8, [[LABEL]]] diff --git a/llvm/test/CodeGen/ARM/big-endian-neon-fp16-bitconv.ll b/llvm/test/CodeGen/ARM/big-endian-neon-fp16-bitconv.ll --- a/llvm/test/CodeGen/ARM/big-endian-neon-fp16-bitconv.ll +++ b/llvm/test/CodeGen/ARM/big-endian-neon-fp16-bitconv.ll @@ -56,8 +56,8 @@ ; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI2_0: -; CHECK-NEXT: .long 3212836864 @ float -1 -; CHECK-NEXT: .long 1065353216 @ float 1 +; CHECK-NEXT: .long 0xbf800000 @ float -1 +; CHECK-NEXT: .long 0x3f800000 @ float 1 entry: %c = fadd <2 x float> %a, %v = bitcast <2 x float> %c to <4 x half> @@ -208,10 +208,10 @@ ; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI8_0: -; CHECK-NEXT: .long 3212836864 @ float -1 -; CHECK-NEXT: .long 1065353216 @ float 1 -; CHECK-NEXT: .long 3212836864 @ float -1 -; CHECK-NEXT: .long 1065353216 @ float 1 +; CHECK-NEXT: .long 0xbf800000 @ float -1 +; CHECK-NEXT: .long 0x3f800000 @ float 1 +; CHECK-NEXT: .long 0xbf800000 @ float -1 +; CHECK-NEXT: .long 0x3f800000 @ float 1 entry: %c = fadd <4 x float> %a, %v = bitcast <4 x float> %c to <8 x half> @@ -325,10 +325,10 @@ ; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI12_0: -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 entry: %z = fadd <4 x half> %a, %y = bitcast <4 x half> %z to i64 @@ -352,10 +352,10 @@ ; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI13_0: -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 entry: %z = fadd <4 x half> %a, %y = bitcast <4 x half> %z to double @@ -381,10 +381,10 @@ ; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI14_0: -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 ; CHECK-NEXT: .LCPI14_1: ; CHECK-NEXT: .long 4294967295 @ 0xffffffff ; CHECK-NEXT: .long 1 @ 0x1 @@ -413,13 +413,13 @@ ; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI15_0: -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 ; CHECK-NEXT: .LCPI15_1: -; CHECK-NEXT: .long 3212836864 @ float -1 -; CHECK-NEXT: .long 1065353216 @ float 1 +; CHECK-NEXT: .long 0xbf800000 @ float -1 +; CHECK-NEXT: .long 0x3f800000 @ float 1 entry: %z = fadd <4 x half> %a, %y = bitcast <4 x half> %z to <2 x float> @@ -444,10 +444,10 @@ ; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI16_0: -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 ; CHECK-NEXT: .LCPI16_1: ; CHECK-NEXT: .short 65535 @ 0xffff ; CHECK-NEXT: .short 1 @ 0x1 @@ -477,10 +477,10 @@ ; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI17_0: -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 entry: %z = fadd <4 x half> %a, %y = bitcast <4 x half> %z to <8 x i8> @@ -513,14 +513,14 @@ ; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI18_0: -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 entry: %z = fadd <8 x half> %a, %y = bitcast <8 x half> %z to i128 @@ -547,14 +547,14 @@ ; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI19_0: -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 entry: %z = fadd <8 x half> %a, %y = bitcast <8 x half> %z to <2 x double> @@ -582,14 +582,14 @@ ; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI20_0: -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 ; CHECK-NEXT: .LCPI20_1: ; CHECK-NEXT: .long 4294967295 @ 0xffffffff ; CHECK-NEXT: .long 1 @ 0x1 @@ -622,19 +622,19 @@ ; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI21_0: -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 ; CHECK-NEXT: .LCPI21_1: -; CHECK-NEXT: .long 3212836864 @ float -1 -; CHECK-NEXT: .long 1065353216 @ float 1 -; CHECK-NEXT: .long 3212836864 @ float -1 -; CHECK-NEXT: .long 1065353216 @ float 1 +; CHECK-NEXT: .long 0xbf800000 @ float -1 +; CHECK-NEXT: .long 0x3f800000 @ float 1 +; CHECK-NEXT: .long 0xbf800000 @ float -1 +; CHECK-NEXT: .long 0x3f800000 @ float 1 entry: %z = fadd <8 x half> %a, %y = bitcast <8 x half> %z to <4 x float> @@ -661,14 +661,14 @@ ; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI22_0: -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 ; CHECK-NEXT: .LCPI22_1: ; CHECK-NEXT: .short 65535 @ 0xffff ; CHECK-NEXT: .short 1 @ 0x1 @@ -703,14 +703,14 @@ ; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI23_0: -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 -; CHECK-NEXT: .short 48128 @ half -1 -; CHECK-NEXT: .short 15360 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 +; CHECK-NEXT: .short 0xbc00 @ half -1 +; CHECK-NEXT: .short 0x3c00 @ half 1 entry: %z = fadd <8 x half> %a, %y = bitcast <8 x half> %z to <16 x i8> diff --git a/llvm/test/CodeGen/ARM/constant-islands.ll b/llvm/test/CodeGen/ARM/constant-islands.ll --- a/llvm/test/CodeGen/ARM/constant-islands.ll +++ b/llvm/test/CodeGen/ARM/constant-islands.ll @@ -6,7 +6,7 @@ ; CHECK: b .LBB ; CHECK-NOT: b .LBB ; CHECK: [[CONST]]: -; CHECK-NEXT: .long 1150963712 +; CHECK-NEXT: .long 0x449a5000 %tst = fcmp oeq float %in, 1234.5 diff --git a/llvm/test/CodeGen/ARM/constantfp.ll b/llvm/test/CodeGen/ARM/constantfp.ll --- a/llvm/test/CodeGen/ARM/constantfp.ll +++ b/llvm/test/CodeGen/ARM/constantfp.ll @@ -198,8 +198,8 @@ ; CHECK-NO-XO: vldr {{s[0-9]+}}, {{[[]}}[[REG]]{{[]]}} ; CHECK-NO-XO-NOT: .rodata ; CHECK-NO-XO: [[LABEL]]: -; CHECK-NO-XO: .long 1335165689 -; CHECK-NO-XO: .long 1307470632 +; CHECK-NO-XO: .long 0x4f9502f9 +; CHECK-NO-XO: .long 0x4dee6b28 ; CHECK-XO-FLOAT-LABEL: lower_fpconst_select ; CHECK-XO-FLOAT: movw [[REG:r[0-9]+]], :lower16:[[LABEL:.?LCP[0-9]+_[0-9]+]] @@ -208,8 +208,8 @@ ; CHECK-XO-FLOAT: .rodata ; CHECK-XO-FLOAT-NOT: .text ; CHECK-XO-FLOAT: [[LABEL]]: -; CHECK-XO-FLOAT: .long 1335165689 -; CHECK-XO-FLOAT: .long 1307470632 +; CHECK-XO-FLOAT: .long 0x4f9502f9 +; CHECK-XO-FLOAT: .long 0x4dee6b28 ; CHECK-XO-ROPI-LABEL: lower_fpconst_select ; CHECK-XO-ROPI: movw [[REG:r[0-9]+]], :lower16:([[LABEL1:.?LCP[0-9]+_[0-9]+]]-([[LABEL2:.?LPC[0-9]+_[0-9]+]]+4)) @@ -219,8 +219,8 @@ ; CHECK-XO-ROPI: .rodata ; CHECK-XO-ROPI-NOT: .text ; CHECK-XO-ROPI: [[LABEL1]]: -; CHECK-XO-ROPI: .long 1335165689 -; CHECK-XO-ROPI: .long 1307470632 +; CHECK-XO-ROPI: .long 0x4f9502f9 +; CHECK-XO-ROPI: .long 0x4dee6b28 %cmp = fcmp nnan oeq float %f, 0.000000e+00 %sel = select i1 %cmp, float 5.000000e+08, float 5.000000e+09 diff --git a/llvm/test/CodeGen/ARM/vecreduce-fadd-legalization-strict.ll b/llvm/test/CodeGen/ARM/vecreduce-fadd-legalization-strict.ll --- a/llvm/test/CodeGen/ARM/vecreduce-fadd-legalization-strict.ll +++ b/llvm/test/CodeGen/ARM/vecreduce-fadd-legalization-strict.ll @@ -26,7 +26,7 @@ ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI0_0: -; CHECK-NEXT: .long 0 @ float 0 +; CHECK-NEXT: .long 0x00000000 @ float 0 %b = call half @llvm.experimental.vector.reduce.v2.fadd.f16.v1f16(half 0.0, <1 x half> %a) ret half %b } @@ -42,7 +42,7 @@ ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI1_0: -; CHECK-NEXT: .long 0 @ float 0 +; CHECK-NEXT: .long 0x00000000 @ float 0 %b = call float @llvm.experimental.vector.reduce.v2.fadd.f32.v1f32(float 0.0, <1 x float> %a) ret float %b } @@ -93,7 +93,7 @@ ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI4_0: -; CHECK-NEXT: .long 0 @ float 0 +; CHECK-NEXT: .long 0x00000000 @ float 0 %b = call float @llvm.experimental.vector.reduce.v2.fadd.f32.v3f32(float 0.0, <3 x float> %a) ret float %b } @@ -160,7 +160,7 @@ ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI6_0: -; CHECK-NEXT: .long 0 @ float 0 +; CHECK-NEXT: .long 0x00000000 @ float 0 %b = call float @llvm.experimental.vector.reduce.v2.fadd.f32.v16f32(float 0.0, <16 x float> %a) ret float %b } diff --git a/llvm/test/CodeGen/ARM/vecreduce-fmul-legalization-strict.ll b/llvm/test/CodeGen/ARM/vecreduce-fmul-legalization-strict.ll --- a/llvm/test/CodeGen/ARM/vecreduce-fmul-legalization-strict.ll +++ b/llvm/test/CodeGen/ARM/vecreduce-fmul-legalization-strict.ll @@ -26,7 +26,7 @@ ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI0_0: -; CHECK-NEXT: .long 0 @ float 0 +; CHECK-NEXT: .long 0x00000000 @ float 0 %b = call half @llvm.experimental.vector.reduce.v2.fmul.f16.v1f16(half 0.0, <1 x half> %a) ret half %b } @@ -42,7 +42,7 @@ ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI1_0: -; CHECK-NEXT: .long 0 @ float 0 +; CHECK-NEXT: .long 0x00000000 @ float 0 %b = call float @llvm.experimental.vector.reduce.v2.fmul.f32.v1f32(float 0.0, <1 x float> %a) ret float %b } @@ -93,7 +93,7 @@ ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI4_0: -; CHECK-NEXT: .long 0 @ float 0 +; CHECK-NEXT: .long 0x00000000 @ float 0 %b = call float @llvm.experimental.vector.reduce.v2.fmul.f32.v3f32(float 0.0, <3 x float> %a) ret float %b } @@ -160,7 +160,7 @@ ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI6_0: -; CHECK-NEXT: .long 0 @ float 0 +; CHECK-NEXT: .long 0x00000000 @ float 0 %b = call float @llvm.experimental.vector.reduce.v2.fmul.f32.v16f32(float 0.0, <16 x float> %a) ret float %b } diff --git a/llvm/test/CodeGen/Mips/cconv/memory-layout.ll b/llvm/test/CodeGen/Mips/cconv/memory-layout.ll --- a/llvm/test/CodeGen/Mips/cconv/memory-layout.ll +++ b/llvm/test/CodeGen/Mips/cconv/memory-layout.ll @@ -44,7 +44,7 @@ ; ALL: .p2align 2 ; ALL-LABEL: float: -; ALL: .4byte 1065353216 +; ALL: .4byte 0x3f800000 ; ALL: .size float, 4 ; ALL: .p2align 3 @@ -54,7 +54,7 @@ ; ALL: .p2align 3 ; ALL-LABEL: double: -; ALL: .8byte 4607182418800017408 +; ALL: .8byte 0x3ff0000000000000 ; ALL: .size double, 8 ; O32: .p2align 2 @@ -95,8 +95,8 @@ ; ALL: .p2align 2 ; ALL-LABEL: float_array: -; ALL: .4byte 1065353216 -; ALL: .4byte 1073741824 +; ALL: .4byte 0x3f800000 +; ALL: .4byte 0x40000000 ; ALL: .size float_array, 8 ; ALL: .p2align 3 @@ -107,8 +107,8 @@ ; ALL: .p2align 3 ; ALL-LABEL: double_array: -; ALL: .8byte 4607182418800017408 -; ALL: .8byte 4611686018427387904 +; ALL: .8byte 0x3ff0000000000000 +; ALL: .8byte 0x4000000000000000 ; ALL: .size double_array, 16 ; O32: .p2align 2 @@ -132,7 +132,7 @@ ; ALL-LABEL: mixed: ; ALL: .byte 1 ; ALL: .space 7 -; ALL: .8byte 4607182418800017408 +; ALL: .8byte 0x3ff0000000000000 ; ALL: .2byte 515 ; ALL: .space 6 ; ALL: .size mixed, 24 diff --git a/llvm/test/CodeGen/PowerPC/aix-lower-constant-pool-index.ll b/llvm/test/CodeGen/PowerPC/aix-lower-constant-pool-index.ll --- a/llvm/test/CodeGen/PowerPC/aix-lower-constant-pool-index.ll +++ b/llvm/test/CodeGen/PowerPC/aix-lower-constant-pool-index.ll @@ -48,7 +48,7 @@ ; 32SMALL-ASM: .csect .rodata[RO] ; 32SMALL-ASM: .align 2 ; 32SMALL-ASM: .LCPI0_0: -; 32SMALL-ASM: .long 1085276160 +; 32SMALL-ASM: .long 0x40b00000 ; 32SMALL-ASM: .test_float: ; 32SMALL-ASM: lwz [[REG1:[0-9]+]], LC0(2) ; 32SMALL-ASM: lfs 1, 0([[REG1]]) @@ -57,7 +57,7 @@ ; 32LARGE-ASM: .csect .rodata[RO] ; 32LARGE-ASM: .align 2 ; 32LARGE-ASM: .LCPI0_0: -; 32LARGE-ASM: .long 1085276160 +; 32LARGE-ASM: .long 0x40b00000 ; 32LARGE-ASM: .test_float: ; 32LARGE-ASM: addis [[REG1:[0-9]+]], LC0@u(2) ; 32LARGE-ASM: lwz [[REG2:[0-9]+]], LC0@l([[REG1]]) @@ -67,7 +67,7 @@ ; 64SMALL-ASM: .csect .rodata[RO] ; 64SMALL-ASM: .align 2 ; 64SMALL-ASM: .LCPI0_0: -; 64SMALL-ASM: .long 1085276160 +; 64SMALL-ASM: .long 0x40b00000 ; 64SMALL-ASM: .test_float: ; 64SMALL-ASM: ld [[REG1:[0-9]+]], LC0(2) ; 64SMALL-ASM: lfs 1, 0([[REG1]]) @@ -76,7 +76,7 @@ ; 64LARGE-ASM: .csect .rodata[RO] ; 64LARGE-ASM: .align 2 ; 64LARGE-ASM: .LCPI0_0: -; 64LARGE-ASM: .long 1085276160 +; 64LARGE-ASM: .long 0x40b00000 ; 64LARGE-ASM: .test_float: ; 64LARGE-ASM: addis [[REG1:[0-9]+]], LC0@u(2) ; 64LARGE-ASM: ld [[REG2:[0-9]+]], LC0@l([[REG1]]) diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll @@ -60,17 +60,17 @@ ; CHECK: .globl fvar ; CHECK-NEXT: .align 2 ; CHECK-NEXT: fvar: -; CHECK-NEXT: .long 1145569280 +; CHECK-NEXT: .long 0x44480000 ; CHECK: .globl dvar ; CHECK-NEXT: .align 3 ; CHECK-NEXT: dvar: -; CHECK-NEXT: .llong 4651127699538968576 +; CHECK-NEXT: .llong 0x408c200000000000 ; CHECK: .globl over_aligned ; CHECK-NEXT: .align 5 ; CHECK-NEXT: over_aligned: -; CHECK-NEXT: .llong 4651127699538968576 +; CHECK-NEXT: .llong 0x408c200000000000 ; CHECK: .globl chrarray ; CHECK-NEXT: chrarray: @@ -82,10 +82,10 @@ ; CHECK: .globl dblarr ; CHECK-NEXT: .align 3 ; CHECK-NEXT: dblarr: -; CHECK-NEXT: .llong 4607182418800017408 -; CHECK-NEXT: .llong 4611686018427387904 -; CHECK-NEXT: .llong 4613937818241073152 -; CHECK-NEXT: .llong 4616189618054758400 +; CHECK-NEXT: .llong 0x3ff0000000000000 +; CHECK-NEXT: .llong 0x4000000000000000 +; CHECK-NEXT: .llong 0x4008000000000000 +; CHECK-NEXT: .llong 0x4010000000000000 ; CHECK: .globl d_0 ; CHECK-NEXT: .align 3 diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-rodata.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-rodata.ll --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-rodata.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-rodata.ll @@ -36,15 +36,15 @@ ; CHECK-NEXT: .globl const_fvar ; CHECK-NEXT: .align 2 ; CHECK-NEXT: const_fvar: -; CHECK-NEXT: .long 1145569280 +; CHECK-NEXT: .long 0x44480000 ; CHECK-NEXT: .globl const_dvar ; CHECK-NEXT: .align 3 ; CHECK-NEXT: const_dvar: -; CHECK-NEXT: .llong 4651127699538968576 +; CHECK-NEXT: .llong 0x408c200000000000 ; CHECK-NEXT: .globl const_over_aligned ; CHECK-NEXT: .align 5 ; CHECK-NEXT: const_over_aligned: -; CHECK-NEXT: .llong 4651127699538968576 +; CHECK-NEXT: .llong 0x408c200000000000 ; CHECK-NEXT: .globl const_chrarray ; CHECK-NEXT: const_chrarray: ; CHECK-NEXT: .byte 97 @@ -54,10 +54,10 @@ ; CHECK-NEXT: .globl const_dblarr ; CHECK-NEXT: .align 3 ; CHECK-NEXT: const_dblarr: -; CHECK-NEXT: .llong 4607182418800017408 -; CHECK-NEXT: .llong 4611686018427387904 -; CHECK-NEXT: .llong 4613937818241073152 -; CHECK-NEXT: .llong 4616189618054758400 +; CHECK-NEXT: .llong 0x3ff0000000000000 +; CHECK-NEXT: .llong 0x4000000000000000 +; CHECK-NEXT: .llong 0x4008000000000000 +; CHECK-NEXT: .llong 0x4010000000000000 ; OBJ: File: {{.*}}aix-xcoff-rodata.ll.tmp.o diff --git a/llvm/test/CodeGen/PowerPC/float-asmprint.ll b/llvm/test/CodeGen/PowerPC/float-asmprint.ll --- a/llvm/test/CodeGen/PowerPC/float-asmprint.ll +++ b/llvm/test/CodeGen/PowerPC/float-asmprint.ll @@ -11,24 +11,24 @@ @var16 = global half -0.0, align 2 ; CHECK: var128: -; CHECK-NEXT: .quad -9223372036854775808 # fp128 -0 +; CHECK-NEXT: .quad 0x8000000000000000 # fp128 -0 ; CHECK-NEXT: .quad 0 ; CHECK-NEXT: .size ; CHECK: varppc128: -; CHECK-NEXT: .quad -9223372036854775808 # ppc_fp128 -0 +; CHECK-NEXT: .quad 0x8000000000000000 # ppc_fp128 -0 ; CHECK-NEXT: .quad 0 ; CHECK-NEXT: .size ; CHECK: var64: -; CHECK-NEXT: .quad -9223372036854775808 # double -0 +; CHECK-NEXT: .quad 0x8000000000000000 # double -0 ; CHECK-NEXT: .size ; CHECK: var32: -; CHECK-NEXT: .long 2147483648 # float -0 +; CHECK-NEXT: .long 0x80000000 # float -0 ; CHECK-NEXT: .size ; CHECK: var16: -; CHECK-NEXT: .short 32768 # half -0 +; CHECK-NEXT: .short 0x8000 # half -0 ; CHECK-NEXT: .size diff --git a/llvm/test/CodeGen/PowerPC/mcm-12.ll b/llvm/test/CodeGen/PowerPC/mcm-12.ll --- a/llvm/test/CodeGen/PowerPC/mcm-12.ll +++ b/llvm/test/CodeGen/PowerPC/mcm-12.ll @@ -17,19 +17,19 @@ } ; CHECK: [[VAR:[a-z0-9A-Z_.]+]]: -; CHECK: .quad 4562098671269285104 +; CHECK: .quad 0x3f4fd4920b498cf0 ; CHECK-LABEL: test_double_const: ; CHECK: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha ; CHECK: lfd {{[0-9]+}}, [[VAR]]@toc@l([[REG1]]) ; CHECK-VSX: [[VAR:[a-z0-9A-Z_.]+]]: -; CHECK-VSX: .quad 4562098671269285104 +; CHECK-VSX: .quad 0x3f4fd4920b498cf0 ; CHECK-VSX-LABEL: test_double_const: ; CHECK-VSX: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha ; CHECK-VSX: lfd {{[0-9]+}}, [[VAR]]@toc@l({{[0-9]+}}) ; CHECK-P9: [[VAR:[a-z0-9A-Z_.]+]]: -; CHECK-P9: .quad 4562098671269285104 +; CHECK-P9: .quad 0x3f4fd4920b498cf0 ; CHECK-P9-LABEL: test_double_const: ; CHECK-P9: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha ; CHECK-P9: lfd {{[0-9]+}}, [[VAR]]@toc@l([[REG1]]) diff --git a/llvm/test/CodeGen/PowerPC/mcm-4.ll b/llvm/test/CodeGen/PowerPC/mcm-4.ll --- a/llvm/test/CodeGen/PowerPC/mcm-4.ll +++ b/llvm/test/CodeGen/PowerPC/mcm-4.ll @@ -23,41 +23,41 @@ } ; MEDIUM: [[VAR:[a-z0-9A-Z_.]+]]: -; MEDIUM: .quad 4562098671269285104 +; MEDIUM: .quad 0x3f4fd4920b498cf0 ; MEDIUM-LABEL: test_double_const: ; MEDIUM: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha ; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l ; MEDIUM: lfd {{[0-9]+}}, 0([[REG2]]) ; MEDIUM-VSX: [[VAR:[a-z0-9A-Z_.]+]]: -; MEDIUM-VSX: .quad 4562098671269285104 +; MEDIUM-VSX: .quad 0x3f4fd4920b498cf0 ; MEDIUM-VSX-LABEL: test_double_const: ; MEDIUM-VSX: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha ; MEDIUM-VSX: lfd {{[0-9]+}}, [[VAR]]@toc@l([[REG1]]) ; LARGE: [[VAR:[a-z0-9A-Z_.]+]]: -; LARGE: .quad 4562098671269285104 +; LARGE: .quad 0x3f4fd4920b498cf0 ; LARGE-LABEL: test_double_const: ; LARGE: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha ; LARGE: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]]) ; LARGE: lfd {{[0-9]+}}, 0([[REG2]]) ; LARGE-VSX: [[VAR:[a-z0-9A-Z_.]+]]: -; LARGE-VSX: .quad 4562098671269285104 +; LARGE-VSX: .quad 0x3f4fd4920b498cf0 ; LARGE-VSX-LABEL: test_double_const: ; LARGE-VSX: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha ; LARGE-VSX: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]]) ; LARGE-VSX: lfdx {{[0-9]+}}, 0, [[REG2]] ; MEDIUM-P9: [[VAR:[a-z0-9A-Z_.]+]]: -; MEDIUM-P9: .quad 4562098671269285104 +; MEDIUM-P9: .quad 0x3f4fd4920b498cf0 ; MEDIUM-P9-LABEL: test_double_const: ; MEDIUM-P9: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha ; MEDIUM-P9: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l ; MEDIUM-P9: lfd {{[0-9]+}}, 0([[REG2]]) ; LARGE-P9: [[VAR:[a-z0-9A-Z_.]+]]: -; LARGE-P9: .quad 4562098671269285104 +; LARGE-P9: .quad 0x3f4fd4920b498cf0 ; LARGE-P9-LABEL: test_double_const: ; LARGE-P9: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha ; LARGE-P9: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]]) diff --git a/llvm/test/CodeGen/PowerPC/ppcf128-endian.ll b/llvm/test/CodeGen/PowerPC/ppcf128-endian.ll --- a/llvm/test/CodeGen/PowerPC/ppcf128-endian.ll +++ b/llvm/test/CodeGen/PowerPC/ppcf128-endian.ll @@ -39,7 +39,7 @@ ret void } ; CHECK: .LCPI[[LC:[0-9]+]]_0: -; CHECK: .long 1065353216 +; CHECK: .long 0x3f800000 ; CHECK: .LCPI[[LC]]_1: ; CHECK: .long 0 ; CHECK: @caller_const diff --git a/llvm/test/CodeGen/PowerPC/pr16573.ll b/llvm/test/CodeGen/PowerPC/pr16573.ll --- a/llvm/test/CodeGen/PowerPC/pr16573.ll +++ b/llvm/test/CodeGen/PowerPC/pr16573.ll @@ -7,5 +7,5 @@ ret double %1 } -; CHECK: .quad -9111018957755033591 +; CHECK: .quad 0x818f2887b9295809 diff --git a/llvm/test/CodeGen/SystemZ/fp-const-03.ll b/llvm/test/CodeGen/SystemZ/fp-const-03.ll --- a/llvm/test/CodeGen/SystemZ/fp-const-03.ll +++ b/llvm/test/CodeGen/SystemZ/fp-const-03.ll @@ -9,6 +9,6 @@ ; CHECK: le %f0, 0([[REGISTER]]) ; CHECK: br %r14 ; -; CONST: .long 1065353217 +; CONST: .long 0x3f800001 ret float 0x3ff0000020000000 } diff --git a/llvm/test/CodeGen/SystemZ/fp-const-04.ll b/llvm/test/CodeGen/SystemZ/fp-const-04.ll --- a/llvm/test/CodeGen/SystemZ/fp-const-04.ll +++ b/llvm/test/CodeGen/SystemZ/fp-const-04.ll @@ -10,6 +10,6 @@ ; CHECK: ldeb %f0, 0([[REGISTER]]) ; CHECK: br %r14 ; -; CONST: .long 1065353217 +; CONST: .long 0x3f800001 ret double 0x3ff0000020000000 } diff --git a/llvm/test/CodeGen/SystemZ/fp-const-05.ll b/llvm/test/CodeGen/SystemZ/fp-const-05.ll --- a/llvm/test/CodeGen/SystemZ/fp-const-05.ll +++ b/llvm/test/CodeGen/SystemZ/fp-const-05.ll @@ -12,7 +12,7 @@ ; CHECK: std %f2, 8(%r2) ; CHECK: br %r14 ; -; CONST: .long 1065353217 +; CONST: .long 0x3f800001 store fp128 0xL00000000000000003fff000002000000, fp128 *%x ret void } diff --git a/llvm/test/CodeGen/SystemZ/fp-const-06.ll b/llvm/test/CodeGen/SystemZ/fp-const-06.ll --- a/llvm/test/CodeGen/SystemZ/fp-const-06.ll +++ b/llvm/test/CodeGen/SystemZ/fp-const-06.ll @@ -9,6 +9,6 @@ ; CHECK: ld %f0, 0([[REGISTER]]) ; CHECK: br %r14 ; -; CONST: .quad 4607182419068452864 +; CONST: .quad 0x3ff0000010000000 ret double 0x3ff0000010000000 } diff --git a/llvm/test/CodeGen/SystemZ/fp-const-07.ll b/llvm/test/CodeGen/SystemZ/fp-const-07.ll --- a/llvm/test/CodeGen/SystemZ/fp-const-07.ll +++ b/llvm/test/CodeGen/SystemZ/fp-const-07.ll @@ -12,7 +12,7 @@ ; CHECK: std %f2, 8(%r2) ; CHECK: br %r14 ; -; CONST: .quad 4607182419068452864 +; CONST: .quad 0x3ff0000010000000 store fp128 0xL00000000000000003fff000001000000, fp128 *%x ret void } diff --git a/llvm/test/CodeGen/SystemZ/fp-const-08.ll b/llvm/test/CodeGen/SystemZ/fp-const-08.ll --- a/llvm/test/CodeGen/SystemZ/fp-const-08.ll +++ b/llvm/test/CodeGen/SystemZ/fp-const-08.ll @@ -14,8 +14,8 @@ ; CHECK: std %f2, 8(%r2) ; CHECK: br %r14 ; -; CONST: .quad 4611404543450677248 -; CONST: .quad 576460752303423488 +; CONST: .quad 0x3fff000000000000 +; CONST: .quad 0x0800000000000000 store fp128 0xL08000000000000003fff000000000000, fp128 *%x ret void } diff --git a/llvm/test/CodeGen/SystemZ/fp-const-09.ll b/llvm/test/CodeGen/SystemZ/fp-const-09.ll --- a/llvm/test/CodeGen/SystemZ/fp-const-09.ll +++ b/llvm/test/CodeGen/SystemZ/fp-const-09.ll @@ -13,8 +13,8 @@ ; CHECK: std %f2, 8(%r2) ; CHECK: br %r14 ; -; CONST: .quad 4611404543450677248 -; CONST: .quad 1 +; CONST: .quad 0x3fff000000000000 +; CONST: .quad 0x0000000000000001 store fp128 0xL00000000000000013fff000000000000, fp128 *%x ret void } diff --git a/llvm/test/CodeGen/SystemZ/fp-const-10.ll b/llvm/test/CodeGen/SystemZ/fp-const-10.ll --- a/llvm/test/CodeGen/SystemZ/fp-const-10.ll +++ b/llvm/test/CodeGen/SystemZ/fp-const-10.ll @@ -6,7 +6,7 @@ ; converstion to QNaN. define double @f1() { ; CHECK-LABEL: .LCPI0_0 -; CHECK: .quad 9219994337134247936 +; CHECK: .quad 0x7ff4000000000000 ; CHECK-LABEL: f1: ; CHECK: larl %r1, .LCPI0_0 ; CHECK-NOT: ldeb %f0, 0(%r1) diff --git a/llvm/test/CodeGen/SystemZ/fp-const-11.ll b/llvm/test/CodeGen/SystemZ/fp-const-11.ll --- a/llvm/test/CodeGen/SystemZ/fp-const-11.ll +++ b/llvm/test/CodeGen/SystemZ/fp-const-11.ll @@ -33,8 +33,8 @@ ; CHECK: vl [[REG:%v[0-9]+]], 0([[REGISTER]]) ; CHECK: vst [[REG]], 0(%r2) ; CHECK: br %r14 -; CONST: .quad 4611404543484231680 -; CONST: .quad 0 +; CONST: .quad 0x3fff000002000000 +; CONST: .quad 0x0 store fp128 0xL00000000000000003fff000002000000, fp128 *%x ret void } diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll @@ -255,7 +255,7 @@ ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.5: ; CHECK-NEXT: .LCPI1_0: -; CHECK-NEXT: .long 0 @ float 0 +; CHECK-NEXT: .long 0x00000000 @ float 0 entry: %cmp8 = icmp eq i32 %N, 0 br i1 %cmp8, label %for.cond.cleanup, label %vector.ph @@ -532,7 +532,7 @@ ; CHECK-NEXT: .long 2 @ 0x2 ; CHECK-NEXT: .long 3 @ 0x3 ; CHECK-NEXT: .LCPI2_0: -; CHECK-NEXT: .long 0 @ float 0 +; CHECK-NEXT: .long 0x00000000 @ float 0 entry: %cmp8 = icmp eq i32 %N, 0 br i1 %cmp8, label %for.cond.cleanup, label %vector.ph diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll @@ -1535,7 +1535,7 @@ ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.10: ; CHECK-NEXT: .LCPI9_0: -; CHECK-NEXT: .long 0 @ float 0 +; CHECK-NEXT: .long 0x00000000 @ float 0 entry: %cmp8 = icmp eq i32 %N, 0 br i1 %cmp8, label %for.cond.cleanup, label %for.body.preheader @@ -1692,7 +1692,7 @@ ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.10: ; CHECK-NEXT: .LCPI10_0: -; CHECK-NEXT: .long 0 @ float 0 +; CHECK-NEXT: .long 0x00000000 @ float 0 entry: %cmp9 = icmp eq i32 %N, 0 br i1 %cmp9, label %for.cond.cleanup, label %for.body.preheader @@ -1858,7 +1858,7 @@ ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.10: ; CHECK-NEXT: .LCPI11_0: -; CHECK-NEXT: .long 0 @ float 0 +; CHECK-NEXT: .long 0x00000000 @ float 0 entry: %cmp10 = icmp eq i32 %N, 0 br i1 %cmp10, label %for.cond.cleanup, label %for.body.preheader diff --git a/llvm/test/CodeGen/Thumb2/aligned-constants.ll b/llvm/test/CodeGen/Thumb2/aligned-constants.ll --- a/llvm/test/CodeGen/Thumb2/aligned-constants.ll +++ b/llvm/test/CodeGen/Thumb2/aligned-constants.ll @@ -13,7 +13,7 @@ ; CHECK: .long 2370821947 ; CHECK: .long 1080815255 ; CHECK: LCPI -; CHECK: .long 1123477881 +; CHECK: .long 0x42f6e979 define void @func(float* nocapture %x, double* nocapture %y) nounwind ssp { entry: %0 = load float, float* %x, align 4 diff --git a/llvm/test/CodeGen/Thumb2/constant-islands-new-island-padding.ll b/llvm/test/CodeGen/Thumb2/constant-islands-new-island-padding.ll --- a/llvm/test/CodeGen/Thumb2/constant-islands-new-island-padding.ll +++ b/llvm/test/CodeGen/Thumb2/constant-islands-new-island-padding.ll @@ -10,7 +10,7 @@ ; Check that the constant island pass moves the float constant pool entry inside ; the function. -; CHECK: .long 1067320814 @ float 1.23455596 +; CHECK: .long 0x3f9e05ee @ float 1.23455596 ; CHECK: {{.*}} %do.end define i32 @testpadding(i32 %a) { diff --git a/llvm/test/CodeGen/Thumb2/mve-ctlz.ll b/llvm/test/CodeGen/Thumb2/mve-ctlz.ll --- a/llvm/test/CodeGen/Thumb2/mve-ctlz.ll +++ b/llvm/test/CodeGen/Thumb2/mve-ctlz.ll @@ -31,7 +31,7 @@ ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI0_0: -; CHECK-NEXT: .long 0 @ float 0 +; CHECK-NEXT: .long 0x00000000 @ float 0 entry: %0 = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %src, i1 0) ret <2 x i64> %0 @@ -97,7 +97,7 @@ ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI4_0: -; CHECK-NEXT: .long 0 @ float 0 +; CHECK-NEXT: .long 0x00000000 @ float 0 entry: %0 = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %src, i1 1) ret <2 x i64> %0 diff --git a/llvm/test/CodeGen/Thumb2/mve-ctpop.ll b/llvm/test/CodeGen/Thumb2/mve-ctpop.ll --- a/llvm/test/CodeGen/Thumb2/mve-ctpop.ll +++ b/llvm/test/CodeGen/Thumb2/mve-ctpop.ll @@ -58,7 +58,7 @@ ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI0_0: -; CHECK-NEXT: .long 0 @ float 0 +; CHECK-NEXT: .long 0x00000000 @ float 0 entry: %0 = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %src) ret <2 x i64> %0 diff --git a/llvm/test/CodeGen/Thumb2/mve-cttz.ll b/llvm/test/CodeGen/Thumb2/mve-cttz.ll --- a/llvm/test/CodeGen/Thumb2/mve-cttz.ll +++ b/llvm/test/CodeGen/Thumb2/mve-cttz.ll @@ -35,7 +35,7 @@ ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI0_0: -; CHECK-NEXT: .long 0 @ float 0 +; CHECK-NEXT: .long 0x00000000 @ float 0 entry: %0 = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %src, i1 0) ret <2 x i64> %0 @@ -111,7 +111,7 @@ ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI4_0: -; CHECK-NEXT: .long 0 @ float 0 +; CHECK-NEXT: .long 0x00000000 @ float 0 entry: %0 = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %src, i1 1) ret <2 x i64> %0 diff --git a/llvm/test/CodeGen/Thumb2/mve-phireg.ll b/llvm/test/CodeGen/Thumb2/mve-phireg.ll --- a/llvm/test/CodeGen/Thumb2/mve-phireg.ll +++ b/llvm/test/CodeGen/Thumb2/mve-phireg.ll @@ -227,9 +227,9 @@ ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.2: ; CHECK-NEXT: .LCPI1_0: -; CHECK-NEXT: .long 4 @ float 5.60519386E-45 +; CHECK-NEXT: .long 0x00000004 @ float 5.60519386E-45 ; CHECK-NEXT: .LCPI1_1: -; CHECK-NEXT: .long 0 @ float 0 +; CHECK-NEXT: .long 0x00000000 @ float 0 entry: %f = alloca i16, align 2 %g = alloca [3 x [8 x [4 x i16*]]], align 4 diff --git a/llvm/test/CodeGen/Thumb2/mve-pred-build-var.ll b/llvm/test/CodeGen/Thumb2/mve-pred-build-var.ll --- a/llvm/test/CodeGen/Thumb2/mve-pred-build-var.ll +++ b/llvm/test/CodeGen/Thumb2/mve-pred-build-var.ll @@ -191,7 +191,7 @@ ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI9_0: -; CHECK-NEXT: .long 0 @ float 0 +; CHECK-NEXT: .long 0x00000000 @ float 0 entry: %c = icmp ult i32 %s, %t %vc = insertelement <2 x i1> zeroinitializer, i1 %c, i64 0 @@ -217,7 +217,7 @@ ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI10_0: -; CHECK-NEXT: .long 0 @ float 0 +; CHECK-NEXT: .long 0x00000000 @ float 0 entry: %c = icmp ult i32 %s, %t %vc = insertelement <2 x i1> zeroinitializer, i1 %c, i64 1 diff --git a/llvm/test/CodeGen/Thumb2/mve-vecreduce-fadd.ll b/llvm/test/CodeGen/Thumb2/mve-vecreduce-fadd.ll --- a/llvm/test/CodeGen/Thumb2/mve-vecreduce-fadd.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vecreduce-fadd.ll @@ -14,7 +14,7 @@ ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI0_0: -; CHECK-NEXT: .long 0 @ float 0 +; CHECK-NEXT: .long 0x00000000 @ float 0 entry: %z = call fast float @llvm.experimental.vector.reduce.v2.fadd.f32.v2f32(float %y, <2 x float> %x) ret float %z @@ -79,7 +79,7 @@ ; CHECK-NEXT: .p2align 1 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI3_0: -; CHECK-NEXT: .short 0 @ half 0 +; CHECK-NEXT: .short 0x0000 @ half 0 entry: %y = load half, half* %yy %z = call fast half @llvm.experimental.vector.reduce.v2.fadd.f16.v4f16(half %y, <4 x half> %x) diff --git a/llvm/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll b/llvm/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll --- a/llvm/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll +++ b/llvm/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll @@ -14,7 +14,7 @@ ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI0_0: -; CHECK-NEXT: .long 2139095040 @ float +Inf +; CHECK-NEXT: .long 0x7f800000 @ float +Inf entry: %z = call fast float @llvm.experimental.vector.reduce.fmin.v2f32(<2 x float> %x) ret float %z @@ -83,7 +83,7 @@ ; CHECK-NEXT: .p2align 1 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI3_0: -; CHECK-NEXT: .short 31744 @ half +Inf +; CHECK-NEXT: .short 0x7c00 @ half +Inf entry: %z = call fast half @llvm.experimental.vector.reduce.fmin.v4f16(<4 x half> %x) ret half %z @@ -522,7 +522,7 @@ ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI18_0: -; CHECK-NEXT: .long 2139095040 @ float +Inf +; CHECK-NEXT: .long 0x7f800000 @ float +Inf entry: %z = call fast float @llvm.experimental.vector.reduce.fmin.v2f32(<2 x float> %x) %c = fcmp fast olt float %y, %z @@ -601,7 +601,7 @@ ; CHECK-NEXT: .p2align 1 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI21_0: -; CHECK-NEXT: .short 31744 @ half +Inf +; CHECK-NEXT: .short 0x7c00 @ half +Inf entry: %y = load half, half* %yy %z = call fast half @llvm.experimental.vector.reduce.fmin.v4f16(<4 x half> %x) @@ -1136,7 +1136,7 @@ ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI36_0: -; CHECK-NEXT: .long 4286578688 @ float -Inf +; CHECK-NEXT: .long 0xff800000 @ float -Inf entry: %z = call fast float @llvm.experimental.vector.reduce.fmax.v2f32(<2 x float> %x) ret float %z @@ -1204,7 +1204,7 @@ ; CHECK-NEXT: .p2align 1 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI39_0: -; CHECK-NEXT: .short 64512 @ half -Inf +; CHECK-NEXT: .short 0xfc00 @ half -Inf entry: %z = call fast half @llvm.experimental.vector.reduce.fmax.v4f16(<4 x half> %x) ret half %z @@ -1641,7 +1641,7 @@ ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI54_0: -; CHECK-NEXT: .long 4286578688 @ float -Inf +; CHECK-NEXT: .long 0xff800000 @ float -Inf entry: %z = call fast float @llvm.experimental.vector.reduce.fmax.v2f32(<2 x float> %x) %c = fcmp fast ogt float %y, %z @@ -1720,7 +1720,7 @@ ; CHECK-NEXT: .p2align 1 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI57_0: -; CHECK-NEXT: .short 64512 @ half -Inf +; CHECK-NEXT: .short 0xfc00 @ half -Inf entry: %y = load half, half* %yy %z = call fast half @llvm.experimental.vector.reduce.fmax.v4f16(<4 x half> %x) diff --git a/llvm/test/CodeGen/WebAssembly/global.ll b/llvm/test/CodeGen/WebAssembly/global.ll --- a/llvm/test/CodeGen/WebAssembly/global.ll +++ b/llvm/test/CodeGen/WebAssembly/global.ll @@ -121,28 +121,28 @@ ; CHECK: .type f32nil,@object ; CHECK: .p2align 2{{$}} ; CHECK-NEXT: f32nil: -; CHECK-NEXT: .int32 0{{$}} +; CHECK-NEXT: .int32 0x00000000{{$}} ; CHECK-NEXT: .size f32nil, 4{{$}} @f32nil = internal global float zeroinitializer ; CHECK: .type f32z,@object ; CHECK: .p2align 2{{$}} ; CHECK-NEXT: f32z: -; CHECK-NEXT: .int32 0{{$}} +; CHECK-NEXT: .int32 0x00000000{{$}} ; CHECK-NEXT: .size f32z, 4{{$}} @f32z = internal global float 0.0 ; CHECK: .type f32nz,@object ; CHECK: .p2align 2{{$}} ; CHECK: f32nz: -; CHECK: .int32 2147483648{{$}} +; CHECK: .int32 0x80000000{{$}} ; CHECK: .size f32nz, 4{{$}} @f32nz = internal global float -0.0 ; CHECK: .type f32two,@object ; CHECK: .p2align 2{{$}} ; CHECK-NEXT: f32two: -; CHECK-NEXT: .int32 1073741824{{$}} +; CHECK-NEXT: .int32 0x40000000{{$}} ; CHECK-NEXT: .size f32two, 4{{$}} @f32two = internal global float 2.0 @@ -156,28 +156,28 @@ ; CHECK: .type f64nil,@object ; CHECK: .p2align 3{{$}} ; CHECK-NEXT: f64nil: -; CHECK-NEXT: .int64 0{{$}} +; CHECK-NEXT: .int64 0x0000000000000000{{$}} ; CHECK-NEXT: .size f64nil, 8{{$}} @f64nil = internal global double zeroinitializer ; CHECK: .type f64z,@object ; CHECK: .p2align 3{{$}} ; CHECK-NEXT: f64z: -; CHECK-NEXT: .int64 0{{$}} +; CHECK-NEXT: .int64 0x0000000000000000{{$}} ; CHECK-NEXT: .size f64z, 8{{$}} @f64z = internal global double 0.0 ; CHECK: .type f64nz,@object ; CHECK: .p2align 3{{$}} ; CHECK-NEXT: f64nz: -; CHECK-NEXT: .int64 -9223372036854775808{{$}} +; CHECK-NEXT: .int64 0x8000000000000000{{$}} ; CHECK-NEXT: .size f64nz, 8{{$}} @f64nz = internal global double -0.0 ; CHECK: .type f64two,@object ; CHECK: .p2align 3{{$}} ; CHECK-NEXT: f64two: -; CHECK-NEXT: .int64 4611686018427387904{{$}} +; CHECK-NEXT: .int64 0x4000000000000000{{$}} ; CHECK-NEXT: .size f64two, 8{{$}} @f64two = internal global double 2.0 diff --git a/llvm/test/CodeGen/X86/broadcast-elm-cross-splat-vec.ll b/llvm/test/CodeGen/X86/broadcast-elm-cross-splat-vec.ll --- a/llvm/test/CodeGen/X86/broadcast-elm-cross-splat-vec.ll +++ b/llvm/test/CodeGen/X86/broadcast-elm-cross-splat-vec.ll @@ -1956,10 +1956,10 @@ ; AVX512: .LCPI37 -; AVX512-NEXT: .quad 4616189618054758400 # double 4 -; AVX512-NEXT: .quad 4607182418800017408 # double 1 -; AVX512-NEXT: .quad 4611686018427387904 # double 2 -; AVX512-NEXT: .quad 4613937818241073152 # double 3 +; AVX512-NEXT: .quad 0x4010000000000000 # double 4 +; AVX512-NEXT: .quad 0x3ff0000000000000 # double 1 +; AVX512-NEXT: .quad 0x4000000000000000 # double 2 +; AVX512-NEXT: .quad 0x4008000000000000 # double 3 ; AVX512-NOT: .quad define <8 x double> @f8xf64_f256(<8 x double> %a) { diff --git a/llvm/test/CodeGen/X86/copysign-constant-magnitude.ll b/llvm/test/CodeGen/X86/copysign-constant-magnitude.ll --- a/llvm/test/CodeGen/X86/copysign-constant-magnitude.ll +++ b/llvm/test/CodeGen/X86/copysign-constant-magnitude.ll @@ -7,8 +7,8 @@ ; the constant load values because those are important. ; CHECK: [[SIGNMASK1:L.+]]: -; CHECK-NEXT: .quad -9223372036854775808 ## double -0 -; CHECK-NEXT: .quad -9223372036854775808 ## double -0 +; CHECK-NEXT: .quad 0x8000000000000000 ## double -0 +; CHECK-NEXT: .quad 0x8000000000000000 ## double -0 define double @mag_pos0_double(double %x) nounwind { ; CHECK-LABEL: mag_pos0_double: @@ -20,7 +20,7 @@ } ; CHECK: [[SIGNMASK2:L.+]]: -; CHECK-NEXT: .quad -9223372036854775808 ## double -0 +; CHECK-NEXT: .quad 0x8000000000000000 ## double -0 define double @mag_neg0_double(double %x) nounwind { ; CHECK-LABEL: mag_neg0_double: @@ -33,10 +33,10 @@ } ; CHECK: [[SIGNMASK3:L.+]]: -; CHECK-NEXT: .quad -9223372036854775808 ## double -0 -; CHECK-NEXT: .quad -9223372036854775808 ## double -0 +; CHECK-NEXT: .quad 0x8000000000000000 ## double -0 +; CHECK-NEXT: .quad 0x8000000000000000 ## double -0 ; CHECK: [[ONE3:L.+]]: -; CHECK-NEXT: .quad 4607182418800017408 ## double 1 +; CHECK-NEXT: .quad 0x3ff0000000000000 ## double 1 define double @mag_pos1_double(double %x) nounwind { ; CHECK-LABEL: mag_pos1_double: @@ -50,11 +50,11 @@ } ; CHECK: [[SIGNMASK4:L.+]]: -; CHECK-NEXT: .quad -9223372036854775808 ## double -0 -; CHECK-NEXT: .quad -9223372036854775808 ## double -0 +; CHECK-NEXT: .quad 0x8000000000000000 ## double -0 +; CHECK-NEXT: .quad 0x8000000000000000 ## double -0 ; CHECK: [[ONE4:L.+]]: -; CHECK-NEXT: .quad 4607182418800017408 ## double 1 -; CHECK-NEXT: .quad 4607182418800017408 ## double 1 +; CHECK-NEXT: .quad 0x3ff0000000000000 ## double 1 +; CHECK-NEXT: .quad 0x3ff0000000000000 ## double 1 define double @mag_neg1_double(double %x) nounwind { ; CHECK-LABEL: mag_neg1_double: @@ -67,10 +67,10 @@ } ; CHECK: [[SIGNMASK5:L.+]]: -; CHECK-NEXT: .long 2147483648 ## float -0 -; CHECK-NEXT: .long 2147483648 ## float -0 -; CHECK-NEXT: .long 2147483648 ## float -0 -; CHECK-NEXT: .long 2147483648 ## float -0 +; CHECK-NEXT: .long 0x80000000 ## float -0 +; CHECK-NEXT: .long 0x80000000 ## float -0 +; CHECK-NEXT: .long 0x80000000 ## float -0 +; CHECK-NEXT: .long 0x80000000 ## float -0 define float @mag_pos0_float(float %x) nounwind { ; CHECK-LABEL: mag_pos0_float: @@ -82,7 +82,7 @@ } ; CHECK: [[SIGNMASK6:L.+]]: -; CHECK-NEXT: .long 2147483648 ## float -0 +; CHECK-NEXT: .long 0x80000000 ## float -0 define float @mag_neg0_float(float %x) nounwind { ; CHECK-LABEL: mag_neg0_float: @@ -95,12 +95,12 @@ } ; CHECK: [[SIGNMASK7:L.+]]: -; CHECK-NEXT: .long 2147483648 ## float -0 -; CHECK-NEXT: .long 2147483648 ## float -0 -; CHECK-NEXT: .long 2147483648 ## float -0 -; CHECK-NEXT: .long 2147483648 ## float -0 +; CHECK-NEXT: .long 0x80000000 ## float -0 +; CHECK-NEXT: .long 0x80000000 ## float -0 +; CHECK-NEXT: .long 0x80000000 ## float -0 +; CHECK-NEXT: .long 0x80000000 ## float -0 ; CHECK: [[ONE7:L.+]]: -; CHECK-NEXT: .long 1065353216 ## float 1 +; CHECK-NEXT: .long 0x3f800000 ## float 1 define float @mag_pos1_float(float %x) nounwind { ; CHECK-LABEL: mag_pos1_float: @@ -114,15 +114,15 @@ } ; CHECK: [[SIGNMASK8:L.+]]: -; CHECK-NEXT: .long 2147483648 ## float -0 -; CHECK-NEXT: .long 2147483648 ## float -0 -; CHECK-NEXT: .long 2147483648 ## float -0 -; CHECK-NEXT: .long 2147483648 ## float -0 +; CHECK-NEXT: .long 0x80000000 ## float -0 +; CHECK-NEXT: .long 0x80000000 ## float -0 +; CHECK-NEXT: .long 0x80000000 ## float -0 +; CHECK-NEXT: .long 0x80000000 ## float -0 ; CHECK: [[ONE8:L.+]]: -; CHECK-NEXT: .long 1065353216 ## float 1 -; CHECK-NEXT: .long 1065353216 ## float 1 -; CHECK-NEXT: .long 1065353216 ## float 1 -; CHECK-NEXT: .long 1065353216 ## float 1 +; CHECK-NEXT: .long 0x3f800000 ## float 1 +; CHECK-NEXT: .long 0x3f800000 ## float 1 +; CHECK-NEXT: .long 0x3f800000 ## float 1 +; CHECK-NEXT: .long 0x3f800000 ## float 1 define float @mag_neg1_float(float %x) nounwind { ; CHECK-LABEL: mag_neg1_float: diff --git a/llvm/test/CodeGen/X86/float-asmprint.ll b/llvm/test/CodeGen/X86/float-asmprint.ll --- a/llvm/test/CodeGen/X86/float-asmprint.ll +++ b/llvm/test/CodeGen/X86/float-asmprint.ll @@ -13,44 +13,44 @@ @var4f16 = global <4 x half> ; CHECK: var128: -; CHECK-NEXT: .quad 0 # fp128 -0 -; CHECK-NEXT: .quad -9223372036854775808 +; CHECK-NEXT: .quad 0x0000000000000000 # fp128 -0 +; CHECK-NEXT: .quad 0x8000000000000000 ; CHECK-NEXT: .size ; CHECK: varppc128: ; For ppc_fp128, the high double always comes first. -; CHECK-NEXT: .quad -9223372036854775808 # ppc_fp128 -0 -; CHECK-NEXT: .quad 0 +; CHECK-NEXT: .quad 0x8000000000000000 # ppc_fp128 -0 +; CHECK-NEXT: .quad 0x0000000000000000 ; CHECK-NEXT: .size ; CHECK: var80: -; CHECK-NEXT: .quad 0 # x86_fp80 -0 -; CHECK-NEXT: .short 32768 +; CHECK-NEXT: .quad 0x0000000000000000 # x86_fp80 -0 +; CHECK-NEXT: .short 0x8000 ; CHECK-NEXT: .zero 6 ; CHECK-NEXT: .size ; CHECK: var64: -; CHECK-NEXT: .quad -9223372036854775808 # double -0 +; CHECK-NEXT: .quad 0x8000000000000000 # double -0 ; CHECK-NEXT: .size ; CHECK: var32: -; CHECK-NEXT: .long 2147483648 # float -0 +; CHECK-NEXT: .long 0x80000000 # float -0 ; CHECK-NEXT: .size ; CHECK: var16: -; CHECK-NEXT: .short 32768 # half -0 +; CHECK-NEXT: .short 0x8000 # half -0 ; CHECK-NEXT: .size ; CHECK: var4f32: -; CHECK-NEXT: .long 2147483648 # float -0 -; CHECK-NEXT: .long 0 # float 0 -; CHECK-NEXT: .long 1065353216 # float 1 -; CHECK-NEXT: .long 1073741824 # float 2 +; CHECK-NEXT: .long 0x80000000 # float -0 +; CHECK-NEXT: .long 0x00000000 # float 0 +; CHECK-NEXT: .long 0x3f800000 # float 1 +; CHECK-NEXT: .long 0x40000000 # float 2 ; CHECK-NEXT: .size ; CHECK: var4f16: -; CHECK-NEXT: .short 32768 # half -0 -; CHECK-NEXT: .short 0 # half 0 -; CHECK-NEXT: .short 15360 # half 1 -; CHECK-NEXT: .short 16384 # half 2 +; CHECK-NEXT: .short 0x8000 # half -0 +; CHECK-NEXT: .short 0x0000 # half 0 +; CHECK-NEXT: .short 0x3c00 # half 1 +; CHECK-NEXT: .short 0x4000 # half 2 ; CHECK-NEXT: .size diff --git a/llvm/test/CodeGen/X86/fp-immediate-shorten.ll b/llvm/test/CodeGen/X86/fp-immediate-shorten.ll --- a/llvm/test/CodeGen/X86/fp-immediate-shorten.ll +++ b/llvm/test/CodeGen/X86/fp-immediate-shorten.ll @@ -2,7 +2,7 @@ ; RUN: llc < %s -mtriple=i686-- -mattr=-sse2,-sse3 | FileCheck %s -; CHECK: {{.long.1123418112}} +; CHECK: {{.long.0x42f60000}} define double @D() { ret double 1.230000e+02 diff --git a/llvm/test/CodeGen/X86/fp128-load.ll b/llvm/test/CodeGen/X86/fp128-load.ll --- a/llvm/test/CodeGen/X86/fp128-load.ll +++ b/llvm/test/CodeGen/X86/fp128-load.ll @@ -32,6 +32,6 @@ } ; CHECK-LABEL: my_fp128: -; CHECK-NEXT: .quad 0 -; CHECK-NEXT: .quad 4611404543450677248 +; CHECK-NEXT: .quad 0x0 +; CHECK-NEXT: .quad 0x3fff000000000000 ; CHECK-NEXT: .size my_fp128, 16 diff --git a/llvm/test/CodeGen/X86/pr13577.ll b/llvm/test/CodeGen/X86/pr13577.ll --- a/llvm/test/CodeGen/X86/pr13577.ll +++ b/llvm/test/CodeGen/X86/pr13577.ll @@ -2,9 +2,9 @@ ; RUN: llc < %s -mtriple=x86_64-darwin | FileCheck %s ; CHECK-LABEL: LCPI0_0: -; CHECK-NEXT: .long 4286578688 +; CHECK-NEXT: .long 0xff800000 ; CHECK-LABEL: LCPI0_1: -; CHECK-NEXT: .long 2139095040 +; CHECK-NEXT: .long 0x7f800000 define x86_fp80 @foo(x86_fp80 %a) { ; CHECK-LABEL: foo: diff --git a/llvm/test/CodeGen/X86/pr40730.ll b/llvm/test/CodeGen/X86/pr40730.ll --- a/llvm/test/CodeGen/X86/pr40730.ll +++ b/llvm/test/CodeGen/X86/pr40730.ll @@ -17,10 +17,10 @@ } ; CHECK: .LCPI1_0: -; CHECK-NEXT: .quad 60129542157 -; CHECK-NEXT: .quad 60129542157 -; CHECK-NEXT: .quad 68719476736 -; CHECK-NEXT: .quad 60129542157 +; CHECK-NEXT: .quad 0x0000000e0000000d +; CHECK-NEXT: .quad 0x0000000e0000000d +; CHECK-NEXT: .quad 0x0000001000000000 +; CHECK-NEXT: .quad 0x0000000e0000000d define <8 x i32> @shuffle_v8i32_0dcd3f14_constant(<8 x i32> %a0) { ; CHECK-LABEL: shuffle_v8i32_0dcd3f14_constant: diff --git a/llvm/test/CodeGen/X86/vec-copysign.ll b/llvm/test/CodeGen/X86/vec-copysign.ll --- a/llvm/test/CodeGen/X86/vec-copysign.ll +++ b/llvm/test/CodeGen/X86/vec-copysign.ll @@ -5,16 +5,16 @@ ; Use a macosx triple to make sure the format of those constant strings is exact. ; CHECK: [[SIGNMASK1:L.+]]: -; CHECK-NEXT: .long 2147483648 -; CHECK-NEXT: .long 2147483648 -; CHECK-NEXT: .long 2147483648 -; CHECK-NEXT: .long 2147483648 +; CHECK-NEXT: .long 0x80000000 +; CHECK-NEXT: .long 0x80000000 +; CHECK-NEXT: .long 0x80000000 +; CHECK-NEXT: .long 0x80000000 ; CHECK: [[MAGMASK1:L.+]]: -; CHECK-NEXT: .long 2147483647 -; CHECK-NEXT: .long 2147483647 -; CHECK-NEXT: .long 2147483647 -; CHECK-NEXT: .long 2147483647 +; CHECK-NEXT: .long 0x7fffffff +; CHECK-NEXT: .long 0x7fffffff +; CHECK-NEXT: .long 0x7fffffff +; CHECK-NEXT: .long 0x7fffffff define <4 x float> @v4f32(<4 x float> %a, <4 x float> %b) nounwind { ; SSE2-LABEL: v4f32: @@ -36,30 +36,30 @@ } ; SSE2: [[MAGMASK2:L.+]]: -; SSE2-NEXT: .long 2147483647 -; SSE2-NEXT: .long 2147483647 -; SSE2-NEXT: .long 2147483647 -; SSE2-NEXT: .long 2147483647 +; SSE2-NEXT: .long 0x7fffffff +; SSE2-NEXT: .long 0x7fffffff +; SSE2-NEXT: .long 0x7fffffff +; SSE2-NEXT: .long 0x7fffffff ; AVX: [[SIGNMASK2:L.+]]: -; AVX-NEXT: .long 2147483648 -; AVX-NEXT: .long 2147483648 -; AVX-NEXT: .long 2147483648 -; AVX-NEXT: .long 2147483648 -; AVX-NEXT: .long 2147483648 -; AVX-NEXT: .long 2147483648 -; AVX-NEXT: .long 2147483648 -; AVX-NEXT: .long 2147483648 +; AVX-NEXT: .long 0x80000000 +; AVX-NEXT: .long 0x80000000 +; AVX-NEXT: .long 0x80000000 +; AVX-NEXT: .long 0x80000000 +; AVX-NEXT: .long 0x80000000 +; AVX-NEXT: .long 0x80000000 +; AVX-NEXT: .long 0x80000000 +; AVX-NEXT: .long 0x80000000 ; AVX: [[MAGMASK2:L.+]]: -; AVX-NEXT: .long 2147483647 -; AVX-NEXT: .long 2147483647 -; AVX-NEXT: .long 2147483647 -; AVX-NEXT: .long 2147483647 -; AVX-NEXT: .long 2147483647 -; AVX-NEXT: .long 2147483647 -; AVX-NEXT: .long 2147483647 -; AVX-NEXT: .long 2147483647 +; AVX-NEXT: .long 0x7fffffff +; AVX-NEXT: .long 0x7fffffff +; AVX-NEXT: .long 0x7fffffff +; AVX-NEXT: .long 0x7fffffff +; AVX-NEXT: .long 0x7fffffff +; AVX-NEXT: .long 0x7fffffff +; AVX-NEXT: .long 0x7fffffff +; AVX-NEXT: .long 0x7fffffff define <8 x float> @v8f32(<8 x float> %a, <8 x float> %b) nounwind { ; SSE2-LABEL: v8f32: @@ -86,12 +86,12 @@ } ; CHECK: [[SIGNMASK3:L.+]]: -; CHECK-NEXT: .quad -9223372036854775808 -; CHECK-NEXT: .quad -9223372036854775808 +; CHECK-NEXT: .quad 0x8000000000000000 +; CHECK-NEXT: .quad 0x8000000000000000 ; CHECK: [[MAGMASK3:L.+]]: -; CHECK-NEXT: .quad 9223372036854775807 -; CHECK-NEXT: .quad 9223372036854775807 +; CHECK-NEXT: .quad 0x7fffffffffffffff +; CHECK-NEXT: .quad 0x7fffffffffffffff define <2 x double> @v2f64(<2 x double> %a, <2 x double> %b) nounwind { ; SSE2-LABEL: v2f64: @@ -113,20 +113,20 @@ } ; SSE2: [[MAGMASK4:L.+]]: -; SSE2-NEXT: .quad 9223372036854775807 -; SSE2-NEXT: .quad 9223372036854775807 +; SSE2-NEXT: .quad 0x7fffffffffffffff +; SSE2-NEXT: .quad 0x7fffffffffffffff ; AVX: [[SIGNMASK4:L.+]]: -; AVX-NEXT: .quad -9223372036854775808 -; AVX-NEXT: .quad -9223372036854775808 -; AVX-NEXT: .quad -9223372036854775808 -; AVX-NEXT: .quad -9223372036854775808 +; AVX-NEXT: .quad 0x8000000000000000 +; AVX-NEXT: .quad 0x8000000000000000 +; AVX-NEXT: .quad 0x8000000000000000 +; AVX-NEXT: .quad 0x8000000000000000 ; AVX: [[MAGMASK4:L.+]]: -; AVX-NEXT: .quad 9223372036854775807 -; AVX-NEXT: .quad 9223372036854775807 -; AVX-NEXT: .quad 9223372036854775807 -; AVX-NEXT: .quad 9223372036854775807 +; AVX-NEXT: .quad 0x7fffffffffffffff +; AVX-NEXT: .quad 0x7fffffffffffffff +; AVX-NEXT: .quad 0x7fffffffffffffff +; AVX-NEXT: .quad 0x7fffffffffffffff define <4 x double> @v4f64(<4 x double> %a, <4 x double> %b) nounwind { ; SSE2-LABEL: v4f64: diff --git a/llvm/test/CodeGen/X86/vec_uint_to_fp-fastmath.ll b/llvm/test/CodeGen/X86/vec_uint_to_fp-fastmath.ll --- a/llvm/test/CodeGen/X86/vec_uint_to_fp-fastmath.ll +++ b/llvm/test/CodeGen/X86/vec_uint_to_fp-fastmath.ll @@ -31,10 +31,10 @@ ; CST-NEXT: .long 1392508928 # 0x53000000 ; CST: [[MAGICCSTADDR:.LCPI[0-9_]+]]: -; CST-NEXT: .long 1392509056 # float 5.49764202E+11 -; CST-NEXT: .long 1392509056 # float 5.49764202E+11 -; CST-NEXT: .long 1392509056 # float 5.49764202E+11 -; CST-NEXT: .long 1392509056 # float 5.49764202E+11 +; CST-NEXT: .long 0x53000080 # float 5.49764202E+11 +; CST-NEXT: .long 0x53000080 # float 5.49764202E+11 +; CST-NEXT: .long 0x53000080 # float 5.49764202E+11 +; CST-NEXT: .long 0x53000080 # float 5.49764202E+11 ; AVX2: [[LOWCSTADDR:.LCPI[0-9_]+]]: ; AVX2-NEXT: .long 1258291200 # 0x4b000000 @@ -43,7 +43,7 @@ ; AVX2-NEXT: .long 1392508928 # 0x53000000 ; AVX2: [[MAGICCSTADDR:.LCPI[0-9_]+]]: -; AVX2-NEXT: .long 1392509056 # float 5.49764202E+11 +; AVX2-NEXT: .long 0x53000080 # float 5.49764202E+11 define <4 x float> @test_uitofp_v4i32_to_v4f32(<4 x i32> %arg) { ; SSE2-LABEL: test_uitofp_v4i32_to_v4f32: @@ -114,7 +114,7 @@ ; AVX2-NEXT: .long 1392508928 # 0x53000000 ; AVX2: [[MAGICCSTADDR:.LCPI[0-9_]+]]: -; AVX2-NEXT: .long 1392509056 # float 5.49764202E+11 +; AVX2-NEXT: .long 0x53000080 # float 5.49764202E+11 define <8 x float> @test_uitofp_v8i32_to_v8f32(<8 x i32> %arg) { ; Legalization will break the thing is 2 x <4 x i32> on anthing prior AVX. diff --git a/llvm/test/CodeGen/X86/vec_uint_to_fp.ll b/llvm/test/CodeGen/X86/vec_uint_to_fp.ll --- a/llvm/test/CodeGen/X86/vec_uint_to_fp.ll +++ b/llvm/test/CodeGen/X86/vec_uint_to_fp.ll @@ -23,10 +23,10 @@ ; CST-NEXT: .long 1392508928 ## 0x53000000 ; CST: [[MAGICCSTADDR:LCPI0_[0-9]+]]: -; CST-NEXT: .long 1392509056 ## float 5.49764202E+11 -; CST-NEXT: .long 1392509056 ## float 5.49764202E+11 -; CST-NEXT: .long 1392509056 ## float 5.49764202E+11 -; CST-NEXT: .long 1392509056 ## float 5.49764202E+11 +; CST-NEXT: .long 0x53000080 ## float 5.49764202E+11 +; CST-NEXT: .long 0x53000080 ## float 5.49764202E+11 +; CST-NEXT: .long 0x53000080 ## float 5.49764202E+11 +; CST-NEXT: .long 0x53000080 ## float 5.49764202E+11 ; AVX2: [[LOWCSTADDR:LCPI0_[0-9]+]]: ; AVX2-NEXT: .long 1258291200 ## 0x4b000000 @@ -35,7 +35,7 @@ ; AVX2-NEXT: .long 1392508928 ## 0x53000000 ; AVX2: [[MAGICCSTADDR:LCPI0_[0-9]+]]: -; AVX2-NEXT: .long 1392509056 ## float 5.49764202E+11 +; AVX2-NEXT: .long 0x53000080 ## float 5.49764202E+11 define <4 x float> @test1(<4 x i32> %A) nounwind { ; CHECK-LABEL: test1: @@ -91,7 +91,7 @@ ; AVX2-NEXT: .long 1392508928 ## 0x53000000 ; AVX2: [[MAGICCSTADDR:LCPI1_[0-9]+]]: -; AVX2-NEXT: .long 1392509056 ## float 5.49764202E+11 +; AVX2-NEXT: .long 0x53000080 ## float 5.49764202E+11 define <8 x float> @test2(<8 x i32> %A) nounwind { ; CHECK-LABEL: test2: diff --git a/llvm/test/CodeGen/X86/win_cst_pool.ll b/llvm/test/CodeGen/X86/win_cst_pool.ll --- a/llvm/test/CodeGen/X86/win_cst_pool.ll +++ b/llvm/test/CodeGen/X86/win_cst_pool.ll @@ -14,7 +14,7 @@ ; CHECK-NEXT: .section .rdata,"dr",discard,__real@0000000000800000 ; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: __real@0000000000800000: -; CHECK-NEXT: .quad 8388608 +; CHECK-NEXT: .quad 0x0000000000800000 ; CHECK: double: ; CHECK: movsd __real@0000000000800000(%rip), %xmm0 ; CHECK-NEXT: ret @@ -22,7 +22,7 @@ ; MINGW: .section .rdata,"dr" ; MINGW-NEXT: .p2align 3 ; MINGW-NEXT: [[LABEL:\.LC.*]]: -; MINGW-NEXT: .quad 8388608 +; MINGW-NEXT: .quad 0x0000000000800000 ; MINGW: double: ; MINGW: movsd [[LABEL]](%rip), %xmm0 ; MINGW-NEXT: ret @@ -69,8 +69,8 @@ ; CHECK-NEXT: .section .rdata,"dr",discard,__xmm@00000000000000003f8000003f800000 ; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: __xmm@00000000000000003f8000003f800000: -; CHECK-NEXT: .long 1065353216 # float 1 -; CHECK-NEXT: .long 1065353216 # float 1 +; CHECK-NEXT: .long 0x3f800000 # float 1 +; CHECK-NEXT: .long 0x3f800000 # float 1 ; CHECK-NEXT: .zero 4 ; CHECK-NEXT: .zero 4 ; CHECK: undef1: @@ -88,8 +88,8 @@ ; CHECK-NEXT: .section .rdata,"dr",discard,__real@bf8000003f800000 ; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: __real@bf8000003f800000: -; CHECK-NEXT: .long 1065353216 -; CHECK-NEXT: .long 3212836864 +; CHECK-NEXT: .long 0x3f800000 +; CHECK-NEXT: .long 0xbf800000 define <4 x i64> @ymm() { entry: diff --git a/llvm/test/CodeGen/X86/x86-setcc-int-to-fp-combine.ll b/llvm/test/CodeGen/X86/x86-setcc-int-to-fp-combine.ll --- a/llvm/test/CodeGen/X86/x86-setcc-int-to-fp-combine.ll +++ b/llvm/test/CodeGen/X86/x86-setcc-int-to-fp-combine.ll @@ -46,10 +46,10 @@ ; Also test the general purpose constant folding of int->fp. define void @foo2(<4 x float>* noalias %result) nounwind { ; CHECK-LABEL: LCPI2_0: -; CHECK-NEXT: .long 1082130432 ## float 4 -; CHECK-NEXT: .long 1084227584 ## float 5 -; CHECK-NEXT: .long 1086324736 ## float 6 -; CHECK-NEXT: .long 1088421888 ## float 7 +; CHECK-NEXT: .long 0x40800000 ## float 4 +; CHECK-NEXT: .long 0x40a00000 ## float 5 +; CHECK-NEXT: .long 0x40c00000 ## float 6 +; CHECK-NEXT: .long 0x40e00000 ## float 7 ; CHECK-LABEL: foo2: ; CHECK: ## %bb.0: ; CHECK-NEXT: movaps {{.*#+}} xmm0 = [4.0E+0,5.0E+0,6.0E+0,7.0E+0] @@ -83,10 +83,10 @@ ; Test the general purpose constant folding of uint->fp. define void @foo4(<4 x float>* noalias %result) nounwind { ; CHECK-LABEL: LCPI4_0: -; CHECK-NEXT: .long 1065353216 ## float 1 -; CHECK-NEXT: .long 1123942400 ## float 127 -; CHECK-NEXT: .long 1124073472 ## float 128 -; CHECK-NEXT: .long 1132396544 ## float 255 +; CHECK-NEXT: .long 0x3f800000 ## float 1 +; CHECK-NEXT: .long 0x42fe0000 ## float 127 +; CHECK-NEXT: .long 0x43000000 ## float 128 +; CHECK-NEXT: .long 0x437f0000 ## float 255 ; CHECK-LABEL: foo4: ; CHECK: ## %bb.0: ; CHECK-NEXT: movaps {{.*#+}} xmm0 = [1.0E+0,1.27E+2,1.28E+2,2.55E+2]