diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
--- a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
@@ -28,6 +28,7 @@
 
 namespace llvm {
 // Forward declarations.
+struct LegalityQuery;
 class LegalizerInfo;
 class Legalizer;
 class MachineRegisterInfo;
@@ -190,6 +191,9 @@
                          ArrayRef<Register> Src1Regs,
                          ArrayRef<Register> Src2Regs, LLT NarrowTy);
 
+  /// Helper function to test whether an operation is supported by the target.
+  bool isSupported(const LegalityQuery &Q);
+
 public:
   LegalizeResult fewerElementsVectorImplicitDef(MachineInstr &MI,
                                                 unsigned TypeIdx, LLT NarrowTy);
@@ -263,6 +267,8 @@
   LegalizeResult lowerBswap(MachineInstr &MI);
   LegalizeResult lowerBitreverse(MachineInstr &MI);
   LegalizeResult lowerReadRegister(MachineInstr &MI);
+  LegalizeResult lowerUADDSAT_USUBSAT(MachineInstr &MI);
+  LegalizeResult lowerSADDSAT_SSUBSAT(MachineInstr &MI);
 
 private:
   MachineRegisterInfo &MRI;
diff --git a/llvm/include/llvm/Support/TargetOpcodes.def b/llvm/include/llvm/Support/TargetOpcodes.def
--- a/llvm/include/llvm/Support/TargetOpcodes.def
+++ b/llvm/include/llvm/Support/TargetOpcodes.def
@@ -442,6 +442,18 @@
 // the high half of the result.
 HANDLE_TARGET_OPCODE(G_SMULH)
 
+/// Generic saturating unsigned addition.
+HANDLE_TARGET_OPCODE(G_UADDSAT)
+
+/// Generic saturating signed addition.
+HANDLE_TARGET_OPCODE(G_SADDSAT)
+
+/// Generic saturating unsigned subtraction.
+HANDLE_TARGET_OPCODE(G_USUBSAT)
+
+/// Generic saturating signed subtraction.
+HANDLE_TARGET_OPCODE(G_SSUBSAT)
+
 /// Generic FP addition.
 HANDLE_TARGET_OPCODE(G_FADD)
 
diff --git a/llvm/include/llvm/Target/GenericOpcodes.td b/llvm/include/llvm/Target/GenericOpcodes.td
--- a/llvm/include/llvm/Target/GenericOpcodes.td
+++ b/llvm/include/llvm/Target/GenericOpcodes.td
@@ -469,6 +469,42 @@
   let isCommutable = 1;
 }
 
+//------------------------------------------------------------------------------
+// Saturating ops
+//------------------------------------------------------------------------------
+
+// Generic saturating unsigned addition.
+def G_UADDSAT : GenericInstruction {
+  let OutOperandList = (outs type0:$dst);
+  let InOperandList = (ins type0:$src1, type0:$src2);
+  let hasSideEffects = 0;
+  let isCommutable = 1;
+}
+
+// Generic saturating signed addition.
+def G_SADDSAT : GenericInstruction {
+  let OutOperandList = (outs type0:$dst);
+  let InOperandList = (ins type0:$src1, type0:$src2);
+  let hasSideEffects = 0;
+  let isCommutable = 1;
+}
+
+// Generic saturating unsigned subtraction.
+def G_USUBSAT : GenericInstruction {
+  let OutOperandList = (outs type0:$dst);
+  let InOperandList = (ins type0:$src1, type0:$src2);
+  let hasSideEffects = 0;
+  let isCommutable = 0;
+}
+
+// Generic saturating signed subtraction.
+def G_SSUBSAT : GenericInstruction {
+  let OutOperandList = (outs type0:$dst);
+  let InOperandList = (ins type0:$src1, type0:$src2);
+  let hasSideEffects = 0;
+  let isCommutable = 0;
+}
+
 //------------------------------------------------------------------------------
 // Floating Point Unary Ops.
 //------------------------------------------------------------------------------
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -1404,6 +1404,14 @@
     return translateOverflowIntrinsic(CI, TargetOpcode::G_UMULO, MIRBuilder);
   case Intrinsic::smul_with_overflow:
     return translateOverflowIntrinsic(CI, TargetOpcode::G_SMULO, MIRBuilder);
+  case Intrinsic::uadd_sat:
+    return translateBinaryOp(TargetOpcode::G_UADDSAT, CI, MIRBuilder);
+  case Intrinsic::sadd_sat:
+    return translateBinaryOp(TargetOpcode::G_SADDSAT, CI, MIRBuilder);
+  case Intrinsic::usub_sat:
+    return translateBinaryOp(TargetOpcode::G_USUBSAT, CI, MIRBuilder);
+  case Intrinsic::ssub_sat:
+    return translateBinaryOp(TargetOpcode::G_SSUBSAT, CI, MIRBuilder);
   case Intrinsic::fmuladd: {
     const TargetMachine &TM = MF->getTarget();
     const TargetLowering &TLI = *MF->getSubtarget().getTargetLowering();
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -2433,6 +2433,12 @@
     return lowerBitreverse(MI);
   case G_READ_REGISTER:
     return lowerReadRegister(MI);
+  case G_UADDSAT:
+  case G_USUBSAT:
+    return lowerUADDSAT_USUBSAT(MI);
+  case G_SADDSAT:
+  case G_SSUBSAT:
+    return lowerSADDSAT_SSUBSAT(MI);
   }
 }
 
@@ -3852,14 +3858,15 @@
   return Legalized;
 }
 
+bool LegalizerHelper::isSupported(const LegalityQuery &Q) {
+  auto QAction = LI.getAction(Q).Action;
+  return QAction == Legal || QAction == Libcall || QAction == Custom;
+}
+
 LegalizerHelper::LegalizeResult
 LegalizerHelper::lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
   unsigned Opc = MI.getOpcode();
   auto &TII = *MI.getMF()->getSubtarget().getInstrInfo();
-  auto isSupported = [this](const LegalityQuery &Q) {
-    auto QAction = LI.getAction(Q).Action;
-    return QAction == Legal || QAction == Libcall || QAction == Custom;
-  };
   switch (Opc) {
   default:
     return UnableToLegalize;
@@ -4513,6 +4520,74 @@
   return Legalized;
 }
 
+LegalizerHelper::LegalizeResult
+LegalizerHelper::lowerUADDSAT_USUBSAT(MachineInstr &MI) {
+  Register Res = MI.getOperand(0).getReg();
+  Register LHS = MI.getOperand(1).getReg();
+  Register RHS = MI.getOperand(2).getReg();
+  LLT Ty = MRI.getType(Res);
+  LLT BoolTy = Ty.changeElementSize(1);
+  bool IsAdd = MI.getOpcode() == TargetOpcode::G_UADDSAT;
+
+  if (isSupported({TargetOpcode::G_UMIN, {Ty, Ty}})) {
+    // uadd.sat(a, b) -> a + umin(~a, b)
+    // usub.sat(a, b) -> a - umin(a, b)
+    Register Not =
+        IsAdd ? MIRBuilder.buildNot(Ty, LHS)->getOperand(0).getReg() : LHS;
+    auto Min = MIRBuilder.buildUMin(Ty, Not, RHS);
+    unsigned Opcode = IsAdd ? TargetOpcode::G_ADD : TargetOpcode::G_SUB;
+    MIRBuilder.buildInstr(Opcode, {Res}, {LHS, Min});
+  } else {
+    // uadd.sat(a, b) ->
+    //   {r, ov} = uaddo(a, b)
+    //   ov ? 0xffffffff : r
+    // usub.sat(a, b) ->
+    //   {r, ov} = usubo(a, b)
+    //   ov ? 0 : r
+    unsigned Opcode = IsAdd ? TargetOpcode::G_UADDO : TargetOpcode::G_USUBO;
+    auto Addo = MIRBuilder.buildInstr(Opcode, {Ty, BoolTy}, {LHS, RHS});
+    Register Add = Addo->getOperand(0).getReg();
+    Register Overflow = Addo->getOperand(1).getReg();
+    APInt ClampInt(Ty.getScalarSizeInBits(), IsAdd ? -1 : 0, true);
+    auto Clamp = MIRBuilder.buildConstant(Ty, ClampInt);
+    MIRBuilder.buildSelect(Res, Overflow, Clamp, Add);
+  }
+
+  MI.eraseFromParent();
+  return Legalized;
+}
+
+LegalizerHelper::LegalizeResult
+LegalizerHelper::lowerSADDSAT_SSUBSAT(MachineInstr &MI) {
+  Register Dst = MI.getOperand(0).getReg();
+  Register LHS = MI.getOperand(1).getReg();
+  Register RHS = MI.getOperand(2).getReg();
+  LLT Ty = MRI.getType(Dst);
+  LLT BoolTy = Ty.changeElementSize(1);
+  bool IsAdd = MI.getOpcode() == TargetOpcode::G_SADDSAT;
+
+  // sadd.sat(a, b) ->
+  //   {r, ov} = saddo(a, b)
+  //   ov ? (r >>> 31) + 0x80000000 : r
+  // ssub.sat(a, b) ->
+  //   {r, ov} = ssubo(a, b)
+  //   ov ? (r >>> 31) + 0x80000000 : r
+  auto Addo = MIRBuilder.buildInstr(IsAdd ? TargetOpcode::G_SADDO
+                                          : TargetOpcode::G_SSUBO,
+                                    {Ty, BoolTy}, {LHS, RHS});
+  Register Add = Addo->getOperand(0).getReg();
+  Register Overflow = Addo->getOperand(1).getReg();
+  uint64_t NumBits = Ty.getScalarSizeInBits();
+  auto Amount = MIRBuilder.buildConstant(Ty, NumBits - 1);
+  auto Sign = MIRBuilder.buildAShr(Ty, Add, Amount);
+  auto MinVal = MIRBuilder.buildConstant(Ty, APInt::getSignedMinValue(NumBits));
+  auto Clamp = MIRBuilder.buildAdd(Ty, Sign, MinVal);
+  MIRBuilder.buildSelect(Dst, Overflow, Clamp, Add);
+
+  MI.eraseFromParent();
+  return Legalized;
+}
+
 LegalizerHelper::LegalizeResult
 LegalizerHelper::lowerBswap(MachineInstr &MI) {
   Register Dst = MI.getOperand(0).getReg();
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -305,6 +305,8 @@
 
   getActionDefinitionsBuilder({G_SADDO, G_SSUBO})
     .lower();
+  getActionDefinitionsBuilder({G_UADDSAT, G_SADDSAT, G_USUBSAT, G_SSUBSAT})
+    .lower();
 
   getActionDefinitionsBuilder(G_BITCAST)
     // Don't worry about the size constraint.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
@@ -314,6 +314,18 @@
 # DEBUG-NEXT: G_SMULH (opcode {{[0-9]+}}): 1 type index, 0 imm indices
 # DEBUG-NEXT: .. the first uncovered type index: 1, OK
 # DEBUG-NEXT: .. the first uncovered imm index: 0, OK
+# DEBUG-NEXT: G_UADDSAT (opcode 117): 1 type index, 0 imm indices
+# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: G_SADDSAT (opcode 118): 1 type index, 0 imm indices
+# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: G_USUBSAT (opcode 119): 1 type index, 0 imm indices
+# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: G_SSUBSAT (opcode 120): 1 type index, 0 imm indices
+# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
 # DEBUG-NEXT: G_FADD (opcode {{[0-9]+}}): 1 type index, 0 imm indices
 # DEBUG-NEXT: .. the first uncovered type index: 1, OK
 # DEBUG-NEXT: .. the first uncovered imm index: 0, OK
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sat.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sat.ll
@@ -0,0 +1,129 @@
+; RUN: llc -march=amdgcn -global-isel -stop-after=irtranslator %s -o - | FileCheck %s
+
+; CHECK-LABEL: name: uaddsat_i16
+; CHECK: G_UADDSAT
+define i16 @uaddsat_i16(i16 %lhs, i16 %rhs) {
+  %res = call i16 @llvm.uadd.sat.i16(i16 %lhs, i16 %rhs)
+  ret i16 %res
+}
+declare i16 @llvm.uadd.sat.i16(i16, i16)
+
+; CHECK-LABEL: name: uaddsat_i32
+; CHECK: G_UADDSAT
+define i32 @uaddsat_i32(i32 %lhs, i32 %rhs) {
+  %res = call i32 @llvm.uadd.sat.i32(i32 %lhs, i32 %rhs)
+  ret i32 %res
+}
+declare i32 @llvm.uadd.sat.i32(i32, i32)
+
+; CHECK-LABEL: name: uaddsat_i64
+; CHECK: G_UADDSAT
+define i64 @uaddsat_i64(i64 %lhs, i64 %rhs) {
+  %res = call i64 @llvm.uadd.sat.i64(i64 %lhs, i64 %rhs)
+  ret i64 %res
+}
+declare i64 @llvm.uadd.sat.i64(i64, i64)
+
+; CHECK-LABEL: name: uaddsat_v2i32
+; CHECK: G_UADDSAT
+define <2 x i32> @uaddsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
+  %res = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
+  ret <2 x i32> %res
+}
+declare <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32>, <2 x i32>)
+
+; CHECK-LABEL: name: saddsat_i16
+; CHECK: G_SADDSAT
+define i16 @saddsat_i16(i16 %lhs, i16 %rhs) {
+  %res = call i16 @llvm.sadd.sat.i16(i16 %lhs, i16 %rhs)
+  ret i16 %res
+}
+declare i16 @llvm.sadd.sat.i16(i16, i16)
+
+; CHECK-LABEL: name: saddsat_i32
+; CHECK: G_SADDSAT
+define i32 @saddsat_i32(i32 %lhs, i32 %rhs) {
+  %res = call i32 @llvm.sadd.sat.i32(i32 %lhs, i32 %rhs)
+  ret i32 %res
+}
+declare i32 @llvm.sadd.sat.i32(i32, i32)
+
+; CHECK-LABEL: name: saddsat_i64
+; CHECK: G_SADDSAT
+define i64 @saddsat_i64(i64 %lhs, i64 %rhs) {
+  %res = call i64 @llvm.sadd.sat.i64(i64 %lhs, i64 %rhs)
+  ret i64 %res
+}
+declare i64 @llvm.sadd.sat.i64(i64, i64)
+
+; CHECK-LABEL: name: saddsat_v2i32
+; CHECK: G_SADDSAT
+define <2 x i32> @saddsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
+  %res = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
+  ret <2 x i32> %res
+}
+declare <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32>, <2 x i32>)
+
+; CHECK-LABEL: name: usubsat_i16
+; CHECK: G_USUBSAT
+define i16 @usubsat_i16(i16 %lhs, i16 %rhs) {
+  %res = call i16 @llvm.usub.sat.i16(i16 %lhs, i16 %rhs)
+  ret i16 %res
+}
+declare i16 @llvm.usub.sat.i16(i16, i16)
+
+; CHECK-LABEL: name: usubsat_i32
+; CHECK: G_USUBSAT
+define i32 @usubsat_i32(i32 %lhs, i32 %rhs) {
+  %res = call i32 @llvm.usub.sat.i32(i32 %lhs, i32 %rhs)
+  ret i32 %res
+}
+declare i32 @llvm.usub.sat.i32(i32, i32)
+
+; CHECK-LABEL: name: usubsat_i64
+; CHECK: G_USUBSAT
+define i64 @usubsat_i64(i64 %lhs, i64 %rhs) {
+  %res = call i64 @llvm.usub.sat.i64(i64 %lhs, i64 %rhs)
+  ret i64 %res
+}
+declare i64 @llvm.usub.sat.i64(i64, i64)
+
+; CHECK-LABEL: name: usubsat_v2i32
+; CHECK: G_USUBSAT
+define <2 x i32> @usubsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
+  %res = call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
+  ret <2 x i32> %res
+}
+declare <2 x i32> @llvm.usub.sat.v2i32(<2 x i32>, <2 x i32>)
+
+; CHECK-LABEL: name: ssubsat_i16
+; CHECK: G_SSUBSAT
+define i16 @ssubsat_i16(i16 %lhs, i16 %rhs) {
+  %res = call i16 @llvm.ssub.sat.i16(i16 %lhs, i16 %rhs)
+  ret i16 %res
+}
+declare i16 @llvm.ssub.sat.i16(i16, i16)
+
+; CHECK-LABEL: name: ssubsat_i32
+; CHECK: G_SSUBSAT
+define i32 @ssubsat_i32(i32 %lhs, i32 %rhs) {
+  %res = call i32 @llvm.ssub.sat.i32(i32 %lhs, i32 %rhs)
+  ret i32 %res
+}
+declare i32 @llvm.ssub.sat.i32(i32, i32)
+
+; CHECK-LABEL: name: ssubsat_i64
+; CHECK: G_SSUBSAT
+define i64 @ssubsat_i64(i64 %lhs, i64 %rhs) {
+  %res = call i64 @llvm.ssub.sat.i64(i64 %lhs, i64 %rhs)
+  ret i64 %res
+}
+declare i64 @llvm.ssub.sat.i64(i64, i64)
+
+; CHECK-LABEL: name: ssubsat_v2i32
+; CHECK: G_SSUBSAT
+define <2 x i32> @ssubsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
+  %res = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
+  ret <2 x i32> %res
+}
+declare <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32>, <2 x i32>)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sat.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sat.mir
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sat.mir
@@ -0,0 +1,254 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -run-pass=legalizer %s -o - | FileCheck %s
+
+---
+name: uaddsat_s16
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1
+
+    ; CHECK-LABEL: name: uaddsat_s16
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+    ; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+    ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
+    ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+    ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
+    ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
+    ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]]
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
+    ; CHECK: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1
+    ; CHECK: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[C1]], [[TRUNC]]
+    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
+    ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
+    %3:_(s32) = COPY $vgpr0
+    %0:_(s16) = G_TRUNC %3(s32)
+    %4:_(s32) = COPY $vgpr1
+    %1:_(s16) = G_TRUNC %4(s32)
+    %2:sgpr_64 = COPY $sgpr30_sgpr31
+    %5:_(s16) = G_UADDSAT %0, %1
+    %7:_(s32) = G_ANYEXT %5(s16)
+    $vgpr0 = COPY %7(s32)
+...
+
+---
+name: uaddsat_s32
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1
+
+    ; CHECK-LABEL: name: uaddsat_s32
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+    ; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C]]
+    ; CHECK: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[XOR]], [[COPY1]]
+    ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[UMIN]]
+    ; CHECK: $vgpr0 = COPY [[ADD]](s32)
+    %0:_(s32) = COPY $vgpr0
+    %1:_(s32) = COPY $vgpr1
+    %2:_(s32) = G_UADDSAT %0, %1
+    $vgpr0 = COPY %2
+...
+
+---
+name: saddsat_s16
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1
+
+    ; CHECK-LABEL: name: saddsat_s16
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+    ; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
+    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+    ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
+    ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY3]], [[COPY4]]
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
+    ; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
+    ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C1]](s32)
+    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
+    ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+    ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[C1]](s32)
+    ; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]](s32)
+    ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[ASHR]](s32), [[ASHR1]]
+    ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
+    ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY7]], [[C1]](s32)
+    ; CHECK: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C1]](s32)
+    ; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[C]](s16)
+    ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[ASHR2]](s32), [[SEXT]]
+    ; CHECK: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP1]], [[ICMP]]
+    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
+    ; CHECK: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[C2]](s32)
+    ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[ASHR3]](s32)
+    ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
+    ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY8]], [[C3]]
+    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ADD1]](s32)
+    ; CHECK: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[XOR]](s1), [[TRUNC1]], [[TRUNC]]
+    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
+    ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
+    %3:_(s32) = COPY $vgpr0
+    %0:_(s16) = G_TRUNC %3(s32)
+    %4:_(s32) = COPY $vgpr1
+    %1:_(s16) = G_TRUNC %4(s32)
+    %2:sgpr_64 = COPY $sgpr30_sgpr31
+    %5:_(s16) = G_SADDSAT %0, %1
+    %7:_(s32) = G_ANYEXT %5(s16)
+    $vgpr0 = COPY %7(s32)
+...
+
+---
+name: saddsat_s32
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1
+
+    ; CHECK-LABEL: name: saddsat_s32
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+    ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]]
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[ADD]](s32), [[COPY]]
+    ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY1]](s32), [[C]]
+    ; CHECK: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP1]], [[ICMP]]
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
+    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[ADD]], [[C1]](s32)
+    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
+    ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[C2]]
+    ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[XOR]](s1), [[ADD1]], [[ADD]]
+    ; CHECK: $vgpr0 = COPY [[SELECT]](s32)
+    %0:_(s32) = COPY $vgpr0
+    %1:_(s32) = COPY $vgpr1
+    %2:_(s32) = G_SADDSAT %0, %1
+    $vgpr0 = COPY %2
+...
+
+---
+name: usubsat_s16
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1
+
+    ; CHECK-LABEL: name: usubsat_s16
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+    ; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+    ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
+    ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+    ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]]
+    ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
+    ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SUB]](s32), [[AND2]]
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SUB]](s32)
+    ; CHECK: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
+    ; CHECK: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[C1]], [[TRUNC]]
+    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
+    ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
+    %3:_(s32) = COPY $vgpr0
+    %0:_(s16) = G_TRUNC %3(s32)
+    %4:_(s32) = COPY $vgpr1
+    %1:_(s16) = G_TRUNC %4(s32)
+    %2:sgpr_64 = COPY $sgpr30_sgpr31
+    %5:_(s16) = G_USUBSAT %0, %1
+    %7:_(s32) = G_ANYEXT %5(s16)
+    $vgpr0 = COPY %7(s32)
+...
+
+---
+name: usubsat_s32
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1
+
+    ; CHECK-LABEL: name: usubsat_s32
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+    ; CHECK: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[COPY]], [[COPY1]]
+    ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[UMIN]]
+    ; CHECK: $vgpr0 = COPY [[SUB]](s32)
+    %0:_(s32) = COPY $vgpr0
+    %1:_(s32) = COPY $vgpr1
+    %2:_(s32) = G_USUBSAT %0, %1
+    $vgpr0 = COPY %2
+...
+
+---
+name: ssubsat_s16
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1
+
+    ; CHECK-LABEL: name: ssubsat_s16
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+    ; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
+    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+    ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
+    ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY3]], [[COPY4]]
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SUB]](s32)
+    ; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
+    ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C1]](s32)
+    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
+    ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
+    ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[C1]](s32)
+    ; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]](s32)
+    ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[ASHR]](s32), [[ASHR1]]
+    ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
+    ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY7]], [[C1]](s32)
+    ; CHECK: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C1]](s32)
+    ; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[C]](s16)
+    ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[ASHR2]](s32), [[SEXT]]
+    ; CHECK: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP1]], [[ICMP]]
+    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
+    ; CHECK: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[C2]](s32)
+    ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[ASHR3]](s32)
+    ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
+    ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY8]], [[C3]]
+    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
+    ; CHECK: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[XOR]](s1), [[TRUNC1]], [[TRUNC]]
+    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
+    ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
+    %3:_(s32) = COPY $vgpr0
+    %0:_(s16) = G_TRUNC %3(s32)
+    %4:_(s32) = COPY $vgpr1
+    %1:_(s16) = G_TRUNC %4(s32)
+    %2:sgpr_64 = COPY $sgpr30_sgpr31
+    %5:_(s16) = G_SSUBSAT %0, %1
+    %7:_(s32) = G_ANYEXT %5(s16)
+    $vgpr0 = COPY %7(s32)
+...
+
+---
+name: ssubsat_s32
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1
+
+    ; CHECK-LABEL: name: ssubsat_s32
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+    ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY1]]
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SUB]](s32), [[COPY]]
+    ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[COPY1]](s32), [[C]]
+    ; CHECK: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP1]], [[ICMP]]
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
+    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SUB]], [[C1]](s32)
+    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
+    ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[C2]]
+    ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[XOR]](s1), [[ADD]], [[SUB]]
+    ; CHECK: $vgpr0 = COPY [[SELECT]](s32)
+    %0:_(s32) = COPY $vgpr0
+    %1:_(s32) = COPY $vgpr1
+    %2:_(s32) = G_SSUBSAT %0, %1
+    $vgpr0 = COPY %2
+...