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GlobalISel: Lower s64->s16 G_FPTRUNC
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Authored by arsenm on Jan 20 2020, 4:34 AM.

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Details

Reviewers

aemerson
aditya_nandakumar
paquette
dsanders
volkan

Summary

This is more or less directly ported from the AMDGPU custom lowering
for FP_TO_FP16. I made a few minor fixups (using G_UNMERGE_VALUES
instead of creating shift/trunc to extract the two halves, and zexting
an inverted compare instead of select_cc).

This also does not include the fast math expansion the DAG which
converts to f32 and then to f16. I think that belongs in a
pre-legalize combine instead.

Diff Detail

Event Timeline

arsenm created this revision.Jan 20 2020, 4:34 AM

Herald added a project: Restricted Project. · View Herald TranscriptJan 20 2020, 4:34 AM

Herald added subscribers: kerbowa, Petar.Avramovic, volkan and 6 others. · View Herald Transcript

ping

nhaehnle removed a subscriber: nhaehnle.Jan 29 2020, 1:27 AM

ping

LGTM.

This revision is now accepted and ready to land.Feb 14 2020, 10:06 AM

bfbfa18591db4eff68a6692b8503efd1571cdb88

Revision Contents

Path

Size

llvm/

include/

llvm/

CodeGen/

GlobalISel/

LegalizerHelper.h

2 lines

lib/

CodeGen/

GlobalISel/

LegalizerHelper.cpp

124 lines

Target/

AMDGPU/

AMDGPULegalizerInfo.cpp

3 lines

test/

CodeGen/

AMDGPU/

GlobalISel/

legalize-fptrunc.mir

404 lines

Diff 239077

llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h

Show First 20 Lines • Show All 243 Lines • ▼ Show 20 Lines	public:

LegalizeResult lowerBitcast(MachineInstr &MI);		LegalizeResult lowerBitcast(MachineInstr &MI);
LegalizeResult lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty);		LegalizeResult lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty);

LegalizeResult lowerU64ToF32BitOps(MachineInstr &MI);		LegalizeResult lowerU64ToF32BitOps(MachineInstr &MI);
LegalizeResult lowerUITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty);		LegalizeResult lowerUITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
LegalizeResult lowerSITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty);		LegalizeResult lowerSITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
LegalizeResult lowerFPTOUI(MachineInstr &MI, unsigned TypeIdx, LLT Ty);		LegalizeResult lowerFPTOUI(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
		LegalizeResult lowerFPTRUNC_F64_TO_F16(MachineInstr &MI);
		LegalizeResult lowerFPTRUNC(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
LegalizeResult lowerMinMax(MachineInstr &MI, unsigned TypeIdx, LLT Ty);		LegalizeResult lowerMinMax(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
LegalizeResult lowerFCopySign(MachineInstr &MI, unsigned TypeIdx, LLT Ty);		LegalizeResult lowerFCopySign(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
LegalizeResult lowerFMinNumMaxNum(MachineInstr &MI);		LegalizeResult lowerFMinNumMaxNum(MachineInstr &MI);
LegalizeResult lowerFMad(MachineInstr &MI);		LegalizeResult lowerFMad(MachineInstr &MI);
LegalizeResult lowerIntrinsicRound(MachineInstr &MI);		LegalizeResult lowerIntrinsicRound(MachineInstr &MI);
LegalizeResult lowerUnmergeValues(MachineInstr &MI);		LegalizeResult lowerUnmergeValues(MachineInstr &MI);
LegalizeResult lowerShuffleVector(MachineInstr &MI);		LegalizeResult lowerShuffleVector(MachineInstr &MI);
LegalizeResult lowerDynStackAlloc(MachineInstr &MI);		LegalizeResult lowerDynStackAlloc(MachineInstr &MI);
Show All 28 Lines

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Show First 20 Lines • Show All 2,386 Lines • ▼ Show 20 Lines	case G_USUBE: {
return Legalized;		return Legalized;
}		}
case G_UITOFP:		case G_UITOFP:
return lowerUITOFP(MI, TypeIdx, Ty);		return lowerUITOFP(MI, TypeIdx, Ty);
case G_SITOFP:		case G_SITOFP:
return lowerSITOFP(MI, TypeIdx, Ty);		return lowerSITOFP(MI, TypeIdx, Ty);
case G_FPTOUI:		case G_FPTOUI:
return lowerFPTOUI(MI, TypeIdx, Ty);		return lowerFPTOUI(MI, TypeIdx, Ty);
		case G_FPTRUNC:
		return lowerFPTRUNC(MI, TypeIdx, Ty);
case G_SMIN:		case G_SMIN:
case G_SMAX:		case G_SMAX:
case G_UMIN:		case G_UMIN:
case G_UMAX:		case G_UMAX:
return lowerMinMax(MI, TypeIdx, Ty);		return lowerMinMax(MI, TypeIdx, Ty);
case G_FCOPYSIGN:		case G_FCOPYSIGN:
return lowerFCopySign(MI, TypeIdx, Ty);		return lowerFCopySign(MI, TypeIdx, Ty);
case G_FMINNUM:		case G_FMINNUM:
▲ Show 20 Lines • Show All 1,723 Lines • ▼ Show 20 Lines	LegalizerHelper::lowerFPTOUI(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
MachineInstrBuilder FCMP =		MachineInstrBuilder FCMP =
MIRBuilder.buildFCmp(CmpInst::FCMP_ULT, S1, Src, Threshold);		MIRBuilder.buildFCmp(CmpInst::FCMP_ULT, S1, Src, Threshold);
MIRBuilder.buildSelect(Dst, FCMP, FPTOSI, Res);		MIRBuilder.buildSelect(Dst, FCMP, FPTOSI, Res);

MI.eraseFromParent();		MI.eraseFromParent();
return Legalized;		return Legalized;
}		}

		// f64 -> f16 conversion using round-to-nearest-even rounding mode.
		LegalizerHelper::LegalizeResult
		LegalizerHelper::lowerFPTRUNC_F64_TO_F16(MachineInstr &MI) {
		Register Dst = MI.getOperand(0).getReg();
		Register Src = MI.getOperand(1).getReg();

		if (MRI.getType(Src).isVector()) // TODO: Handle vectors directly.
		return UnableToLegalize;

		const unsigned ExpMask = 0x7ff;
		const unsigned ExpBiasf64 = 1023;
		const unsigned ExpBiasf16 = 15;
		const LLT S32 = LLT::scalar(32);
		const LLT S1 = LLT::scalar(1);

		auto Unmerge = MIRBuilder.buildUnmerge(S32, Src);
		Register U = Unmerge.getReg(0);
		Register UH = Unmerge.getReg(1);

		auto E = MIRBuilder.buildLShr(S32, UH, MIRBuilder.buildConstant(S32, 20));

		// Subtract the fp64 exponent bias (1023) to get the real exponent and
		// add the f16 bias (15) to get the biased exponent for the f16 format.
		E = MIRBuilder.buildAdd(
		S32, E, MIRBuilder.buildConstant(S32, -ExpBiasf64 + ExpBiasf16));
		E = MIRBuilder.buildAnd(S32, E, MIRBuilder.buildConstant(S32, ExpMask));

		auto M = MIRBuilder.buildLShr(S32, UH, MIRBuilder.buildConstant(S32, 8));
		M = MIRBuilder.buildAnd(S32, M, MIRBuilder.buildConstant(S32, 0xffe));

		auto MaskedSig = MIRBuilder.buildAnd(S32, UH,
		MIRBuilder.buildConstant(S32, 0x1ff));
		MaskedSig = MIRBuilder.buildOr(S32, MaskedSig, U);

		auto Zero = MIRBuilder.buildConstant(S32, 0);
		auto SigCmpNE0 = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, MaskedSig, Zero);
		auto Lo40Set = MIRBuilder.buildZExt(S32, SigCmpNE0);
		M = MIRBuilder.buildOr(S32, M, Lo40Set);

		// (M != 0 ? 0x0200 : 0) \| 0x7c00;
		auto Bits0x200 = MIRBuilder.buildConstant(S32, 0x0200);
		auto CmpM_NE0 = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, M, Zero);
		auto SelectCC = MIRBuilder.buildSelect(S32, CmpM_NE0, Bits0x200, Zero);

		auto Bits0x7c00 = MIRBuilder.buildConstant(S32, 0x7c00);
		auto I = MIRBuilder.buildOr(S32, SelectCC, Bits0x7c00);

		// N = M \| (E << 12);
		auto EShl12 = MIRBuilder.buildShl(S32, E, MIRBuilder.buildConstant(S32, 12));
		auto N = MIRBuilder.buildOr(S32, M, EShl12);

		// B = clamp(1-E, 0, 13);
		auto One = MIRBuilder.buildConstant(S32, 1);
		auto OneSubExp = MIRBuilder.buildSub(S32, One, E);
		auto B = MIRBuilder.buildSMax(S32, OneSubExp, Zero);
		B = MIRBuilder.buildSMin(S32, B, MIRBuilder.buildConstant(S32, 13));

		auto SigSetHigh = MIRBuilder.buildOr(S32, M,
		MIRBuilder.buildConstant(S32, 0x1000));

		auto D = MIRBuilder.buildLShr(S32, SigSetHigh, B);
		auto D0 = MIRBuilder.buildShl(S32, D, B);

		auto D0_NE_SigSetHigh = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1,
		D0, SigSetHigh);
		auto D1 = MIRBuilder.buildZExt(S32, D0_NE_SigSetHigh);
		D = MIRBuilder.buildOr(S32, D, D1);

		auto CmpELtOne = MIRBuilder.buildICmp(CmpInst::ICMP_SLT, S1, E, One);
		auto V = MIRBuilder.buildSelect(S32, CmpELtOne, D, N);

		auto VLow3 = MIRBuilder.buildAnd(S32, V, MIRBuilder.buildConstant(S32, 7));
		V = MIRBuilder.buildLShr(S32, V, MIRBuilder.buildConstant(S32, 2));

		auto VLow3Eq3 = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1, VLow3,
		MIRBuilder.buildConstant(S32, 3));
		auto V0 = MIRBuilder.buildZExt(S32, VLow3Eq3);

		auto VLow3Gt5 = MIRBuilder.buildICmp(CmpInst::ICMP_SGT, S1, VLow3,
		MIRBuilder.buildConstant(S32, 5));
		auto V1 = MIRBuilder.buildZExt(S32, VLow3Gt5);

		V1 = MIRBuilder.buildOr(S32, V0, V1);
		V = MIRBuilder.buildAdd(S32, V, V1);

		auto CmpEGt30 = MIRBuilder.buildICmp(CmpInst::ICMP_SGT, S1,
		E, MIRBuilder.buildConstant(S32, 30));
		V = MIRBuilder.buildSelect(S32, CmpEGt30,
		MIRBuilder.buildConstant(S32, 0x7c00), V);

		auto CmpEGt1039 = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1,
		E, MIRBuilder.buildConstant(S32, 1039));
		V = MIRBuilder.buildSelect(S32, CmpEGt1039, I, V);

		// Extract the sign bit.
		auto Sign = MIRBuilder.buildLShr(S32, UH, MIRBuilder.buildConstant(S32, 16));
		Sign = MIRBuilder.buildAnd(S32, Sign, MIRBuilder.buildConstant(S32, 0x8000));

		// Insert the sign bit
		V = MIRBuilder.buildOr(S32, Sign, V);

		MIRBuilder.buildTrunc(Dst, V);
		MI.eraseFromParent();
		return Legalized;
		}

		LegalizerHelper::LegalizeResult
		LegalizerHelper::lowerFPTRUNC(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
		Register Dst = MI.getOperand(0).getReg();
		Register Src = MI.getOperand(1).getReg();

		LLT DstTy = MRI.getType(Dst);
		LLT SrcTy = MRI.getType(Src);
		const LLT S64 = LLT::scalar(64);
		const LLT S16 = LLT::scalar(16);

		if (DstTy.getScalarType() == S16 && SrcTy.getScalarType() == S64)
		return lowerFPTRUNC_F64_TO_F16(MI);

		return UnableToLegalize;
		}

static CmpInst::Predicate minMaxToCompare(unsigned Opc) {		static CmpInst::Predicate minMaxToCompare(unsigned Opc) {
switch (Opc) {		switch (Opc) {
case TargetOpcode::G_SMIN:		case TargetOpcode::G_SMIN:
return CmpInst::ICMP_SLT;		return CmpInst::ICMP_SLT;
case TargetOpcode::G_SMAX:		case TargetOpcode::G_SMAX:
return CmpInst::ICMP_SGT;		return CmpInst::ICMP_SGT;
case TargetOpcode::G_UMIN:		case TargetOpcode::G_UMIN:
return CmpInst::ICMP_ULT;		return CmpInst::ICMP_ULT;
▲ Show 20 Lines • Show All 469 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Show First 20 Lines • Show All 412 Lines • ▼ Show 20 Lines	if (ST.has16BitInsts()) {
getActionDefinitionsBuilder({G_FSQRT, G_FFLOOR})		getActionDefinitionsBuilder({G_FSQRT, G_FFLOOR})
.legalFor({S32, S64})		.legalFor({S32, S64})
.scalarize(0)		.scalarize(0)
.clampScalar(0, S32, S64);		.clampScalar(0, S32, S64);
}		}

getActionDefinitionsBuilder(G_FPTRUNC)		getActionDefinitionsBuilder(G_FPTRUNC)
.legalFor({{S32, S64}, {S16, S32}})		.legalFor({{S32, S64}, {S16, S32}})
.scalarize(0);		.scalarize(0)
		.lower();

getActionDefinitionsBuilder(G_FPEXT)		getActionDefinitionsBuilder(G_FPEXT)
.legalFor({{S64, S32}, {S32, S16}})		.legalFor({{S64, S32}, {S32, S16}})
.lowerFor({{S64, S16}}) // FIXME: Implement		.lowerFor({{S64, S16}}) // FIXME: Implement
.scalarize(0);		.scalarize(0);

// TODO: Verify V_BFI_B32 is generated from expanded bit ops.		// TODO: Verify V_BFI_B32 is generated from expanded bit ops.
getActionDefinitionsBuilder(G_FCOPYSIGN).lower();		getActionDefinitionsBuilder(G_FCOPYSIGN).lower();
▲ Show 20 Lines • Show All 2,049 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptrunc.mir

Show First 20 Lines • Show All 65 Lines • ▼ Show 20 Lines	bb.0:
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC1]](s16)		; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC1]](s16)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32)		; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)		; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1		%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s16>) = G_FPTRUNC %0		%1:_(<2 x s16>) = G_FPTRUNC %0
%2:_(<2 x s32>) = G_ANYEXT %1		%2:_(<2 x s32>) = G_ANYEXT %1
$vgpr0_vgpr1 = COPY %2		$vgpr0_vgpr1 = COPY %2
...		...

		---
		name: test_fptrunc_s64_to_s16
		body: \|
		bb.0:
		liveins: $vgpr0_vgpr1

		; CHECK-LABEL: name: test_fptrunc_s64_to_s16
		; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
		; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
		; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
		; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
		; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1008
		; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LSHR]], [[C1]]
		; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2047
		; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C2]]
		; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
		; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C3]](s32)
		; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4094
		; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C4]]
		; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 511
		; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C5]]
		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[UV]]
		; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
		; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[OR]](s32), [[C6]]
		; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[ZEXT]]
		; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 512
		; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[OR1]](s32), [[C6]]
		; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[C7]], [[C6]]
		; CHECK: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 31744
		; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SELECT]], [[C8]]
		; CHECK: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C9]](s32)
		; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL]]
		; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
		; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C10]], [[AND]]
		; CHECK: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SUB]], [[C6]]
		; CHECK: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 13
		; CHECK: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SMAX]], [[C11]]
		; CHECK: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 4096
		; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]]
		; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[SMIN]](s32)
		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR2]], [[SMIN]](s32)
		; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL1]](s32), [[OR4]]
		; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP2]](s1)
		; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[ZEXT1]]
		; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[AND]](s32), [[C10]]
		; CHECK: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s1), [[OR5]], [[OR3]]
		; CHECK: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
		; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C13]]
		; CHECK: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
		; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[SELECT1]], [[C14]](s32)
		; CHECK: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
		; CHECK: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[AND3]](s32), [[C15]]
		; CHECK: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP4]](s1)
		; CHECK: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
		; CHECK: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[AND3]](s32), [[C16]]
		; CHECK: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP5]](s1)
		; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[ZEXT3]]
		; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR3]], [[OR6]]
		; CHECK: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 30
		; CHECK: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[AND]](s32), [[C17]]
		; CHECK: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP6]](s1), [[C8]], [[ADD1]]
		; CHECK: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 1039
		; CHECK: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[AND]](s32), [[C18]]
		; CHECK: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP7]](s1), [[OR2]], [[SELECT2]]
		; CHECK: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
		; CHECK: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C19]](s32)
		; CHECK: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 32768
		; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C20]]
		; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SELECT3]]
		; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR7]](s32)
		; CHECK: $vgpr0 = COPY [[COPY1]](s32)
		%0:_(s64) = COPY $vgpr0_vgpr1
		%1:_(s16) = G_FPTRUNC %0
		%2:_(s32) = G_ANYEXT %1
		$vgpr0 = COPY %2
		...

		---
		name: test_fptrunc_v2s64_to_v2s16
		body: \|
		bb.0:
		liveins: $vgpr0_vgpr1_vgpr2_vgpr3

		; CHECK-LABEL: name: test_fptrunc_v2s64_to_v2s16
		; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
		; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
		; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](s64)
		; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
		; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)
		; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1008
		; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LSHR]], [[C1]]
		; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2047
		; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C2]]
		; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
		; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C3]](s32)
		; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4094
		; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C4]]
		; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 511
		; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C5]]
		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[UV2]]
		; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
		; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[OR]](s32), [[C6]]
		; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[ZEXT]]
		; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 512
		; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[OR1]](s32), [[C6]]
		; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[C7]], [[C6]]
		; CHECK: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 31744
		; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SELECT]], [[C8]]
		; CHECK: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C9]](s32)
		; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL]]
		; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
		; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C10]], [[AND]]
		; CHECK: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SUB]], [[C6]]
		; CHECK: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 13
		; CHECK: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SMAX]], [[C11]]
		; CHECK: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 4096
		; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]]
		; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[SMIN]](s32)
		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR2]], [[SMIN]](s32)
		; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL1]](s32), [[OR4]]
		; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP2]](s1)
		; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[ZEXT1]]
		; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[AND]](s32), [[C10]]
		; CHECK: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s1), [[OR5]], [[OR3]]
		; CHECK: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
		; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C13]]
		; CHECK: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
		; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[SELECT1]], [[C14]](s32)
		; CHECK: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
		; CHECK: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[AND3]](s32), [[C15]]
		; CHECK: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP4]](s1)
		; CHECK: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
		; CHECK: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[AND3]](s32), [[C16]]
		; CHECK: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP5]](s1)
		; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[ZEXT3]]
		; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR3]], [[OR6]]
		; CHECK: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 30
		; CHECK: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[AND]](s32), [[C17]]
		; CHECK: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP6]](s1), [[C8]], [[ADD1]]
		; CHECK: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 1039
		; CHECK: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[AND]](s32), [[C18]]
		; CHECK: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP7]](s1), [[OR2]], [[SELECT2]]
		; CHECK: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
		; CHECK: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C19]](s32)
		; CHECK: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 32768
		; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C20]]
		; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SELECT3]]
		; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR7]](s32)
		; CHECK: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64)
		; CHECK: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C]](s32)
		; CHECK: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[LSHR5]], [[C1]]
		; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ADD2]], [[C2]]
		; CHECK: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C3]](s32)
		; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C4]]
		; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[UV5]], [[C5]]
		; CHECK: [[OR8:%[0-9]+]]:_(s32) = G_OR [[AND7]], [[UV4]]
		; CHECK: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[OR8]](s32), [[C6]]
		; CHECK: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP8]](s1)
		; CHECK: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[ZEXT4]]
		; CHECK: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[OR9]](s32), [[C6]]
		; CHECK: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP9]](s1), [[C7]], [[C6]]
		; CHECK: [[OR10:%[0-9]+]]:_(s32) = G_OR [[SELECT4]], [[C8]]
		; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C9]](s32)
		; CHECK: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL2]]
		; CHECK: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C10]], [[AND5]]
		; CHECK: [[SMAX1:%[0-9]+]]:_(s32) = G_SMAX [[SUB1]], [[C6]]
		; CHECK: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[C11]]
		; CHECK: [[OR12:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[C12]]
		; CHECK: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[OR12]], [[SMIN1]](s32)
		; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[LSHR7]], [[SMIN1]](s32)
		; CHECK: [[ICMP10:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL3]](s32), [[OR12]]
		; CHECK: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP10]](s1)
		; CHECK: [[OR13:%[0-9]+]]:_(s32) = G_OR [[LSHR7]], [[ZEXT5]]
		; CHECK: [[ICMP11:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[AND5]](s32), [[C10]]
		; CHECK: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[ICMP11]](s1), [[OR13]], [[OR11]]
		; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[SELECT5]], [[C13]]
		; CHECK: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[SELECT5]], [[C14]](s32)
		; CHECK: [[ICMP12:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[AND8]](s32), [[C15]]
		; CHECK: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP12]](s1)
		; CHECK: [[ICMP13:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[AND8]](s32), [[C16]]
		; CHECK: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP13]](s1)
		; CHECK: [[OR14:%[0-9]+]]:_(s32) = G_OR [[ZEXT6]], [[ZEXT7]]
		; CHECK: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[LSHR8]], [[OR14]]
		; CHECK: [[ICMP14:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[AND5]](s32), [[C17]]
		; CHECK: [[SELECT6:%[0-9]+]]:_(s32) = G_SELECT [[ICMP14]](s1), [[C8]], [[ADD3]]
		; CHECK: [[ICMP15:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[AND5]](s32), [[C18]]
		; CHECK: [[SELECT7:%[0-9]+]]:_(s32) = G_SELECT [[ICMP15]](s1), [[OR10]], [[SELECT6]]
		; CHECK: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C19]](s32)
		; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C20]]
		; CHECK: [[OR15:%[0-9]+]]:_(s32) = G_OR [[AND9]], [[SELECT7]]
		; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[OR15]](s32)
		; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
		; CHECK: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
		%0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
		%1:_(<2 x s16>) = G_FPTRUNC %0
		$vgpr0 = COPY %1
		...

		---
		name: test_fptrunc_s64_to_s16_afn
		body: \|
		bb.0:
		liveins: $vgpr0_vgpr1

		; CHECK-LABEL: name: test_fptrunc_s64_to_s16_afn
		; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
		; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
		; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
		; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
		; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1008
		; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LSHR]], [[C1]]
		; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2047
		; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C2]]
		; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
		; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C3]](s32)
		; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4094
		; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C4]]
		; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 511
		; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C5]]
		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[UV]]
		; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
		; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[OR]](s32), [[C6]]
		; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[ZEXT]]
		; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 512
		; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[OR1]](s32), [[C6]]
		; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[C7]], [[C6]]
		; CHECK: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 31744
		; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SELECT]], [[C8]]
		; CHECK: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C9]](s32)
		; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL]]
		; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
		; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C10]], [[AND]]
		; CHECK: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SUB]], [[C6]]
		; CHECK: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 13
		; CHECK: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SMAX]], [[C11]]
		; CHECK: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 4096
		; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]]
		; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[SMIN]](s32)
		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR2]], [[SMIN]](s32)
		; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL1]](s32), [[OR4]]
		; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP2]](s1)
		; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[ZEXT1]]
		; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[AND]](s32), [[C10]]
		; CHECK: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s1), [[OR5]], [[OR3]]
		; CHECK: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
		; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C13]]
		; CHECK: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
		; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[SELECT1]], [[C14]](s32)
		; CHECK: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
		; CHECK: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[AND3]](s32), [[C15]]
		; CHECK: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP4]](s1)
		; CHECK: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
		; CHECK: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[AND3]](s32), [[C16]]
		; CHECK: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP5]](s1)
		; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[ZEXT3]]
		; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR3]], [[OR6]]
		; CHECK: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 30
		; CHECK: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[AND]](s32), [[C17]]
		; CHECK: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP6]](s1), [[C8]], [[ADD1]]
		; CHECK: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 1039
		; CHECK: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[AND]](s32), [[C18]]
		; CHECK: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP7]](s1), [[OR2]], [[SELECT2]]
		; CHECK: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
		; CHECK: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C19]](s32)
		; CHECK: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 32768
		; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C20]]
		; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SELECT3]]
		; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR7]](s32)
		; CHECK: $vgpr0 = COPY [[COPY1]](s32)
		%0:_(s64) = COPY $vgpr0_vgpr1
		%1:_(s16) = G_FPTRUNC %0
		%2:_(s32) = afn G_ANYEXT %1
		$vgpr0 = COPY %2
		...

		---
		name: test_fptrunc_v2s64_to_v2s16_afn
		body: \|
		bb.0:
		liveins: $vgpr0_vgpr1_vgpr2_vgpr3

		; CHECK-LABEL: name: test_fptrunc_v2s64_to_v2s16_afn
		; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
		; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
		; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](s64)
		; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
		; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)
		; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1008
		; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LSHR]], [[C1]]
		; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2047
		; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C2]]
		; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
		; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C3]](s32)
		; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4094
		; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C4]]
		; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 511
		; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C5]]
		; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[UV2]]
		; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
		; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[OR]](s32), [[C6]]
		; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
		; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[ZEXT]]
		; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 512
		; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[OR1]](s32), [[C6]]
		; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[C7]], [[C6]]
		; CHECK: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 31744
		; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SELECT]], [[C8]]
		; CHECK: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
		; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C9]](s32)
		; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL]]
		; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
		; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C10]], [[AND]]
		; CHECK: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SUB]], [[C6]]
		; CHECK: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 13
		; CHECK: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SMAX]], [[C11]]
		; CHECK: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 4096
		; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]]
		; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[SMIN]](s32)
		; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR2]], [[SMIN]](s32)
		; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL1]](s32), [[OR4]]
		; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP2]](s1)
		; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[ZEXT1]]
		; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[AND]](s32), [[C10]]
		; CHECK: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s1), [[OR5]], [[OR3]]
		; CHECK: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
		; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C13]]
		; CHECK: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
		; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[SELECT1]], [[C14]](s32)
		; CHECK: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
		; CHECK: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[AND3]](s32), [[C15]]
		; CHECK: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP4]](s1)
		; CHECK: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
		; CHECK: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[AND3]](s32), [[C16]]
		; CHECK: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP5]](s1)
		; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[ZEXT3]]
		; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR3]], [[OR6]]
		; CHECK: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 30
		; CHECK: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[AND]](s32), [[C17]]
		; CHECK: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP6]](s1), [[C8]], [[ADD1]]
		; CHECK: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 1039
		; CHECK: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[AND]](s32), [[C18]]
		; CHECK: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP7]](s1), [[OR2]], [[SELECT2]]
		; CHECK: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
		; CHECK: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C19]](s32)
		; CHECK: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 32768
		; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C20]]
		; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SELECT3]]
		; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR7]](s32)
		; CHECK: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64)
		; CHECK: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C]](s32)
		; CHECK: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[LSHR5]], [[C1]]
		; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ADD2]], [[C2]]
		; CHECK: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C3]](s32)
		; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C4]]
		; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[UV5]], [[C5]]
		; CHECK: [[OR8:%[0-9]+]]:_(s32) = G_OR [[AND7]], [[UV4]]
		; CHECK: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[OR8]](s32), [[C6]]
		; CHECK: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP8]](s1)
		; CHECK: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[ZEXT4]]
		; CHECK: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[OR9]](s32), [[C6]]
		; CHECK: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP9]](s1), [[C7]], [[C6]]
		; CHECK: [[OR10:%[0-9]+]]:_(s32) = G_OR [[SELECT4]], [[C8]]
		; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C9]](s32)
		; CHECK: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL2]]
		; CHECK: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C10]], [[AND5]]
		; CHECK: [[SMAX1:%[0-9]+]]:_(s32) = G_SMAX [[SUB1]], [[C6]]
		; CHECK: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[C11]]
		; CHECK: [[OR12:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[C12]]
		; CHECK: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[OR12]], [[SMIN1]](s32)
		; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[LSHR7]], [[SMIN1]](s32)
		; CHECK: [[ICMP10:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL3]](s32), [[OR12]]
		; CHECK: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP10]](s1)
		; CHECK: [[OR13:%[0-9]+]]:_(s32) = G_OR [[LSHR7]], [[ZEXT5]]
		; CHECK: [[ICMP11:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[AND5]](s32), [[C10]]
		; CHECK: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[ICMP11]](s1), [[OR13]], [[OR11]]
		; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[SELECT5]], [[C13]]
		; CHECK: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[SELECT5]], [[C14]](s32)
		; CHECK: [[ICMP12:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[AND8]](s32), [[C15]]
		; CHECK: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP12]](s1)
		; CHECK: [[ICMP13:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[AND8]](s32), [[C16]]
		; CHECK: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP13]](s1)
		; CHECK: [[OR14:%[0-9]+]]:_(s32) = G_OR [[ZEXT6]], [[ZEXT7]]
		; CHECK: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[LSHR8]], [[OR14]]
		; CHECK: [[ICMP14:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[AND5]](s32), [[C17]]
		; CHECK: [[SELECT6:%[0-9]+]]:_(s32) = G_SELECT [[ICMP14]](s1), [[C8]], [[ADD3]]
		; CHECK: [[ICMP15:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[AND5]](s32), [[C18]]
		; CHECK: [[SELECT7:%[0-9]+]]:_(s32) = G_SELECT [[ICMP15]](s1), [[OR10]], [[SELECT6]]
		; CHECK: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C19]](s32)
		; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C20]]
		; CHECK: [[OR15:%[0-9]+]]:_(s32) = G_OR [[AND9]], [[SELECT7]]
		; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[OR15]](s32)
		; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16)
		; CHECK: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>)
		%0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
		%1:_(<2 x s16>) = afn G_FPTRUNC %0
		$vgpr0 = COPY %1
		...

This is an archive of the discontinued LLVM Phabricator instance.

GlobalISel: Lower s64->s16 G_FPTRUNCClosedPublic

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Diff 239077

llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptrunc.mir

GlobalISel: Lower s64->s16 G_FPTRUNC
ClosedPublic