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[SLP] Revectorize partially vectorized instructions
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Authored by anton-afanasyev on Jan 14 2020, 2:36 AM.

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Summary

This is just a draft with a lot of dirty hacks to show proof-of-concept
for the revectorization of partially vectorized instructions.

The main motivation comes from here: http://llvm.org/pr42022.
We need to merge store <2 x float>, store <2 x float> to store <4 x float>.
Such cases happen, for instance, when SLP-optimizing already SLP-optimized inlined
code.

The solution is to permit insertelement's as vectorization tree node, but this should
be done carefully: insertelement's couldn't be scheduled (they have inner deps).

Early feedback is appreciated since this unfinished work could concern another revisions
(like D44067 or PR35732).

This is follow-up of D70587 and D70924

Event Timeline

Herald added a project: Restricted Project. · View Herald TranscriptJan 14 2020, 2:36 AM

I saw similar thing in recent research

https://www.nextgenvec.org/slides/revec-cc.pdf

They proposed a new compiler pass to perform revectorization.

Did you look at it? What do you think?

I saw similar thing in recent research

https://www.nextgenvec.org/slides/revec-cc.pdf

They proposed a new compiler pass to perform revectorization.

Did you look at it? What do you think?

Thank you, I'm to learn it. There is another obvious solution for such task using special pass: just break partitial vectorization before SLP pass.

anton-afanasyev retitled this revision from [SLP] Vectorize partially vectorized instructions to [SLP] Revectorize partially vectorized instructions.Jan 16 2020, 1:27 AM
anton-afanasyev edited the summary of this revision. (Show Details)