diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -2351,6 +2351,10 @@ def mharden_sls_EQ : Joined<["-"], "mharden-sls=">, HelpText<"Select straight-line speculation hardening scope">; +def msve_vector_bits : Joined<["-"], "msve-vector-bits=">, + Group, + HelpText<"Specify the size in bits of an SVE vector register." + " Has no effect unless SVE is enabled. (Default is \"scalable\")">; def msimd128 : Flag<["-"], "msimd128">, Group; def munimplemented_simd128 : Flag<["-"], "munimplemented-simd128">, Group; diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp --- a/clang/lib/Driver/ToolChains/Clang.cpp +++ b/clang/lib/Driver/ToolChains/Clang.cpp @@ -1715,6 +1715,22 @@ if (IndirectBranches) CmdArgs.push_back("-mbranch-target-enforce"); } + + if (any_of(CmdArgs, [](const char *Arg) { + return (strcmp(Arg, "+sve") == 0 || strcmp(Arg, "+sve2") == 0); + })) { + if (Arg *A = Args.getLastArg(options::OPT_msve_vector_bits)) { + StringRef Bits = A->getValue(); + if (Bits != "scalable") { + CmdArgs.push_back("-mllvm"); + CmdArgs.push_back( + Args.MakeArgString("-aarch64-sve-vector-bits-min=" + Bits)); + // CmdArgs.push_back("-mllvm"); + // CmdArgs.push_back( + // Args.MakeArgString("-aarch64-sve-vector-bits-max=" + Bits)); + } + } + } } void Clang::AddMIPSTargetArgs(const ArgList &Args, diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp --- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp @@ -1819,7 +1819,7 @@ if (FPOffsetFits && CanUseBP) // Both are ok. Pick the best. UseFP = PreferFP; else if (!CanUseBP) { // Can't use BP. Forced to use FP. - assert(!SVEStackSize && "Expected BP to be available"); + // assert(!SVEStackSize && "Expected BP to be available"); UseFP = true; } // else we can use BP and FP, but the offset from FP won't fit.