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Differential D71328

[llvm][MIRVRegNamerUtils] Adding hashing for memoperands.
ClosedPublic

Authored by plotfi on Dec 10 2019, 10:42 PM.

Details

Reviewers
aditya_nandakumar
bogner
Commits
rGf5b7a468375d: [llvm][MIRVRegNamerUtils] Adding hashing on memoperands.
Summary

Now memoperand differences wont result in hash collisions.

Diff Detail

Event Timeline

plotfi created this revision.Dec 10 2019, 10:42 PM
Herald added a project: Restricted Project. · View Herald TranscriptDec 10 2019, 10:42 PM
Herald added subscribers: llvm-commits, hiraditya, nhaehnle, jvesely. · View Herald Transcript
plotfi retitled this revision from [llvm][MIRVRegNamerUtils] Adding hashinf for memoperands. to [llvm][MIRVRegNamerUtils] Adding hashing for memoperands..Dec 11 2019, 9:29 AM
aditya_nandakumar accepted this revision.Dec 11 2019, 10:52 AM
This revision is now accepted and ready to land.Dec 11 2019, 10:52 AM
Closed by commit rGf5b7a468375d: [llvm][MIRVRegNamerUtils] Adding hashing on memoperands. (authored by plotfi). · Explain WhyDec 11 2019, 7:19 PM
This revision was automatically updated to reflect the committed changes.
nhaehnle removed a subscriber: nhaehnle.Dec 13 2019, 5:55 AM

Revision Contents

PathSize
llvm/
lib/
CodeGen/
11 lines
test/
CodeGen/
MIR/
AMDGPU/
42 lines

Diff 233486

llvm/lib/CodeGen/MIRVRegNamerUtils.cpp

Show First 20 Lines • Show All 66 Lines • ▼ Show 20 Lines auto GetHashableMO = [this](const MachineOperand &MO) -> unsigned {
// is contributing to a hash collision but there's enough information // is contributing to a hash collision but there's enough information
// (Opcodes,other registers etc) that this will likely not be a problem. // (Opcodes,other registers etc) that this will likely not be a problem.
return 0; return 0;
}; };
SmallVector<unsigned, 16> MIOperands = {MI.getOpcode(), MI.getFlags()}; SmallVector<unsigned, 16> MIOperands = {MI.getOpcode(), MI.getFlags()};
llvm::transform(MI.uses(), std::back_inserter(MIOperands), GetHashableMO); llvm::transform(MI.uses(), std::back_inserter(MIOperands), GetHashableMO);
for (const auto *Op : MI.memoperands()) {
MIOperands.push_back((unsigned)Op->getSize());
MIOperands.push_back((unsigned)Op->getFlags());
MIOperands.push_back((unsigned)Op->getOffset());
MIOperands.push_back((unsigned)Op->getOrdering());
MIOperands.push_back((unsigned)Op->getAddrSpace());
MIOperands.push_back((unsigned)Op->getSyncScopeID());
MIOperands.push_back((unsigned)Op->getBaseAlignment());
MIOperands.push_back((unsigned)Op->getFailureOrdering());
}
auto HashMI = hash_combine_range(MIOperands.begin(), MIOperands.end()); auto HashMI = hash_combine_range(MIOperands.begin(), MIOperands.end());
return std::to_string(HashMI).substr(0, 5); return std::to_string(HashMI).substr(0, 5);
} }
unsigned VRegRenamer::createVirtualRegister(unsigned VReg) { unsigned VRegRenamer::createVirtualRegister(unsigned VReg) {
assert(Register::isVirtualRegister(VReg) && "Expected Virtual Registers"); assert(Register::isVirtualRegister(VReg) && "Expected Virtual Registers");
std::string Name = getInstructionOpcodeHash(*MRI.getVRegDef(VReg)); std::string Name = getInstructionOpcodeHash(*MRI.getVRegDef(VReg));
return createVirtualRegisterWithLowerName(VReg, Name); return createVirtualRegisterWithLowerName(VReg, Name);
Show All 35 Lines

llvm/test/CodeGen/MIR/AMDGPU/mircanon-memoperands.mir

  • This file was added.
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass mir-canonicalizer -o - %s | FileCheck %s
--- |
target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
define amdgpu_kernel void @f(i32 addrspace(1)* nocapture %arg) {
unreachable
}
...
---
name: f
alignment: 1
registers:
- { id: 0, class: sgpr_64 }
- { id: 1, class: sreg_64_xexec }
- { id: 2, class: sreg_64_xexec }
- { id: 3, class: sreg_64_xexec }
- { id: 4, class: sreg_64_xexec }
- { id: 5, class: sreg_64_xexec }
- { id: 6, class: sreg_64_xexec }
liveins:
- { reg: '$sgpr4_sgpr5', virtual-reg: '%4' }
body: |
bb.0:
liveins: $sgpr4_sgpr5
; CHECK: COPY
; CHECK-NEXT: %bb0_{{[0-9]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM
; CHECK-NEXT: %bb0_{{[0-9]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM
; CHECK-NEXT: %bb0_{{[0-9]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM
; CHECK-NEXT: %bb0_{{[0-9]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM
; CHECK-NEXT: %bb0_{{[0-9]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM
; CHECK-NEXT: %bb0_{{[0-9]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM
%0 = COPY $sgpr4_sgpr5
%1 = S_LOAD_DWORDX2_IMM %0, 0, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`)
%2 = S_LOAD_DWORDX2_IMM %0, 0, 0, 0 :: ( dereferenceable invariant load 8 from `i64 addrspace(4)* undef`)
%3 = S_LOAD_DWORDX2_IMM %0, 0, 0, 0 :: ( invariant load 8 from `i64 addrspace(4)* undef`)
%4 = S_LOAD_DWORDX2_IMM %0, 0, 0, 0 :: ( load 8 from `i64 addrspace(4)* undef`)
%5 = S_LOAD_DWORDX2_IMM %0, 0, 0, 0 :: ( load 8 from `i64 addrspace(2)* undef`)
%6 = S_LOAD_DWORDX2_IMM %0, 0, 0, 0 :: ( load 8 from `i64 addrspace(1)* undef`)
...