[TargetLowering] Allow constants with multiple uses

[dstuttard]

Summary

Multiple uses of a constant was causing an assert in target lowering for
propagating fnegs. Allow multiple uses when it is a constant fixes the issue.

Change-Id: Iffd1ce18bf13ec68d91ff47aecd7cf1918fd3c0a

[lebedev.ri]

llvm/test/CodeGen/AMDGPU/const-multiuse-tl.ll

2

This test doesn't actually check anything.

[dstuttard]

Included wrong version of the test initially

[dstuttard]

llvm/test/CodeGen/AMDGPU/const-multiuse-tl.ll

2

Yes, spotted it just after I uploaded. It does now. It's really only testing that it doesn't assert.

[dstuttard]

Added @RKSimon to review as the last major modifier of the code here.

[RKSimon]

llvm/test/CodeGen/AMDGPU/const-multiuse-tl.ll

2

Is this reduced as much as possible (both in terms of instructions and metadata)?

[dstuttard]

I've got some failures as a result of this change in X86 (haven't tried the other backends). I guess that the failures are probably due to the fneg propagation working better for constants - but I haven't investigated yet. There will need to be more test changes as a result of this change.
My question is - does the change look reasonable? If so I'll take a look at the lit regressions for other backends.

llvm/test/CodeGen/AMDGPU/const-multiuse-tl.ll

2

I've attempted to reduce it as much as possible - I did attempt to reduce it further but that stopped the problem occurring.
I might be able to reduce the metadata more.

[RKSimon]

I'd like to see more of the regressions on other targets (x86 in particular) - in many cases this will cause a lot of extra constant pool entries.

[dstuttard]

In D70595#1756702, @RKSimon wrote:

I'd like to see more of the regressions on other targets (x86 in particular) - in many cases this will cause a lot of extra constant pool entries.

Ok - I'' take a look at those and upload some patches.

I'm more than happy if this can be solved in a different way - the issue isn't an optimisation opportunity, it is actually causing a problem with the attached example due to the difference between checking isNegatibleForFree (and it syaing it is) and it then finding a problem in getNegatedExpression when it returns a different (and unexpected) result from a call to isNegatableForFree when handling an ISD::FMA.

[RKSimon]

I'd be more interested in fixing the isNegatibleForFree/getNegatedExpression mismatch - the next step for PR42863 will be to convert AMDGPU's performFNegCombine to TLI isNegatibleForFree/getNegatedExpression callbacks like X86.

[dstuttard]

Added test updates for failing lit tests.

[dstuttard]

Changed the implementation slightly.
Now the isNegatibleForFree includes a bool for allowing multi-use
constants. This is only set to true for calls from getNegatedExpression so it
only allows for the situation where a constant becomes multi-use during
getNegatedExpression recursive evaluation.

This makes all the existing lit tests pass again (with no changes).

[spatel]

First, we can definitely reduce the test - it only needs an fneg(fma(fmul X, C), -C, Y) pattern to show the crash, and that should repro on any target with fma support (so it's just unlucky that we didn't hit this bug sooner).

I thought we could get away with a simpler patch as originally proposed here, but I have convinced myself that would only be sweeping the bug under the rug. In fact, I don't think the current version of this patch goes far enough. When we're rewriting the expression, we can create arbitrary values, so *any* value (not just a constant) could have its number of uses changed and cause a crash/assert from mismatched handling in isNegatibleForFree/getNegatedExpression. I haven't reduced a test for that, but it seems possible.

I'll post an alternate patch that should solve the problem and see what people think of it.

[spatel]

In D70595#1767515, @spatel wrote:

I'll post an alternate patch that should solve the problem and see what people think of it.

D70975

[lebedev.ri]

@dstuttard does D70975 cover the original problem motivating this patch?

[dstuttard]

In D70595#1775820, @lebedev.ri wrote:

@dstuttard does D70975 cover the original problem motivating this patch?

Yes - confirmed that the alternative also fixes the issue for me.
I'll abandon this one.

[dstuttard]

Alternative fix D70975 works.

llvm/include/llvm/CodeGen/TargetLowering.h

virtual void insertCopiesSplitCSR(
     llvm_unreachable("Not Implemented");
   }
 
   /// Return 1 if we can compute the negated form of the specified expression
   /// for the same cost as the expression itself, or 2 if we can compute the
   /// negated form more cheaply than the expression itself. Else return 0.
   virtual char isNegatibleForFree(SDValue Op, SelectionDAG &DAG,
                                   bool LegalOperations, bool ForCodeSize,
+                                  bool AllowMultiConst,
                                   unsigned Depth = 0) const;
 
   /// If isNegatibleForFree returns true, return the newly negated expression.
   virtual SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG,
                                        bool LegalOperations, bool ForCodeSize,
                                        unsigned Depth = 0) const;
 
   //===--------------------------------------------------------------------===//

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

if (N1C && N1C->isZero())
     if (N1C->isNegative() || Options.NoSignedZerosFPMath || Flags.hasNoSignedZeros())
       return N0;
 
   if (SDValue NewSel = foldBinOpIntoSelect(N))
     return NewSel;
 
   // fold (fadd A, (fneg B)) -> (fsub A, B)
   if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
-      TLI.isNegatibleForFree(N1, DAG, LegalOperations, ForCodeSize) == 2)
+      TLI.isNegatibleForFree(N1, DAG, LegalOperations, ForCodeSize, false) == 2)
     return DAG.getNode(
         ISD::FSUB, DL, VT, N0,
         TLI.getNegatedExpression(N1, DAG, LegalOperations, ForCodeSize), Flags);
 
   // fold (fadd (fneg A), B) -> (fsub B, A)
   if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
-      TLI.isNegatibleForFree(N0, DAG, LegalOperations, ForCodeSize) == 2)
+      TLI.isNegatibleForFree(N0, DAG, LegalOperations, ForCodeSize, false) == 2)
     return DAG.getNode(
         ISD::FSUB, DL, VT, N1,
         TLI.getNegatedExpression(N0, DAG, LegalOperations, ForCodeSize), Flags);
 
   auto isFMulNegTwo = [](SDValue FMul) {
     if (!FMul.hasOneUse() || FMul.getOpcode() != ISD::FMUL)
       return false;
     auto *C = isConstOrConstSplatFP(FMul.getOperand(1), true);
SDValue DAGCombiner::visitFSUB(SDNode *N) {
   // (fsub -0.0, N1) -> -N1
   // NOTE: It is safe to transform an FSUB(-0.0,X) into an FNEG(X), since the
   //       FSUB does not specify the sign bit of a NaN. Also note that for
   //       the same reason, the inverse transform is not safe, unless fast math
   //       flags are in play.
   if (N0CFP && N0CFP->isZero()) {
     if (N0CFP->isNegative() ||
         (Options.NoSignedZerosFPMath || Flags.hasNoSignedZeros())) {
-      if (TLI.isNegatibleForFree(N1, DAG, LegalOperations, ForCodeSize))
+      if (TLI.isNegatibleForFree(N1, DAG, LegalOperations, ForCodeSize, false))
         return TLI.getNegatedExpression(N1, DAG, LegalOperations, ForCodeSize);
       if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
         return DAG.getNode(ISD::FNEG, DL, VT, N1, Flags);
     }
   }
 
   if (((Options.UnsafeFPMath && Options.NoSignedZerosFPMath) ||
        (Flags.hasAllowReassociation() && Flags.hasNoSignedZeros())) &&
       N1.getOpcode() == ISD::FADD) {
     // X - (X + Y) -> -Y
     if (N0 == N1->getOperand(0))
       return DAG.getNode(ISD::FNEG, DL, VT, N1->getOperand(1), Flags);
     // X - (Y + X) -> -Y
     if (N0 == N1->getOperand(1))
       return DAG.getNode(ISD::FNEG, DL, VT, N1->getOperand(0), Flags);
   }
 
   // fold (fsub A, (fneg B)) -> (fadd A, B)
-  if (TLI.isNegatibleForFree(N1, DAG, LegalOperations, ForCodeSize))
+  if (TLI.isNegatibleForFree(N1, DAG, LegalOperations, ForCodeSize, false))
     return DAG.getNode(
         ISD::FADD, DL, VT, N0,
         TLI.getNegatedExpression(N1, DAG, LegalOperations, ForCodeSize), Flags);
 
   // FSUB -> FMA combines:
   if (SDValue Fused = visitFSUBForFMACombine(N)) {
     AddToWorklist(Fused.getNode());
     return Fused;
   }
 
   return SDValue();
 }
 
 /// Return true if both inputs are at least as cheap in negated form and at
 /// least one input is strictly cheaper in negated form.
 bool DAGCombiner::isCheaperToUseNegatedFPOps(SDValue X, SDValue Y) {
   if (char LHSNeg =
-          TLI.isNegatibleForFree(X, DAG, LegalOperations, ForCodeSize))
+      TLI.isNegatibleForFree(X, DAG, LegalOperations, ForCodeSize, false))
     if (char RHSNeg =
-            TLI.isNegatibleForFree(Y, DAG, LegalOperations, ForCodeSize))
+        TLI.isNegatibleForFree(Y, DAG, LegalOperations, ForCodeSize, false))
       // Both negated operands are at least as cheap as their counterparts.
       // Check to see if at least one is cheaper negated.
       if (LHSNeg == 2 || RHSNeg == 2)
         return true;
 
   return false;
 }
 

 SDValue DAGCombiner::visitFNEG(SDNode *N) {
   SDValue N0 = N->getOperand(0);
   EVT VT = N->getValueType(0);
 
   // Constant fold FNEG.
   if (isConstantFPBuildVectorOrConstantFP(N0))
     return DAG.getNode(ISD::FNEG, SDLoc(N), VT, N0);
 
-  if (TLI.isNegatibleForFree(N0, DAG, LegalOperations, ForCodeSize))
+  if (TLI.isNegatibleForFree(N0, DAG, LegalOperations, ForCodeSize, false))
     return TLI.getNegatedExpression(N0, DAG, LegalOperations, ForCodeSize);
 
   // Transform fneg(bitconvert(x)) -> bitconvert(x ^ sign) to avoid loading
   // constant pool values.
   if (!TLI.isFNegFree(VT) &&
       N0.getOpcode() == ISD::BITCAST &&
       N0.getNode()->hasOneUse()) {
     SDValue Int = N0.getOperand(0);

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

if (!isa<ConstantSDNode>(Op.getOperand(0))) {
     return true;
   }
 
   return false;
 }
 
 char TargetLowering::isNegatibleForFree(SDValue Op, SelectionDAG &DAG,
                                         bool LegalOperations, bool ForCodeSize,
-                                        unsigned Depth) const {
+                                        bool AllowMultiConst, unsigned Depth) const {
   // fneg is removable even if it has multiple uses.
   if (Op.getOpcode() == ISD::FNEG)
     return 2;
 
   // Don't allow anything with multiple uses unless we know it is free.
   EVT VT = Op.getValueType();
   const SDNodeFlags Flags = Op->getFlags();
   const TargetOptions &Options = DAG.getTarget().Options;
-  if (!Op.hasOneUse() && !(Op.getOpcode() == ISD::FP_EXTEND &&
-                           isFPExtFree(VT, Op.getOperand(0).getValueType())))
+  if (!Op.hasOneUse() &&
+      !(Op.getOpcode() == ISD::FP_EXTEND &&
+        isFPExtFree(VT, Op.getOperand(0).getValueType())) &&
+      !(AllowMultiConst && Op.getOpcode() == ISD::ConstantFP)
+      )
     return 0;
 
   // Don't recurse exponentially.
   if (Depth > SelectionDAG::MaxRecursionDepth)
     return 0;
 
   switch (Op.getOpcode()) {
   case ISD::ConstantFP: {
if (!Options.NoSignedZerosFPMath && !Flags.hasNoSignedZeros())
       return 0;
 
     // After operation legalization, it might not be legal to create new FSUBs.
     if (LegalOperations && !isOperationLegalOrCustom(ISD::FSUB, VT))
       return 0;
 
     // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
     if (char V = isNegatibleForFree(Op.getOperand(0), DAG, LegalOperations,
-                                    ForCodeSize, Depth + 1))
+                                    ForCodeSize, AllowMultiConst, Depth + 1))
       return V;
     // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
     return isNegatibleForFree(Op.getOperand(1), DAG, LegalOperations,
-                              ForCodeSize, Depth + 1);
+                              ForCodeSize, AllowMultiConst, Depth + 1);
   case ISD::FSUB:
     // We can't turn -(A-B) into B-A when we honor signed zeros.
     if (!Options.NoSignedZerosFPMath && !Flags.hasNoSignedZeros())
       return 0;
 
     // fold (fneg (fsub A, B)) -> (fsub B, A)
     return 1;
 
   case ISD::FMUL:
   case ISD::FDIV:
     // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y))
     if (char V = isNegatibleForFree(Op.getOperand(0), DAG, LegalOperations,
-                                    ForCodeSize, Depth + 1))
+                                    ForCodeSize, AllowMultiConst, Depth + 1))
       return V;
 
     // Ignore X * 2.0 because that is expected to be canonicalized to X + X.
     if (auto *C = isConstOrConstSplatFP(Op.getOperand(1)))
       if (C->isExactlyValue(2.0) && Op.getOpcode() == ISD::FMUL)
         return 0;
 
     return isNegatibleForFree(Op.getOperand(1), DAG, LegalOperations,
-                              ForCodeSize, Depth + 1);
+                              ForCodeSize, AllowMultiConst, Depth + 1);
 
   case ISD::FMA:
   case ISD::FMAD: {
     if (!Options.NoSignedZerosFPMath && !Flags.hasNoSignedZeros())
       return 0;
 
     // fold (fneg (fma X, Y, Z)) -> (fma (fneg X), Y, (fneg Z))
     // fold (fneg (fma X, Y, Z)) -> (fma X, (fneg Y), (fneg Z))
     char V2 = isNegatibleForFree(Op.getOperand(2), DAG, LegalOperations,
-                                 ForCodeSize, Depth + 1);
+                                 ForCodeSize, AllowMultiConst, Depth + 1);
     if (!V2)
       return 0;
 
     // One of Op0/Op1 must be cheaply negatible, then select the cheapest.
     char V0 = isNegatibleForFree(Op.getOperand(0), DAG, LegalOperations,
-                                 ForCodeSize, Depth + 1);
+                                 ForCodeSize, AllowMultiConst, Depth + 1);
     char V1 = isNegatibleForFree(Op.getOperand(1), DAG, LegalOperations,
-                                 ForCodeSize, Depth + 1);
+                                 ForCodeSize, AllowMultiConst, Depth + 1);
     char V01 = std::max(V0, V1);
     return V01 ? std::max(V01, V2) : 0;
   }
 
   case ISD::FP_EXTEND:
   case ISD::FP_ROUND:
   case ISD::FSIN:
     return isNegatibleForFree(Op.getOperand(0), DAG, LegalOperations,
-                              ForCodeSize, Depth + 1);
+                              ForCodeSize, AllowMultiConst, Depth + 1);
   }
 
   return 0;
 }
 
 SDValue TargetLowering::getNegatedExpression(SDValue Op, SelectionDAG &DAG,
                                              bool LegalOperations,
                                              bool ForCodeSize,
SDValue TargetLowering::getNegatedExpression(SDValue Op, SelectionDAG &DAG,
   }
   case ISD::FADD:
     assert((DAG.getTarget().Options.NoSignedZerosFPMath ||
             Flags.hasNoSignedZeros()) &&
            "Expected NSZ fp-flag");
 
     // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
     if (isNegatibleForFree(Op.getOperand(0), DAG, LegalOperations, ForCodeSize,
-                           Depth + 1))
+                           true, Depth + 1))
       return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
                          getNegatedExpression(Op.getOperand(0), DAG,
                                               LegalOperations, ForCodeSize,
                                               Depth + 1),
                          Op.getOperand(1), Flags);
     // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
     return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
                        getNegatedExpression(Op.getOperand(1), DAG,
case ISD::FSUB:
     // fold (fneg (fsub A, B)) -> (fsub B, A)
     return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
                        Op.getOperand(1), Op.getOperand(0), Flags);
 
   case ISD::FMUL:
   case ISD::FDIV:
     // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
     if (isNegatibleForFree(Op.getOperand(0), DAG, LegalOperations, ForCodeSize,
-                           Depth + 1))
+                           true, Depth + 1))
       return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
                          getNegatedExpression(Op.getOperand(0), DAG,
                                               LegalOperations, ForCodeSize,
                                               Depth + 1),
                          Op.getOperand(1), Flags);
 
     // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
     return DAG.getNode(
         Op.getOpcode(), SDLoc(Op), Op.getValueType(), Op.getOperand(0),
         getNegatedExpression(Op.getOperand(1), DAG, LegalOperations,
                              ForCodeSize, Depth + 1),
         Flags);
 
   case ISD::FMA:
   case ISD::FMAD: {
     assert((DAG.getTarget().Options.NoSignedZerosFPMath ||
             Flags.hasNoSignedZeros()) &&
            "Expected NSZ fp-flag");
 
     SDValue Neg2 = getNegatedExpression(Op.getOperand(2), DAG, LegalOperations,
                                         ForCodeSize, Depth + 1);
 
     char V0 = isNegatibleForFree(Op.getOperand(0), DAG, LegalOperations,
-                                 ForCodeSize, Depth + 1);
+                                 true, ForCodeSize, Depth + 1);
     char V1 = isNegatibleForFree(Op.getOperand(1), DAG, LegalOperations,
-                                 ForCodeSize, Depth + 1);
+                                 true, ForCodeSize, Depth + 1);
     if (V0 >= V1) {
       // fold (fneg (fma X, Y, Z)) -> (fma (fneg X), Y, (fneg Z))
       SDValue Neg0 = getNegatedExpression(
           Op.getOperand(0), DAG, LegalOperations, ForCodeSize, Depth + 1);
       return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(), Neg0,
                          Op.getOperand(1), Neg2, Flags);
     }
 

llvm/lib/Target/X86/X86ISelLowering.h

public:
     /// i16 is legal, but undesirable since i16 instruction encodings are longer
     /// and some i16 instructions are slow.
     bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const override;
 
     /// Return 1 if we can compute the negated form of the specified expression
     /// for the same cost as the expression itself, or 2 if we can compute the
     /// negated form more cheaply than the expression itself. Else return 0.
     char isNegatibleForFree(SDValue Op, SelectionDAG &DAG, bool LegalOperations,
-                            bool ForCodeSize, unsigned Depth) const override;
+                            bool ForCodeSize, bool AllowMultiConst,
+                            unsigned Depth) const override;
 
     /// If isNegatibleForFree returns true, return the newly negated expression.
     SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG,
                                  bool LegalOperations, bool ForCodeSize,
                                  unsigned Depth) const override;
 
     MachineBasicBlock *
     EmitInstrWithCustomInserter(MachineInstr &MI,

llvm/lib/Target/X86/X86ISelLowering.cpp

   }
 
   return SDValue();
 }
 
 char X86TargetLowering::isNegatibleForFree(SDValue Op, SelectionDAG &DAG,
                                            bool LegalOperations,
                                            bool ForCodeSize,
+                                           bool AllowMultiConst,
                                            unsigned Depth) const {
   // fneg patterns are removable even if they have multiple uses.
   if (isFNEG(DAG, Op.getNode(), Depth))
     return 2;
 
   // Don't recurse exponentially.
   if (Depth > SelectionDAG::MaxRecursionDepth)
     return 0;

     if (!Op.hasOneUse() || !Subtarget.hasAnyFMA() || !isTypeLegal(VT) ||
         !(SVT == MVT::f32 || SVT == MVT::f64) || !LegalOperations)
       break;
 
     // This is always negatible for free but we might be able to remove some
     // extra operand negations as well.
     for (int i = 0; i != 3; ++i) {
       char V = isNegatibleForFree(Op.getOperand(i), DAG, LegalOperations,
-                                  ForCodeSize, Depth + 1);
+                                  ForCodeSize, AllowMultiConst, Depth + 1);
       if (V == 2)
         return V;
     }
     return 1;
   }
   }
 
   return TargetLowering::isNegatibleForFree(Op, DAG, LegalOperations,
-                                            ForCodeSize, Depth);
+                                            ForCodeSize, AllowMultiConst, Depth);
 }
 
 SDValue X86TargetLowering::getNegatedExpression(SDValue Op, SelectionDAG &DAG,
                                                 bool LegalOperations,
                                                 bool ForCodeSize,
                                                 unsigned Depth) const {
   // fneg patterns are removable even if they have multiple uses.
   if (SDValue Arg = isFNEG(DAG, Op.getNode(), Depth))

         !(SVT == MVT::f32 || SVT == MVT::f64) || !LegalOperations)
       break;
 
     // This is always negatible for free but we might be able to remove some
     // extra operand negations as well.
     SmallVector<SDValue, 4> NewOps(Op.getNumOperands(), SDValue());
     for (int i = 0; i != 3; ++i) {
       char V = isNegatibleForFree(Op.getOperand(i), DAG, LegalOperations,
-                                  ForCodeSize, Depth + 1);
+                                  ForCodeSize, true, Depth + 1);
       if (V == 2)
         NewOps[i] = getNegatedExpression(Op.getOperand(i), DAG, LegalOperations,
                                          ForCodeSize, Depth + 1);
     }
 
     bool NegA = !!NewOps[0];
     bool NegB = !!NewOps[1];
     bool NegC = !!NewOps[2];

 
   SDValue A = N->getOperand(0);
   SDValue B = N->getOperand(1);
   SDValue C = N->getOperand(2);
 
   auto invertIfNegative = [&DAG, &TLI, &DCI](SDValue &V) {
     bool CodeSize = DAG.getMachineFunction().getFunction().hasOptSize();
     bool LegalOperations = !DCI.isBeforeLegalizeOps();
-    if (TLI.isNegatibleForFree(V, DAG, LegalOperations, CodeSize) == 2) {
+    if (TLI.isNegatibleForFree(V, DAG, LegalOperations, CodeSize, false) == 2) {
       V = TLI.getNegatedExpression(V, DAG, LegalOperations, CodeSize);
       return true;
     }
     // Look through extract_vector_elts. If it comes from an FNEG, create a
     // new extract from the FNEG input.
     if (V.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
         isNullConstant(V.getOperand(1))) {
       SDValue Vec = V.getOperand(0);
-      if (TLI.isNegatibleForFree(Vec, DAG, LegalOperations, CodeSize) == 2) {
+      if (TLI.isNegatibleForFree(Vec, DAG, LegalOperations, CodeSize, false) == 2) {
         SDValue NegVal =
             TLI.getNegatedExpression(Vec, DAG, LegalOperations, CodeSize);
         V = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(V), V.getValueType(),
                         NegVal, V.getOperand(1));
         return true;
       }
     }
 

                                TargetLowering::DAGCombinerInfo &DCI) {
   SDLoc dl(N);
   EVT VT = N->getValueType(0);
   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
   bool CodeSize = DAG.getMachineFunction().getFunction().hasOptSize();
   bool LegalOperations = !DCI.isBeforeLegalizeOps();
 
   SDValue N2 = N->getOperand(2);
-  if (TLI.isNegatibleForFree(N2, DAG, LegalOperations, CodeSize) != 2)
+  if (TLI.isNegatibleForFree(N2, DAG, LegalOperations, CodeSize, false) != 2)
     return SDValue();
 
   SDValue NegN2 = TLI.getNegatedExpression(N2, DAG, LegalOperations, CodeSize);
   unsigned NewOpcode = negateFMAOpcode(N->getOpcode(), false, true, false);
 
   if (N->getNumOperands() == 4)
     return DAG.getNode(NewOpcode, dl, VT, N->getOperand(0), N->getOperand(1),
                        NegN2, N->getOperand(3));

llvm/test/CodeGen/AMDGPU/const-multiuse-tl.ll

+; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN %s
+
+; GCN: v_fma_f32 v0, s0, 0, 0.5
+
+define amdgpu_ps void @main(float addrspace(6)* %arg1) #0 {
+main_body:
+  %tmp2 = load float, float addrspace(6)* %arg1
+  %tmp3 = call nsz float @llvm.floor.f32(float undef) #2
+  %tmp4 = fptosi float %tmp3 to i32
+  %tmp5 = add i32 0, %tmp4
+  %tmp6 = sub i32 0, %tmp5
+  %tmp7 = sitofp i32 %tmp4 to float
+  %tmp8 = fmul nsz float %tmp7, 0x3FEBB67AE0000000
+  %tmp9 = sitofp i32 %tmp6 to float
+  %tmp10 = call nsz float @llvm.fmuladd.f32(float %tmp9, float 0xBFEBB67AE0000000, float %tmp8) #2
+  %tmp11 = fsub nsz float 0.000000e+00, %tmp10
+  %tmp12 = call nsz float @llvm.fmuladd.f32(float %tmp11, float 5.000000e-01, float 5.000000e-01) #2
+  %tmp13 = call nsz float @llvm.fmuladd.f32(float 0.000000e+00, float %tmp2, float 5.000000e-01) #2
+  %tmp14 = call nsz float @llvm.floor.f32(float %tmp13) #2
+  %tmp15 = fptosi float %tmp14 to i32
+  %tmp16 = icmp eq i32 %tmp15, 0
+  br i1 %tmp16, label %endif06, label %if04
+
+if04:                                             ; preds = %main_body
+  %tmp17 = fadd nsz float %tmp12, -5.000000e-01
+  %tmp18 = fneg nsz float %tmp17
+  %tmp19 = fmul nsz float 0.000000e+00, %tmp18
+  %tmp20 = call nsz float @llvm.fmuladd.f32(float 0.000000e+00, float 0.000000e+00, float %tmp19) #2
+  %tmp21 = fadd nsz float %tmp20, 5.000000e-01
+  %tmp22 = fadd nsz float %tmp21, 0.000000e+00
+  %tmp23 = fmul nsz float %tmp22, 0.000000e+00
+  %tmp24 = call nsz <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float %tmp23, float undef, <8 x i32> undef, <4 x i32> undef, i1 false, i32 0, i32 0) #4
+  %tmp25 = extractelement <4 x float> %tmp24, i32 3
+  %tmp26 = fsub nsz float 1.000000e+00, %tmp25
+  %tmp27 = call nsz float @llvm.fmuladd.f32(float undef, float %tmp26, float undef) #2
+  unreachable
+
+endif06:                                          ; preds = %main_body
+  ret void
+}
+
+; Function Attrs: nounwind readonly
+declare <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 immarg, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1
+
+; Function Attrs: nounwind readnone speculatable willreturn
+declare float @llvm.floor.f32(float) #3
+
+; Function Attrs: nounwind readnone speculatable willreturn
+declare float @llvm.fmuladd.f32(float, float, float) #3
+
+attributes #0 = { "no-signed-zeros-fp-math"="true" }
+attributes #1 = { nounwind readonly }
+attributes #2 = { nounwind readnone }
+attributes #3 = { nounwind readnone speculatable willreturn }
+attributes #4 = { convergent nounwind readnone }