diff --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td --- a/llvm/lib/Target/PowerPC/PPC.td +++ b/llvm/lib/Target/PowerPC/PPC.td @@ -22,35 +22,35 @@ // CPU Directives // //===----------------------------------------------------------------------===// -def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">; -def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">; -def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">; -def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">; -def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">; -def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">; -def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">; -def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">; -def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">; -def Directive32 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">; -def Directive64 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">; -def DirectiveA2 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">; -def DirectiveE500 : SubtargetFeature<"", "DarwinDirective", +def Directive440 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_440", "">; +def Directive601 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_601", "">; +def Directive602 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_602", "">; +def Directive603 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">; +def Directive604 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">; +def Directive620 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">; +def Directive7400: SubtargetFeature<"", "CPUDirective", "PPC::DIR_7400", "">; +def Directive750 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_750", "">; +def Directive970 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_970", "">; +def Directive32 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_32", "">; +def Directive64 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_64", "">; +def DirectiveA2 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_A2", "">; +def DirectiveE500 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_E500", "">; -def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective", +def DirectiveE500mc : SubtargetFeature<"", "CPUDirective", "PPC::DIR_E500mc", "">; -def DirectiveE5500 : SubtargetFeature<"", "DarwinDirective", +def DirectiveE5500 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_E5500", "">; -def DirectivePwr3: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR3", "">; -def DirectivePwr4: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR4", "">; -def DirectivePwr5: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5", "">; +def DirectivePwr3: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR3", "">; +def DirectivePwr4: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR4", "">; +def DirectivePwr5: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5", "">; def DirectivePwr5x - : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5X", "">; -def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">; + : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5X", "">; +def DirectivePwr6: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6", "">; def DirectivePwr6x - : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6X", "">; -def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">; -def DirectivePwr8: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR8", "">; -def DirectivePwr9: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR9", "">; + : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6X", "">; +def DirectivePwr7: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR7", "">; +def DirectivePwr8: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR8", "">; +def DirectivePwr9: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR9", "">; def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true", "Enable 64-bit instructions">; diff --git a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp --- a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp +++ b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp @@ -1611,8 +1611,8 @@ unsigned Directive = PPC::DIR_NONE; for (const Function &F : M) { const PPCSubtarget &STI = TM.getSubtarget(F); - unsigned FDir = STI.getDarwinDirective(); - Directive = Directive > FDir ? FDir : STI.getDarwinDirective(); + unsigned FDir = STI.getCPUDirective(); + Directive = Directive > FDir ? FDir : STI.getCPUDirective(); if (STI.hasMFOCRF() && Directive < PPC::DIR_970) Directive = PPC::DIR_970; if (STI.hasAltivec() && Directive < PPC::DIR_7400) diff --git a/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp b/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp --- a/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp +++ b/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp @@ -158,7 +158,7 @@ // new group. if (isLoadAfterStore(SU) && CurSlots < 6) { unsigned Directive = - DAG->MF.getSubtarget().getDarwinDirective(); + DAG->MF.getSubtarget().getCPUDirective(); // If we're using a special group-terminating nop, then we need only one. // FIXME: the same for P9 as previous gen until POWER9 scheduling is ready if (Directive == PPC::DIR_PWR6 || Directive == PPC::DIR_PWR7 || @@ -218,7 +218,7 @@ void PPCDispatchGroupSBHazardRecognizer::EmitNoop() { unsigned Directive = - DAG->MF.getSubtarget().getDarwinDirective(); + DAG->MF.getSubtarget().getCPUDirective(); // If the group has now filled all of its slots, or if we're using a special // group-terminating nop, the group is complete. // FIXME: the same for P9 as previous gen until POWER9 scheduling is ready diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -1201,7 +1201,7 @@ if (Subtarget.isDarwin()) setPrefFunctionAlignment(Align(16)); - switch (Subtarget.getDarwinDirective()) { + switch (Subtarget.getCPUDirective()) { default: break; case PPC::DIR_970: case PPC::DIR_A2: @@ -1230,15 +1230,15 @@ // The Freescale cores do better with aggressive inlining of memcpy and // friends. GCC uses same threshold of 128 bytes (= 32 word stores). - if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc || - Subtarget.getDarwinDirective() == PPC::DIR_E5500) { + if (Subtarget.getCPUDirective() == PPC::DIR_E500mc || + Subtarget.getCPUDirective() == PPC::DIR_E5500) { MaxStoresPerMemset = 32; MaxStoresPerMemsetOptSize = 16; MaxStoresPerMemcpy = 32; MaxStoresPerMemcpyOptSize = 8; MaxStoresPerMemmove = 32; MaxStoresPerMemmoveOptSize = 8; - } else if (Subtarget.getDarwinDirective() == PPC::DIR_A2) { + } else if (Subtarget.getCPUDirective() == PPC::DIR_A2) { // The A2 also benefits from (very) aggressive inlining of memcpy and // friends. The overhead of a the function call, even when warm, can be // over one hundred cycles. @@ -11717,7 +11717,7 @@ // Combine multiple FDIVs with the same divisor into multiple FMULs by the // reciprocal if there are two or more FDIVs (for embedded cores with only // one FP pipeline) for three or more FDIVs (for generic OOO cores). - switch (Subtarget.getDarwinDirective()) { + switch (Subtarget.getCPUDirective()) { default: return 3; case PPC::DIR_440: @@ -14190,7 +14190,7 @@ } Align PPCTargetLowering::getPrefLoopAlignment(MachineLoop *ML) const { - switch (Subtarget.getDarwinDirective()) { + switch (Subtarget.getCPUDirective()) { default: break; case PPC::DIR_970: case PPC::DIR_PWR4: @@ -15369,7 +15369,7 @@ return SDValue(); auto IsProfitable = [this](bool IsNeg, bool IsAddOne, EVT VT) -> bool { - switch (this->Subtarget.getDarwinDirective()) { + switch (this->Subtarget.getCPUDirective()) { default: // TODO: enhance the condition for subtarget before pwr8 return false; diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -108,7 +108,7 @@ PPCInstrInfo::CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const { unsigned Directive = - static_cast(STI)->getDarwinDirective(); + static_cast(STI)->getCPUDirective(); if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 || Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) { const InstrItineraryData *II = @@ -125,7 +125,7 @@ PPCInstrInfo::CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const { unsigned Directive = - DAG->MF.getSubtarget().getDarwinDirective(); + DAG->MF.getSubtarget().getCPUDirective(); // FIXME: Leaving this as-is until we have POWER9 scheduling info if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8) @@ -202,7 +202,7 @@ // On some cores, there is an additional delay between writing to a condition // register, and using it from a branch. - unsigned Directive = Subtarget.getDarwinDirective(); + unsigned Directive = Subtarget.getCPUDirective(); switch (Directive) { default: break; case PPC::DIR_7400: @@ -469,7 +469,7 @@ MachineBasicBlock::iterator MI) const { // This function is used for scheduling, and the nop wanted here is the type // that terminates dispatch groups on the POWER cores. - unsigned Directive = Subtarget.getDarwinDirective(); + unsigned Directive = Subtarget.getCPUDirective(); unsigned Opcode; switch (Directive) { default: Opcode = PPC::NOP; break; diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.h b/llvm/lib/Target/PowerPC/PPCSubtarget.h --- a/llvm/lib/Target/PowerPC/PPCSubtarget.h +++ b/llvm/lib/Target/PowerPC/PPCSubtarget.h @@ -84,7 +84,7 @@ InstrItineraryData InstrItins; /// Which cpu directive was used. - unsigned DarwinDirective; + unsigned CPUDirective; /// Used by the ISel to turn in optimizations for POWER4-derived architectures bool HasMFOCRF; @@ -169,8 +169,11 @@ Align getStackAlignment() const { return StackAlignment; } /// getDarwinDirective - Returns the -m directive specified for the cpu. + unsigned getDarwinDirective() const { return CPUDirective; } + + /// getCPUDirective - Returns the -m directive specified for the cpu. /// - unsigned getDarwinDirective() const { return DarwinDirective; } + unsigned getCPUDirective() const { return CPUDirective; } /// getInstrItins - Return the instruction itineraries based on subtarget /// selection. diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp --- a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp +++ b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp @@ -61,7 +61,7 @@ void PPCSubtarget::initializeEnvironment() { StackAlignment = Align(16); - DarwinDirective = PPC::DIR_NONE; + CPUDirective = PPC::DIR_NONE; HasMFOCRF = false; Has64BitSupport = false; Use64BitRegs = false; @@ -190,7 +190,7 @@ bool PPCSubtarget::enableMachineScheduler() const { return true; } bool PPCSubtarget::enableMachinePipeliner() const { - return (DarwinDirective == PPC::DIR_PWR9) && EnableMachinePipeliner; + return (CPUDirective == PPC::DIR_PWR9) && EnableMachinePipeliner; } bool PPCSubtarget::useDFAforSMS() const { return false; } diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp --- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp @@ -554,7 +554,7 @@ void PPCTTIImpl::getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP) { - if (ST->getDarwinDirective() == PPC::DIR_A2) { + if (ST->getCPUDirective() == PPC::DIR_A2) { // The A2 is in-order with a deep pipeline, and concatenation unrolling // helps expose latency-hiding opportunities to the instruction scheduler. UP.Partial = UP.Runtime = true; @@ -580,7 +580,7 @@ // on combining the loads generated for consecutive accesses, and failure to // do so is particularly expensive. This makes it much more likely (compared // to only using concatenation unrolling). - if (ST->getDarwinDirective() == PPC::DIR_A2) + if (ST->getCPUDirective() == PPC::DIR_A2) return true; return LoopHasReductions; @@ -650,7 +650,7 @@ return CacheLineSize; // On P7, P8 or P9 we have a cache line size of 128. - unsigned Directive = ST->getDarwinDirective(); + unsigned Directive = ST->getCPUDirective(); if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 || Directive == PPC::DIR_PWR9) return 128; @@ -666,7 +666,7 @@ } unsigned PPCTTIImpl::getMaxInterleaveFactor(unsigned VF) { - unsigned Directive = ST->getDarwinDirective(); + unsigned Directive = ST->getCPUDirective(); // The 440 has no SIMD support, but floating-point instructions // have a 5-cycle latency, so unroll by 5x for latency hiding. if (Directive == PPC::DIR_440)