diff --git a/llvm/lib/CodeGen/MIRNamerPass.cpp b/llvm/lib/CodeGen/MIRNamerPass.cpp
--- a/llvm/lib/CodeGen/MIRNamerPass.cpp
+++ b/llvm/lib/CodeGen/MIRNamerPass.cpp
@@ -56,9 +56,10 @@
 
     NamedVRegCursor NVC(MF.getRegInfo());
 
+    unsigned BBNumber = 0;
     ReversePostOrderTraversal<MachineBasicBlock *> RPOT(&*MF.begin());
     for (auto &MBB : RPOT)
-      Changed |= NVC.renameVRegs(MBB);
+      Changed |= NVC.renameVRegs(MBB, BBNumber++);
 
     return Changed;
   }
diff --git a/llvm/lib/CodeGen/MIRVRegNamerUtils.h b/llvm/lib/CodeGen/MIRVRegNamerUtils.h
--- a/llvm/lib/CodeGen/MIRVRegNamerUtils.h
+++ b/llvm/lib/CodeGen/MIRVRegNamerUtils.h
@@ -53,6 +53,8 @@
   /// RenamedInOtherBB - VRegs that we already renamed: ie breadcrumbs.
   std::vector<Register> RenamedInOtherBB;
 
+  unsigned CurrentBBNumber = 0;
+
 public:
   NamedVRegCursor() = delete;
   /// 1000 for the SkipGapSize was a good heuristic at the time of the writing
@@ -77,13 +79,18 @@
   /// take its place.
   unsigned createVirtualRegister(unsigned VReg);
 
+  unsigned createVirtualRegisterWithName(unsigned VReg,
+                                         const std::string &Name);
+
   /// renameVRegs - For a given MachineBasicBlock, scan for side-effecting
   /// instructions, walk the def-use from each side-effecting root (in sorted
   /// root order) and rename the encountered vregs in the def-use graph in a
   /// canonical ordering. This method maintains book keeping for which vregs
   /// were already renamed in RenamedInOtherBB.
   // @return changed
-  bool renameVRegs(MachineBasicBlock *MBB);
+  bool renameVRegs(MachineBasicBlock *MBB, unsigned BBNum = 0);
+
+  unsigned getCurrentBBNumber() const { return CurrentBBNumber; }
 };
 
 } // namespace llvm
diff --git a/llvm/lib/CodeGen/MIRVRegNamerUtils.cpp b/llvm/lib/CodeGen/MIRVRegNamerUtils.cpp
--- a/llvm/lib/CodeGen/MIRVRegNamerUtils.cpp
+++ b/llvm/lib/CodeGen/MIRVRegNamerUtils.cpp
@@ -8,6 +8,7 @@
 
 #include "MIRVRegNamerUtils.h"
 #include "llvm/Support/Debug.h"
+#include <sstream>
 
 using namespace llvm;
 
@@ -24,16 +25,20 @@
 class TypedVReg {
   VRType Type;
   Register Reg;
+  std::string Token;
 
 public:
-  TypedVReg(Register Reg) : Type(RSE_Reg), Reg(Reg) {}
-  TypedVReg(VRType Type) : Type(Type), Reg(~0U) {
+  TypedVReg(Register Reg, std::string Token = "")
+      : Type(RSE_Reg), Reg(Reg), Token(Token) {}
+  TypedVReg(VRType Type, std::string Token = "")
+      : Type(Type), Reg(~0U), Token(Token) {
     assert(Type != RSE_Reg && "Expected a non-Register Type.");
   }
 
   bool isReg() const { return Type == RSE_Reg; }
   bool isFrameIndex() const { return Type == RSE_FrameIndex; }
   bool isCandidate() const { return Type == RSE_NewCandidate; }
+  const std::string &getToken() const { return Token; }
 
   VRType getType() const { return Type; }
   Register getReg() const {
@@ -78,6 +83,27 @@
   return Candidates;
 }
 
+std::string getInstructionOpcodeStr(MachineInstr &I) {
+  std::string S;
+  raw_string_ostream OS(S);
+  I.print(OS);
+  OS.flush();
+
+  // Trim the assignment, or start from the begining in the case of a store.
+  size_t i = S.find("=");
+  if (i == std::string::npos) {
+    i = S.find(" ");
+    S = S.substr(0, i);
+    return S;
+  }
+  S = (i == std::string::npos) ? S : S.substr(i);
+  i = S.find(" ");
+  S = S.substr(i + 1);
+  i = S.find(" ");
+  S = S.substr(0, i - 1);
+  return S;
+}
+
 void doCandidateWalk(std::vector<TypedVReg> &VRegs,
                      std::queue<TypedVReg> &RegQueue,
                      std::vector<MachineInstr *> &VisitedMIs,
@@ -93,7 +119,7 @@
 
     if (TReg.isFrameIndex()) {
       LLVM_DEBUG(dbgs() << "Popping frame index.\n";);
-      VRegs.push_back(TypedVReg(RSE_FrameIndex));
+      VRegs.push_back(TypedVReg(RSE_FrameIndex, TReg.getToken()));
       continue;
     }
 
@@ -110,11 +136,24 @@
       if (!llvm::any_of(VRegs, [&](const TypedVReg &TR) {
             return TR.isReg() && TR.getReg() == Reg;
           })) {
-        VRegs.push_back(TypedVReg(Reg));
+
+        MachineInstr *Def = nullptr;
+        for (auto RI = MRI.def_begin(Reg), RE = MRI.def_end(); RI != RE; ++RI) {
+          Def = RI->getParent();
+          break;
+        }
+
+        VRegs.push_back(
+            TypedVReg(Reg, TReg.getToken() + getInstructionOpcodeStr(*Def)));
       }
     } else {
       LLVM_DEBUG(dbgs() << "Popping physreg.\n";);
-      VRegs.push_back(TypedVReg(Reg));
+      std::string S;
+      raw_string_ostream OS(S);
+      printReg(Reg, MRI.getTargetRegisterInfo()).Print(OS);
+      OS.flush();
+      llvm::errs() << "WTF2: " << OS.str() << "\n";
+      VRegs.push_back(TypedVReg(Reg, TReg.getToken() + S));
       continue;
     }
 
@@ -142,12 +181,12 @@
         MachineOperand &MO = Def->getOperand(I);
         if (MO.isFI()) {
           LLVM_DEBUG(dbgs() << "Pushing frame index.\n";);
-          RegQueue.push(TypedVReg(RSE_FrameIndex));
+          RegQueue.push(TypedVReg(RSE_FrameIndex, TReg.getToken()));
         }
 
         if (!MO.isReg())
           continue;
-        RegQueue.push(TypedVReg(MO.getReg()));
+        RegQueue.push(TypedVReg(MO.getReg(), TReg.getToken()));
       }
     }
   }
@@ -198,7 +237,8 @@
       continue;
     }
 
-    auto Rename = NVC.createVirtualRegister(Reg);
+    auto Rename = NVC.createVirtualRegisterWithName(Reg, vreg.getToken());
+    // auto Rename = NVC.createVirtualRegister(Reg);
 
     if (VRegRenameMap.find(Reg) == VRegRenameMap.end()) {
       LLVM_DEBUG(dbgs() << "Mapping vreg ";);
@@ -263,7 +303,13 @@
 
   std::vector<TypedVReg> VRegs;
   for (auto candidate : Candidates) {
-    VRegs.push_back(TypedVReg(RSE_NewCandidate));
+    std::stringstream sstr;
+    sstr << "BB";
+    sstr << NVC.getCurrentBBNumber();
+    sstr << "_";
+    sstr << getInstructionOpcodeStr(*candidate);
+    std::string TokenPrefix = sstr.str();
+    VRegs.push_back(TypedVReg(RSE_NewCandidate, TokenPrefix));
 
     std::queue<TypedVReg> RegQueue;
 
@@ -280,7 +326,7 @@
         continue;
 
       LLVM_DEBUG(dbgs() << "Enqueue register"; MO.dump(); dbgs() << "\n";);
-      RegQueue.push(TypedVReg(MO.getReg()));
+      RegQueue.push(TypedVReg(MO.getReg(), TokenPrefix));
     }
 
     // Here we walk the root candidates. We start from the 0th operand because
@@ -298,8 +344,8 @@
 
       LLVM_DEBUG(dbgs() << "Enqueue Reg/FI"; MO.dump(); dbgs() << "\n";);
 
-      RegQueue.push(MO.isReg() ? TypedVReg(MO.getReg())
-                               : TypedVReg(RSE_FrameIndex));
+      RegQueue.push(MO.isReg() ? TypedVReg(MO.getReg(), TokenPrefix)
+                               : TypedVReg(RSE_FrameIndex, TokenPrefix));
     }
 
     doCandidateWalk(VRegs, RegQueue, VisitedMIs, MBB);
@@ -343,6 +389,20 @@
   return MRI.createGenericVirtualRegister(MRI.getType(VReg), OS.str());
 }
 
-bool NamedVRegCursor::renameVRegs(MachineBasicBlock *MBB) {
+unsigned
+NamedVRegCursor::createVirtualRegisterWithName(unsigned VReg,
+                                               const std::string &Name) {
+  static unsigned i = 0;
+  std::stringstream sstr;
+  sstr << tolower(Name.c_str());
+  sstr << i++;
+  llvm::errs() << "[" << sstr.str() << "]\n";
+  if (auto RC = MRI.getRegClassOrNull(VReg))
+    return MRI.createVirtualRegister(RC, sstr.str());
+  return MRI.createGenericVirtualRegister(MRI.getType(VReg), sstr.str());
+}
+
+bool NamedVRegCursor::renameVRegs(MachineBasicBlock *MBB, unsigned BBNum) {
+  CurrentBBNumber = BBNum;
   return ::renameVRegs(MBB, RenamedInOtherBB, *this);
 }