Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp =================================================================== --- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -112,6 +112,9 @@ // 'add' is an overloaded mnemonic. bool checkPseudoAddTPRel(MCInst &Inst, OperandVector &Operands); + // Check instruction constraints. + bool validateInstruction(MCInst &Inst, OperandVector &Operands); + /// Helper for processing MC instructions that have been successfully matched /// by MatchAndEmitInstruction. Modifications to the emitted instructions, /// like the expansion of pseudo instructions (e.g., "li"), can be performed @@ -133,6 +136,8 @@ OperandMatchResultTy parseBareSymbol(OperandVector &Operands); OperandMatchResultTy parseCallSymbol(OperandVector &Operands); OperandMatchResultTy parseJALOffset(OperandVector &Operands); + OperandMatchResultTy parseVTypeIAsmOperand(OperandVector &Operands); + OperandMatchResultTy parseMaskRegister(OperandVector &Operands); bool parseOperand(OperandVector &Operands, StringRef Mnemonic); @@ -199,7 +204,8 @@ Token, Register, Immediate, - SystemRegister + SystemRegister, + VType, } Kind; bool IsRV64; @@ -220,12 +226,37 @@ // e.g.: read/write or user/supervisor/machine privileges. }; + enum class VSEW { + SEW_8 = 0, + SEW_16, + SEW_32, + SEW_64, + SEW_128, + SEW_256, + SEW_512, + SEW_1024, + }; + + enum class VLMUL { + LMUL_1 = 0, + LMUL_2, + LMUL_4, + LMUL_8 + }; + + struct VType { + VSEW sew; + VLMUL lmul; + unsigned Encoding; + }; + SMLoc StartLoc, EndLoc; union { StringRef Tok; RegOp Reg; ImmOp Imm; struct SysRegOp SysReg; + struct VType VType; }; RISCVOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} @@ -249,6 +280,9 @@ case KindTy::SystemRegister: SysReg = o.SysReg; break; + case KindTy::VType: + VType = o.VType; + break; } } @@ -257,6 +291,7 @@ bool isImm() const override { return Kind == KindTy::Immediate; } bool isMem() const override { return false; } bool isSystemRegister() const { return Kind == KindTy::SystemRegister; } + bool isVType() const { return Kind == KindTy::VType; } static bool evaluateConstantImm(const MCExpr *Expr, int64_t &Imm, RISCVMCExpr::VariantKind &VK) { @@ -325,6 +360,8 @@ bool isCSRSystemRegister() const { return isSystemRegister(); } + bool isVTypeI() const { return isVType(); } + /// Return true if the operand is a valid for the fence instruction e.g. /// ('iorw'). bool isFenceArg() const { @@ -421,6 +458,16 @@ VK == RISCVMCExpr::VK_RISCV_None; } + bool isSImm5() const { + if (!isImm()) + return false; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + int64_t Imm; + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); + return IsConstantImm && isInt<5>(Imm) && + VK == RISCVMCExpr::VK_RISCV_None; + } + bool isSImm6() const { if (!isImm()) return false; @@ -613,6 +660,53 @@ return Tok; } + static StringRef getSEWStr(VSEW sew) { + switch (sew) { + default: + return "e8"; + case VSEW::SEW_8: + return "e8"; + case VSEW::SEW_16: + return "e16"; + case VSEW::SEW_32: + return "e32"; + case VSEW::SEW_64: + return "e64"; + case VSEW::SEW_128: + return "e128"; + case VSEW::SEW_256: + return "e256"; + case VSEW::SEW_512: + return "e512"; + case VSEW::SEW_1024: + return "e1024"; + } + } + + static StringRef getLMULStr(VLMUL lmul) { + switch (lmul) { + default: + return "m1"; + case VLMUL::LMUL_1: + return "m1"; + case VLMUL::LMUL_2: + return "m2"; + case VLMUL::LMUL_4: + return "m4"; + case VLMUL::LMUL_8: + return "m8"; + } + } + + StringRef getVType(SmallVectorImpl &Out) const { + assert(Kind == KindTy::VType && "Invalid access!"); + Twine vtype(getSEWStr(VType.sew)); + vtype.concat(Twine(",")); + vtype.concat(Twine(getLMULStr(VType.lmul))); + + return vtype.toStringRef(Out); + } + void print(raw_ostream &OS) const override { switch (Kind) { case KindTy::Immediate: @@ -628,6 +722,10 @@ case KindTy::SystemRegister: OS << "'; break; + case KindTy::VType: + SmallVector VTypeBuf; + OS << "'; + break; } } @@ -672,6 +770,18 @@ return Op; } + static std::unique_ptr + createVType(unsigned sew, unsigned lmul, SMLoc S, unsigned Encoding, + bool IsRV64) { + auto Op = std::make_unique(KindTy::VType); + Op->VType.sew = static_cast(sew); + Op->VType.lmul = static_cast(lmul); + Op->VType.Encoding = Encoding; + Op->StartLoc = S; + Op->IsRV64 = IsRV64; + return Op; + } + void addExpr(MCInst &Inst, const MCExpr *Expr) const { assert(Expr && "Expr shouldn't be null!"); int64_t Imm = 0; @@ -719,6 +829,11 @@ Inst.addOperand(MCOperand::createImm(SysReg.Encoding)); } + void addVTypeIOperands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + Inst.addOperand(MCOperand::createImm(VType.Encoding)); + } + // Returns the rounding mode represented by this RISCVOperand. Should only // be called after checking isFRMArg. RISCVFPRndMode::RoundingMode getRoundingMode() const { @@ -788,6 +903,8 @@ default: break; case Match_Success: + if (validateInstruction(Inst, Operands)) + return true; return processInstruction(Inst, IDLoc, Operands, Out); case Match_MissingFeature: return Error(IDLoc, "instruction use requires an option to be enabled"); @@ -937,6 +1054,10 @@ SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc(); return Error(ErrorLoc, "operand must be a symbol with %tprel_add modifier"); } + case Match_InvalidVTypeIAsmOperand: { + SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc(); + return Error(ErrorLoc, "operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8]"); + } } llvm_unreachable("Unknown match type detected!"); @@ -1257,6 +1378,68 @@ return parseImmediate(Operands); } +OperandMatchResultTy RISCVAsmParser::parseVTypeIAsmOperand(OperandVector &Operands) { + SMLoc S = getLoc(); + if (getLexer().getKind() != AsmToken::Identifier) + return MatchOperand_NoMatch; + + // Parse "e8,m1" + StringRef Name = getLexer().getTok().getIdentifier(); + if (!Name.consume_front("e")) + return MatchOperand_NoMatch; + APInt sew(16, Name, 10); + if (sew != 8 && sew != 16 && sew != 32 && sew != 64 && + sew != 128 && sew != 256 && sew != 512 && sew != 1024) + return MatchOperand_NoMatch; + getLexer().Lex(); + + if (!getLexer().is(AsmToken::Comma)) + return MatchOperand_NoMatch; + getLexer().Lex(); + + Name = getLexer().getTok().getIdentifier(); + if (!Name.consume_front("m")) + return MatchOperand_NoMatch; + APInt lmul(16, Name, 10); + if (lmul != 1 && lmul != 2 && lmul != 4 && lmul != 8) + return MatchOperand_NoMatch; + getLexer().Lex(); + + if (getLexer().getKind() != AsmToken::EndOfStatement) + return MatchOperand_NoMatch; + + unsigned Encoding = 0; + sew.ashrInPlace(3); + Encoding = (sew.logBase2() << 2) | lmul.logBase2(); + Operands.push_back(RISCVOperand::createVType(sew.logBase2(), lmul.logBase2(), + S, Encoding, isRV64())); + + return MatchOperand_Success; +} + +OperandMatchResultTy RISCVAsmParser::parseMaskRegister(OperandVector &Operands) { + switch (getLexer().getKind()) { + default: + return MatchOperand_NoMatch; + case AsmToken::Identifier: + StringRef Name = getLexer().getTok().getIdentifier(); + if (!Name.consume_back(".t")) + return MatchOperand_NoMatch; + Register RegNo; + matchRegisterNameHelper(isRV32E(), RegNo, Name); + + if (RegNo == RISCV::NoRegister) + return MatchOperand_NoMatch; + SMLoc S = getLoc(); + SMLoc E = SMLoc::getFromPointer(S.getPointer() - 1); + getLexer().Lex(); + Operands.push_back(RISCVOperand::createReg(RegNo, S, E, isRV64())); + } + + return MatchOperand_Success; +} + + OperandMatchResultTy RISCVAsmParser::parseMemOpBaseReg(OperandVector &Operands) { if (getLexer().isNot(AsmToken::LParen)) { @@ -1741,6 +1924,216 @@ return false; } +bool RISCVAsmParser::validateInstruction(MCInst &Inst, + OperandVector &Operands) { + SMLoc Loc = Operands[0]->getStartLoc(); + const unsigned Opcode = Inst.getOpcode(); + switch (Opcode) { + case RISCV::VWADDU_VV_T: + case RISCV::VWADDU_VX_T: + case RISCV::VWSUBU_VV_T: + case RISCV::VWSUBU_VX_T: + case RISCV::VWADD_VV_T: + case RISCV::VWADD_VX_T: + case RISCV::VWSUB_VV_T: + case RISCV::VWSUB_VX_T: + case RISCV::VWMUL_VV_T: + case RISCV::VWMUL_VX_T: + case RISCV::VWMULU_VV_T: + case RISCV::VWMULU_VX_T: + case RISCV::VWMULSU_VV_T: + case RISCV::VWMULSU_VX_T: + case RISCV::VWMACCU_VV_T: + case RISCV::VWMACCU_VX_T: + case RISCV::VWMACC_VV_T: + case RISCV::VWMACC_VX_T: + case RISCV::VWMACCSU_VV_T: + case RISCV::VWMACCSU_VX_T: + case RISCV::VWMACCUS_VX_T: + case RISCV::VWSMACCU_VV_T: + case RISCV::VWSMACCU_VX_T: + case RISCV::VWSMACC_VV_T: + case RISCV::VWSMACC_VX_T: + case RISCV::VWSMACCSU_VV_T: + case RISCV::VWSMACCSU_VX_T: + case RISCV::VWSMACCUS_VX_T: + case RISCV::VFWADD_VV_T: + case RISCV::VFWADD_VF_T: + case RISCV::VFWSUB_VV_T: + case RISCV::VFWSUB_VF_T: + case RISCV::VFWMUL_VV_T: + case RISCV::VFWMUL_VF_T: + case RISCV::VFWMACC_VV_T: + case RISCV::VFWMACC_VF_T: + case RISCV::VFWNMACC_VV_T: + case RISCV::VFWNMACC_VF_T: + case RISCV::VFWMSAC_VV_T: + case RISCV::VFWMSAC_VF_T: + case RISCV::VFWNMSAC_VV_T: + case RISCV::VFWNMSAC_VF_T: + case RISCV::VRGATHER_VV_T: + case RISCV::VRGATHER_VX_T: + { + unsigned DestReg = Inst.getOperand(0).getReg(); + unsigned MaskReg = Inst.getOperand(3).getReg(); + + if (DestReg == MaskReg) + return Error(Loc, "The destination vector register group cannot overlap" + " the mask register of a different element width."); + } // Fall through. + case RISCV::VWADDU_VV: + case RISCV::VWSUBU_VV: + case RISCV::VWADD_VV: + case RISCV::VWSUB_VV: + case RISCV::VWMUL_VV: + case RISCV::VWMULU_VV: + case RISCV::VWMULSU_VV: + case RISCV::VWMACCU_VV: + case RISCV::VWMACC_VV: + case RISCV::VWMACCSU_VV: + case RISCV::VWSMACCU_VV: + case RISCV::VWSMACC_VV: + case RISCV::VWSMACCSU_VV: + case RISCV::VFWADD_VV: + case RISCV::VFWSUB_VV: + case RISCV::VFWMUL_VV: + case RISCV::VFWMACC_VV: + case RISCV::VFWNMACC_VV: + case RISCV::VFWMSAC_VV: + case RISCV::VFWNMSAC_VV: + case RISCV::VRGATHER_VV: + case RISCV::VCOMPRESS_VM: + { + unsigned DestReg = Inst.getOperand(0).getReg(); + unsigned Src1Reg = Inst.getOperand(2).getReg(); + + if (DestReg == Src1Reg) + return Error(Loc, "The destination vector register group cannot overlap" + " a source vector register group of a different element width."); + } // Fall through. + case RISCV::VWADDU_VX: + case RISCV::VWSUBU_VX: + case RISCV::VWADD_VX: + case RISCV::VWSUB_VX: + case RISCV::VWMUL_VX: + case RISCV::VWMULU_VX: + case RISCV::VWMULSU_VX: + case RISCV::VWMACCU_VX: + case RISCV::VWMACC_VX: + case RISCV::VWMACCSU_VX: + case RISCV::VWMACCUS_VX: + case RISCV::VWSMACCU_VX: + case RISCV::VWSMACC_VX: + case RISCV::VWSMACCSU_VX: + case RISCV::VWSMACCUS_VX: + case RISCV::VFWADD_VF: + case RISCV::VFWSUB_VF: + case RISCV::VFWMUL_VF: + case RISCV::VFWMACC_VF: + case RISCV::VFWNMACC_VF: + case RISCV::VFWMSAC_VF: + case RISCV::VFWNMSAC_VF: + case RISCV::VRGATHER_VX: + case RISCV::VRGATHER_VI: + { + unsigned DestReg = Inst.getOperand(0).getReg(); + unsigned Src2Reg = Inst.getOperand(1).getReg(); + + if (DestReg == Src2Reg) + return Error(Loc, "The destination vector register group cannot overlap" + " a source vector register group of a different element width."); + break; + } + case RISCV::VRGATHER_VI_T: + { + unsigned DestReg = Inst.getOperand(0).getReg(); + unsigned Src2Reg = Inst.getOperand(1).getReg(); + unsigned MaskReg = Inst.getOperand(3).getReg(); + + if (DestReg == Src2Reg) + return Error(Loc, "The destination vector register group cannot overlap" + " a source vector register group of a different element width."); + if (DestReg == MaskReg) + return Error(Loc, "The destination vector register group cannot overlap" + " the mask register of a different element width."); + break; + } + case RISCV::VFWCVT_XU_F_V_T: + case RISCV::VFWCVT_X_F_V_T: + case RISCV::VFWCVT_F_XU_V_T: + case RISCV::VFWCVT_F_X_V_T: + case RISCV::VFWCVT_F_F_V_T: + case RISCV::VIOTA_M_T: + { + unsigned DestReg = Inst.getOperand(0).getReg(); + unsigned MaskReg = Inst.getOperand(2).getReg(); + + if (DestReg == MaskReg) + return Error(Loc, "The destination vector register group cannot overlap" + " the mask register of a different element width."); + } // Fall through. + case RISCV::VFWCVT_XU_F_V: + case RISCV::VFWCVT_X_F_V: + case RISCV::VFWCVT_F_XU_V: + case RISCV::VFWCVT_F_X_V: + case RISCV::VFWCVT_F_F_V: + case RISCV::VIOTA_M: + case RISCV::VNSRL_WV: + case RISCV::VNSRL_WX: + case RISCV::VNSRL_WI: + case RISCV::VNSRA_WV: + case RISCV::VNSRA_WX: + case RISCV::VNSRA_WI: + case RISCV::VNCLIPU_WV: + case RISCV::VNCLIPU_WX: + case RISCV::VNCLIPU_WI: + case RISCV::VNCLIP_WV: + case RISCV::VNCLIP_WX: + case RISCV::VNCLIP_WI: + case RISCV::VFNCVT_XU_F_W: + case RISCV::VFNCVT_X_F_W: + case RISCV::VFNCVT_F_XU_W: + case RISCV::VFNCVT_F_X_W: + case RISCV::VFNCVT_F_F_W: + case RISCV::VFNCVT_ROD_F_F_W: + { + unsigned DestReg = Inst.getOperand(0).getReg(); + unsigned Src2Reg = Inst.getOperand(1).getReg(); + + if (DestReg == Src2Reg) + return Error(Loc, "The destination vector register group cannot overlap" + " a source vector register group of a different element width."); + break; + } + case RISCV::VSLIDEUP_VX_T: + case RISCV::VSLIDEUP_VI_T: + case RISCV::VSLIDE1UP_VX_T: + { + unsigned DestReg = Inst.getOperand(0).getReg(); + unsigned MaskReg = Inst.getOperand(3).getReg(); + + if (DestReg == MaskReg) + return Error(Loc, "The destination vector register group cannot overlap" + " the mask register of a different element width."); + } // Fall through. + case RISCV::VSLIDEUP_VX: + case RISCV::VSLIDEUP_VI: + case RISCV::VSLIDE1UP_VX: + { + unsigned DestReg = Inst.getOperand(0).getReg(); + unsigned Src2Reg = Inst.getOperand(1).getReg(); + + if (DestReg == Src2Reg) + return Error(Loc, "The destination vector register group cannot overlap" + " a source vector register group of a different element width."); + break; + } + default: + return false; + } + return false; +} + bool RISCVAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc, OperandVector &Operands, MCStreamer &Out) { Index: llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp =================================================================== --- llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -18,6 +18,7 @@ #include "llvm/MC/MCDisassembler/MCDisassembler.h" #include "llvm/MC/MCFixedLenDisassembler.h" #include "llvm/MC/MCInst.h" +#include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/Support/Endian.h" @@ -31,10 +32,12 @@ namespace { class RISCVDisassembler : public MCDisassembler { + std::unique_ptr const MCII; public: - RISCVDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) - : MCDisassembler(STI, Ctx) {} + RISCVDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, + MCInstrInfo const *MCII) + : MCDisassembler(STI, Ctx), MCII(MCII) {} DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef Bytes, uint64_t Address, @@ -46,7 +49,7 @@ static MCDisassembler *createRISCVDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx) { - return new RISCVDisassembler(STI, Ctx); + return new RISCVDisassembler(STI, Ctx, T.createMCInstrInfo()); } extern "C" void LLVMInitializeRISCVDisassembler() { @@ -149,6 +152,17 @@ return MCDisassembler::Success; } +static DecodeStatus DecodeVPRRegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { + if (RegNo >= 32) + return MCDisassembler::Fail; + + Register Reg = RISCV::V0 + RegNo; + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} + // Add implied SP operand for instructions *SP compressed instructions. The SP // operand isn't explicitly encoded in the instruction. static void addImplySP(MCInst &Inst, int64_t Address, const void *Decoder) { @@ -312,6 +326,15 @@ return MCDisassembler::Success; } +static void addImplyVMask(MCInst &Inst, uint32_t Insn, + const MCInstrInfo &MCII) { + MCInstrDesc const &Desc = MCII.get(Inst.getOpcode()); + if (Desc.TSFlags & RISCVII::InstVector) { + if ((Insn & (0x1 << 25)) == 0) + Inst.addOperand(MCOperand::createReg(RISCV::V0)); + } +} + DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size, ArrayRef Bytes, uint64_t Address, @@ -331,6 +354,8 @@ Insn = support::endian::read32le(Bytes.data()); LLVM_DEBUG(dbgs() << "Trying RISCV32 table :\n"); Result = decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI); + // Append Vector Mask register if it is a masked instruction. + addImplyVMask(MI, Insn, *MCII); Size = 4; } else { if (Bytes.size() < 2) { Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h =================================================================== --- llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h +++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h @@ -41,6 +41,12 @@ raw_ostream &O); void printAtomicMemOp(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); + void printVTypeI(const MCInst *MI, unsigned OpNo, + const MCSubtargetInfo &STI, + raw_ostream &O); + void printVPRMaskOp(const MCInst *MI, unsigned OpNo, + const MCSubtargetInfo &STI, + raw_ostream &O); // Autogenerated by tblgen. void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI, Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp =================================================================== --- llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp +++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp @@ -149,6 +149,29 @@ return; } +void RISCVInstPrinter::printVTypeI(const MCInst *MI, unsigned OpNo, + const MCSubtargetInfo &STI, + raw_ostream &O) { + unsigned Imm = MI->getOperand(OpNo).getImm(); + unsigned sew = (Imm >> 2) & 0x7; + unsigned lmul = Imm & 0x3; + + lmul = 0x1 << lmul; + sew = 0x1 << (sew + 3); + O << "e" << sew << ",m" << lmul; +} + +void RISCVInstPrinter::printVPRMaskOp(const MCInst *MI, unsigned OpNo, + const MCSubtargetInfo &STI, + raw_ostream &O) { + const MCOperand &MO = MI->getOperand(OpNo); + + assert(MO.isReg() && "printVPRMaskOp can only print register operands"); + printRegName(O, MO.getReg()); + O << ".t"; + return; +} + const char *RISCVInstPrinter::getRegisterName(unsigned RegNo) { return getRegisterName(RegNo, ArchRegNames ? RISCV::NoRegAltName : RISCV::ABIRegAltName); Index: llvm/lib/Target/RISCV/RISCV.td =================================================================== --- llvm/lib/Target/RISCV/RISCV.td +++ llvm/lib/Target/RISCV/RISCV.td @@ -49,6 +49,12 @@ def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">, AssemblerPredicate<"FeatureRVCHints">; +def FeatureStdExtV + : SubtargetFeature<"v", "HasStdExtV", "true", + "'V' (Vector Instructions)">; +def HasStdExtV : Predicate<"Subtarget->hasStdExtV()">, + AssemblerPredicate<"FeatureStdExtV">; + def Feature64Bit : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">; def IsRV64 : Predicate<"Subtarget->is64Bit()">, Index: llvm/lib/Target/RISCV/RISCVInstrFormats.td =================================================================== --- llvm/lib/Target/RISCV/RISCVInstrFormats.td +++ llvm/lib/Target/RISCV/RISCVInstrFormats.td @@ -71,6 +71,7 @@ def OPC_NMSUB : RISCVOpcode<0b1001011>; def OPC_NMADD : RISCVOpcode<0b1001111>; def OPC_OP_FP : RISCVOpcode<0b1010011>; +def OPC_OP_V : RISCVOpcode<0b1010111>; def OPC_BRANCH : RISCVOpcode<0b1100011>; def OPC_JALR : RISCVOpcode<0b1100111>; def OPC_JAL : RISCVOpcode<0b1101111>; @@ -99,6 +100,7 @@ let Pattern = pattern; let TSFlags{4-0} = format.Value; + let TSFlags{5} = 0; // Used by v-ext. } // Pseudo instructions Index: llvm/lib/Target/RISCV/RISCVInstrFormatsV.td =================================================================== --- /dev/null +++ llvm/lib/Target/RISCV/RISCVInstrFormatsV.td @@ -0,0 +1,283 @@ +//===-- RISCVInstrFormatsV.td - RISCV V Instruction Formats --*- tablegen -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file describes the RISC-V V extension instruction formats. +// +//===----------------------------------------------------------------------===// + +class RISCVVFormat val> { + bits<3> Value = val; +} +def OPIVV : RISCVVFormat<0b000>; +def OPFVV : RISCVVFormat<0b001>; +def OPMVV : RISCVVFormat<0b010>; +def OPIVI : RISCVVFormat<0b011>; +def OPIVX : RISCVVFormat<0b100>; +def OPFVF : RISCVVFormat<0b101>; +def OPMVX : RISCVVFormat<0b110>; + +class RISCVMOP val> { + bits<3> Value = val; +} +def MOPLDUnitStrideU : RISCVMOP<0b000>; +def MOPLDStridedU : RISCVMOP<0b010>; +def MOPLDIndexedU : RISCVMOP<0b011>; +def MOPLDUnitStrideS : RISCVMOP<0b100>; +def MOPLDStridedS : RISCVMOP<0b110>; +def MOPLDIndexedS : RISCVMOP<0b111>; + +def MOPSTUnitStride : RISCVMOP<0b000>; +def MOPSTStrided : RISCVMOP<0b010>; +def MOPSTIndexedOrder: RISCVMOP<0b011>; +def MOPSTIndexedUnOrd: RISCVMOP<0b111>; + +class RISCVLSUMOP val> { + bits<5> Value = val; +} +def LUMOPUnitStride : RISCVLSUMOP<0b00000>; +def LUMOPUnitStrideFF: RISCVLSUMOP<0b10000>; +def SUMOPUnitStride : RISCVLSUMOP<0b00000>; + +class RISCVWidth val> { + bits<3> Value = val; +} +def LSWidthVByte : RISCVWidth<0b000>; +def LSWidthVHalf : RISCVWidth<0b101>; +def LSWidthVWord : RISCVWidth<0b110>; +def LSWidthVSEW : RISCVWidth<0b111>; + +class RVInstSetVLi + : RVInst { + bits<5> rs1; + bits<5> rd; + bits<11> vtypei; + + let Inst{31} = 0; + let Inst{30-20} = vtypei; + let Inst{19-15} = rs1; + let Inst{14-12} = 0b111; + let Inst{11-7} = rd; + let Opcode = OPC_OP_V.Value; +} + +class RVInstSetVL + : RVInst { + bits<5> rs2; + bits<5> rs1; + bits<5> rd; + + let Inst{31} = 1; + let Inst{30-25} = 0b000000; + let Inst{24-20} = rs2; + let Inst{19-15} = rs1; + let Inst{14-12} = 0b111; + let Inst{11-7} = rd; + let Opcode = OPC_OP_V.Value; +} + +class RVInstVV funct6, RISCVVFormat opv, bit vm, dag outs, dag ins, + string opcodestr, string argstr> + : RVInst { + bits<5> vs2; + bits<5> vs1; + bits<5> vd; + + let Inst{31-26} = funct6; + let Inst{25} = vm; + let Inst{24-20} = vs2; + let Inst{19-15} = vs1; + let Inst{14-12} = opv.Value; + let Inst{11-7} = vd; + let Opcode = OPC_OP_V.Value; + + let TSFlags{5} = 1; +} + +class RVInstVX funct6, RISCVVFormat opv, bit vm, dag outs, dag ins, + string opcodestr, string argstr> + : RVInst { + bits<5> vs2; + bits<5> rs1; + bits<5> vd; + + let Inst{31-26} = funct6; + let Inst{25} = vm; + let Inst{24-20} = vs2; + let Inst{19-15} = rs1; + let Inst{14-12} = opv.Value; + let Inst{11-7} = vd; + let Opcode = OPC_OP_V.Value; + + let TSFlags{5} = 1; +} + +class RVInstV2 funct6, bits<5> vs2, RISCVVFormat opv, bit vm, dag outs, dag ins, + string opcodestr, string argstr> + : RVInst { + bits<5> rs1; + bits<5> vd; + + let Inst{31-26} = funct6; + let Inst{25} = vm; + let Inst{24-20} = vs2; + let Inst{19-15} = rs1; + let Inst{14-12} = opv.Value; + let Inst{11-7} = vd; + let Opcode = OPC_OP_V.Value; + + let TSFlags{5} = 1; +} + +class RVInstIVI funct6, bit vm, dag outs, dag ins, string opcodestr, + string argstr> + : RVInst { + bits<5> vs2; + bits<5> imm; + bits<5> vd; + + let Inst{31-26} = funct6; + let Inst{25} = vm; + let Inst{24-20} = vs2; + let Inst{19-15} = imm; + let Inst{14-12} = 0b011; + let Inst{11-7} = vd; + let Opcode = OPC_OP_V.Value; + + let TSFlags{5} = 1; +} + +class RVInstV funct6, bits<5> vs1, RISCVVFormat opv, bit vm, dag outs, + dag ins, string opcodestr, string argstr> + : RVInst { + bits<5> vs2; + bits<5> vd; + + let Inst{31-26} = funct6; + let Inst{25} = vm; + let Inst{24-20} = vs2; + let Inst{19-15} = vs1; + let Inst{14-12} = opv.Value; + let Inst{11-7} = vd; + let Opcode = OPC_OP_V.Value; + + let TSFlags{5} = 1; +} + +class RVInstVLU nf, RISCVMOP mop, bit vm, RISCVLSUMOP lumop, + RISCVWidth width, dag outs, dag ins, string opcodestr, + string argstr> + : RVInst { + bits<5> rs1; + bits<5> vd; + + let Inst{31-29} = nf; + let Inst{28-26} = mop.Value; + let Inst{25} = vm; + let Inst{24-20} = lumop.Value; + let Inst{19-15} = rs1; + let Inst{14-12} = width.Value; + let Inst{11-7} = vd; + let Opcode = OPC_LOAD_FP.Value; + + let TSFlags{5} = 1; +} + +class RVInstVLS nf, RISCVMOP mop, bit vm, RISCVWidth width, + dag outs, dag ins, string opcodestr, string argstr> + : RVInst { + bits<5> rs2; + bits<5> rs1; + bits<5> vd; + + let Inst{31-29} = nf; + let Inst{28-26} = mop.Value; + let Inst{25} = vm; + let Inst{24-20} = rs2; + let Inst{19-15} = rs1; + let Inst{14-12} = width.Value; + let Inst{11-7} = vd; + let Opcode = OPC_LOAD_FP.Value; + + let TSFlags{5} = 1; +} + +class RVInstVLX nf, RISCVMOP mop, bit vm, RISCVWidth width, + dag outs, dag ins, string opcodestr, string argstr> + : RVInst { + bits<5> vs2; + bits<5> rs1; + bits<5> vd; + + let Inst{31-29} = nf; + let Inst{28-26} = mop.Value; + let Inst{25} = vm; + let Inst{24-20} = vs2; + let Inst{19-15} = rs1; + let Inst{14-12} = width.Value; + let Inst{11-7} = vd; + let Opcode = OPC_LOAD_FP.Value; + + let TSFlags{5} = 1; +} + +class RVInstVSU nf, RISCVMOP mop, bit vm, RISCVLSUMOP sumop, + RISCVWidth width, dag outs, dag ins, string opcodestr, + string argstr> + : RVInst { + bits<5> rs1; + bits<5> vs3; + + let Inst{31-29} = nf; + let Inst{28-26} = mop.Value; + let Inst{25} = vm; + let Inst{24-20} = sumop.Value; + let Inst{19-15} = rs1; + let Inst{14-12} = width.Value; + let Inst{11-7} = vs3; + let Opcode = OPC_STORE_FP.Value; + + let TSFlags{5} = 1; +} + +class RVInstVSS nf, RISCVMOP mop, bit vm, RISCVWidth width, + dag outs, dag ins, string opcodestr, string argstr> + : RVInst { + bits<5> rs2; + bits<5> rs1; + bits<5> vs3; + + let Inst{31-29} = nf; + let Inst{28-26} = mop.Value; + let Inst{25} = vm; + let Inst{24-20} = rs2; + let Inst{19-15} = rs1; + let Inst{14-12} = width.Value; + let Inst{11-7} = vs3; + let Opcode = OPC_STORE_FP.Value; + + let TSFlags{5} = 1; +} + +class RVInstVSX nf, RISCVMOP mop, bit vm, RISCVWidth width, + dag outs, dag ins, string opcodestr, string argstr> + : RVInst { + bits<5> vs2; + bits<5> rs1; + bits<5> vs3; + + let Inst{31-29} = nf; + let Inst{28-26} = mop.Value; + let Inst{25} = vm; + let Inst{24-20} = vs2; + let Inst{19-15} = rs1; + let Inst{14-12} = width.Value; + let Inst{11-7} = vs3; + let Opcode = OPC_STORE_FP.Value; + + let TSFlags{5} = 1; +} Index: llvm/lib/Target/RISCV/RISCVInstrInfo.td =================================================================== --- llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -1116,3 +1116,4 @@ include "RISCVInstrInfoF.td" include "RISCVInstrInfoD.td" include "RISCVInstrInfoC.td" +include "RISCVInstrInfoV.td" Index: llvm/lib/Target/RISCV/RISCVInstrInfoV.td =================================================================== --- /dev/null +++ llvm/lib/Target/RISCV/RISCVInstrInfoV.td @@ -0,0 +1,869 @@ +//===-- RISCVInstrInfoV.td - RISC-V 'V' instructions -------*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file describes the RISC-V instructions from the standard 'V', +// Vector instruction set extension. +// +//===----------------------------------------------------------------------===// + +include "RISCVInstrFormatsV.td" + +//===----------------------------------------------------------------------===// +// Operand and SDNode transformation definitions. +//===----------------------------------------------------------------------===// + +def VTypeIAsmOperand : AsmOperandClass { + let Name = "VTypeI"; + let ParserMethod = "parseVTypeIAsmOperand"; + let DiagnosticType = "InvalidVTypeIAsmOperand"; +} + +def VTypeIOp : Operand { + let ParserMatchClass = VTypeIAsmOperand; + let PrintMethod = "printVTypeI"; + let DecoderMethod = "decodeUImmOperand<11>"; +} + +def VPRAsmOperand : AsmOperandClass { + let Name = "RVVRegOpOperand"; + let RenderMethod = "addRegOperands"; + let PredicateMethod = "isReg"; + let ParserMethod = "parseRegister"; +} + +def VPRRegOp: RegisterOperand { + let ParserMatchClass = VPRAsmOperand; + let PrintMethod = "printOperand"; +} + +def VPRMaskAsmOperand : AsmOperandClass { + let Name = "RVVMaskRegOpOperand"; + let RenderMethod = "addRegOperands"; + let PredicateMethod = "isReg"; + let ParserMethod = "parseMaskRegister"; +} + +def VPRMaskRegOp: RegisterOperand { + let ParserMatchClass = VPRMaskAsmOperand; + let PrintMethod = "printVPRMaskOp"; +} + +def simm5 : Operand, ImmLeaf(Imm);}]> { + let ParserMatchClass = SImmAsmOperand<5>; + let EncoderMethod = "getImmOpValue"; + let DecoderMethod = "decodeSImmOperand<5>"; + let MCOperandPredicate = [{ + int64_t Imm; + if (MCOp.evaluateAsConstantImm(Imm)) + return isInt<5>(Imm); + return MCOp.isBareSymbolRef(); + }]; +} + +//===----------------------------------------------------------------------===// +// Instruction class templates +//===----------------------------------------------------------------------===// + +let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in { +// load vd, (rs1) (without mask) +class VUnitStrideLoad + : RVInstVLU<0b000, mop, 1, lumop, width, (outs VPRRegOp:$vd), + (ins GPR:$rs1), opcodestr, "$vd, (${rs1})">; + +// load vd, (rs1), vm (with mask) +class VUnitStrideLoad_t + : RVInstVLU<0b000, mop, 0, lumop, width, (outs VPRRegOp:$vd), + (ins GPR:$rs1, VPRMaskRegOp:$vm), opcodestr, "$vd, (${rs1}), $vm">; + +// load vd, (rs1), rs2 (without mask) +class VStridedLoad + : RVInstVLS<0b000, mop, 1, width, (outs VPRRegOp:$vd), + (ins GPR:$rs1, GPR:$rs2), opcodestr, "$vd, (${rs1}), $rs2">; + +// load vd, (rs1), rs2, vm (with mask) +class VStridedLoad_t + : RVInstVLS<0b000, mop, 0, width, (outs VPRRegOp:$vd), + (ins GPR:$rs1, GPR:$rs2, VPRMaskRegOp:$vm), opcodestr, + "$vd, (${rs1}), $rs2, $vm">; + +// load vd, (rs1), vs2 (without mask) +class VIndexedLoad + : RVInstVLX<0b000, mop, 1, width, (outs VPRRegOp:$vd), + (ins GPR:$rs1, VPRRegOp:$vs2), opcodestr, + "$vd, (${rs1}), $vs2">; + +// load vd, (rs1), vs2, vm (with mask) +class VIndexedLoad_t + : RVInstVLX<0b000, mop, 0, width, (outs VPRRegOp:$vd), + (ins GPR:$rs1, VPRRegOp:$vs2, VPRMaskRegOp:$vm), opcodestr, + "$vd, (${rs1}), $vs2, $vm">; +} + +let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in { +// store vd, vs3, (rs1) (without mask) +class VUnitStrideStore + : RVInstVSU<0b000, mop, 1, sumop, width, (outs), + (ins VPRRegOp:$vs3, GPR:$rs1), opcodestr, "$vs3, (${rs1})">; + +// store vd, vs3, (rs1), vm (with mask) +class VUnitStrideStore_t + : RVInstVSU<0b000, mop, 0, sumop, width, (outs), + (ins VPRRegOp:$vs3, GPR:$rs1, VPRMaskRegOp:$vm), opcodestr, + "$vs3, (${rs1}), $vm">; + +// store vd, vs3, (rs1), rs2 (without mask) +class VStridedStore + : RVInstVSS<0b000, mop, 1, width, (outs), + (ins VPRRegOp:$vs3, GPR:$rs1, GPR:$rs2), opcodestr, + "$vs3, (${rs1}), $rs2">; + +// store vd, vs3, (rs1), rs2, vm (with mask) +class VStridedStore_t + : RVInstVSS<0b000, mop, 0, width, (outs), + (ins VPRRegOp:$vs3, GPR:$rs1, GPR:$rs2, VPRMaskRegOp:$vm), + opcodestr, "$vs3, (${rs1}), $rs2, $vm">; + +// store vd, vs3, (rs1), vs2 (without mask) +class VIndexedStore + : RVInstVSX<0b000, mop, 1, width, (outs), + (ins VPRRegOp:$vs3, GPR:$rs1, VPRRegOp:$vs2), opcodestr, + "$vs3, (${rs1}), $vs2">; + +// store vd, vs3, (rs1), vs2, vm (with mask) +class VIndexedStore_t + : RVInstVSX<0b000, mop, 0, width, (outs), + (ins VPRRegOp:$vs3, GPR:$rs1, VPRRegOp:$vs2, VPRMaskRegOp:$vm), + opcodestr, "$vs3, (${rs1}), $vs2, $vm">; +} + +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { +// op vd, vs2, vs1 (without mask) +class VALUVV funct6, RISCVVFormat opv, string opcodestr> + : RVInstVV; + +// op vd, vs2, vs1, vm (with mask) +class VALUVV_t funct6, RISCVVFormat opv, string opcodestr> + : RVInstVV; + +// op vd, vs2, vs1, v0 (without mask, use v0 as carry input) +class VALUmVV funct6, RISCVVFormat opv, string opcodestr> + : RVInstVV; + +// op vd, vs1, vs2 (without mask, reverse the order of vs1 and vs2) +class VALUrVV funct6, RISCVVFormat opv, string opcodestr> + : RVInstVV; + +// op vd, vs1, vs2, vm (with mask, reverse the order of vs1 and vs2) +class VALUrVV_t funct6, RISCVVFormat opv, string opcodestr> + : RVInstVV; + +// op vd, vs2, rs1 (without mask) +class VALUVX funct6, RISCVVFormat opv, string opcodestr> + : RVInstVX; + +// op vd, vs2, rs1, vm (with mask) +class VALUVX_t funct6, RISCVVFormat opv, string opcodestr> + : RVInstVX; + +// op vd, vs2, rs1, v0 (without mask, use v0 as carry input) +class VALUmVX funct6, RISCVVFormat opv, string opcodestr> + : RVInstVX; + +// op vd, rs1, vs2 (without mask, reverse the order of rs1 and vs2) +class VALUrVX funct6, RISCVVFormat opv, string opcodestr> + : RVInstVX; + +// op vd, rs1, vs2, vm (with mask, reverse the order of rs1 and vs2) +class VALUrVX_t funct6, RISCVVFormat opv, string opcodestr> + : RVInstVX; + +// op vd, vs2, imm (without mask) +class VALUVI funct6, string opcodestr, Operand optype = simm5> + : RVInstIVI; + +// op vd, vs2, imm, vm (with mask) +class VALUVI_t funct6, string opcodestr, Operand optype = simm5> + : RVInstIVI; + +// op vd, vs2, imm, v0 (without mask, use v0 as carry input) +class VALUmVI funct6, string opcodestr, Operand optype = simm5> + : RVInstIVI; + +// op vd, vs2, rs1 (Float) (without mask) +class VALUVF funct6, RISCVVFormat opv, string opcodestr> + : RVInstVX; + +// op vd, vs2, rs1, vm (Float) (with mask) +class VALUVF_t funct6, RISCVVFormat opv, string opcodestr> + : RVInstVX; + +// op vd, rs1, vs2 (Float) (without mask, reverse the order of rs1 and vs2) +class VALUrVF funct6, RISCVVFormat opv, string opcodestr> + : RVInstVX; + +// op vd, rs1, vs2 (Float) (with mask, reverse the order of rs1 and vs2) +class VALUrVF_t funct6, RISCVVFormat opv, string opcodestr> + : RVInstVX; + +// op vd, vs2 (without mask, use vs1 as instruction encoding) +class VALUVs2 funct6, bits<5> vs1, RISCVVFormat opv, string opcodestr> + : RVInstV; + +// op vd, vs2, vm (with mask, use vs1 as instruction encoding) +class VALUVs2_t funct6, bits<5> vs1, RISCVVFormat opv, string opcodestr> + : RVInstV; +} + +//===----------------------------------------------------------------------===// +// Combination of instruction classes. +// Use these multiclasses to define instructions more easily. +//===----------------------------------------------------------------------===// + +multiclass VALUVV_Mask funct6, RISCVVFormat opv, string opcodestr> { + def "": VALUVV; + def _T : VALUVV_t; +} + +multiclass VALUrVV_Mask funct6, RISCVVFormat opv, string opcodestr> { + def "": VALUrVV; + def _T : VALUrVV_t; +} + +multiclass VALUVX_Mask funct6, RISCVVFormat opv, string opcodestr> { + def "": VALUVX; + def _T : VALUVX_t; +} + +multiclass VALUrVX_Mask funct6, RISCVVFormat opv, string opcodestr> { + def "": VALUrVX; + def _T : VALUrVX_t; +} + +multiclass VALUVI_Mask funct6, string opcodestr, Operand optype = simm5> { + def "": VALUVI; + def _T : VALUVI_t; +} + +multiclass VALUVF_Mask funct6, RISCVVFormat opv, string opcodestr> { + def "": VALUVF; + def _T : VALUVF_t; +} + +multiclass VALUrVF_Mask funct6, RISCVVFormat opv, string opcodestr> { + def "": VALUrVF; + def _T : VALUrVF_t; +} + +multiclass VALUVs2_Mask funct6, bits<5> vs1, RISCVVFormat opv, string opcodestr> { + def "": VALUVs2; + def _T : VALUVs2_t; +} + +multiclass VUnitStrideLoadMask { + def "": VUnitStrideLoad; + def _T : VUnitStrideLoad_t; +} + +multiclass VStridedLoadMask { + def "": VStridedLoad; + def _T : VStridedLoad_t; +} + +multiclass VIndexedLoadMask { + def "": VIndexedLoad; + def _T : VIndexedLoad_t; +} + +multiclass VUnitStrideStoreMask { + def "": VUnitStrideStore; + def _T : VUnitStrideStore_t; +} + +multiclass VStridedStoreMask { + def "": VStridedStore; + def _T : VStridedStore_t; +} + +multiclass VIndexedStoreMask { + def "": VIndexedStore; + def _T : VIndexedStore_t; +} + +multiclass VALU_IV_V_X_I funct6, Operand optype = simm5, string vw = "v"> { + defm V : VALUVV_Mask; + defm X : VALUVX_Mask; + defm I : VALUVI_Mask; +} + +multiclass VALU_IV_V_X funct6, string vw = "v"> { + defm V : VALUVV_Mask; + defm X : VALUVX_Mask; +} + +multiclass VALUr_IV_V_X funct6, string vw = "v"> { + defm V : VALUrVV_Mask; + defm X : VALUrVX_Mask; +} + +multiclass VALU_IV_X_I funct6, Operand optype = simm5, string vw = "v"> { + defm X : VALUVX_Mask; + defm I : VALUVI_Mask; +} + +multiclass VALU_IV_V funct6> { + defm _VS : VALUVV_Mask; +} + +multiclass VALU_IV_X funct6, string vw = "v"> { + defm X : VALUVX_Mask; +} + +multiclass VALUr_IV_X funct6, string vw = "v"> { + defm X : VALUrVX_Mask; +} + +multiclass VALU_MV_V_X funct6, string vw = "v"> { + defm V : VALUVV_Mask; + defm X : VALUVX_Mask; +} + +multiclass VALU_MV_V funct6> { + defm _VS : VALUVV_Mask; +} + +multiclass VALU_MV_M funct6, string vm = "v"> { + def M : VALUVV; +} + +multiclass VALU_MV_X funct6, string vw = "v"> { + defm X : VALUVX_Mask; +} + +multiclass VALUr_MV_V_X funct6, string vw = "v"> { + defm V : VALUrVV_Mask; + defm X : VALUrVX_Mask; +} + +multiclass VALUr_MV_X funct6, string vw = "v"> { + defm X : VALUrVX_Mask; +} + +multiclass VALU_MV_VS2 funct6, bits<5> vs1> { + defm "" : VALUVs2_Mask; +} + +multiclass VALUm_IV_V_X_I funct6> { + def _VVM : VALUmVV; + def _VXM : VALUmVX; + def _VIM : VALUmVI; +} + +multiclass VALUm_IV_V_X funct6> { + def _VVM : VALUmVV; + def _VXM : VALUmVX; +} + +// These instructions are always masked. +multiclass VALU_IV_V_X_I_t funct6, Operand optype = simm5, string vw = "v"> { + def _VVM : VALUVV_t; + def _VXM : VALUVX_t; + def _VIM : VALUVI_t; +} + +multiclass VALU_FV_V_F funct6, string vw = "v"> { + defm V : VALUVV_Mask; + defm F : VALUVF_Mask; +} + +multiclass VALU_FV_F funct6, string vw = "v"> { + defm F : VALUVF_Mask; +} + +multiclass VALUr_FV_V_F funct6, string vw = "v"> { + defm V : VALUrVV_Mask; + defm F : VALUrVF_Mask; +} + +multiclass VALU_FV_V funct6> { + defm _VS : VALUVV_Mask; +} + +multiclass VALU_FV_VS2 funct6, bits<5> vs1> { + defm "" : VALUVs2_Mask; +} + +//===----------------------------------------------------------------------===// +// Instructions +//===----------------------------------------------------------------------===// + +let Predicates = [HasStdExtV] in { + +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { +def VSETVLI : RVInstSetVLi<(outs GPR:$rd), (ins GPR:$rs1, VTypeIOp:$vtypei), + "vsetvli", "$rd, $rs1, $vtypei">; +def VSETVL : RVInstSetVL<(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2), + "vsetvl", "$rd, $rs1, $rs2">; +} + +// Vector Unit-Stride Instructions +defm VLB_V : VUnitStrideLoadMask; +defm VLH_V : VUnitStrideLoadMask; +defm VLW_V : VUnitStrideLoadMask; + +defm VLBU_V : VUnitStrideLoadMask; +defm VLHU_V : VUnitStrideLoadMask; +defm VLWU_V : VUnitStrideLoadMask; + +defm VLE_V : VUnitStrideLoadMask; + +defm VLBFF_V : VUnitStrideLoadMask; +defm VLHFF_V : VUnitStrideLoadMask; +defm VLWFF_V : VUnitStrideLoadMask; + +defm VLBUFF_V : VUnitStrideLoadMask; +defm VLHUFF_V : VUnitStrideLoadMask; +defm VLWUFF_V : VUnitStrideLoadMask; + +defm VLEFF_V : VUnitStrideLoadMask; + +defm VSB_V : VUnitStrideStoreMask; +defm VSH_V : VUnitStrideStoreMask; +defm VSW_V : VUnitStrideStoreMask; + +defm VSE_V : VUnitStrideStoreMask; + +// Vector Strided Instructions +defm VLSB_V : VStridedLoadMask; +defm VLSH_V : VStridedLoadMask; +defm VLSW_V : VStridedLoadMask; + +defm VLSBU_V : VStridedLoadMask; +defm VLSHU_V : VStridedLoadMask; +defm VLSWU_V : VStridedLoadMask; + +defm VLSE_V : VStridedLoadMask; + +defm VSSB_V : VStridedStoreMask; +defm VSSH_V : VStridedStoreMask; +defm VSSW_V : VStridedStoreMask; +defm VSSE_V : VStridedStoreMask; + +// Vector Indexed Instructions +defm VLXB_V : VIndexedLoadMask; +defm VLXH_V : VIndexedLoadMask; +defm VLXW_V : VIndexedLoadMask; + +defm VLXBU_V : VIndexedLoadMask; +defm VLXHU_V : VIndexedLoadMask; +defm VLXWU_V : VIndexedLoadMask; + +defm VLXE_V : VIndexedLoadMask; + +defm VSXB_V : VIndexedStoreMask; +defm VSXH_V : VIndexedStoreMask; +defm VSXW_V : VIndexedStoreMask; +defm VSXE_V : VIndexedStoreMask; + +defm VSUXB_V : VIndexedStoreMask; +defm VSUXH_V : VIndexedStoreMask; +defm VSUXW_V : VIndexedStoreMask; +defm VSUXE_V : VIndexedStoreMask; + +// Vector Single-Width Integer Add and Subtract +defm VADD_V : VALU_IV_V_X_I<"vadd", 0b000000>; +defm VSUB_V : VALU_IV_V_X<"vsub", 0b000010>; +defm VRSUB_V: VALU_IV_X_I<"vrsub", 0b000011>; + +// Vector Widening Integer Add/Subtract +let Constraints = "@earlyclobber $vd" in { +defm VWADDU_V : VALU_MV_V_X<"vwaddu", 0b110000>; +defm VWSUBU_V : VALU_MV_V_X<"vwsubu", 0b110010>; +defm VWADD_V : VALU_MV_V_X<"vwadd", 0b110001>; +defm VWSUB_V : VALU_MV_V_X<"vwsub", 0b110011>; +} +defm VWADDU_W : VALU_MV_V_X<"vwaddu", 0b110100, "w">; +defm VWSUBU_W : VALU_MV_V_X<"vwsubu", 0b110110, "w">; +defm VWADD_W : VALU_MV_V_X<"vwadd", 0b110101, "w">; +defm VWSUB_W : VALU_MV_V_X<"vwsub", 0b110111, "w">; + +// Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions +defm VADC : VALUm_IV_V_X_I<"vadc", 0b010000>; +defm VMADC : VALUm_IV_V_X_I<"vmadc", 0b010001>; +defm VSBC : VALUm_IV_V_X<"vsbc", 0b010010>; +defm VMSBC : VALUm_IV_V_X<"vmsbc", 0b010011>; + +// Vector Bitwise Logical Instructions +defm VAND_V : VALU_IV_V_X_I<"vand", 0b001001>; +defm VOR_V : VALU_IV_V_X_I<"vor", 0b001010>; +defm VXOR_V : VALU_IV_V_X_I<"vxor", 0b001011>; + +// Vector Single-Width Bit Shift Instructions +defm VSLL_V : VALU_IV_V_X_I<"vsll", 0b100101, uimm5>; +defm VSRL_V : VALU_IV_V_X_I<"vsrl", 0b101000, uimm5>; +defm VSRA_V : VALU_IV_V_X_I<"vsra", 0b101001, uimm5>; + +// Vector Narrowing Integer Right Shift Instructions +defm VNSRL_W : VALU_IV_V_X_I<"vnsrl", 0b101100, uimm5, "w">; +defm VNSRA_W : VALU_IV_V_X_I<"vnsra", 0b101101, uimm5, "w">; + +// Vector Integer Comparison Instructions +defm VMSEQ_V : VALU_IV_V_X_I<"vmseq", 0b011000>; +defm VMSNE_V : VALU_IV_V_X_I<"vmsne", 0b011001>; +defm VMSLTU_V : VALU_IV_V_X<"vmsltu", 0b011010>; +defm VMSLT_V : VALU_IV_V_X<"vmslt", 0b011011>; +defm VMSLEU_V : VALU_IV_V_X_I<"vmsleu", 0b011100>; +defm VMSLE_V : VALU_IV_V_X_I<"vmsle", 0b011101>; +defm VMSGTU_V : VALU_IV_X_I<"vmsgtu", 0b011110>; +defm VMSGT_V : VALU_IV_X_I<"vmsgt", 0b011111>; + +// Vector Integer Min/Max Instructions +defm VMINU_V : VALU_IV_V_X<"vminu", 0b000100>; +defm VMIN_V : VALU_IV_V_X<"vmin", 0b000101>; +defm VMAXU_V : VALU_IV_V_X<"vmaxu", 0b000110>; +defm VMAX_V : VALU_IV_V_X<"vmax", 0b000111>; + +// Vector Single-Width Integer Multiply Instructions +defm VMUL_V : VALU_MV_V_X<"vmul", 0b100101>; +defm VMULH_V: VALU_MV_V_X<"vmulh", 0b100111>; +defm VMULHU_V : VALU_MV_V_X<"vmulhu", 0b100100>; +defm VMULHSU_V : VALU_MV_V_X<"vmulhsu", 0b100110>; + +// Vector Integer Divide Instructions +defm VDIVU_V : VALU_MV_V_X<"vdivu", 0b100000>; +defm VDIV_V : VALU_MV_V_X<"vdiv", 0b100001>; +defm VREMU_V : VALU_MV_V_X<"vremu", 0b100010>; +defm VREM_V : VALU_MV_V_X<"vrem", 0b100011>; + +// Vector Widening Integer Multiply Instructions +let Constraints = "@earlyclobber $vd" in { +defm VWMUL_V : VALU_MV_V_X<"vwmul", 0b111011>; +defm VWMULU_V : VALU_MV_V_X<"vwmulu", 0b111000>; +defm VWMULSU_V : VALU_MV_V_X<"vwmulsu", 0b111010>; +} + +// Vector Single-Width Integer Multiply-Add Instructions +defm VMACC_V : VALUr_MV_V_X<"vmacc", 0b101101>; +defm VNMSAC_V : VALUr_MV_V_X<"vnmsac", 0b101111>; +defm VMADD_V : VALUr_MV_V_X<"vmadd", 0b101001>; +defm VNMSUB_V : VALUr_MV_V_X<"vnmsub", 0b101011>; + +// Vector Widening Integer Multiply-Add Instructions +let Constraints = "@earlyclobber $vd" in { +defm VWMACCU_V : VALUr_MV_V_X<"vwmaccu", 0b111100>; +defm VWMACC_V : VALUr_MV_V_X<"vwmacc", 0b111101>; +defm VWMACCSU_V : VALUr_MV_V_X<"vwmaccsu", 0b111111>; +defm VWMACCUS_V : VALUr_MV_X<"vwmaccus", 0b111110>; +} + +// Vector Integer Merge Instructions +defm VMERGE : VALU_IV_V_X_I_t<"vmerge", 0b010111>; + +// Vector Integer Move Instructions +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { +// op vd, vs1 +def VMV_V_V : RVInstVV<0b010111, OPIVV, 1, (outs VPRRegOp:$vd), + (ins VPRRegOp:$vs1), "vmv.v.v", "$vd, $vs1"> { + let vs2 = 0; +} +// op vd, rs1 +def VMV_V_X : RVInstVX<0b010111, OPIVX, 1, (outs VPRRegOp:$vd), + (ins GPR:$rs1), "vmv.v.x", "$vd, $rs1"> { + let vs2 = 0; +} +// op vd, imm +def VMV_V_I : RVInstIVI<0b010111, 1, (outs VPRRegOp:$vd), + (ins simm5:$imm), "vmv.v.i", "$vd, $imm"> { + let vs2 = 0; +} +} + +// Vector Fixed-Point Arithmetic Instructions +defm VSADDU_V : VALU_IV_V_X_I<"vsaddu", 0b100000>; +defm VSADD_V : VALU_IV_V_X_I<"vsadd", 0b100001>; +defm VSSUBU_V : VALU_IV_V_X<"vssubu", 0b100010>; +defm VSSUB_V : VALU_IV_V_X<"vssub", 0b100011>; + +// Vector Single-Width Averaging Add and Subtract +defm VAADD_V : VALU_IV_V_X_I<"vaadd", 0b100100>; +defm VASUB_V : VALU_IV_V_X<"vasub", 0b100110>; + +// Vector Single-Width Fractional Multiply with Rounding and Saturation +defm VSMUL_V : VALU_IV_V_X<"vsmul", 0b100111>; + +// Vector Widening Saturating Scaled Multiply-Add +let Constraints = "@earlyclobber $vd" in { +defm VWSMACCU_V : VALUr_IV_V_X<"vwsmaccu", 0b111100>; +defm VWSMACC_V : VALUr_IV_V_X<"vwsmacc", 0b111101>; +defm VWSMACCSU_V : VALUr_IV_V_X<"vwsmaccsu", 0b111111>; +defm VWSMACCUS_V : VALUr_IV_X<"vwsmaccus", 0b111110>; +} + +// Vector Single-Width Scaling Shift Instructions +defm VSSRL_V : VALU_IV_V_X_I<"vssrl", 0b101010, uimm5>; +defm VSSRA_V : VALU_IV_V_X_I<"vssra", 0b101011, uimm5>; + +// Vector Narrowing Fixed-Point Clip Instructions +defm VNCLIPU_W : VALU_IV_V_X_I<"vnclipu", 0b101110, uimm5, "w">; +defm VNCLIP_W : VALU_IV_V_X_I<"vnclip", 0b101111, uimm5, "w">; + +// Vector Single-Width Floating-Point Add/Subtract Instructions +defm VFADD_V : VALU_FV_V_F<"vfadd", 0b000000>; +defm VFSUB_V : VALU_FV_V_F<"vfsub", 0b000010>; +defm VFRSUB_V : VALU_FV_F<"vfrsub", 0b100111>; + +// Vector Widening Floating-Point Add/Subtract Instructions +let Constraints = "@earlyclobber $vd" in { +defm VFWADD_V : VALU_FV_V_F<"vfwadd", 0b110000>; +defm VFWSUB_V : VALU_FV_V_F<"vfwsub", 0b110010>; +} + +defm VFWADD_W : VALU_FV_V_F<"vfwadd", 0b110100, "w">; +defm VFWSUB_W : VALU_FV_V_F<"vfwsub", 0b110110, "w">; + +// Vector Single-Width Floating-Point Multiply/Divide Instructions +defm VFMUL_V : VALU_FV_V_F<"vfmul", 0b100100>; +defm VFDIV_V : VALU_FV_V_F<"vfdiv", 0b100000>; +defm VFRDIV_V : VALU_FV_F<"vfrdiv", 0b100001>; + +// Vector Widening Floating-Point Multiply +let Constraints = "@earlyclobber $vd" in { +defm VFWMUL_V : VALU_FV_V_F<"vfwmul", 0b111000>; +} + +// Vector Single-Width Floating-Point Fused Multiply-Add Instructions +defm VFMACC_V: VALUr_FV_V_F<"vfmacc", 0b101100>; +defm VFNMACC_V : VALUr_FV_V_F<"vfnmacc", 0b101101>; +defm VFMSAC_V : VALUr_FV_V_F<"vfmsac", 0b101110>; +defm VFNMSAC_V : VALUr_FV_V_F<"vfnmsac", 0b101111>; +defm VFMADD_V : VALUr_FV_V_F<"vfmadd", 0b101000>; +defm VFNMADD_V : VALUr_FV_V_F<"vfnmadd", 0b101001>; +defm VFMSUB_V : VALUr_FV_V_F<"vfmsub", 0b101010>; +defm VFNMSUB_V : VALUr_FV_V_F<"vfnmsub", 0b101011>; + +// Vector Widening Floating-Point Fused Multiply-Add Instructions +let Constraints = "@earlyclobber $vd" in { +defm VFWMACC_V : VALUr_FV_V_F<"vfwmacc", 0b111100>; +defm VFWNMACC_V : VALUr_FV_V_F<"vfwnmacc", 0b111101>; +defm VFWMSAC_V : VALUr_FV_V_F<"vfwmsac", 0b111110>; +defm VFWNMSAC_V : VALUr_FV_V_F<"vfwnmsac", 0b111111>; +} + +// Vector Floating-Point Square-Root Instruction +defm VFSQRT_V : VALU_FV_VS2<"vfsqrt.v", 0b100011, 0b00000>; + +// Vector Floating-Point MIN/MAX Instructions +defm VFMIN_V : VALU_FV_V_F<"vfmin", 0b000100>; +defm VFMAX_V : VALU_FV_V_F<"vfmax", 0b000110>; + +// Vector Floating-Point Sign-Injection Instructions +defm VFSGNJ_V : VALU_FV_V_F<"vfsgnj", 0b001000>; +defm VFSGNJN_V : VALU_FV_V_F<"vfsgnjn", 0b001001>; +defm VFSGNJX_V : VALU_FV_V_F<"vfsgnjx", 0b001010>; + +// Vector Floating-Point Compare Instructions +defm VMFEQ_V : VALU_FV_V_F<"vmfeq", 0b011000>; +defm VMFNE_V : VALU_FV_V_F<"vmfne", 0b011100>; +defm VMFLT_V : VALU_FV_V_F<"vmflt", 0b011011>; +defm VMFLE_V : VALU_FV_V_F<"vmfle", 0b011001>; +defm VMFGT_V : VALU_FV_F<"vmfgt", 0b011101>; +defm VMFGE_V : VALU_FV_F<"vmfge", 0b011111>; + +// Vector Floating-Point Classify Instruction +defm VFCLASS_V : VALU_FV_VS2<"vfclass.v", 0b100011, 0b10000>; + +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { +// Vector Floating-Point Merge Instruction +def VFMERGE_VFM : RVInstVX<0b010111, OPFVF, 0, (outs VPRRegOp:$vd), + (ins VPRRegOp:$vs2, FPR32:$rs1, VPRV0:$v0), + "vfmerge.vfm", "$vd, $vs2, $rs1, v0">; + +// Vector Floating-Point Move Instruction +def VFMV_V_F : RVInstVX<0b010111, OPFVF, 1, (outs VPRRegOp:$vd), + (ins FPR32:$rs1), "vfmv.v.f", "$vd, $rs1"> { + let vs2 = 0; +} +} + +// Single-Width Floating-Point/Integer Type-Convert Instructions +defm VFCVT_XU_F_V : VALU_FV_VS2<"vfcvt.xu.f.v", 0b100010, 0b00000>; +defm VFCVT_X_F_V : VALU_FV_VS2<"vfcvt.x.f.v", 0b100010, 0b00001>; +defm VFCVT_F_XU_V : VALU_FV_VS2<"vfcvt.f.xu.v", 0b100010, 0b00010>; +defm VFCVT_F_X_V : VALU_FV_VS2<"vfcvt.f.x.v", 0b100010, 0b00011>; + +// Widening Floating-Point/Integer Type-Convert Instructions +let Constraints = "@earlyclobber $vd" in { +defm VFWCVT_XU_F_V : VALU_FV_VS2<"vfwcvt.xu.f.v", 0b100010, 0b01000>; +defm VFWCVT_X_F_V : VALU_FV_VS2<"vfwcvt.x.f.v", 0b100010, 0b01001>; +defm VFWCVT_F_XU_V : VALU_FV_VS2<"vfwcvt.f.xu.v", 0b100010, 0b01010>; +defm VFWCVT_F_X_V : VALU_FV_VS2<"vfwcvt.f.x.v", 0b100010, 0b01011>; +defm VFWCVT_F_F_V : VALU_FV_VS2<"vfwcvt.f.f.v", 0b100010, 0b01100>; +} + +// Narrowing Floating-Point/Integer Type-Convert Instructions +defm VFNCVT_XU_F_W : VALU_FV_VS2<"vfncvt.xu.f.w", 0b100010, 0b10000>; +defm VFNCVT_X_F_W : VALU_FV_VS2<"vfncvt.x.f.w", 0b100010, 0b10001>; +defm VFNCVT_F_XU_W : VALU_FV_VS2<"vfncvt.f.xu.w", 0b100010, 0b10010>; +defm VFNCVT_F_X_W : VALU_FV_VS2<"vfncvt.f.x.w", 0b100010, 0b10011>; +defm VFNCVT_F_F_W : VALU_FV_VS2<"vfncvt.f.f.w", 0b100010, 0b10100>; +defm VFNCVT_ROD_F_F_W : VALU_FV_VS2<"vfncvt.rod.f.f.w", 0b100010, 0b10101>; + +// Vector Single-Width Integer Reduction Instructions +defm VREDSUM : VALU_MV_V<"vredsum", 0b000000>; +defm VREDMAXU : VALU_MV_V<"vredmaxu", 0b000110>; +defm VREDMAX : VALU_MV_V<"vredmax", 0b000111>; +defm VREDMINU : VALU_MV_V<"vredminu", 0b000100>; +defm VREDMIN : VALU_MV_V<"vredmin", 0b000101>; +defm VREDAND : VALU_MV_V<"vredand", 0b000001>; +defm VREDOR : VALU_MV_V<"vredor", 0b000010>; +defm VREDXOR : VALU_MV_V<"vredxor", 0b000011>; + +// Vector Widening Integer Reduction Instructions +defm VWREDSUMU : VALU_IV_V<"vwredsumu", 0b110000>; +defm VWREDSUM : VALU_IV_V<"vwredsum", 0b110001>; + +// Vector Single-Width Floating-Point Reduction Instructions +defm VFREDOSUM : VALU_FV_V<"vfredosum", 0b000011>; +defm VFREDSUM : VALU_FV_V<"vfredsum", 0b000001>; +defm VFREDMAX : VALU_FV_V<"vfredmax", 0b000111>; +defm VFREDMIN : VALU_FV_V<"vfredmin", 0b000101>; + +// Vector Widening Floating-Point Reduction Instructions +defm VFWREDOSUM : VALU_FV_V<"vfwredosum", 0b110011>; +defm VFWREDSUM : VALU_FV_V<"vfwredsum", 0b110001>; + +// Vector Mask-Register Logical Instructions +defm VMAND_M : VALU_MV_M<"vmand", 0b011001, "m">; +defm VMNAND_M : VALU_MV_M<"vmnand", 0b011101, "m">; +defm VMANDNOT_M : VALU_MV_M<"vmandnot", 0b011000, "m">; +defm VMXOR_M : VALU_MV_M<"vmxor", 0b011011, "m">; +defm VMOR_M : VALU_MV_M<"vmor", 0b011010, "m">; +defm VMNOR_M : VALU_MV_M<"vmnor", 0b011110, "m">; +defm VMORNOT_M : VALU_MV_M<"vmornot", 0b011100, "m">; +defm VMXNOR_M : VALU_MV_M<"vmxnor", 0b011111, "m">; + +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { +// Vector mask population count vpopc +def VPOPC_M : RVInstV<0b010000, 0b10000, OPMVV, 1, (outs GPR:$vd), + (ins VPRRegOp:$vs2), "vpopc.m", "$vd, $vs2">; +def VPOPC_M_T : RVInstV<0b010000, 0b10000, OPMVV, 0, (outs GPR:$vd), + (ins VPRRegOp:$vs2, VPRMaskRegOp:$vm), + "vpopc.m", "$vd, $vs2, $vm">; + +// vfirst find-first-set mask bit +def VFIRST_M : RVInstV<0b010000, 0b10001, OPMVV, 1, (outs GPR:$vd), + (ins VPRRegOp:$vs2), "vfirst.m", "$vd, $vs2">; +def VFIRST_M_T : RVInstV<0b010000, 0b10001, OPMVV, 0, (outs GPR:$vd), + (ins VPRRegOp:$vs2, VPRMaskRegOp:$vm), + "vfirst.m", "$vd, $vs2, $vm">; +} + +// vmsbf.m set-before-first mask bit +defm VMSBF_M : VALU_MV_VS2<"vmsbf.m", 0b010100, 0b00001>; + +// vmsif.m set-including-first mask bit +defm VMSIF_M : VALU_MV_VS2<"vmsif.m", 0b010100, 0b00011>; + +// vmsof.m set-only-first mask bit +defm VMSOF_M : VALU_MV_VS2<"vmsof.m", 0b010100, 0b00010>; + +// Vector Iota Instruction +let Constraints = "@earlyclobber $vd" in { +defm VIOTA_M : VALU_MV_VS2<"viota.m", 0b010100, 0b10000>; +} + +// Vector Element Index Instruction +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { +def VID_V : RVInstV<0b010100, 0b10001, OPMVV, 1, (outs VPRRegOp:$vd), + (ins), "vid.v", "$vd"> { + let vs2 = 0; +} + +def VID_V_T : RVInstV<0b010100, 0b10001, OPMVV, 0, (outs VPRRegOp:$vd), + (ins VPRMaskRegOp:$vm), "vid.v", "$vd, $vm"> { + let vs2 = 0; +} + +// Integer Scalar Move Instructions +def VMV_X_S : RVInstV<0b010000, 0b00000, OPMVV, 1, (outs GPR:$vd), + (ins VPRRegOp:$vs2), "vmv.x.s", "$vd, $vs2">; +def VMV_S_X : RVInstV2<0b010000, 0b00000, OPMVX, 1, (outs VPRRegOp:$vd), + (ins GPR:$rs1), "vmv.s.x", "$vd, $rs1">; + +// Floating-Point Scalar Move Instructions +def VFMV_F_S : RVInstV<0b010000, 0b00000, OPFVV, 1, (outs FPR32:$vd), + (ins VPRRegOp:$vs2), "vfmv.f.s", "$vd, $vs2">; +def VFMV_S_F : RVInstV2<0b010000, 0b00000, OPFVF, 1, (outs VPRRegOp:$vd), + (ins FPR32:$rs1), "vfmv.s.f", "$vd, $rs1">; +} + +// Vector Slide Instructions +let Constraints = "@earlyclobber $vd" in { +defm VSLIDEUP_V : VALU_IV_X_I<"vslideup", 0b001110, uimm5>; +} +defm VSLIDEDOWN_V : VALU_IV_X_I<"vslidedown", 0b001111, uimm5>; + +let Constraints = "@earlyclobber $vd" in { +defm VSLIDE1UP_V : VALU_MV_X<"vslide1up", 0b001110>; +} +defm VSLIDE1DOWN_V : VALU_MV_X<"vslide1down", 0b001111>; + +// Vector Register Gather Instruction +let Constraints = "@earlyclobber $vd" in { +defm VRGATHER_V : VALU_IV_V_X_I<"vrgather", 0b001100, uimm5>; +} + +// Vector Compress Instruction +let Constraints = "@earlyclobber $vd" in { +defm VCOMPRESS_V : VALU_MV_M<"vcompress", 0b010111>; +} + +} // Predicates = [HasStdExtV] Index: llvm/lib/Target/RISCV/RISCVRegisterInfo.td =================================================================== --- llvm/lib/Target/RISCV/RISCVRegisterInfo.td +++ llvm/lib/Target/RISCV/RISCVRegisterInfo.td @@ -233,3 +233,57 @@ (sequence "F%u_D", 10, 15), (sequence "F%u_D", 8, 9) )>; + +// Vector registers +let RegAltNameIndices = [ABIRegAltName] in { + def V0 : RISCVReg<0, "v0", ["v0"]>, DwarfRegNum<[64]>; + def V1 : RISCVReg<1, "v1", ["v1"]>, DwarfRegNum<[65]>; + def V2 : RISCVReg<2, "v2", ["v2"]>, DwarfRegNum<[66]>; + def V3 : RISCVReg<3, "v3", ["v3"]>, DwarfRegNum<[67]>; + def V4 : RISCVReg<4, "v4", ["v4"]>, DwarfRegNum<[68]>; + def V5 : RISCVReg<5, "v5", ["v5"]>, DwarfRegNum<[69]>; + def V6 : RISCVReg<6, "v6", ["v6"]>, DwarfRegNum<[70]>; + def V7 : RISCVReg<7, "v7", ["v7"]>, DwarfRegNum<[71]>; + def V8 : RISCVReg<8, "v8", ["v8"]>, DwarfRegNum<[72]>; + def V9 : RISCVReg<9, "v9", ["v9"]>, DwarfRegNum<[73]>; + def V10 : RISCVReg<10,"v10", ["v10"]>, DwarfRegNum<[74]>; + def V11 : RISCVReg<11,"v11", ["v11"]>, DwarfRegNum<[75]>; + def V12 : RISCVReg<12,"v12", ["v12"]>, DwarfRegNum<[76]>; + def V13 : RISCVReg<13,"v13", ["v13"]>, DwarfRegNum<[77]>; + def V14 : RISCVReg<14,"v14", ["v14"]>, DwarfRegNum<[78]>; + def V15 : RISCVReg<15,"v15", ["v15"]>, DwarfRegNum<[79]>; + def V16 : RISCVReg<16,"v16", ["v16"]>, DwarfRegNum<[80]>; + def V17 : RISCVReg<17,"v17", ["v17"]>, DwarfRegNum<[81]>; + def V18 : RISCVReg<18,"v18", ["v18"]>, DwarfRegNum<[82]>; + def V19 : RISCVReg<19,"v19", ["v19"]>, DwarfRegNum<[83]>; + def V20 : RISCVReg<20,"v20", ["v20"]>, DwarfRegNum<[84]>; + def V21 : RISCVReg<21,"v21", ["v21"]>, DwarfRegNum<[85]>; + def V22 : RISCVReg<22,"v22", ["v22"]>, DwarfRegNum<[86]>; + def V23 : RISCVReg<23,"v23", ["v23"]>, DwarfRegNum<[87]>; + def V24 : RISCVReg<24,"v24", ["v24"]>, DwarfRegNum<[88]>; + def V25 : RISCVReg<25,"v25", ["v25"]>, DwarfRegNum<[89]>; + def V26 : RISCVReg<26,"v26", ["v26"]>, DwarfRegNum<[90]>; + def V27 : RISCVReg<27,"v27", ["v27"]>, DwarfRegNum<[91]>; + def V28 : RISCVReg<28,"v28", ["v28"]>, DwarfRegNum<[92]>; + def V29 : RISCVReg<29,"v29", ["v29"]>, DwarfRegNum<[93]>; + def V30 : RISCVReg<30,"v30", ["v30"]>, DwarfRegNum<[94]>; + def V31 : RISCVReg<31,"v31", ["v31"]>, DwarfRegNum<[95]>; +} + +class RegisterTypes reg_types> { + list types = reg_types; +} + +def VLenVT : RegisterTypes<[nxv16i8, nxv8i16, nxv4i32, nxv2i64]>; + +// The order of registers represents the preferred allocation sequence, +// meaning caller-save regs are listed before callee-save. +def VPR : RegisterClass<"RISCV", VLenVT.types, + 128, (add + (sequence "V%u", 25, 31), + (sequence "V%u", 8, 24), + (sequence "V%u", 0, 7) + )> { +} + +def VPRV0 : RegisterClass<"RISCV", VLenVT.types, 128, (add V0)>; Index: llvm/lib/Target/RISCV/RISCVSubtarget.h =================================================================== --- llvm/lib/Target/RISCV/RISCVSubtarget.h +++ llvm/lib/Target/RISCV/RISCVSubtarget.h @@ -39,6 +39,7 @@ bool HasStdExtF = false; bool HasStdExtD = false; bool HasStdExtC = false; + bool HasStdExtV = false; bool HasRV64 = false; bool IsRV32E = false; bool EnableLinkerRelax = false; @@ -87,6 +88,7 @@ bool hasStdExtF() const { return HasStdExtF; } bool hasStdExtD() const { return HasStdExtD; } bool hasStdExtC() const { return HasStdExtC; } + bool hasStdExtV() const { return HasStdExtV; } bool is64Bit() const { return HasRV64; } bool isRV32E() const { return IsRV32E; } bool enableLinkerRelax() const { return EnableLinkerRelax; } Index: llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h =================================================================== --- llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h +++ llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h @@ -44,7 +44,9 @@ InstFormatCJ = 16, InstFormatOther = 17, - InstFormatMask = 31 + InstFormatMask = 31, + + InstVector = (0x1 << 5), }; enum { Index: llvm/test/MC/RISCV/rvv/add.s =================================================================== --- /dev/null +++ llvm/test/MC/RISCV/rvv/add.s @@ -0,0 +1,331 @@ +// RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+v < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=riscv64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \ +// RUN: | llvm-objdump -d -mattr=+v - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +vadd.vv v1, v3, v2, v0.t +// CHECK-INST: vadd.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x00,0x31,0x00] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 00 + +vadd.vv v1, v3, v2 +// CHECK-INST: vadd.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x00,0x31,0x02] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 02 + +vadd.vx v1, v3, a0, v0.t +// CHECK-INST: vadd.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x40,0x35,0x00] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 00 + +vadd.vx v1, v3, a0 +// CHECK-INST: vadd.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x40,0x35,0x02] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 02 + +vadd.vi v1, v3, 15, v0.t +// CHECK-INST: vadd.vi v1, v3, 15, v0.t +// CHECK-ENCODING: [0xd7,0xb0,0x37,0x00] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 37 00 + +vadd.vi v1, v3, 15 +// CHECK-INST: vadd.vi v1, v3, 15 +// CHECK-ENCODING: [0xd7,0xb0,0x37,0x02] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 37 02 + +vwaddu.vv v1, v3, v2, v0.t +// CHECK-INST: vwaddu.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x20,0x31,0xc0] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 c0 + +vwaddu.vv v1, v3, v2 +// CHECK-INST: vwaddu.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x20,0x31,0xc2] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 c2 + +vwaddu.vx v1, v3, a0, v0.t +// CHECK-INST: vwaddu.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x60,0x35,0xc0] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 c0 + +vwaddu.vx v1, v3, a0 +// CHECK-INST: vwaddu.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x60,0x35,0xc2] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 c2 + +vwadd.vv v1, v3, v2, v0.t +// CHECK-INST: vwadd.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x20,0x31,0xc4] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 c4 + +vwadd.vv v1, v3, v2 +// CHECK-INST: vwadd.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x20,0x31,0xc6] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 c6 + +vwadd.vx v1, v3, a0, v0.t +// CHECK-INST: vwadd.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x60,0x35,0xc4] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 c4 + +vwadd.vx v1, v3, a0 +// CHECK-INST: vwadd.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x60,0x35,0xc6] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 c6 + +vwaddu.wv v1, v3, v2, v0.t +// CHECK-INST: vwaddu.wv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x20,0x31,0xd0] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 d0 + +vwaddu.wv v1, v3, v2 +// CHECK-INST: vwaddu.wv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x20,0x31,0xd2] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 d2 + +vwaddu.wx v1, v3, a0, v0.t +// CHECK-INST: vwaddu.wx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x60,0x35,0xd0] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 d0 + +vwaddu.wx v1, v3, a0 +// CHECK-INST: vwaddu.wx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x60,0x35,0xd2] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 d2 + +vwadd.wv v1, v3, v2, v0.t +// CHECK-INST: vwadd.wv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x20,0x31,0xd4] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 d4 + +vwadd.wv v1, v3, v2 +// CHECK-INST: vwadd.wv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x20,0x31,0xd6] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 d6 + +vwadd.wx v1, v3, a0, v0.t +// CHECK-INST: vwadd.wx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x60,0x35,0xd4] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 d4 + +vwadd.wx v1, v3, a0 +// CHECK-INST: vwadd.wx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x60,0x35,0xd6] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 d6 + +vadc.vvm v1, v3, v2, v0 +// CHECK-INST: vadc.vvm v1, v3, v2, v0 +// CHECK-ENCODING: [0xd7,0x00,0x31,0x42] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 42 + +vadc.vxm v1, v3, a0, v0 +// CHECK-INST: vadc.vxm v1, v3, a0, v0 +// CHECK-ENCODING: [0xd7,0x40,0x35,0x42] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 42 + +vadc.vim v1, v3, 15, v0 +// CHECK-INST: vadc.vim v1, v3, 15, v0 +// CHECK-ENCODING: [0xd7,0xb0,0x37,0x42] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 37 42 + +vmadc.vvm v1, v3, v2, v0 +// CHECK-INST: vmadc.vvm v1, v3, v2, v0 +// CHECK-ENCODING: [0xd7,0x00,0x31,0x46] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 46 + +vmadc.vxm v1, v3, a0, v0 +// CHECK-INST: vmadc.vxm v1, v3, a0, v0 +// CHECK-ENCODING: [0xd7,0x40,0x35,0x46] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 46 + +vmadc.vim v1, v3, 15, v0 +// CHECK-INST: vmadc.vim v1, v3, 15, v0 +// CHECK-ENCODING: [0xd7,0xb0,0x37,0x46] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 37 46 + +vsaddu.vv v1, v3, v2, v0.t +// CHECK-INST: vsaddu.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x00,0x31,0x80] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 80 + +vsaddu.vv v1, v3, v2 +// CHECK-INST: vsaddu.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x00,0x31,0x82] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 82 + +vsaddu.vx v1, v3, a0, v0.t +// CHECK-INST: vsaddu.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x40,0x35,0x80] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 80 + +vsaddu.vx v1, v3, a0 +// CHECK-INST: vsaddu.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x40,0x35,0x82] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 82 + +vsaddu.vi v1, v3, 15, v0.t +// CHECK-INST: vsaddu.vi v1, v3, 15, v0.t +// CHECK-ENCODING: [0xd7,0xb0,0x37,0x80] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 37 80 + +vsaddu.vi v1, v3, 15 +// CHECK-INST: vsaddu.vi v1, v3, 15 +// CHECK-ENCODING: [0xd7,0xb0,0x37,0x82] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 37 82 + +vsadd.vv v1, v3, v2, v0.t +// CHECK-INST: vsadd.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x00,0x31,0x84] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 84 + +vsadd.vv v1, v3, v2 +// CHECK-INST: vsadd.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x00,0x31,0x86] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 86 + +vsadd.vx v1, v3, a0, v0.t +// CHECK-INST: vsadd.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x40,0x35,0x84] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 84 + +vsadd.vx v1, v3, a0 +// CHECK-INST: vsadd.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x40,0x35,0x86] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 86 + +vsadd.vi v1, v3, 15, v0.t +// CHECK-INST: vsadd.vi v1, v3, 15, v0.t +// CHECK-ENCODING: [0xd7,0xb0,0x37,0x84] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 37 84 + +vsadd.vi v1, v3, 15 +// CHECK-INST: vsadd.vi v1, v3, 15 +// CHECK-ENCODING: [0xd7,0xb0,0x37,0x86] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 37 86 + +vaadd.vv v1, v3, v2, v0.t +// CHECK-INST: vaadd.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x00,0x31,0x90] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 90 + +vaadd.vv v1, v3, v2 +// CHECK-INST: vaadd.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x00,0x31,0x92] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 92 + +vaadd.vx v1, v3, a0, v0.t +// CHECK-INST: vaadd.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x40,0x35,0x90] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 90 + +vaadd.vx v1, v3, a0 +// CHECK-INST: vaadd.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x40,0x35,0x92] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 92 + +vaadd.vi v1, v3, 15, v0.t +// CHECK-INST: vaadd.vi v1, v3, 15, v0.t +// CHECK-ENCODING: [0xd7,0xb0,0x37,0x90] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 37 90 + +vaadd.vi v1, v3, 15 +// CHECK-INST: vaadd.vi v1, v3, 15 +// CHECK-ENCODING: [0xd7,0xb0,0x37,0x92] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 37 92 + +vfadd.vv v1, v3, v2, v0.t +// CHECK-INST: vfadd.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x10,0x31,0x00] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 00 + +vfadd.vv v1, v3, v2 +// CHECK-INST: vfadd.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x10,0x31,0x02] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 02 + +vfadd.vf v1, v3, fa0, v0.t +// CHECK-INST: vfadd.vf v1, v3, fa0, v0.t +// CHECK-ENCODING: [0xd7,0x50,0x35,0x00] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 00 + +vfadd.vf v1, v3, fa0 +// CHECK-INST: vfadd.vf v1, v3, fa0 +// CHECK-ENCODING: [0xd7,0x50,0x35,0x02] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 02 + +vfwadd.vv v1, v3, v2, v0.t +// CHECK-INST: vfwadd.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x10,0x31,0xc0] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 c0 + +vfwadd.vv v1, v3, v2 +// CHECK-INST: vfwadd.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x10,0x31,0xc2] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 c2 + +vfwadd.vf v1, v3, fa0, v0.t +// CHECK-INST: vfwadd.vf v1, v3, fa0, v0.t +// CHECK-ENCODING: [0xd7,0x50,0x35,0xc0] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 c0 + +vfwadd.vf v1, v3, fa0 +// CHECK-INST: vfwadd.vf v1, v3, fa0 +// CHECK-ENCODING: [0xd7,0x50,0x35,0xc2] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 c2 Index: llvm/test/MC/RISCV/rvv/and.s =================================================================== --- /dev/null +++ llvm/test/MC/RISCV/rvv/and.s @@ -0,0 +1,43 @@ +// RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+v < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=riscv64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \ +// RUN: | llvm-objdump -d -mattr=+v - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +vand.vv v1, v3, v2, v0.t +// CHECK-INST: vand.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x00,0x31,0x24] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 24 + +vand.vv v1, v3, v2 +// CHECK-INST: vand.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x00,0x31,0x26] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 26 + +vand.vx v1, v3, a0, v0.t +// CHECK-INST: vand.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x40,0x35,0x24] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 24 + +vand.vx v1, v3, a0 +// CHECK-INST: vand.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x40,0x35,0x26] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 26 + +vand.vi v1, v3, 15, v0.t +// CHECK-INST: vand.vi v1, v3, 15, v0.t +// CHECK-ENCODING: [0xd7,0xb0,0x37,0x24] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 37 24 + +vand.vi v1, v3, 15 +// CHECK-INST: vand.vi v1, v3, 15 +// CHECK-ENCODING: [0xd7,0xb0,0x37,0x26] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 37 26 Index: llvm/test/MC/RISCV/rvv/clip.s =================================================================== --- /dev/null +++ llvm/test/MC/RISCV/rvv/clip.s @@ -0,0 +1,79 @@ +// RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+v < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=riscv64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \ +// RUN: | llvm-objdump -d -mattr=+v - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +vnclipu.wv v1, v3, v2, v0.t +// CHECK-INST: vnclipu.wv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x00,0x31,0xb8] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 b8 + +vnclipu.wv v1, v3, v2 +// CHECK-INST: vnclipu.wv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x00,0x31,0xba] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 ba + +vnclipu.wx v1, v3, a0, v0.t +// CHECK-INST: vnclipu.wx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x40,0x35,0xb8] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 b8 + +vnclipu.wx v1, v3, a0 +// CHECK-INST: vnclipu.wx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x40,0x35,0xba] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 ba + +vnclipu.wi v1, v3, 31, v0.t +// CHECK-INST: vnclipu.wi v1, v3, 31, v0.t +// CHECK-ENCODING: [0xd7,0xb0,0x3f,0xb8] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 3f b8 + +vnclipu.wi v1, v3, 31 +// CHECK-INST: vnclipu.wi v1, v3, 31 +// CHECK-ENCODING: [0xd7,0xb0,0x3f,0xba] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 3f ba + +vnclip.wv v1, v3, v2, v0.t +// CHECK-INST: vnclip.wv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x00,0x31,0xbc] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 bc + +vnclip.wv v1, v3, v2 +// CHECK-INST: vnclip.wv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x00,0x31,0xbe] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 be + +vnclip.wx v1, v3, a0, v0.t +// CHECK-INST: vnclip.wx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x40,0x35,0xbc] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 bc + +vnclip.wx v1, v3, a0 +// CHECK-INST: vnclip.wx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x40,0x35,0xbe] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 be + +vnclip.wi v1, v3, 31, v0.t +// CHECK-INST: vnclip.wi v1, v3, 31, v0.t +// CHECK-ENCODING: [0xd7,0xb0,0x3f,0xbc] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 3f bc + +vnclip.wi v1, v3, 31 +// CHECK-INST: vnclip.wi v1, v3, 31 +// CHECK-ENCODING: [0xd7,0xb0,0x3f,0xbe] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 3f be Index: llvm/test/MC/RISCV/rvv/compare.s =================================================================== --- /dev/null +++ llvm/test/MC/RISCV/rvv/compare.s @@ -0,0 +1,367 @@ +// RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+v < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=riscv64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \ +// RUN: | llvm-objdump -d -mattr=+v - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +vmseq.vv v1, v3, v2, v0.t +// CHECK-INST: vmseq.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x00,0x31,0x60] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 60 + +vmseq.vv v1, v3, v2 +// CHECK-INST: vmseq.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x00,0x31,0x62] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 62 + +vmseq.vx v1, v3, a0, v0.t +// CHECK-INST: vmseq.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x40,0x35,0x60] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 60 + +vmseq.vx v1, v3, a0 +// CHECK-INST: vmseq.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x40,0x35,0x62] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 62 + +vmseq.vi v1, v3, 15, v0.t +// CHECK-INST: vmseq.vi v1, v3, 15, v0.t +// CHECK-ENCODING: [0xd7,0xb0,0x37,0x60] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 37 60 + +vmseq.vi v1, v3, 15 +// CHECK-INST: vmseq.vi v1, v3, 15 +// CHECK-ENCODING: [0xd7,0xb0,0x37,0x62] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 37 62 + +vmsne.vv v1, v3, v2, v0.t +// CHECK-INST: vmsne.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x00,0x31,0x64] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 64 + +vmsne.vv v1, v3, v2 +// CHECK-INST: vmsne.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x00,0x31,0x66] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 66 + +vmsne.vx v1, v3, a0, v0.t +// CHECK-INST: vmsne.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x40,0x35,0x64] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 64 + +vmsne.vx v1, v3, a0 +// CHECK-INST: vmsne.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x40,0x35,0x66] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 66 + +vmsne.vi v1, v3, 15, v0.t +// CHECK-INST: vmsne.vi v1, v3, 15, v0.t +// CHECK-ENCODING: [0xd7,0xb0,0x37,0x64] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 37 64 + +vmsne.vi v1, v3, 15 +// CHECK-INST: vmsne.vi v1, v3, 15 +// CHECK-ENCODING: [0xd7,0xb0,0x37,0x66] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 37 66 + +vmsltu.vv v1, v3, v2, v0.t +// CHECK-INST: vmsltu.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x00,0x31,0x68] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 68 + +vmsltu.vv v1, v3, v2 +// CHECK-INST: vmsltu.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x00,0x31,0x6a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 6a + +vmsltu.vx v1, v3, a0, v0.t +// CHECK-INST: vmsltu.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x40,0x35,0x68] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 68 + +vmsltu.vx v1, v3, a0 +// CHECK-INST: vmsltu.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x40,0x35,0x6a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 6a + +vmslt.vv v1, v3, v2, v0.t +// CHECK-INST: vmslt.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x00,0x31,0x6c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 6c + +vmslt.vv v1, v3, v2 +// CHECK-INST: vmslt.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x00,0x31,0x6e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 6e + +vmslt.vx v1, v3, a0, v0.t +// CHECK-INST: vmslt.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x40,0x35,0x6c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 6c + +vmslt.vx v1, v3, a0 +// CHECK-INST: vmslt.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x40,0x35,0x6e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 6e + +vmsleu.vv v1, v3, v2, v0.t +// CHECK-INST: vmsleu.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x00,0x31,0x70] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 70 + +vmsleu.vv v1, v3, v2 +// CHECK-INST: vmsleu.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x00,0x31,0x72] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 72 + +vmsleu.vx v1, v3, a0, v0.t +// CHECK-INST: vmsleu.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x40,0x35,0x70] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 70 + +vmsleu.vx v1, v3, a0 +// CHECK-INST: vmsleu.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x40,0x35,0x72] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 72 + +vmsleu.vi v1, v3, 15, v0.t +// CHECK-INST: vmsleu.vi v1, v3, 15, v0.t +// CHECK-ENCODING: [0xd7,0xb0,0x37,0x70] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 37 70 + +vmsleu.vi v1, v3, 15 +// CHECK-INST: vmsleu.vi v1, v3, 15 +// CHECK-ENCODING: [0xd7,0xb0,0x37,0x72] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 37 72 + +vmsle.vv v1, v3, v2, v0.t +// CHECK-INST: vmsle.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x00,0x31,0x74] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 74 + +vmsle.vv v1, v3, v2 +// CHECK-INST: vmsle.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x00,0x31,0x76] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 76 + +vmsle.vx v1, v3, a0, v0.t +// CHECK-INST: vmsle.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x40,0x35,0x74] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 74 + +vmsle.vx v1, v3, a0 +// CHECK-INST: vmsle.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x40,0x35,0x76] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 76 + +vmsle.vi v1, v3, 15, v0.t +// CHECK-INST: vmsle.vi v1, v3, 15, v0.t +// CHECK-ENCODING: [0xd7,0xb0,0x37,0x74] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 37 74 + +vmsle.vi v1, v3, 15 +// CHECK-INST: vmsle.vi v1, v3, 15 +// CHECK-ENCODING: [0xd7,0xb0,0x37,0x76] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 37 76 + +vmsgtu.vx v1, v3, a0, v0.t +// CHECK-INST: vmsgtu.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x40,0x35,0x78] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 78 + +vmsgtu.vx v1, v3, a0 +// CHECK-INST: vmsgtu.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x40,0x35,0x7a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 7a + +vmsgtu.vi v1, v3, 15, v0.t +// CHECK-INST: vmsgtu.vi v1, v3, 15, v0.t +// CHECK-ENCODING: [0xd7,0xb0,0x37,0x78] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 37 78 + +vmsgtu.vi v1, v3, 15 +// CHECK-INST: vmsgtu.vi v1, v3, 15 +// CHECK-ENCODING: [0xd7,0xb0,0x37,0x7a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 37 7a + +vmsgt.vx v1, v3, a0, v0.t +// CHECK-INST: vmsgt.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x40,0x35,0x7c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 7c + +vmsgt.vx v1, v3, a0 +// CHECK-INST: vmsgt.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x40,0x35,0x7e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 7e + +vmsgt.vi v1, v3, 15, v0.t +// CHECK-INST: vmsgt.vi v1, v3, 15, v0.t +// CHECK-ENCODING: [0xd7,0xb0,0x37,0x7c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 37 7c + +vmsgt.vi v1, v3, 15 +// CHECK-INST: vmsgt.vi v1, v3, 15 +// CHECK-ENCODING: [0xd7,0xb0,0x37,0x7e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 37 7e + +vmfeq.vv v1, v3, v2, v0.t +// CHECK-INST: vmfeq.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x10,0x31,0x60] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 60 + +vmfeq.vv v1, v3, v2 +// CHECK-INST: vmfeq.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x10,0x31,0x62] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 62 + +vmfeq.vf v1, v3, fa0, v0.t +// CHECK-INST: vmfeq.vf v1, v3, fa0, v0.t +// CHECK-ENCODING: [0xd7,0x50,0x35,0x60] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 60 + +vmfeq.vf v1, v3, fa0 +// CHECK-INST: vmfeq.vf v1, v3, fa0 +// CHECK-ENCODING: [0xd7,0x50,0x35,0x62] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 62 + +vmfne.vv v1, v3, v2, v0.t +// CHECK-INST: vmfne.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x10,0x31,0x70] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 70 + +vmfne.vv v1, v3, v2 +// CHECK-INST: vmfne.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x10,0x31,0x72] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 72 + +vmfne.vf v1, v3, fa0, v0.t +// CHECK-INST: vmfne.vf v1, v3, fa0, v0.t +// CHECK-ENCODING: [0xd7,0x50,0x35,0x70] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 70 + +vmfne.vf v1, v3, fa0 +// CHECK-INST: vmfne.vf v1, v3, fa0 +// CHECK-ENCODING: [0xd7,0x50,0x35,0x72] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 72 + +vmflt.vv v1, v3, v2, v0.t +// CHECK-INST: vmflt.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x10,0x31,0x6c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 6c + +vmflt.vv v1, v3, v2 +// CHECK-INST: vmflt.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x10,0x31,0x6e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 6e + +vmflt.vf v1, v3, fa0, v0.t +// CHECK-INST: vmflt.vf v1, v3, fa0, v0.t +// CHECK-ENCODING: [0xd7,0x50,0x35,0x6c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 6c + +vmflt.vf v1, v3, fa0 +// CHECK-INST: vmflt.vf v1, v3, fa0 +// CHECK-ENCODING: [0xd7,0x50,0x35,0x6e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 6e + +vmfle.vv v1, v3, v2, v0.t +// CHECK-INST: vmfle.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x10,0x31,0x64] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 64 + +vmfle.vv v1, v3, v2 +// CHECK-INST: vmfle.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x10,0x31,0x66] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 66 + +vmfle.vf v1, v3, fa0, v0.t +// CHECK-INST: vmfle.vf v1, v3, fa0, v0.t +// CHECK-ENCODING: [0xd7,0x50,0x35,0x64] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 64 + +vmfle.vf v1, v3, fa0 +// CHECK-INST: vmfle.vf v1, v3, fa0 +// CHECK-ENCODING: [0xd7,0x50,0x35,0x66] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 66 + +vmfgt.vf v1, v3, fa0, v0.t +// CHECK-INST: vmfgt.vf v1, v3, fa0, v0.t +// CHECK-ENCODING: [0xd7,0x50,0x35,0x74] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 74 + +vmfgt.vf v1, v3, fa0 +// CHECK-INST: vmfgt.vf v1, v3, fa0 +// CHECK-ENCODING: [0xd7,0x50,0x35,0x76] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 76 + +vmfge.vf v1, v3, fa0, v0.t +// CHECK-INST: vmfge.vf v1, v3, fa0, v0.t +// CHECK-ENCODING: [0xd7,0x50,0x35,0x7c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 7c + +vmfge.vf v1, v3, fa0 +// CHECK-INST: vmfge.vf v1, v3, fa0 +// CHECK-ENCODING: [0xd7,0x50,0x35,0x7e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 7e Index: llvm/test/MC/RISCV/rvv/convert.s =================================================================== --- /dev/null +++ llvm/test/MC/RISCV/rvv/convert.s @@ -0,0 +1,187 @@ +// RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+v < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=riscv64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \ +// RUN: | llvm-objdump -d -mattr=+v - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +vfcvt.xu.f.v v1, v3, v0.t +// CHECK-INST: vfcvt.xu.f.v v1, v3, v0.t +// CHECK-ENCODING: [0xd7,0x10,0x30,0x88] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 30 88 + +vfcvt.xu.f.v v1, v3 +// CHECK-INST: vfcvt.xu.f.v v1, v3 +// CHECK-ENCODING: [0xd7,0x10,0x30,0x8a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 30 8a + +vfcvt.x.f.v v1, v3, v0.t +// CHECK-INST: vfcvt.x.f.v v1, v3, v0.t +// CHECK-ENCODING: [0xd7,0x90,0x30,0x88] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 90 30 88 + +vfcvt.x.f.v v1, v3 +// CHECK-INST: vfcvt.x.f.v v1, v3 +// CHECK-ENCODING: [0xd7,0x90,0x30,0x8a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 90 30 8a + +vfcvt.f.xu.v v1, v3, v0.t +// CHECK-INST: vfcvt.f.xu.v v1, v3, v0.t +// CHECK-ENCODING: [0xd7,0x10,0x31,0x88] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 88 + +vfcvt.f.xu.v v1, v3 +// CHECK-INST: vfcvt.f.xu.v v1, v3 +// CHECK-ENCODING: [0xd7,0x10,0x31,0x8a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 8a + +vfcvt.f.x.v v1, v3, v0.t +// CHECK-INST: vfcvt.f.x.v v1, v3, v0.t +// CHECK-ENCODING: [0xd7,0x90,0x31,0x88] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 90 31 88 + +vfcvt.f.x.v v1, v3 +// CHECK-INST: vfcvt.f.x.v v1, v3 +// CHECK-ENCODING: [0xd7,0x90,0x31,0x8a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 90 31 8a + +vfwcvt.xu.f.v v1, v3, v0.t +// CHECK-INST: vfwcvt.xu.f.v v1, v3, v0.t +// CHECK-ENCODING: [0xd7,0x10,0x34,0x88] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 34 88 + +vfwcvt.xu.f.v v1, v3 +// CHECK-INST: vfwcvt.xu.f.v v1, v3 +// CHECK-ENCODING: [0xd7,0x10,0x34,0x8a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 34 8a + +vfwcvt.x.f.v v1, v3, v0.t +// CHECK-INST: vfwcvt.x.f.v v1, v3, v0.t +// CHECK-ENCODING: [0xd7,0x90,0x34,0x88] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 90 34 88 + +vfwcvt.x.f.v v1, v3 +// CHECK-INST: vfwcvt.x.f.v v1, v3 +// CHECK-ENCODING: [0xd7,0x90,0x34,0x8a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 90 34 8a + +vfwcvt.f.xu.v v1, v3, v0.t +// CHECK-INST: vfwcvt.f.xu.v v1, v3, v0.t +// CHECK-ENCODING: [0xd7,0x10,0x35,0x88] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 35 88 + +vfwcvt.f.xu.v v1, v3 +// CHECK-INST: vfwcvt.f.xu.v v1, v3 +// CHECK-ENCODING: [0xd7,0x10,0x35,0x8a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 35 8a + +vfwcvt.f.x.v v1, v3, v0.t +// CHECK-INST: vfwcvt.f.x.v v1, v3, v0.t +// CHECK-ENCODING: [0xd7,0x90,0x35,0x88] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 90 35 88 + +vfwcvt.f.x.v v1, v3 +// CHECK-INST: vfwcvt.f.x.v v1, v3 +// CHECK-ENCODING: [0xd7,0x90,0x35,0x8a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 90 35 8a + +vfwcvt.f.f.v v1, v3, v0.t +// CHECK-INST: vfwcvt.f.f.v v1, v3, v0.t +// CHECK-ENCODING: [0xd7,0x10,0x36,0x88] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 36 88 + +vfwcvt.f.f.v v1, v3 +// CHECK-INST: vfwcvt.f.f.v v1, v3 +// CHECK-ENCODING: [0xd7,0x10,0x36,0x8a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 36 8a + +vfncvt.xu.f.w v1, v3, v0.t +// CHECK-INST: vfncvt.xu.f.w v1, v3, v0.t +// CHECK-ENCODING: [0xd7,0x10,0x38,0x88] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 38 88 + +vfncvt.xu.f.w v1, v3 +// CHECK-INST: vfncvt.xu.f.w v1, v3 +// CHECK-ENCODING: [0xd7,0x10,0x38,0x8a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 38 8a + +vfncvt.x.f.w v1, v3, v0.t +// CHECK-INST: vfncvt.x.f.w v1, v3, v0.t +// CHECK-ENCODING: [0xd7,0x90,0x38,0x88] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 90 38 88 + +vfncvt.x.f.w v1, v3 +// CHECK-INST: vfncvt.x.f.w v1, v3 +// CHECK-ENCODING: [0xd7,0x90,0x38,0x8a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 90 38 8a + +vfncvt.f.xu.w v1, v3, v0.t +// CHECK-INST: vfncvt.f.xu.w v1, v3, v0.t +// CHECK-ENCODING: [0xd7,0x10,0x39,0x88] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 39 88 + +vfncvt.f.xu.w v1, v3 +// CHECK-INST: vfncvt.f.xu.w v1, v3 +// CHECK-ENCODING: [0xd7,0x10,0x39,0x8a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 39 8a + +vfncvt.f.x.w v1, v3, v0.t +// CHECK-INST: vfncvt.f.x.w v1, v3, v0.t +// CHECK-ENCODING: [0xd7,0x90,0x39,0x88] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 90 39 88 + +vfncvt.f.x.w v1, v3 +// CHECK-INST: vfncvt.f.x.w v1, v3 +// CHECK-ENCODING: [0xd7,0x90,0x39,0x8a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 90 39 8a + +vfncvt.f.f.w v1, v3, v0.t +// CHECK-INST: vfncvt.f.f.w v1, v3, v0.t +// CHECK-ENCODING: [0xd7,0x10,0x3a,0x88] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 3a 88 + +vfncvt.f.f.w v1, v3 +// CHECK-INST: vfncvt.f.f.w v1, v3 +// CHECK-ENCODING: [0xd7,0x10,0x3a,0x8a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 3a 8a + +vfncvt.rod.f.f.w v1, v3, v0.t +// CHECK-INST: vfncvt.rod.f.f.w v1, v3, v0.t +// CHECK-ENCODING: [0xd7,0x90,0x3a,0x88] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 90 3a 88 + +vfncvt.rod.f.f.w v1, v3 +// CHECK-INST: vfncvt.rod.f.f.w v1, v3 +// CHECK-ENCODING: [0xd7,0x90,0x3a,0x8a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 90 3a 8a Index: llvm/test/MC/RISCV/rvv/div.s =================================================================== --- /dev/null +++ llvm/test/MC/RISCV/rvv/div.s @@ -0,0 +1,139 @@ +// RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+v < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=riscv64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \ +// RUN: | llvm-objdump -d -mattr=+v - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +vdivu.vv v1, v3, v2, v0.t +// CHECK-INST: vdivu.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x20,0x31,0x80] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 80 + +vdivu.vv v1, v3, v2 +// CHECK-INST: vdivu.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x20,0x31,0x82] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 82 + +vdivu.vx v1, v3, a0, v0.t +// CHECK-INST: vdivu.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x60,0x35,0x80] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 80 + +vdivu.vx v1, v3, a0 +// CHECK-INST: vdivu.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x60,0x35,0x82] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 82 + +vdiv.vv v1, v3, v2, v0.t +// CHECK-INST: vdiv.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x20,0x31,0x84] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 84 + +vdiv.vv v1, v3, v2 +// CHECK-INST: vdiv.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x20,0x31,0x86] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 86 + +vdiv.vx v1, v3, a0, v0.t +// CHECK-INST: vdiv.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x60,0x35,0x84] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 84 + +vdiv.vx v1, v3, a0 +// CHECK-INST: vdiv.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x60,0x35,0x86] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 86 + +vremu.vv v1, v3, v2, v0.t +// CHECK-INST: vremu.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x20,0x31,0x88] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 88 + +vremu.vv v1, v3, v2 +// CHECK-INST: vremu.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x20,0x31,0x8a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 8a + +vremu.vx v1, v3, a0, v0.t +// CHECK-INST: vremu.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x60,0x35,0x88] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 88 + +vremu.vx v1, v3, a0 +// CHECK-INST: vremu.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x60,0x35,0x8a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 8a + +vrem.vv v1, v3, v2, v0.t +// CHECK-INST: vrem.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x20,0x31,0x8c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 8c + +vrem.vv v1, v3, v2 +// CHECK-INST: vrem.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x20,0x31,0x8e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 8e + +vrem.vx v1, v3, a0, v0.t +// CHECK-INST: vrem.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x60,0x35,0x8c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 8c + +vrem.vx v1, v3, a0 +// CHECK-INST: vrem.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x60,0x35,0x8e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 8e + +vfdiv.vv v1, v3, v2, v0.t +// CHECK-INST: vfdiv.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x10,0x31,0x80] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 80 + +vfdiv.vv v1, v3, v2 +// CHECK-INST: vfdiv.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x10,0x31,0x82] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 82 + +vfdiv.vf v1, v3, fa0, v0.t +// CHECK-INST: vfdiv.vf v1, v3, fa0, v0.t +// CHECK-ENCODING: [0xd7,0x50,0x35,0x80] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 80 + +vfdiv.vf v1, v3, fa0 +// CHECK-INST: vfdiv.vf v1, v3, fa0 +// CHECK-ENCODING: [0xd7,0x50,0x35,0x82] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 82 + +vfrdiv.vf v1, v3, fa0, v0.t +// CHECK-INST: vfrdiv.vf v1, v3, fa0, v0.t +// CHECK-ENCODING: [0xd7,0x50,0x35,0x84] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 84 + +vfrdiv.vf v1, v3, fa0 +// CHECK-INST: vfrdiv.vf v1, v3, fa0 +// CHECK-ENCODING: [0xd7,0x50,0x35,0x86] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 86 Index: llvm/test/MC/RISCV/rvv/load.s =================================================================== --- /dev/null +++ llvm/test/MC/RISCV/rvv/load.s @@ -0,0 +1,331 @@ +// RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+v < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=riscv64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \ +// RUN: | llvm-objdump -d -mattr=+v - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +vlb.v v1, (a0), v0.t +// CHECK-INST: vlb.v v1, (a0), v0.t +// CHECK-ENCODING: [0x87,0x00,0x05,0x10] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 00 05 10 + +vlb.v v1, (a0) +// CHECK-INST: vlb.v v1, (a0) +// CHECK-ENCODING: [0x87,0x00,0x05,0x12] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 00 05 12 + +vlh.v v1, (a0), v0.t +// CHECK-INST: vlh.v v1, (a0), v0.t +// CHECK-ENCODING: [0x87,0x50,0x05,0x10] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 50 05 10 + +vlh.v v1, (a0) +// CHECK-INST: vlh.v v1, (a0) +// CHECK-ENCODING: [0x87,0x50,0x05,0x12] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 50 05 12 + +vlw.v v1, (a0), v0.t +// CHECK-INST: vlw.v v1, (a0), v0.t +// CHECK-ENCODING: [0x87,0x60,0x05,0x10] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 60 05 10 + +vlw.v v1, (a0) +// CHECK-INST: vlw.v v1, (a0) +// CHECK-ENCODING: [0x87,0x60,0x05,0x12] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 60 05 12 + +vlbu.v v1, (a0), v0.t +// CHECK-INST: vlbu.v v1, (a0), v0.t +// CHECK-ENCODING: [0x87,0x00,0x05,0x00] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 00 05 00 + +vlbu.v v1, (a0) +// CHECK-INST: vlbu.v v1, (a0) +// CHECK-ENCODING: [0x87,0x00,0x05,0x02] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 00 05 02 + +vlhu.v v1, (a0), v0.t +// CHECK-INST: vlhu.v v1, (a0), v0.t +// CHECK-ENCODING: [0x87,0x50,0x05,0x00] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 50 05 00 + +vlhu.v v1, (a0) +// CHECK-INST: vlhu.v v1, (a0) +// CHECK-ENCODING: [0x87,0x50,0x05,0x02] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 50 05 02 + +vlwu.v v1, (a0), v0.t +// CHECK-INST: vlwu.v v1, (a0), v0.t +// CHECK-ENCODING: [0x87,0x60,0x05,0x00] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 60 05 00 + +vlwu.v v1, (a0) +// CHECK-INST: vlwu.v v1, (a0) +// CHECK-ENCODING: [0x87,0x60,0x05,0x02] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 60 05 02 + +vlbff.v v1, (a0), v0.t +// CHECK-INST: vlbff.v v1, (a0), v0.t +// CHECK-ENCODING: [0x87,0x00,0x05,0x11] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 00 05 11 + +vlbff.v v1, (a0) +// CHECK-INST: vlbff.v v1, (a0) +// CHECK-ENCODING: [0x87,0x00,0x05,0x13] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 00 05 13 + +vlhff.v v1, (a0), v0.t +// CHECK-INST: vlhff.v v1, (a0), v0.t +// CHECK-ENCODING: [0x87,0x50,0x05,0x11] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 50 05 11 + +vlhff.v v1, (a0) +// CHECK-INST: vlhff.v v1, (a0) +// CHECK-ENCODING: [0x87,0x50,0x05,0x13] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 50 05 13 + +vlwff.v v1, (a0), v0.t +// CHECK-INST: vlwff.v v1, (a0), v0.t +// CHECK-ENCODING: [0x87,0x60,0x05,0x11] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 60 05 11 + +vlwff.v v1, (a0) +// CHECK-INST: vlwff.v v1, (a0) +// CHECK-ENCODING: [0x87,0x60,0x05,0x13] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 60 05 13 + +vlbuff.v v1, (a0), v0.t +// CHECK-INST: vlbuff.v v1, (a0), v0.t +// CHECK-ENCODING: [0x87,0x00,0x05,0x01] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 00 05 01 + +vlbuff.v v1, (a0) +// CHECK-INST: vlbuff.v v1, (a0) +// CHECK-ENCODING: [0x87,0x00,0x05,0x03] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 00 05 03 + +vlhuff.v v1, (a0), v0.t +// CHECK-INST: vlhuff.v v1, (a0), v0.t +// CHECK-ENCODING: [0x87,0x50,0x05,0x01] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 50 05 01 + +vlhuff.v v1, (a0) +// CHECK-INST: vlhuff.v v1, (a0) +// CHECK-ENCODING: [0x87,0x50,0x05,0x03] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 50 05 03 + +vlwuff.v v1, (a0), v0.t +// CHECK-INST: vlwuff.v v1, (a0), v0.t +// CHECK-ENCODING: [0x87,0x60,0x05,0x01] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 60 05 01 + +vlwuff.v v1, (a0) +// CHECK-INST: vlwuff.v v1, (a0) +// CHECK-ENCODING: [0x87,0x60,0x05,0x03] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 60 05 03 + +vleff.v v1, (a0), v0.t +// CHECK-INST: vleff.v v1, (a0), v0.t +// CHECK-ENCODING: [0x87,0x70,0x05,0x01] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 70 05 01 + +vleff.v v1, (a0) +// CHECK-INST: vleff.v v1, (a0) +// CHECK-ENCODING: [0x87,0x70,0x05,0x03] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 70 05 03 + +vlsb.v v1, (a0), a1, v0.t +// CHECK-INST: vlsb.v v1, (a0), a1, v0.t +// CHECK-ENCODING: [0x87,0x00,0xb5,0x18] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 00 b5 18 + +vlsb.v v1, (a0), a1 +// CHECK-INST: vlsb.v v1, (a0), a1 +// CHECK-ENCODING: [0x87,0x00,0xb5,0x1a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 00 b5 1a + +vlsh.v v1, (a0), a1, v0.t +// CHECK-INST: vlsh.v v1, (a0), a1, v0.t +// CHECK-ENCODING: [0x87,0x50,0xb5,0x18] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 50 b5 18 + +vlsh.v v1, (a0), a1 +// CHECK-INST: vlsh.v v1, (a0), a1 +// CHECK-ENCODING: [0x87,0x50,0xb5,0x1a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 50 b5 1a + +vlsw.v v1, (a0), a1, v0.t +// CHECK-INST: vlsw.v v1, (a0), a1, v0.t +// CHECK-ENCODING: [0x87,0x60,0xb5,0x18] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 60 b5 18 + +vlsw.v v1, (a0), a1 +// CHECK-INST: vlsw.v v1, (a0), a1 +// CHECK-ENCODING: [0x87,0x60,0xb5,0x1a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 60 b5 1a + +vlsbu.v v1, (a0), a1, v0.t +// CHECK-INST: vlsbu.v v1, (a0), a1, v0.t +// CHECK-ENCODING: [0x87,0x00,0xb5,0x08] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 00 b5 08 + +vlsbu.v v1, (a0), a1 +// CHECK-INST: vlsbu.v v1, (a0), a1 +// CHECK-ENCODING: [0x87,0x00,0xb5,0x0a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 00 b5 0a + +vlshu.v v1, (a0), a1, v0.t +// CHECK-INST: vlshu.v v1, (a0), a1, v0.t +// CHECK-ENCODING: [0x87,0x50,0xb5,0x08] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 50 b5 08 + +vlshu.v v1, (a0), a1 +// CHECK-INST: vlshu.v v1, (a0), a1 +// CHECK-ENCODING: [0x87,0x50,0xb5,0x0a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 50 b5 0a + +vlswu.v v1, (a0), a1, v0.t +// CHECK-INST: vlswu.v v1, (a0), a1, v0.t +// CHECK-ENCODING: [0x87,0x60,0xb5,0x08] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 60 b5 08 + +vlswu.v v1, (a0), a1 +// CHECK-INST: vlswu.v v1, (a0), a1 +// CHECK-ENCODING: [0x87,0x60,0xb5,0x0a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 60 b5 0a + +vlse.v v1, (a0), a1, v0.t +// CHECK-INST: vlse.v v1, (a0), a1, v0.t +// CHECK-ENCODING: [0x87,0x70,0xb5,0x08] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 70 b5 08 + +vlse.v v1, (a0), a1 +// CHECK-INST: vlse.v v1, (a0), a1 +// CHECK-ENCODING: [0x87,0x70,0xb5,0x0a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 70 b5 0a + +vlxb.v v1, (a0), v3, v0.t +// CHECK-INST: vlxb.v v1, (a0), v3, v0.t +// CHECK-ENCODING: [0x87,0x00,0x35,0x1c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 00 35 1c + +vlxb.v v1, (a0), v3 +// CHECK-INST: vlxb.v v1, (a0), v3 +// CHECK-ENCODING: [0x87,0x00,0x35,0x1e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 00 35 1e + +vlxh.v v1, (a0), v3, v0.t +// CHECK-INST: vlxh.v v1, (a0), v3, v0.t +// CHECK-ENCODING: [0x87,0x50,0x35,0x1c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 50 35 1c + +vlxh.v v1, (a0), v3 +// CHECK-INST: vlxh.v v1, (a0), v3 +// CHECK-ENCODING: [0x87,0x50,0x35,0x1e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 50 35 1e + +vlxw.v v1, (a0), v3, v0.t +// CHECK-INST: vlxw.v v1, (a0), v3, v0.t +// CHECK-ENCODING: [0x87,0x60,0x35,0x1c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 60 35 1c + +vlxw.v v1, (a0), v3 +// CHECK-INST: vlxw.v v1, (a0), v3 +// CHECK-ENCODING: [0x87,0x60,0x35,0x1e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 60 35 1e + +vlxbu.v v1, (a0), v3, v0.t +// CHECK-INST: vlxbu.v v1, (a0), v3, v0.t +// CHECK-ENCODING: [0x87,0x00,0x35,0x0c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 00 35 0c + +vlxbu.v v1, (a0), v3 +// CHECK-INST: vlxbu.v v1, (a0), v3 +// CHECK-ENCODING: [0x87,0x00,0x35,0x0e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 00 35 0e + +vlxhu.v v1, (a0), v3, v0.t +// CHECK-INST: vlxhu.v v1, (a0), v3, v0.t +// CHECK-ENCODING: [0x87,0x50,0x35,0x0c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 50 35 0c + +vlxhu.v v1, (a0), v3 +// CHECK-INST: vlxhu.v v1, (a0), v3 +// CHECK-ENCODING: [0x87,0x50,0x35,0x0e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 50 35 0e + +vlxwu.v v1, (a0), v3, v0.t +// CHECK-INST: vlxwu.v v1, (a0), v3, v0.t +// CHECK-ENCODING: [0x87,0x60,0x35,0x0c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 60 35 0c + +vlxwu.v v1, (a0), v3 +// CHECK-INST: vlxwu.v v1, (a0), v3 +// CHECK-ENCODING: [0x87,0x60,0x35,0x0e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 60 35 0e + +vlxe.v v1, (a0), v3, v0.t +// CHECK-INST: vlxe.v v1, (a0), v3, v0.t +// CHECK-ENCODING: [0x87,0x70,0x35,0x0c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 70 35 0c + +vlxe.v v1, (a0), v3 +// CHECK-INST: vlxe.v v1, (a0), v3 +// CHECK-ENCODING: [0x87,0x70,0x35,0x0e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 87 70 35 0e Index: llvm/test/MC/RISCV/rvv/macc.s =================================================================== --- /dev/null +++ llvm/test/MC/RISCV/rvv/macc.s @@ -0,0 +1,559 @@ +// RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+v < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=riscv64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \ +// RUN: | llvm-objdump -d -mattr=+v - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +vmacc.vv v1, v2, v3, v0.t +// CHECK-INST: vmacc.vv v1, v2, v3, v0.t +// CHECK-ENCODING: [0xd7,0x20,0x31,0xb4] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 b4 + +vmacc.vv v1, v2, v3 +// CHECK-INST: vmacc.vv v1, v2, v3 +// CHECK-ENCODING: [0xd7,0x20,0x31,0xb6] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 b6 + +vmacc.vx v1, a0, v3, v0.t +// CHECK-INST: vmacc.vx v1, a0, v3, v0.t +// CHECK-ENCODING: [0xd7,0x60,0x35,0xb4] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 b4 + +vmacc.vx v1, a0, v3 +// CHECK-INST: vmacc.vx v1, a0, v3 +// CHECK-ENCODING: [0xd7,0x60,0x35,0xb6] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 b6 + +vnmsac.vv v1, v2, v3, v0.t +// CHECK-INST: vnmsac.vv v1, v2, v3, v0.t +// CHECK-ENCODING: [0xd7,0x20,0x31,0xbc] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 bc + +vnmsac.vv v1, v2, v3 +// CHECK-INST: vnmsac.vv v1, v2, v3 +// CHECK-ENCODING: [0xd7,0x20,0x31,0xbe] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 be + +vnmsac.vx v1, a0, v3, v0.t +// CHECK-INST: vnmsac.vx v1, a0, v3, v0.t +// CHECK-ENCODING: [0xd7,0x60,0x35,0xbc] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 bc + +vnmsac.vx v1, a0, v3 +// CHECK-INST: vnmsac.vx v1, a0, v3 +// CHECK-ENCODING: [0xd7,0x60,0x35,0xbe] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 be + +vmadd.vv v1, v2, v3, v0.t +// CHECK-INST: vmadd.vv v1, v2, v3, v0.t +// CHECK-ENCODING: [0xd7,0x20,0x31,0xa4] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 a4 + +vmadd.vv v1, v2, v3 +// CHECK-INST: vmadd.vv v1, v2, v3 +// CHECK-ENCODING: [0xd7,0x20,0x31,0xa6] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 a6 + +vmadd.vx v1, a0, v3, v0.t +// CHECK-INST: vmadd.vx v1, a0, v3, v0.t +// CHECK-ENCODING: [0xd7,0x60,0x35,0xa4] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 a4 + +vmadd.vx v1, a0, v3 +// CHECK-INST: vmadd.vx v1, a0, v3 +// CHECK-ENCODING: [0xd7,0x60,0x35,0xa6] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 a6 + +vnmsub.vv v1, v2, v3, v0.t +// CHECK-INST: vnmsub.vv v1, v2, v3, v0.t +// CHECK-ENCODING: [0xd7,0x20,0x31,0xac] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 ac + +vnmsub.vv v1, v2, v3 +// CHECK-INST: vnmsub.vv v1, v2, v3 +// CHECK-ENCODING: [0xd7,0x20,0x31,0xae] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 ae + +vnmsub.vx v1, a0, v3, v0.t +// CHECK-INST: vnmsub.vx v1, a0, v3, v0.t +// CHECK-ENCODING: [0xd7,0x60,0x35,0xac] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 ac + +vnmsub.vx v1, a0, v3 +// CHECK-INST: vnmsub.vx v1, a0, v3 +// CHECK-ENCODING: [0xd7,0x60,0x35,0xae] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 ae + +vwmaccu.vv v1, v2, v3, v0.t +// CHECK-INST: vwmaccu.vv v1, v2, v3, v0.t +// CHECK-ENCODING: [0xd7,0x20,0x31,0xf0] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 f0 + +vwmaccu.vv v1, v2, v3 +// CHECK-INST: vwmaccu.vv v1, v2, v3 +// CHECK-ENCODING: [0xd7,0x20,0x31,0xf2] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 f2 + +vwmaccu.vx v1, a0, v3, v0.t +// CHECK-INST: vwmaccu.vx v1, a0, v3, v0.t +// CHECK-ENCODING: [0xd7,0x60,0x35,0xf0] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 f0 + +vwmaccu.vx v1, a0, v3 +// CHECK-INST: vwmaccu.vx v1, a0, v3 +// CHECK-ENCODING: [0xd7,0x60,0x35,0xf2] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 f2 + +vwmacc.vv v1, v2, v3, v0.t +// CHECK-INST: vwmacc.vv v1, v2, v3, v0.t +// CHECK-ENCODING: [0xd7,0x20,0x31,0xf4] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 f4 + +vwmacc.vv v1, v2, v3 +// CHECK-INST: vwmacc.vv v1, v2, v3 +// CHECK-ENCODING: [0xd7,0x20,0x31,0xf6] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 f6 + +vwmacc.vx v1, a0, v3, v0.t +// CHECK-INST: vwmacc.vx v1, a0, v3, v0.t +// CHECK-ENCODING: [0xd7,0x60,0x35,0xf4] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 f4 + +vwmacc.vx v1, a0, v3 +// CHECK-INST: vwmacc.vx v1, a0, v3 +// CHECK-ENCODING: [0xd7,0x60,0x35,0xf6] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 f6 + +vwmaccsu.vv v1, v2, v3, v0.t +// CHECK-INST: vwmaccsu.vv v1, v2, v3, v0.t +// CHECK-ENCODING: [0xd7,0x20,0x31,0xfc] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 fc + +vwmaccsu.vv v1, v2, v3 +// CHECK-INST: vwmaccsu.vv v1, v2, v3 +// CHECK-ENCODING: [0xd7,0x20,0x31,0xfe] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 fe + +vwmaccsu.vx v1, a0, v3, v0.t +// CHECK-INST: vwmaccsu.vx v1, a0, v3, v0.t +// CHECK-ENCODING: [0xd7,0x60,0x35,0xfc] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 fc + +vwmaccsu.vx v1, a0, v3 +// CHECK-INST: vwmaccsu.vx v1, a0, v3 +// CHECK-ENCODING: [0xd7,0x60,0x35,0xfe] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 fe + +vwmaccus.vx v1, a0, v3, v0.t +// CHECK-INST: vwmaccus.vx v1, a0, v3, v0.t +// CHECK-ENCODING: [0xd7,0x60,0x35,0xf8] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 f8 + +vwmaccus.vx v1, a0, v3 +// CHECK-INST: vwmaccus.vx v1, a0, v3 +// CHECK-ENCODING: [0xd7,0x60,0x35,0xfa] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 fa + +vwsmaccu.vv v1, v2, v3, v0.t +// CHECK-INST: vwsmaccu.vv v1, v2, v3, v0.t +// CHECK-ENCODING: [0xd7,0x00,0x31,0xf0] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 f0 + +vwsmaccu.vv v1, v2, v3 +// CHECK-INST: vwsmaccu.vv v1, v2, v3 +// CHECK-ENCODING: [0xd7,0x00,0x31,0xf2] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 f2 + +vwsmaccu.vx v1, a0, v3, v0.t +// CHECK-INST: vwsmaccu.vx v1, a0, v3, v0.t +// CHECK-ENCODING: [0xd7,0x40,0x35,0xf0] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 f0 + +vwsmaccu.vx v1, a0, v3 +// CHECK-INST: vwsmaccu.vx v1, a0, v3 +// CHECK-ENCODING: [0xd7,0x40,0x35,0xf2] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 f2 + +vwsmacc.vv v1, v2, v3, v0.t +// CHECK-INST: vwsmacc.vv v1, v2, v3, v0.t +// CHECK-ENCODING: [0xd7,0x00,0x31,0xf4] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 f4 + +vwsmacc.vv v1, v2, v3 +// CHECK-INST: vwsmacc.vv v1, v2, v3 +// CHECK-ENCODING: [0xd7,0x00,0x31,0xf6] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 f6 + +vwsmacc.vx v1, a0, v3, v0.t +// CHECK-INST: vwsmacc.vx v1, a0, v3, v0.t +// CHECK-ENCODING: [0xd7,0x40,0x35,0xf4] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 f4 + +vwsmacc.vx v1, a0, v3 +// CHECK-INST: vwsmacc.vx v1, a0, v3 +// CHECK-ENCODING: [0xd7,0x40,0x35,0xf6] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 f6 + +vwsmaccsu.vv v1, v2, v3, v0.t +// CHECK-INST: vwsmaccsu.vv v1, v2, v3, v0.t +// CHECK-ENCODING: [0xd7,0x00,0x31,0xfc] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 fc + +vwsmaccsu.vv v1, v2, v3 +// CHECK-INST: vwsmaccsu.vv v1, v2, v3 +// CHECK-ENCODING: [0xd7,0x00,0x31,0xfe] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 fe + +vwsmaccsu.vx v1, a0, v3, v0.t +// CHECK-INST: vwsmaccsu.vx v1, a0, v3, v0.t +// CHECK-ENCODING: [0xd7,0x40,0x35,0xfc] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 fc + +vwsmaccsu.vx v1, a0, v3 +// CHECK-INST: vwsmaccsu.vx v1, a0, v3 +// CHECK-ENCODING: [0xd7,0x40,0x35,0xfe] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 fe + +vwsmaccus.vx v1, a0, v3, v0.t +// CHECK-INST: vwsmaccus.vx v1, a0, v3, v0.t +// CHECK-ENCODING: [0xd7,0x40,0x35,0xf8] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 f8 + +vwsmaccus.vx v1, a0, v3 +// CHECK-INST: vwsmaccus.vx v1, a0, v3 +// CHECK-ENCODING: [0xd7,0x40,0x35,0xfa] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 fa + +vfmacc.vv v1, v2, v3, v0.t +// CHECK-INST: vfmacc.vv v1, v2, v3, v0.t +// CHECK-ENCODING: [0xd7,0x10,0x31,0xb0] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 b0 + +vfmacc.vv v1, v2, v3 +// CHECK-INST: vfmacc.vv v1, v2, v3 +// CHECK-ENCODING: [0xd7,0x10,0x31,0xb2] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 b2 + +vfmacc.vf v1, fa0, v3, v0.t +// CHECK-INST: vfmacc.vf v1, fa0, v3, v0.t +// CHECK-ENCODING: [0xd7,0x50,0x35,0xb0] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 b0 + +vfmacc.vf v1, fa0, v3 +// CHECK-INST: vfmacc.vf v1, fa0, v3 +// CHECK-ENCODING: [0xd7,0x50,0x35,0xb2] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 b2 + +vfnmacc.vv v1, v2, v3, v0.t +// CHECK-INST: vfnmacc.vv v1, v2, v3, v0.t +// CHECK-ENCODING: [0xd7,0x10,0x31,0xb4] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 b4 + +vfnmacc.vv v1, v2, v3 +// CHECK-INST: vfnmacc.vv v1, v2, v3 +// CHECK-ENCODING: [0xd7,0x10,0x31,0xb6] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 b6 + +vfnmacc.vf v1, fa0, v3, v0.t +// CHECK-INST: vfnmacc.vf v1, fa0, v3, v0.t +// CHECK-ENCODING: [0xd7,0x50,0x35,0xb4] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 b4 + +vfnmacc.vf v1, fa0, v3 +// CHECK-INST: vfnmacc.vf v1, fa0, v3 +// CHECK-ENCODING: [0xd7,0x50,0x35,0xb6] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 b6 + +vfmsac.vv v1, v2, v3, v0.t +// CHECK-INST: vfmsac.vv v1, v2, v3, v0.t +// CHECK-ENCODING: [0xd7,0x10,0x31,0xb8] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 b8 + +vfmsac.vv v1, v2, v3 +// CHECK-INST: vfmsac.vv v1, v2, v3 +// CHECK-ENCODING: [0xd7,0x10,0x31,0xba] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 ba + +vfmsac.vf v1, fa0, v3, v0.t +// CHECK-INST: vfmsac.vf v1, fa0, v3, v0.t +// CHECK-ENCODING: [0xd7,0x50,0x35,0xb8] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 b8 + +vfmsac.vf v1, fa0, v3 +// CHECK-INST: vfmsac.vf v1, fa0, v3 +// CHECK-ENCODING: [0xd7,0x50,0x35,0xba] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 ba + +vfnmsac.vv v1, v2, v3, v0.t +// CHECK-INST: vfnmsac.vv v1, v2, v3, v0.t +// CHECK-ENCODING: [0xd7,0x10,0x31,0xbc] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 bc + +vfnmsac.vv v1, v2, v3 +// CHECK-INST: vfnmsac.vv v1, v2, v3 +// CHECK-ENCODING: [0xd7,0x10,0x31,0xbe] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 be + +vfnmsac.vf v1, fa0, v3, v0.t +// CHECK-INST: vfnmsac.vf v1, fa0, v3, v0.t +// CHECK-ENCODING: [0xd7,0x50,0x35,0xbc] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 bc + +vfnmsac.vf v1, fa0, v3 +// CHECK-INST: vfnmsac.vf v1, fa0, v3 +// CHECK-ENCODING: [0xd7,0x50,0x35,0xbe] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 be + +vfmadd.vv v1, v2, v3, v0.t +// CHECK-INST: vfmadd.vv v1, v2, v3, v0.t +// CHECK-ENCODING: [0xd7,0x10,0x31,0xa0] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 a0 + +vfmadd.vv v1, v2, v3 +// CHECK-INST: vfmadd.vv v1, v2, v3 +// CHECK-ENCODING: [0xd7,0x10,0x31,0xa2] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 a2 + +vfmadd.vf v1, fa0, v3, v0.t +// CHECK-INST: vfmadd.vf v1, fa0, v3, v0.t +// CHECK-ENCODING: [0xd7,0x50,0x35,0xa0] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 a0 + +vfmadd.vf v1, fa0, v3 +// CHECK-INST: vfmadd.vf v1, fa0, v3 +// CHECK-ENCODING: [0xd7,0x50,0x35,0xa2] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 a2 + +vfnmadd.vv v1, v2, v3, v0.t +// CHECK-INST: vfnmadd.vv v1, v2, v3, v0.t +// CHECK-ENCODING: [0xd7,0x10,0x31,0xa4] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 a4 + +vfnmadd.vv v1, v2, v3 +// CHECK-INST: vfnmadd.vv v1, v2, v3 +// CHECK-ENCODING: [0xd7,0x10,0x31,0xa6] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 a6 + +vfnmadd.vf v1, fa0, v3, v0.t +// CHECK-INST: vfnmadd.vf v1, fa0, v3, v0.t +// CHECK-ENCODING: [0xd7,0x50,0x35,0xa4] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 a4 + +vfnmadd.vf v1, fa0, v3 +// CHECK-INST: vfnmadd.vf v1, fa0, v3 +// CHECK-ENCODING: [0xd7,0x50,0x35,0xa6] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 a6 + +vfmsub.vv v1, v2, v3, v0.t +// CHECK-INST: vfmsub.vv v1, v2, v3, v0.t +// CHECK-ENCODING: [0xd7,0x10,0x31,0xa8] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 a8 + +vfmsub.vv v1, v2, v3 +// CHECK-INST: vfmsub.vv v1, v2, v3 +// CHECK-ENCODING: [0xd7,0x10,0x31,0xaa] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 aa + +vfmsub.vf v1, fa0, v3, v0.t +// CHECK-INST: vfmsub.vf v1, fa0, v3, v0.t +// CHECK-ENCODING: [0xd7,0x50,0x35,0xa8] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 a8 + +vfmsub.vf v1, fa0, v3 +// CHECK-INST: vfmsub.vf v1, fa0, v3 +// CHECK-ENCODING: [0xd7,0x50,0x35,0xaa] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 aa + +vfnmsub.vv v1, v2, v3, v0.t +// CHECK-INST: vfnmsub.vv v1, v2, v3, v0.t +// CHECK-ENCODING: [0xd7,0x10,0x31,0xac] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 ac + +vfnmsub.vv v1, v2, v3 +// CHECK-INST: vfnmsub.vv v1, v2, v3 +// CHECK-ENCODING: [0xd7,0x10,0x31,0xae] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 ae + +vfnmsub.vf v1, fa0, v3, v0.t +// CHECK-INST: vfnmsub.vf v1, fa0, v3, v0.t +// CHECK-ENCODING: [0xd7,0x50,0x35,0xac] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 ac + +vfnmsub.vf v1, fa0, v3 +// CHECK-INST: vfnmsub.vf v1, fa0, v3 +// CHECK-ENCODING: [0xd7,0x50,0x35,0xae] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 ae + +vfwmacc.vv v1, v2, v3, v0.t +// CHECK-INST: vfwmacc.vv v1, v2, v3, v0.t +// CHECK-ENCODING: [0xd7,0x10,0x31,0xf0] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 f0 + +vfwmacc.vv v1, v2, v3 +// CHECK-INST: vfwmacc.vv v1, v2, v3 +// CHECK-ENCODING: [0xd7,0x10,0x31,0xf2] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 f2 + +vfwmacc.vf v1, fa0, v3, v0.t +// CHECK-INST: vfwmacc.vf v1, fa0, v3, v0.t +// CHECK-ENCODING: [0xd7,0x50,0x35,0xf0] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 f0 + +vfwmacc.vf v1, fa0, v3 +// CHECK-INST: vfwmacc.vf v1, fa0, v3 +// CHECK-ENCODING: [0xd7,0x50,0x35,0xf2] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 f2 + +vfwnmacc.vv v1, v2, v3, v0.t +// CHECK-INST: vfwnmacc.vv v1, v2, v3, v0.t +// CHECK-ENCODING: [0xd7,0x10,0x31,0xf4] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 f4 + +vfwnmacc.vv v1, v2, v3 +// CHECK-INST: vfwnmacc.vv v1, v2, v3 +// CHECK-ENCODING: [0xd7,0x10,0x31,0xf6] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 f6 + +vfwnmacc.vf v1, fa0, v3, v0.t +// CHECK-INST: vfwnmacc.vf v1, fa0, v3, v0.t +// CHECK-ENCODING: [0xd7,0x50,0x35,0xf4] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 f4 + +vfwnmacc.vf v1, fa0, v3 +// CHECK-INST: vfwnmacc.vf v1, fa0, v3 +// CHECK-ENCODING: [0xd7,0x50,0x35,0xf6] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 f6 + +vfwmsac.vv v1, v2, v3, v0.t +// CHECK-INST: vfwmsac.vv v1, v2, v3, v0.t +// CHECK-ENCODING: [0xd7,0x10,0x31,0xf8] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 f8 + +vfwmsac.vv v1, v2, v3 +// CHECK-INST: vfwmsac.vv v1, v2, v3 +// CHECK-ENCODING: [0xd7,0x10,0x31,0xfa] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 fa + +vfwmsac.vf v1, fa0, v3, v0.t +// CHECK-INST: vfwmsac.vf v1, fa0, v3, v0.t +// CHECK-ENCODING: [0xd7,0x50,0x35,0xf8] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 f8 + +vfwmsac.vf v1, fa0, v3 +// CHECK-INST: vfwmsac.vf v1, fa0, v3 +// CHECK-ENCODING: [0xd7,0x50,0x35,0xfa] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 fa + +vfwnmsac.vv v1, v2, v3, v0.t +// CHECK-INST: vfwnmsac.vv v1, v2, v3, v0.t +// CHECK-ENCODING: [0xd7,0x10,0x31,0xfc] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 fc + +vfwnmsac.vv v1, v2, v3 +// CHECK-INST: vfwnmsac.vv v1, v2, v3 +// CHECK-ENCODING: [0xd7,0x10,0x31,0xfe] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 fe + +vfwnmsac.vf v1, fa0, v3, v0.t +// CHECK-INST: vfwnmsac.vf v1, fa0, v3, v0.t +// CHECK-ENCODING: [0xd7,0x50,0x35,0xfc] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 fc + +vfwnmsac.vf v1, fa0, v3 +// CHECK-INST: vfwnmsac.vf v1, fa0, v3 +// CHECK-ENCODING: [0xd7,0x50,0x35,0xfe] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 fe Index: llvm/test/MC/RISCV/rvv/mask.s =================================================================== --- /dev/null +++ llvm/test/MC/RISCV/rvv/mask.s @@ -0,0 +1,139 @@ +// RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+v < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=riscv64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \ +// RUN: | llvm-objdump -d -mattr=+v - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +vmand.mm v1, v3, v2 +// CHECK-INST: vmand.mm v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x20,0x31,0x66] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 66 + +vmnand.mm v1, v3, v2 +// CHECK-INST: vmnand.mm v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x20,0x31,0x76] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 76 + +vmandnot.mm v1, v3, v2 +// CHECK-INST: vmandnot.mm v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x20,0x31,0x62] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 62 + +vmxor.mm v1, v3, v2 +// CHECK-INST: vmxor.mm v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x20,0x31,0x6e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 6e + +vmor.mm v1, v3, v2 +// CHECK-INST: vmor.mm v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x20,0x31,0x6a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 6a + +vmnor.mm v1, v3, v2 +// CHECK-INST: vmnor.mm v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x20,0x31,0x7a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 7a + +vmornot.mm v1, v3, v2 +// CHECK-INST: vmornot.mm v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x20,0x31,0x72] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 72 + +vmxnor.mm v1, v3, v2 +// CHECK-INST: vmxnor.mm v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x20,0x31,0x7e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 7e + +vpopc.m a2, v3, v0.t +// CHECK-INST: vpopc.m a2, v3, v0.t +// CHECK-ENCODING: [0x57,0x26,0x38,0x40] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 57 26 38 40 + +vpopc.m a2, v3 +// CHECK-INST: vpopc.m a2, v3 +// CHECK-ENCODING: [0x57,0x26,0x38,0x42] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 57 26 38 42 + +vfirst.m a2, v3, v0.t +// CHECK-INST: vfirst.m a2, v3, v0.t +// CHECK-ENCODING: [0x57,0xa6,0x38,0x40] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 57 a6 38 40 + +vfirst.m a2, v3 +// CHECK-INST: vfirst.m a2, v3 +// CHECK-ENCODING: [0x57,0xa6,0x38,0x42] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 57 a6 38 42 + +vmsbf.m v1, v3, v0.t +// CHECK-INST: vmsbf.m v1, v3, v0.t +// CHECK-ENCODING: [0xd7,0xa0,0x30,0x50] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 a0 30 50 + +vmsbf.m v1, v3 +// CHECK-INST: vmsbf.m v1, v3 +// CHECK-ENCODING: [0xd7,0xa0,0x30,0x52] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 a0 30 52 + +vmsif.m v1, v3, v0.t +// CHECK-INST: vmsif.m v1, v3, v0.t +// CHECK-ENCODING: [0xd7,0xa0,0x31,0x50] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 a0 31 50 + +vmsif.m v1, v3 +// CHECK-INST: vmsif.m v1, v3 +// CHECK-ENCODING: [0xd7,0xa0,0x31,0x52] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 a0 31 52 + +vmsof.m v1, v3, v0.t +// CHECK-INST: vmsof.m v1, v3, v0.t +// CHECK-ENCODING: [0xd7,0x20,0x31,0x50] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 50 + +vmsof.m v1, v3 +// CHECK-INST: vmsof.m v1, v3 +// CHECK-ENCODING: [0xd7,0x20,0x31,0x52] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 52 + +viota.m v1, v3, v0.t +// CHECK-INST: viota.m v1, v3, v0.t +// CHECK-ENCODING: [0xd7,0x20,0x38,0x50] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 38 50 + +viota.m v1, v3 +// CHECK-INST: viota.m v1, v3 +// CHECK-ENCODING: [0xd7,0x20,0x38,0x52] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 38 52 + +vid.v v1, v0.t +// CHECK-INST: vid.v v1, v0.t +// CHECK-ENCODING: [0xd7,0xa0,0x08,0x50] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 a0 08 50 + +vid.v v1 +// CHECK-INST: vid.v v1 +// CHECK-ENCODING: [0xd7,0xa0,0x08,0x52] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 a0 08 52 Index: llvm/test/MC/RISCV/rvv/minmax.s =================================================================== --- /dev/null +++ llvm/test/MC/RISCV/rvv/minmax.s @@ -0,0 +1,151 @@ +// RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+v < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=riscv64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \ +// RUN: | llvm-objdump -d -mattr=+v - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +vminu.vv v1, v3, v2, v0.t +// CHECK-INST: vminu.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x00,0x31,0x10] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 10 + +vminu.vv v1, v3, v2 +// CHECK-INST: vminu.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x00,0x31,0x12] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 12 + +vminu.vx v1, v3, a0, v0.t +// CHECK-INST: vminu.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x40,0x35,0x10] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 10 + +vminu.vx v1, v3, a0 +// CHECK-INST: vminu.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x40,0x35,0x12] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 12 + +vmin.vv v1, v3, v2, v0.t +// CHECK-INST: vmin.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x00,0x31,0x14] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 14 + +vmin.vv v1, v3, v2 +// CHECK-INST: vmin.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x00,0x31,0x16] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 16 + +vmin.vx v1, v3, a0, v0.t +// CHECK-INST: vmin.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x40,0x35,0x14] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 14 + +vmin.vx v1, v3, a0 +// CHECK-INST: vmin.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x40,0x35,0x16] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 16 + +vmaxu.vv v1, v3, v2, v0.t +// CHECK-INST: vmaxu.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x00,0x31,0x18] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 18 + +vmaxu.vv v1, v3, v2 +// CHECK-INST: vmaxu.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x00,0x31,0x1a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 1a + +vmaxu.vx v1, v3, a0, v0.t +// CHECK-INST: vmaxu.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x40,0x35,0x18] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 18 + +vmaxu.vx v1, v3, a0 +// CHECK-INST: vmaxu.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x40,0x35,0x1a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 1a + +vmax.vv v1, v3, v2, v0.t +// CHECK-INST: vmax.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x00,0x31,0x1c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 1c + +vmax.vv v1, v3, v2 +// CHECK-INST: vmax.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x00,0x31,0x1e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 1e + +vmax.vx v1, v3, a0, v0.t +// CHECK-INST: vmax.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x40,0x35,0x1c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 1c + +vmax.vx v1, v3, a0 +// CHECK-INST: vmax.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x40,0x35,0x1e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 1e + +vfmin.vv v1, v3, v2, v0.t +// CHECK-INST: vfmin.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x10,0x31,0x10] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 10 + +vfmin.vv v1, v3, v2 +// CHECK-INST: vfmin.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x10,0x31,0x12] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 12 + +vfmin.vf v1, v3, fa0, v0.t +// CHECK-INST: vfmin.vf v1, v3, fa0, v0.t +// CHECK-ENCODING: [0xd7,0x50,0x35,0x10] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 10 + +vfmin.vf v1, v3, fa0 +// CHECK-INST: vfmin.vf v1, v3, fa0 +// CHECK-ENCODING: [0xd7,0x50,0x35,0x12] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 12 + +vfmax.vv v1, v3, v2, v0.t +// CHECK-INST: vfmax.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x10,0x31,0x18] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 18 + +vfmax.vv v1, v3, v2 +// CHECK-INST: vfmax.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x10,0x31,0x1a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 1a + +vfmax.vf v1, v3, fa0, v0.t +// CHECK-INST: vfmax.vf v1, v3, fa0, v0.t +// CHECK-ENCODING: [0xd7,0x50,0x35,0x18] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 18 + +vfmax.vf v1, v3, fa0 +// CHECK-INST: vfmax.vf v1, v3, fa0 +// CHECK-ENCODING: [0xd7,0x50,0x35,0x1a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 1a Index: llvm/test/MC/RISCV/rvv/mul.s =================================================================== --- /dev/null +++ llvm/test/MC/RISCV/rvv/mul.s @@ -0,0 +1,247 @@ +// RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+v < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=riscv64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \ +// RUN: | llvm-objdump -d -mattr=+v - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +vmul.vv v1, v3, v2, v0.t +// CHECK-INST: vmul.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x20,0x31,0x94] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 94 + +vmul.vv v1, v3, v2 +// CHECK-INST: vmul.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x20,0x31,0x96] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 96 + +vmul.vx v1, v3, a0, v0.t +// CHECK-INST: vmul.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x60,0x35,0x94] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 94 + +vmul.vx v1, v3, a0 +// CHECK-INST: vmul.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x60,0x35,0x96] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 96 + +vmulh.vv v1, v3, v2, v0.t +// CHECK-INST: vmulh.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x20,0x31,0x9c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 9c + +vmulh.vv v1, v3, v2 +// CHECK-INST: vmulh.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x20,0x31,0x9e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 9e + +vmulh.vx v1, v3, a0, v0.t +// CHECK-INST: vmulh.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x60,0x35,0x9c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 9c + +vmulh.vx v1, v3, a0 +// CHECK-INST: vmulh.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x60,0x35,0x9e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 9e + +vmulhu.vv v1, v3, v2, v0.t +// CHECK-INST: vmulhu.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x20,0x31,0x90] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 90 + +vmulhu.vv v1, v3, v2 +// CHECK-INST: vmulhu.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x20,0x31,0x92] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 92 + +vmulhu.vx v1, v3, a0, v0.t +// CHECK-INST: vmulhu.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x60,0x35,0x90] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 90 + +vmulhu.vx v1, v3, a0 +// CHECK-INST: vmulhu.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x60,0x35,0x92] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 92 + +vmulhsu.vv v1, v3, v2, v0.t +// CHECK-INST: vmulhsu.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x20,0x31,0x98] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 98 + +vmulhsu.vv v1, v3, v2 +// CHECK-INST: vmulhsu.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x20,0x31,0x9a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 9a + +vmulhsu.vx v1, v3, a0, v0.t +// CHECK-INST: vmulhsu.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x60,0x35,0x98] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 98 + +vmulhsu.vx v1, v3, a0 +// CHECK-INST: vmulhsu.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x60,0x35,0x9a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 9a + +vwmul.vv v1, v3, v2, v0.t +// CHECK-INST: vwmul.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x20,0x31,0xec] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 ec + +vwmul.vv v1, v3, v2 +// CHECK-INST: vwmul.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x20,0x31,0xee] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 ee + +vwmul.vx v1, v3, a0, v0.t +// CHECK-INST: vwmul.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x60,0x35,0xec] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 ec + +vwmul.vx v1, v3, a0 +// CHECK-INST: vwmul.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x60,0x35,0xee] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 ee + +vwmulu.vv v1, v3, v2, v0.t +// CHECK-INST: vwmulu.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x20,0x31,0xe0] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 e0 + +vwmulu.vv v1, v3, v2 +// CHECK-INST: vwmulu.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x20,0x31,0xe2] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 e2 + +vwmulu.vx v1, v3, a0, v0.t +// CHECK-INST: vwmulu.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x60,0x35,0xe0] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 e0 + +vwmulu.vx v1, v3, a0 +// CHECK-INST: vwmulu.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x60,0x35,0xe2] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 e2 + +vwmulsu.vv v1, v3, v2, v0.t +// CHECK-INST: vwmulsu.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x20,0x31,0xe8] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 e8 + +vwmulsu.vv v1, v3, v2 +// CHECK-INST: vwmulsu.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x20,0x31,0xea] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 ea + +vwmulsu.vx v1, v3, a0, v0.t +// CHECK-INST: vwmulsu.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x60,0x35,0xe8] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 e8 + +vwmulsu.vx v1, v3, a0 +// CHECK-INST: vwmulsu.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x60,0x35,0xea] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 ea + +vsmul.vv v1, v3, v2, v0.t +// CHECK-INST: vsmul.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x00,0x31,0x9c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 9c + +vsmul.vv v1, v3, v2 +// CHECK-INST: vsmul.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x00,0x31,0x9e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 9e + +vsmul.vx v1, v3, a0, v0.t +// CHECK-INST: vsmul.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x40,0x35,0x9c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 9c + +vsmul.vx v1, v3, a0 +// CHECK-INST: vsmul.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x40,0x35,0x9e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 9e + +vfmul.vv v1, v3, v2, v0.t +// CHECK-INST: vfmul.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x10,0x31,0x90] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 90 + +vfmul.vv v1, v3, v2 +// CHECK-INST: vfmul.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x10,0x31,0x92] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 92 + +vfmul.vf v1, v3, fa0, v0.t +// CHECK-INST: vfmul.vf v1, v3, fa0, v0.t +// CHECK-ENCODING: [0xd7,0x50,0x35,0x90] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 90 + +vfmul.vf v1, v3, fa0 +// CHECK-INST: vfmul.vf v1, v3, fa0 +// CHECK-ENCODING: [0xd7,0x50,0x35,0x92] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 92 + +vfwmul.vv v1, v3, v2, v0.t +// CHECK-INST: vfwmul.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x10,0x31,0xe0] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 e0 + +vfwmul.vv v1, v3, v2 +// CHECK-INST: vfwmul.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x10,0x31,0xe2] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 e2 + +vfwmul.vf v1, v3, fa0, v0.t +// CHECK-INST: vfwmul.vf v1, v3, fa0, v0.t +// CHECK-ENCODING: [0xd7,0x50,0x35,0xe0] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 e0 + +vfwmul.vf v1, v3, fa0 +// CHECK-INST: vfwmul.vf v1, v3, fa0 +// CHECK-ENCODING: [0xd7,0x50,0x35,0xe2] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 e2 Index: llvm/test/MC/RISCV/rvv/mv.s =================================================================== --- /dev/null +++ llvm/test/MC/RISCV/rvv/mv.s @@ -0,0 +1,55 @@ +// RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+v < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=riscv64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \ +// RUN: | llvm-objdump -d -mattr=+v - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +vmv.v.v v1, v2 +// CHECK-INST: vmv.v.v v1, v2 +// CHECK-ENCODING: [0xd7,0x00,0x01,0x5e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 01 5e + +vmv.v.x v1, a0 +// CHECK-INST: vmv.v.x v1, a0 +// CHECK-ENCODING: [0xd7,0x40,0x05,0x5e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 05 5e + +vmv.v.i v1, 15 +// CHECK-INST: vmv.v.i v1, 15 +// CHECK-ENCODING: [0xd7,0xb0,0x07,0x5e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 07 5e + +vmv.x.s a2, v3 +// CHECK-INST: vmv.x.s a2, v3 +// CHECK-ENCODING: [0x57,0x26,0x30,0x42] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 57 26 30 42 + +vmv.s.x v1, a0 +// CHECK-INST: vmv.s.x v1, a0 +// CHECK-ENCODING: [0xd7,0x60,0x05,0x42] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 05 42 + +vfmv.v.f v1, fa0 +// CHECK-INST: vfmv.v.f v1, fa0 +// CHECK-ENCODING: [0xd7,0x50,0x05,0x5e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 05 5e + +vfmv.f.s fa0, v3 +// CHECK-INST: vfmv.f.s fa0, v3 +// CHECK-ENCODING: [0x57,0x15,0x30,0x42] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 57 15 30 42 + +vfmv.s.f v1, fa0 +// CHECK-INST: vfmv.s.f v1, fa0 +// CHECK-ENCODING: [0xd7,0x50,0x05,0x42] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 05 42 Index: llvm/test/MC/RISCV/rvv/or.s =================================================================== --- /dev/null +++ llvm/test/MC/RISCV/rvv/or.s @@ -0,0 +1,43 @@ +// RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+v < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=riscv64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \ +// RUN: | llvm-objdump -d -mattr=+v - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +vor.vv v1, v3, v2, v0.t +// CHECK-INST: vor.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x00,0x31,0x28] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 28 + +vor.vv v1, v3, v2 +// CHECK-INST: vor.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x00,0x31,0x2a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 2a + +vor.vx v1, v3, a0, v0.t +// CHECK-INST: vor.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x40,0x35,0x28] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 28 + +vor.vx v1, v3, a0 +// CHECK-INST: vor.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x40,0x35,0x2a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 2a + +vor.vi v1, v3, 15, v0.t +// CHECK-INST: vor.vi v1, v3, 15, v0.t +// CHECK-ENCODING: [0xd7,0xb0,0x37,0x28] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 37 28 + +vor.vi v1, v3, 15 +// CHECK-INST: vor.vi v1, v3, 15 +// CHECK-ENCODING: [0xd7,0xb0,0x37,0x2a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 37 2a Index: llvm/test/MC/RISCV/rvv/others.s =================================================================== --- /dev/null +++ llvm/test/MC/RISCV/rvv/others.s @@ -0,0 +1,169 @@ +// RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+v < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=riscv64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \ +// RUN: | llvm-objdump -d -mattr=+v - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +vmerge.vvm v1, v3, v2, v0 +// CHECK-INST: vmerge.vvm v1, v3, v2, v0 +// CHECK-ENCODING: [0xd7,0x00,0x31,0x5c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 5c + +vmerge.vxm v1, v3, a0, v0 +// CHECK-INST: vmerge.vxm v1, v3, a0, v0 +// CHECK-ENCODING: [0xd7,0x40,0x35,0x5c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 5c + +vmerge.vim v1, v3, 15, v0 +// CHECK-INST: vmerge.vim v1, v3, 15, v0 +// CHECK-ENCODING: [0xd7,0xb0,0x37,0x5c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 37 5c + +vslideup.vx v1, v3, a0, v0.t +// CHECK-INST: vslideup.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x40,0x35,0x38] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 38 + +vslideup.vx v1, v3, a0 +// CHECK-INST: vslideup.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x40,0x35,0x3a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 3a + +vslideup.vi v1, v3, 31, v0.t +// CHECK-INST: vslideup.vi v1, v3, 31, v0.t +// CHECK-ENCODING: [0xd7,0xb0,0x3f,0x38] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 3f 38 + +vslideup.vi v1, v3, 31 +// CHECK-INST: vslideup.vi v1, v3, 31 +// CHECK-ENCODING: [0xd7,0xb0,0x3f,0x3a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 3f 3a + +vslidedown.vx v1, v3, a0, v0.t +// CHECK-INST: vslidedown.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x40,0x35,0x3c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 3c + +vslidedown.vx v1, v3, a0 +// CHECK-INST: vslidedown.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x40,0x35,0x3e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 3e + +vslidedown.vi v1, v3, 31, v0.t +// CHECK-INST: vslidedown.vi v1, v3, 31, v0.t +// CHECK-ENCODING: [0xd7,0xb0,0x3f,0x3c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 3f 3c + +vslidedown.vi v1, v3, 31 +// CHECK-INST: vslidedown.vi v1, v3, 31 +// CHECK-ENCODING: [0xd7,0xb0,0x3f,0x3e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 3f 3e + +vslide1up.vx v1, v3, a0, v0.t +// CHECK-INST: vslide1up.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x60,0x35,0x38] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 38 + +vslide1up.vx v1, v3, a0 +// CHECK-INST: vslide1up.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x60,0x35,0x3a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 3a + +vslide1down.vx v1, v3, a0, v0.t +// CHECK-INST: vslide1down.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x60,0x35,0x3c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 3c + +vslide1down.vx v1, v3, a0 +// CHECK-INST: vslide1down.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x60,0x35,0x3e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 3e + +vrgather.vv v1, v3, v2, v0.t +// CHECK-INST: vrgather.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x00,0x31,0x30] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 30 + +vrgather.vv v1, v3, v2 +// CHECK-INST: vrgather.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x00,0x31,0x32] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 32 + +vrgather.vx v1, v3, a0, v0.t +// CHECK-INST: vrgather.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x40,0x35,0x30] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 30 + +vrgather.vx v1, v3, a0 +// CHECK-INST: vrgather.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x40,0x35,0x32] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 32 + +vrgather.vi v1, v3, 31, v0.t +// CHECK-INST: vrgather.vi v1, v3, 31, v0.t +// CHECK-ENCODING: [0xd7,0xb0,0x3f,0x30] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 3f 30 + +vrgather.vi v1, v3, 31 +// CHECK-INST: vrgather.vi v1, v3, 31 +// CHECK-ENCODING: [0xd7,0xb0,0x3f,0x32] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 3f 32 + +vcompress.vm v1, v3, v2 +// CHECK-INST: vcompress.vm v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x20,0x31,0x5e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 5e + +vfsqrt.v v1, v3, v0.t +// CHECK-INST: vfsqrt.v v1, v3, v0.t +// CHECK-ENCODING: [0xd7,0x10,0x30,0x8c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 30 8c + +vfsqrt.v v1, v3 +// CHECK-INST: vfsqrt.v v1, v3 +// CHECK-ENCODING: [0xd7,0x10,0x30,0x8e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 30 8e + +vfclass.v v1, v3, v0.t +// CHECK-INST: vfclass.v v1, v3, v0.t +// CHECK-ENCODING: [0xd7,0x10,0x38,0x8c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 38 8c + +vfclass.v v1, v3 +// CHECK-INST: vfclass.v v1, v3 +// CHECK-ENCODING: [0xd7,0x10,0x38,0x8e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 38 8e + +vfmerge.vfm v1, v3, fa0, v0 +// CHECK-INST: vfmerge.vfm v1, v3, fa0, v0 +// CHECK-ENCODING: [0xd7,0x50,0x35,0x5c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 5c Index: llvm/test/MC/RISCV/rvv/reduction.s =================================================================== --- /dev/null +++ llvm/test/MC/RISCV/rvv/reduction.s @@ -0,0 +1,199 @@ +// RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+v < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=riscv64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \ +// RUN: | llvm-objdump -d -mattr=+v - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +vredsum.vs v1, v3, v2, v0.t +// CHECK-INST: vredsum.vs v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x20,0x31,0x00] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 00 + +vredsum.vs v1, v3, v2 +// CHECK-INST: vredsum.vs v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x20,0x31,0x02] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 02 + +vredmaxu.vs v1, v3, v2, v0.t +// CHECK-INST: vredmaxu.vs v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x20,0x31,0x18] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 18 + +vredmaxu.vs v1, v3, v2 +// CHECK-INST: vredmaxu.vs v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x20,0x31,0x1a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 1a + +vredmax.vs v1, v3, v2, v0.t +// CHECK-INST: vredmax.vs v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x20,0x31,0x1c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 1c + +vredmax.vs v1, v3, v2 +// CHECK-INST: vredmax.vs v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x20,0x31,0x1e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 1e + +vredminu.vs v1, v3, v2, v0.t +// CHECK-INST: vredminu.vs v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x20,0x31,0x10] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 10 + +vredminu.vs v1, v3, v2 +// CHECK-INST: vredminu.vs v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x20,0x31,0x12] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 12 + +vredmin.vs v1, v3, v2, v0.t +// CHECK-INST: vredmin.vs v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x20,0x31,0x14] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 14 + +vredmin.vs v1, v3, v2 +// CHECK-INST: vredmin.vs v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x20,0x31,0x16] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 16 + +vredand.vs v1, v3, v2, v0.t +// CHECK-INST: vredand.vs v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x20,0x31,0x04] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 04 + +vredand.vs v1, v3, v2 +// CHECK-INST: vredand.vs v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x20,0x31,0x06] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 06 + +vredor.vs v1, v3, v2, v0.t +// CHECK-INST: vredor.vs v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x20,0x31,0x08] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 08 + +vredor.vs v1, v3, v2 +// CHECK-INST: vredor.vs v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x20,0x31,0x0a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 0a + +vredxor.vs v1, v3, v2, v0.t +// CHECK-INST: vredxor.vs v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x20,0x31,0x0c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 0c + +vredxor.vs v1, v3, v2 +// CHECK-INST: vredxor.vs v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x20,0x31,0x0e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 0e + +vwredsumu.vs v1, v3, v2, v0.t +// CHECK-INST: vwredsumu.vs v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x00,0x31,0xc0] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 c0 + +vwredsumu.vs v1, v3, v2 +// CHECK-INST: vwredsumu.vs v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x00,0x31,0xc2] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 c2 + +vwredsum.vs v1, v3, v2, v0.t +// CHECK-INST: vwredsum.vs v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x00,0x31,0xc4] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 c4 + +vwredsum.vs v1, v3, v2 +// CHECK-INST: vwredsum.vs v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x00,0x31,0xc6] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 c6 + +vfredosum.vs v1, v3, v2, v0.t +// CHECK-INST: vfredosum.vs v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x10,0x31,0x0c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 0c + +vfredosum.vs v1, v3, v2 +// CHECK-INST: vfredosum.vs v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x10,0x31,0x0e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 0e + +vfredsum.vs v1, v3, v2, v0.t +// CHECK-INST: vfredsum.vs v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x10,0x31,0x04] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 04 + +vfredsum.vs v1, v3, v2 +// CHECK-INST: vfredsum.vs v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x10,0x31,0x06] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 06 + +vfredmax.vs v1, v3, v2, v0.t +// CHECK-INST: vfredmax.vs v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x10,0x31,0x1c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 1c + +vfredmax.vs v1, v3, v2 +// CHECK-INST: vfredmax.vs v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x10,0x31,0x1e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 1e + +vfredmin.vs v1, v3, v2, v0.t +// CHECK-INST: vfredmin.vs v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x10,0x31,0x14] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 14 + +vfredmin.vs v1, v3, v2 +// CHECK-INST: vfredmin.vs v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x10,0x31,0x16] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 16 + +vfwredosum.vs v1, v3, v2, v0.t +// CHECK-INST: vfwredosum.vs v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x10,0x31,0xcc] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 cc + +vfwredosum.vs v1, v3, v2 +// CHECK-INST: vfwredosum.vs v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x10,0x31,0xce] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 ce + +vfwredsum.vs v1, v3, v2, v0.t +// CHECK-INST: vfwredsum.vs v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x10,0x31,0xc4] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 c4 + +vfwredsum.vs v1, v3, v2 +// CHECK-INST: vfwredsum.vs v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x10,0x31,0xc6] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 c6 Index: llvm/test/MC/RISCV/rvv/shift.s =================================================================== --- /dev/null +++ llvm/test/MC/RISCV/rvv/shift.s @@ -0,0 +1,259 @@ +// RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+v < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=riscv64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \ +// RUN: | llvm-objdump -d -mattr=+v - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +vsll.vv v1, v3, v2, v0.t +// CHECK-INST: vsll.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x00,0x31,0x94] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 94 + +vsll.vv v1, v3, v2 +// CHECK-INST: vsll.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x00,0x31,0x96] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 96 + +vsll.vx v1, v3, a0, v0.t +// CHECK-INST: vsll.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x40,0x35,0x94] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 94 + +vsll.vx v1, v3, a0 +// CHECK-INST: vsll.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x40,0x35,0x96] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 96 + +vsll.vi v1, v3, 31, v0.t +// CHECK-INST: vsll.vi v1, v3, 31, v0.t +// CHECK-ENCODING: [0xd7,0xb0,0x3f,0x94] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 3f 94 + +vsll.vi v1, v3, 31 +// CHECK-INST: vsll.vi v1, v3, 31 +// CHECK-ENCODING: [0xd7,0xb0,0x3f,0x96] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 3f 96 + +vsrl.vv v1, v3, v2, v0.t +// CHECK-INST: vsrl.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x00,0x31,0xa0] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 a0 + +vsrl.vv v1, v3, v2 +// CHECK-INST: vsrl.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x00,0x31,0xa2] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 a2 + +vsrl.vx v1, v3, a0, v0.t +// CHECK-INST: vsrl.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x40,0x35,0xa0] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 a0 + +vsrl.vx v1, v3, a0 +// CHECK-INST: vsrl.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x40,0x35,0xa2] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 a2 + +vsrl.vi v1, v3, 31, v0.t +// CHECK-INST: vsrl.vi v1, v3, 31, v0.t +// CHECK-ENCODING: [0xd7,0xb0,0x3f,0xa0] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 3f a0 + +vsrl.vi v1, v3, 31 +// CHECK-INST: vsrl.vi v1, v3, 31 +// CHECK-ENCODING: [0xd7,0xb0,0x3f,0xa2] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 3f a2 + +vsra.vv v1, v3, v2, v0.t +// CHECK-INST: vsra.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x00,0x31,0xa4] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 a4 + +vsra.vv v1, v3, v2 +// CHECK-INST: vsra.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x00,0x31,0xa6] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 a6 + +vsra.vx v1, v3, a0, v0.t +// CHECK-INST: vsra.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x40,0x35,0xa4] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 a4 + +vsra.vx v1, v3, a0 +// CHECK-INST: vsra.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x40,0x35,0xa6] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 a6 + +vsra.vi v1, v3, 31, v0.t +// CHECK-INST: vsra.vi v1, v3, 31, v0.t +// CHECK-ENCODING: [0xd7,0xb0,0x3f,0xa4] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 3f a4 + +vsra.vi v1, v3, 31 +// CHECK-INST: vsra.vi v1, v3, 31 +// CHECK-ENCODING: [0xd7,0xb0,0x3f,0xa6] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 3f a6 + +vnsrl.wv v1, v3, v2, v0.t +// CHECK-INST: vnsrl.wv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x00,0x31,0xb0] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 b0 + +vnsrl.wv v1, v3, v2 +// CHECK-INST: vnsrl.wv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x00,0x31,0xb2] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 b2 + +vnsrl.wx v1, v3, a0, v0.t +// CHECK-INST: vnsrl.wx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x40,0x35,0xb0] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 b0 + +vnsrl.wx v1, v3, a0 +// CHECK-INST: vnsrl.wx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x40,0x35,0xb2] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 b2 + +vnsrl.wi v1, v3, 31, v0.t +// CHECK-INST: vnsrl.wi v1, v3, 31, v0.t +// CHECK-ENCODING: [0xd7,0xb0,0x3f,0xb0] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 3f b0 + +vnsrl.wi v1, v3, 31 +// CHECK-INST: vnsrl.wi v1, v3, 31 +// CHECK-ENCODING: [0xd7,0xb0,0x3f,0xb2] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 3f b2 + +vnsra.wv v1, v3, v2, v0.t +// CHECK-INST: vnsra.wv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x00,0x31,0xb4] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 b4 + +vnsra.wv v1, v3, v2 +// CHECK-INST: vnsra.wv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x00,0x31,0xb6] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 b6 + +vnsra.wx v1, v3, a0, v0.t +// CHECK-INST: vnsra.wx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x40,0x35,0xb4] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 b4 + +vnsra.wx v1, v3, a0 +// CHECK-INST: vnsra.wx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x40,0x35,0xb6] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 b6 + +vnsra.wi v1, v3, 31, v0.t +// CHECK-INST: vnsra.wi v1, v3, 31, v0.t +// CHECK-ENCODING: [0xd7,0xb0,0x3f,0xb4] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 3f b4 + +vnsra.wi v1, v3, 31 +// CHECK-INST: vnsra.wi v1, v3, 31 +// CHECK-ENCODING: [0xd7,0xb0,0x3f,0xb6] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 3f b6 + +vssrl.vv v1, v3, v2, v0.t +// CHECK-INST: vssrl.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x00,0x31,0xa8] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 a8 + +vssrl.vv v1, v3, v2 +// CHECK-INST: vssrl.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x00,0x31,0xaa] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 aa + +vssrl.vx v1, v3, a0, v0.t +// CHECK-INST: vssrl.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x40,0x35,0xa8] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 a8 + +vssrl.vx v1, v3, a0 +// CHECK-INST: vssrl.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x40,0x35,0xaa] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 aa + +vssrl.vi v1, v3, 31, v0.t +// CHECK-INST: vssrl.vi v1, v3, 31, v0.t +// CHECK-ENCODING: [0xd7,0xb0,0x3f,0xa8] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 3f a8 + +vssrl.vi v1, v3, 31 +// CHECK-INST: vssrl.vi v1, v3, 31 +// CHECK-ENCODING: [0xd7,0xb0,0x3f,0xaa] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 3f aa + +vssra.vv v1, v3, v2, v0.t +// CHECK-INST: vssra.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x00,0x31,0xac] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 ac + +vssra.vv v1, v3, v2 +// CHECK-INST: vssra.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x00,0x31,0xae] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 ae + +vssra.vx v1, v3, a0, v0.t +// CHECK-INST: vssra.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x40,0x35,0xac] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 ac + +vssra.vx v1, v3, a0 +// CHECK-INST: vssra.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x40,0x35,0xae] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 ae + +vssra.vi v1, v3, 31, v0.t +// CHECK-INST: vssra.vi v1, v3, 31, v0.t +// CHECK-ENCODING: [0xd7,0xb0,0x3f,0xac] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 3f ac + +vssra.vi v1, v3, 31 +// CHECK-INST: vssra.vi v1, v3, 31 +// CHECK-ENCODING: [0xd7,0xb0,0x3f,0xae] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 3f ae Index: llvm/test/MC/RISCV/rvv/sign-injection.s =================================================================== --- /dev/null +++ llvm/test/MC/RISCV/rvv/sign-injection.s @@ -0,0 +1,79 @@ +// RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+v < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=riscv64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \ +// RUN: | llvm-objdump -d -mattr=+v - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +vfsgnj.vv v1, v3, v2, v0.t +// CHECK-INST: vfsgnj.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x10,0x31,0x20] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 20 + +vfsgnj.vv v1, v3, v2 +// CHECK-INST: vfsgnj.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x10,0x31,0x22] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 22 + +vfsgnj.vf v1, v3, fa0, v0.t +// CHECK-INST: vfsgnj.vf v1, v3, fa0, v0.t +// CHECK-ENCODING: [0xd7,0x50,0x35,0x20] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 20 + +vfsgnj.vf v1, v3, fa0 +// CHECK-INST: vfsgnj.vf v1, v3, fa0 +// CHECK-ENCODING: [0xd7,0x50,0x35,0x22] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 22 + +vfsgnjn.vv v1, v3, v2, v0.t +// CHECK-INST: vfsgnjn.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x10,0x31,0x24] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 24 + +vfsgnjn.vv v1, v3, v2 +// CHECK-INST: vfsgnjn.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x10,0x31,0x26] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 26 + +vfsgnjn.vf v1, v3, fa0, v0.t +// CHECK-INST: vfsgnjn.vf v1, v3, fa0, v0.t +// CHECK-ENCODING: [0xd7,0x50,0x35,0x24] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 24 + +vfsgnjn.vf v1, v3, fa0 +// CHECK-INST: vfsgnjn.vf v1, v3, fa0 +// CHECK-ENCODING: [0xd7,0x50,0x35,0x26] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 26 + +vfsgnjx.vv v1, v3, v2, v0.t +// CHECK-INST: vfsgnjx.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x10,0x31,0x28] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 28 + +vfsgnjx.vv v1, v3, v2 +// CHECK-INST: vfsgnjx.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x10,0x31,0x2a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 2a + +vfsgnjx.vf v1, v3, fa0, v0.t +// CHECK-INST: vfsgnjx.vf v1, v3, fa0, v0.t +// CHECK-ENCODING: [0xd7,0x50,0x35,0x28] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 28 + +vfsgnjx.vf v1, v3, fa0 +// CHECK-INST: vfsgnjx.vf v1, v3, fa0 +// CHECK-ENCODING: [0xd7,0x50,0x35,0x2a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 2a Index: llvm/test/MC/RISCV/rvv/snippet.s =================================================================== --- /dev/null +++ llvm/test/MC/RISCV/rvv/snippet.s @@ -0,0 +1,31 @@ +// A snippet from https://github.com/riscv/riscv-v-spec. +// +// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \ +// RUN: | llvm-objdump -d -mattr=+v - | FileCheck %s --check-prefix=CHECK-INST + +loop: + vsetvli a3, a0, e16,m4 # vtype = 16-bit integer vectors +// CHECK-INST: d7 76 65 00 vsetvli a3, a0, e16,m4 + vlh.v v4, (a1) # Get 16b vector +// CHECK-INST: 07 d2 05 12 vlh.v v4, (a1) + slli t1, a3, 1 # Multiply length by two bytes/element +// CHECK-INST: 13 93 16 00 slli t1, a3, 1 + add a1, a1, t1 # Bump pointer +// CHECK-INST: b3 85 65 00 add a1, a1, t1 + vwmul.vx v8, v4, x10 # 32b in +// CHECK-INST: 57 64 45 ee vwmul.vx v8, v4, a0 + + vsetvli x0, a0, e32,m8 # Operate on 32b values +// CHECK-INST: 57 70 b5 00 vsetvli zero, a0, e32,m8 + vsrl.vi v8, v8, 3 +// CHECK-INST: 57 b4 81 a2 vsrl.vi v8, v8, 3 + vsw.v v8, (a2) # Store vector of 32b +// CHECK-INST: 27 64 06 02 vsw.v v8, (a2) + slli t1, a3, 2 # Multiply length by four bytes/element +// CHECK-INST: 13 93 26 00 slli t1, a3, 2 + add a2, a2, t1 # Bump pointer +// CHECK-INST: 33 06 66 00 add a2, a2, t1 + sub a0, a0, a3 # Decrement count +// CHECK-INST: 33 05 d5 40 sub a0, a0, a3 + bnez a0, loop # Any more? +// CHECK-INST: e3 1a 05 fc bnez a0, -44 Index: llvm/test/MC/RISCV/rvv/store.s =================================================================== --- /dev/null +++ llvm/test/MC/RISCV/rvv/store.s @@ -0,0 +1,199 @@ +// RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+v < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=riscv64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \ +// RUN: | llvm-objdump -d -mattr=+v - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +vsb.v v4, (a0), v0.t +// CHECK-INST: vsb.v v4, (a0), v0.t +// CHECK-ENCODING: [0x27,0x02,0x05,0x00] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 27 02 05 00 + +vsb.v v4, (a0) +// CHECK-INST: vsb.v v4, (a0) +// CHECK-ENCODING: [0x27,0x02,0x05,0x02] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 27 02 05 02 + +vsh.v v4, (a0), v0.t +// CHECK-INST: vsh.v v4, (a0), v0.t +// CHECK-ENCODING: [0x27,0x52,0x05,0x00] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 27 52 05 00 + +vsh.v v4, (a0) +// CHECK-INST: vsh.v v4, (a0) +// CHECK-ENCODING: [0x27,0x52,0x05,0x02] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 27 52 05 02 + +vsw.v v4, (a0), v0.t +// CHECK-INST: vsw.v v4, (a0), v0.t +// CHECK-ENCODING: [0x27,0x62,0x05,0x00] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 27 62 05 00 + +vsw.v v4, (a0) +// CHECK-INST: vsw.v v4, (a0) +// CHECK-ENCODING: [0x27,0x62,0x05,0x02] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 27 62 05 02 + +vse.v v4, (a0), v0.t +// CHECK-INST: vse.v v4, (a0), v0.t +// CHECK-ENCODING: [0x27,0x72,0x05,0x00] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 27 72 05 00 + +vse.v v4, (a0) +// CHECK-INST: vse.v v4, (a0) +// CHECK-ENCODING: [0x27,0x72,0x05,0x02] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 27 72 05 02 + +vssb.v v4, (a0), a1, v0.t +// CHECK-INST: vssb.v v4, (a0), a1, v0.t +// CHECK-ENCODING: [0x27,0x02,0xb5,0x08] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 27 02 b5 08 + +vssb.v v4, (a0), a1 +// CHECK-INST: vssb.v v4, (a0), a1 +// CHECK-ENCODING: [0x27,0x02,0xb5,0x0a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 27 02 b5 0a + +vssh.v v4, (a0), a1, v0.t +// CHECK-INST: vssh.v v4, (a0), a1, v0.t +// CHECK-ENCODING: [0x27,0x52,0xb5,0x08] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 27 52 b5 08 + +vssh.v v4, (a0), a1 +// CHECK-INST: vssh.v v4, (a0), a1 +// CHECK-ENCODING: [0x27,0x52,0xb5,0x0a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 27 52 b5 0a + +vssw.v v4, (a0), a1, v0.t +// CHECK-INST: vssw.v v4, (a0), a1, v0.t +// CHECK-ENCODING: [0x27,0x62,0xb5,0x08] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 27 62 b5 08 + +vssw.v v4, (a0), a1 +// CHECK-INST: vssw.v v4, (a0), a1 +// CHECK-ENCODING: [0x27,0x62,0xb5,0x0a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 27 62 b5 0a + +vsse.v v4, (a0), a1, v0.t +// CHECK-INST: vsse.v v4, (a0), a1, v0.t +// CHECK-ENCODING: [0x27,0x72,0xb5,0x08] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 27 72 b5 08 + +vsse.v v4, (a0), a1 +// CHECK-INST: vsse.v v4, (a0), a1 +// CHECK-ENCODING: [0x27,0x72,0xb5,0x0a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 27 72 b5 0a + +vsxb.v v4, (a0), v3, v0.t +// CHECK-INST: vsxb.v v4, (a0), v3, v0.t +// CHECK-ENCODING: [0x27,0x02,0x35,0x0c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 27 02 35 0c + +vsxb.v v4, (a0), v3 +// CHECK-INST: vsxb.v v4, (a0), v3 +// CHECK-ENCODING: [0x27,0x02,0x35,0x0e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 27 02 35 0e + +vsxh.v v4, (a0), v3, v0.t +// CHECK-INST: vsxh.v v4, (a0), v3, v0.t +// CHECK-ENCODING: [0x27,0x52,0x35,0x0c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 27 52 35 0c + +vsxh.v v4, (a0), v3 +// CHECK-INST: vsxh.v v4, (a0), v3 +// CHECK-ENCODING: [0x27,0x52,0x35,0x0e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 27 52 35 0e + +vsxw.v v4, (a0), v3, v0.t +// CHECK-INST: vsxw.v v4, (a0), v3, v0.t +// CHECK-ENCODING: [0x27,0x62,0x35,0x0c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 27 62 35 0c + +vsxw.v v4, (a0), v3 +// CHECK-INST: vsxw.v v4, (a0), v3 +// CHECK-ENCODING: [0x27,0x62,0x35,0x0e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 27 62 35 0e + +vsxe.v v4, (a0), v3, v0.t +// CHECK-INST: vsxe.v v4, (a0), v3, v0.t +// CHECK-ENCODING: [0x27,0x72,0x35,0x0c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 27 72 35 0c + +vsxe.v v4, (a0), v3 +// CHECK-INST: vsxe.v v4, (a0), v3 +// CHECK-ENCODING: [0x27,0x72,0x35,0x0e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 27 72 35 0e + +vsuxb.v v4, (a0), v3, v0.t +// CHECK-INST: vsuxb.v v4, (a0), v3, v0.t +// CHECK-ENCODING: [0x27,0x02,0x35,0x1c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 27 02 35 1c + +vsuxb.v v4, (a0), v3 +// CHECK-INST: vsuxb.v v4, (a0), v3 +// CHECK-ENCODING: [0x27,0x02,0x35,0x1e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 27 02 35 1e + +vsuxh.v v4, (a0), v3, v0.t +// CHECK-INST: vsuxh.v v4, (a0), v3, v0.t +// CHECK-ENCODING: [0x27,0x52,0x35,0x1c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 27 52 35 1c + +vsuxh.v v4, (a0), v3 +// CHECK-INST: vsuxh.v v4, (a0), v3 +// CHECK-ENCODING: [0x27,0x52,0x35,0x1e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 27 52 35 1e + +vsuxw.v v4, (a0), v3, v0.t +// CHECK-INST: vsuxw.v v4, (a0), v3, v0.t +// CHECK-ENCODING: [0x27,0x62,0x35,0x1c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 27 62 35 1c + +vsuxw.v v4, (a0), v3 +// CHECK-INST: vsuxw.v v4, (a0), v3 +// CHECK-ENCODING: [0x27,0x62,0x35,0x1e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 27 62 35 1e + +vsuxe.v v4, (a0), v3, v0.t +// CHECK-INST: vsuxe.v v4, (a0), v3, v0.t +// CHECK-ENCODING: [0x27,0x72,0x35,0x1c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 27 72 35 1c + +vsuxe.v v4, (a0), v3 +// CHECK-INST: vsuxe.v v4, (a0), v3 +// CHECK-ENCODING: [0x27,0x72,0x35,0x1e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 27 72 35 1e Index: llvm/test/MC/RISCV/rvv/sub.s =================================================================== --- /dev/null +++ llvm/test/MC/RISCV/rvv/sub.s @@ -0,0 +1,307 @@ +// RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+v < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=riscv64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \ +// RUN: | llvm-objdump -d -mattr=+v - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +vsub.vv v1, v3, v2, v0.t +// CHECK-INST: vsub.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x00,0x31,0x08] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 08 + +vsub.vv v1, v3, v2 +// CHECK-INST: vsub.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x00,0x31,0x0a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 0a + +vsub.vx v1, v3, a0, v0.t +// CHECK-INST: vsub.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x40,0x35,0x08] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 08 + +vsub.vx v1, v3, a0 +// CHECK-INST: vsub.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x40,0x35,0x0a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 0a + +vrsub.vx v1, v3, a0, v0.t +// CHECK-INST: vrsub.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x40,0x35,0x0c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 0c + +vrsub.vx v1, v3, a0 +// CHECK-INST: vrsub.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x40,0x35,0x0e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 0e + +vrsub.vi v1, v3, 15, v0.t +// CHECK-INST: vrsub.vi v1, v3, 15, v0.t +// CHECK-ENCODING: [0xd7,0xb0,0x37,0x0c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 37 0c + +vrsub.vi v1, v3, 15 +// CHECK-INST: vrsub.vi v1, v3, 15 +// CHECK-ENCODING: [0xd7,0xb0,0x37,0x0e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 37 0e + +vwsubu.vv v1, v3, v2, v0.t +// CHECK-INST: vwsubu.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x20,0x31,0xc8] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 c8 + +vwsubu.vv v1, v3, v2 +// CHECK-INST: vwsubu.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x20,0x31,0xca] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 ca + +vwsubu.vx v1, v3, a0, v0.t +// CHECK-INST: vwsubu.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x60,0x35,0xc8] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 c8 + +vwsubu.vx v1, v3, a0 +// CHECK-INST: vwsubu.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x60,0x35,0xca] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 ca + +vwsub.vv v1, v3, v2, v0.t +// CHECK-INST: vwsub.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x20,0x31,0xcc] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 cc + +vwsub.vv v1, v3, v2 +// CHECK-INST: vwsub.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x20,0x31,0xce] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 ce + +vwsub.vx v1, v3, a0, v0.t +// CHECK-INST: vwsub.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x60,0x35,0xcc] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 cc + +vwsub.vx v1, v3, a0 +// CHECK-INST: vwsub.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x60,0x35,0xce] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 ce + +vwsubu.wv v1, v3, v2, v0.t +// CHECK-INST: vwsubu.wv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x20,0x31,0xd8] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 d8 + +vwsubu.wv v1, v3, v2 +// CHECK-INST: vwsubu.wv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x20,0x31,0xda] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 da + +vwsubu.wx v1, v3, a0, v0.t +// CHECK-INST: vwsubu.wx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x60,0x35,0xd8] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 d8 + +vwsubu.wx v1, v3, a0 +// CHECK-INST: vwsubu.wx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x60,0x35,0xda] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 da + +vwsub.wv v1, v3, v2, v0.t +// CHECK-INST: vwsub.wv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x20,0x31,0xdc] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 dc + +vwsub.wv v1, v3, v2 +// CHECK-INST: vwsub.wv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x20,0x31,0xde] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 20 31 de + +vwsub.wx v1, v3, a0, v0.t +// CHECK-INST: vwsub.wx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x60,0x35,0xdc] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 dc + +vwsub.wx v1, v3, a0 +// CHECK-INST: vwsub.wx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x60,0x35,0xde] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 60 35 de + +vsbc.vvm v1, v3, v2, v0 +// CHECK-INST: vsbc.vvm v1, v3, v2, v0 +// CHECK-ENCODING: [0xd7,0x00,0x31,0x4a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 4a + +vsbc.vxm v1, v3, a0, v0 +// CHECK-INST: vsbc.vxm v1, v3, a0, v0 +// CHECK-ENCODING: [0xd7,0x40,0x35,0x4a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 4a + +vmsbc.vvm v1, v3, v2, v0 +// CHECK-INST: vmsbc.vvm v1, v3, v2, v0 +// CHECK-ENCODING: [0xd7,0x00,0x31,0x4e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 4e + +vmsbc.vxm v1, v3, a0, v0 +// CHECK-INST: vmsbc.vxm v1, v3, a0, v0 +// CHECK-ENCODING: [0xd7,0x40,0x35,0x4e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 4e + +vssubu.vv v1, v3, v2, v0.t +// CHECK-INST: vssubu.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x00,0x31,0x88] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 88 + +vssubu.vv v1, v3, v2 +// CHECK-INST: vssubu.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x00,0x31,0x8a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 8a + +vssubu.vx v1, v3, a0, v0.t +// CHECK-INST: vssubu.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x40,0x35,0x88] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 88 + +vssubu.vx v1, v3, a0 +// CHECK-INST: vssubu.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x40,0x35,0x8a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 8a + +vssub.vv v1, v3, v2, v0.t +// CHECK-INST: vssub.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x00,0x31,0x8c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 8c + +vssub.vv v1, v3, v2 +// CHECK-INST: vssub.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x00,0x31,0x8e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 8e + +vssub.vx v1, v3, a0, v0.t +// CHECK-INST: vssub.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x40,0x35,0x8c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 8c + +vssub.vx v1, v3, a0 +// CHECK-INST: vssub.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x40,0x35,0x8e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 8e + +vasub.vv v1, v3, v2, v0.t +// CHECK-INST: vasub.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x00,0x31,0x98] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 98 + +vasub.vv v1, v3, v2 +// CHECK-INST: vasub.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x00,0x31,0x9a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 9a + +vasub.vx v1, v3, a0, v0.t +// CHECK-INST: vasub.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x40,0x35,0x98] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 98 + +vasub.vx v1, v3, a0 +// CHECK-INST: vasub.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x40,0x35,0x9a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 9a + +vfsub.vv v1, v3, v2, v0.t +// CHECK-INST: vfsub.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x10,0x31,0x08] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 08 + +vfsub.vv v1, v3, v2 +// CHECK-INST: vfsub.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x10,0x31,0x0a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 0a + +vfsub.vf v1, v3, fa0, v0.t +// CHECK-INST: vfsub.vf v1, v3, fa0, v0.t +// CHECK-ENCODING: [0xd7,0x50,0x35,0x08] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 08 + +vfsub.vf v1, v3, fa0 +// CHECK-INST: vfsub.vf v1, v3, fa0 +// CHECK-ENCODING: [0xd7,0x50,0x35,0x0a] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 0a + +vfrsub.vf v1, v3, fa0, v0.t +// CHECK-INST: vfrsub.vf v1, v3, fa0, v0.t +// CHECK-ENCODING: [0xd7,0x50,0x35,0x9c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 9c + +vfrsub.vf v1, v3, fa0 +// CHECK-INST: vfrsub.vf v1, v3, fa0 +// CHECK-ENCODING: [0xd7,0x50,0x35,0x9e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 9e + +vfwsub.vv v1, v3, v2, v0.t +// CHECK-INST: vfwsub.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x10,0x31,0xc8] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 c8 + +vfwsub.vv v1, v3, v2 +// CHECK-INST: vfwsub.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x10,0x31,0xca] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 10 31 ca + +vfwsub.vf v1, v3, fa0, v0.t +// CHECK-INST: vfwsub.vf v1, v3, fa0, v0.t +// CHECK-ENCODING: [0xd7,0x50,0x35,0xc8] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 c8 + +vfwsub.vf v1, v3, fa0 +// CHECK-INST: vfwsub.vf v1, v3, fa0 +// CHECK-ENCODING: [0xd7,0x50,0x35,0xca] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 50 35 ca Index: llvm/test/MC/RISCV/rvv/vsetvl.s =================================================================== --- /dev/null +++ llvm/test/MC/RISCV/rvv/vsetvl.s @@ -0,0 +1,19 @@ +// RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+v < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=riscv64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \ +// RUN: | llvm-objdump -d -mattr=+v - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +vsetvli a2, a0, e32,m4 +// CHECK-INST: vsetvli a2, a0, e32,m4 +// CHECK-ENCODING: [0x57,0x76,0xa5,0x00] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 57 76 a5 00 + +vsetvl a2, a0, a1 +// CHECK-INST: vsetvl a2, a0, a1 +// CHECK-ENCODING: [0x57,0x76,0xb5,0x80] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: 57 76 b5 80 Index: llvm/test/MC/RISCV/rvv/xor.s =================================================================== --- /dev/null +++ llvm/test/MC/RISCV/rvv/xor.s @@ -0,0 +1,43 @@ +// RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+v < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=riscv64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \ +// RUN: | llvm-objdump -d -mattr=+v - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+v < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +vxor.vv v1, v3, v2, v0.t +// CHECK-INST: vxor.vv v1, v3, v2, v0.t +// CHECK-ENCODING: [0xd7,0x00,0x31,0x2c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 2c + +vxor.vv v1, v3, v2 +// CHECK-INST: vxor.vv v1, v3, v2 +// CHECK-ENCODING: [0xd7,0x00,0x31,0x2e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 00 31 2e + +vxor.vx v1, v3, a0, v0.t +// CHECK-INST: vxor.vx v1, v3, a0, v0.t +// CHECK-ENCODING: [0xd7,0x40,0x35,0x2c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 2c + +vxor.vx v1, v3, a0 +// CHECK-INST: vxor.vx v1, v3, a0 +// CHECK-ENCODING: [0xd7,0x40,0x35,0x2e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 40 35 2e + +vxor.vi v1, v3, 15, v0.t +// CHECK-INST: vxor.vi v1, v3, 15, v0.t +// CHECK-ENCODING: [0xd7,0xb0,0x37,0x2c] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 37 2c + +vxor.vi v1, v3, 15 +// CHECK-INST: vxor.vi v1, v3, 15 +// CHECK-ENCODING: [0xd7,0xb0,0x37,0x2e] +// CHECK-ERROR: instruction use requires an option to be enabled +// CHECK-UNKNOWN: d7 b0 37 2e