[PowerPC]: Fix predicate handling with SPE

[jhibbits]

Summary

SPE floating-point compare instructions only update the GT bit in the CR
field. All predicates must therefore be reduced to GT/LE.

[kthomsen]

Justin,
last week, I found out, that there is a second place for this GT/LE modification needed. Therefore I moved the switch/case into a separate function.

diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 2cb0387..b678656
--- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -3860,6 +3878,36 @@ static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) {
   }
 }
 
+// For SPE operations, the Result is stored in GT
+// Return the corresponding GT or LE code for this
+// Prior to this, the Compare must have been modified to EF?CMP?? in SelectCC
+static PPC::Predicate getPredicateForSetCCForSPE(ISD::CondCode CC) {
+  PPC::Predicate Opc = PPC::PRED_SPE;
+  switch(CC) {
+    case ISD::SETOEQ:
+    case ISD::SETEQ:
+    case ISD::SETOLT:
+    case ISD::SETLT:
+    case ISD::SETOGT:
+    case ISD::SETGT:
+      Opc = PPC::PRED_GT;
+      break;
+    case ISD::SETUNE:
+    case ISD::SETNE:
+    case ISD::SETULE:
+    case ISD::SETLE:
+    case ISD::SETUGE:
+    case ISD::SETGE:
+     Opc = PPC::PRED_LE;
+      break;
+    default:
+      printf("Undefined SPE Predicate for CC %u\n",CC);
+      break;
+  }
+  return Opc;
+}
+
+
 /// getCRIdxForSetCC - Return the index of the condition register field
 /// associated with the SetCC condition, and whether or not the field is
 /// treated as inverted.  That is, lt = 0; ge = 0 inverted.
@@ -4890,6 +4937,13 @@ void PPCDAGToDAGISel::Select(SDNode *N) {
     }
 
     unsigned BROpc = getPredicateForSetCC(CC);
+    // Override BROpc if SPE with f64/f32 operation
+    // Watch out: N->getOperand(0).getValueType is not the same as N->getValueType(0)
+    if (PPCSubTarget->hasSPE()
+        && ( N->getOperand(0).getValueType() == MVT::f64
+            || N->getOperand(0).getValueType() == MVT::f32) ) {
+      BROpc = getPredicateForSetCCForSPE(CC);
+    }
 
     unsigned SelectCCOp;
     if (N->getValueType(0) == MVT::i32)
@@ -5048,6 +5102,12 @@ void PPCDAGToDAGISel::Select(SDNode *N) {
       PCC |= getBranchHint(PCC, FuncInfo, N->getOperand(4));
 
     SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl);
+
+    if (PPCSubTarget->hasSPE() && N->getOperand(2).getValueType().isFloatingPoint()) {
+      // For SPE instructions, the result is in GT bit of the CR
+      PCC = getPredicateForSetCCForSPE(CC);
+    }            
+
     SDValue Ops[] = { getI32Imm(PCC, dl), CondCode,
                         N->getOperand(4), N->getOperand(0) };
     CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops);

Not sure, if the naming of the function getPredicateForSetCCForSPE() is good. Maybe we need to rename this.
Best regards,
Kei

[jhibbits]

Thanks, @kthomsen. Can you provide a LLVM IR test case for this? And test cases for the other two reviews I added you on, since you wrote the patches initially?

[kthomsen]

I don't have build test cases for the patches. For the next 4 weeks, I will be on vacation and at two conferences.
My (local) tests are done by creating a C file with some specific code to test the patch and have a look into the generated assembler file and the results by running the binary on a target machine.
Looks like, that I need to find someone, who can show/guide/help me how to write and run a test cases.

[jhibbits]

@kthomsen you can use 'clang -emit-llvm' to emit LLVM IR from your C test cases. There are reducer passes that you can run on that as well, to reduce the test case to the smallest needed, but I can't recall what they are.

[jhibbits]

Update diff with @kthomsen's comment. With this, and D69484, D69486, and
D70570, clang can now build a fully working powerpcspe FreeBSD world.

[jhibbits]

Add tests, taken from the C test in comments in D54583.

[Jim]

A few nits.
You can use git-clang-format to format your patch for following llvm coding style.

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

3874

It doesn't need indentation for case.
It should look like:

switch (CC) {
case ISD::SETOEQ:
...

4930

It looks weird. Does it use tab as indentation?

[jhibbits]

Apply style fixes.

[jhibbits]

Thanks @Jim, yes the code was copied from a comment in another review and I didn't run clang-format on it. Thanks for pointing out 'git-clang-format', I didn't know about that before.

[jhibbits]

Ping on this? I've been using this patch for quite some time now, and really want to get it in before 10.

[jsji]

Looks like to me that Vector Compare in SPE also has different CR bit semantics .
So this patch will only handle floating point part for SPE? If so, maybe we should make it explicit in title.

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

3871

Can we merge this into getPredicateForSetCC? So that we don't need to add code in every callsite of getPredicateForSetCC?

3891

If we don't merge this into getPredicateForSetCC, maybe it would be better to list those should have been legalized ones like getPredicateForSetCC.

5088

Why we are using isFloatingPoint() here, while checking MVT::f32/MVT::f64 above?

llvm/test/CodeGen/PowerPC/spe.ll

2

Maybe we should include one RUN line for -O0 to test FastIsel as well?

2

Why not generate the checks using script?

149–150

Why don't we check bits with ugt?

[jhibbits]

In D69483#1799302, @jsji wrote:

Looks like to me that Vector Compare in SPE also has different CR bit semantics .
So this patch will only handle floating point part for SPE? If so, maybe we should make it explicit in title.

Correct. We currently only do codegen for SPE floating point, not for vector. I currently have no plans to implement vector support any time soon, if ever.

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

3891

Since this is called in more places than getPredicateForSetCC, this comment makes more sense to implement.

5088

No real reason why. I don't see any difference between them in this use case, but I can unify the conditions.

llvm/test/CodeGen/PowerPC/spe.ll

2

Is there an example of generating checks via a script? These checks were generated from a C file provided by @kthomsen a while back, with -emit-llvm, and pared down to the smallest working set I could.

149–150

The asm generated with ugt is much larger, including extra efscmpeq checks as well, so I chose not to include that.

[jsji]

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

3891

? Why more places than getPredicateForSetCC? I think we call it after each getPredicateForSetCC

5088

Yes, please.

llvm/test/CodeGen/PowerPC/spe.ll

2

Just run llvm/utils/update_llc_test_checks.py --llc-binary ../build/bin/llc llvm/test/CodeGen/PowerPC/spe.ll .
The script should generate CHECKs automatically.
We can then examine each of them to see whether they are desired.

149–150

But then we lose the test point here?
If we can use llvm/utils/update_llc_test_checks.py to generate the test, then it should be easier to keep them.

[jhibbits]

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

3891

You're right. I didn't check the full path below before the getPredicateForSetCCForSPE(). However, getPredicateForSetCCForSPE() is *only* to be used for floating point checks. getPredicateForSetCC() doesn't take a type. I guess I could add a type argument for getPredicateForCC().

llvm/test/CodeGen/PowerPC/spe.ll

2

Thanks. I was unaware of that script, and should probably poke around more to see what else is there that I can make use of in the future.

149–150

Good point. Originally, this test was just to make sure the instruction itself was generated. The other tests I adapted because they were easy to add in the correctness of the condition check.

[jsji]

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

3891

Yes, we need to add arguments for getPredicateForCC in order to consider SPE.

llvm/test/CodeGen/PowerPC/spe.ll

2

Great! Let me know if you meet problems in the script, we should fix it if there is bug.

[jhibbits]

Address comments. As part of this I ran 'update_llc_test_checks.py' on the
whole spe.ll file. I'm not sure if that's necessary for this, but I included
the output anyway. If it's better as a separate change I can do that.

[jsji]

LGTM.
Yes, it would be better if you can run update_llc_test_checks.py without this patch first, commit it, rebase, then run update_llc_test_checks.py with this patch again.

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

5086

Unnecessary new line?

[jhibbits]

Committed as 2c4620ad57b

[Jim]

You can refer https://llvm.org/docs/Phabricator.html#committing-a-change to commit a change.
If your commit message has Differential Revision: <URL>, the differential will close automatically.
arc patch D<Revision> is used to fetch a differential from Phabricator.
https://llvm.org/docs/Phabricator.html#committing-someone-s-change-from-phabricator

[jhibbits]

@Jim Yeah, I know. I normally do fix the commit message, but forgot before pushing this one. I'll have to check, but I thought arc had a way to update the commit message when generating the review.

[MaskRay]

In D69483#1802367, @jhibbits wrote:

@Jim Yeah, I know. I normally do fix the commit message, but forgot before pushing this one. I'll have to check, but I thought arc had a way to update the commit message when generating the review.

arc amend copies Phabricator summary to the git commit message. It also rewrites metadata tags such as Reviewed By:. I use a script to strip unneeded metadata tags before committing: https://lists.llvm.org/pipermail/llvm-dev/2020-January/137895.html

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC,
   } else {
     assert(LHS.getValueType() == MVT::f128 && "Unknown vt!");
     assert(PPCSubTarget->hasVSX() && "__float128 requires VSX");
     Opc = PPC::XSCMPUQP;
   }
   return SDValue(CurDAG->getMachineNode(Opc, dl, MVT::i32, LHS, RHS), 0);
 }
 
-static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) {
+static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC, const EVT &VT,
+    const PPCSubtarget *Subtarget) {
+  // For SPE instructions, the result is in GT bit of the CR
+  bool UseSPE = Subtarget->hasSPE() && VT.isFloatingPoint();
+
   switch (CC) {
   case ISD::SETUEQ:
   case ISD::SETONE:
   case ISD::SETOLE:
   case ISD::SETOGE:
     llvm_unreachable("Should be lowered by legalize!");
   default: llvm_unreachable("Unknown condition!");
   case ISD::SETOEQ:
-  case ISD::SETEQ:  return PPC::PRED_EQ;
+  case ISD::SETEQ:  return UseSPE ? PPC::PRED_GT : PPC::PRED_EQ;
   case ISD::SETUNE:
-  case ISD::SETNE:  return PPC::PRED_NE;
+  case ISD::SETNE:  return UseSPE ? PPC::PRED_LE : PPC::PRED_NE;
   case ISD::SETOLT:
-  case ISD::SETLT:  return PPC::PRED_LT;
+  case ISD::SETLT:  return UseSPE ? PPC::PRED_GT : PPC::PRED_LT;
   case ISD::SETULE:
-  case ISD::SETLE:  return PPC::PRED_LE;
+  case ISD::SETLE:  return UseSPE ? PPC::PRED_LE : PPC::PRED_LE;
   case ISD::SETOGT:
-  case ISD::SETGT:  return PPC::PRED_GT;
+  case ISD::SETGT:  return UseSPE ? PPC::PRED_GT : PPC::PRED_GT;
   case ISD::SETUGE:
-  case ISD::SETGE:  return PPC::PRED_GE;
+  case ISD::SETGE:  return UseSPE ? PPC::PRED_LE : PPC::PRED_GE;
   case ISD::SETO:   return PPC::PRED_NU;
   case ISD::SETUO:  return PPC::PRED_UN;
     // These two are invalid for floating point.  Assume we have int.
   case ISD::SETULT: return PPC::PRED_LT;
   case ISD::SETUGT: return PPC::PRED_GT;
   }
 }
 
 /// getCRIdxForSetCC - Return the index of the condition register field
 /// associated with the SetCC condition, and whether or not the field is
 /// treated as inverted.  That is, lt = 0; ge = 0 inverted.
 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert) {
   Invert = false;
   switch (CC) {
   default: llvm_unreachable("Unknown condition!");
   case ISD::SETOLT:
   case ISD::SETLT:  return 0;                  // Bit #0 = SETOLT
   case ISD::SETOGT:
   case ISD::SETGT:  return 1;                  // Bit #1 = SETOGT
   case ISD::SETOEQ:
   case ISD::SETEQ:  return 2;                  // Bit #2 = SETOEQ
   case ISD::SETUO:  return 3;                  // Bit #3 = SETUO
   case ISD::SETUGE:
   case ISD::SETGE:  Invert = true; return 0;   // !Bit #0 = SETUGE
   case ISD::SETULE:
   case ISD::SETLE:  Invert = true; return 1;   // !Bit #1 = SETULE
   case ISD::SETUNE:
   case ISD::SETNE:  Invert = true; return 2;   // !Bit #2 = SETUNE
   case ISD::SETO:   Invert = true; return 3;   // !Bit #3 = SETO
   case ISD::SETUEQ:
   case ISD::SETOGE:
   case ISD::SETOLE:
   case ISD::SETONE:
     llvm_unreachable("Invalid branch code: should be expanded by legalize");
   // These are invalid for floating point.  Assume integer.
   case ISD::SETULT: return 0;
   case ISD::SETUGT: return 1;
   }
 }
 
if (N->getValueType(0) == MVT::i1) {
                                            C, N->getOperand(2)), 0);
       SDValue NotCAndF(CurDAG->getMachineNode(PPC::CRAND, dl, MVT::i1,
                                               NotC, N->getOperand(3)), 0);
 
       CurDAG->SelectNodeTo(N, PPC::CROR, MVT::i1, CAndT, NotCAndF);
       return;
     }
 
-    unsigned BROpc = getPredicateForSetCC(CC);
+    unsigned BROpc = getPredicateForSetCC(CC, N->getOperand(0).getValueType(),
+        PPCSubTarget);
 
     unsigned SelectCCOp;
     if (N->getValueType(0) == MVT::i32)
       SelectCCOp = PPC::SELECT_CC_I4;
     else if (N->getValueType(0) == MVT::i64)
       SelectCCOp = PPC::SELECT_CC_I8;
     else if (N->getValueType(0) == MVT::f32) {
       if (PPCSubTarget->hasP8Vector())
         SelectCCOp = PPC::SELECT_CC_VSSRC;
       else if (PPCSubTarget->hasSPE())
         SelectCCOp = PPC::SELECT_CC_SPE4;
       else
case PPCISD::COND_BRANCH: {
     SDValue Pred = getI32Imm(PCC, dl);
     SDValue Ops[] = { Pred, N->getOperand(2), N->getOperand(3),
       N->getOperand(0), N->getOperand(4) };
     CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops);
     return;
   }
   case ISD::BR_CC: {
     ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
-    unsigned PCC = getPredicateForSetCC(CC);
+    unsigned PCC = getPredicateForSetCC(CC, N->getOperand(2).getValueType(),
+        PPCSubTarget);
 
     if (N->getOperand(2).getValueType() == MVT::i1) {
       unsigned Opc;
       bool Swap;
       switch (PCC) {
       default: llvm_unreachable("Unexpected Boolean-operand predicate");
       case PPC::PRED_LT: Opc = PPC::CRANDC; Swap = true;  break;
       case PPC::PRED_LE: Opc = PPC::CRORC;  Swap = true;  break;
if (N->getOperand(2).getValueType() == MVT::i1) {
                            N->getOperand(0));
       return;
     }
 
     if (EnableBranchHint)
       PCC |= getBranchHint(PCC, *FuncInfo, N->getOperand(4));
 
     SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl);
+
     SDValue Ops[] = { getI32Imm(PCC, dl), CondCode,
                         N->getOperand(4), N->getOperand(0) };
     CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops);
     return;
   }
   case ISD::BRIND: {
     // FIXME: Should custom lower this.
     SDValue Chain = N->getOperand(0);
     SDValue Target = N->getOperand(1);
     unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8;

llvm/test/CodeGen/PowerPC/spe.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu \
 ; RUN:          -mattr=+spe |  FileCheck %s
 
 declare float @llvm.fabs.float(float)
 define float @test_float_abs(float %a) #0 {
+; CHECK-LABEL: test_float_abs:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    efsabs 3, 3
+; CHECK-NEXT:    blr
   entry:
     %0 = tail call float @llvm.fabs.float(float %a)
     ret float %0
-; CHECK-LABEL: test_float_abs
-; CHECK: efsabs 3, 3
-; CHECK: blr
 }
 
 define float @test_fnabs(float %a) #0 {
+; CHECK-LABEL: test_fnabs:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    efsnabs 3, 3
+; CHECK-NEXT:    blr
   entry:
     %0 = tail call float @llvm.fabs.float(float %a)
     %sub = fsub float -0.000000e+00, %0
     ret float %sub
-; CHECK-LABEL: @test_fnabs
-; CHECK: efsnabs
-; CHECK: blr
 }
 
 define float @test_fdiv(float %a, float %b) {
+; CHECK-LABEL: test_fdiv:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    efsdiv 3, 3, 4
+; CHECK-NEXT:    blr
 entry:
   %v = fdiv float %a, %b
   ret float %v
 
-; CHECK-LABEL: test_fdiv
-; CHECK: efsdiv
-; CHECK: blr
 }
 
 define float @test_fmul(float %a, float %b) {
+; CHECK-LABEL: test_fmul:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    efsmul 3, 3, 4
+; CHECK-NEXT:    blr
   entry:
   %v = fmul float %a, %b
   ret float %v
 ; CHECK-LABEL @test_fmul
-; CHECK: efsmul
-; CHECK: blr
 }
 
 define float @test_fadd(float %a, float %b) {
+; CHECK-LABEL: test_fadd:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    efsadd 3, 3, 4
+; CHECK-NEXT:    blr
   entry:
   %v = fadd float %a, %b
   ret float %v
 ; CHECK-LABEL @test_fadd
-; CHECK: efsadd
-; CHECK: blr
 }
 
 define float @test_fsub(float %a, float %b) {
+; CHECK-LABEL: test_fsub:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    efssub 3, 3, 4
+; CHECK-NEXT:    blr
   entry:
   %v = fsub float %a, %b
   ret float %v
 ; CHECK-LABEL @test_fsub
-; CHECK: efssub
-; CHECK: blr
 }
 
 define float @test_fneg(float %a) {
+; CHECK-LABEL: test_fneg:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    efsneg 3, 3
+; CHECK-NEXT:    blr
   entry:
   %v = fsub float -0.0, %a
   ret float %v
 
 ; CHECK-LABEL @test_fneg
-; CHECK: efsneg
-; CHECK: blr
 }
 
 define float @test_dtos(double %a) {
+; CHECK-LABEL: test_dtos:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    evmergelo 3, 3, 4
+; CHECK-NEXT:    efscfd 3, 3
+; CHECK-NEXT:    blr
   entry:
   %v = fptrunc double %a to float
   ret float %v
-; CHECK-LABEL: test_dtos
-; CHECK: efscfd
-; CHECK: blr
-}
-
-define i1 @test_fcmpgt(float %a, float %b) {
-  entry:
-  %r = fcmp ogt float %a, %b
-  ret i1 %r
-; CHECK-LABEL: test_fcmpgt
-; CHECK: efscmpgt
-; CHECK: blr
-}
-
-define i1 @test_fcmpugt(float %a, float %b) {
-  entry:
-  %r = fcmp ugt float %a, %b
-  ret i1 %r
-; CHECK-LABEL: test_fcmpugt
-; CHECK: efscmpgt
-; CHECK: blr
-}
-
-define i1 @test_fcmple(float %a, float %b) {
-  entry:
-  %r = fcmp ole float %a, %b
-  ret i1 %r
-; CHECK-LABEL: test_fcmple
-; CHECK: efscmpgt
-; CHECK: blr
-}
-
-define i1 @test_fcmpule(float %a, float %b) {
-  entry:
-  %r = fcmp ule float %a, %b
-  ret i1 %r
-; CHECK-LABEL: test_fcmpule
-; CHECK: efscmpgt
-; CHECK: blr
 }
 
-define i1 @test_fcmpeq(float %a, float %b) {
-  entry:
-  %r = fcmp oeq float %a, %b
-  ret i1 %r
-; CHECK-LABEL: test_fcmpeq
-; CHECK: efscmpeq
-; CHECK: blr
+define i32 @test_fcmpgt(float %a, float %b) {
+; CHECK-LABEL: test_fcmpgt:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    stwu 1, -16(1)
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    efscmpgt 0, 3, 4
+; CHECK-NEXT:    ble 0, .LBB8_2
+; CHECK-NEXT:  # %bb.1: # %tr
+; CHECK-NEXT:    li 3, 1
+; CHECK-NEXT:    b .LBB8_3
+; CHECK-NEXT:  .LBB8_2: # %fa
+; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:  .LBB8_3: # %ret
+; CHECK-NEXT:    stw 3, 12(1)
+; CHECK-NEXT:    lwz 3, 12(1)
+; CHECK-NEXT:    addi 1, 1, 16
+; CHECK-NEXT:    blr
+  entry:
+  %r = alloca i32, align 4
+  %c = fcmp ogt float %a, %b
+  br i1 %c, label %tr, label %fa
+tr:
+  store i32 1, i32* %r, align 4
+  br label %ret
+fa:
+  store i32 0, i32* %r, align 4
+  br label %ret
+ret:
+  %0 = load i32, i32* %r, align 4
+  ret i32 %0
+}
+
+define i32 @test_fcmpugt(float %a, float %b) {
+; CHECK-LABEL: test_fcmpugt:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    stwu 1, -16(1)
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    efscmpeq 0, 4, 4
+; CHECK-NEXT:    bc 4, 1, .LBB9_4
+; CHECK-NEXT:  # %bb.1: # %entry
+; CHECK-NEXT:    efscmpeq 0, 3, 3
+; CHECK-NEXT:    bc 4, 1, .LBB9_4
+; CHECK-NEXT:  # %bb.2: # %entry
+; CHECK-NEXT:    efscmpgt 0, 3, 4
+; CHECK-NEXT:    bc 12, 1, .LBB9_4
+; CHECK-NEXT:  # %bb.3: # %fa
+; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:    b .LBB9_5
+; CHECK-NEXT:  .LBB9_4: # %tr
+; CHECK-NEXT:    li 3, 1
+; CHECK-NEXT:  .LBB9_5: # %ret
+; CHECK-NEXT:    stw 3, 12(1)
+; CHECK-NEXT:    lwz 3, 12(1)
+; CHECK-NEXT:    addi 1, 1, 16
+; CHECK-NEXT:    blr
+  entry:
+  %r = alloca i32, align 4
+  %c = fcmp ugt float %a, %b
+  br i1 %c, label %tr, label %fa
+tr:
+  store i32 1, i32* %r, align 4
+  br label %ret
+fa:
+  store i32 0, i32* %r, align 4
+  br label %ret
+ret:
+  %0 = load i32, i32* %r, align 4
+  ret i32 %0
+}
+
+define i32 @test_fcmple(float %a, float %b) {
+; CHECK-LABEL: test_fcmple:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    stwu 1, -16(1)
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    efscmpeq 0, 3, 3
+; CHECK-NEXT:    bc 4, 1, .LBB10_4
+; CHECK-NEXT:  # %bb.1: # %entry
+; CHECK-NEXT:    efscmpeq 0, 4, 4
+; CHECK-NEXT:    bc 4, 1, .LBB10_4
+; CHECK-NEXT:  # %bb.2: # %entry
+; CHECK-NEXT:    efscmpgt 0, 3, 4
+; CHECK-NEXT:    bc 12, 1, .LBB10_4
+; CHECK-NEXT:  # %bb.3: # %tr
+; CHECK-NEXT:    li 3, 1
+; CHECK-NEXT:    b .LBB10_5
+; CHECK-NEXT:  .LBB10_4: # %fa
+; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:  .LBB10_5: # %ret
+; CHECK-NEXT:    stw 3, 12(1)
+; CHECK-NEXT:    lwz 3, 12(1)
+; CHECK-NEXT:    addi 1, 1, 16
+; CHECK-NEXT:    blr
+  entry:
+  %r = alloca i32, align 4
+  %c = fcmp ole float %a, %b
+  br i1 %c, label %tr, label %fa
+tr:
+  store i32 1, i32* %r, align 4
+  br label %ret
+fa:
+  store i32 0, i32* %r, align 4
+  br label %ret
+ret:
+  %0 = load i32, i32* %r, align 4
+  ret i32 %0
+}
+
+define i32 @test_fcmpule(float %a, float %b) {
+; CHECK-LABEL: test_fcmpule:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    stwu 1, -16(1)
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    efscmpgt 0, 3, 4
+; CHECK-NEXT:    bgt 0, .LBB11_2
+; CHECK-NEXT:  # %bb.1: # %tr
+; CHECK-NEXT:    li 3, 1
+; CHECK-NEXT:    b .LBB11_3
+; CHECK-NEXT:  .LBB11_2: # %fa
+; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:  .LBB11_3: # %ret
+; CHECK-NEXT:    stw 3, 12(1)
+; CHECK-NEXT:    lwz 3, 12(1)
+; CHECK-NEXT:    addi 1, 1, 16
+; CHECK-NEXT:    blr
+  entry:
+  %r = alloca i32, align 4
+  %c = fcmp ule float %a, %b
+  br i1 %c, label %tr, label %fa
+tr:
+  store i32 1, i32* %r, align 4
+  br label %ret
+fa:
+  store i32 0, i32* %r, align 4
+  br label %ret
+ret:
+  %0 = load i32, i32* %r, align 4
+  ret i32 %0
+}
+
+; The type of comparison found in C's if (x == y)
+define i32 @test_fcmpeq(float %a, float %b) {
+; CHECK-LABEL: test_fcmpeq:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    stwu 1, -16(1)
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    efscmpeq 0, 3, 4
+; CHECK-NEXT:    ble 0, .LBB12_2
+; CHECK-NEXT:  # %bb.1: # %tr
+; CHECK-NEXT:    li 3, 1
+; CHECK-NEXT:    b .LBB12_3
+; CHECK-NEXT:  .LBB12_2: # %fa
+; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:  .LBB12_3: # %ret
+; CHECK-NEXT:    stw 3, 12(1)
+; CHECK-NEXT:    lwz 3, 12(1)
+; CHECK-NEXT:    addi 1, 1, 16
+; CHECK-NEXT:    blr
+  entry:
+  %r = alloca i32, align 4
+  %c = fcmp oeq float %a, %b
+  br i1 %c, label %tr, label %fa
+tr:
+  store i32 1, i32* %r, align 4
+  br label %ret
+fa:
+  store i32 0, i32* %r, align 4
+  br label %ret
+ret:
+  %0 = load i32, i32* %r, align 4
+  ret i32 %0
 }
 
 ; (un)ordered tests are expanded to une and oeq so verify
 define i1 @test_fcmpuno(float %a, float %b) {
+; CHECK-LABEL: test_fcmpuno:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    efscmpeq 0, 3, 3
+; CHECK-NEXT:    efscmpeq 1, 4, 4
+; CHECK-NEXT:    li 5, 1
+; CHECK-NEXT:    crand 20, 5, 1
+; CHECK-NEXT:    bc 12, 20, .LBB13_2
+; CHECK-NEXT:  # %bb.1: # %entry
+; CHECK-NEXT:    ori 3, 5, 0
+; CHECK-NEXT:    blr
+; CHECK-NEXT:  .LBB13_2: # %entry
+; CHECK-NEXT:    addi 3, 0, 0
+; CHECK-NEXT:    blr
   entry:
   %r = fcmp uno float %a, %b
   ret i1 %r
-; CHECK-LABEL: test_fcmpuno
-; CHECK: efscmpeq
-; CHECK: efscmpeq
-; CHECK: crand
-; CHECK: blr
 }
 
 define i1 @test_fcmpord(float %a, float %b) {
+; CHECK-LABEL: test_fcmpord:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    efscmpeq 0, 4, 4
+; CHECK-NEXT:    efscmpeq 1, 3, 3
+; CHECK-NEXT:    li 5, 1
+; CHECK-NEXT:    crnand 20, 5, 1
+; CHECK-NEXT:    bc 12, 20, .LBB14_2
+; CHECK-NEXT:  # %bb.1: # %entry
+; CHECK-NEXT:    ori 3, 5, 0
+; CHECK-NEXT:    blr
+; CHECK-NEXT:  .LBB14_2: # %entry
+; CHECK-NEXT:    addi 3, 0, 0
+; CHECK-NEXT:    blr
   entry:
   %r = fcmp ord float %a, %b
   ret i1 %r
-; CHECK-LABEL: test_fcmpord
-; CHECK: efscmpeq
-; CHECK: efscmpeq
-; CHECK: crnand
-; CHECK: blr
 }
 
 define i1 @test_fcmpueq(float %a, float %b) {
+; CHECK-LABEL: test_fcmpueq:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    efscmpeq 0, 3, 3
+; CHECK-NEXT:    efscmpeq 1, 4, 4
+; CHECK-NEXT:    crnand 20, 5, 1
+; CHECK-NEXT:    efscmpeq 0, 3, 4
+; CHECK-NEXT:    li 5, 1
+; CHECK-NEXT:    crnor 20, 1, 20
+; CHECK-NEXT:    bc 12, 20, .LBB15_2
+; CHECK-NEXT:  # %bb.1: # %entry
+; CHECK-NEXT:    ori 3, 5, 0
+; CHECK-NEXT:    blr
+; CHECK-NEXT:  .LBB15_2: # %entry
+; CHECK-NEXT:    addi 3, 0, 0
+; CHECK-NEXT:    blr
   entry:
   %r = fcmp ueq float %a, %b
   ret i1 %r
-; CHECK-LABEL: test_fcmpueq
-; CHECK: efscmpeq
-; CHECK: blr
 }
 
 define i1 @test_fcmpne(float %a, float %b) {
+; CHECK-LABEL: test_fcmpne:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    efscmpeq 0, 4, 4
+; CHECK-NEXT:    efscmpeq 1, 3, 3
+; CHECK-NEXT:    crand 20, 5, 1
+; CHECK-NEXT:    efscmpeq 0, 3, 4
+; CHECK-NEXT:    li 5, 1
+; CHECK-NEXT:    crorc 20, 1, 20
+; CHECK-NEXT:    bc 12, 20, .LBB16_2
+; CHECK-NEXT:  # %bb.1: # %entry
+; CHECK-NEXT:    ori 3, 5, 0
+; CHECK-NEXT:    blr
+; CHECK-NEXT:  .LBB16_2: # %entry
+; CHECK-NEXT:    addi 3, 0, 0
+; CHECK-NEXT:    blr
   entry:
   %r = fcmp one float %a, %b
   ret i1 %r
-; CHECK-LABEL: test_fcmpne
-; CHECK: efscmpeq
-; CHECK: blr
 }
 
-define i1 @test_fcmpune(float %a, float %b) {
-  entry:
-  %r = fcmp une float %a, %b
-  ret i1 %r
-; CHECK-LABEL: test_fcmpune
-; CHECK: efscmpeq
-; CHECK: blr
-}
-
-define i1 @test_fcmplt(float %a, float %b) {
-  entry:
-  %r = fcmp olt float %a, %b
-  ret i1 %r
-; CHECK-LABEL: test_fcmplt
-; CHECK: efscmplt
-; CHECK: blr
+define i32 @test_fcmpune(float %a, float %b) {
+; CHECK-LABEL: test_fcmpune:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    stwu 1, -16(1)
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    efscmpeq 0, 3, 4
+; CHECK-NEXT:    bgt 0, .LBB17_2
+; CHECK-NEXT:  # %bb.1: # %tr
+; CHECK-NEXT:    li 3, 1
+; CHECK-NEXT:    b .LBB17_3
+; CHECK-NEXT:  .LBB17_2: # %fa
+; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:  .LBB17_3: # %ret
+; CHECK-NEXT:    stw 3, 12(1)
+; CHECK-NEXT:    lwz 3, 12(1)
+; CHECK-NEXT:    addi 1, 1, 16
+; CHECK-NEXT:    blr
+  entry:
+  %r = alloca i32, align 4
+  %c = fcmp une float %a, %b
+  br i1 %c, label %tr, label %fa
+tr:
+  store i32 1, i32* %r, align 4
+  br label %ret
+fa:
+  store i32 0, i32* %r, align 4
+  br label %ret
+ret:
+  %0 = load i32, i32* %r, align 4
+  ret i32 %0
+}
+
+define i32 @test_fcmplt(float %a, float %b) {
+; CHECK-LABEL: test_fcmplt:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    stwu 1, -16(1)
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    efscmplt 0, 3, 4
+; CHECK-NEXT:    ble 0, .LBB18_2
+; CHECK-NEXT:  # %bb.1: # %tr
+; CHECK-NEXT:    li 3, 1
+; CHECK-NEXT:    b .LBB18_3
+; CHECK-NEXT:  .LBB18_2: # %fa
+; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:  .LBB18_3: # %ret
+; CHECK-NEXT:    stw 3, 12(1)
+; CHECK-NEXT:    lwz 3, 12(1)
+; CHECK-NEXT:    addi 1, 1, 16
+; CHECK-NEXT:    blr
+  entry:
+  %r = alloca i32, align 4
+  %c = fcmp olt float %a, %b
+  br i1 %c, label %tr, label %fa
+tr:
+  store i32 1, i32* %r, align 4
+  br label %ret
+fa:
+  store i32 0, i32* %r, align 4
+  br label %ret
+ret:
+  %0 = load i32, i32* %r, align 4
+  ret i32 %0
 }
 
 define i1 @test_fcmpult(float %a, float %b) {
+; CHECK-LABEL: test_fcmpult:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    efscmpeq 0, 3, 3
+; CHECK-NEXT:    efscmpeq 1, 4, 4
+; CHECK-NEXT:    crnand 20, 5, 1
+; CHECK-NEXT:    efscmplt 0, 3, 4
+; CHECK-NEXT:    li 5, 1
+; CHECK-NEXT:    crnor 20, 1, 20
+; CHECK-NEXT:    bc 12, 20, .LBB19_2
+; CHECK-NEXT:  # %bb.1: # %entry
+; CHECK-NEXT:    ori 3, 5, 0
+; CHECK-NEXT:    blr
+; CHECK-NEXT:  .LBB19_2: # %entry
+; CHECK-NEXT:    addi 3, 0, 0
+; CHECK-NEXT:    blr
   entry:
   %r = fcmp ult float %a, %b
   ret i1 %r
-; CHECK-LABEL: test_fcmpult
-; CHECK: efscmplt
-; CHECK: blr
 }
 
-define i1 @test_fcmpge(float %a, float %b) {
-  entry:
-  %r = fcmp oge float %a, %b
-  ret i1 %r
-; CHECK-LABEL: test_fcmpge
-; CHECK: efscmplt
-; CHECK: blr
+define i32 @test_fcmpge(float %a, float %b) {
+; CHECK-LABEL: test_fcmpge:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    stwu 1, -16(1)
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    efscmpeq 0, 3, 3
+; CHECK-NEXT:    bc 4, 1, .LBB20_4
+; CHECK-NEXT:  # %bb.1: # %entry
+; CHECK-NEXT:    efscmpeq 0, 4, 4
+; CHECK-NEXT:    bc 4, 1, .LBB20_4
+; CHECK-NEXT:  # %bb.2: # %entry
+; CHECK-NEXT:    efscmplt 0, 3, 4
+; CHECK-NEXT:    bc 12, 1, .LBB20_4
+; CHECK-NEXT:  # %bb.3: # %tr
+; CHECK-NEXT:    li 3, 1
+; CHECK-NEXT:    b .LBB20_5
+; CHECK-NEXT:  .LBB20_4: # %fa
+; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:  .LBB20_5: # %ret
+; CHECK-NEXT:    stw 3, 12(1)
+; CHECK-NEXT:    lwz 3, 12(1)
+; CHECK-NEXT:    addi 1, 1, 16
+; CHECK-NEXT:    blr
+  entry:
+  %r = alloca i32, align 4
+  %c = fcmp oge float %a, %b
+  br i1 %c, label %tr, label %fa
+tr:
+  store i32 1, i32* %r, align 4
+  br label %ret
+fa:
+  store i32 0, i32* %r, align 4
+  br label %ret
+ret:
+  %0 = load i32, i32* %r, align 4
+  ret i32 %0
+}
+
+define i32 @test_fcmpuge(float %a, float %b) {
+; CHECK-LABEL: test_fcmpuge:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    stwu 1, -16(1)
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    efscmplt 0, 3, 4
+; CHECK-NEXT:    bgt 0, .LBB21_2
+; CHECK-NEXT:  # %bb.1: # %tr
+; CHECK-NEXT:    li 3, 1
+; CHECK-NEXT:    b .LBB21_3
+; CHECK-NEXT:  .LBB21_2: # %fa
+; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:  .LBB21_3: # %ret
+; CHECK-NEXT:    stw 3, 12(1)
+; CHECK-NEXT:    lwz 3, 12(1)
+; CHECK-NEXT:    addi 1, 1, 16
+; CHECK-NEXT:    blr
+  entry:
+  %r = alloca i32, align 4
+  %c = fcmp uge float %a, %b
+  br i1 %c, label %tr, label %fa
+tr:
+  store i32 1, i32* %r, align 4
+  br label %ret
+fa:
+  store i32 0, i32* %r, align 4
+  br label %ret
+ret:
+  %0 = load i32, i32* %r, align 4
+  ret i32 %0
 }
 
-define i1 @test_fcmpuge(float %a, float %b) {
-  entry:
-  %r = fcmp uge float %a, %b
-  ret i1 %r
-; CHECK-LABEL: test_fcmpuge
-; CHECK: efscmplt
-; CHECK: blr
-}
 
 define i32 @test_ftoui(float %a) {
+; CHECK-LABEL: test_ftoui:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    efsctuiz 3, 3
+; CHECK-NEXT:    blr
   %v = fptoui float %a to i32
   ret i32 %v
-; CHECK-LABEL: test_ftoui
-; CHECK: efsctuiz
 }
 
 define i32 @test_ftosi(float %a) {
+; CHECK-LABEL: test_ftosi:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    efsctsiz 3, 3
+; CHECK-NEXT:    blr
   %v = fptosi float %a to i32
   ret i32 %v
-; CHECK-LABEL: test_ftosi
-; CHECK: efsctsiz
 }
 
 define float @test_ffromui(i32 %a) {
+; CHECK-LABEL: test_ffromui:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    efscfui 3, 3
+; CHECK-NEXT:    blr
   %v = uitofp i32 %a to float
   ret float %v
-; CHECK-LABEL: test_ffromui
-; CHECK: efscfui
 }
 
 define float @test_ffromsi(i32 %a) {
+; CHECK-LABEL: test_ffromsi:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    efscfsi 3, 3
+; CHECK-NEXT:    blr
   %v = sitofp i32 %a to float
   ret float %v
-; CHECK-LABEL: test_ffromsi
-; CHECK: efscfsi
 }
 
 define i32 @test_fasmconst(float %x) {
+; CHECK-LABEL: test_fasmconst:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    stwu 1, -32(1)
+; CHECK-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-NEXT:    stw 3, 20(1)
+; CHECK-NEXT:    stw 3, 24(1)
+; CHECK-NEXT:    lwz 3, 20(1)
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    efsctsi 3, 3
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    addi 1, 1, 32
+; CHECK-NEXT:    blr
 entry:
   %x.addr = alloca float, align 8
   store float %x, float* %x.addr, align 8
   %0 = load float, float* %x.addr, align 8
   %1 = call i32 asm sideeffect "efsctsi $0, $1", "=f,f"(float %0)
   ret i32 %1
-; CHECK-LABEL: test_fasmconst
 ; Check that it's not loading a double
-; CHECK-NOT: evldd
-; CHECK: #APP
-; CHECK: efsctsi
-; CHECK: #NO_APP
 }
 
 ; Double tests
 
 define void @test_double_abs(double * %aa) #0 {
+; CHECK-LABEL: test_double_abs:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    evldd 4, 0(3)
+; CHECK-NEXT:    efdabs 4, 4
+; CHECK-NEXT:    evstdd 4, 0(3)
+; CHECK-NEXT:    blr
   entry:
     %0 = load double, double * %aa
     %1 = tail call double @llvm.fabs.f64(double %0) #2
     store double %1, double * %aa
     ret void
-; CHECK-LABEL: test_double_abs
-; CHECK: efdabs
-; CHECK: blr
 }
 
 ; Function Attrs: nounwind readnone
 declare double @llvm.fabs.f64(double) #1
 
 define void @test_dnabs(double * %aa) #0 {
+; CHECK-LABEL: test_dnabs:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    evldd 4, 0(3)
+; CHECK-NEXT:    efdnabs 4, 4
+; CHECK-NEXT:    evstdd 4, 0(3)
+; CHECK-NEXT:    blr
   entry:
     %0 = load double, double * %aa
     %1 = tail call double @llvm.fabs.f64(double %0) #2
     %sub = fsub double -0.000000e+00, %1
     store double %sub, double * %aa
     ret void
 }
 ; CHECK-LABEL: @test_dnabs
 ; CHECK: efdnabs
 ; CHECK: blr
 
 define double @test_ddiv(double %a, double %b) {
+; CHECK-LABEL: test_ddiv:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    evmergelo 5, 5, 6
+; CHECK-NEXT:    evmergelo 3, 3, 4
+; CHECK-NEXT:    efddiv 4, 3, 5
+; CHECK-NEXT:    evmergehi 3, 4, 4
+; CHECK-NEXT:    # kill: def $r4 killed $r4 killed $s4
+; CHECK-NEXT:    # kill: def $r3 killed $r3 killed $s3
+; CHECK-NEXT:    blr
 entry:
   %v = fdiv double %a, %b
   ret double %v
 
-; CHECK-LABEL: test_ddiv
-; CHECK: efddiv
-; CHECK: blr
 }
 
 define double @test_dmul(double %a, double %b) {
+; CHECK-LABEL: test_dmul:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    evmergelo 5, 5, 6
+; CHECK-NEXT:    evmergelo 3, 3, 4
+; CHECK-NEXT:    efdmul 4, 3, 5
+; CHECK-NEXT:    evmergehi 3, 4, 4
+; CHECK-NEXT:    # kill: def $r4 killed $r4 killed $s4
+; CHECK-NEXT:    # kill: def $r3 killed $r3 killed $s3
+; CHECK-NEXT:    blr
   entry:
   %v = fmul double %a, %b
   ret double %v
 ; CHECK-LABEL @test_dmul
-; CHECK: efdmul
-; CHECK: blr
 }
 
 define double @test_dadd(double %a, double %b) {
+; CHECK-LABEL: test_dadd:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    evmergelo 5, 5, 6
+; CHECK-NEXT:    evmergelo 3, 3, 4
+; CHECK-NEXT:    efdadd 4, 3, 5
+; CHECK-NEXT:    evmergehi 3, 4, 4
+; CHECK-NEXT:    # kill: def $r4 killed $r4 killed $s4
+; CHECK-NEXT:    # kill: def $r3 killed $r3 killed $s3
+; CHECK-NEXT:    blr
   entry:
   %v = fadd double %a, %b
   ret double %v
 ; CHECK-LABEL @test_dadd
-; CHECK: efdadd
-; CHECK: blr
 }
 
 define double @test_dsub(double %a, double %b) {
+; CHECK-LABEL: test_dsub:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    evmergelo 5, 5, 6
+; CHECK-NEXT:    evmergelo 3, 3, 4
+; CHECK-NEXT:    efdsub 4, 3, 5
+; CHECK-NEXT:    evmergehi 3, 4, 4
+; CHECK-NEXT:    # kill: def $r4 killed $r4 killed $s4
+; CHECK-NEXT:    # kill: def $r3 killed $r3 killed $s3
+; CHECK-NEXT:    blr
   entry:
   %v = fsub double %a, %b
   ret double %v
 ; CHECK-LABEL @test_dsub
-; CHECK: efdsub
-; CHECK: blr
 }
 
 define double @test_dneg(double %a) {
+; CHECK-LABEL: test_dneg:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    evmergelo 3, 3, 4
+; CHECK-NEXT:    efdneg 4, 3
+; CHECK-NEXT:    evmergehi 3, 4, 4
+; CHECK-NEXT:    # kill: def $r4 killed $r4 killed $s4
+; CHECK-NEXT:    # kill: def $r3 killed $r3 killed $s3
+; CHECK-NEXT:    blr
   entry:
   %v = fsub double -0.0, %a
   ret double %v
 
 ; CHECK-LABEL @test_dneg
-; CHECK: blr
 }
 
 define double @test_stod(float %a) {
+; CHECK-LABEL: test_stod:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    efdcfs 4, 3
+; CHECK-NEXT:    evmergehi 3, 4, 4
+; CHECK-NEXT:    # kill: def $r4 killed $r4 killed $s4
+; CHECK-NEXT:    # kill: def $r3 killed $r3 killed $s3
+; CHECK-NEXT:    blr
   entry:
   %v = fpext float %a to double
   ret double %v
-; CHECK-LABEL: test_stod
-; CHECK: efdcfs
-; CHECK: blr
 }
 
 ; (un)ordered tests are expanded to une and oeq so verify
 define i1 @test_dcmpuno(double %a, double %b) {
+; CHECK-LABEL: test_dcmpuno:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    evmergelo 5, 5, 6
+; CHECK-NEXT:    evmergelo 3, 3, 4
+; CHECK-NEXT:    li 7, 1
+; CHECK-NEXT:    efdcmpeq 0, 3, 3
+; CHECK-NEXT:    efdcmpeq 1, 5, 5
+; CHECK-NEXT:    crand 20, 5, 1
+; CHECK-NEXT:    bc 12, 20, .LBB35_2
+; CHECK-NEXT:  # %bb.1: # %entry
+; CHECK-NEXT:    ori 3, 7, 0
+; CHECK-NEXT:    blr
+; CHECK-NEXT:  .LBB35_2: # %entry
+; CHECK-NEXT:    addi 3, 0, 0
+; CHECK-NEXT:    blr
   entry:
   %r = fcmp uno double %a, %b
   ret i1 %r
-; CHECK-LABEL: test_dcmpuno
-; CHECK: efdcmpeq
-; CHECK: efdcmpeq
-; CHECK: crand
-; CHECK: blr
 }
 
 define i1 @test_dcmpord(double %a, double %b) {
+; CHECK-LABEL: test_dcmpord:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    evmergelo 3, 3, 4
+; CHECK-NEXT:    evmergelo 4, 5, 6
+; CHECK-NEXT:    li 7, 1
+; CHECK-NEXT:    efdcmpeq 0, 4, 4
+; CHECK-NEXT:    efdcmpeq 1, 3, 3
+; CHECK-NEXT:    crnand 20, 5, 1
+; CHECK-NEXT:    bc 12, 20, .LBB36_2
+; CHECK-NEXT:  # %bb.1: # %entry
+; CHECK-NEXT:    ori 3, 7, 0
+; CHECK-NEXT:    blr
+; CHECK-NEXT:  .LBB36_2: # %entry
+; CHECK-NEXT:    addi 3, 0, 0
+; CHECK-NEXT:    blr
   entry:
   %r = fcmp ord double %a, %b
   ret i1 %r
-; CHECK-LABEL: test_dcmpord
-; CHECK: efdcmpeq
-; CHECK: efdcmpeq
-; CHECK: crnand
-; CHECK: blr
-}
-
-define i1 @test_dcmpgt(double %a, double %b) {
-  entry:
-  %r = fcmp ogt double %a, %b
-  ret i1 %r
-; CHECK-LABEL: test_dcmpgt
-; CHECK: efdcmpgt
-; CHECK: blr
 }
 
-define i1 @test_dcmpugt(double %a, double %b) {
-  entry:
-  %r = fcmp ugt double %a, %b
-  ret i1 %r
-; CHECK-LABEL: test_dcmpugt
-; CHECK: efdcmpgt
-; CHECK: blr
-}
-
-define i1 @test_dcmple(double %a, double %b) {
-  entry:
-  %r = fcmp ole double %a, %b
-  ret i1 %r
-; CHECK-LABEL: test_dcmple
-; CHECK: efdcmpgt
-; CHECK: blr
-}
-
-define i1 @test_dcmpule(double %a, double %b) {
-  entry:
-  %r = fcmp ule double %a, %b
-  ret i1 %r
-; CHECK-LABEL: test_dcmpule
-; CHECK: efdcmpgt
-; CHECK: blr
-}
-
-define i1 @test_dcmpeq(double %a, double %b) {
-  entry:
-  %r = fcmp oeq double %a, %b
-  ret i1 %r
-; CHECK-LABEL: test_dcmpeq
-; CHECK: efdcmpeq
-; CHECK: blr
-}
-
-define i1 @test_dcmpueq(double %a, double %b) {
-  entry:
-  %r = fcmp ueq double %a, %b
-  ret i1 %r
-; CHECK-LABEL: test_dcmpueq
-; CHECK: efdcmpeq
-; CHECK: blr
+define i32 @test_dcmpgt(double %a, double %b) {
+; CHECK-LABEL: test_dcmpgt:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    stwu 1, -16(1)
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    evmergelo 5, 5, 6
+; CHECK-NEXT:    evmergelo 3, 3, 4
+; CHECK-NEXT:    efdcmpgt 0, 3, 5
+; CHECK-NEXT:    ble 0, .LBB37_2
+; CHECK-NEXT:  # %bb.1: # %tr
+; CHECK-NEXT:    li 3, 1
+; CHECK-NEXT:    b .LBB37_3
+; CHECK-NEXT:  .LBB37_2: # %fa
+; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:  .LBB37_3: # %ret
+; CHECK-NEXT:    stw 3, 12(1)
+; CHECK-NEXT:    lwz 3, 12(1)
+; CHECK-NEXT:    addi 1, 1, 16
+; CHECK-NEXT:    blr
+  entry:
+  %r = alloca i32, align 4
+  %c = fcmp ogt double %a, %b
+  br i1 %c, label %tr, label %fa
+tr:
+  store i32 1, i32* %r, align 4
+  br label %ret
+fa:
+  store i32 0, i32* %r, align 4
+  br label %ret
+ret:
+  %0 = load i32, i32* %r, align 4
+  ret i32 %0
+}
+
+define i32 @test_dcmpugt(double %a, double %b) {
+; CHECK-LABEL: test_dcmpugt:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    stwu 1, -16(1)
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    evmergelo 3, 3, 4
+; CHECK-NEXT:    evmergelo 4, 5, 6
+; CHECK-NEXT:    efdcmpeq 0, 4, 4
+; CHECK-NEXT:    bc 4, 1, .LBB38_4
+; CHECK-NEXT:  # %bb.1: # %entry
+; CHECK-NEXT:    efdcmpeq 0, 3, 3
+; CHECK-NEXT:    bc 4, 1, .LBB38_4
+; CHECK-NEXT:  # %bb.2: # %entry
+; CHECK-NEXT:    efdcmpgt 0, 3, 4
+; CHECK-NEXT:    bc 12, 1, .LBB38_4
+; CHECK-NEXT:  # %bb.3: # %fa
+; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:    b .LBB38_5
+; CHECK-NEXT:  .LBB38_4: # %tr
+; CHECK-NEXT:    li 3, 1
+; CHECK-NEXT:  .LBB38_5: # %ret
+; CHECK-NEXT:    stw 3, 12(1)
+; CHECK-NEXT:    lwz 3, 12(1)
+; CHECK-NEXT:    addi 1, 1, 16
+; CHECK-NEXT:    blr
+  entry:
+  %r = alloca i32, align 4
+  %c = fcmp ugt double %a, %b
+  br i1 %c, label %tr, label %fa
+tr:
+  store i32 1, i32* %r, align 4
+  br label %ret
+fa:
+  store i32 0, i32* %r, align 4
+  br label %ret
+ret:
+  %0 = load i32, i32* %r, align 4
+  ret i32 %0
+}
+
+define i32 @test_dcmple(double %a, double %b) {
+; CHECK-LABEL: test_dcmple:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    stwu 1, -16(1)
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    evmergelo 5, 5, 6
+; CHECK-NEXT:    evmergelo 3, 3, 4
+; CHECK-NEXT:    efdcmpgt 0, 3, 5
+; CHECK-NEXT:    bgt 0, .LBB39_2
+; CHECK-NEXT:  # %bb.1: # %tr
+; CHECK-NEXT:    li 3, 1
+; CHECK-NEXT:    b .LBB39_3
+; CHECK-NEXT:  .LBB39_2: # %fa
+; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:  .LBB39_3: # %ret
+; CHECK-NEXT:    stw 3, 12(1)
+; CHECK-NEXT:    lwz 3, 12(1)
+; CHECK-NEXT:    addi 1, 1, 16
+; CHECK-NEXT:    blr
+  entry:
+  %r = alloca i32, align 4
+  %c = fcmp ule double %a, %b
+  br i1 %c, label %tr, label %fa
+tr:
+  store i32 1, i32* %r, align 4
+  br label %ret
+fa:
+  store i32 0, i32* %r, align 4
+  br label %ret
+ret:
+  %0 = load i32, i32* %r, align 4
+  ret i32 %0
+}
+
+define i32 @test_dcmpule(double %a, double %b) {
+; CHECK-LABEL: test_dcmpule:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    stwu 1, -16(1)
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    evmergelo 5, 5, 6
+; CHECK-NEXT:    evmergelo 3, 3, 4
+; CHECK-NEXT:    efdcmpgt 0, 3, 5
+; CHECK-NEXT:    bgt 0, .LBB40_2
+; CHECK-NEXT:  # %bb.1: # %tr
+; CHECK-NEXT:    li 3, 1
+; CHECK-NEXT:    b .LBB40_3
+; CHECK-NEXT:  .LBB40_2: # %fa
+; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:  .LBB40_3: # %ret
+; CHECK-NEXT:    stw 3, 12(1)
+; CHECK-NEXT:    lwz 3, 12(1)
+; CHECK-NEXT:    addi 1, 1, 16
+; CHECK-NEXT:    blr
+  entry:
+  %r = alloca i32, align 4
+  %c = fcmp ule double %a, %b
+  br i1 %c, label %tr, label %fa
+tr:
+  store i32 1, i32* %r, align 4
+  br label %ret
+fa:
+  store i32 0, i32* %r, align 4
+  br label %ret
+ret:
+  %0 = load i32, i32* %r, align 4
+  ret i32 %0
+}
+
+; The type of comparison found in C's if (x == y)
+define i32 @test_dcmpeq(double %a, double %b) {
+; CHECK-LABEL: test_dcmpeq:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    stwu 1, -16(1)
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    evmergelo 5, 5, 6
+; CHECK-NEXT:    evmergelo 3, 3, 4
+; CHECK-NEXT:    efdcmpeq 0, 3, 5
+; CHECK-NEXT:    ble 0, .LBB41_2
+; CHECK-NEXT:  # %bb.1: # %tr
+; CHECK-NEXT:    li 3, 1
+; CHECK-NEXT:    b .LBB41_3
+; CHECK-NEXT:  .LBB41_2: # %fa
+; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:  .LBB41_3: # %ret
+; CHECK-NEXT:    stw 3, 12(1)
+; CHECK-NEXT:    lwz 3, 12(1)
+; CHECK-NEXT:    addi 1, 1, 16
+; CHECK-NEXT:    blr
+  entry:
+  %r = alloca i32, align 4
+  %c = fcmp oeq double %a, %b
+  br i1 %c, label %tr, label %fa
+tr:
+  store i32 1, i32* %r, align 4
+  br label %ret
+fa:
+  store i32 0, i32* %r, align 4
+  br label %ret
+ret:
+  %0 = load i32, i32* %r, align 4
+  ret i32 %0
+}
+
+define i32 @test_dcmpueq(double %a, double %b) {
+; CHECK-LABEL: test_dcmpueq:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    stwu 1, -16(1)
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    evmergelo 3, 3, 4
+; CHECK-NEXT:    evmergelo 4, 5, 6
+; CHECK-NEXT:    efdcmpeq 0, 4, 4
+; CHECK-NEXT:    bc 4, 1, .LBB42_4
+; CHECK-NEXT:  # %bb.1: # %entry
+; CHECK-NEXT:    efdcmpeq 0, 3, 3
+; CHECK-NEXT:    bc 4, 1, .LBB42_4
+; CHECK-NEXT:  # %bb.2: # %entry
+; CHECK-NEXT:    efdcmpeq 0, 3, 4
+; CHECK-NEXT:    bc 12, 1, .LBB42_4
+; CHECK-NEXT:  # %bb.3: # %fa
+; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:    b .LBB42_5
+; CHECK-NEXT:  .LBB42_4: # %tr
+; CHECK-NEXT:    li 3, 1
+; CHECK-NEXT:  .LBB42_5: # %ret
+; CHECK-NEXT:    stw 3, 12(1)
+; CHECK-NEXT:    lwz 3, 12(1)
+; CHECK-NEXT:    addi 1, 1, 16
+; CHECK-NEXT:    blr
+  entry:
+  %r = alloca i32, align 4
+  %c = fcmp ueq double %a, %b
+  br i1 %c, label %tr, label %fa
+tr:
+  store i32 1, i32* %r, align 4
+  br label %ret
+fa:
+  store i32 0, i32* %r, align 4
+  br label %ret
+ret:
+  %0 = load i32, i32* %r, align 4
+  ret i32 %0
 }
 
 define i1 @test_dcmpne(double %a, double %b) {
+; CHECK-LABEL: test_dcmpne:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    evmergelo 3, 3, 4
+; CHECK-NEXT:    evmergelo 4, 5, 6
+; CHECK-NEXT:    li 7, 1
+; CHECK-NEXT:    efdcmpeq 0, 4, 4
+; CHECK-NEXT:    efdcmpeq 1, 3, 3
+; CHECK-NEXT:    efdcmpeq 5, 3, 4
+; CHECK-NEXT:    crand 24, 5, 1
+; CHECK-NEXT:    crorc 20, 21, 24
+; CHECK-NEXT:    bc 12, 20, .LBB43_2
+; CHECK-NEXT:  # %bb.1: # %entry
+; CHECK-NEXT:    ori 3, 7, 0
+; CHECK-NEXT:    blr
+; CHECK-NEXT:  .LBB43_2: # %entry
+; CHECK-NEXT:    addi 3, 0, 0
+; CHECK-NEXT:    blr
   entry:
   %r = fcmp one double %a, %b
   ret i1 %r
-; CHECK-LABEL: test_dcmpne
-; CHECK: efdcmpeq
-; CHECK: blr
-}
-
-define i1 @test_dcmpune(double %a, double %b) {
-  entry:
-  %r = fcmp une double %a, %b
-  ret i1 %r
-; CHECK-LABEL: test_dcmpune
-; CHECK: efdcmpeq
-; CHECK: blr
-}
-
-define i1 @test_dcmplt(double %a, double %b) {
-  entry:
-  %r = fcmp olt double %a, %b
-  ret i1 %r
-; CHECK-LABEL: test_dcmplt
-; CHECK: efdcmplt
-; CHECK: blr
 }
 
-define i1 @test_dcmpult(double %a, double %b) {
-  entry:
-  %r = fcmp ult double %a, %b
-  ret i1 %r
-; CHECK-LABEL: test_dcmpult
-; CHECK: efdcmplt
-; CHECK: blr
+define i32 @test_dcmpune(double %a, double %b) {
+; CHECK-LABEL: test_dcmpune:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    stwu 1, -16(1)
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    evmergelo 5, 5, 6
+; CHECK-NEXT:    evmergelo 3, 3, 4
+; CHECK-NEXT:    efdcmpeq 0, 3, 5
+; CHECK-NEXT:    bgt 0, .LBB44_2
+; CHECK-NEXT:  # %bb.1: # %tr
+; CHECK-NEXT:    li 3, 1
+; CHECK-NEXT:    b .LBB44_3
+; CHECK-NEXT:  .LBB44_2: # %fa
+; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:  .LBB44_3: # %ret
+; CHECK-NEXT:    stw 3, 12(1)
+; CHECK-NEXT:    lwz 3, 12(1)
+; CHECK-NEXT:    addi 1, 1, 16
+; CHECK-NEXT:    blr
+  entry:
+  %r = alloca i32, align 4
+  %c = fcmp une double %a, %b
+  br i1 %c, label %tr, label %fa
+tr:
+  store i32 1, i32* %r, align 4
+  br label %ret
+fa:
+  store i32 0, i32* %r, align 4
+  br label %ret
+ret:
+  %0 = load i32, i32* %r, align 4
+  ret i32 %0
+}
+
+define i32 @test_dcmplt(double %a, double %b) {
+; CHECK-LABEL: test_dcmplt:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    stwu 1, -16(1)
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    evmergelo 5, 5, 6
+; CHECK-NEXT:    evmergelo 3, 3, 4
+; CHECK-NEXT:    efdcmplt 0, 3, 5
+; CHECK-NEXT:    ble 0, .LBB45_2
+; CHECK-NEXT:  # %bb.1: # %tr
+; CHECK-NEXT:    li 3, 1
+; CHECK-NEXT:    b .LBB45_3
+; CHECK-NEXT:  .LBB45_2: # %fa
+; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:  .LBB45_3: # %ret
+; CHECK-NEXT:    stw 3, 12(1)
+; CHECK-NEXT:    lwz 3, 12(1)
+; CHECK-NEXT:    addi 1, 1, 16
+; CHECK-NEXT:    blr
+  entry:
+  %r = alloca i32, align 4
+  %c = fcmp olt double %a, %b
+  br i1 %c, label %tr, label %fa
+tr:
+  store i32 1, i32* %r, align 4
+  br label %ret
+fa:
+  store i32 0, i32* %r, align 4
+  br label %ret
+ret:
+  %0 = load i32, i32* %r, align 4
+  ret i32 %0
+}
+
+define i32 @test_dcmpult(double %a, double %b) {
+; CHECK-LABEL: test_dcmpult:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    stwu 1, -16(1)
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    evmergelo 3, 3, 4
+; CHECK-NEXT:    evmergelo 4, 5, 6
+; CHECK-NEXT:    efdcmpeq 0, 4, 4
+; CHECK-NEXT:    bc 4, 1, .LBB46_4
+; CHECK-NEXT:  # %bb.1: # %entry
+; CHECK-NEXT:    efdcmpeq 0, 3, 3
+; CHECK-NEXT:    bc 4, 1, .LBB46_4
+; CHECK-NEXT:  # %bb.2: # %entry
+; CHECK-NEXT:    efdcmplt 0, 3, 4
+; CHECK-NEXT:    bc 12, 1, .LBB46_4
+; CHECK-NEXT:  # %bb.3: # %fa
+; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:    b .LBB46_5
+; CHECK-NEXT:  .LBB46_4: # %tr
+; CHECK-NEXT:    li 3, 1
+; CHECK-NEXT:  .LBB46_5: # %ret
+; CHECK-NEXT:    stw 3, 12(1)
+; CHECK-NEXT:    lwz 3, 12(1)
+; CHECK-NEXT:    addi 1, 1, 16
+; CHECK-NEXT:    blr
+  entry:
+  %r = alloca i32, align 4
+  %c = fcmp ult double %a, %b
+  br i1 %c, label %tr, label %fa
+tr:
+  store i32 1, i32* %r, align 4
+  br label %ret
+fa:
+  store i32 0, i32* %r, align 4
+  br label %ret
+ret:
+  %0 = load i32, i32* %r, align 4
+  ret i32 %0
 }
 
 define i1 @test_dcmpge(double %a, double %b) {
+; CHECK-LABEL: test_dcmpge:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    evmergelo 3, 3, 4
+; CHECK-NEXT:    evmergelo 4, 5, 6
+; CHECK-NEXT:    li 7, 1
+; CHECK-NEXT:    efdcmpeq 0, 4, 4
+; CHECK-NEXT:    efdcmpeq 1, 3, 3
+; CHECK-NEXT:    efdcmplt 5, 3, 4
+; CHECK-NEXT:    crand 24, 5, 1
+; CHECK-NEXT:    crorc 20, 21, 24
+; CHECK-NEXT:    bc 12, 20, .LBB47_2
+; CHECK-NEXT:  # %bb.1: # %entry
+; CHECK-NEXT:    ori 3, 7, 0
+; CHECK-NEXT:    blr
+; CHECK-NEXT:  .LBB47_2: # %entry
+; CHECK-NEXT:    addi 3, 0, 0
+; CHECK-NEXT:    blr
   entry:
   %r = fcmp oge double %a, %b
   ret i1 %r
-; CHECK-LABEL: test_dcmpge
-; CHECK: efdcmplt
-; CHECK: blr
 }
 
-define i1 @test_dcmpuge(double %a, double %b) {
-  entry:
-  %r = fcmp uge double %a, %b
-  ret i1 %r
-; CHECK-LABEL: test_dcmpuge
-; CHECK: efdcmplt
-; CHECK: blr
+define i32 @test_dcmpuge(double %a, double %b) {
+; CHECK-LABEL: test_dcmpuge:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    stwu 1, -16(1)
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    evmergelo 5, 5, 6
+; CHECK-NEXT:    evmergelo 3, 3, 4
+; CHECK-NEXT:    efdcmplt 0, 3, 5
+; CHECK-NEXT:    bgt 0, .LBB48_2
+; CHECK-NEXT:  # %bb.1: # %tr
+; CHECK-NEXT:    li 3, 1
+; CHECK-NEXT:    b .LBB48_3
+; CHECK-NEXT:  .LBB48_2: # %fa
+; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:  .LBB48_3: # %ret
+; CHECK-NEXT:    stw 3, 12(1)
+; CHECK-NEXT:    lwz 3, 12(1)
+; CHECK-NEXT:    addi 1, 1, 16
+; CHECK-NEXT:    blr
+  entry:
+  %r = alloca i32, align 4
+  %c = fcmp uge double %a, %b
+  br i1 %c, label %tr, label %fa
+tr:
+  store i32 1, i32* %r, align 4
+  br label %ret
+fa:
+  store i32 0, i32* %r, align 4
+  br label %ret
+ret:
+  %0 = load i32, i32* %r, align 4
+  ret i32 %0
 }
 
 define double @test_dselect(double %a, double %b, i1 %c) {
+; CHECK-LABEL: test_dselect:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    andi. 7, 7, 1
+; CHECK-NEXT:    evmergelo 5, 5, 6
+; CHECK-NEXT:    evmergelo 4, 3, 4
+; CHECK-NEXT:    bc 12, 1, .LBB49_2
+; CHECK-NEXT:  # %bb.1: # %entry
+; CHECK-NEXT:    evor 4, 5, 5
+; CHECK-NEXT:  .LBB49_2: # %entry
+; CHECK-NEXT:    evmergehi 3, 4, 4
+; CHECK-NEXT:    # kill: def $r4 killed $r4 killed $s4
+; CHECK-NEXT:    # kill: def $r3 killed $r3 killed $s3
+; CHECK-NEXT:    blr
 entry:
   %r = select i1 %c, double %a, double %b
   ret double %r
-; CHECK-LABEL: test_dselect
-; CHECK: andi.
-; CHECK: bc
-; CHECK: evor
-; CHECK: evmergehi
-; CHECK: blr
 }
 
 define i32 @test_dtoui(double %a) {
+; CHECK-LABEL: test_dtoui:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    evmergelo 3, 3, 4
+; CHECK-NEXT:    efdctuiz 3, 3
+; CHECK-NEXT:    blr
 entry:
   %v = fptoui double %a to i32
   ret i32 %v
-; CHECK-LABEL: test_dtoui
-; CHECK: efdctuiz
 }
 
 define i32 @test_dtosi(double %a) {
+; CHECK-LABEL: test_dtosi:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    evmergelo 3, 3, 4
+; CHECK-NEXT:    efdctsiz 3, 3
+; CHECK-NEXT:    blr
 entry:
   %v = fptosi double %a to i32
   ret i32 %v
-; CHECK-LABEL: test_dtosi
-; CHECK: efdctsiz
 }
 
 define double @test_dfromui(i32 %a) {
+; CHECK-LABEL: test_dfromui:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    efdcfui 4, 3
+; CHECK-NEXT:    evmergehi 3, 4, 4
+; CHECK-NEXT:    # kill: def $r4 killed $r4 killed $s4
+; CHECK-NEXT:    # kill: def $r3 killed $r3 killed $s3
+; CHECK-NEXT:    blr
 entry:
   %v = uitofp i32 %a to double
   ret double %v
-; CHECK-LABEL: test_dfromui
-; CHECK: efdcfui
 }
 
 define double @test_dfromsi(i32 %a) {
+; CHECK-LABEL: test_dfromsi:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    efdcfsi 4, 3
+; CHECK-NEXT:    evmergehi 3, 4, 4
+; CHECK-NEXT:    # kill: def $r4 killed $r4 killed $s4
+; CHECK-NEXT:    # kill: def $r3 killed $r3 killed $s3
+; CHECK-NEXT:    blr
 entry:
   %v = sitofp i32 %a to double
   ret double %v
-; CHECK-LABEL: test_dfromsi
-; CHECK: efdcfsi
 }
 
 define i32 @test_dasmconst(double %x) {
+; CHECK-LABEL: test_dasmconst:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    stwu 1, -16(1)
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    evmergelo 3, 3, 4
+; CHECK-NEXT:    evstdd 3, 8(1)
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    efdctsi 3, 3
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    addi 1, 1, 16
+; CHECK-NEXT:    blr
 entry:
   %x.addr = alloca double, align 8
   store double %x, double* %x.addr, align 8
   %0 = load double, double* %x.addr, align 8
   %1 = call i32 asm sideeffect "efdctsi $0, $1", "=d,d"(double %0)
   ret i32 %1
-; CHECK-LABEL: test_dasmconst
-; CHECK: evmergelo
-; CHECK: #APP
-; CHECK: efdctsi
-; CHECK: #NO_APP
 }
 
 declare double @test_spill_spe_regs(double, double);
 define dso_local void @test_func2() #0 {
+; CHECK-LABEL: test_func2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    blr
 entry:
   ret void
 }
 
 declare void @test_memset(i8* nocapture writeonly, i8, i32, i1)
 @global_var1 = global i32 0, align 4
 define double @test_spill(double %a, i32 %a1, i64 %a2, i8 * %a3, i32 *%a4, i32* %a5) nounwind {
+; CHECK-LABEL: test_spill:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mflr 0
+; CHECK-NEXT:    stw 0, 4(1)
+; CHECK-NEXT:    stwu 1, -352(1)
+; CHECK-NEXT:    li 5, 256
+; CHECK-NEXT:    evstddx 30, 1, 5 # 8-byte Folded Spill
+; CHECK-NEXT:    li 5, 264
+; CHECK-NEXT:    evstddx 31, 1, 5 # 8-byte Folded Spill
+; CHECK-NEXT:    li 5, .LCPI56_0@l
+; CHECK-NEXT:    lis 6, .LCPI56_0@ha
+; CHECK-NEXT:    evlddx 5, 6, 5
+; CHECK-NEXT:    stw 14, 280(1) # 4-byte Folded Spill
+; CHECK-NEXT:    stw 15, 284(1) # 4-byte Folded Spill
+; CHECK-NEXT:    stw 16, 288(1) # 4-byte Folded Spill
+; CHECK-NEXT:    stw 17, 292(1) # 4-byte Folded Spill
+; CHECK-NEXT:    stw 18, 296(1) # 4-byte Folded Spill
+; CHECK-NEXT:    stw 19, 300(1) # 4-byte Folded Spill
+; CHECK-NEXT:    stw 20, 304(1) # 4-byte Folded Spill
+; CHECK-NEXT:    stw 21, 308(1) # 4-byte Folded Spill
+; CHECK-NEXT:    stw 22, 312(1) # 4-byte Folded Spill
+; CHECK-NEXT:    stw 23, 316(1) # 4-byte Folded Spill
+; CHECK-NEXT:    stw 24, 320(1) # 4-byte Folded Spill
+; CHECK-NEXT:    stw 25, 324(1) # 4-byte Folded Spill
+; CHECK-NEXT:    stw 26, 328(1) # 4-byte Folded Spill
+; CHECK-NEXT:    stw 27, 332(1) # 4-byte Folded Spill
+; CHECK-NEXT:    stw 28, 336(1) # 4-byte Folded Spill
+; CHECK-NEXT:    stw 29, 340(1) # 4-byte Folded Spill
+; CHECK-NEXT:    stw 30, 344(1) # 4-byte Folded Spill
+; CHECK-NEXT:    stw 31, 348(1) # 4-byte Folded Spill
+; CHECK-NEXT:    evstdd 14, 128(1) # 8-byte Folded Spill
+; CHECK-NEXT:    evstdd 15, 136(1) # 8-byte Folded Spill
+; CHECK-NEXT:    evstdd 16, 144(1) # 8-byte Folded Spill
+; CHECK-NEXT:    evstdd 17, 152(1) # 8-byte Folded Spill
+; CHECK-NEXT:    evstdd 18, 160(1) # 8-byte Folded Spill
+; CHECK-NEXT:    evstdd 19, 168(1) # 8-byte Folded Spill
+; CHECK-NEXT:    evstdd 20, 176(1) # 8-byte Folded Spill
+; CHECK-NEXT:    evstdd 21, 184(1) # 8-byte Folded Spill
+; CHECK-NEXT:    evstdd 22, 192(1) # 8-byte Folded Spill
+; CHECK-NEXT:    evstdd 23, 200(1) # 8-byte Folded Spill
+; CHECK-NEXT:    evstdd 24, 208(1) # 8-byte Folded Spill
+; CHECK-NEXT:    evstdd 25, 216(1) # 8-byte Folded Spill
+; CHECK-NEXT:    evstdd 26, 224(1) # 8-byte Folded Spill
+; CHECK-NEXT:    evstdd 27, 232(1) # 8-byte Folded Spill
+; CHECK-NEXT:    evstdd 28, 240(1) # 8-byte Folded Spill
+; CHECK-NEXT:    evstdd 29, 248(1) # 8-byte Folded Spill
+; CHECK-NEXT:    evmergelo 3, 3, 4
+; CHECK-NEXT:    lwz 4, 360(1)
+; CHECK-NEXT:    efdadd 3, 3, 3
+; CHECK-NEXT:    efdadd 3, 3, 5
+; CHECK-NEXT:    evstdd 3, 24(1) # 8-byte Folded Spill
+; CHECK-NEXT:    stw 4, 20(1) # 4-byte Folded Spill
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    addi 3, 1, 76
+; CHECK-NEXT:    li 4, 0
+; CHECK-NEXT:    li 5, 24
+; CHECK-NEXT:    li 6, 1
+; CHECK-NEXT:    li 30, 0
+; CHECK-NEXT:    bl test_memset
+; CHECK-NEXT:    lwz 3, 20(1) # 4-byte Folded Reload
+; CHECK-NEXT:    stw 30, 0(3)
+; CHECK-NEXT:    bl test_func2
+; CHECK-NEXT:    addi 3, 1, 32
+; CHECK-NEXT:    li 4, 0
+; CHECK-NEXT:    li 5, 20
+; CHECK-NEXT:    li 6, 1
+; CHECK-NEXT:    bl test_memset
+; CHECK-NEXT:    evldd 4, 24(1) # 8-byte Folded Reload
+; CHECK-NEXT:    li 5, 264
+; CHECK-NEXT:    evmergehi 3, 4, 4
+; CHECK-NEXT:    evlddx 31, 1, 5 # 8-byte Folded Reload
+; CHECK-NEXT:    li 5, 256
+; CHECK-NEXT:    evlddx 30, 1, 5 # 8-byte Folded Reload
+; CHECK-NEXT:    evldd 29, 248(1) # 8-byte Folded Reload
+; CHECK-NEXT:    evldd 28, 240(1) # 8-byte Folded Reload
+; CHECK-NEXT:    evldd 27, 232(1) # 8-byte Folded Reload
+; CHECK-NEXT:    evldd 26, 224(1) # 8-byte Folded Reload
+; CHECK-NEXT:    evldd 25, 216(1) # 8-byte Folded Reload
+; CHECK-NEXT:    evldd 24, 208(1) # 8-byte Folded Reload
+; CHECK-NEXT:    evldd 23, 200(1) # 8-byte Folded Reload
+; CHECK-NEXT:    evldd 22, 192(1) # 8-byte Folded Reload
+; CHECK-NEXT:    evldd 21, 184(1) # 8-byte Folded Reload
+; CHECK-NEXT:    evldd 20, 176(1) # 8-byte Folded Reload
+; CHECK-NEXT:    evldd 19, 168(1) # 8-byte Folded Reload
+; CHECK-NEXT:    evldd 18, 160(1) # 8-byte Folded Reload
+; CHECK-NEXT:    evldd 17, 152(1) # 8-byte Folded Reload
+; CHECK-NEXT:    evldd 16, 144(1) # 8-byte Folded Reload
+; CHECK-NEXT:    evldd 15, 136(1) # 8-byte Folded Reload
+; CHECK-NEXT:    evldd 14, 128(1) # 8-byte Folded Reload
+; CHECK-NEXT:    # kill: def $r3 killed $r3 killed $s3
+; CHECK-NEXT:    # kill: def $r4 killed $r4 killed $s4
+; CHECK-NEXT:    lwz 31, 348(1) # 4-byte Folded Reload
+; CHECK-NEXT:    lwz 30, 344(1) # 4-byte Folded Reload
+; CHECK-NEXT:    lwz 29, 340(1) # 4-byte Folded Reload
+; CHECK-NEXT:    lwz 28, 336(1) # 4-byte Folded Reload
+; CHECK-NEXT:    lwz 27, 332(1) # 4-byte Folded Reload
+; CHECK-NEXT:    lwz 26, 328(1) # 4-byte Folded Reload
+; CHECK-NEXT:    lwz 25, 324(1) # 4-byte Folded Reload
+; CHECK-NEXT:    lwz 24, 320(1) # 4-byte Folded Reload
+; CHECK-NEXT:    lwz 23, 316(1) # 4-byte Folded Reload
+; CHECK-NEXT:    lwz 22, 312(1) # 4-byte Folded Reload
+; CHECK-NEXT:    lwz 21, 308(1) # 4-byte Folded Reload
+; CHECK-NEXT:    lwz 20, 304(1) # 4-byte Folded Reload
+; CHECK-NEXT:    lwz 19, 300(1) # 4-byte Folded Reload
+; CHECK-NEXT:    lwz 18, 296(1) # 4-byte Folded Reload
+; CHECK-NEXT:    lwz 17, 292(1) # 4-byte Folded Reload
+; CHECK-NEXT:    lwz 16, 288(1) # 4-byte Folded Reload
+; CHECK-NEXT:    lwz 15, 284(1) # 4-byte Folded Reload
+; CHECK-NEXT:    lwz 14, 280(1) # 4-byte Folded Reload
+; CHECK-NEXT:    lwz 0, 356(1)
+; CHECK-NEXT:    addi 1, 1, 352
+; CHECK-NEXT:    mtlr 0
+; CHECK-NEXT:    blr
 entry:
   %v1 = alloca [13 x i32], align 4
   %v2 = alloca [11 x i32], align 4
   %0 = fadd double %a, %a
   call void asm sideeffect "","~{s0},~{s3},~{s4},~{s5},~{s6},~{s7},~{s8},~{s9},~{s10},~{s11},~{s12},~{s13},~{s14},~{s15},~{s16},~{s17},~{s18},~{s19},~{s20},~{s21},~{s22},~{s23},~{s24},~{s25},~{s26},~{s27},~{s28},~{s29},~{s30},~{s31}"() nounwind
   %1 = fadd double %0, 3.14159
   %2 = bitcast [13 x i32]* %v1 to i8*
   call void @test_memset(i8* align 4 %2, i8 0, i32 24, i1 true)
   store i32 0, i32* %a5, align 4
   call void @test_func2()
   %3 = bitcast [11 x i32]* %v2 to i8*
   call void @test_memset(i8* align 4 %3, i8 0, i32 20, i1 true)
   br label %return
 
 return:
   ret double %1
 
-; CHECK-LABEL: test_spill
-; CHECK: li [[VREG:[0-9]+]], 256
-; CHECK: evstddx {{[0-9]+}}, {{[0-9]+}}, [[VREG]]
-; CHECK-NOT: evstdd {{[0-9]+}}, 256({{[0-9]+}}
-; CHECK: evstdd
-; CHECK: efdadd
-; CHECK: evldd
 }