diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h b/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
--- a/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
@@ -157,6 +157,32 @@
     return tryFoldImplicitDef(MI, DeadInsts);
   }
 
+  bool tryCombineTrunc(MachineInstr &MI,
+                       SmallVectorImpl<MachineInstr *> &DeadInsts) {
+    assert(MI.getOpcode() == TargetOpcode::G_TRUNC);
+
+    Builder.setInstr(MI);
+    Register DstReg = MI.getOperand(0).getReg();
+    Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg());
+
+    // Try to fold trunc(g_constant) when the smaller constant type is legal.
+    // Can't use MIPattern because we don't have a specific constant in mind.
+    auto *SrcMI = MRI.getVRegDef(SrcReg);
+    if (SrcMI->getOpcode() == TargetOpcode::G_CONSTANT) {
+      const LLT &DstTy = MRI.getType(DstReg);
+      if (isInstLegal({TargetOpcode::G_CONSTANT, {DstTy}})) {
+        auto &CstVal = SrcMI->getOperand(1);
+        Builder.buildConstant(
+            DstReg, CstVal.getCImm()->getValue().trunc(DstTy.getSizeInBits()));
+        markInstAndDefDead(MI, *SrcMI, DeadInsts);
+        return true;
+      }
+    }
+
+    return false;
+  }
+
+
   /// Try to fold G_[ASZ]EXT (G_IMPLICIT_DEF).
   bool tryFoldImplicitDef(MachineInstr &MI,
                           SmallVectorImpl<MachineInstr *> &DeadInsts) {
@@ -420,6 +446,9 @@
     case TargetOpcode::G_EXTRACT:
       return tryCombineExtract(MI, DeadInsts);
     case TargetOpcode::G_TRUNC: {
+      if (tryCombineTrunc(MI, DeadInsts))
+        return true;
+
       bool Changed = false;
       for (auto &Use : MRI.use_instructions(MI.getOperand(0).getReg()))
         Changed |= tryCombineInstruction(Use, DeadInsts, WrapperObserver);
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-merge-values.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-merge-values.mir
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-merge-values.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-merge-values.mir
@@ -6,19 +6,18 @@
 body: |
   bb.0:
     ; CHECK-LABEL: name: test_merge_s4
-    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
-    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
-    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
-    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)
-    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C2]]
-    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C1]](s32)
-    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)
-    ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C2]]
-    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
-    ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[COPY]]
-    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[OR]](s32)
-    ; CHECK: [[COPY1:%[0-9]+]]:_(s8) = COPY [[TRUNC2]](s8)
-    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY1]](s8)
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
+    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[C2]], [[C1]]
+    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+    ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
+    ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[COPY1]]
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[OR]](s32)
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[TRUNC]](s8)
+    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY2]](s8)
     ; CHECK: $x0 = COPY [[ANYEXT]](s64)
     %0:_(s64) = G_CONSTANT i64 0
     %1:_(s4) = G_TRUNC %0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ext-legalizer.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ext-legalizer.mir
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ext-legalizer.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ext-legalizer.mir
@@ -10,11 +10,10 @@
     ; CHECK-LABEL: name: test_sext_trunc_i64_i32_i64
     ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
     ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
-    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
-    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)
-    ; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[TRUNC]](s32)
-    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)
-    ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[TRUNC1]](s32)
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+    ; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY1]], [[C]](s32)
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY2]](s32)
     ; CHECK: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
     %0:_(s64) = COPY $vgpr0_vgpr1
     %1:_(s32) = G_TRUNC %0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
@@ -804,11 +804,10 @@
     liveins: $vgpr0_vgpr1
     ; CHECK-LABEL: name: test_extract_s8_s64_offset2
     ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
-    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
-    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)
-    ; CHECK: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[TRUNC]](s32)
-    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
-    ; CHECK: $vgpr0 = COPY [[TRUNC1]](s32)
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+    ; CHECK: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[C]](s32)
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
+    ; CHECK: $vgpr0 = COPY [[TRUNC]](s32)
     %0:_(s64) = COPY $vgpr0_vgpr1
     %1:_(s8) = G_EXTRACT %0, 2
     %2:_(s32) = G_ANYEXT %1
@@ -841,11 +840,10 @@
     liveins: $vgpr0_vgpr1
     ; CHECK-LABEL: name: test_extract_s8_s64_offset16
     ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
-    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
-    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)
-    ; CHECK: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[TRUNC]](s32)
-    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
-    ; CHECK: $vgpr0 = COPY [[TRUNC1]](s32)
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+    ; CHECK: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[C]](s32)
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
+    ; CHECK: $vgpr0 = COPY [[TRUNC]](s32)
     %0:_(s64) = COPY $vgpr0_vgpr1
     %1:_(s8) = G_EXTRACT %0, 16
     %2:_(s32) = G_ANYEXT %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir
@@ -141,10 +141,9 @@
     ; SI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -9223372036854775808
     ; SI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 9223372036854775807
     ; SI: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]]
-    ; SI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
     ; SI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY1]](s32)
-    ; SI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C2]](s64)
-    ; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXT]], [[TRUNC]](s32)
+    ; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+    ; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXT]], [[C2]](s32)
     ; SI: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]
     ; SI: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[AND1]]
     ; SI: $vgpr0_vgpr1 = COPY [[OR]](s64)
@@ -154,10 +153,9 @@
     ; VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -9223372036854775808
     ; VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 9223372036854775807
     ; VI: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]]
-    ; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
     ; VI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY1]](s32)
-    ; VI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C2]](s64)
-    ; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXT]], [[TRUNC]](s32)
+    ; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+    ; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXT]], [[C2]](s32)
     ; VI: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]
     ; VI: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[AND1]]
     ; VI: $vgpr0_vgpr1 = COPY [[OR]](s64)
@@ -167,10 +165,9 @@
     ; GFX9: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -9223372036854775808
     ; GFX9: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 9223372036854775807
     ; GFX9: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]]
-    ; GFX9: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
     ; GFX9: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY1]](s32)
-    ; GFX9: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C2]](s64)
-    ; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXT]], [[TRUNC]](s32)
+    ; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+    ; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXT]], [[C2]](s32)
     ; GFX9: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]
     ; GFX9: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[AND1]]
     ; GFX9: $vgpr0_vgpr1 = COPY [[OR]](s64)
@@ -192,11 +189,10 @@
     ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
     ; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
     ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
-    ; SI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
-    ; SI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C2]](s64)
-    ; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[TRUNC]](s32)
-    ; SI: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
-    ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
+    ; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+    ; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[C2]](s32)
+    ; SI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
+    ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
     ; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[AND1]]
     ; SI: $vgpr0 = COPY [[OR]](s32)
     ; VI-LABEL: name: test_copysign_s32_s64
@@ -205,11 +201,10 @@
     ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
     ; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
     ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
-    ; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
-    ; VI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C2]](s64)
-    ; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[TRUNC]](s32)
-    ; VI: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
-    ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
+    ; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+    ; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[C2]](s32)
+    ; VI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
+    ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
     ; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[AND1]]
     ; VI: $vgpr0 = COPY [[OR]](s32)
     ; GFX9-LABEL: name: test_copysign_s32_s64
@@ -218,11 +213,10 @@
     ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
     ; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
     ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
-    ; GFX9: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
-    ; GFX9: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C2]](s64)
-    ; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[TRUNC]](s32)
-    ; GFX9: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
-    ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
+    ; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+    ; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[C2]](s32)
+    ; GFX9: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
+    ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
     ; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[AND1]]
     ; GFX9: $vgpr0 = COPY [[OR]](s32)
     %0:_(s32) = COPY $vgpr0
@@ -354,12 +348,11 @@
     ; SI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -9223372036854775808
     ; SI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 9223372036854775807
     ; SI: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]]
-    ; SI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
-    ; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
+    ; SI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
     ; SI: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY1]](s32)
-    ; SI: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C3]]
-    ; SI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C2]](s64)
-    ; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[AND1]], [[TRUNC]](s32)
+    ; SI: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C2]]
+    ; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 48
+    ; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[AND1]], [[C3]](s32)
     ; SI: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]
     ; SI: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[AND2]]
     ; SI: $vgpr0_vgpr1 = COPY [[OR]](s64)
@@ -369,12 +362,11 @@
     ; VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -9223372036854775808
     ; VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 9223372036854775807
     ; VI: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]]
-    ; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
-    ; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
+    ; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
     ; VI: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY1]](s32)
-    ; VI: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C3]]
-    ; VI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C2]](s64)
-    ; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[AND1]], [[TRUNC]](s32)
+    ; VI: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C2]]
+    ; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 48
+    ; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[AND1]], [[C3]](s32)
     ; VI: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]
     ; VI: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[AND2]]
     ; VI: $vgpr0_vgpr1 = COPY [[OR]](s64)
@@ -384,12 +376,11 @@
     ; GFX9: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -9223372036854775808
     ; GFX9: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 9223372036854775807
     ; GFX9: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]]
-    ; GFX9: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
-    ; GFX9: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
+    ; GFX9: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
     ; GFX9: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY1]](s32)
-    ; GFX9: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C3]]
-    ; GFX9: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C2]](s64)
-    ; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[AND1]], [[TRUNC]](s32)
+    ; GFX9: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C2]]
+    ; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 48
+    ; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[AND1]], [[C3]](s32)
     ; GFX9: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C]]
     ; GFX9: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[AND2]]
     ; GFX9: $vgpr0_vgpr1 = COPY [[OR]](s64)
@@ -413,11 +404,10 @@
     ; SI: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768
     ; SI: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
     ; SI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
-    ; SI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
-    ; SI: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[C2]](s64)
-    ; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[TRUNC1]](s32)
-    ; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s64)
-    ; SI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C]]
+    ; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 48
+    ; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[C2]](s32)
+    ; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s64)
+    ; SI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
     ; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[AND1]]
     ; SI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
     ; SI: $vgpr0 = COPY [[ANYEXT]](s32)
@@ -428,11 +418,10 @@
     ; VI: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768
     ; VI: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
     ; VI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
-    ; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
-    ; VI: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[C2]](s64)
-    ; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[TRUNC1]](s32)
-    ; VI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s64)
-    ; VI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C]]
+    ; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 48
+    ; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[C2]](s32)
+    ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s64)
+    ; VI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
     ; VI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[AND1]]
     ; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
     ; VI: $vgpr0 = COPY [[ANYEXT]](s32)
@@ -443,11 +432,10 @@
     ; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768
     ; GFX9: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
     ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
-    ; GFX9: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
-    ; GFX9: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[C2]](s64)
-    ; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[TRUNC1]](s32)
-    ; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s64)
-    ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C]]
+    ; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 48
+    ; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[C2]](s32)
+    ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s64)
+    ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
     ; GFX9: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[AND1]]
     ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
     ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
@@ -119,9 +119,9 @@
     ; GFX7: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
     ; GFX7: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
     ; GFX7: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s32), [[AND1]]
-    ; GFX7: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
-    ; GFX7: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
-    ; GFX7: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[TRUNC]], [[TRUNC1]]
+    ; GFX7: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
+    ; GFX7: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+    ; GFX7: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[C2]], [[TRUNC]]
     ; GFX7: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
     ; GFX7: $vgpr0 = COPY [[ANYEXT]](s32)
     ; GFX8-LABEL: name: test_icmp_s8
@@ -133,9 +133,9 @@
     ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
     ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
     ; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s32), [[AND1]]
-    ; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
-    ; GFX8: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
-    ; GFX8: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[TRUNC]], [[TRUNC1]]
+    ; GFX8: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
+    ; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+    ; GFX8: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[C2]], [[TRUNC]]
     ; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
     ; GFX8: $vgpr0 = COPY [[ANYEXT]](s32)
     ; GFX9-LABEL: name: test_icmp_s8
@@ -147,9 +147,9 @@
     ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
     ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
     ; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s32), [[AND1]]
-    ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
-    ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
-    ; GFX9: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[TRUNC]], [[TRUNC1]]
+    ; GFX9: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
+    ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+    ; GFX9: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[C2]], [[TRUNC]]
     ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
     ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
     %0:_(s8) = G_CONSTANT i8 0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir
@@ -92,18 +92,17 @@
 body: |
   bb.0:
     ; CHECK-LABEL: name: test_merge_s16_s8_s8
-    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; CHECK: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
-    ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
-    ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C2]]
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+    ; CHECK: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
+    ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[C2]], [[C1]]
     ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
     ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
-    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32)
     ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C4]]
     ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C3]](s32)
-    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
-    ; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
+    ; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC]]
     ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
     ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
     %0:_(s8) = G_CONSTANT i8 0
@@ -118,28 +117,26 @@
 body: |
   bb.0:
     ; CHECK-LABEL: name: test_merge_s24_s8_s8_s8
-    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
     ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
-    ; CHECK: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
-    ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
-    ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
-    ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
-    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
-    ; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
-    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
-    ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C5]]
+    ; CHECK: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+    ; CHECK: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
+    ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[C2]], [[C1]]
+    ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+    ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C4]]
     ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY]](s32)
-    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
-    ; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
-    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[C2]](s32)
-    ; CHECK: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C3]]
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
+    ; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC]]
+    ; CHECK: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
+    ; CHECK: [[AND2:%[0-9]+]]:_(s16) = G_AND [[C5]], [[C1]]
     ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C5]]
-    ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
-    ; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
-    ; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
+    ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+    ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C3]](s32)
+    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
+    ; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC1]]
     ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
     ; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
     ; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
@@ -160,28 +157,26 @@
 body: |
   bb.0:
     ; CHECK-LABEL: name: test_merge_s32_s8_s8_s8_s8
-    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
-    ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
-    ; CHECK: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
-    ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
-    ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
-    ; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
-    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
-    ; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
-    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
-    ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C6]]
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+    ; CHECK: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+    ; CHECK: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
+    ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[C3]], [[C2]]
+    ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
+    ; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C5]]
     ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY]](s32)
-    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
-    ; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
-    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[C2]](s32)
-    ; CHECK: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C4]]
-    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
-    ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C6]]
-    ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C5]](s32)
-    ; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
-    ; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
+    ; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC]]
+    ; CHECK: [[C6:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
+    ; CHECK: [[AND2:%[0-9]+]]:_(s16) = G_AND [[C6]], [[C2]]
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C5]]
+    ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
+    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
+    ; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC1]]
     ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
     ; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
     ; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
@@ -256,62 +251,62 @@
 body: |
   bb.0:
     ; CHECK-LABEL: name: test_merge_s24_s4_s4_s4_s4_s4_s4
-    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
-    ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
-    ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
-    ; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+    ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+    ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
     ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
-    ; CHECK: [[C6:%[0-9]+]]:_(s16) = G_CONSTANT i16 15
-    ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
-    ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C6]]
-    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
-    ; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
-    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
-    ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C7]]
+    ; CHECK: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 15
+    ; CHECK: [[C6:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
+    ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[C6]], [[C5]]
+    ; CHECK: [[C7:%[0-9]+]]:_(s16) = G_CONSTANT i16 4
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+    ; CHECK: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C8]]
     ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY]](s32)
-    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
-    ; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
-    ; CHECK: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
-    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
-    ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C7]]
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
+    ; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC]]
+    ; CHECK: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
+    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C8]]
     ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[COPY2]](s32)
-    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
-    ; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[OR]], [[TRUNC2]]
-    ; CHECK: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
-    ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
-    ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
-    ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C7]]
+    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
+    ; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[OR]], [[TRUNC1]]
+    ; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
+    ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
+    ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+    ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C8]]
     ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY4]](s32)
-    ; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
-    ; CHECK: [[OR2:%[0-9]+]]:_(s16) = G_OR [[OR1]], [[TRUNC3]]
-    ; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[C4]](s32)
-    ; CHECK: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C6]]
-    ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
-    ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
-    ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C7]]
-    ; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY6]](s32)
-    ; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
-    ; CHECK: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
-    ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C7]]
-    ; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C8]](s32)
-    ; CHECK: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[SHL4]](s32)
-    ; CHECK: [[OR4:%[0-9]+]]:_(s16) = G_OR [[OR3]], [[TRUNC6]]
+    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
+    ; CHECK: [[OR2:%[0-9]+]]:_(s16) = G_OR [[OR1]], [[TRUNC2]]
+    ; CHECK: [[COPY6:%[0-9]+]]:_(s16) = COPY [[C7]](s16)
+    ; CHECK: [[AND4:%[0-9]+]]:_(s16) = G_AND [[COPY6]], [[C5]]
+    ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+    ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
+    ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C8]]
+    ; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY7]](s32)
+    ; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
+    ; CHECK: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC3]]
     ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C7]]
-    ; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C9]](s32)
-    ; CHECK: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL5]](s32)
-    ; CHECK: [[OR5:%[0-9]+]]:_(s16) = G_OR [[OR4]], [[TRUNC7]]
+    ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C8]]
+    ; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C9]](s32)
+    ; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[SHL4]](s32)
+    ; CHECK: [[OR4:%[0-9]+]]:_(s16) = G_OR [[OR3]], [[TRUNC4]]
+    ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C8]]
+    ; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C10]](s32)
+    ; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL5]](s32)
+    ; CHECK: [[OR5:%[0-9]+]]:_(s16) = G_OR [[OR4]], [[TRUNC5]]
     ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)
     ; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR5]](s16)
-    ; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
-    ; CHECK: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C10]](s32)
+    ; CHECK: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+    ; CHECK: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C11]](s32)
     ; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL6]]
-    ; CHECK: [[TRUNC8:%[0-9]+]]:_(s24) = G_TRUNC [[OR6]](s32)
-    ; CHECK: S_NOP 0, implicit [[TRUNC8]](s24)
+    ; CHECK: [[TRUNC6:%[0-9]+]]:_(s24) = G_TRUNC [[OR6]](s32)
+    ; CHECK: S_NOP 0, implicit [[TRUNC6]](s24)
     %0:_(s4) = G_CONSTANT i4 0
     %1:_(s4) = G_CONSTANT i4 1
     %2:_(s4) = G_CONSTANT i4 2
@@ -327,63 +322,63 @@
 body: |
   bb.0:
     ; CHECK-LABEL: name: test_merge_s28_s4_s4_s4_s4_s4_s4_s4
-    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
-    ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
-    ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
-    ; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
-    ; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+    ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+    ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
+    ; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
     ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
-    ; CHECK: [[C7:%[0-9]+]]:_(s16) = G_CONSTANT i16 15
-    ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
-    ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C7]]
-    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
-    ; CHECK: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
-    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
-    ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C8]]
+    ; CHECK: [[C6:%[0-9]+]]:_(s16) = G_CONSTANT i16 15
+    ; CHECK: [[C7:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
+    ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[C7]], [[C6]]
+    ; CHECK: [[C8:%[0-9]+]]:_(s16) = G_CONSTANT i16 4
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+    ; CHECK: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C9]]
     ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY]](s32)
-    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
-    ; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
-    ; CHECK: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
-    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
-    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
-    ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C8]]
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
+    ; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC]]
+    ; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
+    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C9]]
     ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[COPY2]](s32)
-    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
-    ; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[OR]], [[TRUNC2]]
-    ; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
-    ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
-    ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
-    ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C8]]
+    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
+    ; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[OR]], [[TRUNC1]]
+    ; CHECK: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
+    ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
+    ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+    ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C9]]
     ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY4]](s32)
-    ; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
-    ; CHECK: [[OR2:%[0-9]+]]:_(s16) = G_OR [[OR1]], [[TRUNC3]]
-    ; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[C4]](s32)
-    ; CHECK: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C7]]
-    ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
-    ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
-    ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C8]]
-    ; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY6]](s32)
-    ; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
-    ; CHECK: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
-    ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
-    ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C8]]
-    ; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C9]](s32)
-    ; CHECK: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[SHL4]](s32)
-    ; CHECK: [[OR4:%[0-9]+]]:_(s16) = G_OR [[OR3]], [[TRUNC6]]
-    ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C8]]
-    ; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C10]](s32)
-    ; CHECK: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL5]](s32)
-    ; CHECK: [[OR5:%[0-9]+]]:_(s16) = G_OR [[OR4]], [[TRUNC7]]
+    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
+    ; CHECK: [[OR2:%[0-9]+]]:_(s16) = G_OR [[OR1]], [[TRUNC2]]
+    ; CHECK: [[COPY6:%[0-9]+]]:_(s16) = COPY [[C8]](s16)
+    ; CHECK: [[AND4:%[0-9]+]]:_(s16) = G_AND [[COPY6]], [[C6]]
+    ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+    ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
+    ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C9]]
+    ; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY7]](s32)
+    ; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
+    ; CHECK: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC3]]
+    ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
+    ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C9]]
+    ; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C10]](s32)
+    ; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[SHL4]](s32)
+    ; CHECK: [[OR4:%[0-9]+]]:_(s16) = G_OR [[OR3]], [[TRUNC4]]
+    ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+    ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C9]]
+    ; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C11]](s32)
+    ; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL5]](s32)
+    ; CHECK: [[OR5:%[0-9]+]]:_(s16) = G_OR [[OR4]], [[TRUNC5]]
     ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)
     ; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR5]](s16)
-    ; CHECK: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
-    ; CHECK: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C11]](s32)
+    ; CHECK: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+    ; CHECK: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C12]](s32)
     ; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL6]]
-    ; CHECK: [[TRUNC8:%[0-9]+]]:_(s28) = G_TRUNC [[OR6]](s32)
-    ; CHECK: S_NOP 0, implicit [[TRUNC8]](s28)
+    ; CHECK: [[TRUNC6:%[0-9]+]]:_(s28) = G_TRUNC [[OR6]](s32)
+    ; CHECK: S_NOP 0, implicit [[TRUNC6]](s28)
     %0:_(s4) = G_CONSTANT i4 0
     %1:_(s4) = G_CONSTANT i4 1
     %2:_(s4) = G_CONSTANT i4 2
@@ -415,80 +410,76 @@
 body: |
   bb.0:
     ; CHECK-LABEL: name: test_merge_s96_s8_s8_s8_s8_s8_s8_s8_s8_s8_s8_s8_s8
-    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
-    ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
-    ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
-    ; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
-    ; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
-    ; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
-    ; CHECK: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
-    ; CHECK: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 9
-    ; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
-    ; CHECK: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
-    ; CHECK: [[C12:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
-    ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
-    ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C12]]
-    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
-    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
-    ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C13]]
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
+    ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
+    ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+    ; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 9
+    ; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
+    ; CHECK: [[C7:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+    ; CHECK: [[C8:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
+    ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[C8]], [[C7]]
+    ; CHECK: [[C9:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
+    ; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C10]]
     ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY]](s32)
-    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
-    ; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
-    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[C2]](s32)
-    ; CHECK: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C12]]
-    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
-    ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C13]]
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
+    ; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC]]
+    ; CHECK: [[C11:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
+    ; CHECK: [[AND2:%[0-9]+]]:_(s16) = G_AND [[C11]], [[C7]]
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
+    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C10]]
     ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
-    ; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
-    ; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
-    ; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[C4]](s32)
-    ; CHECK: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C12]]
-    ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
-    ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C13]]
+    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
+    ; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC1]]
+    ; CHECK: [[C12:%[0-9]+]]:_(s16) = G_CONSTANT i16 4
+    ; CHECK: [[AND4:%[0-9]+]]:_(s16) = G_AND [[C12]], [[C7]]
+    ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
+    ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+    ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C10]]
     ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY4]](s32)
-    ; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
-    ; CHECK: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
-    ; CHECK: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[C6]](s32)
-    ; CHECK: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C12]]
-    ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C7]](s32)
-    ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C13]]
+    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
+    ; CHECK: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC2]]
+    ; CHECK: [[C13:%[0-9]+]]:_(s16) = G_CONSTANT i16 6
+    ; CHECK: [[AND6:%[0-9]+]]:_(s16) = G_AND [[C13]], [[C7]]
+    ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
+    ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+    ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C10]]
     ; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[COPY6]](s32)
-    ; CHECK: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
-    ; CHECK: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
-    ; CHECK: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[C8]](s32)
-    ; CHECK: [[AND8:%[0-9]+]]:_(s16) = G_AND [[TRUNC8]], [[C12]]
-    ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
-    ; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C13]]
-    ; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[COPY8]](s32)
-    ; CHECK: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[SHL4]](s32)
-    ; CHECK: [[OR4:%[0-9]+]]:_(s16) = G_OR [[AND8]], [[TRUNC9]]
-    ; CHECK: [[TRUNC10:%[0-9]+]]:_(s16) = G_TRUNC [[C10]](s32)
-    ; CHECK: [[AND10:%[0-9]+]]:_(s16) = G_AND [[TRUNC10]], [[C12]]
-    ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
-    ; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C13]]
-    ; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[COPY10]](s32)
-    ; CHECK: [[TRUNC11:%[0-9]+]]:_(s16) = G_TRUNC [[SHL5]](s32)
-    ; CHECK: [[OR5:%[0-9]+]]:_(s16) = G_OR [[AND10]], [[TRUNC11]]
+    ; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
+    ; CHECK: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC3]]
+    ; CHECK: [[COPY8:%[0-9]+]]:_(s16) = COPY [[C9]](s16)
+    ; CHECK: [[AND8:%[0-9]+]]:_(s16) = G_AND [[COPY8]], [[C7]]
+    ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
+    ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
+    ; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C10]]
+    ; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[COPY9]](s32)
+    ; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[SHL4]](s32)
+    ; CHECK: [[OR4:%[0-9]+]]:_(s16) = G_OR [[AND8]], [[TRUNC4]]
+    ; CHECK: [[C14:%[0-9]+]]:_(s16) = G_CONSTANT i16 10
+    ; CHECK: [[AND10:%[0-9]+]]:_(s16) = G_AND [[C14]], [[C7]]
+    ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
+    ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
+    ; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C10]]
+    ; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[COPY11]](s32)
+    ; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL5]](s32)
+    ; CHECK: [[OR5:%[0-9]+]]:_(s16) = G_OR [[AND10]], [[TRUNC5]]
     ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
     ; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
-    ; CHECK: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
-    ; CHECK: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C14]](s32)
+    ; CHECK: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+    ; CHECK: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C15]](s32)
     ; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL6]]
     ; CHECK: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)
     ; CHECK: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[OR3]](s16)
-    ; CHECK: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[ZEXT3]], [[C14]](s32)
+    ; CHECK: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[ZEXT3]], [[C15]](s32)
     ; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL7]]
     ; CHECK: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[OR4]](s16)
     ; CHECK: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[OR5]](s16)
-    ; CHECK: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[ZEXT5]], [[C14]](s32)
+    ; CHECK: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[ZEXT5]], [[C15]](s32)
     ; CHECK: [[OR8:%[0-9]+]]:_(s32) = G_OR [[ZEXT4]], [[SHL8]]
     ; CHECK: [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[OR6]](s32), [[OR7]](s32), [[OR8]](s32)
     ; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[MV]](s96)
@@ -544,48 +535,44 @@
 body: |
   bb.0:
     ; CHECK-LABEL: name: test_merge_s56_s8_s8_s8_s8_s8_s8_s8
-    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
-    ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
-    ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
-    ; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
-    ; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
     ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
-    ; CHECK: [[C7:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
-    ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
-    ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C7]]
-    ; CHECK: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
-    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
-    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
-    ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C9]]
+    ; CHECK: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+    ; CHECK: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
+    ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[C4]], [[C3]]
+    ; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
+    ; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C6]]
     ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY]](s32)
-    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
-    ; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
-    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[C2]](s32)
-    ; CHECK: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C7]]
-    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
-    ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C9]]
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
+    ; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC]]
+    ; CHECK: [[C7:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
+    ; CHECK: [[AND2:%[0-9]+]]:_(s16) = G_AND [[C7]], [[C3]]
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
+    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C6]]
     ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
-    ; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
-    ; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
-    ; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[C4]](s32)
-    ; CHECK: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C7]]
-    ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
-    ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
-    ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C9]]
+    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
+    ; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC1]]
+    ; CHECK: [[C8:%[0-9]+]]:_(s16) = G_CONSTANT i16 4
+    ; CHECK: [[AND4:%[0-9]+]]:_(s16) = G_AND [[C8]], [[C3]]
+    ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
+    ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+    ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C6]]
     ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY4]](s32)
-    ; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
-    ; CHECK: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
-    ; CHECK: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[C6]](s32)
-    ; CHECK: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C7]]
+    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
+    ; CHECK: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC2]]
+    ; CHECK: [[C9:%[0-9]+]]:_(s16) = G_CONSTANT i16 6
+    ; CHECK: [[AND6:%[0-9]+]]:_(s16) = G_AND [[C9]], [[C3]]
     ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
-    ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C9]]
-    ; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C8]](s32)
-    ; CHECK: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
-    ; CHECK: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
+    ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C6]]
+    ; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C5]](s32)
+    ; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
+    ; CHECK: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC3]]
     ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
     ; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
     ; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
@@ -596,8 +583,8 @@
     ; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[ZEXT3]], [[C10]](s32)
     ; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL5]]
     ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR4]](s32), [[OR5]](s32)
-    ; CHECK: [[TRUNC8:%[0-9]+]]:_(s56) = G_TRUNC [[MV]](s64)
-    ; CHECK: S_NOP 0, implicit [[TRUNC8]](s56)
+    ; CHECK: [[TRUNC4:%[0-9]+]]:_(s56) = G_TRUNC [[MV]](s64)
+    ; CHECK: S_NOP 0, implicit [[TRUNC4]](s56)
     %0:_(s8) = G_CONSTANT i8 0
     %1:_(s8) = G_CONSTANT i8 1
     %2:_(s8) = G_CONSTANT i8 2
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
@@ -112,11 +112,9 @@
     ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
     ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
-    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
-    ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C1]](s32)
-    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C2]](s32)
-    ; CHECK: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[TRUNC]], [[TRUNC1]]
+    ; CHECK: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
+    ; CHECK: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
+    ; CHECK: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[C1]], [[C2]]
     ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
     ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
     %0:_(s32) = G_CONSTANT i32 0
@@ -140,11 +138,9 @@
     ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
     ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
-    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
-    ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C1]](s32)
-    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C2]](s32)
-    ; CHECK: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[TRUNC]], [[TRUNC1]]
+    ; CHECK: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
+    ; CHECK: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
+    ; CHECK: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[C1]], [[C2]]
     ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
     ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
     %0:_(s32) = G_CONSTANT i32 0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir
@@ -25,11 +25,10 @@
     ; CHECK-LABEL: name: test_sext_s16_to_s64
     ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32)
-    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
-    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)
-    ; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[TRUNC]](s32)
-    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)
-    ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[TRUNC1]](s32)
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 48
+    ; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C]](s32)
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+    ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s32)
     ; CHECK: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
     %0:_(s32) = COPY $vgpr0
     %1:_(s16) = G_TRUNC %0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir
@@ -98,9 +98,8 @@
 
     ; GFX6-LABEL: name: test_sitofp_s64_to_s32
     ; GFX6: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
-    ; GFX6: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
-    ; GFX6: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)
-    ; GFX6: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[TRUNC]](s32)
+    ; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
+    ; GFX6: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[C]](s32)
     ; GFX6: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
     ; GFX6: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ASHR]](s64)
     ; GFX6: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[UV]], [[UV2]]
@@ -119,13 +118,12 @@
     ; GFX6: [[AND:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C4]]
     ; GFX6: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 1099511627775
     ; GFX6: [[AND1:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C5]]
-    ; GFX6: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 40
-    ; GFX6: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[C6]](s64)
-    ; GFX6: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[TRUNC1]](s32)
+    ; GFX6: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 40
+    ; GFX6: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[C6]](s32)
     ; GFX6: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 23
     ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SELECT]], [[C7]](s32)
-    ; GFX6: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
-    ; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[TRUNC2]]
+    ; GFX6: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
+    ; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[TRUNC]]
     ; GFX6: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 549755813888
     ; GFX6: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ugt), [[AND1]](s64), [[C8]]
     ; GFX6: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[AND1]](s64), [[C8]]
@@ -142,9 +140,8 @@
     ; GFX6: $vgpr0 = COPY [[SITOFP]](s32)
     ; GFX8-LABEL: name: test_sitofp_s64_to_s32
     ; GFX8: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
-    ; GFX8: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
-    ; GFX8: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)
-    ; GFX8: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[TRUNC]](s32)
+    ; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
+    ; GFX8: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[C]](s32)
     ; GFX8: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
     ; GFX8: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ASHR]](s64)
     ; GFX8: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[UV]], [[UV2]]
@@ -163,13 +160,12 @@
     ; GFX8: [[AND:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C4]]
     ; GFX8: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 1099511627775
     ; GFX8: [[AND1:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C5]]
-    ; GFX8: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 40
-    ; GFX8: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[C6]](s64)
-    ; GFX8: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[TRUNC1]](s32)
+    ; GFX8: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 40
+    ; GFX8: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[C6]](s32)
     ; GFX8: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 23
     ; GFX8: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SELECT]], [[C7]](s32)
-    ; GFX8: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
-    ; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[TRUNC2]]
+    ; GFX8: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
+    ; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[TRUNC]]
     ; GFX8: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 549755813888
     ; GFX8: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ugt), [[AND1]](s64), [[C8]]
     ; GFX8: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[AND1]](s64), [[C8]]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uitofp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uitofp.mir
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uitofp.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uitofp.mir
@@ -85,13 +85,12 @@
     ; GFX6: [[AND:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C3]]
     ; GFX6: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 1099511627775
     ; GFX6: [[AND1:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C4]]
-    ; GFX6: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 40
-    ; GFX6: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C5]](s64)
-    ; GFX6: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[TRUNC]](s32)
+    ; GFX6: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 40
+    ; GFX6: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[C5]](s32)
     ; GFX6: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 23
     ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SELECT]], [[C6]](s32)
-    ; GFX6: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
-    ; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[TRUNC1]]
+    ; GFX6: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
+    ; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[TRUNC]]
     ; GFX6: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 549755813888
     ; GFX6: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ugt), [[AND1]](s64), [[C7]]
     ; GFX6: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[AND1]](s64), [[C7]]
@@ -116,13 +115,12 @@
     ; GFX8: [[AND:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[C3]]
     ; GFX8: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 1099511627775
     ; GFX8: [[AND1:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C4]]
-    ; GFX8: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 40
-    ; GFX8: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C5]](s64)
-    ; GFX8: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[TRUNC]](s32)
+    ; GFX8: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 40
+    ; GFX8: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[C5]](s32)
     ; GFX8: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 23
     ; GFX8: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SELECT]], [[C6]](s32)
-    ; GFX8: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
-    ; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[TRUNC1]]
+    ; GFX8: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
+    ; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[TRUNC]]
     ; GFX8: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 549755813888
     ; GFX8: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ugt), [[AND1]](s64), [[C7]]
     ; GFX8: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[AND1]](s64), [[C7]]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir
@@ -198,17 +198,14 @@
     ; CHECK-LABEL: name: test_unmerge_s8_s32
     ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)
-    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
-    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)
-    ; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXT]], [[TRUNC]](s32)
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+    ; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ZEXT]], [[C]](s32)
     ; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[ZEXT]], [[SHL]]
-    ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
-    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[C1]](s64)
-    ; CHECK: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[OR]], [[TRUNC1]](s32)
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+    ; CHECK: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[OR]], [[C1]](s32)
     ; CHECK: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[SHL1]]
-    ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
-    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[C2]](s64)
-    ; CHECK: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[OR1]], [[TRUNC2]](s32)
+    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+    ; CHECK: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[OR1]], [[C2]](s32)
     ; CHECK: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[SHL2]]
     ; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[OR2]](s64)
     ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s16)
diff --git a/llvm/test/CodeGen/X86/GlobalISel/add-ext.ll b/llvm/test/CodeGen/X86/GlobalISel/add-ext.ll
--- a/llvm/test/CodeGen/X86/GlobalISel/add-ext.ll
+++ b/llvm/test/CodeGen/X86/GlobalISel/add-ext.ll
@@ -45,8 +45,7 @@
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addl $-5, %edi
 ; CHECK-NEXT:    movslq %edi, %rax
-; CHECK-NEXT:    movq $3, %rcx
-; CHECK-NEXT:    shlq %cl, %rax
+; CHECK-NEXT:    shlq $3, %rax
 ; CHECK-NEXT:    addq %rsi, %rax
 ; CHECK-NEXT:    retq
 
diff --git a/llvm/test/CodeGen/X86/GlobalISel/ashr-scalar.ll b/llvm/test/CodeGen/X86/GlobalISel/ashr-scalar.ll
--- a/llvm/test/CodeGen/X86/GlobalISel/ashr-scalar.ll
+++ b/llvm/test/CodeGen/X86/GlobalISel/ashr-scalar.ll
@@ -17,8 +17,7 @@
 ; X64-LABEL: test_ashr_i64_imm:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movq %rdi, %rax
-; X64-NEXT:    movq $5, %rcx
-; X64-NEXT:    sarq %cl, %rax
+; X64-NEXT:    sarq $5, %rax
 ; X64-NEXT:    retq
   %res = ashr i64 %arg1, 5
   ret i64 %res
@@ -50,8 +49,7 @@
 ; X64-LABEL: test_ashr_i32_imm:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    movl $5, %ecx
-; X64-NEXT:    sarl %cl, %eax
+; X64-NEXT:    sarl $5, %eax
 ; X64-NEXT:    retq
   %res = ashr i32 %arg1, 5
   ret i32 %res
@@ -86,8 +84,7 @@
 ; X64-LABEL: test_ashr_i16_imm:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    movw $5, %cx
-; X64-NEXT:    sarw %cl, %ax
+; X64-NEXT:    sarw $5, %ax
 ; X64-NEXT:    # kill: def $ax killed $ax killed $eax
 ; X64-NEXT:    retq
   %a = trunc i32 %arg1 to i16
diff --git a/llvm/test/CodeGen/X86/GlobalISel/ext-x86-64.ll b/llvm/test/CodeGen/X86/GlobalISel/ext-x86-64.ll
--- a/llvm/test/CodeGen/X86/GlobalISel/ext-x86-64.ll
+++ b/llvm/test/CodeGen/X86/GlobalISel/ext-x86-64.ll
@@ -18,10 +18,8 @@
 ; X64-LABEL: test_sext_i8:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    movq $56, %rcx
-; X64-NEXT:    shlq %cl, %rax
-; X64-NEXT:    movq $56, %rcx
-; X64-NEXT:    sarq %cl, %rax
+; X64-NEXT:    shlq $56, %rax
+; X64-NEXT:    sarq $56, %rax
 ; X64-NEXT:    retq
   %r = sext i8 %val to i64
   ret i64 %r
@@ -31,10 +29,8 @@
 ; X64-LABEL: test_sext_i16:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    movq $48, %rcx
-; X64-NEXT:    shlq %cl, %rax
-; X64-NEXT:    movq $48, %rcx
-; X64-NEXT:    sarq %cl, %rax
+; X64-NEXT:    shlq $48, %rax
+; X64-NEXT:    sarq $48, %rax
 ; X64-NEXT:    retq
   %r = sext i16 %val to i64
   ret i64 %r
diff --git a/llvm/test/CodeGen/X86/GlobalISel/ext.ll b/llvm/test/CodeGen/X86/GlobalISel/ext.ll
--- a/llvm/test/CodeGen/X86/GlobalISel/ext.ll
+++ b/llvm/test/CodeGen/X86/GlobalISel/ext.ll
@@ -89,10 +89,8 @@
 ; X64-LABEL: test_sext_i8:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    movl $24, %ecx
-; X64-NEXT:    shll %cl, %eax
-; X64-NEXT:    movl $24, %ecx
-; X64-NEXT:    sarl %cl, %eax
+; X64-NEXT:    shll $24, %eax
+; X64-NEXT:    sarl $24, %eax
 ; X64-NEXT:    retq
 ;
 ; X32-LABEL: test_sext_i8:
@@ -107,10 +105,8 @@
 ; X64-LABEL: test_sext_i16:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    movl $16, %ecx
-; X64-NEXT:    shll %cl, %eax
-; X64-NEXT:    movl $16, %ecx
-; X64-NEXT:    sarl %cl, %eax
+; X64-NEXT:    shll $16, %eax
+; X64-NEXT:    sarl $16, %eax
 ; X64-NEXT:    retq
 ;
 ; X32-LABEL: test_sext_i16:
diff --git a/llvm/test/CodeGen/X86/GlobalISel/gep.ll b/llvm/test/CodeGen/X86/GlobalISel/gep.ll
--- a/llvm/test/CodeGen/X86/GlobalISel/gep.ll
+++ b/llvm/test/CodeGen/X86/GlobalISel/gep.ll
@@ -6,10 +6,8 @@
 ; X64_GISEL-LABEL: test_gep_i8:
 ; X64_GISEL:       # %bb.0:
 ; X64_GISEL-NEXT:    # kill: def $esi killed $esi def $rsi
-; X64_GISEL-NEXT:    movq $56, %rcx
-; X64_GISEL-NEXT:    shlq %cl, %rsi
-; X64_GISEL-NEXT:    movq $56, %rcx
-; X64_GISEL-NEXT:    sarq %cl, %rsi
+; X64_GISEL-NEXT:    shlq $56, %rsi
+; X64_GISEL-NEXT:    sarq $56, %rsi
 ; X64_GISEL-NEXT:    movq $4, %rax
 ; X64_GISEL-NEXT:    imulq %rsi, %rax
 ; X64_GISEL-NEXT:    addq %rdi, %rax
@@ -44,10 +42,8 @@
 ; X64_GISEL-LABEL: test_gep_i16:
 ; X64_GISEL:       # %bb.0:
 ; X64_GISEL-NEXT:    # kill: def $esi killed $esi def $rsi
-; X64_GISEL-NEXT:    movq $48, %rcx
-; X64_GISEL-NEXT:    shlq %cl, %rsi
-; X64_GISEL-NEXT:    movq $48, %rcx
-; X64_GISEL-NEXT:    sarq %cl, %rsi
+; X64_GISEL-NEXT:    shlq $48, %rsi
+; X64_GISEL-NEXT:    sarq $48, %rsi
 ; X64_GISEL-NEXT:    movq $4, %rax
 ; X64_GISEL-NEXT:    imulq %rsi, %rax
 ; X64_GISEL-NEXT:    addq %rdi, %rax
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir
--- a/llvm/test/CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir
@@ -78,11 +78,10 @@
     ; CHECK-LABEL: name: test_sext_i1
     ; CHECK: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
     ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s8)
-    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
-    ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s64)
-    ; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[TRUNC]](s8)
-    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s64)
-    ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[TRUNC1]](s8)
+    ; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 63
+    ; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[C]](s8)
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s8) = COPY [[C]](s8)
+    ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[COPY1]](s8)
     ; CHECK: $rax = COPY [[ASHR]](s64)
     ; CHECK: RET 0, implicit $rax
     %0(s8) = COPY $dil
diff --git a/llvm/test/CodeGen/X86/GlobalISel/lshr-scalar.ll b/llvm/test/CodeGen/X86/GlobalISel/lshr-scalar.ll
--- a/llvm/test/CodeGen/X86/GlobalISel/lshr-scalar.ll
+++ b/llvm/test/CodeGen/X86/GlobalISel/lshr-scalar.ll
@@ -17,8 +17,7 @@
 ; X64-LABEL: test_lshr_i64_imm:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movq %rdi, %rax
-; X64-NEXT:    movq $5, %rcx
-; X64-NEXT:    shrq %cl, %rax
+; X64-NEXT:    shrq $5, %rax
 ; X64-NEXT:    retq
   %res = lshr i64 %arg1, 5
   ret i64 %res
@@ -50,8 +49,7 @@
 ; X64-LABEL: test_lshr_i32_imm:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    movl $5, %ecx
-; X64-NEXT:    shrl %cl, %eax
+; X64-NEXT:    shrl $5, %eax
 ; X64-NEXT:    retq
   %res = lshr i32 %arg1, 5
   ret i32 %res
@@ -86,8 +84,7 @@
 ; X64-LABEL: test_lshr_i16_imm:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    movw $5, %cx
-; X64-NEXT:    shrw %cl, %ax
+; X64-NEXT:    shrw $5, %ax
 ; X64-NEXT:    # kill: def $ax killed $ax killed $eax
 ; X64-NEXT:    retq
   %a = trunc i32 %arg1 to i16
diff --git a/llvm/test/CodeGen/X86/GlobalISel/shl-scalar.ll b/llvm/test/CodeGen/X86/GlobalISel/shl-scalar.ll
--- a/llvm/test/CodeGen/X86/GlobalISel/shl-scalar.ll
+++ b/llvm/test/CodeGen/X86/GlobalISel/shl-scalar.ll
@@ -17,8 +17,7 @@
 ; X64-LABEL: test_shl_i64_imm:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movq %rdi, %rax
-; X64-NEXT:    movq $5, %rcx
-; X64-NEXT:    shlq %cl, %rax
+; X64-NEXT:    shlq $5, %rax
 ; X64-NEXT:    retq
   %res = shl i64 %arg1, 5
   ret i64 %res
@@ -49,8 +48,7 @@
 ; X64-LABEL: test_shl_i32_imm:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    movl $5, %ecx
-; X64-NEXT:    shll %cl, %eax
+; X64-NEXT:    shll $5, %eax
 ; X64-NEXT:    retq
   %res = shl i32 %arg1, 5
   ret i32 %res
@@ -85,8 +83,7 @@
 ; X64-LABEL: test_shl_i16_imm:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    movw $5, %cx
-; X64-NEXT:    shlw %cl, %ax
+; X64-NEXT:    shlw $5, %ax
 ; X64-NEXT:    # kill: def $ax killed $ax killed $eax
 ; X64-NEXT:    retq
   %a = trunc i32 %arg1 to i16
diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-sitofp.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-sitofp.mir
--- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-sitofp.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-sitofp.mir
@@ -89,11 +89,10 @@
     ; CHECK: liveins: $edi
     ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
     ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
-    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
-    ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s32)
-    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[TRUNC]](s8)
-    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s32)
-    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[TRUNC1]](s8)
+    ; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 24
+    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s8)
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[C]](s8)
+    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[COPY2]](s8)
     ; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32)
     ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[SITOFP]](s32)
     ; CHECK: $xmm0 = COPY [[ANYEXT]](s128)
@@ -123,11 +122,10 @@
     ; CHECK: liveins: $edi
     ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
     ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
-    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
-    ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s32)
-    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[TRUNC]](s8)
-    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s32)
-    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[TRUNC1]](s8)
+    ; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 16
+    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s8)
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[C]](s8)
+    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[COPY2]](s8)
     ; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32)
     ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[SITOFP]](s32)
     ; CHECK: $xmm0 = COPY [[ANYEXT]](s128)
@@ -209,11 +207,10 @@
     ; CHECK: liveins: $edi
     ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
     ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
-    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
-    ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s32)
-    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[TRUNC]](s8)
-    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s32)
-    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[TRUNC1]](s8)
+    ; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 24
+    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s8)
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[C]](s8)
+    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[COPY2]](s8)
     ; CHECK: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s32)
     ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[SITOFP]](s64)
     ; CHECK: $xmm0 = COPY [[ANYEXT]](s128)
@@ -243,11 +240,10 @@
     ; CHECK: liveins: $edi
     ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
     ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
-    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
-    ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s32)
-    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[TRUNC]](s8)
-    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[C]](s32)
-    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[TRUNC1]](s8)
+    ; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 16
+    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s8)
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[C]](s8)
+    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[COPY2]](s8)
     ; CHECK: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s32)
     ; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[SITOFP]](s64)
     ; CHECK: $xmm0 = COPY [[ANYEXT]](s128)